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Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/vega10')
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h241
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h453
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h2045
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h9868
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h18193
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h64636
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_default.h3873
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_offset.h7230
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_sh_mask.h29868
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h117
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h209
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h601
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_default.h1011
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_offset.h1967
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h10127
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h342
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h375
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h1463
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h1271
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h1688
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h10281
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_default.h22340
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_offset.h3649
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h133884
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h176
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_offset.h327
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h1196
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h286
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h547
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h1852
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h282
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h539
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h1810
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h100
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_offset.h175
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h258
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h194
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_offset.h363
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_sh_mask.h1314
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h127
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_offset.h222
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h811
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_default.h122
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h208
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h488
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h1343
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/vega10_enum.h22531
47 files changed, 361003 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h
new file mode 100644
index 000000000000..1650dc369f7d
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _athub_1_0_DEFAULT_HEADER
+#define _athub_1_0_DEFAULT_HEADER
+
+
+// addressBlock: athub_atsdec
+#define mmATC_ATS_CNTL_DEFAULT 0x009a0800
+#define mmATC_ATS_STATUS_DEFAULT 0x00000000
+#define mmATC_ATS_FAULT_CNTL_DEFAULT 0x000001ff
+#define mmATC_ATS_FAULT_STATUS_INFO_DEFAULT 0x00000000
+#define mmATC_ATS_FAULT_STATUS_ADDR_DEFAULT 0x00000000
+#define mmATC_ATS_DEFAULT_PAGE_LOW_DEFAULT 0x00000000
+#define mmATC_TRANS_FAULT_RSPCNTRL_DEFAULT 0xffffffff
+#define mmATC_ATS_FAULT_STATUS_INFO2_DEFAULT 0x00000000
+#define mmATHUB_MISC_CNTL_DEFAULT 0x00040200
+#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_DEFAULT 0x00000000
+#define mmATC_VMID0_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID1_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID2_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID3_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID4_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID5_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID6_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID7_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID8_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID9_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID10_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID11_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID12_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID13_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID14_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID15_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_ATS_VMID_STATUS_DEFAULT 0x00000000
+#define mmATC_ATS_GFX_ATCL2_STATUS_DEFAULT 0x00000000
+#define mmATC_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmATC_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmATC_PERFCOUNTER2_CFG_DEFAULT 0x00000000
+#define mmATC_PERFCOUNTER3_CFG_DEFAULT 0x00000000
+#define mmATC_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+#define mmATC_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmATC_PERFCOUNTER_HI_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define mmATHUB_PCIE_PASID_CNTL_DEFAULT 0x00000000
+#define mmATHUB_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
+#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
+#define mmATHUB_COMMAND_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000
+#define mmATHUB_MEM_POWER_LS_DEFAULT 0x00000208
+#define mmATS_IH_CREDIT_DEFAULT 0x00150002
+#define mmATHUB_IH_CREDIT_DEFAULT 0x00020002
+#define mmATC_VMID16_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID17_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID18_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID19_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID20_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID21_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID22_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID23_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID24_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID25_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID26_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID27_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID28_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID29_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID30_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID31_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_ATS_MMHUB_ATCL2_STATUS_DEFAULT 0x00000000
+#define mmATHUB_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000
+#define mmATHUB_SHARED_ACTIVE_FCN_ID_DEFAULT 0x00000000
+#define mmATC_ATS_SDPPORT_CNTL_DEFAULT 0x03ffa210
+#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_DEFAULT 0x00000000
+#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_DEFAULT 0x00000000
+
+
+// addressBlock: athub_xpbdec
+#define mmXPB_RTR_SRC_APRTR0_DEFAULT 0x00000000
+#define mmXPB_RTR_SRC_APRTR1_DEFAULT 0x00000000
+#define mmXPB_RTR_SRC_APRTR2_DEFAULT 0x00000000
+#define mmXPB_RTR_SRC_APRTR3_DEFAULT 0x00000000
+#define mmXPB_RTR_SRC_APRTR4_DEFAULT 0x00000000
+#define mmXPB_RTR_SRC_APRTR5_DEFAULT 0x00000000
+#define mmXPB_RTR_SRC_APRTR6_DEFAULT 0x00000000
+#define mmXPB_RTR_SRC_APRTR7_DEFAULT 0x00000000
+#define mmXPB_RTR_SRC_APRTR8_DEFAULT 0x00000000
+#define mmXPB_RTR_SRC_APRTR9_DEFAULT 0x00000000
+#define mmXPB_XDMA_RTR_SRC_APRTR0_DEFAULT 0x00000000
+#define mmXPB_XDMA_RTR_SRC_APRTR1_DEFAULT 0x00000000
+#define mmXPB_XDMA_RTR_SRC_APRTR2_DEFAULT 0x00000000
+#define mmXPB_XDMA_RTR_SRC_APRTR3_DEFAULT 0x00000000
+#define mmXPB_RTR_DEST_MAP0_DEFAULT 0x00000000
+#define mmXPB_RTR_DEST_MAP1_DEFAULT 0x00000000
+#define mmXPB_RTR_DEST_MAP2_DEFAULT 0x00000000
+#define mmXPB_RTR_DEST_MAP3_DEFAULT 0x00000000
+#define mmXPB_RTR_DEST_MAP4_DEFAULT 0x00000000
+#define mmXPB_RTR_DEST_MAP5_DEFAULT 0x00000000
+#define mmXPB_RTR_DEST_MAP6_DEFAULT 0x00000000
+#define mmXPB_RTR_DEST_MAP7_DEFAULT 0x00000000
+#define mmXPB_RTR_DEST_MAP8_DEFAULT 0x00000000
+#define mmXPB_RTR_DEST_MAP9_DEFAULT 0x00000000
+#define mmXPB_XDMA_RTR_DEST_MAP0_DEFAULT 0x00000000
+#define mmXPB_XDMA_RTR_DEST_MAP1_DEFAULT 0x00000000
+#define mmXPB_XDMA_RTR_DEST_MAP2_DEFAULT 0x00000000
+#define mmXPB_XDMA_RTR_DEST_MAP3_DEFAULT 0x00000000
+#define mmXPB_CLG_CFG0_DEFAULT 0x00000000
+#define mmXPB_CLG_CFG1_DEFAULT 0x00000000
+#define mmXPB_CLG_CFG2_DEFAULT 0x00000000
+#define mmXPB_CLG_CFG3_DEFAULT 0x00000000
+#define mmXPB_CLG_CFG4_DEFAULT 0x00000000
+#define mmXPB_CLG_CFG5_DEFAULT 0x00000000
+#define mmXPB_CLG_CFG6_DEFAULT 0x00000000
+#define mmXPB_CLG_CFG7_DEFAULT 0x00000000
+#define mmXPB_CLG_EXTRA_DEFAULT 0x00000000
+#define mmXPB_CLG_EXTRA_MSK_DEFAULT 0x00000000
+#define mmXPB_LB_ADDR_DEFAULT 0x00000000
+#define mmXPB_WCB_STS_DEFAULT 0x00000000
+#define mmXPB_HST_CFG_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR_CFG_DEFAULT 0x0000000f
+#define mmXPB_P2P_BAR0_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR1_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR2_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR3_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR4_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR5_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR6_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR7_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR_SETUP_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR_DELTA_ABOVE_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR_DELTA_BELOW_DEFAULT 0x00000000
+#define mmXPB_PEER_SYS_BAR0_DEFAULT 0x00000000
+#define mmXPB_PEER_SYS_BAR1_DEFAULT 0x00000000
+#define mmXPB_PEER_SYS_BAR2_DEFAULT 0x00000000
+#define mmXPB_PEER_SYS_BAR3_DEFAULT 0x00000000
+#define mmXPB_PEER_SYS_BAR4_DEFAULT 0x00000000
+#define mmXPB_PEER_SYS_BAR5_DEFAULT 0x00000000
+#define mmXPB_PEER_SYS_BAR6_DEFAULT 0x00000000
+#define mmXPB_PEER_SYS_BAR7_DEFAULT 0x00000000
+#define mmXPB_PEER_SYS_BAR8_DEFAULT 0x00000000
+#define mmXPB_PEER_SYS_BAR9_DEFAULT 0x00000000
+#define mmXPB_XDMA_PEER_SYS_BAR0_DEFAULT 0x00000000
+#define mmXPB_XDMA_PEER_SYS_BAR1_DEFAULT 0x00000000
+#define mmXPB_XDMA_PEER_SYS_BAR2_DEFAULT 0x00000000
+#define mmXPB_XDMA_PEER_SYS_BAR3_DEFAULT 0x00000000
+#define mmXPB_CLK_GAT_DEFAULT 0x00040400
+#define mmXPB_INTF_CFG_DEFAULT 0x000f1040
+#define mmXPB_INTF_STS_DEFAULT 0x00000000
+#define mmXPB_PIPE_STS_DEFAULT 0x00000000
+#define mmXPB_SUB_CTRL_DEFAULT 0x00000000
+#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_DEFAULT 0x00000000
+#define mmXPB_PERF_KNOBS_DEFAULT 0x00000000
+#define mmXPB_STICKY_DEFAULT 0x00000000
+#define mmXPB_STICKY_W1C_DEFAULT 0x00000000
+#define mmXPB_MISC_CFG_DEFAULT 0x4d585042
+#define mmXPB_INTF_CFG2_DEFAULT 0x00000040
+#define mmXPB_CLG_EXTRA_RD_DEFAULT 0x00000000
+#define mmXPB_CLG_EXTRA_MSK_RD_DEFAULT 0x00000000
+#define mmXPB_CLG_GFX_MATCH_DEFAULT 0x03000000
+#define mmXPB_CLG_GFX_MATCH_MSK_DEFAULT 0x00000000
+#define mmXPB_CLG_MM_MATCH_DEFAULT 0x03000000
+#define mmXPB_CLG_MM_MATCH_MSK_DEFAULT 0x00000000
+#define mmXPB_CLG_GFX_UNITID_MAPPING0_DEFAULT 0x00000000
+#define mmXPB_CLG_GFX_UNITID_MAPPING1_DEFAULT 0x00000040
+#define mmXPB_CLG_GFX_UNITID_MAPPING2_DEFAULT 0x00000080
+#define mmXPB_CLG_GFX_UNITID_MAPPING3_DEFAULT 0x000000c0
+#define mmXPB_CLG_GFX_UNITID_MAPPING4_DEFAULT 0x00000100
+#define mmXPB_CLG_GFX_UNITID_MAPPING5_DEFAULT 0x00000140
+#define mmXPB_CLG_GFX_UNITID_MAPPING6_DEFAULT 0x00000000
+#define mmXPB_CLG_GFX_UNITID_MAPPING7_DEFAULT 0x000001c0
+#define mmXPB_CLG_MM_UNITID_MAPPING0_DEFAULT 0x00000000
+#define mmXPB_CLG_MM_UNITID_MAPPING1_DEFAULT 0x00000040
+#define mmXPB_CLG_MM_UNITID_MAPPING2_DEFAULT 0x00000080
+#define mmXPB_CLG_MM_UNITID_MAPPING3_DEFAULT 0x000000c0
+
+
+// addressBlock: athub_rpbdec
+#define mmRPB_PASSPW_CONF_DEFAULT 0x00000230
+#define mmRPB_BLOCKLEVEL_CONF_DEFAULT 0x000000f0
+#define mmRPB_TAG_CONF_DEFAULT 0x00204020
+#define mmRPB_EFF_CNTL_DEFAULT 0x00001010
+#define mmRPB_ARB_CNTL_DEFAULT 0x00040404
+#define mmRPB_ARB_CNTL2_DEFAULT 0x00040104
+#define mmRPB_BIF_CNTL_DEFAULT 0x01000404
+#define mmRPB_WR_SWITCH_CNTL_DEFAULT 0x02040810
+#define mmRPB_RD_SWITCH_CNTL_DEFAULT 0x02040810
+#define mmRPB_CID_QUEUE_WR_DEFAULT 0x00000000
+#define mmRPB_CID_QUEUE_RD_DEFAULT 0x00000000
+#define mmRPB_CID_QUEUE_EX_DEFAULT 0x00000000
+#define mmRPB_CID_QUEUE_EX_DATA_DEFAULT 0x00000000
+#define mmRPB_SWITCH_CNTL2_DEFAULT 0x02040810
+#define mmRPB_DEINTRLV_COMBINE_CNTL_DEFAULT 0x00000004
+#define mmRPB_VC_SWITCH_RDWR_DEFAULT 0x00004040
+#define mmRPB_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmRPB_PERFCOUNTER_HI_DEFAULT 0x00000000
+#define mmRPB_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmRPB_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmRPB_PERFCOUNTER2_CFG_DEFAULT 0x00000000
+#define mmRPB_PERFCOUNTER3_CFG_DEFAULT 0x00000000
+#define mmRPB_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+#define mmRPB_RD_QUEUE_CNTL_DEFAULT 0x00000000
+#define mmRPB_RD_QUEUE_CNTL2_DEFAULT 0x00000000
+#define mmRPB_WR_QUEUE_CNTL_DEFAULT 0x00000000
+#define mmRPB_WR_QUEUE_CNTL2_DEFAULT 0x00000000
+#define mmRPB_EA_QUEUE_WR_DEFAULT 0x00000000
+#define mmRPB_ATS_CNTL_DEFAULT 0x58088422
+#define mmRPB_ATS_CNTL2_DEFAULT 0x00050b13
+#define mmRPB_SDPPORT_CNTL_DEFAULT 0x0fd14814
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h
new file mode 100644
index 000000000000..80042e1c8770
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h
@@ -0,0 +1,453 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _athub_1_0_OFFSET_HEADER
+#define _athub_1_0_OFFSET_HEADER
+
+
+
+// addressBlock: athub_atsdec
+// base address: 0x3080
+#define mmATC_ATS_CNTL 0x0000
+#define mmATC_ATS_CNTL_BASE_IDX 0
+#define mmATC_ATS_STATUS 0x0003
+#define mmATC_ATS_STATUS_BASE_IDX 0
+#define mmATC_ATS_FAULT_CNTL 0x0004
+#define mmATC_ATS_FAULT_CNTL_BASE_IDX 0
+#define mmATC_ATS_FAULT_STATUS_INFO 0x0005
+#define mmATC_ATS_FAULT_STATUS_INFO_BASE_IDX 0
+#define mmATC_ATS_FAULT_STATUS_ADDR 0x0006
+#define mmATC_ATS_FAULT_STATUS_ADDR_BASE_IDX 0
+#define mmATC_ATS_DEFAULT_PAGE_LOW 0x0007
+#define mmATC_ATS_DEFAULT_PAGE_LOW_BASE_IDX 0
+#define mmATC_TRANS_FAULT_RSPCNTRL 0x0008
+#define mmATC_TRANS_FAULT_RSPCNTRL_BASE_IDX 0
+#define mmATC_ATS_FAULT_STATUS_INFO2 0x0009
+#define mmATC_ATS_FAULT_STATUS_INFO2_BASE_IDX 0
+#define mmATHUB_MISC_CNTL 0x000a
+#define mmATHUB_MISC_CNTL_BASE_IDX 0
+#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x000b
+#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_BASE_IDX 0
+#define mmATC_VMID0_PASID_MAPPING 0x000c
+#define mmATC_VMID0_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID1_PASID_MAPPING 0x000d
+#define mmATC_VMID1_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID2_PASID_MAPPING 0x000e
+#define mmATC_VMID2_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID3_PASID_MAPPING 0x000f
+#define mmATC_VMID3_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID4_PASID_MAPPING 0x0010
+#define mmATC_VMID4_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID5_PASID_MAPPING 0x0011
+#define mmATC_VMID5_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID6_PASID_MAPPING 0x0012
+#define mmATC_VMID6_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID7_PASID_MAPPING 0x0013
+#define mmATC_VMID7_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID8_PASID_MAPPING 0x0014
+#define mmATC_VMID8_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID9_PASID_MAPPING 0x0015
+#define mmATC_VMID9_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID10_PASID_MAPPING 0x0016
+#define mmATC_VMID10_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID11_PASID_MAPPING 0x0017
+#define mmATC_VMID11_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID12_PASID_MAPPING 0x0018
+#define mmATC_VMID12_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID13_PASID_MAPPING 0x0019
+#define mmATC_VMID13_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID14_PASID_MAPPING 0x001a
+#define mmATC_VMID14_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID15_PASID_MAPPING 0x001b
+#define mmATC_VMID15_PASID_MAPPING_BASE_IDX 0
+#define mmATC_ATS_VMID_STATUS 0x001c
+#define mmATC_ATS_VMID_STATUS_BASE_IDX 0
+#define mmATC_ATS_GFX_ATCL2_STATUS 0x001d
+#define mmATC_ATS_GFX_ATCL2_STATUS_BASE_IDX 0
+#define mmATC_PERFCOUNTER0_CFG 0x001e
+#define mmATC_PERFCOUNTER0_CFG_BASE_IDX 0
+#define mmATC_PERFCOUNTER1_CFG 0x001f
+#define mmATC_PERFCOUNTER1_CFG_BASE_IDX 0
+#define mmATC_PERFCOUNTER2_CFG 0x0020
+#define mmATC_PERFCOUNTER2_CFG_BASE_IDX 0
+#define mmATC_PERFCOUNTER3_CFG 0x0021
+#define mmATC_PERFCOUNTER3_CFG_BASE_IDX 0
+#define mmATC_PERFCOUNTER_RSLT_CNTL 0x0022
+#define mmATC_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define mmATC_PERFCOUNTER_LO 0x0023
+#define mmATC_PERFCOUNTER_LO_BASE_IDX 0
+#define mmATC_PERFCOUNTER_HI 0x0024
+#define mmATC_PERFCOUNTER_HI_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL 0x0025
+#define mmATHUB_PCIE_ATS_CNTL_BASE_IDX 0
+#define mmATHUB_PCIE_PASID_CNTL 0x0026
+#define mmATHUB_PCIE_PASID_CNTL_BASE_IDX 0
+#define mmATHUB_PCIE_PAGE_REQ_CNTL 0x0027
+#define mmATHUB_PCIE_PAGE_REQ_CNTL_BASE_IDX 0
+#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x0028
+#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 0
+#define mmATHUB_COMMAND 0x0029
+#define mmATHUB_COMMAND_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_0 0x002a
+#define mmATHUB_PCIE_ATS_CNTL_VF_0_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_1 0x002b
+#define mmATHUB_PCIE_ATS_CNTL_VF_1_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_2 0x002c
+#define mmATHUB_PCIE_ATS_CNTL_VF_2_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_3 0x002d
+#define mmATHUB_PCIE_ATS_CNTL_VF_3_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_4 0x002e
+#define mmATHUB_PCIE_ATS_CNTL_VF_4_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_5 0x002f
+#define mmATHUB_PCIE_ATS_CNTL_VF_5_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_6 0x0030
+#define mmATHUB_PCIE_ATS_CNTL_VF_6_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_7 0x0031
+#define mmATHUB_PCIE_ATS_CNTL_VF_7_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_8 0x0032
+#define mmATHUB_PCIE_ATS_CNTL_VF_8_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_9 0x0033
+#define mmATHUB_PCIE_ATS_CNTL_VF_9_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_10 0x0034
+#define mmATHUB_PCIE_ATS_CNTL_VF_10_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_11 0x0035
+#define mmATHUB_PCIE_ATS_CNTL_VF_11_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_12 0x0036
+#define mmATHUB_PCIE_ATS_CNTL_VF_12_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_13 0x0037
+#define mmATHUB_PCIE_ATS_CNTL_VF_13_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_14 0x0038
+#define mmATHUB_PCIE_ATS_CNTL_VF_14_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_15 0x0039
+#define mmATHUB_PCIE_ATS_CNTL_VF_15_BASE_IDX 0
+#define mmATHUB_MEM_POWER_LS 0x003a
+#define mmATHUB_MEM_POWER_LS_BASE_IDX 0
+#define mmATS_IH_CREDIT 0x003b
+#define mmATS_IH_CREDIT_BASE_IDX 0
+#define mmATHUB_IH_CREDIT 0x003c
+#define mmATHUB_IH_CREDIT_BASE_IDX 0
+#define mmATC_VMID16_PASID_MAPPING 0x003d
+#define mmATC_VMID16_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID17_PASID_MAPPING 0x003e
+#define mmATC_VMID17_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID18_PASID_MAPPING 0x003f
+#define mmATC_VMID18_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID19_PASID_MAPPING 0x0040
+#define mmATC_VMID19_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID20_PASID_MAPPING 0x0041
+#define mmATC_VMID20_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID21_PASID_MAPPING 0x0042
+#define mmATC_VMID21_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID22_PASID_MAPPING 0x0043
+#define mmATC_VMID22_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID23_PASID_MAPPING 0x0044
+#define mmATC_VMID23_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID24_PASID_MAPPING 0x0045
+#define mmATC_VMID24_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID25_PASID_MAPPING 0x0046
+#define mmATC_VMID25_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID26_PASID_MAPPING 0x0047
+#define mmATC_VMID26_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID27_PASID_MAPPING 0x0048
+#define mmATC_VMID27_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID28_PASID_MAPPING 0x0049
+#define mmATC_VMID28_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID29_PASID_MAPPING 0x004a
+#define mmATC_VMID29_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID30_PASID_MAPPING 0x004b
+#define mmATC_VMID30_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID31_PASID_MAPPING 0x004c
+#define mmATC_VMID31_PASID_MAPPING_BASE_IDX 0
+#define mmATC_ATS_MMHUB_ATCL2_STATUS 0x004d
+#define mmATC_ATS_MMHUB_ATCL2_STATUS_BASE_IDX 0
+#define mmATHUB_SHARED_VIRT_RESET_REQ 0x004e
+#define mmATHUB_SHARED_VIRT_RESET_REQ_BASE_IDX 0
+#define mmATHUB_SHARED_ACTIVE_FCN_ID 0x004f
+#define mmATHUB_SHARED_ACTIVE_FCN_ID_BASE_IDX 0
+#define mmATC_ATS_SDPPORT_CNTL 0x0050
+#define mmATC_ATS_SDPPORT_CNTL_BASE_IDX 0
+#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT 0x0052
+#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_BASE_IDX 0
+#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT 0x0053
+#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_BASE_IDX 0
+
+
+// addressBlock: athub_xpbdec
+// base address: 0x31f0
+#define mmXPB_RTR_SRC_APRTR0 0x005c
+#define mmXPB_RTR_SRC_APRTR0_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR1 0x005d
+#define mmXPB_RTR_SRC_APRTR1_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR2 0x005e
+#define mmXPB_RTR_SRC_APRTR2_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR3 0x005f
+#define mmXPB_RTR_SRC_APRTR3_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR4 0x0060
+#define mmXPB_RTR_SRC_APRTR4_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR5 0x0061
+#define mmXPB_RTR_SRC_APRTR5_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR6 0x0062
+#define mmXPB_RTR_SRC_APRTR6_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR7 0x0063
+#define mmXPB_RTR_SRC_APRTR7_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR8 0x0064
+#define mmXPB_RTR_SRC_APRTR8_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR9 0x0065
+#define mmXPB_RTR_SRC_APRTR9_BASE_IDX 0
+#define mmXPB_XDMA_RTR_SRC_APRTR0 0x0066
+#define mmXPB_XDMA_RTR_SRC_APRTR0_BASE_IDX 0
+#define mmXPB_XDMA_RTR_SRC_APRTR1 0x0067
+#define mmXPB_XDMA_RTR_SRC_APRTR1_BASE_IDX 0
+#define mmXPB_XDMA_RTR_SRC_APRTR2 0x0068
+#define mmXPB_XDMA_RTR_SRC_APRTR2_BASE_IDX 0
+#define mmXPB_XDMA_RTR_SRC_APRTR3 0x0069
+#define mmXPB_XDMA_RTR_SRC_APRTR3_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP0 0x006a
+#define mmXPB_RTR_DEST_MAP0_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP1 0x006b
+#define mmXPB_RTR_DEST_MAP1_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP2 0x006c
+#define mmXPB_RTR_DEST_MAP2_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP3 0x006d
+#define mmXPB_RTR_DEST_MAP3_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP4 0x006e
+#define mmXPB_RTR_DEST_MAP4_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP5 0x006f
+#define mmXPB_RTR_DEST_MAP5_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP6 0x0070
+#define mmXPB_RTR_DEST_MAP6_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP7 0x0071
+#define mmXPB_RTR_DEST_MAP7_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP8 0x0072
+#define mmXPB_RTR_DEST_MAP8_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP9 0x0073
+#define mmXPB_RTR_DEST_MAP9_BASE_IDX 0
+#define mmXPB_XDMA_RTR_DEST_MAP0 0x0074
+#define mmXPB_XDMA_RTR_DEST_MAP0_BASE_IDX 0
+#define mmXPB_XDMA_RTR_DEST_MAP1 0x0075
+#define mmXPB_XDMA_RTR_DEST_MAP1_BASE_IDX 0
+#define mmXPB_XDMA_RTR_DEST_MAP2 0x0076
+#define mmXPB_XDMA_RTR_DEST_MAP2_BASE_IDX 0
+#define mmXPB_XDMA_RTR_DEST_MAP3 0x0077
+#define mmXPB_XDMA_RTR_DEST_MAP3_BASE_IDX 0
+#define mmXPB_CLG_CFG0 0x0078
+#define mmXPB_CLG_CFG0_BASE_IDX 0
+#define mmXPB_CLG_CFG1 0x0079
+#define mmXPB_CLG_CFG1_BASE_IDX 0
+#define mmXPB_CLG_CFG2 0x007a
+#define mmXPB_CLG_CFG2_BASE_IDX 0
+#define mmXPB_CLG_CFG3 0x007b
+#define mmXPB_CLG_CFG3_BASE_IDX 0
+#define mmXPB_CLG_CFG4 0x007c
+#define mmXPB_CLG_CFG4_BASE_IDX 0
+#define mmXPB_CLG_CFG5 0x007d
+#define mmXPB_CLG_CFG5_BASE_IDX 0
+#define mmXPB_CLG_CFG6 0x007e
+#define mmXPB_CLG_CFG6_BASE_IDX 0
+#define mmXPB_CLG_CFG7 0x007f
+#define mmXPB_CLG_CFG7_BASE_IDX 0
+#define mmXPB_CLG_EXTRA 0x0080
+#define mmXPB_CLG_EXTRA_BASE_IDX 0
+#define mmXPB_CLG_EXTRA_MSK 0x0081
+#define mmXPB_CLG_EXTRA_MSK_BASE_IDX 0
+#define mmXPB_LB_ADDR 0x0082
+#define mmXPB_LB_ADDR_BASE_IDX 0
+#define mmXPB_WCB_STS 0x0083
+#define mmXPB_WCB_STS_BASE_IDX 0
+#define mmXPB_HST_CFG 0x0084
+#define mmXPB_HST_CFG_BASE_IDX 0
+#define mmXPB_P2P_BAR_CFG 0x0085
+#define mmXPB_P2P_BAR_CFG_BASE_IDX 0
+#define mmXPB_P2P_BAR0 0x0086
+#define mmXPB_P2P_BAR0_BASE_IDX 0
+#define mmXPB_P2P_BAR1 0x0087
+#define mmXPB_P2P_BAR1_BASE_IDX 0
+#define mmXPB_P2P_BAR2 0x0088
+#define mmXPB_P2P_BAR2_BASE_IDX 0
+#define mmXPB_P2P_BAR3 0x0089
+#define mmXPB_P2P_BAR3_BASE_IDX 0
+#define mmXPB_P2P_BAR4 0x008a
+#define mmXPB_P2P_BAR4_BASE_IDX 0
+#define mmXPB_P2P_BAR5 0x008b
+#define mmXPB_P2P_BAR5_BASE_IDX 0
+#define mmXPB_P2P_BAR6 0x008c
+#define mmXPB_P2P_BAR6_BASE_IDX 0
+#define mmXPB_P2P_BAR7 0x008d
+#define mmXPB_P2P_BAR7_BASE_IDX 0
+#define mmXPB_P2P_BAR_SETUP 0x008e
+#define mmXPB_P2P_BAR_SETUP_BASE_IDX 0
+#define mmXPB_P2P_BAR_DELTA_ABOVE 0x0090
+#define mmXPB_P2P_BAR_DELTA_ABOVE_BASE_IDX 0
+#define mmXPB_P2P_BAR_DELTA_BELOW 0x0091
+#define mmXPB_P2P_BAR_DELTA_BELOW_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR0 0x0092
+#define mmXPB_PEER_SYS_BAR0_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR1 0x0093
+#define mmXPB_PEER_SYS_BAR1_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR2 0x0094
+#define mmXPB_PEER_SYS_BAR2_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR3 0x0095
+#define mmXPB_PEER_SYS_BAR3_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR4 0x0096
+#define mmXPB_PEER_SYS_BAR4_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR5 0x0097
+#define mmXPB_PEER_SYS_BAR5_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR6 0x0098
+#define mmXPB_PEER_SYS_BAR6_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR7 0x0099
+#define mmXPB_PEER_SYS_BAR7_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR8 0x009a
+#define mmXPB_PEER_SYS_BAR8_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR9 0x009b
+#define mmXPB_PEER_SYS_BAR9_BASE_IDX 0
+#define mmXPB_XDMA_PEER_SYS_BAR0 0x009c
+#define mmXPB_XDMA_PEER_SYS_BAR0_BASE_IDX 0
+#define mmXPB_XDMA_PEER_SYS_BAR1 0x009d
+#define mmXPB_XDMA_PEER_SYS_BAR1_BASE_IDX 0
+#define mmXPB_XDMA_PEER_SYS_BAR2 0x009e
+#define mmXPB_XDMA_PEER_SYS_BAR2_BASE_IDX 0
+#define mmXPB_XDMA_PEER_SYS_BAR3 0x009f
+#define mmXPB_XDMA_PEER_SYS_BAR3_BASE_IDX 0
+#define mmXPB_CLK_GAT 0x00a0
+#define mmXPB_CLK_GAT_BASE_IDX 0
+#define mmXPB_INTF_CFG 0x00a1
+#define mmXPB_INTF_CFG_BASE_IDX 0
+#define mmXPB_INTF_STS 0x00a2
+#define mmXPB_INTF_STS_BASE_IDX 0
+#define mmXPB_PIPE_STS 0x00a3
+#define mmXPB_PIPE_STS_BASE_IDX 0
+#define mmXPB_SUB_CTRL 0x00a4
+#define mmXPB_SUB_CTRL_BASE_IDX 0
+#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB 0x00a5
+#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_BASE_IDX 0
+#define mmXPB_PERF_KNOBS 0x00a6
+#define mmXPB_PERF_KNOBS_BASE_IDX 0
+#define mmXPB_STICKY 0x00a7
+#define mmXPB_STICKY_BASE_IDX 0
+#define mmXPB_STICKY_W1C 0x00a8
+#define mmXPB_STICKY_W1C_BASE_IDX 0
+#define mmXPB_MISC_CFG 0x00a9
+#define mmXPB_MISC_CFG_BASE_IDX 0
+#define mmXPB_INTF_CFG2 0x00aa
+#define mmXPB_INTF_CFG2_BASE_IDX 0
+#define mmXPB_CLG_EXTRA_RD 0x00ab
+#define mmXPB_CLG_EXTRA_RD_BASE_IDX 0
+#define mmXPB_CLG_EXTRA_MSK_RD 0x00ac
+#define mmXPB_CLG_EXTRA_MSK_RD_BASE_IDX 0
+#define mmXPB_CLG_GFX_MATCH 0x00ad
+#define mmXPB_CLG_GFX_MATCH_BASE_IDX 0
+#define mmXPB_CLG_GFX_MATCH_MSK 0x00ae
+#define mmXPB_CLG_GFX_MATCH_MSK_BASE_IDX 0
+#define mmXPB_CLG_MM_MATCH 0x00af
+#define mmXPB_CLG_MM_MATCH_BASE_IDX 0
+#define mmXPB_CLG_MM_MATCH_MSK 0x00b0
+#define mmXPB_CLG_MM_MATCH_MSK_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING0 0x00b1
+#define mmXPB_CLG_GFX_UNITID_MAPPING0_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING1 0x00b2
+#define mmXPB_CLG_GFX_UNITID_MAPPING1_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING2 0x00b3
+#define mmXPB_CLG_GFX_UNITID_MAPPING2_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING3 0x00b4
+#define mmXPB_CLG_GFX_UNITID_MAPPING3_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING4 0x00b5
+#define mmXPB_CLG_GFX_UNITID_MAPPING4_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING5 0x00b6
+#define mmXPB_CLG_GFX_UNITID_MAPPING5_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING6 0x00b7
+#define mmXPB_CLG_GFX_UNITID_MAPPING6_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING7 0x00b8
+#define mmXPB_CLG_GFX_UNITID_MAPPING7_BASE_IDX 0
+#define mmXPB_CLG_MM_UNITID_MAPPING0 0x00b9
+#define mmXPB_CLG_MM_UNITID_MAPPING0_BASE_IDX 0
+#define mmXPB_CLG_MM_UNITID_MAPPING1 0x00ba
+#define mmXPB_CLG_MM_UNITID_MAPPING1_BASE_IDX 0
+#define mmXPB_CLG_MM_UNITID_MAPPING2 0x00bb
+#define mmXPB_CLG_MM_UNITID_MAPPING2_BASE_IDX 0
+#define mmXPB_CLG_MM_UNITID_MAPPING3 0x00bc
+#define mmXPB_CLG_MM_UNITID_MAPPING3_BASE_IDX 0
+
+
+// addressBlock: athub_rpbdec
+// base address: 0x33b0
+#define mmRPB_PASSPW_CONF 0x00cc
+#define mmRPB_PASSPW_CONF_BASE_IDX 0
+#define mmRPB_BLOCKLEVEL_CONF 0x00cd
+#define mmRPB_BLOCKLEVEL_CONF_BASE_IDX 0
+#define mmRPB_TAG_CONF 0x00cf
+#define mmRPB_TAG_CONF_BASE_IDX 0
+#define mmRPB_EFF_CNTL 0x00d1
+#define mmRPB_EFF_CNTL_BASE_IDX 0
+#define mmRPB_ARB_CNTL 0x00d2
+#define mmRPB_ARB_CNTL_BASE_IDX 0
+#define mmRPB_ARB_CNTL2 0x00d3
+#define mmRPB_ARB_CNTL2_BASE_IDX 0
+#define mmRPB_BIF_CNTL 0x00d4
+#define mmRPB_BIF_CNTL_BASE_IDX 0
+#define mmRPB_WR_SWITCH_CNTL 0x00d5
+#define mmRPB_WR_SWITCH_CNTL_BASE_IDX 0
+#define mmRPB_RD_SWITCH_CNTL 0x00d7
+#define mmRPB_RD_SWITCH_CNTL_BASE_IDX 0
+#define mmRPB_CID_QUEUE_WR 0x00d8
+#define mmRPB_CID_QUEUE_WR_BASE_IDX 0
+#define mmRPB_CID_QUEUE_RD 0x00d9
+#define mmRPB_CID_QUEUE_RD_BASE_IDX 0
+#define mmRPB_CID_QUEUE_EX 0x00dc
+#define mmRPB_CID_QUEUE_EX_BASE_IDX 0
+#define mmRPB_CID_QUEUE_EX_DATA 0x00dd
+#define mmRPB_CID_QUEUE_EX_DATA_BASE_IDX 0
+#define mmRPB_SWITCH_CNTL2 0x00de
+#define mmRPB_SWITCH_CNTL2_BASE_IDX 0
+#define mmRPB_DEINTRLV_COMBINE_CNTL 0x00df
+#define mmRPB_DEINTRLV_COMBINE_CNTL_BASE_IDX 0
+#define mmRPB_VC_SWITCH_RDWR 0x00e0
+#define mmRPB_VC_SWITCH_RDWR_BASE_IDX 0
+#define mmRPB_PERFCOUNTER_LO 0x00e1
+#define mmRPB_PERFCOUNTER_LO_BASE_IDX 0
+#define mmRPB_PERFCOUNTER_HI 0x00e2
+#define mmRPB_PERFCOUNTER_HI_BASE_IDX 0
+#define mmRPB_PERFCOUNTER0_CFG 0x00e3
+#define mmRPB_PERFCOUNTER0_CFG_BASE_IDX 0
+#define mmRPB_PERFCOUNTER1_CFG 0x00e4
+#define mmRPB_PERFCOUNTER1_CFG_BASE_IDX 0
+#define mmRPB_PERFCOUNTER2_CFG 0x00e5
+#define mmRPB_PERFCOUNTER2_CFG_BASE_IDX 0
+#define mmRPB_PERFCOUNTER3_CFG 0x00e6
+#define mmRPB_PERFCOUNTER3_CFG_BASE_IDX 0
+#define mmRPB_PERFCOUNTER_RSLT_CNTL 0x00e7
+#define mmRPB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define mmRPB_RD_QUEUE_CNTL 0x00e9
+#define mmRPB_RD_QUEUE_CNTL_BASE_IDX 0
+#define mmRPB_RD_QUEUE_CNTL2 0x00ea
+#define mmRPB_RD_QUEUE_CNTL2_BASE_IDX 0
+#define mmRPB_WR_QUEUE_CNTL 0x00eb
+#define mmRPB_WR_QUEUE_CNTL_BASE_IDX 0
+#define mmRPB_WR_QUEUE_CNTL2 0x00ec
+#define mmRPB_WR_QUEUE_CNTL2_BASE_IDX 0
+#define mmRPB_EA_QUEUE_WR 0x00ed
+#define mmRPB_EA_QUEUE_WR_BASE_IDX 0
+#define mmRPB_ATS_CNTL 0x00ee
+#define mmRPB_ATS_CNTL_BASE_IDX 0
+#define mmRPB_ATS_CNTL2 0x00ef
+#define mmRPB_ATS_CNTL2_BASE_IDX 0
+#define mmRPB_SDPPORT_CNTL 0x00f0
+#define mmRPB_SDPPORT_CNTL_BASE_IDX 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h
new file mode 100644
index 000000000000..777b05c89708
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h
@@ -0,0 +1,2045 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _athub_1_0_SH_MASK_HEADER
+#define _athub_1_0_SH_MASK_HEADER
+
+
+// addressBlock: athub_atsdec
+//ATC_ATS_CNTL
+#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
+#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
+#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
+#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
+#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14
+#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15
+#define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16
+#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
+#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
+#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
+#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003F00L
+#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER_MASK 0x00100000L
+#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER_MASK 0x00200000L
+#define ATC_ATS_CNTL__TRANS_EXE_RETURN_MASK 0x00C00000L
+//ATC_ATS_STATUS
+#define ATC_ATS_STATUS__BUSY__SHIFT 0x0
+#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1
+#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2
+#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x3
+#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x6
+#define ATC_ATS_STATUS__BUSY_MASK 0x00000001L
+#define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L
+#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L
+#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING_MASK 0x00000038L
+#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING_MASK 0x000001C0L
+//ATC_ATS_FAULT_CNTL
+#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0
+#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa
+#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14
+#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x000001FFL
+#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0007FC00L
+#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1FF00000L
+//ATC_ATS_FAULT_STATUS_INFO
+#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0
+#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10
+#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12
+#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18
+#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x000001FFL
+#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007C00L
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L
+#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L
+#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00F80000L
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0F000000L
+//ATC_ATS_FAULT_STATUS_ADDR
+#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0
+#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xFFFFFFFFL
+//ATC_ATS_DEFAULT_PAGE_LOW
+#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0
+#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xFFFFFFFFL
+//ATC_TRANS_FAULT_RSPCNTRL
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID0__SHIFT 0x0
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID1__SHIFT 0x1
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID2__SHIFT 0x2
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID3__SHIFT 0x3
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID4__SHIFT 0x4
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID5__SHIFT 0x5
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID6__SHIFT 0x6
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID7__SHIFT 0x7
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID8__SHIFT 0x8
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID9__SHIFT 0x9
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID11__SHIFT 0xb
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID12__SHIFT 0xc
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID13__SHIFT 0xd
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID14__SHIFT 0xe
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID15__SHIFT 0xf
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID16__SHIFT 0x10
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID17__SHIFT 0x11
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID18__SHIFT 0x12
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID19__SHIFT 0x13
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID20__SHIFT 0x14
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID21__SHIFT 0x15
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID22__SHIFT 0x16
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID23__SHIFT 0x17
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID24__SHIFT 0x18
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID25__SHIFT 0x19
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID26__SHIFT 0x1a
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID27__SHIFT 0x1b
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID28__SHIFT 0x1c
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID29__SHIFT 0x1d
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID30__SHIFT 0x1e
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID31__SHIFT 0x1f
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID0_MASK 0x00000001L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID1_MASK 0x00000002L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID2_MASK 0x00000004L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID3_MASK 0x00000008L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID4_MASK 0x00000010L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID5_MASK 0x00000020L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID6_MASK 0x00000040L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID7_MASK 0x00000080L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID8_MASK 0x00000100L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID9_MASK 0x00000200L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID10_MASK 0x00000400L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID11_MASK 0x00000800L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID12_MASK 0x00001000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID13_MASK 0x00002000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID14_MASK 0x00004000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID15_MASK 0x00008000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID16_MASK 0x00010000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID17_MASK 0x00020000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID18_MASK 0x00040000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID19_MASK 0x00080000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID20_MASK 0x00100000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID21_MASK 0x00200000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID22_MASK 0x00400000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID23_MASK 0x00800000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID24_MASK 0x01000000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID25_MASK 0x02000000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID26_MASK 0x04000000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID27_MASK 0x08000000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID28_MASK 0x10000000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID29_MASK 0x20000000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID30_MASK 0x40000000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID31_MASK 0x80000000L
+//ATC_ATS_FAULT_STATUS_INFO2
+#define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0
+#define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1
+#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID__SHIFT 0x9
+#define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x00000001L
+#define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x0000001EL
+#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID_MASK 0x00003E00L
+//ATHUB_MISC_CNTL
+#define ATHUB_MISC_CNTL__CG_OFFDLY__SHIFT 0x6
+#define ATHUB_MISC_CNTL__CG_ENABLE__SHIFT 0x12
+#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE__SHIFT 0x13
+#define ATHUB_MISC_CNTL__PG_ENABLE__SHIFT 0x14
+#define ATHUB_MISC_CNTL__PG_OFFDLY__SHIFT 0x15
+#define ATHUB_MISC_CNTL__CG_STATUS__SHIFT 0x1b
+#define ATHUB_MISC_CNTL__PG_STATUS__SHIFT 0x1c
+#define ATHUB_MISC_CNTL__CG_OFFDLY_MASK 0x00000FC0L
+#define ATHUB_MISC_CNTL__CG_ENABLE_MASK 0x00040000L
+#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK 0x00080000L
+#define ATHUB_MISC_CNTL__PG_ENABLE_MASK 0x00100000L
+#define ATHUB_MISC_CNTL__PG_OFFDLY_MASK 0x07E00000L
+#define ATHUB_MISC_CNTL__CG_STATUS_MASK 0x08000000L
+#define ATHUB_MISC_CNTL__PG_STATUS_MASK 0x10000000L
+//ATC_VMID_PASID_MAPPING_UPDATE_STATUS
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED__SHIFT 0x10
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED__SHIFT 0x11
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED__SHIFT 0x12
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED__SHIFT 0x13
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED__SHIFT 0x14
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED__SHIFT 0x15
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED__SHIFT 0x16
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED__SHIFT 0x17
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED__SHIFT 0x18
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED__SHIFT 0x19
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED__SHIFT 0x1a
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED__SHIFT 0x1b
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED__SHIFT 0x1c
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED__SHIFT 0x1d
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED__SHIFT 0x1e
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED__SHIFT 0x1f
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED_MASK 0x00010000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED_MASK 0x00020000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED_MASK 0x00040000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED_MASK 0x00080000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED_MASK 0x00100000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED_MASK 0x00200000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED_MASK 0x00400000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED_MASK 0x00800000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED_MASK 0x01000000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED_MASK 0x02000000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED_MASK 0x04000000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED_MASK 0x08000000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED_MASK 0x10000000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED_MASK 0x20000000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED_MASK 0x40000000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED_MASK 0x80000000L
+//ATC_VMID0_PASID_MAPPING
+#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID1_PASID_MAPPING
+#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID2_PASID_MAPPING
+#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID3_PASID_MAPPING
+#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID4_PASID_MAPPING
+#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID5_PASID_MAPPING
+#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID6_PASID_MAPPING
+#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID7_PASID_MAPPING
+#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID8_PASID_MAPPING
+#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID9_PASID_MAPPING
+#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID10_PASID_MAPPING
+#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID11_PASID_MAPPING
+#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID12_PASID_MAPPING
+#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID13_PASID_MAPPING
+#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID14_PASID_MAPPING
+#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID15_PASID_MAPPING
+#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_ATS_VMID_STATUS
+#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0
+#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1
+#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2
+#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3
+#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4
+#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5
+#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6
+#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7
+#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8
+#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9
+#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa
+#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb
+#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc
+#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd
+#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe
+#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf
+#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING__SHIFT 0x10
+#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING__SHIFT 0x11
+#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING__SHIFT 0x12
+#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING__SHIFT 0x13
+#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING__SHIFT 0x14
+#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING__SHIFT 0x15
+#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING__SHIFT 0x16
+#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING__SHIFT 0x17
+#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING__SHIFT 0x18
+#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING__SHIFT 0x19
+#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING__SHIFT 0x1a
+#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING__SHIFT 0x1b
+#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING__SHIFT 0x1c
+#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING__SHIFT 0x1d
+#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING__SHIFT 0x1e
+#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING__SHIFT 0x1f
+#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x00000001L
+#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x00000002L
+#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x00000004L
+#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x00000008L
+#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x00000010L
+#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x00000020L
+#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x00000040L
+#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x00000080L
+#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x00000100L
+#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x00000200L
+#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x00000400L
+#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x00000800L
+#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x00001000L
+#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x00002000L
+#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x00004000L
+#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x00008000L
+#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING_MASK 0x00010000L
+#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING_MASK 0x00020000L
+#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING_MASK 0x00040000L
+#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING_MASK 0x00080000L
+#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING_MASK 0x00100000L
+#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING_MASK 0x00200000L
+#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING_MASK 0x00400000L
+#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING_MASK 0x00800000L
+#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING_MASK 0x01000000L
+#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING_MASK 0x02000000L
+#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING_MASK 0x04000000L
+#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING_MASK 0x08000000L
+#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING_MASK 0x10000000L
+#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING_MASK 0x20000000L
+#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING_MASK 0x40000000L
+#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING_MASK 0x80000000L
+//ATC_ATS_GFX_ATCL2_STATUS
+#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0
+#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L
+//ATC_PERFCOUNTER0_CFG
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//ATC_PERFCOUNTER1_CFG
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//ATC_PERFCOUNTER2_CFG
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//ATC_PERFCOUNTER3_CFG
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
+#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
+#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
+//ATC_PERFCOUNTER_RSLT_CNTL
+#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//ATC_PERFCOUNTER_LO
+#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//ATC_PERFCOUNTER_HI
+#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//ATHUB_PCIE_ATS_CNTL
+#define ATHUB_PCIE_ATS_CNTL__STU__SHIFT 0x10
+#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL__STU_MASK 0x001F0000L
+#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_PASID_CNTL
+#define ATHUB_PCIE_PASID_CNTL__PASID_EN__SHIFT 0x10
+#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x11
+#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x12
+#define ATHUB_PCIE_PASID_CNTL__PASID_EN_MASK 0x00010000L
+#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x00020000L
+#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x00040000L
+//ATHUB_PCIE_PAGE_REQ_CNTL
+#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x00000001L
+#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x00000002L
+//ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//ATHUB_COMMAND
+#define ATHUB_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define ATHUB_COMMAND__BUS_MASTER_EN_MASK 0x00000004L
+//ATHUB_PCIE_ATS_CNTL_VF_0
+#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_1
+#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_2
+#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_3
+#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_4
+#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_5
+#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_6
+#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_7
+#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_8
+#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_9
+#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_10
+#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_11
+#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_12
+#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_13
+#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_14
+#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_15
+#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_MEM_POWER_LS
+#define ATHUB_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
+#define ATHUB_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
+#define ATHUB_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
+#define ATHUB_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
+//ATS_IH_CREDIT
+#define ATS_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
+#define ATS_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10
+#define ATS_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
+#define ATS_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L
+//ATHUB_IH_CREDIT
+#define ATHUB_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
+#define ATHUB_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10
+#define ATHUB_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
+#define ATHUB_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L
+//ATC_VMID16_PASID_MAPPING
+#define ATC_VMID16_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID16_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID16_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID16_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID17_PASID_MAPPING
+#define ATC_VMID17_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID17_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID17_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID17_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID18_PASID_MAPPING
+#define ATC_VMID18_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID18_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID18_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID18_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID19_PASID_MAPPING
+#define ATC_VMID19_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID19_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID19_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID19_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID20_PASID_MAPPING
+#define ATC_VMID20_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID20_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID20_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID20_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID21_PASID_MAPPING
+#define ATC_VMID21_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID21_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID21_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID21_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID22_PASID_MAPPING
+#define ATC_VMID22_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID22_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID22_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID22_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID23_PASID_MAPPING
+#define ATC_VMID23_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID23_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID23_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID23_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID24_PASID_MAPPING
+#define ATC_VMID24_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID24_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID24_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID24_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID25_PASID_MAPPING
+#define ATC_VMID25_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID25_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID25_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID25_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID26_PASID_MAPPING
+#define ATC_VMID26_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID26_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID26_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID26_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID27_PASID_MAPPING
+#define ATC_VMID27_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID27_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID27_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID27_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID28_PASID_MAPPING
+#define ATC_VMID28_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID28_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID28_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID28_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID29_PASID_MAPPING
+#define ATC_VMID29_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID29_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID29_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID29_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID30_PASID_MAPPING
+#define ATC_VMID30_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID30_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID30_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID30_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID31_PASID_MAPPING
+#define ATC_VMID31_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID31_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID31_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID31_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_ATS_MMHUB_ATCL2_STATUS
+#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0
+#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L
+//ATHUB_SHARED_VIRT_RESET_REQ
+#define ATHUB_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define ATHUB_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define ATHUB_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
+#define ATHUB_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L
+//ATHUB_SHARED_ACTIVE_FCN_ID
+#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define ATHUB_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
+#define ATHUB_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//ATC_ATS_SDPPORT_CNTL
+#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE__SHIFT 0x0
+#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE__SHIFT 0x1
+#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD__SHIFT 0x3
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE__SHIFT 0x7
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK__SHIFT 0x8
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD__SHIFT 0x9
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE__SHIFT 0xd
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE__SHIFT 0xe
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE__SHIFT 0xf
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN__SHIFT 0x10
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV__SHIFT 0x11
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN__SHIFT 0x12
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x13
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN__SHIFT 0x14
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV__SHIFT 0x15
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN__SHIFT 0x16
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV__SHIFT 0x17
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN__SHIFT 0x18
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV__SHIFT 0x19
+#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE_MASK 0x00000001L
+#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE_MASK 0x00000006L
+#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD_MASK 0x00000078L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE_MASK 0x00000080L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK_MASK 0x00000100L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD_MASK 0x00001E00L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE_MASK 0x00002000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE_MASK 0x00004000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE_MASK 0x00008000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN_MASK 0x00010000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV_MASK 0x00020000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN_MASK 0x00040000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV_MASK 0x00080000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN_MASK 0x00100000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV_MASK 0x00200000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN_MASK 0x00400000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV_MASK 0x00800000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN_MASK 0x01000000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV_MASK 0x02000000L
+//ATC_ATS_VMID_SNAPSHOT_GFX_STAT
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0__SHIFT 0x0
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1__SHIFT 0x1
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2__SHIFT 0x2
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3__SHIFT 0x3
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4__SHIFT 0x4
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5__SHIFT 0x5
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6__SHIFT 0x6
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7__SHIFT 0x7
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8__SHIFT 0x8
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9__SHIFT 0x9
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10__SHIFT 0xa
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11__SHIFT 0xb
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12__SHIFT 0xc
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13__SHIFT 0xd
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14__SHIFT 0xe
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15__SHIFT 0xf
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0_MASK 0x00000001L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1_MASK 0x00000002L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2_MASK 0x00000004L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3_MASK 0x00000008L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4_MASK 0x00000010L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5_MASK 0x00000020L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6_MASK 0x00000040L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7_MASK 0x00000080L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8_MASK 0x00000100L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9_MASK 0x00000200L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10_MASK 0x00000400L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11_MASK 0x00000800L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12_MASK 0x00001000L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13_MASK 0x00002000L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14_MASK 0x00004000L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15_MASK 0x00008000L
+//ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0__SHIFT 0x0
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1__SHIFT 0x1
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2__SHIFT 0x2
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3__SHIFT 0x3
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4__SHIFT 0x4
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5__SHIFT 0x5
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6__SHIFT 0x6
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7__SHIFT 0x7
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8__SHIFT 0x8
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9__SHIFT 0x9
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10__SHIFT 0xa
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11__SHIFT 0xb
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12__SHIFT 0xc
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13__SHIFT 0xd
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14__SHIFT 0xe
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15__SHIFT 0xf
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0_MASK 0x00000001L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1_MASK 0x00000002L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2_MASK 0x00000004L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3_MASK 0x00000008L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4_MASK 0x00000010L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5_MASK 0x00000020L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6_MASK 0x00000040L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7_MASK 0x00000080L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8_MASK 0x00000100L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9_MASK 0x00000200L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10_MASK 0x00000400L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11_MASK 0x00000800L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12_MASK 0x00001000L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13_MASK 0x00002000L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14_MASK 0x00004000L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15_MASK 0x00008000L
+
+
+// addressBlock: athub_xpbdec
+//XPB_RTR_SRC_APRTR0
+#define XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR1
+#define XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR2
+#define XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR3
+#define XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR4
+#define XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR5
+#define XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR6
+#define XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR7
+#define XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR8
+#define XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR9
+#define XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_XDMA_RTR_SRC_APRTR0
+#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
+#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_XDMA_RTR_SRC_APRTR1
+#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
+#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_XDMA_RTR_SRC_APRTR2
+#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
+#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_XDMA_RTR_SRC_APRTR3
+#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
+#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_DEST_MAP0
+#define XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP1
+#define XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP2
+#define XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP3
+#define XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP4
+#define XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP5
+#define XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP6
+#define XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP7
+#define XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP8
+#define XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP9
+#define XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7C000000L
+//XPB_XDMA_RTR_DEST_MAP0
+#define XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0
+#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
+#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
+#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
+#define XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x00000001L
+#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L
+#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L
+//XPB_XDMA_RTR_DEST_MAP1
+#define XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0
+#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
+#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
+#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
+#define XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x00000001L
+#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L
+#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L
+//XPB_XDMA_RTR_DEST_MAP2
+#define XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0
+#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
+#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
+#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
+#define XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x00000001L
+#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L
+#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L
+//XPB_XDMA_RTR_DEST_MAP3
+#define XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0
+#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
+#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
+#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
+#define XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x00000001L
+#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L
+#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L
+//XPB_CLG_CFG0
+#define XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003C00L
+//XPB_CLG_CFG1
+#define XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003C00L
+//XPB_CLG_CFG2
+#define XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003C00L
+//XPB_CLG_CFG3
+#define XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003C00L
+//XPB_CLG_CFG4
+#define XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003C00L
+//XPB_CLG_CFG5
+#define XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003C00L
+//XPB_CLG_CFG6
+#define XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003C00L
+//XPB_CLG_CFG7
+#define XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003C00L
+//XPB_CLG_EXTRA
+#define XPB_CLG_EXTRA__CMP0_HIGH__SHIFT 0x0
+#define XPB_CLG_EXTRA__CMP0_LOW__SHIFT 0x6
+#define XPB_CLG_EXTRA__VLD0__SHIFT 0xb
+#define XPB_CLG_EXTRA__CLG0_NUM__SHIFT 0xc
+#define XPB_CLG_EXTRA__CMP1_HIGH__SHIFT 0xf
+#define XPB_CLG_EXTRA__CMP1_LOW__SHIFT 0x15
+#define XPB_CLG_EXTRA__VLD1__SHIFT 0x1a
+#define XPB_CLG_EXTRA__CLG1_NUM__SHIFT 0x1b
+#define XPB_CLG_EXTRA__CMP0_HIGH_MASK 0x0000003FL
+#define XPB_CLG_EXTRA__CMP0_LOW_MASK 0x000007C0L
+#define XPB_CLG_EXTRA__VLD0_MASK 0x00000800L
+#define XPB_CLG_EXTRA__CLG0_NUM_MASK 0x00007000L
+#define XPB_CLG_EXTRA__CMP1_HIGH_MASK 0x001F8000L
+#define XPB_CLG_EXTRA__CMP1_LOW_MASK 0x03E00000L
+#define XPB_CLG_EXTRA__VLD1_MASK 0x04000000L
+#define XPB_CLG_EXTRA__CLG1_NUM_MASK 0x38000000L
+//XPB_CLG_EXTRA_MSK
+#define XPB_CLG_EXTRA_MSK__MSK0_HIGH__SHIFT 0x0
+#define XPB_CLG_EXTRA_MSK__MSK0_LOW__SHIFT 0x6
+#define XPB_CLG_EXTRA_MSK__MSK1_HIGH__SHIFT 0xb
+#define XPB_CLG_EXTRA_MSK__MSK1_LOW__SHIFT 0x11
+#define XPB_CLG_EXTRA_MSK__MSK0_HIGH_MASK 0x0000003FL
+#define XPB_CLG_EXTRA_MSK__MSK0_LOW_MASK 0x000007C0L
+#define XPB_CLG_EXTRA_MSK__MSK1_HIGH_MASK 0x0001F800L
+#define XPB_CLG_EXTRA_MSK__MSK1_LOW_MASK 0x003E0000L
+//XPB_LB_ADDR
+#define XPB_LB_ADDR__CMP0__SHIFT 0x0
+#define XPB_LB_ADDR__MASK0__SHIFT 0xa
+#define XPB_LB_ADDR__CMP1__SHIFT 0x14
+#define XPB_LB_ADDR__MASK1__SHIFT 0x1a
+#define XPB_LB_ADDR__CMP0_MASK 0x000003FFL
+#define XPB_LB_ADDR__MASK0_MASK 0x000FFC00L
+#define XPB_LB_ADDR__CMP1_MASK 0x03F00000L
+#define XPB_LB_ADDR__MASK1_MASK 0xFC000000L
+//XPB_WCB_STS
+#define XPB_WCB_STS__PBUF_VLD__SHIFT 0x0
+#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10
+#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17
+#define XPB_WCB_STS__PBUF_VLD_MASK 0x0000FFFFL
+#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007F0000L
+#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3F800000L
+//XPB_HST_CFG
+#define XPB_HST_CFG__BAR_UP_WR_CMD__SHIFT 0x0
+#define XPB_HST_CFG__BAR_UP_WR_CMD_MASK 0x00000001L
+//XPB_P2P_BAR_CFG
+#define XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0
+#define XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4
+#define XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6
+#define XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7
+#define XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8
+#define XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9
+#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa
+#define XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb
+#define XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc
+#define XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000FL
+#define XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L
+#define XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L
+#define XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L
+#define XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L
+#define XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L
+#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L
+#define XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L
+#define XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L
+//XPB_P2P_BAR0
+#define XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR0__VALID__SHIFT 0xc
+#define XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR0__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR0__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR0__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR0__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR0__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR1
+#define XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR1__VALID__SHIFT 0xc
+#define XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR1__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR1__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR1__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR1__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR1__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR2
+#define XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR2__VALID__SHIFT 0xc
+#define XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR2__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR2__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR2__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR2__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR2__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR3
+#define XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR3__VALID__SHIFT 0xc
+#define XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR3__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR3__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR3__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR3__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR3__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR4
+#define XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR4__VALID__SHIFT 0xc
+#define XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR4__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR4__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR4__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR4__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR4__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR5
+#define XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR5__VALID__SHIFT 0xc
+#define XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR5__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR5__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR5__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR5__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR5__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR6
+#define XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR6__VALID__SHIFT 0xc
+#define XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR6__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR6__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR6__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR6__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR6__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR7
+#define XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR7__VALID__SHIFT 0xc
+#define XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR7__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR7__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR7__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR7__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR7__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR_SETUP
+#define XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0
+#define XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc
+#define XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR_SETUP__SEL_MASK 0x000000FFL
+#define XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR_DELTA_ABOVE
+#define XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0
+#define XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8
+#define XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000FFL
+#define XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0FFFFF00L
+//XPB_P2P_BAR_DELTA_BELOW
+#define XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0
+#define XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8
+#define XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000FFL
+#define XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0FFFFF00L
+//XPB_PEER_SYS_BAR0
+#define XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR1
+#define XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR2
+#define XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR3
+#define XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR4
+#define XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR4__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR5
+#define XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR5__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR6
+#define XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR6__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR7
+#define XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR7__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR8
+#define XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR8__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR9
+#define XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR9__ADDR_MASK 0xFFFFFFFEL
+//XPB_XDMA_PEER_SYS_BAR0
+#define XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0
+#define XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x1
+#define XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x00000001L
+#define XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL
+//XPB_XDMA_PEER_SYS_BAR1
+#define XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0
+#define XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x1
+#define XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x00000001L
+#define XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL
+//XPB_XDMA_PEER_SYS_BAR2
+#define XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0
+#define XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x1
+#define XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x00000001L
+#define XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL
+//XPB_XDMA_PEER_SYS_BAR3
+#define XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0
+#define XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x1
+#define XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x00000001L
+#define XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL
+//XPB_CLK_GAT
+#define XPB_CLK_GAT__ONDLY__SHIFT 0x0
+#define XPB_CLK_GAT__OFFDLY__SHIFT 0x6
+#define XPB_CLK_GAT__RDYDLY__SHIFT 0xc
+#define XPB_CLK_GAT__ENABLE__SHIFT 0x12
+#define XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13
+#define XPB_CLK_GAT__ONDLY_MASK 0x0000003FL
+#define XPB_CLK_GAT__OFFDLY_MASK 0x00000FC0L
+#define XPB_CLK_GAT__RDYDLY_MASK 0x0003F000L
+#define XPB_CLK_GAT__ENABLE_MASK 0x00040000L
+#define XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L
+//XPB_INTF_CFG
+#define XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0
+#define XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8
+#define XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10
+#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17
+#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18
+#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19
+#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a
+#define XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b
+#define XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d
+#define XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e
+#define XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f
+#define XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000FFL
+#define XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000FF00L
+#define XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007F0000L
+#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x00800000L
+#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x01000000L
+#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x02000000L
+#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x04000000L
+#define XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L
+#define XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L
+#define XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L
+#define XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000L
+//XPB_INTF_STS
+#define XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0
+#define XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8
+#define XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf
+#define XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10
+#define XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11
+#define XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12
+#define XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13
+#define XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000FFL
+#define XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007F00L
+#define XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L
+#define XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L
+#define XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L
+#define XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L
+#define XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07F80000L
+//XPB_PIPE_STS
+#define XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0
+#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1
+#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8
+#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf
+#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10
+#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11
+#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12
+#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13
+#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14
+#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15
+#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16
+#define XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17
+#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18
+#define XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L
+#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000FEL
+#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007F00L
+#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L
+#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L
+#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L
+#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L
+#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L
+#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L
+#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L
+#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L
+#define XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L
+#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xFF000000L
+//XPB_SUB_CTRL
+#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0
+#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1
+#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2
+#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3
+#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4
+#define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5
+#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6
+#define XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7
+#define XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8
+#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9
+#define XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa
+#define XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb
+#define XPB_SUB_CTRL__RESET_RET__SHIFT 0xc
+#define XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd
+#define XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe
+#define XPB_SUB_CTRL__RESET_HST__SHIFT 0xf
+#define XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10
+#define XPB_SUB_CTRL__RESET_SID__SHIFT 0x11
+#define XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12
+#define XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13
+#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L
+#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L
+#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L
+#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L
+#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L
+#define XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L
+#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L
+#define XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L
+#define XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L
+#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L
+#define XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L
+#define XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L
+#define XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L
+#define XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L
+#define XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L
+#define XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L
+#define XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L
+#define XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L
+#define XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L
+#define XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L
+//XPB_MAP_INVERT_FLUSH_NUM_LSB
+#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0
+#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000FFFFL
+//XPB_PERF_KNOBS
+#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0
+#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6
+#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc
+#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003FL
+#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000FC0L
+#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003F000L
+//XPB_STICKY
+#define XPB_STICKY__BITS__SHIFT 0x0
+#define XPB_STICKY__BITS_MASK 0xFFFFFFFFL
+//XPB_STICKY_W1C
+#define XPB_STICKY_W1C__BITS__SHIFT 0x0
+#define XPB_STICKY_W1C__BITS_MASK 0xFFFFFFFFL
+//XPB_MISC_CFG
+#define XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0
+#define XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8
+#define XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10
+#define XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18
+#define XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f
+#define XPB_MISC_CFG__FIELDNAME0_MASK 0x000000FFL
+#define XPB_MISC_CFG__FIELDNAME1_MASK 0x0000FF00L
+#define XPB_MISC_CFG__FIELDNAME2_MASK 0x00FF0000L
+#define XPB_MISC_CFG__FIELDNAME3_MASK 0x7F000000L
+#define XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L
+//XPB_INTF_CFG2
+#define XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0
+#define XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000FFL
+//XPB_CLG_EXTRA_RD
+#define XPB_CLG_EXTRA_RD__CMP0_HIGH__SHIFT 0x0
+#define XPB_CLG_EXTRA_RD__CMP0_LOW__SHIFT 0x6
+#define XPB_CLG_EXTRA_RD__VLD0__SHIFT 0xb
+#define XPB_CLG_EXTRA_RD__CLG0_NUM__SHIFT 0xc
+#define XPB_CLG_EXTRA_RD__CMP1_HIGH__SHIFT 0xf
+#define XPB_CLG_EXTRA_RD__CMP1_LOW__SHIFT 0x15
+#define XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x1a
+#define XPB_CLG_EXTRA_RD__CLG1_NUM__SHIFT 0x1b
+#define XPB_CLG_EXTRA_RD__CMP0_HIGH_MASK 0x0000003FL
+#define XPB_CLG_EXTRA_RD__CMP0_LOW_MASK 0x000007C0L
+#define XPB_CLG_EXTRA_RD__VLD0_MASK 0x00000800L
+#define XPB_CLG_EXTRA_RD__CLG0_NUM_MASK 0x00007000L
+#define XPB_CLG_EXTRA_RD__CMP1_HIGH_MASK 0x001F8000L
+#define XPB_CLG_EXTRA_RD__CMP1_LOW_MASK 0x03E00000L
+#define XPB_CLG_EXTRA_RD__VLD1_MASK 0x04000000L
+#define XPB_CLG_EXTRA_RD__CLG1_NUM_MASK 0x38000000L
+//XPB_CLG_EXTRA_MSK_RD
+#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH__SHIFT 0x0
+#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW__SHIFT 0x6
+#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH__SHIFT 0xb
+#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW__SHIFT 0x11
+#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH_MASK 0x0000003FL
+#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW_MASK 0x000007C0L
+#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH_MASK 0x0001F800L
+#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW_MASK 0x003E0000L
+//XPB_CLG_GFX_MATCH
+#define XPB_CLG_GFX_MATCH__FARBIRC0_ID__SHIFT 0x0
+#define XPB_CLG_GFX_MATCH__FARBIRC1_ID__SHIFT 0x6
+#define XPB_CLG_GFX_MATCH__FARBIRC2_ID__SHIFT 0xc
+#define XPB_CLG_GFX_MATCH__FARBIRC3_ID__SHIFT 0x12
+#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD__SHIFT 0x18
+#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD__SHIFT 0x19
+#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD__SHIFT 0x1a
+#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD__SHIFT 0x1b
+#define XPB_CLG_GFX_MATCH__FARBIRC0_ID_MASK 0x0000003FL
+#define XPB_CLG_GFX_MATCH__FARBIRC1_ID_MASK 0x00000FC0L
+#define XPB_CLG_GFX_MATCH__FARBIRC2_ID_MASK 0x0003F000L
+#define XPB_CLG_GFX_MATCH__FARBIRC3_ID_MASK 0x00FC0000L
+#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD_MASK 0x01000000L
+#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD_MASK 0x02000000L
+#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD_MASK 0x04000000L
+#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD_MASK 0x08000000L
+//XPB_CLG_GFX_MATCH_MSK
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L
+//XPB_CLG_MM_MATCH
+#define XPB_CLG_MM_MATCH__FARBIRC0_ID__SHIFT 0x0
+#define XPB_CLG_MM_MATCH__FARBIRC1_ID__SHIFT 0x6
+#define XPB_CLG_MM_MATCH__FARBIRC2_ID__SHIFT 0xc
+#define XPB_CLG_MM_MATCH__FARBIRC3_ID__SHIFT 0x12
+#define XPB_CLG_MM_MATCH__FARBIRC0_VLD__SHIFT 0x18
+#define XPB_CLG_MM_MATCH__FARBIRC1_VLD__SHIFT 0x19
+#define XPB_CLG_MM_MATCH__FARBIRC2_VLD__SHIFT 0x1a
+#define XPB_CLG_MM_MATCH__FARBIRC3_VLD__SHIFT 0x1b
+#define XPB_CLG_MM_MATCH__FARBIRC0_ID_MASK 0x0000003FL
+#define XPB_CLG_MM_MATCH__FARBIRC1_ID_MASK 0x00000FC0L
+#define XPB_CLG_MM_MATCH__FARBIRC2_ID_MASK 0x0003F000L
+#define XPB_CLG_MM_MATCH__FARBIRC3_ID_MASK 0x00FC0000L
+#define XPB_CLG_MM_MATCH__FARBIRC0_VLD_MASK 0x01000000L
+#define XPB_CLG_MM_MATCH__FARBIRC1_VLD_MASK 0x02000000L
+#define XPB_CLG_MM_MATCH__FARBIRC2_VLD_MASK 0x04000000L
+#define XPB_CLG_MM_MATCH__FARBIRC3_VLD_MASK 0x08000000L
+//XPB_CLG_MM_MATCH_MSK
+#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0
+#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6
+#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc
+#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12
+#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL
+#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L
+#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L
+#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L
+//XPB_CLG_GFX_UNITID_MAPPING0
+#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GFX_UNITID_MAPPING1
+#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GFX_UNITID_MAPPING2
+#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GFX_UNITID_MAPPING3
+#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GFX_UNITID_MAPPING4
+#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GFX_UNITID_MAPPING5
+#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GFX_UNITID_MAPPING6
+#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GFX_UNITID_MAPPING7
+#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_MM_UNITID_MAPPING0
+#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_MM_UNITID_MAPPING1
+#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_MM_UNITID_MAPPING2
+#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_MM_UNITID_MAPPING3
+#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L
+
+
+// addressBlock: athub_rpbdec
+//RPB_PASSPW_CONF
+#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE__SHIFT 0x0
+#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE__SHIFT 0x1
+#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE__SHIFT 0x2
+#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE__SHIFT 0x3
+#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE__SHIFT 0x4
+#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE__SHIFT 0x5
+#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE__SHIFT 0x6
+#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE__SHIFT 0x7
+#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE__SHIFT 0x8
+#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE__SHIFT 0x9
+#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE__SHIFT 0xa
+#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN__SHIFT 0xb
+#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN__SHIFT 0xc
+#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN__SHIFT 0xd
+#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE__SHIFT 0xe
+#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN__SHIFT 0xf
+#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE__SHIFT 0x10
+#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN__SHIFT 0x11
+#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE_MASK 0x00000001L
+#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE_MASK 0x00000002L
+#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_MASK 0x00000004L
+#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_MASK 0x00000008L
+#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE_MASK 0x00000010L
+#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE_MASK 0x00000020L
+#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE_MASK 0x00000040L
+#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE_MASK 0x00000080L
+#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_MASK 0x00000100L
+#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE_MASK 0x00000200L
+#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE_MASK 0x00000400L
+#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN_MASK 0x00000800L
+#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN_MASK 0x00001000L
+#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN_MASK 0x00002000L
+#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_MASK 0x00004000L
+#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN_MASK 0x00008000L
+#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_MASK 0x00010000L
+#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN_MASK 0x00020000L
+//RPB_BLOCKLEVEL_CONF
+#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE__SHIFT 0x0
+#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL__SHIFT 0x2
+#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL__SHIFT 0x4
+#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL__SHIFT 0x6
+#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE__SHIFT 0x8
+#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE__SHIFT 0xa
+#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE__SHIFT 0xc
+#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xe
+#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xf
+#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x10
+#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x11
+#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_MASK 0x00000003L
+#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL_MASK 0x0000000CL
+#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL_MASK 0x00000030L
+#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL_MASK 0x000000C0L
+#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_MASK 0x00000300L
+#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_MASK 0x00000C00L
+#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_MASK 0x00003000L
+#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00004000L
+#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00008000L
+#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00010000L
+#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00020000L
+//RPB_TAG_CONF
+#define RPB_TAG_CONF__RPB_ATS_TR__SHIFT 0x0
+#define RPB_TAG_CONF__RPB_IO_WR__SHIFT 0x8
+#define RPB_TAG_CONF__RPB_ATS_PR__SHIFT 0x10
+#define RPB_TAG_CONF__RPB_ATS_TR_MASK 0x000000FFL
+#define RPB_TAG_CONF__RPB_IO_WR_MASK 0x0000FF00L
+#define RPB_TAG_CONF__RPB_ATS_PR_MASK 0x00FF0000L
+//RPB_EFF_CNTL
+#define RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0
+#define RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8
+#define RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0x000000FFL
+#define RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0x0000FF00L
+//RPB_ARB_CNTL
+#define RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x0
+#define RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x8
+#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM__SHIFT 0x10
+#define RPB_ARB_CNTL__ARB_MODE__SHIFT 0x18
+#define RPB_ARB_CNTL__SWITCH_NUM_MODE__SHIFT 0x19
+#define RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x000000FFL
+#define RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x0000FF00L
+#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM_MASK 0x00FF0000L
+#define RPB_ARB_CNTL__ARB_MODE_MASK 0x01000000L
+#define RPB_ARB_CNTL__SWITCH_NUM_MODE_MASK 0x02000000L
+//RPB_ARB_CNTL2
+#define RPB_ARB_CNTL2__P2P_SWITCH_NUM__SHIFT 0x0
+#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM__SHIFT 0x8
+#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM__SHIFT 0x10
+#define RPB_ARB_CNTL2__P2P_SWITCH_NUM_MASK 0x000000FFL
+#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM_MASK 0x0000FF00L
+#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM_MASK 0x00FF0000L
+//RPB_BIF_CNTL
+#define RPB_BIF_CNTL__VC0_SWITCH_NUM__SHIFT 0x0
+#define RPB_BIF_CNTL__VC1_SWITCH_NUM__SHIFT 0x8
+#define RPB_BIF_CNTL__ARB_MODE__SHIFT 0x10
+#define RPB_BIF_CNTL__DRAIN_VC_NUM__SHIFT 0x11
+#define RPB_BIF_CNTL__SWITCH_ENABLE__SHIFT 0x12
+#define RPB_BIF_CNTL__SWITCH_THRESHOLD__SHIFT 0x13
+#define RPB_BIF_CNTL__PAGE_PRI_EN__SHIFT 0x1b
+#define RPB_BIF_CNTL__TR_PRI_EN__SHIFT 0x1c
+#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE__SHIFT 0x1d
+#define RPB_BIF_CNTL__PARITY_CHECK_EN__SHIFT 0x1e
+#define RPB_BIF_CNTL__VC0_SWITCH_NUM_MASK 0x000000FFL
+#define RPB_BIF_CNTL__VC1_SWITCH_NUM_MASK 0x0000FF00L
+#define RPB_BIF_CNTL__ARB_MODE_MASK 0x00010000L
+#define RPB_BIF_CNTL__DRAIN_VC_NUM_MASK 0x00020000L
+#define RPB_BIF_CNTL__SWITCH_ENABLE_MASK 0x00040000L
+#define RPB_BIF_CNTL__SWITCH_THRESHOLD_MASK 0x07F80000L
+#define RPB_BIF_CNTL__PAGE_PRI_EN_MASK 0x08000000L
+#define RPB_BIF_CNTL__TR_PRI_EN_MASK 0x10000000L
+#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE_MASK 0x20000000L
+#define RPB_BIF_CNTL__PARITY_CHECK_EN_MASK 0x40000000L
+//RPB_WR_SWITCH_CNTL
+#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
+#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7
+#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe
+#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15
+#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c
+#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL
+#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L
+#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L
+#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L
+#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L
+//RPB_RD_SWITCH_CNTL
+#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
+#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7
+#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe
+#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15
+#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c
+#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL
+#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L
+#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L
+#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L
+#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L
+//RPB_CID_QUEUE_WR
+#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW__SHIFT 0x0
+#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH__SHIFT 0x5
+#define RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0xb
+#define RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0xc
+#define RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xf
+#define RPB_CID_QUEUE_WR__UPDATE__SHIFT 0x12
+#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW_MASK 0x0000001FL
+#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH_MASK 0x000007E0L
+#define RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x00000800L
+#define RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x00007000L
+#define RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x00038000L
+#define RPB_CID_QUEUE_WR__UPDATE_MASK 0x00040000L
+//RPB_CID_QUEUE_RD
+#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW__SHIFT 0x0
+#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH__SHIFT 0x5
+#define RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0xb
+#define RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xe
+#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW_MASK 0x0000001FL
+#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH_MASK 0x000007E0L
+#define RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x00003800L
+#define RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0x0001C000L
+//RPB_CID_QUEUE_EX
+#define RPB_CID_QUEUE_EX__START__SHIFT 0x0
+#define RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1
+#define RPB_CID_QUEUE_EX__START_MASK 0x00000001L
+#define RPB_CID_QUEUE_EX__OFFSET_MASK 0x000001FEL
+//RPB_CID_QUEUE_EX_DATA
+#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0
+#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10
+#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0x0000FFFFL
+#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xFFFF0000L
+//RPB_SWITCH_CNTL2
+#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM__SHIFT 0x0
+#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM__SHIFT 0x7
+#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM__SHIFT 0xe
+#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM__SHIFT 0x15
+#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM_MASK 0x0000007FL
+#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM_MASK 0x00003F80L
+#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM_MASK 0x001FC000L
+#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM_MASK 0x0FE00000L
+//RPB_DEINTRLV_COMBINE_CNTL
+#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER__SHIFT 0x0
+#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN__SHIFT 0x4
+#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE__SHIFT 0x5
+#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER_MASK 0x0000000FL
+#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN_MASK 0x00000010L
+#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE_MASK 0x00000020L
+//RPB_VC_SWITCH_RDWR
+#define RPB_VC_SWITCH_RDWR__MODE__SHIFT 0x0
+#define RPB_VC_SWITCH_RDWR__NUM_RD__SHIFT 0x2
+#define RPB_VC_SWITCH_RDWR__NUM_WR__SHIFT 0xa
+#define RPB_VC_SWITCH_RDWR__MODE_MASK 0x00000003L
+#define RPB_VC_SWITCH_RDWR__NUM_RD_MASK 0x000003FCL
+#define RPB_VC_SWITCH_RDWR__NUM_WR_MASK 0x0003FC00L
+//RPB_PERFCOUNTER_LO
+#define RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//RPB_PERFCOUNTER_HI
+#define RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//RPB_PERFCOUNTER0_CFG
+#define RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//RPB_PERFCOUNTER1_CFG
+#define RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//RPB_PERFCOUNTER2_CFG
+#define RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//RPB_PERFCOUNTER3_CFG
+#define RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
+#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
+#define RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
+#define RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
+//RPB_PERFCOUNTER_RSLT_CNTL
+#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//RPB_RD_QUEUE_CNTL
+#define RPB_RD_QUEUE_CNTL__ARB_MODE__SHIFT 0x0
+#define RPB_RD_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1
+#define RPB_RD_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2
+#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3
+#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4
+#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5
+#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa
+#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10
+#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15
+#define RPB_RD_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L
+#define RPB_RD_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L
+#define RPB_RD_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L
+#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L
+#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L
+#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L
+#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L
+#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L
+#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L
+//RPB_RD_QUEUE_CNTL2
+#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0
+#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5
+#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb
+#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10
+#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL
+#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L
+#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L
+#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L
+//RPB_WR_QUEUE_CNTL
+#define RPB_WR_QUEUE_CNTL__ARB_MODE__SHIFT 0x0
+#define RPB_WR_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1
+#define RPB_WR_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2
+#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3
+#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4
+#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5
+#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa
+#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10
+#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15
+#define RPB_WR_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L
+#define RPB_WR_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L
+#define RPB_WR_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L
+#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L
+#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L
+#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L
+#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L
+#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L
+#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L
+//RPB_WR_QUEUE_CNTL2
+#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0
+#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5
+#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb
+#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10
+#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL
+#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L
+#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L
+#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L
+//RPB_EA_QUEUE_WR
+#define RPB_EA_QUEUE_WR__EA_NUMBER__SHIFT 0x0
+#define RPB_EA_QUEUE_WR__WRITE_QUEUE__SHIFT 0x5
+#define RPB_EA_QUEUE_WR__READ_QUEUE__SHIFT 0x8
+#define RPB_EA_QUEUE_WR__UPDATE__SHIFT 0xb
+#define RPB_EA_QUEUE_WR__EA_NUMBER_MASK 0x0000001FL
+#define RPB_EA_QUEUE_WR__WRITE_QUEUE_MASK 0x000000E0L
+#define RPB_EA_QUEUE_WR__READ_QUEUE_MASK 0x00000700L
+#define RPB_EA_QUEUE_WR__UPDATE_MASK 0x00000800L
+//RPB_ATS_CNTL
+#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE__SHIFT 0x0
+#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE__SHIFT 0x1
+#define RPB_ATS_CNTL__SWITCH_THRESHOLD__SHIFT 0x2
+#define RPB_ATS_CNTL__TIME_SLICE__SHIFT 0x7
+#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM__SHIFT 0xf
+#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM__SHIFT 0x13
+#define RPB_ATS_CNTL__WR_AT__SHIFT 0x17
+#define RPB_ATS_CNTL__INVAL_COM_CMD__SHIFT 0x19
+#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE_MASK 0x00000001L
+#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE_MASK 0x00000002L
+#define RPB_ATS_CNTL__SWITCH_THRESHOLD_MASK 0x0000007CL
+#define RPB_ATS_CNTL__TIME_SLICE_MASK 0x00007F80L
+#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM_MASK 0x00078000L
+#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM_MASK 0x00780000L
+#define RPB_ATS_CNTL__WR_AT_MASK 0x01800000L
+#define RPB_ATS_CNTL__INVAL_COM_CMD_MASK 0x7E000000L
+//RPB_ATS_CNTL2
+#define RPB_ATS_CNTL2__TRANS_CMD__SHIFT 0x0
+#define RPB_ATS_CNTL2__PAGE_REQ_CMD__SHIFT 0x6
+#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE__SHIFT 0xc
+#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE__SHIFT 0xf
+#define RPB_ATS_CNTL2__VENDOR_ID__SHIFT 0x12
+#define RPB_ATS_CNTL2__TRANS_CMD_MASK 0x0000003FL
+#define RPB_ATS_CNTL2__PAGE_REQ_CMD_MASK 0x00000FC0L
+#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE_MASK 0x00007000L
+#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE_MASK 0x00038000L
+#define RPB_ATS_CNTL2__VENDOR_ID_MASK 0x000C0000L
+//RPB_SDPPORT_CNTL
+#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE__SHIFT 0x0
+#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE__SHIFT 0x1
+#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT__SHIFT 0x3
+#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER__SHIFT 0x4
+#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS__SHIFT 0x5
+#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD__SHIFT 0x6
+#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE__SHIFT 0xa
+#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE__SHIFT 0xb
+#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT__SHIFT 0xd
+#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER__SHIFT 0xe
+#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS__SHIFT 0xf
+#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD__SHIFT 0x10
+#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE__SHIFT 0x14
+#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK__SHIFT 0x15
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN__SHIFT 0x16
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV__SHIFT 0x17
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN__SHIFT 0x18
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x19
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN__SHIFT 0x1a
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV__SHIFT 0x1b
+#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE_MASK 0x00000001L
+#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE_MASK 0x00000006L
+#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT_MASK 0x00000008L
+#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER_MASK 0x00000010L
+#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS_MASK 0x00000020L
+#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD_MASK 0x000003C0L
+#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE_MASK 0x00000400L
+#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE_MASK 0x00001800L
+#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT_MASK 0x00002000L
+#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER_MASK 0x00004000L
+#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS_MASK 0x00008000L
+#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD_MASK 0x000F0000L
+#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE_MASK 0x00100000L
+#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK_MASK 0x00200000L
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN_MASK 0x00400000L
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN_MASK 0x04000000L
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h
new file mode 100644
index 000000000000..8a0007ce43dc
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h
@@ -0,0 +1,9868 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dce_12_0_DEFAULT_HEADER
+#define _dce_12_0_DEFAULT_HEADER
+
+
+// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
+#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
+#define mmdispdec_VGA_MEM_READ_PAGE_ADDR_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_perfmon0_dispdec
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON0_PERFCOUNTER_STATE_DEFAULT 0x00000000
+#define mmDC_PERFMON0_PERFMON_CNTL_DEFAULT 0x00000100
+#define mmDC_PERFMON0_PERFMON_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+#define mmDC_PERFMON0_PERFMON_HI_DEFAULT 0x00000000
+#define mmDC_PERFMON0_PERFMON_LOW_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_perfmon13_dispdec
+#define mmDC_PERFMON13_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON13_PERFCOUNTER_STATE_DEFAULT 0x00000000
+#define mmDC_PERFMON13_PERFMON_CNTL_DEFAULT 0x00000100
+#define mmDC_PERFMON13_PERFMON_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+#define mmDC_PERFMON13_PERFMON_HI_DEFAULT 0x00000000
+#define mmDC_PERFMON13_PERFMON_LOW_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_displaypllregs_dispdec
+#define mmPPLL_VREG_CFG_DEFAULT 0x00000000
+#define mmPPLL_MODE_CNTL_DEFAULT 0x00020100
+#define mmPPLL_FREQ_CTRL0_DEFAULT 0x00280000
+#define mmPPLL_FREQ_CTRL1_DEFAULT 0x00000000
+#define mmPPLL_FREQ_CTRL2_DEFAULT 0x00000000
+#define mmPPLL_FREQ_CTRL3_DEFAULT 0x00190040
+#define mmPPLL_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
+#define mmPPLL_BW_CTRL_FINE_DEFAULT 0x00000001
+#define mmPPLL_CAL_CTRL_DEFAULT 0x64000002
+#define mmPPLL_LOOP_CTRL_DEFAULT 0x00000090
+#define mmPPLL_REFCLK_CNTL_DEFAULT 0x00018004
+#define mmPPLL_CLKOUT_CNTL_DEFAULT 0x00022500
+#define mmPPLL_DFT_CNTL_DEFAULT 0x00000004
+#define mmPPLL_ANALOG_CNTL_DEFAULT 0x00000000
+#define mmPPLL_POSTDIV_DEFAULT 0x00000400
+#define mmPPLL_OBSERVE0_DEFAULT 0x00000000
+#define mmPPLL_OBSERVE1_DEFAULT 0x04b00000
+#define mmPPLL_UPDATE_CNTL_DEFAULT 0x00000000
+#define mmPPLL_OBSERVE0_OUT_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dccg_pll0_dispdec
+#define mmPLL_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_perfmon1_dispdec
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON1_PERFCOUNTER_STATE_DEFAULT 0x00000000
+#define mmDC_PERFMON1_PERFMON_CNTL_DEFAULT 0x00000100
+#define mmDC_PERFMON1_PERFMON_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+#define mmDC_PERFMON1_PERFMON_HI_DEFAULT 0x00000000
+#define mmDC_PERFMON1_PERFMON_LOW_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_mcif_wb0_dispdec
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400
+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000
+#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040
+#define mmMCIF_WB0_MCIF_WB_WATERMARK_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000
+#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002
+#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080
+#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff
+#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff
+
+
+// addressBlock: dce_dc_mcif_wb1_dispdec
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400
+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000
+#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040
+#define mmMCIF_WB1_MCIF_WB_WATERMARK_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000
+#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002
+#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080
+#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff
+#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff
+
+
+// addressBlock: dce_dc_mcif_wb2_dispdec
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400
+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000
+#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040
+#define mmMCIF_WB2_MCIF_WB_WATERMARK_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000
+#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002
+#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080
+#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff
+#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff
+
+
+// addressBlock: dce_dc_cwb0_dispdec
+#define mmCWB0_CWB_CTRL_DEFAULT 0x00000110
+#define mmCWB0_CWB_FENCE_PAR0_DEFAULT 0x03ff03ff
+#define mmCWB0_CWB_FENCE_PAR1_DEFAULT 0x000102ff
+#define mmCWB0_CWB_CRC_CTRL_DEFAULT 0x00000000
+#define mmCWB0_CWB_CRC_RED_GREEN_MASK_DEFAULT 0xffffffff
+#define mmCWB0_CWB_CRC_BLUE_MASK_DEFAULT 0x0000ffff
+#define mmCWB0_CWB_CRC_RED_GREEN_RESULT_DEFAULT 0x00000000
+#define mmCWB0_CWB_CRC_BLUE_RESULT_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_cwb1_dispdec
+#define mmCWB1_CWB_CTRL_DEFAULT 0x00000110
+#define mmCWB1_CWB_FENCE_PAR0_DEFAULT 0x03ff03ff
+#define mmCWB1_CWB_FENCE_PAR1_DEFAULT 0x000102ff
+#define mmCWB1_CWB_CRC_CTRL_DEFAULT 0x00000000
+#define mmCWB1_CWB_CRC_RED_GREEN_MASK_DEFAULT 0xffffffff
+#define mmCWB1_CWB_CRC_BLUE_MASK_DEFAULT 0x0000ffff
+#define mmCWB1_CWB_CRC_RED_GREEN_RESULT_DEFAULT 0x00000000
+#define mmCWB1_CWB_CRC_BLUE_RESULT_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_perfmon9_dispdec
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON9_PERFCOUNTER_STATE_DEFAULT 0x00000000
+#define mmDC_PERFMON9_PERFMON_CNTL_DEFAULT 0x00000100
+#define mmDC_PERFMON9_PERFMON_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+#define mmDC_PERFMON9_PERFMON_HI_DEFAULT 0x00000000
+#define mmDC_PERFMON9_PERFMON_LOW_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dispdec
+#define mmVGA_MEM_WRITE_PAGE_ADDR_DEFAULT 0x00000000
+#define mmVGA_MEM_READ_PAGE_ADDR_DEFAULT 0x00000000
+#define mmVGA_RENDER_CONTROL_DEFAULT 0x0000000f
+#define mmVGA_SEQUENCER_RESET_CONTROL_DEFAULT 0x00003f3f
+#define mmVGA_MODE_CONTROL_DEFAULT 0x00000000
+#define mmVGA_SURFACE_PITCH_SELECT_DEFAULT 0x00000002
+#define mmVGA_MEMORY_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmVGA_DISPBUF1_SURFACE_ADDR_DEFAULT 0x00000000
+#define mmVGA_DISPBUF2_SURFACE_ADDR_DEFAULT 0x00000000
+#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmVGA_HDP_CONTROL_DEFAULT 0x00000000
+#define mmVGA_CACHE_CONTROL_DEFAULT 0x00000000
+#define mmD1VGA_CONTROL_DEFAULT 0x00000000
+#define mmD2VGA_CONTROL_DEFAULT 0x00000000
+#define mmVGA_STATUS_DEFAULT 0x00000000
+#define mmVGA_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmVGA_STATUS_CLEAR_DEFAULT 0x00000000
+#define mmVGA_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmVGA_MAIN_CONTROL_DEFAULT 0x00005018
+#define mmVGA_TEST_CONTROL_DEFAULT 0x00000000
+#define mmVGA_QOS_CTRL_DEFAULT 0x00000000
+#define mmCRTC8_IDX_DEFAULT 0x00000000
+#define mmCRTC8_DATA_DEFAULT 0x00000000
+#define mmGENFC_WT_DEFAULT 0x00000000
+#define mmGENS1_DEFAULT 0x00000000
+#define mmATTRDW_DEFAULT 0x00000000
+#define mmATTRX_DEFAULT 0x00000000
+#define mmATTRDR_DEFAULT 0x00000000
+#define mmGENMO_WT_DEFAULT 0x00000000
+#define mmGENS0_DEFAULT 0x00000000
+#define mmGENENB_DEFAULT 0x00000000
+#define mmSEQ8_IDX_DEFAULT 0x00000000
+#define mmSEQ8_DATA_DEFAULT 0x00000000
+#define mmDAC_MASK_DEFAULT 0x00000000
+#define mmDAC_R_INDEX_DEFAULT 0x00000000
+#define mmDAC_W_INDEX_DEFAULT 0x00000000
+#define mmDAC_DATA_DEFAULT 0x00000000
+#define mmGENFC_RD_DEFAULT 0x00000000
+#define mmGENMO_RD_DEFAULT 0x00000000
+#define mmGRPH8_IDX_DEFAULT 0x00000000
+#define mmGRPH8_DATA_DEFAULT 0x00000000
+#define mmCRTC8_IDX_1_DEFAULT 0x00000000
+#define mmCRTC8_DATA_1_DEFAULT 0x00000000
+#define mmGENFC_WT_1_DEFAULT 0x00000000
+#define mmGENS1_1_DEFAULT 0x00000000
+#define mmD3VGA_CONTROL_DEFAULT 0x00000000
+#define mmD4VGA_CONTROL_DEFAULT 0x00000000
+#define mmD5VGA_CONTROL_DEFAULT 0x00000000
+#define mmD6VGA_CONTROL_DEFAULT 0x00000000
+#define mmVGA_SOURCE_SELECT_DEFAULT 0x00000100
+#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
+#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
+#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
+#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
+#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmDCFEV1_CRTC_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmSYMCLKLPA_CLOCK_ENABLE_DEFAULT 0x00000000
+#define mmSYMCLKLPB_CLOCK_ENABLE_DEFAULT 0x00000100
+#define mmDPREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
+#define mmREFCLK_CNTL_DEFAULT 0x00000000
+#define mmMIPI_CLK_CNTL_DEFAULT 0x00000000
+#define mmREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
+#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
+#define mmDCCG_PERFMON_CNTL2_DEFAULT 0x00000000
+#define mmDSICLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
+#define mmDCCG_CBUS_WRCMD_DELAY_DEFAULT 0x00000003
+#define mmDCCG_DS_DTO_INCR_DEFAULT 0x00000000
+#define mmDCCG_DS_DTO_MODULO_DEFAULT 0x00000000
+#define mmDCCG_DS_CNTL_DEFAULT 0x00000000
+#define mmDCCG_DS_HW_CAL_INTERVAL_DEFAULT 0x00989680
+#define mmSYMCLKG_CLOCK_ENABLE_DEFAULT 0x00000600
+#define mmDPREFCLK_CNTL_DEFAULT 0x00000000
+#define mmAOMCLK0_CNTL_DEFAULT 0x00000000
+#define mmAOMCLK1_CNTL_DEFAULT 0x00000000
+#define mmAOMCLK2_CNTL_DEFAULT 0x00000000
+#define mmDCCG_AUDIO_DTO2_PHASE_DEFAULT 0x00000000
+#define mmDCCG_AUDIO_DTO2_MODULO_DEFAULT 0x00000001
+#define mmDCE_VERSION_DEFAULT 0x00000000
+#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
+#define mmDCCG_GTC_CNTL_DEFAULT 0x00000000
+#define mmDCCG_GTC_DTO_INCR_DEFAULT 0x00000000
+#define mmDCCG_GTC_DTO_MODULO_DEFAULT 0x00000000
+#define mmDCCG_GTC_CURRENT_DEFAULT 0x00000000
+#define mmDENTIST_DISPCLK_CNTL_DEFAULT 0x64010064
+#define mmMIPI_DTO_CNTL_DEFAULT 0x00000000
+#define mmMIPI_DTO_PHASE_DEFAULT 0x00000000
+#define mmMIPI_DTO_MODULO_DEFAULT 0x00000000
+#define mmDAC_CLK_ENABLE_DEFAULT 0x00000000
+#define mmDVO_CLK_ENABLE_DEFAULT 0x00000000
+#define mmAVSYNC_COUNTER_WRITE_DEFAULT 0x00000000
+#define mmAVSYNC_COUNTER_CONTROL_DEFAULT 0x00000000
+#define mmDMCU_SMU_INTERRUPT_CNTL_DEFAULT 0x00000000
+#define mmSMU_CONTROL_DEFAULT 0x00000000
+#define mmSMU_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmAVSYNC_COUNTER_READ_DEFAULT 0x00000000
+#define mmMILLISECOND_TIME_BASE_DIV_DEFAULT 0x001186a0
+#define mmDISPCLK_FREQ_CHANGE_CNTL_DEFAULT 0x08010028
+#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_DEFAULT 0x00000001
+#define mmDCCG_PERFMON_CNTL_DEFAULT 0xfffff800
+#define mmDCCG_GATE_DISABLE_CNTL_DEFAULT 0x74ee00fd
+#define mmDISPCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
+#define mmSCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
+#define mmDCCG_CAC_STATUS_DEFAULT 0x00000000
+#define mmPIXCLK1_RESYNC_CNTL_DEFAULT 0x00000000
+#define mmPIXCLK2_RESYNC_CNTL_DEFAULT 0x00000000
+#define mmPIXCLK0_RESYNC_CNTL_DEFAULT 0x00000000
+#define mmMICROSECOND_TIME_BASE_DIV_DEFAULT 0x00120464
+#define mmDCCG_GATE_DISABLE_CNTL2_DEFAULT 0x037f037f
+#define mmSYMCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
+#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
+#define mmDCCG_DISP_CNTL_REG_DEFAULT 0x00000000
+#define mmCRTC0_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmDP_DTO0_PHASE_DEFAULT 0x00000000
+#define mmDP_DTO0_MODULO_DEFAULT 0x00000000
+#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmCRTC1_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmDP_DTO1_PHASE_DEFAULT 0x00000000
+#define mmDP_DTO1_MODULO_DEFAULT 0x00000000
+#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmCRTC2_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmDP_DTO2_PHASE_DEFAULT 0x00000000
+#define mmDP_DTO2_MODULO_DEFAULT 0x00000000
+#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmCRTC3_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmDP_DTO3_PHASE_DEFAULT 0x00000000
+#define mmDP_DTO3_MODULO_DEFAULT 0x00000000
+#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmCRTC4_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmDP_DTO4_PHASE_DEFAULT 0x00000000
+#define mmDP_DTO4_MODULO_DEFAULT 0x00000000
+#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmCRTC5_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmDP_DTO5_PHASE_DEFAULT 0x00000000
+#define mmDP_DTO5_MODULO_DEFAULT 0x00000000
+#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmDCCG_SOFT_RESET_DEFAULT 0x00000000
+#define mmSYMCLKA_CLOCK_ENABLE_DEFAULT 0x00000000
+#define mmSYMCLKB_CLOCK_ENABLE_DEFAULT 0x00000100
+#define mmSYMCLKC_CLOCK_ENABLE_DEFAULT 0x00000200
+#define mmSYMCLKD_CLOCK_ENABLE_DEFAULT 0x00000300
+#define mmSYMCLKE_CLOCK_ENABLE_DEFAULT 0x00000400
+#define mmSYMCLKF_CLOCK_ENABLE_DEFAULT 0x00000500
+#define mmDVOACLKD_CNTL_DEFAULT 0x00070000
+#define mmDVOACLKC_MVP_CNTL_DEFAULT 0x00030000
+#define mmDVOACLKC_CNTL_DEFAULT 0x00030000
+#define mmDCCG_AUDIO_DTO_SOURCE_DEFAULT 0x00000030
+#define mmDCCG_AUDIO_DTO0_PHASE_DEFAULT 0x00000000
+#define mmDCCG_AUDIO_DTO0_MODULE_DEFAULT 0x00000001
+#define mmDCCG_AUDIO_DTO1_PHASE_DEFAULT 0x00000000
+#define mmDCCG_AUDIO_DTO1_MODULE_DEFAULT 0x00000001
+#define mmDCCG_TEST_CLK_SEL_DEFAULT 0x01ff01ff
+#define mmFBC_CNTL_DEFAULT 0x00000500
+#define mmFBC_IDLE_FORCE_CLEAR_MASK_DEFAULT 0x00000000
+#define mmFBC_START_STOP_DELAY_DEFAULT 0x00000000
+#define mmFBC_COMP_CNTL_DEFAULT 0x0000000f
+#define mmFBC_COMP_MODE_DEFAULT 0x00000000
+#define mmFBC_IND_LUT0_DEFAULT 0x00000000
+#define mmFBC_IND_LUT1_DEFAULT 0x00000000
+#define mmFBC_IND_LUT2_DEFAULT 0x00000000
+#define mmFBC_IND_LUT3_DEFAULT 0x00000000
+#define mmFBC_IND_LUT4_DEFAULT 0x00000000
+#define mmFBC_IND_LUT5_DEFAULT 0x00000000
+#define mmFBC_IND_LUT6_DEFAULT 0x00000000
+#define mmFBC_IND_LUT7_DEFAULT 0x00000000
+#define mmFBC_IND_LUT8_DEFAULT 0x00000000
+#define mmFBC_IND_LUT9_DEFAULT 0x00000000
+#define mmFBC_IND_LUT10_DEFAULT 0x00000000
+#define mmFBC_IND_LUT11_DEFAULT 0x00000000
+#define mmFBC_IND_LUT12_DEFAULT 0x00000000
+#define mmFBC_IND_LUT13_DEFAULT 0x00000000
+#define mmFBC_IND_LUT14_DEFAULT 0x00000000
+#define mmFBC_IND_LUT15_DEFAULT 0x00000000
+#define mmFBC_CSM_REGION_OFFSET_01_DEFAULT 0x00000000
+#define mmFBC_CSM_REGION_OFFSET_23_DEFAULT 0x00000000
+#define mmFBC_CLIENT_REGION_MASK_DEFAULT 0x00000000
+#define mmFBC_DEBUG_COMP_DEFAULT 0x00000000
+#define mmFBC_MISC_DEFAULT 0x0c306008
+#define mmFBC_STATUS_DEFAULT 0x00000000
+#define mmFBC_ALPHA_CNTL_DEFAULT 0x00000000
+#define mmFBC_ALPHA_RGB_OVERRIDE_DEFAULT 0x00000000
+#define mmPIPE0_PG_CONFIG_DEFAULT 0x00000001
+#define mmPIPE0_PG_ENABLE_DEFAULT 0x00000000
+#define mmPIPE0_PG_STATUS_DEFAULT 0x00000000
+#define mmPIPE1_PG_CONFIG_DEFAULT 0x00000001
+#define mmPIPE1_PG_ENABLE_DEFAULT 0x00000000
+#define mmPIPE1_PG_STATUS_DEFAULT 0x00000000
+#define mmPIPE2_PG_CONFIG_DEFAULT 0x00000001
+#define mmPIPE2_PG_ENABLE_DEFAULT 0x00000000
+#define mmPIPE2_PG_STATUS_DEFAULT 0x00000000
+#define mmPIPE3_PG_CONFIG_DEFAULT 0x00000001
+#define mmPIPE3_PG_ENABLE_DEFAULT 0x00000000
+#define mmPIPE3_PG_STATUS_DEFAULT 0x00000000
+#define mmPIPE4_PG_CONFIG_DEFAULT 0x00000001
+#define mmPIPE4_PG_ENABLE_DEFAULT 0x00000000
+#define mmPIPE4_PG_STATUS_DEFAULT 0x00000000
+#define mmPIPE5_PG_CONFIG_DEFAULT 0x00000001
+#define mmPIPE5_PG_ENABLE_DEFAULT 0x00000000
+#define mmPIPE5_PG_STATUS_DEFAULT 0x00000000
+#define mmDSI_PG_CONFIG_DEFAULT 0x00000001
+#define mmDSI_PG_ENABLE_DEFAULT 0x00000000
+#define mmDSI_PG_STATUS_DEFAULT 0x00000000
+#define mmDCFEV0_PG_CONFIG_DEFAULT 0x00000001
+#define mmDCFEV0_PG_ENABLE_DEFAULT 0x00000000
+#define mmDCFEV0_PG_STATUS_DEFAULT 0x00000000
+#define mmDCPG_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmDCPG_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmDCPG_INTERRUPT_CONTROL2_DEFAULT 0x00000000
+#define mmDCFEV1_PG_CONFIG_DEFAULT 0x00000001
+#define mmDCFEV1_PG_ENABLE_DEFAULT 0x00000000
+#define mmDCFEV1_PG_STATUS_DEFAULT 0x00000000
+#define mmDC_IP_REQUEST_CNTL_DEFAULT 0x00000000
+#define mmDC_PGCNTL_STATUS_REG_DEFAULT 0x00000000
+#define mmDMIFV_STATUS_DEFAULT 0x00000000
+#define mmDMIF_CONTROL_DEFAULT 0x00000c04
+#define mmDMIF_STATUS_DEFAULT 0x0ff00000
+#define mmDMIF_ARBITRATION_CONTROL_DEFAULT 0x00042710
+#define mmPIPE0_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+#define mmPIPE1_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+#define mmPIPE2_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+#define mmPIPE3_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+#define mmPIPE4_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+#define mmPIPE5_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+#define mmDMIF_P_VMID_DEFAULT 0x00000000
+#define mmDMIF_ADDR_CALC_DEFAULT 0x00000000
+#define mmDMIF_STATUS2_DEFAULT 0x00000000
+#define mmPIPE0_MAX_REQUESTS_DEFAULT 0x000003ff
+#define mmPIPE1_MAX_REQUESTS_DEFAULT 0x000003ff
+#define mmPIPE2_MAX_REQUESTS_DEFAULT 0x000003ff
+#define mmPIPE3_MAX_REQUESTS_DEFAULT 0x000003ff
+#define mmPIPE4_MAX_REQUESTS_DEFAULT 0x000003ff
+#define mmPIPE5_MAX_REQUESTS_DEFAULT 0x000003ff
+#define mmLOW_POWER_TILING_CONTROL_DEFAULT 0x00001000
+#define mmMCIF_CONTROL_DEFAULT 0x00000000
+#define mmMCIF_WRITE_COMBINE_CONTROL_DEFAULT 0x00000080
+#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000
+#define mmCC_DC_PIPE_DIS_DEFAULT 0x00000000
+#define mmSMU_WM_CONTROL_DEFAULT 0x00000000
+#define mmRBBMIF_TIMEOUT_DEFAULT 0x20000a00
+#define mmRBBMIF_STATUS_DEFAULT 0x80000000
+#define mmRBBMIF_TIMEOUT_DIS_DEFAULT 0x00000000
+#define mmDCI_MEM_PWR_STATUS_DEFAULT 0x00000000
+#define mmDCI_MEM_PWR_STATUS2_DEFAULT 0x00000000
+#define mmDCI_CLK_CNTL_DEFAULT 0x00000000
+#define mmDCI_CLK_CNTL2_DEFAULT 0x00020020
+#define mmDCI_MEM_PWR_CNTL_DEFAULT 0x00000000
+#define mmDCI_MEM_PWR_CNTL2_DEFAULT 0x00000000
+#define mmDCI_MEM_PWR_CNTL3_DEFAULT 0x00000000
+#define mmPIPE0_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000
+#define mmPIPE1_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000
+#define mmPIPE2_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000
+#define mmPIPE3_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000
+#define mmPIPE4_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000
+#define mmPIPE5_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000
+#define mmRBBMIF_STATUS_FLAG_DEFAULT 0x00000000
+#define mmDCI_SOFT_RESET_DEFAULT 0x00000000
+#define mmDMIF_URG_OVERRIDE_DEFAULT 0x00000000
+#define mmPIPE6_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+#define mmPIPE7_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+#define mmPIPE6_MAX_REQUESTS_DEFAULT 0x000003ff
+#define mmPIPE7_MAX_REQUESTS_DEFAULT 0x000003ff
+#define mmDVMM_REG_RD_STATUS_DEFAULT 0x00000000
+#define mmDVMM_REG_RD_DATA_DEFAULT 0x00000000
+#define mmDVMM_PTE_REQ_DEFAULT 0x000120ff
+#define mmDVMM_CNTL_DEFAULT 0x00000000
+#define mmDVMM_FAULT_STATUS_DEFAULT 0x00000000
+#define mmDVMM_FAULT_ADDR_DEFAULT 0x00000000
+#define mmFMON_CTRL_DEFAULT 0x0000f040
+#define mmDVMM_PTE_PGMEM_CONTROL_DEFAULT 0x00000000
+#define mmDVMM_PTE_PGMEM_STATE_DEFAULT 0x00000000
+#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000
+#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_DEFAULT 0x00000000
+#define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000
+#define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000
+#define mmDCI_MEM_PWR_CNTL4_DEFAULT 0x0000003f
+#define mmMCIF_WB_MISC_CTRL_DEFAULT 0x00010001
+#define mmDCI_MEM_PWR_STATUS3_DEFAULT 0x00000000
+#define mmDMIF_CURSOR_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_CURSOR_MEM_CONTROL_DEFAULT 0x00000000
+#define mmDCHUB_FB_LOCATION_DEFAULT 0x00000000
+#define mmDCHUB_FB_OFFSET_DEFAULT 0x00000000
+#define mmDCHUB_AGP_BASE_DEFAULT 0x00000000
+#define mmDCHUB_AGP_BOT_DEFAULT 0x00000000
+#define mmDCHUB_AGP_TOP_DEFAULT 0x00000000
+#define mmDCHUB_DRAM_APER_BASE_DEFAULT 0x00000000
+#define mmDCHUB_DRAM_APER_DEF_DEFAULT 0x00000000
+#define mmDCHUB_DRAM_APER_TOP_DEFAULT 0x00000000
+#define mmDCHUB_CONTROL_STATUS_DEFAULT 0x00c00000
+#define mmWB_ENABLE_DEFAULT 0x00000000
+#define mmWB_EC_CONFIG_DEFAULT 0x55000000
+#define mmCNV_MODE_DEFAULT 0x00000000
+#define mmCNV_WINDOW_START_DEFAULT 0x00000000
+#define mmCNV_WINDOW_SIZE_DEFAULT 0x00100010
+#define mmCNV_UPDATE_DEFAULT 0x00000000
+#define mmCNV_SOURCE_SIZE_DEFAULT 0x00100010
+#define mmCNV_CSC_CONTROL_DEFAULT 0x00000000
+#define mmCNV_CSC_C11_C12_DEFAULT 0x00000000
+#define mmCNV_CSC_C13_C14_DEFAULT 0x00000000
+#define mmCNV_CSC_C21_C22_DEFAULT 0x00000000
+#define mmCNV_CSC_C23_C24_DEFAULT 0x00000000
+#define mmCNV_CSC_C31_C32_DEFAULT 0x00000000
+#define mmCNV_CSC_C33_C34_DEFAULT 0x00000000
+#define mmCNV_CSC_ROUND_OFFSET_R_DEFAULT 0x00000000
+#define mmCNV_CSC_ROUND_OFFSET_G_DEFAULT 0x00000000
+#define mmCNV_CSC_ROUND_OFFSET_B_DEFAULT 0x00000000
+#define mmCNV_CSC_CLAMP_R_DEFAULT 0x00000fff
+#define mmCNV_CSC_CLAMP_G_DEFAULT 0x00000fff
+#define mmCNV_CSC_CLAMP_B_DEFAULT 0x00000fff
+#define mmCNV_TEST_CNTL_DEFAULT 0x00000000
+#define mmCNV_TEST_CRC_RED_DEFAULT 0x0000fff0
+#define mmCNV_TEST_CRC_GREEN_DEFAULT 0x0000fff0
+#define mmCNV_TEST_CRC_BLUE_DEFAULT 0x0000fff0
+#define mmCNV_INPUT_SELECT_DEFAULT 0x00000000
+#define mmWB_SOFT_RESET_DEFAULT 0x00000000
+#define mmWB_WARM_UP_MODE_CTL1_DEFAULT 0x88700100
+#define mmWB_WARM_UP_MODE_CTL2_DEFAULT 0x00000100
+#define mmWBSCL_COEF_RAM_SELECT_DEFAULT 0x00000000
+#define mmWBSCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
+#define mmWBSCL_MODE_DEFAULT 0x00000000
+#define mmWBSCL_TAP_CONTROL_DEFAULT 0x00001111
+#define mmWBSCL_DEST_SIZE_DEFAULT 0x00010001
+#define mmWBSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00080000
+#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_DEFAULT 0x01000000
+#define mmWBSCL_HORZ_FILTER_INIT_CBCR_DEFAULT 0x01000000
+#define mmWBSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00080000
+#define mmWBSCL_VERT_FILTER_INIT_Y_RGB_DEFAULT 0x01000000
+#define mmWBSCL_VERT_FILTER_INIT_CBCR_DEFAULT 0x01000000
+#define mmWBSCL_ROUND_OFFSET_DEFAULT 0x00800010
+#define mmWBSCL_CLAMP_DEFAULT 0x01fe01fe
+#define mmWBSCL_OVERFLOW_STATUS_DEFAULT 0x00000000
+#define mmWBSCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
+#define mmWBSCL_OUTSIDE_PIX_STRATEGY_DEFAULT 0x80108000
+#define mmWBSCL_TEST_CNTL_DEFAULT 0x00000000
+#define mmWBSCL_TEST_CRC_RED_DEFAULT 0x0000ff00
+#define mmWBSCL_TEST_CRC_GREEN_DEFAULT 0x0000ffff
+#define mmWBSCL_TEST_CRC_BLUE_DEFAULT 0x0000ff00
+#define mmWBSCL_BACKPRESSURE_CNT_EN_DEFAULT 0x00000000
+#define mmWB_MCIF_BACKPRESSURE_CNT_DEFAULT 0x00000000
+#define mmWBSCL_RAM_SHUTDOWN_DEFAULT 0x00000000
+#define mmDMCU_CTRL_DEFAULT 0xffff0101
+#define mmDMCU_STATUS_DEFAULT 0x00000001
+#define mmDMCU_PC_START_ADDR_DEFAULT 0x00000000
+#define mmDMCU_FW_START_ADDR_DEFAULT 0x00000000
+#define mmDMCU_FW_END_ADDR_DEFAULT 0x00000000
+#define mmDMCU_FW_ISR_START_ADDR_DEFAULT 0x00000004
+#define mmDMCU_FW_CS_HI_DEFAULT 0x00000000
+#define mmDMCU_FW_CS_LO_DEFAULT 0x00000000
+#define mmDMCU_RAM_ACCESS_CTRL_DEFAULT 0x00000000
+#define mmDMCU_ERAM_WR_CTRL_DEFAULT 0x000f0000
+#define mmDMCU_ERAM_WR_DATA_DEFAULT 0x00000000
+#define mmDMCU_ERAM_RD_CTRL_DEFAULT 0x000f0000
+#define mmDMCU_ERAM_RD_DATA_DEFAULT 0x00000000
+#define mmDMCU_IRAM_WR_CTRL_DEFAULT 0x00000000
+#define mmDMCU_IRAM_WR_DATA_DEFAULT 0x00000000
+#define mmDMCU_IRAM_RD_CTRL_DEFAULT 0x00000000
+#define mmDMCU_IRAM_RD_DATA_DEFAULT 0x00000000
+#define mmDMCU_EVENT_TRIGGER_DEFAULT 0x00000000
+#define mmDMCU_UC_INTERNAL_INT_STATUS_DEFAULT 0x00000000
+#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_DEFAULT 0x00000000
+#define mmDMCU_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_DEFAULT 0x00000000
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_DEFAULT 0x00000000
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_DEFAULT 0x00000000
+#define mmDC_DMCU_SCRATCH_DEFAULT 0x00000000
+#define mmDMCU_INT_CNT_DEFAULT 0x00000000
+#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_DEFAULT 0x00000000
+#define mmDMCU_UC_CLK_GATING_CNTL_DEFAULT 0x00010102
+#define mmMASTER_COMM_DATA_REG1_DEFAULT 0x00000000
+#define mmMASTER_COMM_DATA_REG2_DEFAULT 0x00000000
+#define mmMASTER_COMM_DATA_REG3_DEFAULT 0x00000000
+#define mmMASTER_COMM_CMD_REG_DEFAULT 0x00000000
+#define mmMASTER_COMM_CNTL_REG_DEFAULT 0x00000000
+#define mmSLAVE_COMM_DATA_REG1_DEFAULT 0x00000000
+#define mmSLAVE_COMM_DATA_REG2_DEFAULT 0x00000000
+#define mmSLAVE_COMM_DATA_REG3_DEFAULT 0x00000000
+#define mmSLAVE_COMM_CMD_REG_DEFAULT 0x00000000
+#define mmSLAVE_COMM_CNTL_REG_DEFAULT 0x00000000
+#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_DEFAULT 0x00000000
+#define mmBL1_PWM_USER_LEVEL_DEFAULT 0x00000000
+#define mmBL1_PWM_TARGET_ABM_LEVEL_DEFAULT 0x00000000
+#define mmBL1_PWM_CURRENT_ABM_LEVEL_DEFAULT 0x00000000
+#define mmBL1_PWM_FINAL_DUTY_CYCLE_DEFAULT 0x00000000
+#define mmBL1_PWM_MINIMUM_DUTY_CYCLE_DEFAULT 0x00000000
+#define mmBL1_PWM_ABM_CNTL_DEFAULT 0x00000000
+#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_DEFAULT 0x00000000
+#define mmBL1_PWM_GRP2_REG_LOCK_DEFAULT 0x00000000
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_DEFAULT 0x00000000
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_DEFAULT 0x00000000
+#define mmDMCU_INTERRUPT_STATUS_1_DEFAULT 0x00000000
+#define mmDMCU_DPRX_INTERRUPT_STATUS1_DEFAULT 0x00000000
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_DEFAULT 0x00000000
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_DEFAULT 0x00000000
+#define mmDC_ABM1_CNTL_DEFAULT 0x00000000
+#define mmDC_ABM1_IPCSC_COEFF_SEL_DEFAULT 0x00000000
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_0_DEFAULT 0x00000400
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_1_DEFAULT 0x00000400
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_2_DEFAULT 0x00000400
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_3_DEFAULT 0x00000400
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_4_DEFAULT 0x00000400
+#define mmDC_ABM1_ACE_THRES_12_DEFAULT 0x00000000
+#define mmDC_ABM1_ACE_THRES_34_DEFAULT 0x00000000
+#define mmDC_ABM1_ACE_CNTL_MISC_DEFAULT 0x00000000
+#define mmDMCU_PERFMON_INTERRUPT_STATUS5_DEFAULT 0x00000000
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_DEFAULT 0x00000000
+#define mmDMCU_PERFMON_INTERRUPT_STATUS1_DEFAULT 0x00000000
+#define mmDMCU_PERFMON_INTERRUPT_STATUS2_DEFAULT 0x00000000
+#define mmDMCU_PERFMON_INTERRUPT_STATUS3_DEFAULT 0x00000000
+#define mmDMCU_PERFMON_INTERRUPT_STATUS4_DEFAULT 0x00000000
+#define mmDC_ABM1_HGLS_REG_READ_PROGRESS_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_MISC_CTRL_DEFAULT 0x00000000
+#define mmDC_ABM1_LS_SUM_OF_LUMA_DEFAULT 0x00000000
+#define mmDC_ABM1_LS_MIN_MAX_LUMA_DEFAULT 0x00000000
+#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_DEFAULT 0x00000000
+#define mmDC_ABM1_LS_PIXEL_COUNT_DEFAULT 0x00000000
+#define mmDC_ABM1_LS_OVR_SCAN_BIN_DEFAULT 0x00000000
+#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_DEFAULT 0x00000000
+#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_DEFAULT 0x00000000
+#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_SAMPLE_RATE_DEFAULT 0x00000000
+#define mmDC_ABM1_LS_SAMPLE_RATE_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_1_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_2_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_3_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_4_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_5_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_6_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_7_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_8_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_9_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_10_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_11_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_12_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_13_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_14_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_15_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_16_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_17_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_18_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_19_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_20_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_21_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_22_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_23_DEFAULT 0x00000000
+#define mmDC_ABM1_HG_RESULT_24_DEFAULT 0x00000000
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_DEFAULT 0x00000000
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_DEFAULT 0x00000000
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_DEFAULT 0x00000000
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_DEFAULT 0x00000000
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_DEFAULT 0x00000000
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_DEFAULT 0x00000000
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_DEFAULT 0x00000000
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_DEFAULT 0x00000000
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_DEFAULT 0x00000000
+#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE_DEFAULT 0x00000000
+#define mmDC_ABM1_BL_MASTER_LOCK_DEFAULT 0x00000000
+#define mmAZALIA_CONTROLLER_CLOCK_GATING_DEFAULT 0x00000000
+#define mmAZALIA_AUDIO_DTO_DEFAULT 0x001b0018
+#define mmAZALIA_AUDIO_DTO_CONTROL_DEFAULT 0x00000000
+#define mmAZALIA_SOCCLK_CONTROL_DEFAULT 0x00000001
+#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_DEFAULT 0x00000000
+#define mmAZALIA_DATA_DMA_CONTROL_DEFAULT 0x0000000a
+#define mmAZALIA_BDL_DMA_CONTROL_DEFAULT 0x0000000a
+#define mmAZALIA_RIRB_AND_DP_CONTROL_DEFAULT 0x00000000
+#define mmAZALIA_CORB_DMA_CONTROL_DEFAULT 0x00000000
+#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_DEFAULT 0x00000000
+#define mmAZALIA_CYCLIC_BUFFER_SYNC_DEFAULT 0x00000000
+#define mmAZALIA_GLOBAL_CAPABILITIES_DEFAULT 0x00000000
+#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000060
+#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_DEFAULT 0x00080008
+#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000080
+#define mmAZALIA_INPUT_CRC0_CONTROL0_DEFAULT 0x00000000
+#define mmAZALIA_INPUT_CRC0_CONTROL1_DEFAULT 0x00000000
+#define mmAZALIA_INPUT_CRC0_CONTROL2_DEFAULT 0x00000000
+#define mmAZALIA_INPUT_CRC0_CONTROL3_DEFAULT 0x00000000
+#define mmAZALIA_INPUT_CRC0_RESULT_DEFAULT 0x00000000
+#define mmAZALIA_INPUT_CRC1_CONTROL0_DEFAULT 0x00000000
+#define mmAZALIA_INPUT_CRC1_CONTROL1_DEFAULT 0x00000000
+#define mmAZALIA_INPUT_CRC1_CONTROL2_DEFAULT 0x00000000
+#define mmAZALIA_INPUT_CRC1_CONTROL3_DEFAULT 0x00000000
+#define mmAZALIA_INPUT_CRC1_RESULT_DEFAULT 0x00000000
+#define mmAZALIA_CRC0_CONTROL0_DEFAULT 0x00000000
+#define mmAZALIA_CRC0_CONTROL1_DEFAULT 0x00000000
+#define mmAZALIA_CRC0_CONTROL2_DEFAULT 0x00000000
+#define mmAZALIA_CRC0_CONTROL3_DEFAULT 0x00000000
+#define mmAZALIA_CRC0_RESULT_DEFAULT 0x00000000
+#define mmAZALIA_CRC1_CONTROL0_DEFAULT 0x00000000
+#define mmAZALIA_CRC1_CONTROL1_DEFAULT 0x00000000
+#define mmAZALIA_CRC1_CONTROL2_DEFAULT 0x00000000
+#define mmAZALIA_CRC1_CONTROL3_DEFAULT 0x00000000
+#define mmAZALIA_CRC1_RESULT_DEFAULT 0x00000000
+#define mmAZALIA_MEM_PWR_CTRL_DEFAULT 0x00000000
+#define mmAZALIA_MEM_PWR_STATUS_DEFAULT 0x00000000
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_DEFAULT 0x1002aa01
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_DEFAULT 0x00100700
+#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_DEFAULT 0x00000000
+#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_DEFAULT 0x0000000d
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_DEFAULT 0x00000001
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_DEFAULT 0xc0000009
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_DEFAULT 0x00000200
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_DEFAULT 0x00000000
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_DEFAULT 0x00aa0100
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_DEFAULT 0x00000000
+#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_DEFAULT 0x00000000
+#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_DEFAULT 0x00000000
+#define mmAZALIA_F0_GTC_GROUP_OFFSET0_DEFAULT 0x00000000
+#define mmAZALIA_F0_GTC_GROUP_OFFSET1_DEFAULT 0x00000000
+#define mmAZALIA_F0_GTC_GROUP_OFFSET2_DEFAULT 0x00000000
+#define mmAZALIA_F0_GTC_GROUP_OFFSET3_DEFAULT 0x00000000
+#define mmAZALIA_F0_GTC_GROUP_OFFSET4_DEFAULT 0x00000000
+#define mmAZALIA_F0_GTC_GROUP_OFFSET5_DEFAULT 0x00000000
+#define mmAZALIA_F0_GTC_GROUP_OFFSET6_DEFAULT 0x00000000
+#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_DEFAULT 0x00000000
+#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_DEFAULT 0x00000000
+#define mmDAC_ENABLE_DEFAULT 0x00000004
+#define mmDAC_SOURCE_SELECT_DEFAULT 0x00000000
+#define mmDAC_CRC_EN_DEFAULT 0x00000000
+#define mmDAC_CRC_CONTROL_DEFAULT 0x00000000
+#define mmDAC_CRC_SIG_RGB_MASK_DEFAULT 0x3fffffff
+#define mmDAC_CRC_SIG_CONTROL_MASK_DEFAULT 0x0000003f
+#define mmDAC_CRC_SIG_RGB_DEFAULT 0x3fffffff
+#define mmDAC_CRC_SIG_CONTROL_DEFAULT 0x0000003f
+#define mmDAC_SYNC_TRISTATE_CONTROL_DEFAULT 0x00000000
+#define mmDAC_STEREOSYNC_SELECT_DEFAULT 0x00000000
+#define mmDAC_AUTODETECT_CONTROL_DEFAULT 0x00070000
+#define mmDAC_AUTODETECT_CONTROL2_DEFAULT 0x0000000b
+#define mmDAC_AUTODETECT_CONTROL3_DEFAULT 0x00000519
+#define mmDAC_AUTODETECT_STATUS_DEFAULT 0x00000000
+#define mmDAC_AUTODETECT_INT_CONTROL_DEFAULT 0x00000000
+#define mmDAC_FORCE_OUTPUT_CNTL_DEFAULT 0x00000000
+#define mmDAC_FORCE_DATA_DEFAULT 0x000001e6
+#define mmDAC_POWERDOWN_DEFAULT 0x01010100
+#define mmDAC_CONTROL_DEFAULT 0x00000000
+#define mmDAC_COMPARATOR_ENABLE_DEFAULT 0x00000000
+#define mmDAC_COMPARATOR_OUTPUT_DEFAULT 0x00000000
+#define mmDAC_PWR_CNTL_DEFAULT 0x00000000
+#define mmDAC_DFT_CONFIG_DEFAULT 0x00000000
+#define mmDAC_FIFO_STATUS_DEFAULT 0x00000000
+#define mmDC_I2C_CONTROL_DEFAULT 0x00000000
+#define mmDC_I2C_ARBITRATION_DEFAULT 0x00000001
+#define mmDC_I2C_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmDC_I2C_SW_STATUS_DEFAULT 0x00000000
+#define mmDC_I2C_DDC1_HW_STATUS_DEFAULT 0x00000000
+#define mmDC_I2C_DDC2_HW_STATUS_DEFAULT 0x00000000
+#define mmDC_I2C_DDC3_HW_STATUS_DEFAULT 0x00000000
+#define mmDC_I2C_DDC4_HW_STATUS_DEFAULT 0x00000000
+#define mmDC_I2C_DDC5_HW_STATUS_DEFAULT 0x00000000
+#define mmDC_I2C_DDC6_HW_STATUS_DEFAULT 0x00000000
+#define mmDC_I2C_DDC1_SPEED_DEFAULT 0x00000002
+#define mmDC_I2C_DDC1_SETUP_DEFAULT 0x00000000
+#define mmDC_I2C_DDC2_SPEED_DEFAULT 0x00000002
+#define mmDC_I2C_DDC2_SETUP_DEFAULT 0x00000000
+#define mmDC_I2C_DDC3_SPEED_DEFAULT 0x00000002
+#define mmDC_I2C_DDC3_SETUP_DEFAULT 0x00000000
+#define mmDC_I2C_DDC4_SPEED_DEFAULT 0x00000002
+#define mmDC_I2C_DDC4_SETUP_DEFAULT 0x00000000
+#define mmDC_I2C_DDC5_SPEED_DEFAULT 0x00000002
+#define mmDC_I2C_DDC5_SETUP_DEFAULT 0x00000000
+#define mmDC_I2C_DDC6_SPEED_DEFAULT 0x00000002
+#define mmDC_I2C_DDC6_SETUP_DEFAULT 0x00000000
+#define mmDC_I2C_TRANSACTION0_DEFAULT 0x00000000
+#define mmDC_I2C_TRANSACTION1_DEFAULT 0x00000000
+#define mmDC_I2C_TRANSACTION2_DEFAULT 0x00000000
+#define mmDC_I2C_TRANSACTION3_DEFAULT 0x00000000
+#define mmDC_I2C_DATA_DEFAULT 0x00000000
+#define mmDC_I2C_DDCVGA_HW_STATUS_DEFAULT 0x00000000
+#define mmDC_I2C_DDCVGA_SPEED_DEFAULT 0x00000002
+#define mmDC_I2C_DDCVGA_SETUP_DEFAULT 0x00000000
+#define mmDC_I2C_EDID_DETECT_CTRL_DEFAULT 0x004001f4
+#define mmDC_I2C_READ_REQUEST_INTERRUPT_DEFAULT 0x40000000
+#define mmGENERIC_I2C_CONTROL_DEFAULT 0x00000000
+#define mmGENERIC_I2C_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmGENERIC_I2C_STATUS_DEFAULT 0x00000000
+#define mmGENERIC_I2C_SPEED_DEFAULT 0x00000002
+#define mmGENERIC_I2C_SETUP_DEFAULT 0x00000000
+#define mmGENERIC_I2C_TRANSACTION_DEFAULT 0x00000000
+#define mmGENERIC_I2C_DATA_DEFAULT 0x00000000
+#define mmGENERIC_I2C_PIN_SELECTION_DEFAULT 0x00000000
+#define mmDCO_SCRATCH0_DEFAULT 0x00000000
+#define mmDCO_SCRATCH1_DEFAULT 0x00000000
+#define mmDCO_SCRATCH2_DEFAULT 0x00000000
+#define mmDCO_SCRATCH3_DEFAULT 0x00000000
+#define mmDCO_SCRATCH4_DEFAULT 0x00000000
+#define mmDCO_SCRATCH5_DEFAULT 0x00000000
+#define mmDCO_SCRATCH6_DEFAULT 0x00000000
+#define mmDCO_SCRATCH7_DEFAULT 0x00000000
+#define mmDCE_VCE_CONTROL_DEFAULT 0x00000000
+#define mmDISP_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmDISP_INTERRUPT_STATUS_CONTINUE_DEFAULT 0x00000000
+#define mmDISP_INTERRUPT_STATUS_CONTINUE2_DEFAULT 0x00000000
+#define mmDISP_INTERRUPT_STATUS_CONTINUE3_DEFAULT 0x00000000
+#define mmDISP_INTERRUPT_STATUS_CONTINUE4_DEFAULT 0x00000000
+#define mmDISP_INTERRUPT_STATUS_CONTINUE5_DEFAULT 0x00000000
+#define mmDISP_INTERRUPT_STATUS_CONTINUE6_DEFAULT 0x00000000
+#define mmDISP_INTERRUPT_STATUS_CONTINUE7_DEFAULT 0x00000000
+#define mmDISP_INTERRUPT_STATUS_CONTINUE8_DEFAULT 0x00000000
+#define mmDISP_INTERRUPT_STATUS_CONTINUE9_DEFAULT 0x00000000
+#define mmDCO_MEM_PWR_STATUS_DEFAULT 0x00000000
+#define mmDCO_MEM_PWR_CTRL_DEFAULT 0x6db6d800
+#define mmDCO_MEM_PWR_CTRL2_DEFAULT 0x001b0000
+#define mmDCO_CLK_CNTL_DEFAULT 0x00000000
+#define mmDCO_POWER_MANAGEMENT_CNTL_DEFAULT 0x00000000
+#define mmDIG_SOFT_RESET_2_DEFAULT 0x00000000
+#define mmDCO_STEREOSYNC_SEL_DEFAULT 0x00000000
+#define mmDCO_SOFT_RESET_DEFAULT 0x00000000
+#define mmDIG_SOFT_RESET_DEFAULT 0x00000000
+#define mmDCO_MEM_PWR_STATUS1_DEFAULT 0x00000000
+#define mmDISP_INTERRUPT_STATUS_CONTINUE10_DEFAULT 0x00000000
+#define mmDCO_CLK_CNTL2_DEFAULT 0x00000000
+#define mmDCO_CLK_CNTL3_DEFAULT 0x00000000
+#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL_DEFAULT 0x00000000
+#define mmDCO_PSP_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmDCO_PSP_INTERRUPT_CLEAR_DEFAULT 0x00000000
+#define mmDCO_GENERIC_INTERRUPT_MESSAGE_DEFAULT 0x00000000
+#define mmDCO_GENERIC_INTERRUPT_CLEAR_DEFAULT 0x00000000
+#define mmFMT_MEMORY0_CONTROL_DEFAULT 0x00000030
+#define mmFMT_MEMORY1_CONTROL_DEFAULT 0x00000031
+#define mmFMT_MEMORY2_CONTROL_DEFAULT 0x00000032
+#define mmFMT_MEMORY3_CONTROL_DEFAULT 0x00000033
+#define mmFMT_MEMORY4_CONTROL_DEFAULT 0x00000034
+#define mmFMT_MEMORY5_CONTROL_DEFAULT 0x00000035
+#define mmDISP_INTERRUPT_STATUS_CONTINUE11_DEFAULT 0x00000000
+#define mmDC_GENERICA_DEFAULT 0x00000000
+#define mmDC_GENERICB_DEFAULT 0x00000000
+#define mmDC_PAD_EXTERN_SIG_DEFAULT 0x00000000
+#define mmDC_REF_CLK_CNTL_DEFAULT 0x00000000
+#define mmDC_GPIO_DEBUG_DEFAULT 0x00000101
+#define mmUNIPHYA_LINK_CNTL_DEFAULT 0x01100100
+#define mmUNIPHYA_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
+#define mmUNIPHYB_LINK_CNTL_DEFAULT 0x01100100
+#define mmUNIPHYB_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
+#define mmUNIPHYC_LINK_CNTL_DEFAULT 0x01100100
+#define mmUNIPHYC_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
+#define mmUNIPHYD_LINK_CNTL_DEFAULT 0x01100100
+#define mmUNIPHYD_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
+#define mmUNIPHYE_LINK_CNTL_DEFAULT 0x01100100
+#define mmUNIPHYE_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
+#define mmUNIPHYF_LINK_CNTL_DEFAULT 0x01100100
+#define mmUNIPHYF_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
+#define mmUNIPHYG_LINK_CNTL_DEFAULT 0x01100100
+#define mmUNIPHYG_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
+#define mmDCIO_WRCMD_DELAY_DEFAULT 0x00033333
+#define mmDC_DVODATA_CONFIG_DEFAULT 0x00000000
+#define mmLVTMA_PWRSEQ_CNTL_DEFAULT 0x00000000
+#define mmLVTMA_PWRSEQ_STATE_DEFAULT 0x00000000
+#define mmLVTMA_PWRSEQ_REF_DIV_DEFAULT 0x00010000
+#define mmLVTMA_PWRSEQ_DELAY1_DEFAULT 0x00000000
+#define mmLVTMA_PWRSEQ_DELAY2_DEFAULT 0x00000000
+#define mmBL_PWM_CNTL_DEFAULT 0x00000000
+#define mmBL_PWM_CNTL2_DEFAULT 0x00000000
+#define mmBL_PWM_PERIOD_CNTL_DEFAULT 0x00000001
+#define mmBL_PWM_GRP1_REG_LOCK_DEFAULT 0x00000000
+#define mmDCIO_GSL_GENLK_PAD_CNTL_DEFAULT 0x00000000
+#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_DEFAULT 0x00000000
+#define mmDCIO_GSL0_CNTL_DEFAULT 0x00000000
+#define mmDCIO_GSL1_CNTL_DEFAULT 0x00000000
+#define mmDCIO_GSL2_CNTL_DEFAULT 0x00000000
+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_DEFAULT 0x00000000
+#define mmDC_GPU_TIMER_START_POSITION_P_FLIP_DEFAULT 0x00000000
+#define mmDC_GPU_TIMER_READ_DEFAULT 0x00000000
+#define mmDC_GPU_TIMER_READ_CNTL_DEFAULT 0x00000000
+#define mmDCIO_CLOCK_CNTL_DEFAULT 0x00000000
+#define mmDCO_DCFE_EXT_VSYNC_CNTL_DEFAULT 0x00000000
+#define mmDCIO_SOFT_RESET_DEFAULT 0x00000000
+#define mmDCIO_DPHY_SEL_DEFAULT 0x000000e4
+#define mmUNIPHY_IMPCAL_LINKA_DEFAULT 0x0f000000
+#define mmUNIPHY_IMPCAL_LINKB_DEFAULT 0x0f000000
+#define mmUNIPHY_IMPCAL_PERIOD_DEFAULT 0x00000000
+#define mmAUXP_IMPCAL_DEFAULT 0x0a000000
+#define mmAUXN_IMPCAL_DEFAULT 0x04000000
+#define mmDCIO_IMPCAL_CNTL_DEFAULT 0x00000000
+#define mmUNIPHY_IMPCAL_PSW_AB_DEFAULT 0x00000000
+#define mmUNIPHY_IMPCAL_LINKC_DEFAULT 0x0f000000
+#define mmUNIPHY_IMPCAL_LINKD_DEFAULT 0x0f000000
+#define mmDCIO_IMPCAL_CNTL_CD_DEFAULT 0x00000000
+#define mmUNIPHY_IMPCAL_PSW_CD_DEFAULT 0x00000000
+#define mmUNIPHY_IMPCAL_LINKE_DEFAULT 0x0f000000
+#define mmUNIPHY_IMPCAL_LINKF_DEFAULT 0x0f000000
+#define mmDCIO_IMPCAL_CNTL_EF_DEFAULT 0x00000000
+#define mmUNIPHY_IMPCAL_PSW_EF_DEFAULT 0x00000000
+#define mmUNIPHYLPA_LINK_CNTL_DEFAULT 0x01100100
+#define mmUNIPHYLPB_LINK_CNTL_DEFAULT 0x01100100
+#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
+#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100
+#define mmDCIO_DPCS_TX_INTERRUPT_DEFAULT 0x00000000
+#define mmDCIO_DPCS_RX_INTERRUPT_DEFAULT 0x00000000
+#define mmDCIO_SEMAPHORE0_DEFAULT 0x00000000
+#define mmDCIO_SEMAPHORE1_DEFAULT 0x00000000
+#define mmDCIO_SEMAPHORE2_DEFAULT 0x00000000
+#define mmDCIO_SEMAPHORE3_DEFAULT 0x00000000
+#define mmDCIO_SEMAPHORE4_DEFAULT 0x00000000
+#define mmDCIO_SEMAPHORE5_DEFAULT 0x00000000
+#define mmDCIO_SEMAPHORE6_DEFAULT 0x00000000
+#define mmDCIO_SEMAPHORE7_DEFAULT 0x00000000
+#define mmDC_GPIO_GENERIC_MASK_DEFAULT 0x04444444
+#define mmDC_GPIO_GENERIC_A_DEFAULT 0x00000000
+#define mmDC_GPIO_GENERIC_EN_DEFAULT 0x00000000
+#define mmDC_GPIO_GENERIC_Y_DEFAULT 0x00000000
+#define mmDC_GPIO_DVODATA_MASK_DEFAULT 0x00000000
+#define mmDC_GPIO_DVODATA_A_DEFAULT 0x00000000
+#define mmDC_GPIO_DVODATA_EN_DEFAULT 0x00000000
+#define mmDC_GPIO_DVODATA_Y_DEFAULT 0x00000000
+#define mmDC_GPIO_DDC1_MASK_DEFAULT 0xcf400000
+#define mmDC_GPIO_DDC1_A_DEFAULT 0x00000000
+#define mmDC_GPIO_DDC1_EN_DEFAULT 0x00000000
+#define mmDC_GPIO_DDC1_Y_DEFAULT 0x00000000
+#define mmDC_GPIO_DDC2_MASK_DEFAULT 0xcf400000
+#define mmDC_GPIO_DDC2_A_DEFAULT 0x00000000
+#define mmDC_GPIO_DDC2_EN_DEFAULT 0x00000000
+#define mmDC_GPIO_DDC2_Y_DEFAULT 0x00000000
+#define mmDC_GPIO_DDC3_MASK_DEFAULT 0xcf400000
+#define mmDC_GPIO_DDC3_A_DEFAULT 0x00000000
+#define mmDC_GPIO_DDC3_EN_DEFAULT 0x00000000
+#define mmDC_GPIO_DDC3_Y_DEFAULT 0x00000000
+#define mmDC_GPIO_DDC4_MASK_DEFAULT 0xcf400000
+#define mmDC_GPIO_DDC4_A_DEFAULT 0x00000000
+#define mmDC_GPIO_DDC4_EN_DEFAULT 0x00000000
+#define mmDC_GPIO_DDC4_Y_DEFAULT 0x00000000
+#define mmDC_GPIO_DDC5_MASK_DEFAULT 0xcf400000
+#define mmDC_GPIO_DDC5_A_DEFAULT 0x00000000
+#define mmDC_GPIO_DDC5_EN_DEFAULT 0x00000000
+#define mmDC_GPIO_DDC5_Y_DEFAULT 0x00000000
+#define mmDC_GPIO_DDC6_MASK_DEFAULT 0xcf400000
+#define mmDC_GPIO_DDC6_A_DEFAULT 0x00000000
+#define mmDC_GPIO_DDC6_EN_DEFAULT 0x00000000
+#define mmDC_GPIO_DDC6_Y_DEFAULT 0x00000000
+#define mmDC_GPIO_DDCVGA_MASK_DEFAULT 0xcf400000
+#define mmDC_GPIO_DDCVGA_A_DEFAULT 0x00000000
+#define mmDC_GPIO_DDCVGA_EN_DEFAULT 0x00000000
+#define mmDC_GPIO_DDCVGA_Y_DEFAULT 0x00000000
+#define mmDC_GPIO_SYNCA_MASK_DEFAULT 0x00004040
+#define mmDC_GPIO_SYNCA_A_DEFAULT 0x00000000
+#define mmDC_GPIO_SYNCA_EN_DEFAULT 0x00000000
+#define mmDC_GPIO_SYNCA_Y_DEFAULT 0x00000000
+#define mmDC_GPIO_GENLK_MASK_DEFAULT 0x10101a10
+#define mmDC_GPIO_GENLK_A_DEFAULT 0x00000000
+#define mmDC_GPIO_GENLK_EN_DEFAULT 0x00000000
+#define mmDC_GPIO_GENLK_Y_DEFAULT 0x00000000
+#define mmDC_GPIO_HPD_MASK_DEFAULT 0x44440440
+#define mmDC_GPIO_HPD_A_DEFAULT 0x00000000
+#define mmDC_GPIO_HPD_EN_DEFAULT 0x22220202
+#define mmDC_GPIO_HPD_Y_DEFAULT 0x00000000
+#define mmDC_GPIO_PWRSEQ_MASK_DEFAULT 0x66404040
+#define mmDC_GPIO_PWRSEQ_A_DEFAULT 0x00000000
+#define mmDC_GPIO_PWRSEQ_EN_DEFAULT 0x00000000
+#define mmDC_GPIO_PWRSEQ_Y_DEFAULT 0x00000000
+#define mmDC_GPIO_PAD_STRENGTH_1_DEFAULT 0x47ac470f
+#define mmDC_GPIO_PAD_STRENGTH_2_DEFAULT 0x00472147
+#define mmPHY_AUX_CNTL_DEFAULT 0x00010001
+#define mmDC_GPIO_I2CPAD_MASK_DEFAULT 0x00000000
+#define mmDC_GPIO_I2CPAD_A_DEFAULT 0x00000000
+#define mmDC_GPIO_I2CPAD_EN_DEFAULT 0x00000000
+#define mmDC_GPIO_I2CPAD_Y_DEFAULT 0x00000000
+#define mmDC_GPIO_I2CPAD_STRENGTH_DEFAULT 0x0000004c
+#define mmDVO_STRENGTH_CONTROL_DEFAULT 0x31116060
+#define mmDVO_VREF_CONTROL_DEFAULT 0x00000000
+#define mmDVO_SKEW_ADJUST_DEFAULT 0x00000000
+#define mmDC_GPIO_I2S_SPDIF_MASK_DEFAULT 0x00000000
+#define mmDC_GPIO_I2S_SPDIF_A_DEFAULT 0x00000000
+#define mmDC_GPIO_I2S_SPDIF_EN_DEFAULT 0x00008000
+#define mmDC_GPIO_I2S_SPDIF_Y_DEFAULT 0x00000000
+#define mmDC_GPIO_I2S_SPDIF_STRENGTH_DEFAULT 0x01021202
+#define mmDC_GPIO_TX12_EN_DEFAULT 0x00000000
+#define mmDC_GPIO_AUX_CTRL_0_DEFAULT 0x00000000
+#define mmDC_GPIO_AUX_CTRL_1_DEFAULT 0x00500000
+#define mmDC_GPIO_AUX_CTRL_2_DEFAULT 0x00000000
+#define mmDC_GPIO_RXEN_DEFAULT 0x007fff7f
+#define mmBPHYC_DAC_MACRO_CNTL_DEFAULT 0x00202002
+#define mmDAC_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+#define mmBPHYC_DAC_AUTO_CALIB_CONTROL_DEFAULT 0x00700255
+#define mmDAC_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+#define mmDAC_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+#define mmDAC_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+#define mmDISP_DSI_DUAL_CTRL_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
+#define mmDPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
+#define mmDPRX_AUX_REFERENCE_PULSE_DIV_DEFAULT 0x0a640064
+#define mmDPRX_AUX_CONTROL_DEFAULT 0x01012c00
+#define mmDPRX_AUX_HPD_CONTROL1_DEFAULT 0x00001407
+#define mmDPRX_AUX_HPD_CONTROL2_DEFAULT 0x00000000
+#define mmDPRX_AUX_RX_STATUS_DEFAULT 0x00000000
+#define mmDPRX_AUX_RX_ERROR_MASK_DEFAULT 0x00000000
+#define mmDPRX_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
+#define mmDPRX_AUX_DPHY_TX_CONTROL_DEFAULT 0x00001002
+#define mmDPRX_AUX_DPHY_RX_CONTROL0_DEFAULT 0x203d1210
+#define mmDPRX_AUX_DPHY_RX_CONTROL1_DEFAULT 0x0a00fa00
+#define mmDPRX_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
+#define mmDPRX_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
+#define mmDPRX_AUX_DMCU_HW_INT_STATUS_DEFAULT 0x00003f00
+#define mmDPRX_AUX_DMCU_HW_INT_ACK_DEFAULT 0x00000000
+#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1_DEFAULT 0x00000000
+#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2_DEFAULT 0x00000001
+#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1_DEFAULT 0x00000000
+#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2_DEFAULT 0x00000000
+#define mmDPRX_AUX_AUX_BUF_INDEX_DEFAULT 0x00000000
+#define mmDPRX_AUX_AUX_BUF_DATA_DEFAULT 0x00000000
+#define mmDPRX_AUX_EDID_INDEX_DEFAULT 0x00000000
+#define mmDPRX_AUX_EDID_DATA_DEFAULT 0x00000000
+#define mmDPRX_AUX_DPCD_INDEX1_DEFAULT 0x00000000
+#define mmDPRX_AUX_DPCD_DATA1_DEFAULT 0x00000000
+#define mmDPRX_AUX_DPCD_INDEX2_DEFAULT 0x00000000
+#define mmDPRX_AUX_DPCD_DATA2_DEFAULT 0x00000000
+#define mmDPRX_AUX_MSG_INDEX1_DEFAULT 0x00000000
+#define mmDPRX_AUX_MSG_DATA1_DEFAULT 0x00000000
+#define mmDPRX_AUX_MSG_INDEX2_DEFAULT 0x00000000
+#define mmDPRX_AUX_MSG_DATA2_DEFAULT 0x00000000
+#define mmDPRX_AUX_KSV_INDEX1_DEFAULT 0x00000000
+#define mmDPRX_AUX_KSV_DATA1_DEFAULT 0x00000000
+#define mmDPRX_AUX_KSV_INDEX2_DEFAULT 0x00000000
+#define mmDPRX_AUX_KSV_DATA2_DEFAULT 0x00000000
+#define mmDPRX_AUX_MSG_TIMEOUT_CONTROL_DEFAULT 0x00000032
+#define mmDPRX_AUX_MSG_BUF_CONTROL1_DEFAULT 0x00000000
+#define mmDPRX_AUX_MSG_BUF_CONTROL2_DEFAULT 0x00000000
+#define mmDPRX_AUX_SCRATCH1_DEFAULT 0x00000000
+#define mmDPRX_AUX_SCRATCH2_DEFAULT 0x00000000
+#define mmDPRX_AUX_MSG1_PENDING_DEFAULT 0x00000000
+#define mmDPRX_AUX_MSG2_PENDING_DEFAULT 0x00000000
+#define mmDPRX_AUX_MSG3_PENDING_DEFAULT 0x00000000
+#define mmDPRX_AUX_MSG4_PENDING_DEFAULT 0x00000000
+#define mmDPRX_DPHY_DPCD_LANE_COUNT_SET_DEFAULT 0x00000000
+#define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET_DEFAULT 0x00000003
+#define mmDPRX_DPHY_DPCD_MSTM_CTRL_DEFAULT 0x00000000
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET_DEFAULT 0x00000000
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS_DEFAULT 0x20000000
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET_DEFAULT 0x00000000
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS_DEFAULT 0x20000000
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET_DEFAULT 0x00000000
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS_DEFAULT 0x20000000
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET_DEFAULT 0x00000000
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS_DEFAULT 0x20000000
+#define mmDPRX_DPHY_READY_DEFAULT 0x00000000
+#define mmDPRX_DPHY_COMMA_STATUS_DEFAULT 0x00000000
+#define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED_DEFAULT 0x00000000
+#define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED_DEFAULT 0x00000000
+#define mmDPRX_DPHY_ERROR_THRESH_A_LANE0_DEFAULT 0x00000000
+#define mmDPRX_DPHY_ERROR_COUNT_A_LANE0_DEFAULT 0x00000000
+#define mmDPRX_DPHY_ERROR_COUNT_B_LANE0_DEFAULT 0x00000000
+#define mmDPRX_DPHY_ERROR_COUNT_C_LANE0_DEFAULT 0x00000000
+#define mmDPRX_DPHY_ERROR_THRESH_A_LANE1_DEFAULT 0x00000000
+#define mmDPRX_DPHY_ERROR_COUNT_A_LANE1_DEFAULT 0x00000000
+#define mmDPRX_DPHY_ERROR_COUNT_B_LANE1_DEFAULT 0x00000000
+#define mmDPRX_DPHY_ERROR_COUNT_C_LANE1_DEFAULT 0x00000000
+#define mmDPRX_DPHY_ERROR_THRESH_A_LANE2_DEFAULT 0x00000000
+#define mmDPRX_DPHY_ERROR_COUNT_A_LANE2_DEFAULT 0x00000000
+#define mmDPRX_DPHY_ERROR_COUNT_B_LANE2_DEFAULT 0x00000000
+#define mmDPRX_DPHY_ERROR_COUNT_C_LANE2_DEFAULT 0x00000000
+#define mmDPRX_DPHY_ERROR_THRESH_A_LANE3_DEFAULT 0x00000000
+#define mmDPRX_DPHY_ERROR_COUNT_A_LANE3_DEFAULT 0x00000000
+#define mmDPRX_DPHY_ERROR_COUNT_B_LANE3_DEFAULT 0x00000000
+#define mmDPRX_DPHY_ERROR_COUNT_C_LANE3_DEFAULT 0x00000000
+#define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL_DEFAULT 0x00000000
+#define mmDPRX_DPHY_SR_ERROR_COUNT_A_DEFAULT 0x00000000
+#define mmDPRX_DPHY_BS_ERROR_COUNT_A_DEFAULT 0x00000000
+#define mmDPRX_DPHY_BS_ERROR_COUNT_B_DEFAULT 0x00000000
+#define mmDPRX_DPHY_LANESETUP0_DEFAULT 0x00000000
+#define mmDPRX_DPHY_LANESETUP1_DEFAULT 0x00000000
+#define mmDPRX_DPHY_LFSRADV_DEFAULT 0x00000039
+#define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT_DEFAULT 0x00000000
+#define mmDPRX_DPHY_SET_ENABLE_DEFAULT 0x00000000
+#define mmDPRX_DPHY_ECF_LSB_DEFAULT 0x00000000
+#define mmDPRX_DPHY_ECF_MSB_DEFAULT 0x00000000
+#define mmDPRX_DPHY_ENHANCED_FRAME_EN_DEFAULT 0x00000001
+#define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE_DEFAULT 0x000a6800
+#define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA_DEFAULT 0xbcbcbcbc
+#define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL_DEFAULT 0x800071c5
+#define mmDPRX_DPHY_BYPASS_DEFAULT 0x00000000
+#define mmDPRX_DPHY_INT_RESET_DEFAULT 0x00000000
+#define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000
+#define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000
+#define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000
+#define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000
+#define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS_DEFAULT 0x00000000
+#define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS_DEFAULT 0x00000000
+#define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS_DEFAULT 0x00000000
+#define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS_DEFAULT 0x00000000
+#define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS_DEFAULT 0x00000000
+#define mmDPRX_DPHY_SPARE_DEFAULT 0x00000000
+#define mmDCRX_GATE_DISABLE_CNTL_DEFAULT 0x00001f0f
+#define mmDCRX_SOFT_RESET_DEFAULT 0x00000000
+#define mmDCRX_LIGHT_SLEEP_CNTL_DEFAULT 0x00000101
+#define mmDCRX_DISPCLK_GATE_CNTL_DEFAULT 0x00000200
+#define mmDCRX_CLK_CNTL_DEFAULT 0x00000000
+#define mmDCRX_TEST_CLK_CNTL_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED160_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED161_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED162_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED163_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED164_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED165_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED166_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED167_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED168_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED169_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED170_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED171_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED172_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED173_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED174_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED175_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED176_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED177_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED178_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED179_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED180_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED181_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED182_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED183_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED184_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED185_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED186_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED187_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED188_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED189_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED190_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED191_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED192_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED193_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED194_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED195_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED196_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED197_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED198_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED199_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED200_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED201_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED202_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED203_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED204_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED205_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED206_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED207_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED208_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED209_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED210_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED211_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED212_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED213_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED214_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED215_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED216_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED217_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED218_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED219_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED220_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED221_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED222_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED223_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED224_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED225_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED226_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED227_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED228_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED229_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED230_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED231_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED232_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED233_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED234_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED235_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED236_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED237_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED238_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED239_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED240_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED241_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED242_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED243_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED244_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED245_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED246_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED247_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED248_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED249_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED250_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED251_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED252_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED253_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED254_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED255_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED256_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED257_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED258_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED259_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED260_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED261_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED262_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED263_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED264_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED265_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED266_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED267_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED268_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED269_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED270_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED271_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED272_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED273_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED274_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED275_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED276_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED277_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED278_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED279_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED280_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED281_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED282_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED283_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED284_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED285_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED286_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED287_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED288_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED289_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED290_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED291_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED292_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED293_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED294_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED295_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED296_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED297_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED298_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED299_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED300_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED301_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED302_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED303_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED304_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED305_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED306_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED307_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED308_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED309_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED310_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED311_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED312_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED313_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED314_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED315_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED316_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED317_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED318_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED319_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED320_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED321_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED322_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED323_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED324_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED325_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED326_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED327_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED328_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED329_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED330_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED331_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED332_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED333_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED334_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED335_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED336_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED337_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED338_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED339_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED340_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED341_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED342_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED343_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED344_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED345_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED346_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED347_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED348_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED349_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED350_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED351_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED352_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED353_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED354_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED355_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED356_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED357_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED358_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED359_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED360_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED361_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED362_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED363_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED364_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED365_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED366_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED367_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED368_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED369_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED370_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED371_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED372_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED373_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED374_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED375_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED376_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED377_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED378_DEFAULT 0x00000000
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED379_DEFAULT 0x00000000
+#define mmI2S0_CNTL_DEFAULT 0x00010000
+#define mmSPDIF0_CNTL_DEFAULT 0x00000000
+#define mmI2S1_CNTL_DEFAULT 0x00010000
+#define mmSPDIF1_CNTL_DEFAULT 0x00000000
+#define mmI2S0_STATUS_DEFAULT 0x00000000
+#define mmI2S1_STATUS_DEFAULT 0x00000000
+#define mmI2S0_CRC_TEST_CNTL_DEFAULT 0x00000100
+#define mmI2S0_CRC_TEST_DATA_01_DEFAULT 0x00000000
+#define mmI2S0_CRC_TEST_DATA_23_DEFAULT 0x00000000
+#define mmI2S1_CRC_TEST_CNTL_DEFAULT 0x00000100
+#define mmI2S1_CRC_TEST_DATA_0_DEFAULT 0x00000000
+#define mmSPDIF0_CRC_TEST_CNTL_DEFAULT 0x00000100
+#define mmSPDIF0_CRC_TEST_DATA_0_DEFAULT 0x00000000
+#define mmSPDIF1_CRC_TEST_CNTL_DEFAULT 0x00000100
+#define mmSPDIF1_CRC_TEST_DATA_DEFAULT 0x00000000
+#define mmCRC_I2S_CONT_REPEAT_NUM_DEFAULT 0x00000000
+#define mmCRC_SPDIF_CONT_REPEAT_NUM_DEFAULT 0x00000000
+#define mmZCAL_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+#define mmZCAL_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+#define mmZCAL_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+#define mmZCAL_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+#define mmZCAL_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0stream0_dispdec
+#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+#define mmAZF0STREAM0_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0stream1_dispdec
+#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+#define mmAZF0STREAM1_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0stream2_dispdec
+#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+#define mmAZF0STREAM2_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0stream3_dispdec
+#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+#define mmAZF0STREAM3_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0stream4_dispdec
+#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+#define mmAZF0STREAM4_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0stream5_dispdec
+#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+#define mmAZF0STREAM5_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0stream6_dispdec
+#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+#define mmAZF0STREAM6_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0stream7_dispdec
+#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+#define mmAZF0STREAM7_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0endpoint0_dispdec
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0endpoint1_dispdec
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0endpoint2_dispdec
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0endpoint3_dispdec
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0endpoint4_dispdec
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0endpoint5_dispdec
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0endpoint6_dispdec
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0endpoint7_dispdec
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0stream8_dispdec
+#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+#define mmAZF0STREAM8_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0stream9_dispdec
+#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+#define mmAZF0STREAM9_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0stream10_dispdec
+#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+#define mmAZF0STREAM10_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0stream11_dispdec
+#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+#define mmAZF0STREAM11_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0stream12_dispdec
+#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+#define mmAZF0STREAM12_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0stream13_dispdec
+#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+#define mmAZF0STREAM13_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0stream14_dispdec
+#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+#define mmAZF0STREAM14_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0stream15_dispdec
+#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_DEFAULT 0x00000000
+#define mmAZF0STREAM15_AZALIA_STREAM_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0inputendpoint0_dispdec
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0inputendpoint1_dispdec
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0inputendpoint2_dispdec
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0inputendpoint3_dispdec
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0inputendpoint4_dispdec
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0inputendpoint5_dispdec
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0inputendpoint6_dispdec
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azf0inputendpoint7_dispdec
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dcp0_dispdec
+#define mmDCP0_GRPH_ENABLE_DEFAULT 0x00000001
+#define mmDCP0_GRPH_CONTROL_DEFAULT 0x20002040
+#define mmDCP0_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000
+#define mmDCP0_GRPH_SWAP_CNTL_DEFAULT 0x00000000
+#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP0_GRPH_PITCH_DEFAULT 0x00000000
+#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP0_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000
+#define mmDCP0_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000
+#define mmDCP0_GRPH_X_START_DEFAULT 0x00000000
+#define mmDCP0_GRPH_Y_START_DEFAULT 0x00000000
+#define mmDCP0_GRPH_X_END_DEFAULT 0x00000000
+#define mmDCP0_GRPH_Y_END_DEFAULT 0x00000000
+#define mmDCP0_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000
+#define mmDCP0_GRPH_UPDATE_DEFAULT 0x00000000
+#define mmDCP0_GRPH_FLIP_CONTROL_DEFAULT 0x00000020
+#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000
+#define mmDCP0_GRPH_DFQ_CONTROL_DEFAULT 0x00000000
+#define mmDCP0_GRPH_DFQ_STATUS_DEFAULT 0x00000000
+#define mmDCP0_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmDCP0_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000
+#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP0_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000
+#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff
+#define mmDCP0_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010
+#define mmDCP0_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000
+#define mmDCP0_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000
+#define mmDCP0_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000
+#define mmDCP0_INPUT_CSC_CONTROL_DEFAULT 0x00000000
+#define mmDCP0_INPUT_CSC_C11_C12_DEFAULT 0x00002000
+#define mmDCP0_INPUT_CSC_C13_C14_DEFAULT 0x00000000
+#define mmDCP0_INPUT_CSC_C21_C22_DEFAULT 0x20000000
+#define mmDCP0_INPUT_CSC_C23_C24_DEFAULT 0x00000000
+#define mmDCP0_INPUT_CSC_C31_C32_DEFAULT 0x00000000
+#define mmDCP0_INPUT_CSC_C33_C34_DEFAULT 0x00002000
+#define mmDCP0_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
+#define mmDCP0_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000
+#define mmDCP0_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000
+#define mmDCP0_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000
+#define mmDCP0_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000
+#define mmDCP0_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000
+#define mmDCP0_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000
+#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000
+#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000
+#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000
+#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000
+#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000
+#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000
+#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000
+#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000
+#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000
+#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000
+#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000
+#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000
+#define mmDCP0_DENORM_CONTROL_DEFAULT 0x00000003
+#define mmDCP0_OUT_ROUND_CONTROL_DEFAULT 0x0000000a
+#define mmDCP0_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff
+#define mmDCP0_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff
+#define mmDCP0_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff
+#define mmDCP0_KEY_CONTROL_DEFAULT 0x00000000
+#define mmDCP0_KEY_RANGE_ALPHA_DEFAULT 0x00000000
+#define mmDCP0_KEY_RANGE_RED_DEFAULT 0x00000000
+#define mmDCP0_KEY_RANGE_GREEN_DEFAULT 0x00000000
+#define mmDCP0_KEY_RANGE_BLUE_DEFAULT 0x00000000
+#define mmDCP0_DEGAMMA_CONTROL_DEFAULT 0x00000000
+#define mmDCP0_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
+#define mmDCP0_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
+#define mmDCP0_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
+#define mmDCP0_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
+#define mmDCP0_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
+#define mmDCP0_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
+#define mmDCP0_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
+#define mmDCP0_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000
+#define mmDCP0_DCP_RANDOM_SEEDS_DEFAULT 0x00000000
+#define mmDCP0_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000
+#define mmDCP0_CUR_CONTROL_DEFAULT 0x00000810
+#define mmDCP0_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP0_CUR_SIZE_DEFAULT 0x00000000
+#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP0_CUR_POSITION_DEFAULT 0x00000000
+#define mmDCP0_CUR_HOT_SPOT_DEFAULT 0x00000000
+#define mmDCP0_CUR_COLOR1_DEFAULT 0x00000000
+#define mmDCP0_CUR_COLOR2_DEFAULT 0x00000000
+#define mmDCP0_CUR_UPDATE_DEFAULT 0x00000000
+#define mmDCP0_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000
+#define mmDCP0_CUR_STEREO_CONTROL_DEFAULT 0x00000000
+#define mmDCP0_DC_LUT_RW_MODE_DEFAULT 0x00000000
+#define mmDCP0_DC_LUT_RW_INDEX_DEFAULT 0x00000000
+#define mmDCP0_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000
+#define mmDCP0_DC_LUT_PWL_DATA_DEFAULT 0x00000000
+#define mmDCP0_DC_LUT_30_COLOR_DEFAULT 0x00000000
+#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000
+#define mmDCP0_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+#define mmDCP0_DC_LUT_AUTOFILL_DEFAULT 0x00000000
+#define mmDCP0_DC_LUT_CONTROL_DEFAULT 0x00000000
+#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000
+#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000
+#define mmDCP0_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000
+#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff
+#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff
+#define mmDCP0_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff
+#define mmDCP0_DCP_CRC_CONTROL_DEFAULT 0x00000000
+#define mmDCP0_DCP_CRC_MASK_DEFAULT 0x00000000
+#define mmDCP0_DCP_CRC_CURRENT_DEFAULT 0x00000000
+#define mmDCP0_DVMM_PTE_CONTROL_DEFAULT 0x00004000
+#define mmDCP0_DCP_CRC_LAST_DEFAULT 0x00000000
+#define mmDCP0_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
+#define mmDCP0_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000
+#define mmDCP0_DCP_GSL_CONTROL_DEFAULT 0x60000020
+#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035
+#define mmDCP0_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200
+#define mmDCP0_HW_ROTATION_DEFAULT 0x00000000
+#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010
+#define mmDCP0_REGAMMA_CONTROL_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_LUT_DATA_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+#define mmDCP0_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
+#define mmDCP0_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
+#define mmDCP0_ALPHA_CONTROL_DEFAULT 0x00000002
+#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000
+#define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000
+#define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000
+#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012
+#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_lb0_dispdec
+#define mmLB0_LB_DATA_FORMAT_DEFAULT 0x00000000
+#define mmLB0_LB_MEMORY_CTRL_DEFAULT 0x000006b0
+#define mmLB0_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
+#define mmLB0_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000
+#define mmLB0_LB_VLINE_START_END_DEFAULT 0x00000000
+#define mmLB0_LB_VLINE2_START_END_DEFAULT 0x00000000
+#define mmLB0_LB_V_COUNTER_DEFAULT 0x00000000
+#define mmLB0_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
+#define mmLB0_LB_INTERRUPT_MASK_DEFAULT 0x00000000
+#define mmLB0_LB_VLINE_STATUS_DEFAULT 0x00000000
+#define mmLB0_LB_VLINE2_STATUS_DEFAULT 0x00000000
+#define mmLB0_LB_VBLANK_STATUS_DEFAULT 0x00000000
+#define mmLB0_LB_SYNC_RESET_SEL_DEFAULT 0x00000002
+#define mmLB0_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000
+#define mmLB0_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000
+#define mmLB0_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000
+#define mmLB0_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000
+#define mmLB0_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000
+#define mmLB0_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000
+#define mmLB0_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000
+#define mmLB0_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
+#define mmLB0_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
+#define mmLB0_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
+#define mmLB0_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
+#define mmLB0_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
+#define mmLB0_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
+#define mmLB0_LB_BUFFER_STATUS_DEFAULT 0x00000002
+#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
+#define mmLB0_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000
+#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000
+#define mmLB0_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002
+#define mmLB0_DC_MVP_LB_CONTROL_DEFAULT 0x00000001
+
+
+// addressBlock: dce_dc_dcfe0_dispdec
+#define mmDCFE0_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000
+#define mmDCFE0_DCFE_SOFT_RESET_DEFAULT 0x00000000
+#define mmDCFE0_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000
+#define mmDCFE0_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000
+#define mmDCFE0_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000
+#define mmDCFE0_DCFE_MISC_DEFAULT 0x00000001
+#define mmDCFE0_DCFE_FLUSH_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_perfmon3_dispdec
+#define mmDC_PERFMON3_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON3_PERFCOUNTER_STATE_DEFAULT 0x00000000
+#define mmDC_PERFMON3_PERFMON_CNTL_DEFAULT 0x00000100
+#define mmDC_PERFMON3_PERFMON_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+#define mmDC_PERFMON3_PERFMON_HI_DEFAULT 0x00000000
+#define mmDC_PERFMON3_PERFMON_LOW_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dmif_pg0_dispdec
+#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
+#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
+#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777
+#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000
+#define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG0_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000
+#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
+#define mmDMIF_PG0_DPG_DVMM_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_scl0_dispdec
+#define mmSCL0_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000
+#define mmSCL0_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
+#define mmSCL0_SCL_MODE_DEFAULT 0x00000000
+#define mmSCL0_SCL_TAP_CONTROL_DEFAULT 0x00000000
+#define mmSCL0_SCL_CONTROL_DEFAULT 0x00000000
+#define mmSCL0_SCL_BYPASS_CONTROL_DEFAULT 0x00000000
+#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
+#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
+#define mmSCL0_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
+#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+#define mmSCL0_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
+#define mmSCL0_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000
+#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+#define mmSCL0_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
+#define mmSCL0_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
+#define mmSCL0_SCL_ROUND_OFFSET_DEFAULT 0x80000000
+#define mmSCL0_SCL_UPDATE_DEFAULT 0x00000000
+#define mmSCL0_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000
+#define mmSCL0_SCL_ALU_CONTROL_DEFAULT 0x00000000
+#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
+#define mmSCL0_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
+#define mmSCL0_VIEWPORT_START_DEFAULT 0x00000000
+#define mmSCL0_VIEWPORT_SIZE_DEFAULT 0x00000000
+#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
+#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
+#define mmSCL0_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000
+#define mmSCL0_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000
+#define mmSCL0_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000
+#define mmSCL0_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_blnd0_dispdec
+#define mmBLND0_BLND_CONTROL_DEFAULT 0xff0220ff
+#define mmBLND0_BLND_SM_CONTROL2_DEFAULT 0x00000000
+#define mmBLND0_BLND_CONTROL2_DEFAULT 0x00000010
+#define mmBLND0_BLND_UPDATE_DEFAULT 0x00000000
+#define mmBLND0_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
+#define mmBLND0_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000
+#define mmBLND0_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_crtc0_dispdec
+#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
+#define mmCRTC0_CRTC_H_TOTAL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_H_BLANK_START_END_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_H_SYNC_A_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_H_SYNC_B_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_VBI_END_DEFAULT 0x00000003
+#define mmCRTC0_CRTC_V_TOTAL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_V_BLANK_START_END_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_V_SYNC_A_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_V_SYNC_B_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_TRIGA_CNTL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_TRIGB_CNTL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_FLOW_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_CONTROL_DEFAULT 0x80400110
+#define mmCRTC0_CRTC_BLANK_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_STATUS_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_STATUS_POSITION_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_COUNT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_COUNT_RESET_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_STEREO_STATUS_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_STEREO_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002
+#define mmCRTC0_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_UPDATE_LOCK_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
+#define mmCRTC0_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
+#define mmCRTC0_CRTC_MVP_STATUS_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_MASTER_EN_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
+#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_BLACK_COLOR_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_CRC_CNTL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_CRC0_DATA_B_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_CRC1_DATA_B_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
+#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
+#define mmCRTC0_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_GSL_WINDOW_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_GSL_CONTROL_DEFAULT 0x00020000
+#define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC0_CRTC_DRR_CONTROL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_fmt0_dispdec
+#define mmFMT0_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
+#define mmFMT0_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
+#define mmFMT0_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
+#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
+#define mmFMT0_FMT_CONTROL_DEFAULT 0x00000000
+#define mmFMT0_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
+#define mmFMT0_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
+#define mmFMT0_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
+#define mmFMT0_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
+#define mmFMT0_FMT_CLAMP_CNTL_DEFAULT 0x00000000
+#define mmFMT0_FMT_CRC_CNTL_DEFAULT 0x01000040
+#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff
+#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff
+#define mmFMT0_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000
+#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000
+#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
+#define mmFMT0_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dcp1_dispdec
+#define mmDCP1_GRPH_ENABLE_DEFAULT 0x00000001
+#define mmDCP1_GRPH_CONTROL_DEFAULT 0x20002040
+#define mmDCP1_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000
+#define mmDCP1_GRPH_SWAP_CNTL_DEFAULT 0x00000000
+#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP1_GRPH_PITCH_DEFAULT 0x00000000
+#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP1_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000
+#define mmDCP1_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000
+#define mmDCP1_GRPH_X_START_DEFAULT 0x00000000
+#define mmDCP1_GRPH_Y_START_DEFAULT 0x00000000
+#define mmDCP1_GRPH_X_END_DEFAULT 0x00000000
+#define mmDCP1_GRPH_Y_END_DEFAULT 0x00000000
+#define mmDCP1_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000
+#define mmDCP1_GRPH_UPDATE_DEFAULT 0x00000000
+#define mmDCP1_GRPH_FLIP_CONTROL_DEFAULT 0x00000020
+#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000
+#define mmDCP1_GRPH_DFQ_CONTROL_DEFAULT 0x00000000
+#define mmDCP1_GRPH_DFQ_STATUS_DEFAULT 0x00000000
+#define mmDCP1_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmDCP1_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000
+#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP1_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000
+#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff
+#define mmDCP1_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010
+#define mmDCP1_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000
+#define mmDCP1_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000
+#define mmDCP1_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000
+#define mmDCP1_INPUT_CSC_CONTROL_DEFAULT 0x00000000
+#define mmDCP1_INPUT_CSC_C11_C12_DEFAULT 0x00002000
+#define mmDCP1_INPUT_CSC_C13_C14_DEFAULT 0x00000000
+#define mmDCP1_INPUT_CSC_C21_C22_DEFAULT 0x20000000
+#define mmDCP1_INPUT_CSC_C23_C24_DEFAULT 0x00000000
+#define mmDCP1_INPUT_CSC_C31_C32_DEFAULT 0x00000000
+#define mmDCP1_INPUT_CSC_C33_C34_DEFAULT 0x00002000
+#define mmDCP1_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
+#define mmDCP1_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000
+#define mmDCP1_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000
+#define mmDCP1_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000
+#define mmDCP1_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000
+#define mmDCP1_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000
+#define mmDCP1_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000
+#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000
+#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000
+#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000
+#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000
+#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000
+#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000
+#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000
+#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000
+#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000
+#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000
+#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000
+#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000
+#define mmDCP1_DENORM_CONTROL_DEFAULT 0x00000003
+#define mmDCP1_OUT_ROUND_CONTROL_DEFAULT 0x0000000a
+#define mmDCP1_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff
+#define mmDCP1_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff
+#define mmDCP1_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff
+#define mmDCP1_KEY_CONTROL_DEFAULT 0x00000000
+#define mmDCP1_KEY_RANGE_ALPHA_DEFAULT 0x00000000
+#define mmDCP1_KEY_RANGE_RED_DEFAULT 0x00000000
+#define mmDCP1_KEY_RANGE_GREEN_DEFAULT 0x00000000
+#define mmDCP1_KEY_RANGE_BLUE_DEFAULT 0x00000000
+#define mmDCP1_DEGAMMA_CONTROL_DEFAULT 0x00000000
+#define mmDCP1_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
+#define mmDCP1_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
+#define mmDCP1_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
+#define mmDCP1_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
+#define mmDCP1_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
+#define mmDCP1_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
+#define mmDCP1_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
+#define mmDCP1_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000
+#define mmDCP1_DCP_RANDOM_SEEDS_DEFAULT 0x00000000
+#define mmDCP1_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000
+#define mmDCP1_CUR_CONTROL_DEFAULT 0x00000810
+#define mmDCP1_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP1_CUR_SIZE_DEFAULT 0x00000000
+#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP1_CUR_POSITION_DEFAULT 0x00000000
+#define mmDCP1_CUR_HOT_SPOT_DEFAULT 0x00000000
+#define mmDCP1_CUR_COLOR1_DEFAULT 0x00000000
+#define mmDCP1_CUR_COLOR2_DEFAULT 0x00000000
+#define mmDCP1_CUR_UPDATE_DEFAULT 0x00000000
+#define mmDCP1_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000
+#define mmDCP1_CUR_STEREO_CONTROL_DEFAULT 0x00000000
+#define mmDCP1_DC_LUT_RW_MODE_DEFAULT 0x00000000
+#define mmDCP1_DC_LUT_RW_INDEX_DEFAULT 0x00000000
+#define mmDCP1_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000
+#define mmDCP1_DC_LUT_PWL_DATA_DEFAULT 0x00000000
+#define mmDCP1_DC_LUT_30_COLOR_DEFAULT 0x00000000
+#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000
+#define mmDCP1_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+#define mmDCP1_DC_LUT_AUTOFILL_DEFAULT 0x00000000
+#define mmDCP1_DC_LUT_CONTROL_DEFAULT 0x00000000
+#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000
+#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000
+#define mmDCP1_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000
+#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff
+#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff
+#define mmDCP1_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff
+#define mmDCP1_DCP_CRC_CONTROL_DEFAULT 0x00000000
+#define mmDCP1_DCP_CRC_MASK_DEFAULT 0x00000000
+#define mmDCP1_DCP_CRC_CURRENT_DEFAULT 0x00000000
+#define mmDCP1_DVMM_PTE_CONTROL_DEFAULT 0x00004000
+#define mmDCP1_DCP_CRC_LAST_DEFAULT 0x00000000
+#define mmDCP1_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
+#define mmDCP1_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000
+#define mmDCP1_DCP_GSL_CONTROL_DEFAULT 0x60000020
+#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035
+#define mmDCP1_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200
+#define mmDCP1_HW_ROTATION_DEFAULT 0x00000000
+#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010
+#define mmDCP1_REGAMMA_CONTROL_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_LUT_DATA_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+#define mmDCP1_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
+#define mmDCP1_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
+#define mmDCP1_ALPHA_CONTROL_DEFAULT 0x00000002
+#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000
+#define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000
+#define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000
+#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012
+#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_lb1_dispdec
+#define mmLB1_LB_DATA_FORMAT_DEFAULT 0x00000000
+#define mmLB1_LB_MEMORY_CTRL_DEFAULT 0x000006b0
+#define mmLB1_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
+#define mmLB1_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000
+#define mmLB1_LB_VLINE_START_END_DEFAULT 0x00000000
+#define mmLB1_LB_VLINE2_START_END_DEFAULT 0x00000000
+#define mmLB1_LB_V_COUNTER_DEFAULT 0x00000000
+#define mmLB1_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
+#define mmLB1_LB_INTERRUPT_MASK_DEFAULT 0x00000000
+#define mmLB1_LB_VLINE_STATUS_DEFAULT 0x00000000
+#define mmLB1_LB_VLINE2_STATUS_DEFAULT 0x00000000
+#define mmLB1_LB_VBLANK_STATUS_DEFAULT 0x00000000
+#define mmLB1_LB_SYNC_RESET_SEL_DEFAULT 0x00000002
+#define mmLB1_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000
+#define mmLB1_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000
+#define mmLB1_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000
+#define mmLB1_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000
+#define mmLB1_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000
+#define mmLB1_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000
+#define mmLB1_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000
+#define mmLB1_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
+#define mmLB1_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
+#define mmLB1_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
+#define mmLB1_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
+#define mmLB1_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
+#define mmLB1_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
+#define mmLB1_LB_BUFFER_STATUS_DEFAULT 0x00000002
+#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
+#define mmLB1_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000
+#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000
+#define mmLB1_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002
+#define mmLB1_DC_MVP_LB_CONTROL_DEFAULT 0x00000001
+
+
+// addressBlock: dce_dc_dcfe1_dispdec
+#define mmDCFE1_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000
+#define mmDCFE1_DCFE_SOFT_RESET_DEFAULT 0x00000000
+#define mmDCFE1_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000
+#define mmDCFE1_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000
+#define mmDCFE1_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000
+#define mmDCFE1_DCFE_MISC_DEFAULT 0x00000001
+#define mmDCFE1_DCFE_FLUSH_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_perfmon4_dispdec
+#define mmDC_PERFMON4_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON4_PERFCOUNTER_STATE_DEFAULT 0x00000000
+#define mmDC_PERFMON4_PERFMON_CNTL_DEFAULT 0x00000100
+#define mmDC_PERFMON4_PERFMON_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+#define mmDC_PERFMON4_PERFMON_HI_DEFAULT 0x00000000
+#define mmDC_PERFMON4_PERFMON_LOW_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dmif_pg1_dispdec
+#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
+#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
+#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777
+#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000
+#define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG1_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000
+#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
+#define mmDMIF_PG1_DPG_DVMM_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_scl1_dispdec
+#define mmSCL1_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000
+#define mmSCL1_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
+#define mmSCL1_SCL_MODE_DEFAULT 0x00000000
+#define mmSCL1_SCL_TAP_CONTROL_DEFAULT 0x00000000
+#define mmSCL1_SCL_CONTROL_DEFAULT 0x00000000
+#define mmSCL1_SCL_BYPASS_CONTROL_DEFAULT 0x00000000
+#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
+#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
+#define mmSCL1_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
+#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+#define mmSCL1_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
+#define mmSCL1_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000
+#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+#define mmSCL1_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
+#define mmSCL1_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
+#define mmSCL1_SCL_ROUND_OFFSET_DEFAULT 0x80000000
+#define mmSCL1_SCL_UPDATE_DEFAULT 0x00000000
+#define mmSCL1_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000
+#define mmSCL1_SCL_ALU_CONTROL_DEFAULT 0x00000000
+#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
+#define mmSCL1_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
+#define mmSCL1_VIEWPORT_START_DEFAULT 0x00000000
+#define mmSCL1_VIEWPORT_SIZE_DEFAULT 0x00000000
+#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
+#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
+#define mmSCL1_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000
+#define mmSCL1_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000
+#define mmSCL1_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000
+#define mmSCL1_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_blnd1_dispdec
+#define mmBLND1_BLND_CONTROL_DEFAULT 0xff0220ff
+#define mmBLND1_BLND_SM_CONTROL2_DEFAULT 0x00000000
+#define mmBLND1_BLND_CONTROL2_DEFAULT 0x00000010
+#define mmBLND1_BLND_UPDATE_DEFAULT 0x00000000
+#define mmBLND1_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
+#define mmBLND1_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000
+#define mmBLND1_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_crtc1_dispdec
+#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
+#define mmCRTC1_CRTC_H_TOTAL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_H_BLANK_START_END_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_H_SYNC_A_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_H_SYNC_B_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_VBI_END_DEFAULT 0x00000003
+#define mmCRTC1_CRTC_V_TOTAL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_V_BLANK_START_END_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_V_SYNC_A_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_V_SYNC_B_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_TRIGA_CNTL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_TRIGB_CNTL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_FLOW_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_CONTROL_DEFAULT 0x80400110
+#define mmCRTC1_CRTC_BLANK_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_STATUS_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_STATUS_POSITION_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_COUNT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_COUNT_RESET_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_STEREO_STATUS_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_STEREO_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002
+#define mmCRTC1_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_UPDATE_LOCK_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
+#define mmCRTC1_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
+#define mmCRTC1_CRTC_MVP_STATUS_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_MASTER_EN_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
+#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_BLACK_COLOR_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_CRC_CNTL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_CRC0_DATA_B_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_CRC1_DATA_B_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
+#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
+#define mmCRTC1_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_GSL_WINDOW_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_GSL_CONTROL_DEFAULT 0x00020000
+#define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC1_CRTC_DRR_CONTROL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_fmt1_dispdec
+#define mmFMT1_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
+#define mmFMT1_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
+#define mmFMT1_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
+#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
+#define mmFMT1_FMT_CONTROL_DEFAULT 0x00000000
+#define mmFMT1_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
+#define mmFMT1_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
+#define mmFMT1_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
+#define mmFMT1_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
+#define mmFMT1_FMT_CLAMP_CNTL_DEFAULT 0x00000000
+#define mmFMT1_FMT_CRC_CNTL_DEFAULT 0x01000040
+#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff
+#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff
+#define mmFMT1_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000
+#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000
+#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
+#define mmFMT1_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dcp2_dispdec
+#define mmDCP2_GRPH_ENABLE_DEFAULT 0x00000001
+#define mmDCP2_GRPH_CONTROL_DEFAULT 0x20002040
+#define mmDCP2_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000
+#define mmDCP2_GRPH_SWAP_CNTL_DEFAULT 0x00000000
+#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP2_GRPH_PITCH_DEFAULT 0x00000000
+#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP2_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000
+#define mmDCP2_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000
+#define mmDCP2_GRPH_X_START_DEFAULT 0x00000000
+#define mmDCP2_GRPH_Y_START_DEFAULT 0x00000000
+#define mmDCP2_GRPH_X_END_DEFAULT 0x00000000
+#define mmDCP2_GRPH_Y_END_DEFAULT 0x00000000
+#define mmDCP2_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000
+#define mmDCP2_GRPH_UPDATE_DEFAULT 0x00000000
+#define mmDCP2_GRPH_FLIP_CONTROL_DEFAULT 0x00000020
+#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000
+#define mmDCP2_GRPH_DFQ_CONTROL_DEFAULT 0x00000000
+#define mmDCP2_GRPH_DFQ_STATUS_DEFAULT 0x00000000
+#define mmDCP2_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmDCP2_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000
+#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP2_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000
+#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff
+#define mmDCP2_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010
+#define mmDCP2_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000
+#define mmDCP2_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000
+#define mmDCP2_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000
+#define mmDCP2_INPUT_CSC_CONTROL_DEFAULT 0x00000000
+#define mmDCP2_INPUT_CSC_C11_C12_DEFAULT 0x00002000
+#define mmDCP2_INPUT_CSC_C13_C14_DEFAULT 0x00000000
+#define mmDCP2_INPUT_CSC_C21_C22_DEFAULT 0x20000000
+#define mmDCP2_INPUT_CSC_C23_C24_DEFAULT 0x00000000
+#define mmDCP2_INPUT_CSC_C31_C32_DEFAULT 0x00000000
+#define mmDCP2_INPUT_CSC_C33_C34_DEFAULT 0x00002000
+#define mmDCP2_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
+#define mmDCP2_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000
+#define mmDCP2_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000
+#define mmDCP2_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000
+#define mmDCP2_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000
+#define mmDCP2_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000
+#define mmDCP2_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000
+#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000
+#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000
+#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000
+#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000
+#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000
+#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000
+#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000
+#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000
+#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000
+#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000
+#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000
+#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000
+#define mmDCP2_DENORM_CONTROL_DEFAULT 0x00000003
+#define mmDCP2_OUT_ROUND_CONTROL_DEFAULT 0x0000000a
+#define mmDCP2_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff
+#define mmDCP2_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff
+#define mmDCP2_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff
+#define mmDCP2_KEY_CONTROL_DEFAULT 0x00000000
+#define mmDCP2_KEY_RANGE_ALPHA_DEFAULT 0x00000000
+#define mmDCP2_KEY_RANGE_RED_DEFAULT 0x00000000
+#define mmDCP2_KEY_RANGE_GREEN_DEFAULT 0x00000000
+#define mmDCP2_KEY_RANGE_BLUE_DEFAULT 0x00000000
+#define mmDCP2_DEGAMMA_CONTROL_DEFAULT 0x00000000
+#define mmDCP2_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
+#define mmDCP2_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
+#define mmDCP2_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
+#define mmDCP2_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
+#define mmDCP2_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
+#define mmDCP2_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
+#define mmDCP2_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
+#define mmDCP2_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000
+#define mmDCP2_DCP_RANDOM_SEEDS_DEFAULT 0x00000000
+#define mmDCP2_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000
+#define mmDCP2_CUR_CONTROL_DEFAULT 0x00000810
+#define mmDCP2_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP2_CUR_SIZE_DEFAULT 0x00000000
+#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP2_CUR_POSITION_DEFAULT 0x00000000
+#define mmDCP2_CUR_HOT_SPOT_DEFAULT 0x00000000
+#define mmDCP2_CUR_COLOR1_DEFAULT 0x00000000
+#define mmDCP2_CUR_COLOR2_DEFAULT 0x00000000
+#define mmDCP2_CUR_UPDATE_DEFAULT 0x00000000
+#define mmDCP2_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000
+#define mmDCP2_CUR_STEREO_CONTROL_DEFAULT 0x00000000
+#define mmDCP2_DC_LUT_RW_MODE_DEFAULT 0x00000000
+#define mmDCP2_DC_LUT_RW_INDEX_DEFAULT 0x00000000
+#define mmDCP2_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000
+#define mmDCP2_DC_LUT_PWL_DATA_DEFAULT 0x00000000
+#define mmDCP2_DC_LUT_30_COLOR_DEFAULT 0x00000000
+#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000
+#define mmDCP2_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+#define mmDCP2_DC_LUT_AUTOFILL_DEFAULT 0x00000000
+#define mmDCP2_DC_LUT_CONTROL_DEFAULT 0x00000000
+#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000
+#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000
+#define mmDCP2_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000
+#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff
+#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff
+#define mmDCP2_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff
+#define mmDCP2_DCP_CRC_CONTROL_DEFAULT 0x00000000
+#define mmDCP2_DCP_CRC_MASK_DEFAULT 0x00000000
+#define mmDCP2_DCP_CRC_CURRENT_DEFAULT 0x00000000
+#define mmDCP2_DVMM_PTE_CONTROL_DEFAULT 0x00004000
+#define mmDCP2_DCP_CRC_LAST_DEFAULT 0x00000000
+#define mmDCP2_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
+#define mmDCP2_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000
+#define mmDCP2_DCP_GSL_CONTROL_DEFAULT 0x60000020
+#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035
+#define mmDCP2_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200
+#define mmDCP2_HW_ROTATION_DEFAULT 0x00000000
+#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010
+#define mmDCP2_REGAMMA_CONTROL_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_LUT_DATA_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+#define mmDCP2_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
+#define mmDCP2_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
+#define mmDCP2_ALPHA_CONTROL_DEFAULT 0x00000002
+#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000
+#define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000
+#define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000
+#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012
+#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_lb2_dispdec
+#define mmLB2_LB_DATA_FORMAT_DEFAULT 0x00000000
+#define mmLB2_LB_MEMORY_CTRL_DEFAULT 0x000006b0
+#define mmLB2_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
+#define mmLB2_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000
+#define mmLB2_LB_VLINE_START_END_DEFAULT 0x00000000
+#define mmLB2_LB_VLINE2_START_END_DEFAULT 0x00000000
+#define mmLB2_LB_V_COUNTER_DEFAULT 0x00000000
+#define mmLB2_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
+#define mmLB2_LB_INTERRUPT_MASK_DEFAULT 0x00000000
+#define mmLB2_LB_VLINE_STATUS_DEFAULT 0x00000000
+#define mmLB2_LB_VLINE2_STATUS_DEFAULT 0x00000000
+#define mmLB2_LB_VBLANK_STATUS_DEFAULT 0x00000000
+#define mmLB2_LB_SYNC_RESET_SEL_DEFAULT 0x00000002
+#define mmLB2_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000
+#define mmLB2_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000
+#define mmLB2_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000
+#define mmLB2_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000
+#define mmLB2_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000
+#define mmLB2_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000
+#define mmLB2_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000
+#define mmLB2_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
+#define mmLB2_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
+#define mmLB2_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
+#define mmLB2_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
+#define mmLB2_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
+#define mmLB2_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
+#define mmLB2_LB_BUFFER_STATUS_DEFAULT 0x00000002
+#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
+#define mmLB2_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000
+#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000
+#define mmLB2_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002
+#define mmLB2_DC_MVP_LB_CONTROL_DEFAULT 0x00000001
+
+
+// addressBlock: dce_dc_dcfe2_dispdec
+#define mmDCFE2_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000
+#define mmDCFE2_DCFE_SOFT_RESET_DEFAULT 0x00000000
+#define mmDCFE2_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000
+#define mmDCFE2_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000
+#define mmDCFE2_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000
+#define mmDCFE2_DCFE_MISC_DEFAULT 0x00000001
+#define mmDCFE2_DCFE_FLUSH_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_perfmon5_dispdec
+#define mmDC_PERFMON5_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON5_PERFCOUNTER_STATE_DEFAULT 0x00000000
+#define mmDC_PERFMON5_PERFMON_CNTL_DEFAULT 0x00000100
+#define mmDC_PERFMON5_PERFMON_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+#define mmDC_PERFMON5_PERFMON_HI_DEFAULT 0x00000000
+#define mmDC_PERFMON5_PERFMON_LOW_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dmif_pg2_dispdec
+#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
+#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
+#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777
+#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000
+#define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG2_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000
+#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
+#define mmDMIF_PG2_DPG_DVMM_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_scl2_dispdec
+#define mmSCL2_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000
+#define mmSCL2_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
+#define mmSCL2_SCL_MODE_DEFAULT 0x00000000
+#define mmSCL2_SCL_TAP_CONTROL_DEFAULT 0x00000000
+#define mmSCL2_SCL_CONTROL_DEFAULT 0x00000000
+#define mmSCL2_SCL_BYPASS_CONTROL_DEFAULT 0x00000000
+#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
+#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
+#define mmSCL2_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
+#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+#define mmSCL2_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
+#define mmSCL2_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000
+#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+#define mmSCL2_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
+#define mmSCL2_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
+#define mmSCL2_SCL_ROUND_OFFSET_DEFAULT 0x80000000
+#define mmSCL2_SCL_UPDATE_DEFAULT 0x00000000
+#define mmSCL2_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000
+#define mmSCL2_SCL_ALU_CONTROL_DEFAULT 0x00000000
+#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
+#define mmSCL2_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
+#define mmSCL2_VIEWPORT_START_DEFAULT 0x00000000
+#define mmSCL2_VIEWPORT_SIZE_DEFAULT 0x00000000
+#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
+#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
+#define mmSCL2_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000
+#define mmSCL2_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000
+#define mmSCL2_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000
+#define mmSCL2_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_blnd2_dispdec
+#define mmBLND2_BLND_CONTROL_DEFAULT 0xff0220ff
+#define mmBLND2_BLND_SM_CONTROL2_DEFAULT 0x00000000
+#define mmBLND2_BLND_CONTROL2_DEFAULT 0x00000010
+#define mmBLND2_BLND_UPDATE_DEFAULT 0x00000000
+#define mmBLND2_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
+#define mmBLND2_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000
+#define mmBLND2_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_crtc2_dispdec
+#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
+#define mmCRTC2_CRTC_H_TOTAL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_H_BLANK_START_END_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_H_SYNC_A_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_H_SYNC_B_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_VBI_END_DEFAULT 0x00000003
+#define mmCRTC2_CRTC_V_TOTAL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_V_BLANK_START_END_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_V_SYNC_A_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_V_SYNC_B_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_TRIGA_CNTL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_TRIGB_CNTL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_FLOW_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_CONTROL_DEFAULT 0x80400110
+#define mmCRTC2_CRTC_BLANK_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_STATUS_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_STATUS_POSITION_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_COUNT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_COUNT_RESET_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_STEREO_STATUS_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_STEREO_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002
+#define mmCRTC2_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_UPDATE_LOCK_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
+#define mmCRTC2_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
+#define mmCRTC2_CRTC_MVP_STATUS_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_MASTER_EN_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
+#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_BLACK_COLOR_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_CRC_CNTL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_CRC0_DATA_B_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_CRC1_DATA_B_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
+#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
+#define mmCRTC2_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_GSL_WINDOW_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_GSL_CONTROL_DEFAULT 0x00020000
+#define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC2_CRTC_DRR_CONTROL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_fmt2_dispdec
+#define mmFMT2_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
+#define mmFMT2_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
+#define mmFMT2_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
+#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
+#define mmFMT2_FMT_CONTROL_DEFAULT 0x00000000
+#define mmFMT2_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
+#define mmFMT2_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
+#define mmFMT2_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
+#define mmFMT2_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
+#define mmFMT2_FMT_CLAMP_CNTL_DEFAULT 0x00000000
+#define mmFMT2_FMT_CRC_CNTL_DEFAULT 0x01000040
+#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff
+#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff
+#define mmFMT2_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000
+#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000
+#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
+#define mmFMT2_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dcp3_dispdec
+#define mmDCP3_GRPH_ENABLE_DEFAULT 0x00000001
+#define mmDCP3_GRPH_CONTROL_DEFAULT 0x20002040
+#define mmDCP3_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000
+#define mmDCP3_GRPH_SWAP_CNTL_DEFAULT 0x00000000
+#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP3_GRPH_PITCH_DEFAULT 0x00000000
+#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP3_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000
+#define mmDCP3_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000
+#define mmDCP3_GRPH_X_START_DEFAULT 0x00000000
+#define mmDCP3_GRPH_Y_START_DEFAULT 0x00000000
+#define mmDCP3_GRPH_X_END_DEFAULT 0x00000000
+#define mmDCP3_GRPH_Y_END_DEFAULT 0x00000000
+#define mmDCP3_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000
+#define mmDCP3_GRPH_UPDATE_DEFAULT 0x00000000
+#define mmDCP3_GRPH_FLIP_CONTROL_DEFAULT 0x00000020
+#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000
+#define mmDCP3_GRPH_DFQ_CONTROL_DEFAULT 0x00000000
+#define mmDCP3_GRPH_DFQ_STATUS_DEFAULT 0x00000000
+#define mmDCP3_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmDCP3_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000
+#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP3_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000
+#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff
+#define mmDCP3_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010
+#define mmDCP3_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000
+#define mmDCP3_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000
+#define mmDCP3_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000
+#define mmDCP3_INPUT_CSC_CONTROL_DEFAULT 0x00000000
+#define mmDCP3_INPUT_CSC_C11_C12_DEFAULT 0x00002000
+#define mmDCP3_INPUT_CSC_C13_C14_DEFAULT 0x00000000
+#define mmDCP3_INPUT_CSC_C21_C22_DEFAULT 0x20000000
+#define mmDCP3_INPUT_CSC_C23_C24_DEFAULT 0x00000000
+#define mmDCP3_INPUT_CSC_C31_C32_DEFAULT 0x00000000
+#define mmDCP3_INPUT_CSC_C33_C34_DEFAULT 0x00002000
+#define mmDCP3_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
+#define mmDCP3_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000
+#define mmDCP3_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000
+#define mmDCP3_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000
+#define mmDCP3_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000
+#define mmDCP3_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000
+#define mmDCP3_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000
+#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000
+#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000
+#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000
+#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000
+#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000
+#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000
+#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000
+#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000
+#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000
+#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000
+#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000
+#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000
+#define mmDCP3_DENORM_CONTROL_DEFAULT 0x00000003
+#define mmDCP3_OUT_ROUND_CONTROL_DEFAULT 0x0000000a
+#define mmDCP3_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff
+#define mmDCP3_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff
+#define mmDCP3_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff
+#define mmDCP3_KEY_CONTROL_DEFAULT 0x00000000
+#define mmDCP3_KEY_RANGE_ALPHA_DEFAULT 0x00000000
+#define mmDCP3_KEY_RANGE_RED_DEFAULT 0x00000000
+#define mmDCP3_KEY_RANGE_GREEN_DEFAULT 0x00000000
+#define mmDCP3_KEY_RANGE_BLUE_DEFAULT 0x00000000
+#define mmDCP3_DEGAMMA_CONTROL_DEFAULT 0x00000000
+#define mmDCP3_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
+#define mmDCP3_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
+#define mmDCP3_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
+#define mmDCP3_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
+#define mmDCP3_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
+#define mmDCP3_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
+#define mmDCP3_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
+#define mmDCP3_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000
+#define mmDCP3_DCP_RANDOM_SEEDS_DEFAULT 0x00000000
+#define mmDCP3_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000
+#define mmDCP3_CUR_CONTROL_DEFAULT 0x00000810
+#define mmDCP3_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP3_CUR_SIZE_DEFAULT 0x00000000
+#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP3_CUR_POSITION_DEFAULT 0x00000000
+#define mmDCP3_CUR_HOT_SPOT_DEFAULT 0x00000000
+#define mmDCP3_CUR_COLOR1_DEFAULT 0x00000000
+#define mmDCP3_CUR_COLOR2_DEFAULT 0x00000000
+#define mmDCP3_CUR_UPDATE_DEFAULT 0x00000000
+#define mmDCP3_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000
+#define mmDCP3_CUR_STEREO_CONTROL_DEFAULT 0x00000000
+#define mmDCP3_DC_LUT_RW_MODE_DEFAULT 0x00000000
+#define mmDCP3_DC_LUT_RW_INDEX_DEFAULT 0x00000000
+#define mmDCP3_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000
+#define mmDCP3_DC_LUT_PWL_DATA_DEFAULT 0x00000000
+#define mmDCP3_DC_LUT_30_COLOR_DEFAULT 0x00000000
+#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000
+#define mmDCP3_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+#define mmDCP3_DC_LUT_AUTOFILL_DEFAULT 0x00000000
+#define mmDCP3_DC_LUT_CONTROL_DEFAULT 0x00000000
+#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000
+#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000
+#define mmDCP3_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000
+#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff
+#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff
+#define mmDCP3_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff
+#define mmDCP3_DCP_CRC_CONTROL_DEFAULT 0x00000000
+#define mmDCP3_DCP_CRC_MASK_DEFAULT 0x00000000
+#define mmDCP3_DCP_CRC_CURRENT_DEFAULT 0x00000000
+#define mmDCP3_DVMM_PTE_CONTROL_DEFAULT 0x00004000
+#define mmDCP3_DCP_CRC_LAST_DEFAULT 0x00000000
+#define mmDCP3_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
+#define mmDCP3_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000
+#define mmDCP3_DCP_GSL_CONTROL_DEFAULT 0x60000020
+#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035
+#define mmDCP3_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200
+#define mmDCP3_HW_ROTATION_DEFAULT 0x00000000
+#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010
+#define mmDCP3_REGAMMA_CONTROL_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_LUT_DATA_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+#define mmDCP3_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
+#define mmDCP3_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
+#define mmDCP3_ALPHA_CONTROL_DEFAULT 0x00000002
+#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000
+#define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000
+#define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000
+#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012
+#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_lb3_dispdec
+#define mmLB3_LB_DATA_FORMAT_DEFAULT 0x00000000
+#define mmLB3_LB_MEMORY_CTRL_DEFAULT 0x000006b0
+#define mmLB3_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
+#define mmLB3_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000
+#define mmLB3_LB_VLINE_START_END_DEFAULT 0x00000000
+#define mmLB3_LB_VLINE2_START_END_DEFAULT 0x00000000
+#define mmLB3_LB_V_COUNTER_DEFAULT 0x00000000
+#define mmLB3_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
+#define mmLB3_LB_INTERRUPT_MASK_DEFAULT 0x00000000
+#define mmLB3_LB_VLINE_STATUS_DEFAULT 0x00000000
+#define mmLB3_LB_VLINE2_STATUS_DEFAULT 0x00000000
+#define mmLB3_LB_VBLANK_STATUS_DEFAULT 0x00000000
+#define mmLB3_LB_SYNC_RESET_SEL_DEFAULT 0x00000002
+#define mmLB3_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000
+#define mmLB3_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000
+#define mmLB3_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000
+#define mmLB3_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000
+#define mmLB3_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000
+#define mmLB3_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000
+#define mmLB3_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000
+#define mmLB3_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
+#define mmLB3_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
+#define mmLB3_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
+#define mmLB3_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
+#define mmLB3_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
+#define mmLB3_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
+#define mmLB3_LB_BUFFER_STATUS_DEFAULT 0x00000002
+#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
+#define mmLB3_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000
+#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000
+#define mmLB3_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002
+#define mmLB3_DC_MVP_LB_CONTROL_DEFAULT 0x00000001
+
+
+// addressBlock: dce_dc_dcfe3_dispdec
+#define mmDCFE3_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000
+#define mmDCFE3_DCFE_SOFT_RESET_DEFAULT 0x00000000
+#define mmDCFE3_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000
+#define mmDCFE3_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000
+#define mmDCFE3_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000
+#define mmDCFE3_DCFE_MISC_DEFAULT 0x00000001
+#define mmDCFE3_DCFE_FLUSH_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_perfmon6_dispdec
+#define mmDC_PERFMON6_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON6_PERFCOUNTER_STATE_DEFAULT 0x00000000
+#define mmDC_PERFMON6_PERFMON_CNTL_DEFAULT 0x00000100
+#define mmDC_PERFMON6_PERFMON_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+#define mmDC_PERFMON6_PERFMON_HI_DEFAULT 0x00000000
+#define mmDC_PERFMON6_PERFMON_LOW_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dmif_pg3_dispdec
+#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
+#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
+#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777
+#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000
+#define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG3_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000
+#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
+#define mmDMIF_PG3_DPG_DVMM_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_scl3_dispdec
+#define mmSCL3_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000
+#define mmSCL3_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
+#define mmSCL3_SCL_MODE_DEFAULT 0x00000000
+#define mmSCL3_SCL_TAP_CONTROL_DEFAULT 0x00000000
+#define mmSCL3_SCL_CONTROL_DEFAULT 0x00000000
+#define mmSCL3_SCL_BYPASS_CONTROL_DEFAULT 0x00000000
+#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
+#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
+#define mmSCL3_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
+#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+#define mmSCL3_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
+#define mmSCL3_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000
+#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+#define mmSCL3_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
+#define mmSCL3_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
+#define mmSCL3_SCL_ROUND_OFFSET_DEFAULT 0x80000000
+#define mmSCL3_SCL_UPDATE_DEFAULT 0x00000000
+#define mmSCL3_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000
+#define mmSCL3_SCL_ALU_CONTROL_DEFAULT 0x00000000
+#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
+#define mmSCL3_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
+#define mmSCL3_VIEWPORT_START_DEFAULT 0x00000000
+#define mmSCL3_VIEWPORT_SIZE_DEFAULT 0x00000000
+#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
+#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
+#define mmSCL3_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000
+#define mmSCL3_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000
+#define mmSCL3_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000
+#define mmSCL3_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_blnd3_dispdec
+#define mmBLND3_BLND_CONTROL_DEFAULT 0xff0220ff
+#define mmBLND3_BLND_SM_CONTROL2_DEFAULT 0x00000000
+#define mmBLND3_BLND_CONTROL2_DEFAULT 0x00000010
+#define mmBLND3_BLND_UPDATE_DEFAULT 0x00000000
+#define mmBLND3_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
+#define mmBLND3_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000
+#define mmBLND3_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_crtc3_dispdec
+#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
+#define mmCRTC3_CRTC_H_TOTAL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_H_BLANK_START_END_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_H_SYNC_A_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_H_SYNC_B_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_VBI_END_DEFAULT 0x00000003
+#define mmCRTC3_CRTC_V_TOTAL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_V_BLANK_START_END_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_V_SYNC_A_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_V_SYNC_B_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_TRIGA_CNTL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_TRIGB_CNTL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_FLOW_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_CONTROL_DEFAULT 0x80400110
+#define mmCRTC3_CRTC_BLANK_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_STATUS_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_STATUS_POSITION_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_COUNT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_COUNT_RESET_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_STEREO_STATUS_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_STEREO_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002
+#define mmCRTC3_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_UPDATE_LOCK_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
+#define mmCRTC3_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
+#define mmCRTC3_CRTC_MVP_STATUS_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_MASTER_EN_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
+#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_BLACK_COLOR_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_CRC_CNTL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_CRC0_DATA_B_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_CRC1_DATA_B_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
+#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
+#define mmCRTC3_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_GSL_WINDOW_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_GSL_CONTROL_DEFAULT 0x00020000
+#define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC3_CRTC_DRR_CONTROL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_fmt3_dispdec
+#define mmFMT3_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
+#define mmFMT3_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
+#define mmFMT3_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
+#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
+#define mmFMT3_FMT_CONTROL_DEFAULT 0x00000000
+#define mmFMT3_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
+#define mmFMT3_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
+#define mmFMT3_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
+#define mmFMT3_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
+#define mmFMT3_FMT_CLAMP_CNTL_DEFAULT 0x00000000
+#define mmFMT3_FMT_CRC_CNTL_DEFAULT 0x01000040
+#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff
+#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff
+#define mmFMT3_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000
+#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000
+#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
+#define mmFMT3_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dcp4_dispdec
+#define mmDCP4_GRPH_ENABLE_DEFAULT 0x00000001
+#define mmDCP4_GRPH_CONTROL_DEFAULT 0x20002040
+#define mmDCP4_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000
+#define mmDCP4_GRPH_SWAP_CNTL_DEFAULT 0x00000000
+#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP4_GRPH_PITCH_DEFAULT 0x00000000
+#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP4_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000
+#define mmDCP4_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000
+#define mmDCP4_GRPH_X_START_DEFAULT 0x00000000
+#define mmDCP4_GRPH_Y_START_DEFAULT 0x00000000
+#define mmDCP4_GRPH_X_END_DEFAULT 0x00000000
+#define mmDCP4_GRPH_Y_END_DEFAULT 0x00000000
+#define mmDCP4_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000
+#define mmDCP4_GRPH_UPDATE_DEFAULT 0x00000000
+#define mmDCP4_GRPH_FLIP_CONTROL_DEFAULT 0x00000020
+#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000
+#define mmDCP4_GRPH_DFQ_CONTROL_DEFAULT 0x00000000
+#define mmDCP4_GRPH_DFQ_STATUS_DEFAULT 0x00000000
+#define mmDCP4_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmDCP4_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000
+#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP4_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000
+#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff
+#define mmDCP4_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010
+#define mmDCP4_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000
+#define mmDCP4_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000
+#define mmDCP4_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000
+#define mmDCP4_INPUT_CSC_CONTROL_DEFAULT 0x00000000
+#define mmDCP4_INPUT_CSC_C11_C12_DEFAULT 0x00002000
+#define mmDCP4_INPUT_CSC_C13_C14_DEFAULT 0x00000000
+#define mmDCP4_INPUT_CSC_C21_C22_DEFAULT 0x20000000
+#define mmDCP4_INPUT_CSC_C23_C24_DEFAULT 0x00000000
+#define mmDCP4_INPUT_CSC_C31_C32_DEFAULT 0x00000000
+#define mmDCP4_INPUT_CSC_C33_C34_DEFAULT 0x00002000
+#define mmDCP4_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
+#define mmDCP4_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000
+#define mmDCP4_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000
+#define mmDCP4_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000
+#define mmDCP4_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000
+#define mmDCP4_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000
+#define mmDCP4_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000
+#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000
+#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000
+#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000
+#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000
+#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000
+#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000
+#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000
+#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000
+#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000
+#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000
+#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000
+#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000
+#define mmDCP4_DENORM_CONTROL_DEFAULT 0x00000003
+#define mmDCP4_OUT_ROUND_CONTROL_DEFAULT 0x0000000a
+#define mmDCP4_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff
+#define mmDCP4_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff
+#define mmDCP4_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff
+#define mmDCP4_KEY_CONTROL_DEFAULT 0x00000000
+#define mmDCP4_KEY_RANGE_ALPHA_DEFAULT 0x00000000
+#define mmDCP4_KEY_RANGE_RED_DEFAULT 0x00000000
+#define mmDCP4_KEY_RANGE_GREEN_DEFAULT 0x00000000
+#define mmDCP4_KEY_RANGE_BLUE_DEFAULT 0x00000000
+#define mmDCP4_DEGAMMA_CONTROL_DEFAULT 0x00000000
+#define mmDCP4_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
+#define mmDCP4_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
+#define mmDCP4_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
+#define mmDCP4_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
+#define mmDCP4_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
+#define mmDCP4_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
+#define mmDCP4_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
+#define mmDCP4_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000
+#define mmDCP4_DCP_RANDOM_SEEDS_DEFAULT 0x00000000
+#define mmDCP4_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000
+#define mmDCP4_CUR_CONTROL_DEFAULT 0x00000810
+#define mmDCP4_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP4_CUR_SIZE_DEFAULT 0x00000000
+#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP4_CUR_POSITION_DEFAULT 0x00000000
+#define mmDCP4_CUR_HOT_SPOT_DEFAULT 0x00000000
+#define mmDCP4_CUR_COLOR1_DEFAULT 0x00000000
+#define mmDCP4_CUR_COLOR2_DEFAULT 0x00000000
+#define mmDCP4_CUR_UPDATE_DEFAULT 0x00000000
+#define mmDCP4_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000
+#define mmDCP4_CUR_STEREO_CONTROL_DEFAULT 0x00000000
+#define mmDCP4_DC_LUT_RW_MODE_DEFAULT 0x00000000
+#define mmDCP4_DC_LUT_RW_INDEX_DEFAULT 0x00000000
+#define mmDCP4_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000
+#define mmDCP4_DC_LUT_PWL_DATA_DEFAULT 0x00000000
+#define mmDCP4_DC_LUT_30_COLOR_DEFAULT 0x00000000
+#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000
+#define mmDCP4_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+#define mmDCP4_DC_LUT_AUTOFILL_DEFAULT 0x00000000
+#define mmDCP4_DC_LUT_CONTROL_DEFAULT 0x00000000
+#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000
+#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000
+#define mmDCP4_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000
+#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff
+#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff
+#define mmDCP4_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff
+#define mmDCP4_DCP_CRC_CONTROL_DEFAULT 0x00000000
+#define mmDCP4_DCP_CRC_MASK_DEFAULT 0x00000000
+#define mmDCP4_DCP_CRC_CURRENT_DEFAULT 0x00000000
+#define mmDCP4_DVMM_PTE_CONTROL_DEFAULT 0x00004000
+#define mmDCP4_DCP_CRC_LAST_DEFAULT 0x00000000
+#define mmDCP4_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
+#define mmDCP4_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000
+#define mmDCP4_DCP_GSL_CONTROL_DEFAULT 0x60000020
+#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035
+#define mmDCP4_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200
+#define mmDCP4_HW_ROTATION_DEFAULT 0x00000000
+#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010
+#define mmDCP4_REGAMMA_CONTROL_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_LUT_DATA_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+#define mmDCP4_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
+#define mmDCP4_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
+#define mmDCP4_ALPHA_CONTROL_DEFAULT 0x00000002
+#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000
+#define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000
+#define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000
+#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012
+#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_lb4_dispdec
+#define mmLB4_LB_DATA_FORMAT_DEFAULT 0x00000000
+#define mmLB4_LB_MEMORY_CTRL_DEFAULT 0x000006b0
+#define mmLB4_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
+#define mmLB4_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000
+#define mmLB4_LB_VLINE_START_END_DEFAULT 0x00000000
+#define mmLB4_LB_VLINE2_START_END_DEFAULT 0x00000000
+#define mmLB4_LB_V_COUNTER_DEFAULT 0x00000000
+#define mmLB4_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
+#define mmLB4_LB_INTERRUPT_MASK_DEFAULT 0x00000000
+#define mmLB4_LB_VLINE_STATUS_DEFAULT 0x00000000
+#define mmLB4_LB_VLINE2_STATUS_DEFAULT 0x00000000
+#define mmLB4_LB_VBLANK_STATUS_DEFAULT 0x00000000
+#define mmLB4_LB_SYNC_RESET_SEL_DEFAULT 0x00000002
+#define mmLB4_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000
+#define mmLB4_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000
+#define mmLB4_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000
+#define mmLB4_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000
+#define mmLB4_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000
+#define mmLB4_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000
+#define mmLB4_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000
+#define mmLB4_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
+#define mmLB4_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
+#define mmLB4_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
+#define mmLB4_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
+#define mmLB4_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
+#define mmLB4_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
+#define mmLB4_LB_BUFFER_STATUS_DEFAULT 0x00000002
+#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
+#define mmLB4_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000
+#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000
+#define mmLB4_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002
+#define mmLB4_DC_MVP_LB_CONTROL_DEFAULT 0x00000001
+
+
+// addressBlock: dce_dc_dcfe4_dispdec
+#define mmDCFE4_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000
+#define mmDCFE4_DCFE_SOFT_RESET_DEFAULT 0x00000000
+#define mmDCFE4_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000
+#define mmDCFE4_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000
+#define mmDCFE4_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000
+#define mmDCFE4_DCFE_MISC_DEFAULT 0x00000001
+#define mmDCFE4_DCFE_FLUSH_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_perfmon7_dispdec
+#define mmDC_PERFMON7_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON7_PERFCOUNTER_STATE_DEFAULT 0x00000000
+#define mmDC_PERFMON7_PERFMON_CNTL_DEFAULT 0x00000100
+#define mmDC_PERFMON7_PERFMON_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+#define mmDC_PERFMON7_PERFMON_HI_DEFAULT 0x00000000
+#define mmDC_PERFMON7_PERFMON_LOW_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dmif_pg4_dispdec
+#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
+#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
+#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777
+#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000
+#define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG4_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000
+#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
+#define mmDMIF_PG4_DPG_DVMM_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_scl4_dispdec
+#define mmSCL4_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000
+#define mmSCL4_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
+#define mmSCL4_SCL_MODE_DEFAULT 0x00000000
+#define mmSCL4_SCL_TAP_CONTROL_DEFAULT 0x00000000
+#define mmSCL4_SCL_CONTROL_DEFAULT 0x00000000
+#define mmSCL4_SCL_BYPASS_CONTROL_DEFAULT 0x00000000
+#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
+#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
+#define mmSCL4_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
+#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+#define mmSCL4_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
+#define mmSCL4_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000
+#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+#define mmSCL4_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
+#define mmSCL4_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
+#define mmSCL4_SCL_ROUND_OFFSET_DEFAULT 0x80000000
+#define mmSCL4_SCL_UPDATE_DEFAULT 0x00000000
+#define mmSCL4_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000
+#define mmSCL4_SCL_ALU_CONTROL_DEFAULT 0x00000000
+#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
+#define mmSCL4_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
+#define mmSCL4_VIEWPORT_START_DEFAULT 0x00000000
+#define mmSCL4_VIEWPORT_SIZE_DEFAULT 0x00000000
+#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
+#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
+#define mmSCL4_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000
+#define mmSCL4_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000
+#define mmSCL4_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000
+#define mmSCL4_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_blnd4_dispdec
+#define mmBLND4_BLND_CONTROL_DEFAULT 0xff0220ff
+#define mmBLND4_BLND_SM_CONTROL2_DEFAULT 0x00000000
+#define mmBLND4_BLND_CONTROL2_DEFAULT 0x00000010
+#define mmBLND4_BLND_UPDATE_DEFAULT 0x00000000
+#define mmBLND4_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
+#define mmBLND4_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000
+#define mmBLND4_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_crtc4_dispdec
+#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
+#define mmCRTC4_CRTC_H_TOTAL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_H_BLANK_START_END_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_H_SYNC_A_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_H_SYNC_B_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_VBI_END_DEFAULT 0x00000003
+#define mmCRTC4_CRTC_V_TOTAL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_V_BLANK_START_END_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_V_SYNC_A_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_V_SYNC_B_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_TRIGA_CNTL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_TRIGB_CNTL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_FLOW_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_CONTROL_DEFAULT 0x80400110
+#define mmCRTC4_CRTC_BLANK_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_STATUS_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_STATUS_POSITION_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_COUNT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_COUNT_RESET_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_STEREO_STATUS_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_STEREO_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002
+#define mmCRTC4_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_UPDATE_LOCK_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
+#define mmCRTC4_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
+#define mmCRTC4_CRTC_MVP_STATUS_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_MASTER_EN_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
+#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_BLACK_COLOR_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_CRC_CNTL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_CRC0_DATA_B_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_CRC1_DATA_B_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
+#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
+#define mmCRTC4_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_GSL_WINDOW_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_GSL_CONTROL_DEFAULT 0x00020000
+#define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC4_CRTC_DRR_CONTROL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_fmt4_dispdec
+#define mmFMT4_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
+#define mmFMT4_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
+#define mmFMT4_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
+#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
+#define mmFMT4_FMT_CONTROL_DEFAULT 0x00000000
+#define mmFMT4_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
+#define mmFMT4_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
+#define mmFMT4_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
+#define mmFMT4_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
+#define mmFMT4_FMT_CLAMP_CNTL_DEFAULT 0x00000000
+#define mmFMT4_FMT_CRC_CNTL_DEFAULT 0x01000040
+#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff
+#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff
+#define mmFMT4_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000
+#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000
+#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
+#define mmFMT4_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dcp5_dispdec
+#define mmDCP5_GRPH_ENABLE_DEFAULT 0x00000001
+#define mmDCP5_GRPH_CONTROL_DEFAULT 0x20002040
+#define mmDCP5_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000
+#define mmDCP5_GRPH_SWAP_CNTL_DEFAULT 0x00000000
+#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP5_GRPH_PITCH_DEFAULT 0x00000000
+#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP5_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000
+#define mmDCP5_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000
+#define mmDCP5_GRPH_X_START_DEFAULT 0x00000000
+#define mmDCP5_GRPH_Y_START_DEFAULT 0x00000000
+#define mmDCP5_GRPH_X_END_DEFAULT 0x00000000
+#define mmDCP5_GRPH_Y_END_DEFAULT 0x00000000
+#define mmDCP5_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000
+#define mmDCP5_GRPH_UPDATE_DEFAULT 0x00000000
+#define mmDCP5_GRPH_FLIP_CONTROL_DEFAULT 0x00000020
+#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000
+#define mmDCP5_GRPH_DFQ_CONTROL_DEFAULT 0x00000000
+#define mmDCP5_GRPH_DFQ_STATUS_DEFAULT 0x00000000
+#define mmDCP5_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmDCP5_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000
+#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP5_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000
+#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff
+#define mmDCP5_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010
+#define mmDCP5_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000
+#define mmDCP5_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000
+#define mmDCP5_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000
+#define mmDCP5_INPUT_CSC_CONTROL_DEFAULT 0x00000000
+#define mmDCP5_INPUT_CSC_C11_C12_DEFAULT 0x00002000
+#define mmDCP5_INPUT_CSC_C13_C14_DEFAULT 0x00000000
+#define mmDCP5_INPUT_CSC_C21_C22_DEFAULT 0x20000000
+#define mmDCP5_INPUT_CSC_C23_C24_DEFAULT 0x00000000
+#define mmDCP5_INPUT_CSC_C31_C32_DEFAULT 0x00000000
+#define mmDCP5_INPUT_CSC_C33_C34_DEFAULT 0x00002000
+#define mmDCP5_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
+#define mmDCP5_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000
+#define mmDCP5_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000
+#define mmDCP5_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000
+#define mmDCP5_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000
+#define mmDCP5_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000
+#define mmDCP5_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000
+#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000
+#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000
+#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000
+#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000
+#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000
+#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000
+#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000
+#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000
+#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000
+#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000
+#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000
+#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000
+#define mmDCP5_DENORM_CONTROL_DEFAULT 0x00000003
+#define mmDCP5_OUT_ROUND_CONTROL_DEFAULT 0x0000000a
+#define mmDCP5_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff
+#define mmDCP5_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff
+#define mmDCP5_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff
+#define mmDCP5_KEY_CONTROL_DEFAULT 0x00000000
+#define mmDCP5_KEY_RANGE_ALPHA_DEFAULT 0x00000000
+#define mmDCP5_KEY_RANGE_RED_DEFAULT 0x00000000
+#define mmDCP5_KEY_RANGE_GREEN_DEFAULT 0x00000000
+#define mmDCP5_KEY_RANGE_BLUE_DEFAULT 0x00000000
+#define mmDCP5_DEGAMMA_CONTROL_DEFAULT 0x00000000
+#define mmDCP5_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
+#define mmDCP5_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
+#define mmDCP5_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
+#define mmDCP5_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
+#define mmDCP5_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
+#define mmDCP5_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
+#define mmDCP5_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
+#define mmDCP5_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000
+#define mmDCP5_DCP_RANDOM_SEEDS_DEFAULT 0x00000000
+#define mmDCP5_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000
+#define mmDCP5_CUR_CONTROL_DEFAULT 0x00000810
+#define mmDCP5_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP5_CUR_SIZE_DEFAULT 0x00000000
+#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP5_CUR_POSITION_DEFAULT 0x00000000
+#define mmDCP5_CUR_HOT_SPOT_DEFAULT 0x00000000
+#define mmDCP5_CUR_COLOR1_DEFAULT 0x00000000
+#define mmDCP5_CUR_COLOR2_DEFAULT 0x00000000
+#define mmDCP5_CUR_UPDATE_DEFAULT 0x00000000
+#define mmDCP5_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000
+#define mmDCP5_CUR_STEREO_CONTROL_DEFAULT 0x00000000
+#define mmDCP5_DC_LUT_RW_MODE_DEFAULT 0x00000000
+#define mmDCP5_DC_LUT_RW_INDEX_DEFAULT 0x00000000
+#define mmDCP5_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000
+#define mmDCP5_DC_LUT_PWL_DATA_DEFAULT 0x00000000
+#define mmDCP5_DC_LUT_30_COLOR_DEFAULT 0x00000000
+#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000
+#define mmDCP5_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+#define mmDCP5_DC_LUT_AUTOFILL_DEFAULT 0x00000000
+#define mmDCP5_DC_LUT_CONTROL_DEFAULT 0x00000000
+#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000
+#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000
+#define mmDCP5_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000
+#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff
+#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff
+#define mmDCP5_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff
+#define mmDCP5_DCP_CRC_CONTROL_DEFAULT 0x00000000
+#define mmDCP5_DCP_CRC_MASK_DEFAULT 0x00000000
+#define mmDCP5_DCP_CRC_CURRENT_DEFAULT 0x00000000
+#define mmDCP5_DVMM_PTE_CONTROL_DEFAULT 0x00004000
+#define mmDCP5_DCP_CRC_LAST_DEFAULT 0x00000000
+#define mmDCP5_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
+#define mmDCP5_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000
+#define mmDCP5_DCP_GSL_CONTROL_DEFAULT 0x60000020
+#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035
+#define mmDCP5_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200
+#define mmDCP5_HW_ROTATION_DEFAULT 0x00000000
+#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010
+#define mmDCP5_REGAMMA_CONTROL_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_LUT_DATA_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+#define mmDCP5_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
+#define mmDCP5_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
+#define mmDCP5_ALPHA_CONTROL_DEFAULT 0x00000002
+#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000
+#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000
+#define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000
+#define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000
+#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012
+#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_lb5_dispdec
+#define mmLB5_LB_DATA_FORMAT_DEFAULT 0x00000000
+#define mmLB5_LB_MEMORY_CTRL_DEFAULT 0x000006b0
+#define mmLB5_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
+#define mmLB5_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000
+#define mmLB5_LB_VLINE_START_END_DEFAULT 0x00000000
+#define mmLB5_LB_VLINE2_START_END_DEFAULT 0x00000000
+#define mmLB5_LB_V_COUNTER_DEFAULT 0x00000000
+#define mmLB5_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
+#define mmLB5_LB_INTERRUPT_MASK_DEFAULT 0x00000000
+#define mmLB5_LB_VLINE_STATUS_DEFAULT 0x00000000
+#define mmLB5_LB_VLINE2_STATUS_DEFAULT 0x00000000
+#define mmLB5_LB_VBLANK_STATUS_DEFAULT 0x00000000
+#define mmLB5_LB_SYNC_RESET_SEL_DEFAULT 0x00000002
+#define mmLB5_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000
+#define mmLB5_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000
+#define mmLB5_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000
+#define mmLB5_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000
+#define mmLB5_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000
+#define mmLB5_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000
+#define mmLB5_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000
+#define mmLB5_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
+#define mmLB5_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
+#define mmLB5_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
+#define mmLB5_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
+#define mmLB5_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
+#define mmLB5_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
+#define mmLB5_LB_BUFFER_STATUS_DEFAULT 0x00000002
+#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
+#define mmLB5_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000
+#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000
+#define mmLB5_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002
+#define mmLB5_DC_MVP_LB_CONTROL_DEFAULT 0x00000001
+
+
+// addressBlock: dce_dc_dcfe5_dispdec
+#define mmDCFE5_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000
+#define mmDCFE5_DCFE_SOFT_RESET_DEFAULT 0x00000000
+#define mmDCFE5_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000
+#define mmDCFE5_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000
+#define mmDCFE5_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000
+#define mmDCFE5_DCFE_MISC_DEFAULT 0x00000001
+#define mmDCFE5_DCFE_FLUSH_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_perfmon8_dispdec
+#define mmDC_PERFMON8_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON8_PERFCOUNTER_STATE_DEFAULT 0x00000000
+#define mmDC_PERFMON8_PERFMON_CNTL_DEFAULT 0x00000100
+#define mmDC_PERFMON8_PERFMON_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+#define mmDC_PERFMON8_PERFMON_HI_DEFAULT 0x00000000
+#define mmDC_PERFMON8_PERFMON_LOW_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dmif_pg5_dispdec
+#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
+#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
+#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777
+#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000
+#define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000
+#define mmDMIF_PG5_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000
+#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
+#define mmDMIF_PG5_DPG_DVMM_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_scl5_dispdec
+#define mmSCL5_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000
+#define mmSCL5_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
+#define mmSCL5_SCL_MODE_DEFAULT 0x00000000
+#define mmSCL5_SCL_TAP_CONTROL_DEFAULT 0x00000000
+#define mmSCL5_SCL_CONTROL_DEFAULT 0x00000000
+#define mmSCL5_SCL_BYPASS_CONTROL_DEFAULT 0x00000000
+#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
+#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
+#define mmSCL5_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
+#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+#define mmSCL5_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000
+#define mmSCL5_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000
+#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+#define mmSCL5_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000
+#define mmSCL5_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
+#define mmSCL5_SCL_ROUND_OFFSET_DEFAULT 0x80000000
+#define mmSCL5_SCL_UPDATE_DEFAULT 0x00000000
+#define mmSCL5_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000
+#define mmSCL5_SCL_ALU_CONTROL_DEFAULT 0x00000000
+#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000
+#define mmSCL5_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
+#define mmSCL5_VIEWPORT_START_DEFAULT 0x00000000
+#define mmSCL5_VIEWPORT_SIZE_DEFAULT 0x00000000
+#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
+#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
+#define mmSCL5_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000
+#define mmSCL5_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000
+#define mmSCL5_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000
+#define mmSCL5_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_blnd5_dispdec
+#define mmBLND5_BLND_CONTROL_DEFAULT 0xff0220ff
+#define mmBLND5_BLND_SM_CONTROL2_DEFAULT 0x00000000
+#define mmBLND5_BLND_CONTROL2_DEFAULT 0x00000010
+#define mmBLND5_BLND_UPDATE_DEFAULT 0x00000000
+#define mmBLND5_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
+#define mmBLND5_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000
+#define mmBLND5_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_crtc5_dispdec
+#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
+#define mmCRTC5_CRTC_H_TOTAL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_H_BLANK_START_END_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_H_SYNC_A_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_H_SYNC_B_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_VBI_END_DEFAULT 0x00000003
+#define mmCRTC5_CRTC_V_TOTAL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_V_BLANK_START_END_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_V_SYNC_A_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_V_SYNC_B_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_TRIGA_CNTL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_TRIGB_CNTL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_FLOW_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_CONTROL_DEFAULT 0x80400110
+#define mmCRTC5_CRTC_BLANK_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_STATUS_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_STATUS_POSITION_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_COUNT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_COUNT_RESET_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_STEREO_STATUS_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_STEREO_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002
+#define mmCRTC5_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_UPDATE_LOCK_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
+#define mmCRTC5_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
+#define mmCRTC5_CRTC_MVP_STATUS_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_MASTER_EN_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
+#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_BLACK_COLOR_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_CRC_CNTL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_CRC0_DATA_B_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_CRC1_DATA_B_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
+#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
+#define mmCRTC5_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_GSL_WINDOW_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_GSL_CONTROL_DEFAULT 0x00020000
+#define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTC5_CRTC_DRR_CONTROL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_fmt5_dispdec
+#define mmFMT5_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000
+#define mmFMT5_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000
+#define mmFMT5_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000
+#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000
+#define mmFMT5_FMT_CONTROL_DEFAULT 0x00000000
+#define mmFMT5_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000
+#define mmFMT5_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000
+#define mmFMT5_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099
+#define mmFMT5_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd
+#define mmFMT5_FMT_CLAMP_CNTL_DEFAULT 0x00000000
+#define mmFMT5_FMT_CRC_CNTL_DEFAULT 0x01000040
+#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff
+#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff
+#define mmFMT5_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000
+#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000
+#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000
+#define mmFMT5_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_unp0_dispdec
+#define mmUNP0_UNP_GRPH_ENABLE_DEFAULT 0x00000001
+#define mmUNP0_UNP_GRPH_CONTROL_DEFAULT 0x0a008008
+#define mmUNP0_UNP_GRPH_CONTROL_C_DEFAULT 0x00008000
+#define mmUNP0_UNP_GRPH_CONTROL_EXP_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_SWAP_CNTL_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_PITCH_L_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_PITCH_C_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_X_START_L_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_X_START_C_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_Y_START_L_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_Y_START_C_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_X_END_L_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_X_END_C_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_Y_END_L_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_Y_END_C_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_UPDATE_DEFAULT 0x00000000
+#define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x0000ffff
+#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_DEFAULT 0x00000000
+#define mmUNP0_UNP_DVMM_PTE_CONTROL_DEFAULT 0x00004000
+#define mmUNP0_UNP_DVMM_PTE_CONTROL_C_DEFAULT 0x00004000
+#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
+#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C_DEFAULT 0x00002220
+#define mmUNP0_UNP_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00002020
+#define mmUNP0_UNP_FLIP_CONTROL_DEFAULT 0x00000001
+#define mmUNP0_UNP_CRC_CONTROL_DEFAULT 0x00000000
+#define mmUNP0_UNP_CRC_MASK_DEFAULT 0x00000000
+#define mmUNP0_UNP_CRC_CURRENT_DEFAULT 0x00000000
+#define mmUNP0_UNP_CRC_LAST_DEFAULT 0x00000000
+#define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000100
+#define mmUNP0_UNP_HW_ROTATION_DEFAULT 0x00000010
+
+
+// addressBlock: dce_dc_lbv0_dispdec
+#define mmLBV0_LBV_DATA_FORMAT_DEFAULT 0x00000000
+#define mmLBV0_LBV_MEMORY_CTRL_DEFAULT 0x000006b0
+#define mmLBV0_LBV_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
+#define mmLBV0_LBV_DESKTOP_HEIGHT_DEFAULT 0x00000000
+#define mmLBV0_LBV_VLINE_START_END_DEFAULT 0x00000000
+#define mmLBV0_LBV_VLINE2_START_END_DEFAULT 0x00000000
+#define mmLBV0_LBV_V_COUNTER_DEFAULT 0x00000000
+#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
+#define mmLBV0_LBV_V_COUNTER_CHROMA_DEFAULT 0x00000000
+#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA_DEFAULT 0x00000000
+#define mmLBV0_LBV_INTERRUPT_MASK_DEFAULT 0x00000000
+#define mmLBV0_LBV_VLINE_STATUS_DEFAULT 0x00000000
+#define mmLBV0_LBV_VLINE2_STATUS_DEFAULT 0x00000000
+#define mmLBV0_LBV_VBLANK_STATUS_DEFAULT 0x00000000
+#define mmLBV0_LBV_SYNC_RESET_SEL_DEFAULT 0x00000002
+#define mmLBV0_LBV_BLACK_KEYER_R_CR_DEFAULT 0x00000000
+#define mmLBV0_LBV_BLACK_KEYER_G_Y_DEFAULT 0x00000000
+#define mmLBV0_LBV_BLACK_KEYER_B_CB_DEFAULT 0x00000000
+#define mmLBV0_LBV_KEYER_COLOR_CTRL_DEFAULT 0x00000000
+#define mmLBV0_LBV_KEYER_COLOR_R_CR_DEFAULT 0x00000000
+#define mmLBV0_LBV_KEYER_COLOR_G_Y_DEFAULT 0x00000000
+#define mmLBV0_LBV_KEYER_COLOR_B_CB_DEFAULT 0x00000000
+#define mmLBV0_LBV_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
+#define mmLBV0_LBV_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
+#define mmLBV0_LBV_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
+#define mmLBV0_LBV_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
+#define mmLBV0_LBV_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
+#define mmLBV0_LBV_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
+#define mmLBV0_LBV_BUFFER_STATUS_DEFAULT 0x12000002
+#define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_sclv0_dispdec
+#define mmSCLV0_SCLV_COEF_RAM_SELECT_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_MODE_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_TAP_CONTROL_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_CONTROL_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_HORZ_FILTER_INIT_DEFAULT 0x01000000
+#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_HORZ_FILTER_INIT_C_DEFAULT 0x01000000
+#define mmSCLV0_SCLV_VERT_FILTER_CONTROL_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_VERT_FILTER_INIT_DEFAULT 0x01000000
+#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
+#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_VERT_FILTER_INIT_C_DEFAULT 0x01000000
+#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000
+#define mmSCLV0_SCLV_ROUND_OFFSET_DEFAULT 0x80000000
+#define mmSCLV0_SCLV_UPDATE_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_ALU_CONTROL_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_VIEWPORT_START_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_VIEWPORT_SIZE_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_VIEWPORT_START_C_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_VIEWPORT_SIZE_C_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_MODE_CHANGE_DET1_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_MODE_CHANGE_DET2_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_MODE_CHANGE_DET3_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_MODE_CHANGE_MASK_DEFAULT 0x00000000
+#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_DEFAULT 0x01000000
+#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C_DEFAULT 0x01000000
+
+
+// addressBlock: dce_dc_col_man0_dispdec
+#define mmCOL_MAN0_COL_MAN_UPDATE_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL_DEFAULT 0x00000000
+#define mmCOL_MAN0_INPUT_CSC_C11_C12_A_DEFAULT 0x00002000
+#define mmCOL_MAN0_INPUT_CSC_C13_C14_A_DEFAULT 0x00000000
+#define mmCOL_MAN0_INPUT_CSC_C21_C22_A_DEFAULT 0x20000000
+#define mmCOL_MAN0_INPUT_CSC_C23_C24_A_DEFAULT 0x00000000
+#define mmCOL_MAN0_INPUT_CSC_C31_C32_A_DEFAULT 0x00000000
+#define mmCOL_MAN0_INPUT_CSC_C33_C34_A_DEFAULT 0x00002000
+#define mmCOL_MAN0_INPUT_CSC_C11_C12_B_DEFAULT 0x00002000
+#define mmCOL_MAN0_INPUT_CSC_C13_C14_B_DEFAULT 0x00000000
+#define mmCOL_MAN0_INPUT_CSC_C21_C22_B_DEFAULT 0x20000000
+#define mmCOL_MAN0_INPUT_CSC_C23_C24_B_DEFAULT 0x00000000
+#define mmCOL_MAN0_INPUT_CSC_C31_C32_B_DEFAULT 0x00000000
+#define mmCOL_MAN0_INPUT_CSC_C33_C34_B_DEFAULT 0x00002000
+#define mmCOL_MAN0_PRESCALE_CONTROL_DEFAULT 0x00000000
+#define mmCOL_MAN0_PRESCALE_VALUES_R_DEFAULT 0x20000000
+#define mmCOL_MAN0_PRESCALE_VALUES_G_DEFAULT 0x20000000
+#define mmCOL_MAN0_PRESCALE_VALUES_B_DEFAULT 0x20000000
+#define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
+#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A_DEFAULT 0x00002000
+#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A_DEFAULT 0x00000000
+#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A_DEFAULT 0x20000000
+#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A_DEFAULT 0x00000000
+#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A_DEFAULT 0x00000000
+#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A_DEFAULT 0x00002000
+#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B_DEFAULT 0x00002000
+#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B_DEFAULT 0x00000000
+#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B_DEFAULT 0x20000000
+#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B_DEFAULT 0x00000000
+#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B_DEFAULT 0x00000000
+#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B_DEFAULT 0x00002000
+#define mmCOL_MAN0_DENORM_CLAMP_CONTROL_DEFAULT 0x00000000
+#define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR_DEFAULT 0x00000fff
+#define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y_DEFAULT 0x00000fff
+#define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB_DEFAULT 0x00000fff
+#define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
+#define mmCOL_MAN0_PACK_FIFO_ERROR_DEFAULT 0x00000000
+#define mmCOL_MAN0_OUTPUT_FIFO_ERROR_DEFAULT 0x00000000
+#define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL_DEFAULT 0x00000000
+#define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX_DEFAULT 0x00000000
+#define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR_DEFAULT 0x00000000
+#define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA_DEFAULT 0x00000000
+#define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2_DEFAULT 0x03800000
+#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B_DEFAULT 0xffff0000
+#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G_DEFAULT 0xffff0000
+#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R_DEFAULT 0xffff0000
+#define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
+#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
+#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
+#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
+
+
+// addressBlock: dce_dc_dcfev0_dispdec
+#define mmDCFEV0_DCFEV_CLOCK_CONTROL_DEFAULT 0x00000000
+#define mmDCFEV0_DCFEV_SOFT_RESET_DEFAULT 0x00000000
+#define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL_DEFAULT 0x00000000
+#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL_DEFAULT 0x00000000
+#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS_DEFAULT 0x00000000
+#define mmDCFEV0_DCFEV_MEM_PWR_CTRL_DEFAULT 0x00000000
+#define mmDCFEV0_DCFEV_MEM_PWR_CTRL2_DEFAULT 0x00000000
+#define mmDCFEV0_DCFEV_MEM_PWR_STATUS_DEFAULT 0x00000000
+#define mmDCFEV0_DCFEV_L_FLUSH_DEFAULT 0x00000000
+#define mmDCFEV0_DCFEV_C_FLUSH_DEFAULT 0x00000000
+#define mmDCFEV0_DCFEV_MISC_DEFAULT 0x00000001
+
+
+// addressBlock: dce_dc_dc_perfmon11_dispdec
+#define mmDC_PERFMON11_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON11_PERFCOUNTER_STATE_DEFAULT 0x00000000
+#define mmDC_PERFMON11_PERFMON_CNTL_DEFAULT 0x00000100
+#define mmDC_PERFMON11_PERFMON_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+#define mmDC_PERFMON11_PERFMON_HI_DEFAULT 0x00000000
+#define mmDC_PERFMON11_PERFMON_LOW_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dmifv_pg0_dispdec
+#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
+#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
+#define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303
+#define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
+#define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL_DEFAULT 0x00003000
+#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200
+#define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000
+#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200
+#define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM_DEFAULT 0x00000000
+#define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
+#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
+#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
+#define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303
+#define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
+#define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL_DEFAULT 0x00003000
+#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200
+#define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000
+#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200
+#define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM_DEFAULT 0x00000000
+#define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_blndv0_dispdec
+#define mmBLNDV0_BLNDV_CONTROL_DEFAULT 0xff0220ff
+#define mmBLNDV0_BLNDV_SM_CONTROL2_DEFAULT 0x00000000
+#define mmBLNDV0_BLNDV_CONTROL2_DEFAULT 0x00000010
+#define mmBLNDV0_BLNDV_UPDATE_DEFAULT 0x00000000
+#define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
+#define mmBLNDV0_BLNDV_V_UPDATE_LOCK_DEFAULT 0x80000000
+#define mmBLNDV0_BLNDV_REG_UPDATE_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_crtcv0_dispdec
+#define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
+#define mmCRTCV0_CRTCV_H_TOTAL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_H_BLANK_START_END_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_H_SYNC_A_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_H_SYNC_A_CNTL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_H_SYNC_B_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_H_SYNC_B_CNTL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_VBI_END_DEFAULT 0x00000003
+#define mmCRTCV0_CRTCV_V_TOTAL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_V_TOTAL_MIN_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_V_TOTAL_MAX_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_V_TOTAL_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_V_BLANK_START_END_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_V_SYNC_A_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_V_SYNC_A_CNTL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_V_SYNC_B_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_V_SYNC_B_CNTL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_DTMTEST_CNTL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_TRIGA_CNTL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_TRIGB_CNTL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_FLOW_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_AVSYNC_COUNTER_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_CONTROL_DEFAULT 0x80400110
+#define mmCRTCV0_CRTCV_BLANK_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_INTERLACE_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_INTERLACE_STATUS_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_STATUS_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_STATUS_POSITION_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_NOM_VERT_POSITION_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_STATUS_VF_COUNT_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_STATUS_HV_COUNT_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_COUNT_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_COUNT_RESET_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_STEREO_STATUS_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_STEREO_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_SNAPSHOT_STATUS_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_SNAPSHOT_POSITION_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_SNAPSHOT_FRAME_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_START_LINE_CONTROL_DEFAULT 0x00003002
+#define mmCRTCV0_CRTCV_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_UPDATE_LOCK_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
+#define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
+#define mmCRTCV0_CRTCV_MVP_STATUS_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_MASTER_EN_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
+#define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_BLACK_COLOR_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_BLACK_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_CRC_CNTL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_CRC0_DATA_RG_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_CRC0_DATA_B_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_CRC1_DATA_RG_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_CRC1_DATA_B_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
+#define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
+#define mmCRTCV0_CRTCV_GSL_VSYNC_GAP_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_GSL_WINDOW_DEFAULT 0x00000000
+#define mmCRTCV0_CRTCV_GSL_CONTROL_DEFAULT 0x00020000
+
+
+// addressBlock: dce_dc_unp1_dispdec
+#define mmUNP1_UNP_GRPH_ENABLE_DEFAULT 0x00000001
+#define mmUNP1_UNP_GRPH_CONTROL_DEFAULT 0x0a008008
+#define mmUNP1_UNP_GRPH_CONTROL_C_DEFAULT 0x00008000
+#define mmUNP1_UNP_GRPH_CONTROL_EXP_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_SWAP_CNTL_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_PITCH_L_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_PITCH_C_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_X_START_L_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_X_START_C_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_Y_START_L_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_Y_START_C_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_X_END_L_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_X_END_C_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_Y_END_L_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_Y_END_C_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_UPDATE_DEFAULT 0x00000000
+#define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x0000ffff
+#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_DEFAULT 0x00000000
+#define mmUNP1_UNP_DVMM_PTE_CONTROL_DEFAULT 0x00004000
+#define mmUNP1_UNP_DVMM_PTE_CONTROL_C_DEFAULT 0x00004000
+#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220
+#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C_DEFAULT 0x00002220
+#define mmUNP1_UNP_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00002020
+#define mmUNP1_UNP_FLIP_CONTROL_DEFAULT 0x00000001
+#define mmUNP1_UNP_CRC_CONTROL_DEFAULT 0x00000000
+#define mmUNP1_UNP_CRC_MASK_DEFAULT 0x00000000
+#define mmUNP1_UNP_CRC_CURRENT_DEFAULT 0x00000000
+#define mmUNP1_UNP_CRC_LAST_DEFAULT 0x00000000
+#define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000100
+#define mmUNP1_UNP_HW_ROTATION_DEFAULT 0x00000010
+
+
+// addressBlock: dce_dc_lbv1_dispdec
+#define mmLBV1_LBV_DATA_FORMAT_DEFAULT 0x00000000
+#define mmLBV1_LBV_MEMORY_CTRL_DEFAULT 0x000006b0
+#define mmLBV1_LBV_MEMORY_SIZE_STATUS_DEFAULT 0x00000000
+#define mmLBV1_LBV_DESKTOP_HEIGHT_DEFAULT 0x00000000
+#define mmLBV1_LBV_VLINE_START_END_DEFAULT 0x00000000
+#define mmLBV1_LBV_VLINE2_START_END_DEFAULT 0x00000000
+#define mmLBV1_LBV_V_COUNTER_DEFAULT 0x00000000
+#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000
+#define mmLBV1_LBV_V_COUNTER_CHROMA_DEFAULT 0x00000000
+#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA_DEFAULT 0x00000000
+#define mmLBV1_LBV_INTERRUPT_MASK_DEFAULT 0x00000000
+#define mmLBV1_LBV_VLINE_STATUS_DEFAULT 0x00000000
+#define mmLBV1_LBV_VLINE2_STATUS_DEFAULT 0x00000000
+#define mmLBV1_LBV_VBLANK_STATUS_DEFAULT 0x00000000
+#define mmLBV1_LBV_SYNC_RESET_SEL_DEFAULT 0x00000002
+#define mmLBV1_LBV_BLACK_KEYER_R_CR_DEFAULT 0x00000000
+#define mmLBV1_LBV_BLACK_KEYER_G_Y_DEFAULT 0x00000000
+#define mmLBV1_LBV_BLACK_KEYER_B_CB_DEFAULT 0x00000000
+#define mmLBV1_LBV_KEYER_COLOR_CTRL_DEFAULT 0x00000000
+#define mmLBV1_LBV_KEYER_COLOR_R_CR_DEFAULT 0x00000000
+#define mmLBV1_LBV_KEYER_COLOR_G_Y_DEFAULT 0x00000000
+#define mmLBV1_LBV_KEYER_COLOR_B_CB_DEFAULT 0x00000000
+#define mmLBV1_LBV_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000
+#define mmLBV1_LBV_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000
+#define mmLBV1_LBV_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000
+#define mmLBV1_LBV_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000
+#define mmLBV1_LBV_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010
+#define mmLBV1_LBV_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000
+#define mmLBV1_LBV_BUFFER_STATUS_DEFAULT 0x12000002
+#define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_sclv1_dispdec
+#define mmSCLV1_SCLV_COEF_RAM_SELECT_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_COEF_RAM_TAP_DATA_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_MODE_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_TAP_CONTROL_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_CONTROL_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_HORZ_FILTER_CONTROL_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_HORZ_FILTER_INIT_DEFAULT 0x01000000
+#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_HORZ_FILTER_INIT_C_DEFAULT 0x01000000
+#define mmSCLV1_SCLV_VERT_FILTER_CONTROL_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_VERT_FILTER_INIT_DEFAULT 0x01000000
+#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000
+#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_VERT_FILTER_INIT_C_DEFAULT 0x01000000
+#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000
+#define mmSCLV1_SCLV_ROUND_OFFSET_DEFAULT 0x80000000
+#define mmSCLV1_SCLV_UPDATE_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_ALU_CONTROL_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_VIEWPORT_START_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_VIEWPORT_SIZE_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_VIEWPORT_START_C_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_VIEWPORT_SIZE_C_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_MODE_CHANGE_DET1_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_MODE_CHANGE_DET2_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_MODE_CHANGE_DET3_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_MODE_CHANGE_MASK_DEFAULT 0x00000000
+#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_DEFAULT 0x01000000
+#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C_DEFAULT 0x01000000
+
+
+// addressBlock: dce_dc_col_man1_dispdec
+#define mmCOL_MAN1_COL_MAN_UPDATE_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL_DEFAULT 0x00000000
+#define mmCOL_MAN1_INPUT_CSC_C11_C12_A_DEFAULT 0x00002000
+#define mmCOL_MAN1_INPUT_CSC_C13_C14_A_DEFAULT 0x00000000
+#define mmCOL_MAN1_INPUT_CSC_C21_C22_A_DEFAULT 0x20000000
+#define mmCOL_MAN1_INPUT_CSC_C23_C24_A_DEFAULT 0x00000000
+#define mmCOL_MAN1_INPUT_CSC_C31_C32_A_DEFAULT 0x00000000
+#define mmCOL_MAN1_INPUT_CSC_C33_C34_A_DEFAULT 0x00002000
+#define mmCOL_MAN1_INPUT_CSC_C11_C12_B_DEFAULT 0x00002000
+#define mmCOL_MAN1_INPUT_CSC_C13_C14_B_DEFAULT 0x00000000
+#define mmCOL_MAN1_INPUT_CSC_C21_C22_B_DEFAULT 0x20000000
+#define mmCOL_MAN1_INPUT_CSC_C23_C24_B_DEFAULT 0x00000000
+#define mmCOL_MAN1_INPUT_CSC_C31_C32_B_DEFAULT 0x00000000
+#define mmCOL_MAN1_INPUT_CSC_C33_C34_B_DEFAULT 0x00002000
+#define mmCOL_MAN1_PRESCALE_CONTROL_DEFAULT 0x00000000
+#define mmCOL_MAN1_PRESCALE_VALUES_R_DEFAULT 0x20000000
+#define mmCOL_MAN1_PRESCALE_VALUES_G_DEFAULT 0x20000000
+#define mmCOL_MAN1_PRESCALE_VALUES_B_DEFAULT 0x20000000
+#define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000
+#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A_DEFAULT 0x00002000
+#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A_DEFAULT 0x00000000
+#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A_DEFAULT 0x20000000
+#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A_DEFAULT 0x00000000
+#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A_DEFAULT 0x00000000
+#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A_DEFAULT 0x00002000
+#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B_DEFAULT 0x00002000
+#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B_DEFAULT 0x00000000
+#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B_DEFAULT 0x20000000
+#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B_DEFAULT 0x00000000
+#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B_DEFAULT 0x00000000
+#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B_DEFAULT 0x00002000
+#define mmCOL_MAN1_DENORM_CLAMP_CONTROL_DEFAULT 0x00000000
+#define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR_DEFAULT 0x00000fff
+#define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y_DEFAULT 0x00000fff
+#define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB_DEFAULT 0x00000fff
+#define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000
+#define mmCOL_MAN1_PACK_FIFO_ERROR_DEFAULT 0x00000000
+#define mmCOL_MAN1_OUTPUT_FIFO_ERROR_DEFAULT 0x00000000
+#define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL_DEFAULT 0x00000000
+#define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX_DEFAULT 0x00000000
+#define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR_DEFAULT 0x00000000
+#define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA_DEFAULT 0x00000000
+#define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2_DEFAULT 0x03800000
+#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B_DEFAULT 0xffff0000
+#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G_DEFAULT 0xffff0000
+#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R_DEFAULT 0xffff0000
+#define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000
+#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000
+#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000
+#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000
+
+
+// addressBlock: dce_dc_dcfev1_dispdec
+#define mmDCFEV1_DCFEV_CLOCK_CONTROL_DEFAULT 0x00000000
+#define mmDCFEV1_DCFEV_SOFT_RESET_DEFAULT 0x00000000
+#define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL_DEFAULT 0x00000000
+#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL_DEFAULT 0x00000000
+#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS_DEFAULT 0x00000000
+#define mmDCFEV1_DCFEV_MEM_PWR_CTRL_DEFAULT 0x00000000
+#define mmDCFEV1_DCFEV_MEM_PWR_CTRL2_DEFAULT 0x00000000
+#define mmDCFEV1_DCFEV_MEM_PWR_STATUS_DEFAULT 0x00000000
+#define mmDCFEV1_DCFEV_L_FLUSH_DEFAULT 0x00000000
+#define mmDCFEV1_DCFEV_C_FLUSH_DEFAULT 0x00000000
+#define mmDCFEV1_DCFEV_MISC_DEFAULT 0x00000001
+
+
+// addressBlock: dce_dc_dc_perfmon12_dispdec
+#define mmDC_PERFMON12_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON12_PERFCOUNTER_STATE_DEFAULT 0x00000000
+#define mmDC_PERFMON12_PERFMON_CNTL_DEFAULT 0x00000100
+#define mmDC_PERFMON12_PERFMON_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+#define mmDC_PERFMON12_PERFMON_HI_DEFAULT 0x00000000
+#define mmDC_PERFMON12_PERFMON_LOW_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dmifv_pg1_dispdec
+#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
+#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
+#define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303
+#define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
+#define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL_DEFAULT 0x00003000
+#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200
+#define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000
+#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200
+#define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM_DEFAULT 0x00000000
+#define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
+#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000
+#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000
+#define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303
+#define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000
+#define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL_DEFAULT 0x00003000
+#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200
+#define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000
+#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200
+#define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM_DEFAULT 0x00000000
+#define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_blndv1_dispdec
+#define mmBLNDV1_BLNDV_CONTROL_DEFAULT 0xff0220ff
+#define mmBLNDV1_BLNDV_SM_CONTROL2_DEFAULT 0x00000000
+#define mmBLNDV1_BLNDV_CONTROL2_DEFAULT 0x00000010
+#define mmBLNDV1_BLNDV_UPDATE_DEFAULT 0x00000000
+#define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000
+#define mmBLNDV1_BLNDV_V_UPDATE_LOCK_DEFAULT 0x80000000
+#define mmBLNDV1_BLNDV_REG_UPDATE_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_crtcv1_dispdec
+#define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM_DEFAULT 0x00000040
+#define mmCRTCV1_CRTCV_H_TOTAL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_H_BLANK_START_END_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_H_SYNC_A_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_H_SYNC_A_CNTL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_H_SYNC_B_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_H_SYNC_B_CNTL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_VBI_END_DEFAULT 0x00000003
+#define mmCRTCV1_CRTCV_V_TOTAL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_V_TOTAL_MIN_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_V_TOTAL_MAX_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_V_TOTAL_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_V_BLANK_START_END_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_V_SYNC_A_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_V_SYNC_A_CNTL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_V_SYNC_B_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_V_SYNC_B_CNTL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_DTMTEST_CNTL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_TRIGA_CNTL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_TRIGB_CNTL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_FLOW_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_AVSYNC_COUNTER_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_CONTROL_DEFAULT 0x80400110
+#define mmCRTCV1_CRTCV_BLANK_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_INTERLACE_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_INTERLACE_STATUS_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_STATUS_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_STATUS_POSITION_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_NOM_VERT_POSITION_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_STATUS_VF_COUNT_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_STATUS_HV_COUNT_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_COUNT_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_COUNT_RESET_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_STEREO_STATUS_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_STEREO_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_SNAPSHOT_STATUS_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_SNAPSHOT_POSITION_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_SNAPSHOT_FRAME_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_START_LINE_CONTROL_DEFAULT 0x00003002
+#define mmCRTCV1_CRTCV_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_UPDATE_LOCK_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK_DEFAULT 0x00010000
+#define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008
+#define mmCRTCV1_CRTCV_MVP_STATUS_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_MASTER_EN_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000
+#define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_BLACK_COLOR_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_BLACK_COLOR_EXT_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_CRC_CNTL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_CRC0_DATA_RG_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_CRC0_DATA_B_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_CRC1_DATA_RG_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_CRC1_DATA_B_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000
+#define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010
+#define mmCRTCV1_CRTCV_GSL_VSYNC_GAP_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_GSL_WINDOW_DEFAULT 0x00000000
+#define mmCRTCV1_CRTCV_GSL_CONTROL_DEFAULT 0x00020000
+
+
+// addressBlock: dce_dc_hpd0_dispdec
+#define mmHPD0_DC_HPD_INT_STATUS_DEFAULT 0x00000000
+#define mmHPD0_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
+#define mmHPD0_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
+#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
+#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_hpd1_dispdec
+#define mmHPD1_DC_HPD_INT_STATUS_DEFAULT 0x00000000
+#define mmHPD1_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
+#define mmHPD1_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
+#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
+#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_hpd2_dispdec
+#define mmHPD2_DC_HPD_INT_STATUS_DEFAULT 0x00000000
+#define mmHPD2_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
+#define mmHPD2_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
+#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
+#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_hpd3_dispdec
+#define mmHPD3_DC_HPD_INT_STATUS_DEFAULT 0x00000000
+#define mmHPD3_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
+#define mmHPD3_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
+#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
+#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_hpd4_dispdec
+#define mmHPD4_DC_HPD_INT_STATUS_DEFAULT 0x00000000
+#define mmHPD4_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
+#define mmHPD4_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
+#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
+#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_hpd5_dispdec
+#define mmHPD5_DC_HPD_INT_STATUS_DEFAULT 0x00000000
+#define mmHPD5_DC_HPD_INT_CONTROL_DEFAULT 0x00000000
+#define mmHPD5_DC_HPD_CONTROL_DEFAULT 0x10fa09c4
+#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000
+#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_perfmon2_dispdec
+#define mmDC_PERFMON2_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON2_PERFCOUNTER_STATE_DEFAULT 0x00000000
+#define mmDC_PERFMON2_PERFMON_CNTL_DEFAULT 0x00000100
+#define mmDC_PERFMON2_PERFMON_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+#define mmDC_PERFMON2_PERFMON_HI_DEFAULT 0x00000000
+#define mmDC_PERFMON2_PERFMON_LOW_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dp_aux0_dispdec
+#define mmDP_AUX0_AUX_CONTROL_DEFAULT 0x01040000
+#define mmDP_AUX0_AUX_SW_CONTROL_DEFAULT 0x00000000
+#define mmDP_AUX0_AUX_ARB_CONTROL_DEFAULT 0x00000000
+#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmDP_AUX0_AUX_SW_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX0_AUX_LS_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX0_AUX_SW_DATA_DEFAULT 0x00000000
+#define mmDP_AUX0_AUX_LS_DATA_DEFAULT 0x00000000
+#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
+#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
+#define mmDP_AUX0_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX0_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dp_aux1_dispdec
+#define mmDP_AUX1_AUX_CONTROL_DEFAULT 0x01040000
+#define mmDP_AUX1_AUX_SW_CONTROL_DEFAULT 0x00000000
+#define mmDP_AUX1_AUX_ARB_CONTROL_DEFAULT 0x00000000
+#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmDP_AUX1_AUX_SW_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX1_AUX_LS_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX1_AUX_SW_DATA_DEFAULT 0x00000000
+#define mmDP_AUX1_AUX_LS_DATA_DEFAULT 0x00000000
+#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
+#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
+#define mmDP_AUX1_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX1_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dp_aux2_dispdec
+#define mmDP_AUX2_AUX_CONTROL_DEFAULT 0x01040000
+#define mmDP_AUX2_AUX_SW_CONTROL_DEFAULT 0x00000000
+#define mmDP_AUX2_AUX_ARB_CONTROL_DEFAULT 0x00000000
+#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmDP_AUX2_AUX_SW_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX2_AUX_LS_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX2_AUX_SW_DATA_DEFAULT 0x00000000
+#define mmDP_AUX2_AUX_LS_DATA_DEFAULT 0x00000000
+#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
+#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
+#define mmDP_AUX2_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX2_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dp_aux3_dispdec
+#define mmDP_AUX3_AUX_CONTROL_DEFAULT 0x01040000
+#define mmDP_AUX3_AUX_SW_CONTROL_DEFAULT 0x00000000
+#define mmDP_AUX3_AUX_ARB_CONTROL_DEFAULT 0x00000000
+#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmDP_AUX3_AUX_SW_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX3_AUX_LS_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX3_AUX_SW_DATA_DEFAULT 0x00000000
+#define mmDP_AUX3_AUX_LS_DATA_DEFAULT 0x00000000
+#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
+#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
+#define mmDP_AUX3_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX3_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dp_aux4_dispdec
+#define mmDP_AUX4_AUX_CONTROL_DEFAULT 0x01040000
+#define mmDP_AUX4_AUX_SW_CONTROL_DEFAULT 0x00000000
+#define mmDP_AUX4_AUX_ARB_CONTROL_DEFAULT 0x00000000
+#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmDP_AUX4_AUX_SW_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX4_AUX_LS_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX4_AUX_SW_DATA_DEFAULT 0x00000000
+#define mmDP_AUX4_AUX_LS_DATA_DEFAULT 0x00000000
+#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
+#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
+#define mmDP_AUX4_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX4_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dp_aux5_dispdec
+#define mmDP_AUX5_AUX_CONTROL_DEFAULT 0x01040000
+#define mmDP_AUX5_AUX_SW_CONTROL_DEFAULT 0x00000000
+#define mmDP_AUX5_AUX_ARB_CONTROL_DEFAULT 0x00000000
+#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmDP_AUX5_AUX_SW_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX5_AUX_LS_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX5_AUX_SW_DATA_DEFAULT 0x00000000
+#define mmDP_AUX5_AUX_LS_DATA_DEFAULT 0x00000000
+#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000
+#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002
+#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210
+#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000
+#define mmDP_AUX5_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX5_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000
+#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000
+#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dig0_dispdec
+#define mmDIG0_DIG_FE_CNTL_DEFAULT 0x00000000
+#define mmDIG0_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
+#define mmDIG0_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
+#define mmDIG0_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
+#define mmDIG0_DIG_TEST_PATTERN_DEFAULT 0x00000060
+#define mmDIG0_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
+#define mmDIG0_DIG_FIFO_STATUS_DEFAULT 0x00000000
+#define mmDIG0_HDMI_CONTROL_DEFAULT 0x00010001
+#define mmDIG0_HDMI_STATUS_DEFAULT 0x00000000
+#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
+#define mmDIG0_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
+#define mmDIG0_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+#define mmDIG0_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+#define mmDIG0_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
+#define mmDIG0_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmDIG0_HDMI_GC_DEFAULT 0x00000004
+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
+#define mmDIG0_AFMT_ISRC1_0_DEFAULT 0x00000000
+#define mmDIG0_AFMT_ISRC1_1_DEFAULT 0x00000000
+#define mmDIG0_AFMT_ISRC1_2_DEFAULT 0x00000000
+#define mmDIG0_AFMT_ISRC1_3_DEFAULT 0x00000000
+#define mmDIG0_AFMT_ISRC1_4_DEFAULT 0x00000000
+#define mmDIG0_AFMT_ISRC2_0_DEFAULT 0x00000000
+#define mmDIG0_AFMT_ISRC2_1_DEFAULT 0x00000000
+#define mmDIG0_AFMT_ISRC2_2_DEFAULT 0x00000000
+#define mmDIG0_AFMT_ISRC2_3_DEFAULT 0x00000000
+#define mmDIG0_AFMT_AVI_INFO0_DEFAULT 0x00000000
+#define mmDIG0_AFMT_AVI_INFO1_DEFAULT 0x00000000
+#define mmDIG0_AFMT_AVI_INFO2_DEFAULT 0x00000000
+#define mmDIG0_AFMT_AVI_INFO3_DEFAULT 0x02000000
+#define mmDIG0_AFMT_MPEG_INFO0_DEFAULT 0x00000000
+#define mmDIG0_AFMT_MPEG_INFO1_DEFAULT 0x00000000
+#define mmDIG0_AFMT_GENERIC_HDR_DEFAULT 0x00000000
+#define mmDIG0_AFMT_GENERIC_0_DEFAULT 0x00000000
+#define mmDIG0_AFMT_GENERIC_1_DEFAULT 0x00000000
+#define mmDIG0_AFMT_GENERIC_2_DEFAULT 0x00000000
+#define mmDIG0_AFMT_GENERIC_3_DEFAULT 0x00000000
+#define mmDIG0_AFMT_GENERIC_4_DEFAULT 0x00000000
+#define mmDIG0_AFMT_GENERIC_5_DEFAULT 0x00000000
+#define mmDIG0_AFMT_GENERIC_6_DEFAULT 0x00000000
+#define mmDIG0_AFMT_GENERIC_7_DEFAULT 0x00000000
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
+#define mmDIG0_HDMI_ACR_32_0_DEFAULT 0x00000000
+#define mmDIG0_HDMI_ACR_32_1_DEFAULT 0x00000000
+#define mmDIG0_HDMI_ACR_44_0_DEFAULT 0x00000000
+#define mmDIG0_HDMI_ACR_44_1_DEFAULT 0x00000000
+#define mmDIG0_HDMI_ACR_48_0_DEFAULT 0x00000000
+#define mmDIG0_HDMI_ACR_48_1_DEFAULT 0x00000000
+#define mmDIG0_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
+#define mmDIG0_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
+#define mmDIG0_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
+#define mmDIG0_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
+#define mmDIG0_AFMT_60958_0_DEFAULT 0x00000000
+#define mmDIG0_AFMT_60958_1_DEFAULT 0x00000000
+#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
+#define mmDIG0_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
+#define mmDIG0_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
+#define mmDIG0_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
+#define mmDIG0_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
+#define mmDIG0_AFMT_60958_2_DEFAULT 0x00000000
+#define mmDIG0_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
+#define mmDIG0_AFMT_STATUS_DEFAULT 0x00000000
+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
+#define mmDIG0_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+#define mmDIG0_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
+#define mmDIG0_DIG_BE_CNTL_DEFAULT 0x00010000
+#define mmDIG0_DIG_BE_EN_CNTL_DEFAULT 0x00000000
+#define mmDIG0_TMDS_CNTL_DEFAULT 0x00000001
+#define mmDIG0_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
+#define mmDIG0_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
+#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
+#define mmDIG0_TMDS_CTL_BITS_DEFAULT 0x00000000
+#define mmDIG0_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
+#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
+#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
+#define mmDIG0_DIG_VERSION_DEFAULT 0x00000000
+#define mmDIG0_DIG_LANE_ENABLE_DEFAULT 0x00000000
+#define mmDIG0_AFMT_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dp0_dispdec
+#define mmDP0_DP_LINK_CNTL_DEFAULT 0x00000000
+#define mmDP0_DP_PIXEL_FORMAT_DEFAULT 0x00000000
+#define mmDP0_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
+#define mmDP0_DP_CONFIG_DEFAULT 0x00000000
+#define mmDP0_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
+#define mmDP0_DP_STEER_FIFO_DEFAULT 0x00000000
+#define mmDP0_DP_MSA_MISC_DEFAULT 0x00000000
+#define mmDP0_DP_VID_TIMING_DEFAULT 0x00000000
+#define mmDP0_DP_VID_N_DEFAULT 0x00002000
+#define mmDP0_DP_VID_M_DEFAULT 0x00000000
+#define mmDP0_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
+#define mmDP0_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
+#define mmDP0_DP_VID_MSA_VBID_DEFAULT 0x01000000
+#define mmDP0_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
+#define mmDP0_DP_DPHY_CNTL_DEFAULT 0x00000000
+#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
+#define mmDP0_DP_DPHY_SYM0_DEFAULT 0x00000000
+#define mmDP0_DP_DPHY_SYM1_DEFAULT 0x00000000
+#define mmDP0_DP_DPHY_SYM2_DEFAULT 0x00000000
+#define mmDP0_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
+#define mmDP0_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
+#define mmDP0_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
+#define mmDP0_DP_DPHY_CRC_EN_DEFAULT 0x00000000
+#define mmDP0_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
+#define mmDP0_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
+#define mmDP0_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
+#define mmDP0_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
+#define mmDP0_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
+#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
+#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000
+#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000
+#define mmDP0_DP_SEC_CNTL_DEFAULT 0x00000000
+#define mmDP0_DP_SEC_CNTL1_DEFAULT 0x00000000
+#define mmDP0_DP_SEC_FRAMING1_DEFAULT 0x00000000
+#define mmDP0_DP_SEC_FRAMING2_DEFAULT 0x00000000
+#define mmDP0_DP_SEC_FRAMING3_DEFAULT 0x00000200
+#define mmDP0_DP_SEC_FRAMING4_DEFAULT 0x00000000
+#define mmDP0_DP_SEC_AUD_N_DEFAULT 0x00008000
+#define mmDP0_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
+#define mmDP0_DP_SEC_AUD_M_DEFAULT 0x00000000
+#define mmDP0_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
+#define mmDP0_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
+#define mmDP0_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
+#define mmDP0_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
+#define mmDP0_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
+#define mmDP0_DP_MSE_SAT0_DEFAULT 0x00000000
+#define mmDP0_DP_MSE_SAT1_DEFAULT 0x00000000
+#define mmDP0_DP_MSE_SAT2_DEFAULT 0x00000000
+#define mmDP0_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
+#define mmDP0_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
+#define mmDP0_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
+#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
+#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
+#define mmDP0_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
+#define mmDP0_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
+#define mmDP0_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dig1_dispdec
+#define mmDIG1_DIG_FE_CNTL_DEFAULT 0x00000000
+#define mmDIG1_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
+#define mmDIG1_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
+#define mmDIG1_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
+#define mmDIG1_DIG_TEST_PATTERN_DEFAULT 0x00000060
+#define mmDIG1_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
+#define mmDIG1_DIG_FIFO_STATUS_DEFAULT 0x00000000
+#define mmDIG1_HDMI_CONTROL_DEFAULT 0x00010001
+#define mmDIG1_HDMI_STATUS_DEFAULT 0x00000000
+#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
+#define mmDIG1_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
+#define mmDIG1_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+#define mmDIG1_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+#define mmDIG1_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
+#define mmDIG1_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmDIG1_HDMI_GC_DEFAULT 0x00000004
+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
+#define mmDIG1_AFMT_ISRC1_0_DEFAULT 0x00000000
+#define mmDIG1_AFMT_ISRC1_1_DEFAULT 0x00000000
+#define mmDIG1_AFMT_ISRC1_2_DEFAULT 0x00000000
+#define mmDIG1_AFMT_ISRC1_3_DEFAULT 0x00000000
+#define mmDIG1_AFMT_ISRC1_4_DEFAULT 0x00000000
+#define mmDIG1_AFMT_ISRC2_0_DEFAULT 0x00000000
+#define mmDIG1_AFMT_ISRC2_1_DEFAULT 0x00000000
+#define mmDIG1_AFMT_ISRC2_2_DEFAULT 0x00000000
+#define mmDIG1_AFMT_ISRC2_3_DEFAULT 0x00000000
+#define mmDIG1_AFMT_AVI_INFO0_DEFAULT 0x00000000
+#define mmDIG1_AFMT_AVI_INFO1_DEFAULT 0x00000000
+#define mmDIG1_AFMT_AVI_INFO2_DEFAULT 0x00000000
+#define mmDIG1_AFMT_AVI_INFO3_DEFAULT 0x02000000
+#define mmDIG1_AFMT_MPEG_INFO0_DEFAULT 0x00000000
+#define mmDIG1_AFMT_MPEG_INFO1_DEFAULT 0x00000000
+#define mmDIG1_AFMT_GENERIC_HDR_DEFAULT 0x00000000
+#define mmDIG1_AFMT_GENERIC_0_DEFAULT 0x00000000
+#define mmDIG1_AFMT_GENERIC_1_DEFAULT 0x00000000
+#define mmDIG1_AFMT_GENERIC_2_DEFAULT 0x00000000
+#define mmDIG1_AFMT_GENERIC_3_DEFAULT 0x00000000
+#define mmDIG1_AFMT_GENERIC_4_DEFAULT 0x00000000
+#define mmDIG1_AFMT_GENERIC_5_DEFAULT 0x00000000
+#define mmDIG1_AFMT_GENERIC_6_DEFAULT 0x00000000
+#define mmDIG1_AFMT_GENERIC_7_DEFAULT 0x00000000
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
+#define mmDIG1_HDMI_ACR_32_0_DEFAULT 0x00000000
+#define mmDIG1_HDMI_ACR_32_1_DEFAULT 0x00000000
+#define mmDIG1_HDMI_ACR_44_0_DEFAULT 0x00000000
+#define mmDIG1_HDMI_ACR_44_1_DEFAULT 0x00000000
+#define mmDIG1_HDMI_ACR_48_0_DEFAULT 0x00000000
+#define mmDIG1_HDMI_ACR_48_1_DEFAULT 0x00000000
+#define mmDIG1_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
+#define mmDIG1_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
+#define mmDIG1_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
+#define mmDIG1_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
+#define mmDIG1_AFMT_60958_0_DEFAULT 0x00000000
+#define mmDIG1_AFMT_60958_1_DEFAULT 0x00000000
+#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
+#define mmDIG1_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
+#define mmDIG1_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
+#define mmDIG1_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
+#define mmDIG1_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
+#define mmDIG1_AFMT_60958_2_DEFAULT 0x00000000
+#define mmDIG1_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
+#define mmDIG1_AFMT_STATUS_DEFAULT 0x00000000
+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
+#define mmDIG1_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+#define mmDIG1_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
+#define mmDIG1_DIG_BE_CNTL_DEFAULT 0x00010000
+#define mmDIG1_DIG_BE_EN_CNTL_DEFAULT 0x00000000
+#define mmDIG1_TMDS_CNTL_DEFAULT 0x00000001
+#define mmDIG1_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
+#define mmDIG1_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
+#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
+#define mmDIG1_TMDS_CTL_BITS_DEFAULT 0x00000000
+#define mmDIG1_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
+#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
+#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
+#define mmDIG1_DIG_VERSION_DEFAULT 0x00000000
+#define mmDIG1_DIG_LANE_ENABLE_DEFAULT 0x00000000
+#define mmDIG1_AFMT_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dp1_dispdec
+#define mmDP1_DP_LINK_CNTL_DEFAULT 0x00000000
+#define mmDP1_DP_PIXEL_FORMAT_DEFAULT 0x00000000
+#define mmDP1_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
+#define mmDP1_DP_CONFIG_DEFAULT 0x00000000
+#define mmDP1_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
+#define mmDP1_DP_STEER_FIFO_DEFAULT 0x00000000
+#define mmDP1_DP_MSA_MISC_DEFAULT 0x00000000
+#define mmDP1_DP_VID_TIMING_DEFAULT 0x00000000
+#define mmDP1_DP_VID_N_DEFAULT 0x00002000
+#define mmDP1_DP_VID_M_DEFAULT 0x00000000
+#define mmDP1_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
+#define mmDP1_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
+#define mmDP1_DP_VID_MSA_VBID_DEFAULT 0x01000000
+#define mmDP1_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
+#define mmDP1_DP_DPHY_CNTL_DEFAULT 0x00000000
+#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
+#define mmDP1_DP_DPHY_SYM0_DEFAULT 0x00000000
+#define mmDP1_DP_DPHY_SYM1_DEFAULT 0x00000000
+#define mmDP1_DP_DPHY_SYM2_DEFAULT 0x00000000
+#define mmDP1_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
+#define mmDP1_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
+#define mmDP1_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
+#define mmDP1_DP_DPHY_CRC_EN_DEFAULT 0x00000000
+#define mmDP1_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
+#define mmDP1_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
+#define mmDP1_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
+#define mmDP1_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
+#define mmDP1_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
+#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
+#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000
+#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000
+#define mmDP1_DP_SEC_CNTL_DEFAULT 0x00000000
+#define mmDP1_DP_SEC_CNTL1_DEFAULT 0x00000000
+#define mmDP1_DP_SEC_FRAMING1_DEFAULT 0x00000000
+#define mmDP1_DP_SEC_FRAMING2_DEFAULT 0x00000000
+#define mmDP1_DP_SEC_FRAMING3_DEFAULT 0x00000200
+#define mmDP1_DP_SEC_FRAMING4_DEFAULT 0x00000000
+#define mmDP1_DP_SEC_AUD_N_DEFAULT 0x00008000
+#define mmDP1_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
+#define mmDP1_DP_SEC_AUD_M_DEFAULT 0x00000000
+#define mmDP1_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
+#define mmDP1_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
+#define mmDP1_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
+#define mmDP1_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
+#define mmDP1_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
+#define mmDP1_DP_MSE_SAT0_DEFAULT 0x00000000
+#define mmDP1_DP_MSE_SAT1_DEFAULT 0x00000000
+#define mmDP1_DP_MSE_SAT2_DEFAULT 0x00000000
+#define mmDP1_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
+#define mmDP1_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
+#define mmDP1_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
+#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
+#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
+#define mmDP1_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
+#define mmDP1_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
+#define mmDP1_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dig2_dispdec
+#define mmDIG2_DIG_FE_CNTL_DEFAULT 0x00000000
+#define mmDIG2_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
+#define mmDIG2_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
+#define mmDIG2_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
+#define mmDIG2_DIG_TEST_PATTERN_DEFAULT 0x00000060
+#define mmDIG2_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
+#define mmDIG2_DIG_FIFO_STATUS_DEFAULT 0x00000000
+#define mmDIG2_HDMI_CONTROL_DEFAULT 0x00010001
+#define mmDIG2_HDMI_STATUS_DEFAULT 0x00000000
+#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
+#define mmDIG2_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
+#define mmDIG2_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+#define mmDIG2_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+#define mmDIG2_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
+#define mmDIG2_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmDIG2_HDMI_GC_DEFAULT 0x00000004
+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
+#define mmDIG2_AFMT_ISRC1_0_DEFAULT 0x00000000
+#define mmDIG2_AFMT_ISRC1_1_DEFAULT 0x00000000
+#define mmDIG2_AFMT_ISRC1_2_DEFAULT 0x00000000
+#define mmDIG2_AFMT_ISRC1_3_DEFAULT 0x00000000
+#define mmDIG2_AFMT_ISRC1_4_DEFAULT 0x00000000
+#define mmDIG2_AFMT_ISRC2_0_DEFAULT 0x00000000
+#define mmDIG2_AFMT_ISRC2_1_DEFAULT 0x00000000
+#define mmDIG2_AFMT_ISRC2_2_DEFAULT 0x00000000
+#define mmDIG2_AFMT_ISRC2_3_DEFAULT 0x00000000
+#define mmDIG2_AFMT_AVI_INFO0_DEFAULT 0x00000000
+#define mmDIG2_AFMT_AVI_INFO1_DEFAULT 0x00000000
+#define mmDIG2_AFMT_AVI_INFO2_DEFAULT 0x00000000
+#define mmDIG2_AFMT_AVI_INFO3_DEFAULT 0x02000000
+#define mmDIG2_AFMT_MPEG_INFO0_DEFAULT 0x00000000
+#define mmDIG2_AFMT_MPEG_INFO1_DEFAULT 0x00000000
+#define mmDIG2_AFMT_GENERIC_HDR_DEFAULT 0x00000000
+#define mmDIG2_AFMT_GENERIC_0_DEFAULT 0x00000000
+#define mmDIG2_AFMT_GENERIC_1_DEFAULT 0x00000000
+#define mmDIG2_AFMT_GENERIC_2_DEFAULT 0x00000000
+#define mmDIG2_AFMT_GENERIC_3_DEFAULT 0x00000000
+#define mmDIG2_AFMT_GENERIC_4_DEFAULT 0x00000000
+#define mmDIG2_AFMT_GENERIC_5_DEFAULT 0x00000000
+#define mmDIG2_AFMT_GENERIC_6_DEFAULT 0x00000000
+#define mmDIG2_AFMT_GENERIC_7_DEFAULT 0x00000000
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
+#define mmDIG2_HDMI_ACR_32_0_DEFAULT 0x00000000
+#define mmDIG2_HDMI_ACR_32_1_DEFAULT 0x00000000
+#define mmDIG2_HDMI_ACR_44_0_DEFAULT 0x00000000
+#define mmDIG2_HDMI_ACR_44_1_DEFAULT 0x00000000
+#define mmDIG2_HDMI_ACR_48_0_DEFAULT 0x00000000
+#define mmDIG2_HDMI_ACR_48_1_DEFAULT 0x00000000
+#define mmDIG2_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
+#define mmDIG2_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
+#define mmDIG2_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
+#define mmDIG2_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
+#define mmDIG2_AFMT_60958_0_DEFAULT 0x00000000
+#define mmDIG2_AFMT_60958_1_DEFAULT 0x00000000
+#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
+#define mmDIG2_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
+#define mmDIG2_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
+#define mmDIG2_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
+#define mmDIG2_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
+#define mmDIG2_AFMT_60958_2_DEFAULT 0x00000000
+#define mmDIG2_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
+#define mmDIG2_AFMT_STATUS_DEFAULT 0x00000000
+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
+#define mmDIG2_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+#define mmDIG2_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
+#define mmDIG2_DIG_BE_CNTL_DEFAULT 0x00010000
+#define mmDIG2_DIG_BE_EN_CNTL_DEFAULT 0x00000000
+#define mmDIG2_TMDS_CNTL_DEFAULT 0x00000001
+#define mmDIG2_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
+#define mmDIG2_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
+#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
+#define mmDIG2_TMDS_CTL_BITS_DEFAULT 0x00000000
+#define mmDIG2_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
+#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
+#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
+#define mmDIG2_DIG_VERSION_DEFAULT 0x00000000
+#define mmDIG2_DIG_LANE_ENABLE_DEFAULT 0x00000000
+#define mmDIG2_AFMT_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dp2_dispdec
+#define mmDP2_DP_LINK_CNTL_DEFAULT 0x00000000
+#define mmDP2_DP_PIXEL_FORMAT_DEFAULT 0x00000000
+#define mmDP2_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
+#define mmDP2_DP_CONFIG_DEFAULT 0x00000000
+#define mmDP2_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
+#define mmDP2_DP_STEER_FIFO_DEFAULT 0x00000000
+#define mmDP2_DP_MSA_MISC_DEFAULT 0x00000000
+#define mmDP2_DP_VID_TIMING_DEFAULT 0x00000000
+#define mmDP2_DP_VID_N_DEFAULT 0x00002000
+#define mmDP2_DP_VID_M_DEFAULT 0x00000000
+#define mmDP2_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
+#define mmDP2_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
+#define mmDP2_DP_VID_MSA_VBID_DEFAULT 0x01000000
+#define mmDP2_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
+#define mmDP2_DP_DPHY_CNTL_DEFAULT 0x00000000
+#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
+#define mmDP2_DP_DPHY_SYM0_DEFAULT 0x00000000
+#define mmDP2_DP_DPHY_SYM1_DEFAULT 0x00000000
+#define mmDP2_DP_DPHY_SYM2_DEFAULT 0x00000000
+#define mmDP2_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
+#define mmDP2_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
+#define mmDP2_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
+#define mmDP2_DP_DPHY_CRC_EN_DEFAULT 0x00000000
+#define mmDP2_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
+#define mmDP2_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
+#define mmDP2_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
+#define mmDP2_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
+#define mmDP2_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
+#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
+#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000
+#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000
+#define mmDP2_DP_SEC_CNTL_DEFAULT 0x00000000
+#define mmDP2_DP_SEC_CNTL1_DEFAULT 0x00000000
+#define mmDP2_DP_SEC_FRAMING1_DEFAULT 0x00000000
+#define mmDP2_DP_SEC_FRAMING2_DEFAULT 0x00000000
+#define mmDP2_DP_SEC_FRAMING3_DEFAULT 0x00000200
+#define mmDP2_DP_SEC_FRAMING4_DEFAULT 0x00000000
+#define mmDP2_DP_SEC_AUD_N_DEFAULT 0x00008000
+#define mmDP2_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
+#define mmDP2_DP_SEC_AUD_M_DEFAULT 0x00000000
+#define mmDP2_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
+#define mmDP2_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
+#define mmDP2_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
+#define mmDP2_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
+#define mmDP2_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
+#define mmDP2_DP_MSE_SAT0_DEFAULT 0x00000000
+#define mmDP2_DP_MSE_SAT1_DEFAULT 0x00000000
+#define mmDP2_DP_MSE_SAT2_DEFAULT 0x00000000
+#define mmDP2_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
+#define mmDP2_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
+#define mmDP2_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
+#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
+#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
+#define mmDP2_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
+#define mmDP2_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
+#define mmDP2_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dig3_dispdec
+#define mmDIG3_DIG_FE_CNTL_DEFAULT 0x00000000
+#define mmDIG3_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
+#define mmDIG3_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
+#define mmDIG3_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
+#define mmDIG3_DIG_TEST_PATTERN_DEFAULT 0x00000060
+#define mmDIG3_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
+#define mmDIG3_DIG_FIFO_STATUS_DEFAULT 0x00000000
+#define mmDIG3_HDMI_CONTROL_DEFAULT 0x00010001
+#define mmDIG3_HDMI_STATUS_DEFAULT 0x00000000
+#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
+#define mmDIG3_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
+#define mmDIG3_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+#define mmDIG3_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+#define mmDIG3_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
+#define mmDIG3_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmDIG3_HDMI_GC_DEFAULT 0x00000004
+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
+#define mmDIG3_AFMT_ISRC1_0_DEFAULT 0x00000000
+#define mmDIG3_AFMT_ISRC1_1_DEFAULT 0x00000000
+#define mmDIG3_AFMT_ISRC1_2_DEFAULT 0x00000000
+#define mmDIG3_AFMT_ISRC1_3_DEFAULT 0x00000000
+#define mmDIG3_AFMT_ISRC1_4_DEFAULT 0x00000000
+#define mmDIG3_AFMT_ISRC2_0_DEFAULT 0x00000000
+#define mmDIG3_AFMT_ISRC2_1_DEFAULT 0x00000000
+#define mmDIG3_AFMT_ISRC2_2_DEFAULT 0x00000000
+#define mmDIG3_AFMT_ISRC2_3_DEFAULT 0x00000000
+#define mmDIG3_AFMT_AVI_INFO0_DEFAULT 0x00000000
+#define mmDIG3_AFMT_AVI_INFO1_DEFAULT 0x00000000
+#define mmDIG3_AFMT_AVI_INFO2_DEFAULT 0x00000000
+#define mmDIG3_AFMT_AVI_INFO3_DEFAULT 0x02000000
+#define mmDIG3_AFMT_MPEG_INFO0_DEFAULT 0x00000000
+#define mmDIG3_AFMT_MPEG_INFO1_DEFAULT 0x00000000
+#define mmDIG3_AFMT_GENERIC_HDR_DEFAULT 0x00000000
+#define mmDIG3_AFMT_GENERIC_0_DEFAULT 0x00000000
+#define mmDIG3_AFMT_GENERIC_1_DEFAULT 0x00000000
+#define mmDIG3_AFMT_GENERIC_2_DEFAULT 0x00000000
+#define mmDIG3_AFMT_GENERIC_3_DEFAULT 0x00000000
+#define mmDIG3_AFMT_GENERIC_4_DEFAULT 0x00000000
+#define mmDIG3_AFMT_GENERIC_5_DEFAULT 0x00000000
+#define mmDIG3_AFMT_GENERIC_6_DEFAULT 0x00000000
+#define mmDIG3_AFMT_GENERIC_7_DEFAULT 0x00000000
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
+#define mmDIG3_HDMI_ACR_32_0_DEFAULT 0x00000000
+#define mmDIG3_HDMI_ACR_32_1_DEFAULT 0x00000000
+#define mmDIG3_HDMI_ACR_44_0_DEFAULT 0x00000000
+#define mmDIG3_HDMI_ACR_44_1_DEFAULT 0x00000000
+#define mmDIG3_HDMI_ACR_48_0_DEFAULT 0x00000000
+#define mmDIG3_HDMI_ACR_48_1_DEFAULT 0x00000000
+#define mmDIG3_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
+#define mmDIG3_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
+#define mmDIG3_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
+#define mmDIG3_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
+#define mmDIG3_AFMT_60958_0_DEFAULT 0x00000000
+#define mmDIG3_AFMT_60958_1_DEFAULT 0x00000000
+#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
+#define mmDIG3_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
+#define mmDIG3_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
+#define mmDIG3_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
+#define mmDIG3_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
+#define mmDIG3_AFMT_60958_2_DEFAULT 0x00000000
+#define mmDIG3_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
+#define mmDIG3_AFMT_STATUS_DEFAULT 0x00000000
+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
+#define mmDIG3_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+#define mmDIG3_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
+#define mmDIG3_DIG_BE_CNTL_DEFAULT 0x00010000
+#define mmDIG3_DIG_BE_EN_CNTL_DEFAULT 0x00000000
+#define mmDIG3_TMDS_CNTL_DEFAULT 0x00000001
+#define mmDIG3_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
+#define mmDIG3_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
+#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
+#define mmDIG3_TMDS_CTL_BITS_DEFAULT 0x00000000
+#define mmDIG3_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
+#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
+#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
+#define mmDIG3_DIG_VERSION_DEFAULT 0x00000000
+#define mmDIG3_DIG_LANE_ENABLE_DEFAULT 0x00000000
+#define mmDIG3_AFMT_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dp3_dispdec
+#define mmDP3_DP_LINK_CNTL_DEFAULT 0x00000000
+#define mmDP3_DP_PIXEL_FORMAT_DEFAULT 0x00000000
+#define mmDP3_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
+#define mmDP3_DP_CONFIG_DEFAULT 0x00000000
+#define mmDP3_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
+#define mmDP3_DP_STEER_FIFO_DEFAULT 0x00000000
+#define mmDP3_DP_MSA_MISC_DEFAULT 0x00000000
+#define mmDP3_DP_VID_TIMING_DEFAULT 0x00000000
+#define mmDP3_DP_VID_N_DEFAULT 0x00002000
+#define mmDP3_DP_VID_M_DEFAULT 0x00000000
+#define mmDP3_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
+#define mmDP3_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
+#define mmDP3_DP_VID_MSA_VBID_DEFAULT 0x01000000
+#define mmDP3_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
+#define mmDP3_DP_DPHY_CNTL_DEFAULT 0x00000000
+#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
+#define mmDP3_DP_DPHY_SYM0_DEFAULT 0x00000000
+#define mmDP3_DP_DPHY_SYM1_DEFAULT 0x00000000
+#define mmDP3_DP_DPHY_SYM2_DEFAULT 0x00000000
+#define mmDP3_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
+#define mmDP3_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
+#define mmDP3_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
+#define mmDP3_DP_DPHY_CRC_EN_DEFAULT 0x00000000
+#define mmDP3_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
+#define mmDP3_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
+#define mmDP3_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
+#define mmDP3_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
+#define mmDP3_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
+#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
+#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000
+#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000
+#define mmDP3_DP_SEC_CNTL_DEFAULT 0x00000000
+#define mmDP3_DP_SEC_CNTL1_DEFAULT 0x00000000
+#define mmDP3_DP_SEC_FRAMING1_DEFAULT 0x00000000
+#define mmDP3_DP_SEC_FRAMING2_DEFAULT 0x00000000
+#define mmDP3_DP_SEC_FRAMING3_DEFAULT 0x00000200
+#define mmDP3_DP_SEC_FRAMING4_DEFAULT 0x00000000
+#define mmDP3_DP_SEC_AUD_N_DEFAULT 0x00008000
+#define mmDP3_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
+#define mmDP3_DP_SEC_AUD_M_DEFAULT 0x00000000
+#define mmDP3_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
+#define mmDP3_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
+#define mmDP3_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
+#define mmDP3_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
+#define mmDP3_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
+#define mmDP3_DP_MSE_SAT0_DEFAULT 0x00000000
+#define mmDP3_DP_MSE_SAT1_DEFAULT 0x00000000
+#define mmDP3_DP_MSE_SAT2_DEFAULT 0x00000000
+#define mmDP3_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
+#define mmDP3_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
+#define mmDP3_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
+#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
+#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
+#define mmDP3_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
+#define mmDP3_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
+#define mmDP3_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dig4_dispdec
+#define mmDIG4_DIG_FE_CNTL_DEFAULT 0x00000000
+#define mmDIG4_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
+#define mmDIG4_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
+#define mmDIG4_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
+#define mmDIG4_DIG_TEST_PATTERN_DEFAULT 0x00000060
+#define mmDIG4_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
+#define mmDIG4_DIG_FIFO_STATUS_DEFAULT 0x00000000
+#define mmDIG4_HDMI_CONTROL_DEFAULT 0x00010001
+#define mmDIG4_HDMI_STATUS_DEFAULT 0x00000000
+#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
+#define mmDIG4_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
+#define mmDIG4_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+#define mmDIG4_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+#define mmDIG4_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
+#define mmDIG4_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmDIG4_HDMI_GC_DEFAULT 0x00000004
+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
+#define mmDIG4_AFMT_ISRC1_0_DEFAULT 0x00000000
+#define mmDIG4_AFMT_ISRC1_1_DEFAULT 0x00000000
+#define mmDIG4_AFMT_ISRC1_2_DEFAULT 0x00000000
+#define mmDIG4_AFMT_ISRC1_3_DEFAULT 0x00000000
+#define mmDIG4_AFMT_ISRC1_4_DEFAULT 0x00000000
+#define mmDIG4_AFMT_ISRC2_0_DEFAULT 0x00000000
+#define mmDIG4_AFMT_ISRC2_1_DEFAULT 0x00000000
+#define mmDIG4_AFMT_ISRC2_2_DEFAULT 0x00000000
+#define mmDIG4_AFMT_ISRC2_3_DEFAULT 0x00000000
+#define mmDIG4_AFMT_AVI_INFO0_DEFAULT 0x00000000
+#define mmDIG4_AFMT_AVI_INFO1_DEFAULT 0x00000000
+#define mmDIG4_AFMT_AVI_INFO2_DEFAULT 0x00000000
+#define mmDIG4_AFMT_AVI_INFO3_DEFAULT 0x02000000
+#define mmDIG4_AFMT_MPEG_INFO0_DEFAULT 0x00000000
+#define mmDIG4_AFMT_MPEG_INFO1_DEFAULT 0x00000000
+#define mmDIG4_AFMT_GENERIC_HDR_DEFAULT 0x00000000
+#define mmDIG4_AFMT_GENERIC_0_DEFAULT 0x00000000
+#define mmDIG4_AFMT_GENERIC_1_DEFAULT 0x00000000
+#define mmDIG4_AFMT_GENERIC_2_DEFAULT 0x00000000
+#define mmDIG4_AFMT_GENERIC_3_DEFAULT 0x00000000
+#define mmDIG4_AFMT_GENERIC_4_DEFAULT 0x00000000
+#define mmDIG4_AFMT_GENERIC_5_DEFAULT 0x00000000
+#define mmDIG4_AFMT_GENERIC_6_DEFAULT 0x00000000
+#define mmDIG4_AFMT_GENERIC_7_DEFAULT 0x00000000
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
+#define mmDIG4_HDMI_ACR_32_0_DEFAULT 0x00000000
+#define mmDIG4_HDMI_ACR_32_1_DEFAULT 0x00000000
+#define mmDIG4_HDMI_ACR_44_0_DEFAULT 0x00000000
+#define mmDIG4_HDMI_ACR_44_1_DEFAULT 0x00000000
+#define mmDIG4_HDMI_ACR_48_0_DEFAULT 0x00000000
+#define mmDIG4_HDMI_ACR_48_1_DEFAULT 0x00000000
+#define mmDIG4_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
+#define mmDIG4_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
+#define mmDIG4_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
+#define mmDIG4_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
+#define mmDIG4_AFMT_60958_0_DEFAULT 0x00000000
+#define mmDIG4_AFMT_60958_1_DEFAULT 0x00000000
+#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
+#define mmDIG4_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
+#define mmDIG4_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
+#define mmDIG4_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
+#define mmDIG4_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
+#define mmDIG4_AFMT_60958_2_DEFAULT 0x00000000
+#define mmDIG4_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
+#define mmDIG4_AFMT_STATUS_DEFAULT 0x00000000
+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
+#define mmDIG4_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+#define mmDIG4_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
+#define mmDIG4_DIG_BE_CNTL_DEFAULT 0x00010000
+#define mmDIG4_DIG_BE_EN_CNTL_DEFAULT 0x00000000
+#define mmDIG4_TMDS_CNTL_DEFAULT 0x00000001
+#define mmDIG4_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
+#define mmDIG4_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
+#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
+#define mmDIG4_TMDS_CTL_BITS_DEFAULT 0x00000000
+#define mmDIG4_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
+#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
+#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
+#define mmDIG4_DIG_VERSION_DEFAULT 0x00000000
+#define mmDIG4_DIG_LANE_ENABLE_DEFAULT 0x00000000
+#define mmDIG4_AFMT_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dp4_dispdec
+#define mmDP4_DP_LINK_CNTL_DEFAULT 0x00000000
+#define mmDP4_DP_PIXEL_FORMAT_DEFAULT 0x00000000
+#define mmDP4_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
+#define mmDP4_DP_CONFIG_DEFAULT 0x00000000
+#define mmDP4_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
+#define mmDP4_DP_STEER_FIFO_DEFAULT 0x00000000
+#define mmDP4_DP_MSA_MISC_DEFAULT 0x00000000
+#define mmDP4_DP_VID_TIMING_DEFAULT 0x00000000
+#define mmDP4_DP_VID_N_DEFAULT 0x00002000
+#define mmDP4_DP_VID_M_DEFAULT 0x00000000
+#define mmDP4_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
+#define mmDP4_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
+#define mmDP4_DP_VID_MSA_VBID_DEFAULT 0x01000000
+#define mmDP4_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
+#define mmDP4_DP_DPHY_CNTL_DEFAULT 0x00000000
+#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
+#define mmDP4_DP_DPHY_SYM0_DEFAULT 0x00000000
+#define mmDP4_DP_DPHY_SYM1_DEFAULT 0x00000000
+#define mmDP4_DP_DPHY_SYM2_DEFAULT 0x00000000
+#define mmDP4_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
+#define mmDP4_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
+#define mmDP4_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
+#define mmDP4_DP_DPHY_CRC_EN_DEFAULT 0x00000000
+#define mmDP4_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
+#define mmDP4_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
+#define mmDP4_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
+#define mmDP4_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
+#define mmDP4_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
+#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
+#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000
+#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000
+#define mmDP4_DP_SEC_CNTL_DEFAULT 0x00000000
+#define mmDP4_DP_SEC_CNTL1_DEFAULT 0x00000000
+#define mmDP4_DP_SEC_FRAMING1_DEFAULT 0x00000000
+#define mmDP4_DP_SEC_FRAMING2_DEFAULT 0x00000000
+#define mmDP4_DP_SEC_FRAMING3_DEFAULT 0x00000200
+#define mmDP4_DP_SEC_FRAMING4_DEFAULT 0x00000000
+#define mmDP4_DP_SEC_AUD_N_DEFAULT 0x00008000
+#define mmDP4_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
+#define mmDP4_DP_SEC_AUD_M_DEFAULT 0x00000000
+#define mmDP4_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
+#define mmDP4_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
+#define mmDP4_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
+#define mmDP4_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
+#define mmDP4_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
+#define mmDP4_DP_MSE_SAT0_DEFAULT 0x00000000
+#define mmDP4_DP_MSE_SAT1_DEFAULT 0x00000000
+#define mmDP4_DP_MSE_SAT2_DEFAULT 0x00000000
+#define mmDP4_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
+#define mmDP4_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
+#define mmDP4_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
+#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
+#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
+#define mmDP4_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
+#define mmDP4_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
+#define mmDP4_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dig5_dispdec
+#define mmDIG5_DIG_FE_CNTL_DEFAULT 0x00000000
+#define mmDIG5_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
+#define mmDIG5_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
+#define mmDIG5_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
+#define mmDIG5_DIG_TEST_PATTERN_DEFAULT 0x00000060
+#define mmDIG5_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
+#define mmDIG5_DIG_FIFO_STATUS_DEFAULT 0x00000000
+#define mmDIG5_HDMI_CONTROL_DEFAULT 0x00010001
+#define mmDIG5_HDMI_STATUS_DEFAULT 0x00000000
+#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
+#define mmDIG5_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
+#define mmDIG5_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+#define mmDIG5_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+#define mmDIG5_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
+#define mmDIG5_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmDIG5_HDMI_GC_DEFAULT 0x00000004
+#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
+#define mmDIG5_AFMT_ISRC1_0_DEFAULT 0x00000000
+#define mmDIG5_AFMT_ISRC1_1_DEFAULT 0x00000000
+#define mmDIG5_AFMT_ISRC1_2_DEFAULT 0x00000000
+#define mmDIG5_AFMT_ISRC1_3_DEFAULT 0x00000000
+#define mmDIG5_AFMT_ISRC1_4_DEFAULT 0x00000000
+#define mmDIG5_AFMT_ISRC2_0_DEFAULT 0x00000000
+#define mmDIG5_AFMT_ISRC2_1_DEFAULT 0x00000000
+#define mmDIG5_AFMT_ISRC2_2_DEFAULT 0x00000000
+#define mmDIG5_AFMT_ISRC2_3_DEFAULT 0x00000000
+#define mmDIG5_AFMT_AVI_INFO0_DEFAULT 0x00000000
+#define mmDIG5_AFMT_AVI_INFO1_DEFAULT 0x00000000
+#define mmDIG5_AFMT_AVI_INFO2_DEFAULT 0x00000000
+#define mmDIG5_AFMT_AVI_INFO3_DEFAULT 0x02000000
+#define mmDIG5_AFMT_MPEG_INFO0_DEFAULT 0x00000000
+#define mmDIG5_AFMT_MPEG_INFO1_DEFAULT 0x00000000
+#define mmDIG5_AFMT_GENERIC_HDR_DEFAULT 0x00000000
+#define mmDIG5_AFMT_GENERIC_0_DEFAULT 0x00000000
+#define mmDIG5_AFMT_GENERIC_1_DEFAULT 0x00000000
+#define mmDIG5_AFMT_GENERIC_2_DEFAULT 0x00000000
+#define mmDIG5_AFMT_GENERIC_3_DEFAULT 0x00000000
+#define mmDIG5_AFMT_GENERIC_4_DEFAULT 0x00000000
+#define mmDIG5_AFMT_GENERIC_5_DEFAULT 0x00000000
+#define mmDIG5_AFMT_GENERIC_6_DEFAULT 0x00000000
+#define mmDIG5_AFMT_GENERIC_7_DEFAULT 0x00000000
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
+#define mmDIG5_HDMI_ACR_32_0_DEFAULT 0x00000000
+#define mmDIG5_HDMI_ACR_32_1_DEFAULT 0x00000000
+#define mmDIG5_HDMI_ACR_44_0_DEFAULT 0x00000000
+#define mmDIG5_HDMI_ACR_44_1_DEFAULT 0x00000000
+#define mmDIG5_HDMI_ACR_48_0_DEFAULT 0x00000000
+#define mmDIG5_HDMI_ACR_48_1_DEFAULT 0x00000000
+#define mmDIG5_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
+#define mmDIG5_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
+#define mmDIG5_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
+#define mmDIG5_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
+#define mmDIG5_AFMT_60958_0_DEFAULT 0x00000000
+#define mmDIG5_AFMT_60958_1_DEFAULT 0x00000000
+#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
+#define mmDIG5_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
+#define mmDIG5_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
+#define mmDIG5_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
+#define mmDIG5_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
+#define mmDIG5_AFMT_60958_2_DEFAULT 0x00000000
+#define mmDIG5_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
+#define mmDIG5_AFMT_STATUS_DEFAULT 0x00000000
+#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
+#define mmDIG5_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+#define mmDIG5_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
+#define mmDIG5_DIG_BE_CNTL_DEFAULT 0x00010000
+#define mmDIG5_DIG_BE_EN_CNTL_DEFAULT 0x00000000
+#define mmDIG5_TMDS_CNTL_DEFAULT 0x00000001
+#define mmDIG5_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
+#define mmDIG5_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
+#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
+#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
+#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
+#define mmDIG5_TMDS_CTL_BITS_DEFAULT 0x00000000
+#define mmDIG5_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
+#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
+#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
+#define mmDIG5_DIG_VERSION_DEFAULT 0x00000000
+#define mmDIG5_DIG_LANE_ENABLE_DEFAULT 0x00000000
+#define mmDIG5_AFMT_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dp5_dispdec
+#define mmDP5_DP_LINK_CNTL_DEFAULT 0x00000000
+#define mmDP5_DP_PIXEL_FORMAT_DEFAULT 0x00000000
+#define mmDP5_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
+#define mmDP5_DP_CONFIG_DEFAULT 0x00000000
+#define mmDP5_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
+#define mmDP5_DP_STEER_FIFO_DEFAULT 0x00000000
+#define mmDP5_DP_MSA_MISC_DEFAULT 0x00000000
+#define mmDP5_DP_VID_TIMING_DEFAULT 0x00000000
+#define mmDP5_DP_VID_N_DEFAULT 0x00002000
+#define mmDP5_DP_VID_M_DEFAULT 0x00000000
+#define mmDP5_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
+#define mmDP5_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
+#define mmDP5_DP_VID_MSA_VBID_DEFAULT 0x01000000
+#define mmDP5_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
+#define mmDP5_DP_DPHY_CNTL_DEFAULT 0x00000000
+#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
+#define mmDP5_DP_DPHY_SYM0_DEFAULT 0x00000000
+#define mmDP5_DP_DPHY_SYM1_DEFAULT 0x00000000
+#define mmDP5_DP_DPHY_SYM2_DEFAULT 0x00000000
+#define mmDP5_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
+#define mmDP5_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
+#define mmDP5_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
+#define mmDP5_DP_DPHY_CRC_EN_DEFAULT 0x00000000
+#define mmDP5_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
+#define mmDP5_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
+#define mmDP5_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
+#define mmDP5_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
+#define mmDP5_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
+#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
+#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000
+#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000
+#define mmDP5_DP_SEC_CNTL_DEFAULT 0x00000000
+#define mmDP5_DP_SEC_CNTL1_DEFAULT 0x00000000
+#define mmDP5_DP_SEC_FRAMING1_DEFAULT 0x00000000
+#define mmDP5_DP_SEC_FRAMING2_DEFAULT 0x00000000
+#define mmDP5_DP_SEC_FRAMING3_DEFAULT 0x00000200
+#define mmDP5_DP_SEC_FRAMING4_DEFAULT 0x00000000
+#define mmDP5_DP_SEC_AUD_N_DEFAULT 0x00008000
+#define mmDP5_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
+#define mmDP5_DP_SEC_AUD_M_DEFAULT 0x00000000
+#define mmDP5_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
+#define mmDP5_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
+#define mmDP5_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
+#define mmDP5_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
+#define mmDP5_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
+#define mmDP5_DP_MSE_SAT0_DEFAULT 0x00000000
+#define mmDP5_DP_MSE_SAT1_DEFAULT 0x00000000
+#define mmDP5_DP_MSE_SAT2_DEFAULT 0x00000000
+#define mmDP5_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
+#define mmDP5_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
+#define mmDP5_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
+#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
+#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
+#define mmDP5_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
+#define mmDP5_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
+#define mmDP5_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dig6_dispdec
+#define mmDIG6_DIG_FE_CNTL_DEFAULT 0x00000000
+#define mmDIG6_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100
+#define mmDIG6_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000
+#define mmDIG6_DIG_CLOCK_PATTERN_DEFAULT 0x00000063
+#define mmDIG6_DIG_TEST_PATTERN_DEFAULT 0x00000060
+#define mmDIG6_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222
+#define mmDIG6_DIG_FIFO_STATUS_DEFAULT 0x00000000
+#define mmDIG6_HDMI_CONTROL_DEFAULT 0x00010001
+#define mmDIG6_HDMI_STATUS_DEFAULT 0x00000000
+#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010
+#define mmDIG6_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000
+#define mmDIG6_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+#define mmDIG6_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+#define mmDIG6_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000
+#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000
+#define mmDIG6_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmDIG6_HDMI_GC_DEFAULT 0x00000004
+#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000
+#define mmDIG6_AFMT_ISRC1_0_DEFAULT 0x00000000
+#define mmDIG6_AFMT_ISRC1_1_DEFAULT 0x00000000
+#define mmDIG6_AFMT_ISRC1_2_DEFAULT 0x00000000
+#define mmDIG6_AFMT_ISRC1_3_DEFAULT 0x00000000
+#define mmDIG6_AFMT_ISRC1_4_DEFAULT 0x00000000
+#define mmDIG6_AFMT_ISRC2_0_DEFAULT 0x00000000
+#define mmDIG6_AFMT_ISRC2_1_DEFAULT 0x00000000
+#define mmDIG6_AFMT_ISRC2_2_DEFAULT 0x00000000
+#define mmDIG6_AFMT_ISRC2_3_DEFAULT 0x00000000
+#define mmDIG6_AFMT_AVI_INFO0_DEFAULT 0x00000000
+#define mmDIG6_AFMT_AVI_INFO1_DEFAULT 0x00000000
+#define mmDIG6_AFMT_AVI_INFO2_DEFAULT 0x00000000
+#define mmDIG6_AFMT_AVI_INFO3_DEFAULT 0x02000000
+#define mmDIG6_AFMT_MPEG_INFO0_DEFAULT 0x00000000
+#define mmDIG6_AFMT_MPEG_INFO1_DEFAULT 0x00000000
+#define mmDIG6_AFMT_GENERIC_HDR_DEFAULT 0x00000000
+#define mmDIG6_AFMT_GENERIC_0_DEFAULT 0x00000000
+#define mmDIG6_AFMT_GENERIC_1_DEFAULT 0x00000000
+#define mmDIG6_AFMT_GENERIC_2_DEFAULT 0x00000000
+#define mmDIG6_AFMT_GENERIC_3_DEFAULT 0x00000000
+#define mmDIG6_AFMT_GENERIC_4_DEFAULT 0x00000000
+#define mmDIG6_AFMT_GENERIC_5_DEFAULT 0x00000000
+#define mmDIG6_AFMT_GENERIC_6_DEFAULT 0x00000000
+#define mmDIG6_AFMT_GENERIC_7_DEFAULT 0x00000000
+#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000
+#define mmDIG6_HDMI_ACR_32_0_DEFAULT 0x00000000
+#define mmDIG6_HDMI_ACR_32_1_DEFAULT 0x00000000
+#define mmDIG6_HDMI_ACR_44_0_DEFAULT 0x00000000
+#define mmDIG6_HDMI_ACR_44_1_DEFAULT 0x00000000
+#define mmDIG6_HDMI_ACR_48_0_DEFAULT 0x00000000
+#define mmDIG6_HDMI_ACR_48_1_DEFAULT 0x00000000
+#define mmDIG6_HDMI_ACR_STATUS_0_DEFAULT 0x00000000
+#define mmDIG6_HDMI_ACR_STATUS_1_DEFAULT 0x00000000
+#define mmDIG6_AFMT_AUDIO_INFO0_DEFAULT 0x00000170
+#define mmDIG6_AFMT_AUDIO_INFO1_DEFAULT 0x00000000
+#define mmDIG6_AFMT_60958_0_DEFAULT 0x00000000
+#define mmDIG6_AFMT_60958_1_DEFAULT 0x00000000
+#define mmDIG6_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000
+#define mmDIG6_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000
+#define mmDIG6_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000
+#define mmDIG6_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000
+#define mmDIG6_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000
+#define mmDIG6_AFMT_60958_2_DEFAULT 0x00000000
+#define mmDIG6_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000
+#define mmDIG6_AFMT_STATUS_DEFAULT 0x00000000
+#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800
+#define mmDIG6_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000
+#define mmDIG6_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000
+#define mmDIG6_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000
+#define mmDIG6_DIG_BE_CNTL_DEFAULT 0x00010000
+#define mmDIG6_DIG_BE_EN_CNTL_DEFAULT 0x00000000
+#define mmDIG6_TMDS_CNTL_DEFAULT 0x00000001
+#define mmDIG6_TMDS_CONTROL_CHAR_DEFAULT 0x00000000
+#define mmDIG6_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000
+#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000
+#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000
+#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000
+#define mmDIG6_TMDS_CTL_BITS_DEFAULT 0x00000000
+#define mmDIG6_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001
+#define mmDIG6_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000
+#define mmDIG6_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000
+#define mmDIG6_DIG_VERSION_DEFAULT 0x00000000
+#define mmDIG6_DIG_LANE_ENABLE_DEFAULT 0x00000000
+#define mmDIG6_AFMT_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dp6_dispdec
+#define mmDP6_DP_LINK_CNTL_DEFAULT 0x00000000
+#define mmDP6_DP_PIXEL_FORMAT_DEFAULT 0x00000000
+#define mmDP6_DP_MSA_COLORIMETRY_DEFAULT 0x00000000
+#define mmDP6_DP_CONFIG_DEFAULT 0x00000000
+#define mmDP6_DP_VID_STREAM_CNTL_DEFAULT 0x00000200
+#define mmDP6_DP_STEER_FIFO_DEFAULT 0x00000000
+#define mmDP6_DP_MSA_MISC_DEFAULT 0x00000000
+#define mmDP6_DP_VID_TIMING_DEFAULT 0x00000000
+#define mmDP6_DP_VID_N_DEFAULT 0x00002000
+#define mmDP6_DP_VID_M_DEFAULT 0x00000000
+#define mmDP6_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000
+#define mmDP6_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000
+#define mmDP6_DP_VID_MSA_VBID_DEFAULT 0x01000000
+#define mmDP6_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000
+#define mmDP6_DP_DPHY_CNTL_DEFAULT 0x00000000
+#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000
+#define mmDP6_DP_DPHY_SYM0_DEFAULT 0x00000000
+#define mmDP6_DP_DPHY_SYM1_DEFAULT 0x00000000
+#define mmDP6_DP_DPHY_SYM2_DEFAULT 0x00000000
+#define mmDP6_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000
+#define mmDP6_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00
+#define mmDP6_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10
+#define mmDP6_DP_DPHY_CRC_EN_DEFAULT 0x00000000
+#define mmDP6_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000
+#define mmDP6_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000
+#define mmDP6_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000
+#define mmDP6_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000
+#define mmDP6_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000
+#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000
+#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000
+#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000
+#define mmDP6_DP_SEC_CNTL_DEFAULT 0x00000000
+#define mmDP6_DP_SEC_CNTL1_DEFAULT 0x00000000
+#define mmDP6_DP_SEC_FRAMING1_DEFAULT 0x00000000
+#define mmDP6_DP_SEC_FRAMING2_DEFAULT 0x00000000
+#define mmDP6_DP_SEC_FRAMING3_DEFAULT 0x00000200
+#define mmDP6_DP_SEC_FRAMING4_DEFAULT 0x00000000
+#define mmDP6_DP_SEC_AUD_N_DEFAULT 0x00008000
+#define mmDP6_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000
+#define mmDP6_DP_SEC_AUD_M_DEFAULT 0x00000000
+#define mmDP6_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000
+#define mmDP6_DP_SEC_TIMESTAMP_DEFAULT 0x00000000
+#define mmDP6_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100
+#define mmDP6_DP_MSE_RATE_CNTL_DEFAULT 0x00000000
+#define mmDP6_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000
+#define mmDP6_DP_MSE_SAT0_DEFAULT 0x00000000
+#define mmDP6_DP_MSE_SAT1_DEFAULT 0x00000000
+#define mmDP6_DP_MSE_SAT2_DEFAULT 0x00000000
+#define mmDP6_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000
+#define mmDP6_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff
+#define mmDP6_DP_MSE_MISC_CNTL_DEFAULT 0x00000000
+#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005
+#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000
+#define mmDP6_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000
+#define mmDP6_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000
+#define mmDP6_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dcio_uniphy0_dispdec
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophycmregs0_dispdec
+#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
+#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
+#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_DEFAULT 0x00000007
+#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_DEFAULT 0x000000ff
+#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophytxregs0_dispdec
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophypllregs0_dispdec
+#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_DEFAULT 0x00280000
+#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_DEFAULT 0x00e80000
+#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
+#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_DEFAULT 0x00000001
+#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_DEFAULT 0x64000000
+#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_DEFAULT 0x00000090
+#define mmDC_COMBOPHYPLLREGS0_VREG_CFG_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS0_OBSERVE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS0_OBSERVE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS0_DFT_OUT_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dcio_uniphy1_dispdec
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophycmregs1_dispdec
+#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
+#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
+#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_DEFAULT 0x00000007
+#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_DEFAULT 0x000000ff
+#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophytxregs1_dispdec
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophypllregs1_dispdec
+#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_DEFAULT 0x00280000
+#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_DEFAULT 0x00e80000
+#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
+#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_DEFAULT 0x00000001
+#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_DEFAULT 0x64000000
+#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_DEFAULT 0x00000090
+#define mmDC_COMBOPHYPLLREGS1_VREG_CFG_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS1_OBSERVE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS1_OBSERVE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS1_DFT_OUT_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dcio_uniphy2_dispdec
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophycmregs2_dispdec
+#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
+#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
+#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_DEFAULT 0x00000007
+#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_DEFAULT 0x000000ff
+#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophytxregs2_dispdec
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophypllregs2_dispdec
+#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_DEFAULT 0x00280000
+#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_DEFAULT 0x00e80000
+#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
+#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_DEFAULT 0x00000001
+#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_DEFAULT 0x64000000
+#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_DEFAULT 0x00000090
+#define mmDC_COMBOPHYPLLREGS2_VREG_CFG_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS2_OBSERVE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS2_OBSERVE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS2_DFT_OUT_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dcio_uniphy3_dispdec
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophycmregs3_dispdec
+#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
+#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
+#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_DEFAULT 0x00000007
+#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_DEFAULT 0x000000ff
+#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophytxregs3_dispdec
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophypllregs3_dispdec
+#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_DEFAULT 0x00280000
+#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_DEFAULT 0x00e80000
+#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
+#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_DEFAULT 0x00000001
+#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_DEFAULT 0x64000000
+#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_DEFAULT 0x00000090
+#define mmDC_COMBOPHYPLLREGS3_VREG_CFG_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS3_OBSERVE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS3_OBSERVE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS3_DFT_OUT_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dcio_uniphy4_dispdec
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophycmregs4_dispdec
+#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
+#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
+#define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL_DEFAULT 0x00000007
+#define mmDC_COMBOPHYCMREGS4_COMMON_TMDP_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS_DEFAULT 0x000000ff
+#define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophytxregs4_dispdec
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophypllregs4_dispdec
+#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0_DEFAULT 0x00280000
+#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3_DEFAULT 0x00e80000
+#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
+#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE_DEFAULT 0x00000001
+#define mmDC_COMBOPHYPLLREGS4_CAL_CTRL_DEFAULT 0x64000000
+#define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL_DEFAULT 0x00000090
+#define mmDC_COMBOPHYPLLREGS4_VREG_CFG_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS4_OBSERVE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS4_OBSERVE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS4_DFT_OUT_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dcio_uniphy5_dispdec
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophycmregs5_dispdec
+#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
+#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
+#define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL_DEFAULT 0x00000007
+#define mmDC_COMBOPHYCMREGS5_COMMON_TMDP_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS_DEFAULT 0x000000ff
+#define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophytxregs5_dispdec
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophypllregs5_dispdec
+#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0_DEFAULT 0x00280000
+#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3_DEFAULT 0x00e80000
+#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
+#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE_DEFAULT 0x00000001
+#define mmDC_COMBOPHYPLLREGS5_CAL_CTRL_DEFAULT 0x64000000
+#define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL_DEFAULT 0x00000090
+#define mmDC_COMBOPHYPLLREGS5_VREG_CFG_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS5_OBSERVE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS5_OBSERVE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS5_DFT_OUT_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dcio_uniphy6_dispdec
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophycmregs6_dispdec
+#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
+#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
+#define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL_DEFAULT 0x00000007
+#define mmDC_COMBOPHYCMREGS6_COMMON_TMDP_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS_DEFAULT 0x000000ff
+#define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophytxregs6_dispdec
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophypllregs6_dispdec
+#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0_DEFAULT 0x00280000
+#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3_DEFAULT 0x00e80000
+#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
+#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE_DEFAULT 0x00000001
+#define mmDC_COMBOPHYPLLREGS6_CAL_CTRL_DEFAULT 0x64000000
+#define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL_DEFAULT 0x00000090
+#define mmDC_COMBOPHYPLLREGS6_VREG_CFG_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS6_OBSERVE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS6_OBSERVE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS6_DFT_OUT_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dcio_uniphy8_dispdec
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophycmregs8_dispdec
+#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00
+#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004
+#define mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL_DEFAULT 0x00000007
+#define mmDC_COMBOPHYCMREGS8_COMMON_TMDP_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS_DEFAULT 0x000000ff
+#define mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6_DEFAULT 0x00000000
+#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophytxregs8_dispdec
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006
+#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_combophypllregs8_dispdec
+#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0_DEFAULT 0x00280000
+#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3_DEFAULT 0x00e80000
+#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
+#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE_DEFAULT 0x00000001
+#define mmDC_COMBOPHYPLLREGS8_CAL_CTRL_DEFAULT 0x64000000
+#define mmDC_COMBOPHYPLLREGS8_LOOP_CTRL_DEFAULT 0x00000090
+#define mmDC_COMBOPHYPLLREGS8_VREG_CFG_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS8_OBSERVE0_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS8_OBSERVE1_DEFAULT 0x00000000
+#define mmDC_COMBOPHYPLLREGS8_DFT_OUT_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dsi0_dispdec
+#define mmDSI0_DISP_DSI_CTRL_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_STATUS_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_VIDEO_MODE_CTRL_DEFAULT 0x00008000
+#define mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_DEFAULT 0x31211101
+#define mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_DEFAULT 0x3e2e1e0e
+#define mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_DEFAULT 0x00001900
+#define mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_COMMAND_MODE_CTRL_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL_DEFAULT 0x00000066
+#define mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_DEFAULT 0x00003c2c
+#define mmDSI0_DISP_DSI_DMA_CMD_OFFSET_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_DMA_CMD_LENGTH_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_DMA_DATA_PITCH_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_DMA_DATA_WIDTH_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_DMA_DATA_HEIGHT_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_DMA_FIFO_CTRL_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA_DEFAULT 0x00000900
+#define mmDSI0_DISP_DSI_DENG_DATA_LENGTH_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_ACK_ERROR_REPORT_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_RDBK_DATA0_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_RDBK_DATA1_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_RDBK_DATA2_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_RDBK_DATA3_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_RDBK_DATATYPE0_DEFAULT 0x22211211
+#define mmDSI0_DISP_DSI_RDBK_DATATYPE1_DEFAULT 0x001c1a02
+#define mmDSI0_DISP_DSI_TRIG_CTRL_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_EXT_MUX_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_RESET_SW_TRIGGER_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_EXT_RESET_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_LANE_CRC_HS_MODE_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_LANE_CRC_LP_MODE_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_LANE_CRC_CTRL_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_PIXEL_CRC_CTRL_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_LANE_CTRL_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_DLN0_PHY_ERROR_DEFAULT 0x00088888
+#define mmDSI0_DISP_DSI_LP_TIMER_CTRL_DEFAULT 0xffffffff
+#define mmDSI0_DISP_DSI_HS_TIMER_CTRL_DEFAULT 0x0000ffff
+#define mmDSI0_DISP_DSI_TIMEOUT_STATUS_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_EOT_PACKET_DEFAULT 0x010f0f08
+#define mmDSI0_DISP_DSI_EOT_PACKET_CTRL_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_MIPI_BIST_CTRL_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_MIPI_BIST_START_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_MIPI_BIST_STATUS_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK_DEFAULT 0xfd37377f
+#define mmDSI0_DISP_DSI_INTERRUPT_CTRL_DEFAULT 0x02222222
+#define mmDSI0_DISP_DSI_CLK_CTRL_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_CLK_STATUS_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_DENG_FIFO_STATUS_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_DENG_FIFO_CTRL_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_CMD_FIFO_DATA_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_CMD_FIFO_CTRL_DEFAULT 0x00000001
+#define mmDSI0_DISP_DSI_TE_CTRL_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_LANE_STATUS_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_PERF_CTRL_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_HSYNC_LENGTH_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_RDBK_NUM_DEFAULT 0x00000000
+#define mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dsi1_dispdec
+#define mmDSI1_DISP_DSI_CTRL_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_STATUS_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_VIDEO_MODE_CTRL_DEFAULT 0x00008000
+#define mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_DEFAULT 0x31211101
+#define mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_DEFAULT 0x3e2e1e0e
+#define mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_DEFAULT 0x00001900
+#define mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_COMMAND_MODE_CTRL_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL_DEFAULT 0x00000066
+#define mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_DEFAULT 0x00003c2c
+#define mmDSI1_DISP_DSI_DMA_CMD_OFFSET_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_DMA_CMD_LENGTH_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_DMA_DATA_PITCH_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_DMA_DATA_WIDTH_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_DMA_DATA_HEIGHT_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_DMA_FIFO_CTRL_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA_DEFAULT 0x00000900
+#define mmDSI1_DISP_DSI_DENG_DATA_LENGTH_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_ACK_ERROR_REPORT_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_RDBK_DATA0_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_RDBK_DATA1_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_RDBK_DATA2_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_RDBK_DATA3_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_RDBK_DATATYPE0_DEFAULT 0x22211211
+#define mmDSI1_DISP_DSI_RDBK_DATATYPE1_DEFAULT 0x001c1a02
+#define mmDSI1_DISP_DSI_TRIG_CTRL_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_EXT_MUX_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_RESET_SW_TRIGGER_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_EXT_RESET_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_LANE_CRC_HS_MODE_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_LANE_CRC_LP_MODE_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_LANE_CRC_CTRL_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_PIXEL_CRC_CTRL_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_LANE_CTRL_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_DLN0_PHY_ERROR_DEFAULT 0x00088888
+#define mmDSI1_DISP_DSI_LP_TIMER_CTRL_DEFAULT 0xffffffff
+#define mmDSI1_DISP_DSI_HS_TIMER_CTRL_DEFAULT 0x0000ffff
+#define mmDSI1_DISP_DSI_TIMEOUT_STATUS_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_EOT_PACKET_DEFAULT 0x010f0f08
+#define mmDSI1_DISP_DSI_EOT_PACKET_CTRL_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_MIPI_BIST_CTRL_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_MIPI_BIST_START_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_MIPI_BIST_STATUS_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK_DEFAULT 0xfd37377f
+#define mmDSI1_DISP_DSI_INTERRUPT_CTRL_DEFAULT 0x02222222
+#define mmDSI1_DISP_DSI_CLK_CTRL_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_CLK_STATUS_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_DENG_FIFO_STATUS_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_DENG_FIFO_CTRL_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_CMD_FIFO_DATA_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_CMD_FIFO_CTRL_DEFAULT 0x00000001
+#define mmDSI1_DISP_DSI_TE_CTRL_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_LANE_STATUS_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_PERF_CTRL_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_HSYNC_LENGTH_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_RDBK_NUM_DEFAULT 0x00000000
+#define mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dprx_sd0_dispdec
+#define mmDPRX_SD0_DPRX_SD_CONTROL_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_STREAM_ENABLE_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_MSA0_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_MSA1_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_MSA2_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_MSA3_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_MSA4_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_MSA5_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_MSA6_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_MSA7_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_MSA8_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_VBID_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_CURRENT_LINE_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_MSE_SAT_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_V_PARAMETER_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL_DEFAULT 0x0000ffff
+#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL_DEFAULT 0x0000ffff
+#define mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_DEFAULT 0x000003ff
+#define mmDPRX_SD0_DPRX_SD_SDP_STEER_DEFAULT 0x00000001
+#define mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_SDP_LEVEL_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_SDP_DATA_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_SDP_ERROR_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_AUDIO_HEADER_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_SDP_CONTROL_DEFAULT 0x00000001
+#define mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_BS_COUNTER_DEFAULT 0x00000000
+#define mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dprx_sd1_dispdec
+#define mmDPRX_SD1_DPRX_SD_CONTROL_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_STREAM_ENABLE_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_MSA0_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_MSA1_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_MSA2_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_MSA3_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_MSA4_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_MSA5_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_MSA6_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_MSA7_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_MSA8_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_VBID_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_CURRENT_LINE_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_MSE_SAT_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_V_PARAMETER_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL_DEFAULT 0x0000ffff
+#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL_DEFAULT 0x0000ffff
+#define mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_DEFAULT 0x000003ff
+#define mmDPRX_SD1_DPRX_SD_SDP_STEER_DEFAULT 0x00000001
+#define mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_SDP_LEVEL_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_SDP_DATA_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_SDP_ERROR_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_AUDIO_HEADER_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_SDP_CONTROL_DEFAULT 0x00000001
+#define mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_BS_COUNTER_DEFAULT 0x00000000
+#define mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_perfmon10_dispdec
+#define mmDC_PERFMON10_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON10_PERFCOUNTER_STATE_DEFAULT 0x00000000
+#define mmDC_PERFMON10_PERFMON_CNTL_DEFAULT 0x00000100
+#define mmDC_PERFMON10_PERFMON_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+#define mmDC_PERFMON10_PERFMON_HI_DEFAULT 0x00000000
+#define mmDC_PERFMON10_PERFMON_LOW_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_zcalregs_dispdec
+#define mmCOMP_EN_CTL_DEFAULT 0x00080000
+#define mmCOMP_EN_DFX_DEFAULT 0x00000000
+#define mmZCAL_FUSES_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
+
+
+// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
+
+
+// addressBlock: dce_dc_dispdec[948..986]
+
+
+// addressBlock: dce_dc_azdec
+#define mmCORB_WRITE_POINTER_DEFAULT 0x00000000
+#define mmCORB_READ_POINTER_DEFAULT 0x00000000
+#define mmCORB_CONTROL_DEFAULT 0x00000000
+#define mmCORB_STATUS_DEFAULT 0x00000000
+#define mmCORB_SIZE_DEFAULT 0x00000002
+#define mmRIRB_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmRIRB_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmRIRB_WRITE_POINTER_DEFAULT 0x00000000
+#define mmRESPONSE_INTERRUPT_COUNT_DEFAULT 0x00000000
+#define mmRIRB_CONTROL_DEFAULT 0x00000000
+#define mmRIRB_STATUS_DEFAULT 0x00000000
+#define mmRIRB_SIZE_DEFAULT 0x00000002
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_DEFAULT 0x00000000
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_DEFAULT 0x00000000
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000
+#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000
+#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DEFAULT 0x00000000
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000
+#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_DEFAULT 0x00000000
+#define mmIMMEDIATE_COMMAND_STATUS_DEFAULT 0x00000000
+#define mmDMA_POSITION_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmDMA_POSITION_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmWALL_CLOCK_COUNTER_ALIAS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azstream0_azdec
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azstream1_azdec
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azstream2_azdec
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azstream3_azdec
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azstream4_azdec
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azstream5_azdec
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azstream6_azdec
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_azstream7_azdec
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000
+
+
+// addressBlock: azf0stream0_streamind
+#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+
+
+// addressBlock: azf0stream1_streamind
+#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+
+
+// addressBlock: azf0stream2_streamind
+#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+
+
+// addressBlock: azf0stream3_streamind
+#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+
+
+// addressBlock: azf0stream4_streamind
+#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+
+
+// addressBlock: azf0stream5_streamind
+#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+
+
+// addressBlock: azf0stream6_streamind
+#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+
+
+// addressBlock: azf0stream7_streamind
+#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+
+
+// addressBlock: azf0stream8_streamind
+#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+
+
+// addressBlock: azf0stream9_streamind
+#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+
+
+// addressBlock: azf0stream10_streamind
+#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+
+
+// addressBlock: azf0stream11_streamind
+#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+
+
+// addressBlock: azf0stream12_streamind
+#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+
+
+// addressBlock: azf0stream13_streamind
+#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+
+
+// addressBlock: azf0stream14_streamind
+#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+
+
+// addressBlock: azf0stream15_streamind
+#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004
+#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000
+#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000
+
+
+// addressBlock: azf0endpoint0_endpointind
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: azf0endpoint1_endpointind
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: azf0endpoint2_endpointind
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: azf0endpoint3_endpointind
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: azf0endpoint4_endpointind
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: azf0endpoint5_endpointind
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: azf0endpoint6_endpointind
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: azf0endpoint7_endpointind
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: azf0inputendpoint0_inputendpointind
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
+
+
+// addressBlock: azf0inputendpoint1_inputendpointind
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
+
+
+// addressBlock: azf0inputendpoint2_inputendpointind
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
+
+
+// addressBlock: azf0inputendpoint3_inputendpointind
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
+
+
+// addressBlock: azf0inputendpoint4_inputendpointind
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
+
+
+// addressBlock: azf0inputendpoint5_inputendpointind
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
+
+
+// addressBlock: azf0inputendpoint6_inputendpointind
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
+
+
+// addressBlock: azf0inputendpoint7_inputendpointind
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
+
+
+// addressBlock: f2codecind
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE_DEFAULT 0x00000003
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2_DEFAULT 0x00000001
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3_DEFAULT 0x000000aa
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x000000b4
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000020
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000040
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x00000010
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3_DEFAULT 0x00000056
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4_DEFAULT 0x00000018
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000020
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x000000f0
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3_DEFAULT 0x000000d6
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4_DEFAULT 0x00000018
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000010
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000000
+
+
+// addressBlock: descriptorind
+#define ixAUDIO_DESCRIPTOR0_DEFAULT 0x00000000
+#define ixAUDIO_DESCRIPTOR1_DEFAULT 0x00000000
+#define ixAUDIO_DESCRIPTOR2_DEFAULT 0x00000000
+#define ixAUDIO_DESCRIPTOR3_DEFAULT 0x00000000
+#define ixAUDIO_DESCRIPTOR4_DEFAULT 0x00000000
+#define ixAUDIO_DESCRIPTOR5_DEFAULT 0x00000000
+#define ixAUDIO_DESCRIPTOR6_DEFAULT 0x00000000
+#define ixAUDIO_DESCRIPTOR7_DEFAULT 0x00000000
+#define ixAUDIO_DESCRIPTOR8_DEFAULT 0x00000000
+#define ixAUDIO_DESCRIPTOR9_DEFAULT 0x00000000
+#define ixAUDIO_DESCRIPTOR10_DEFAULT 0x00000000
+#define ixAUDIO_DESCRIPTOR11_DEFAULT 0x00000000
+#define ixAUDIO_DESCRIPTOR12_DEFAULT 0x00000000
+#define ixAUDIO_DESCRIPTOR13_DEFAULT 0x00000000
+
+
+// addressBlock: sinkinfoind
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0_DEFAULT 0x00000000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1_DEFAULT 0x00000000
+#define ixSINK_DESCRIPTION0_DEFAULT 0x00000000
+#define ixSINK_DESCRIPTION1_DEFAULT 0x00000000
+#define ixSINK_DESCRIPTION2_DEFAULT 0x00000000
+#define ixSINK_DESCRIPTION3_DEFAULT 0x00000000
+#define ixSINK_DESCRIPTION4_DEFAULT 0x00000000
+#define ixSINK_DESCRIPTION5_DEFAULT 0x00000000
+#define ixSINK_DESCRIPTION6_DEFAULT 0x00000000
+#define ixSINK_DESCRIPTION7_DEFAULT 0x00000000
+#define ixSINK_DESCRIPTION8_DEFAULT 0x00000000
+#define ixSINK_DESCRIPTION9_DEFAULT 0x00000000
+#define ixSINK_DESCRIPTION10_DEFAULT 0x00000000
+#define ixSINK_DESCRIPTION11_DEFAULT 0x00000000
+#define ixSINK_DESCRIPTION12_DEFAULT 0x00000000
+#define ixSINK_DESCRIPTION13_DEFAULT 0x00000000
+#define ixSINK_DESCRIPTION14_DEFAULT 0x00000000
+#define ixSINK_DESCRIPTION15_DEFAULT 0x00000000
+#define ixSINK_DESCRIPTION16_DEFAULT 0x00000000
+#define ixSINK_DESCRIPTION17_DEFAULT 0x00000000
+
+
+// addressBlock: azinputcrc0resultind
+#define ixAZALIA_INPUT_CRC0_CHANNEL0_DEFAULT 0x00000000
+#define ixAZALIA_INPUT_CRC0_CHANNEL1_DEFAULT 0x00000000
+#define ixAZALIA_INPUT_CRC0_CHANNEL2_DEFAULT 0x00000000
+#define ixAZALIA_INPUT_CRC0_CHANNEL3_DEFAULT 0x00000000
+#define ixAZALIA_INPUT_CRC0_CHANNEL4_DEFAULT 0x00000000
+#define ixAZALIA_INPUT_CRC0_CHANNEL5_DEFAULT 0x00000000
+#define ixAZALIA_INPUT_CRC0_CHANNEL6_DEFAULT 0x00000000
+#define ixAZALIA_INPUT_CRC0_CHANNEL7_DEFAULT 0x00000000
+
+
+// addressBlock: azinputcrc1resultind
+#define ixAZALIA_INPUT_CRC1_CHANNEL0_DEFAULT 0x00000000
+#define ixAZALIA_INPUT_CRC1_CHANNEL1_DEFAULT 0x00000000
+#define ixAZALIA_INPUT_CRC1_CHANNEL2_DEFAULT 0x00000000
+#define ixAZALIA_INPUT_CRC1_CHANNEL3_DEFAULT 0x00000000
+#define ixAZALIA_INPUT_CRC1_CHANNEL4_DEFAULT 0x00000000
+#define ixAZALIA_INPUT_CRC1_CHANNEL5_DEFAULT 0x00000000
+#define ixAZALIA_INPUT_CRC1_CHANNEL6_DEFAULT 0x00000000
+#define ixAZALIA_INPUT_CRC1_CHANNEL7_DEFAULT 0x00000000
+
+
+// addressBlock: azcrc0resultind
+#define ixAZALIA_CRC0_CHANNEL0_DEFAULT 0x00000000
+#define ixAZALIA_CRC0_CHANNEL1_DEFAULT 0x00000000
+#define ixAZALIA_CRC0_CHANNEL2_DEFAULT 0x00000000
+#define ixAZALIA_CRC0_CHANNEL3_DEFAULT 0x00000000
+#define ixAZALIA_CRC0_CHANNEL4_DEFAULT 0x00000000
+#define ixAZALIA_CRC0_CHANNEL5_DEFAULT 0x00000000
+#define ixAZALIA_CRC0_CHANNEL6_DEFAULT 0x00000000
+#define ixAZALIA_CRC0_CHANNEL7_DEFAULT 0x00000000
+
+
+// addressBlock: azcrc1resultind
+#define ixAZALIA_CRC1_CHANNEL0_DEFAULT 0x00000000
+#define ixAZALIA_CRC1_CHANNEL1_DEFAULT 0x00000000
+#define ixAZALIA_CRC1_CHANNEL2_DEFAULT 0x00000000
+#define ixAZALIA_CRC1_CHANNEL3_DEFAULT 0x00000000
+#define ixAZALIA_CRC1_CHANNEL4_DEFAULT 0x00000000
+#define ixAZALIA_CRC1_CHANNEL5_DEFAULT 0x00000000
+#define ixAZALIA_CRC1_CHANNEL6_DEFAULT 0x00000000
+#define ixAZALIA_CRC1_CHANNEL7_DEFAULT 0x00000000
+
+
+// addressBlock: vgaseqind
+#define ixSEQ00_DEFAULT 0x00000003
+#define ixSEQ01_DEFAULT 0x00000021
+#define ixSEQ02_DEFAULT 0x00000000
+#define ixSEQ03_DEFAULT 0x00000000
+#define ixSEQ04_DEFAULT 0x00000000
+
+
+// addressBlock: vgacrtind
+#define ixCRT00_DEFAULT 0x00000000
+#define ixCRT01_DEFAULT 0x00000000
+#define ixCRT02_DEFAULT 0x00000000
+#define ixCRT03_DEFAULT 0x00000000
+#define ixCRT04_DEFAULT 0x00000000
+#define ixCRT05_DEFAULT 0x00000000
+#define ixCRT06_DEFAULT 0x00000000
+#define ixCRT07_DEFAULT 0x00000000
+#define ixCRT08_DEFAULT 0x00000000
+#define ixCRT09_DEFAULT 0x00000000
+#define ixCRT0A_DEFAULT 0x00000000
+#define ixCRT0B_DEFAULT 0x00000000
+#define ixCRT0C_DEFAULT 0x00000000
+#define ixCRT0D_DEFAULT 0x00000000
+#define ixCRT0E_DEFAULT 0x00000000
+#define ixCRT0F_DEFAULT 0x00000000
+#define ixCRT10_DEFAULT 0x00000000
+#define ixCRT11_DEFAULT 0x00000000
+#define ixCRT12_DEFAULT 0x00000000
+#define ixCRT13_DEFAULT 0x00000000
+#define ixCRT14_DEFAULT 0x00000000
+#define ixCRT15_DEFAULT 0x00000000
+#define ixCRT16_DEFAULT 0x00000000
+#define ixCRT17_DEFAULT 0x00000000
+#define ixCRT18_DEFAULT 0x00000000
+#define ixCRT1E_DEFAULT 0x00000000
+#define ixCRT1F_DEFAULT 0x00000000
+#define ixCRT22_DEFAULT 0x00000000
+
+
+// addressBlock: vgagrphind
+#define ixGRA00_DEFAULT 0x00000000
+#define ixGRA01_DEFAULT 0x00000000
+#define ixGRA02_DEFAULT 0x00000000
+#define ixGRA03_DEFAULT 0x00000000
+#define ixGRA04_DEFAULT 0x00000000
+#define ixGRA05_DEFAULT 0x00000000
+#define ixGRA06_DEFAULT 0x00000000
+#define ixGRA07_DEFAULT 0x00000000
+#define ixGRA08_DEFAULT 0x00000000
+
+
+// addressBlock: vgaattrind
+#define ixATTR00_DEFAULT 0x00000000
+#define ixATTR01_DEFAULT 0x00000000
+#define ixATTR02_DEFAULT 0x00000000
+#define ixATTR03_DEFAULT 0x00000000
+#define ixATTR04_DEFAULT 0x00000000
+#define ixATTR05_DEFAULT 0x00000000
+#define ixATTR06_DEFAULT 0x00000000
+#define ixATTR07_DEFAULT 0x00000000
+#define ixATTR08_DEFAULT 0x00000000
+#define ixATTR09_DEFAULT 0x00000000
+#define ixATTR0A_DEFAULT 0x00000000
+#define ixATTR0B_DEFAULT 0x00000000
+#define ixATTR0C_DEFAULT 0x00000000
+#define ixATTR0D_DEFAULT 0x00000000
+#define ixATTR0E_DEFAULT 0x00000000
+#define ixATTR0F_DEFAULT 0x00000000
+#define ixATTR10_DEFAULT 0x00000000
+#define ixATTR11_DEFAULT 0x00000000
+#define ixATTR12_DEFAULT 0x00000000
+#define ixATTR13_DEFAULT 0x00000000
+#define ixATTR14_DEFAULT 0x00000000
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h
new file mode 100644
index 000000000000..75b660d57bdf
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h
@@ -0,0 +1,18193 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dce_12_0_OFFSET_HEADER
+#define _dce_12_0_OFFSET_HEADER
+
+
+
+// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
+// base address: 0x48
+#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR 0x0012
+#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
+
+
+// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
+// base address: 0x4c
+#define mmdispdec_VGA_MEM_READ_PAGE_ADDR 0x0014
+#define mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
+
+
+// addressBlock: dce_dc_dc_perfmon0_dispdec
+// base address: 0x0
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0020
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0021
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0022
+#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON0_PERFMON_CNTL 0x0023
+#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON0_PERFMON_CNTL2 0x0024
+#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0025
+#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0026
+#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON0_PERFMON_HI 0x0027
+#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON0_PERFMON_LOW 0x0028
+#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_perfmon13_dispdec
+// base address: 0x30
+#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x002c
+#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x002d
+#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x002e
+#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON13_PERFMON_CNTL 0x002f
+#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON13_PERFMON_CNTL2 0x0030
+#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x0031
+#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x0032
+#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON13_PERFMON_HI 0x0033
+#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON13_PERFMON_LOW 0x0034
+#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_displaypllregs_dispdec
+// base address: 0x0
+#define mmPPLL_VREG_CFG 0x0038
+#define mmPPLL_VREG_CFG_BASE_IDX 2
+#define mmPPLL_MODE_CNTL 0x0039
+#define mmPPLL_MODE_CNTL_BASE_IDX 2
+#define mmPPLL_FREQ_CTRL0 0x003a
+#define mmPPLL_FREQ_CTRL0_BASE_IDX 2
+#define mmPPLL_FREQ_CTRL1 0x003b
+#define mmPPLL_FREQ_CTRL1_BASE_IDX 2
+#define mmPPLL_FREQ_CTRL2 0x003c
+#define mmPPLL_FREQ_CTRL2_BASE_IDX 2
+#define mmPPLL_FREQ_CTRL3 0x003d
+#define mmPPLL_FREQ_CTRL3_BASE_IDX 2
+#define mmPPLL_BW_CTRL_COARSE 0x003e
+#define mmPPLL_BW_CTRL_COARSE_BASE_IDX 2
+#define mmPPLL_BW_CTRL_FINE 0x0040
+#define mmPPLL_BW_CTRL_FINE_BASE_IDX 2
+#define mmPPLL_CAL_CTRL 0x0041
+#define mmPPLL_CAL_CTRL_BASE_IDX 2
+#define mmPPLL_LOOP_CTRL 0x0042
+#define mmPPLL_LOOP_CTRL_BASE_IDX 2
+#define mmPPLL_REFCLK_CNTL 0x0050
+#define mmPPLL_REFCLK_CNTL_BASE_IDX 2
+#define mmPPLL_CLKOUT_CNTL 0x0051
+#define mmPPLL_CLKOUT_CNTL_BASE_IDX 2
+#define mmPPLL_DFT_CNTL 0x0052
+#define mmPPLL_DFT_CNTL_BASE_IDX 2
+#define mmPPLL_ANALOG_CNTL 0x0053
+#define mmPPLL_ANALOG_CNTL_BASE_IDX 2
+#define mmPPLL_POSTDIV 0x0054
+#define mmPPLL_POSTDIV_BASE_IDX 2
+#define mmPPLL_OBSERVE0 0x0059
+#define mmPPLL_OBSERVE0_BASE_IDX 2
+#define mmPPLL_OBSERVE1 0x005a
+#define mmPPLL_OBSERVE1_BASE_IDX 2
+#define mmPPLL_UPDATE_CNTL 0x005c
+#define mmPPLL_UPDATE_CNTL_BASE_IDX 2
+#define mmPPLL_OBSERVE0_OUT 0x005d
+#define mmPPLL_OBSERVE0_OUT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dccg_pll0_dispdec
+// base address: 0x0
+#define mmPLL_MACRO_CNTL_RESERVED0 0x0038
+#define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED1 0x0039
+#define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED2 0x003a
+#define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED3 0x003b
+#define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED4 0x003c
+#define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED5 0x003d
+#define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED6 0x003e
+#define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED7 0x003f
+#define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED8 0x0040
+#define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED9 0x0041
+#define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED10 0x0042
+#define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED11 0x0043
+#define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED12 0x0044
+#define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED13 0x0045
+#define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED14 0x0046
+#define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED15 0x0047
+#define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED16 0x0048
+#define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED17 0x0049
+#define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED18 0x004a
+#define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED19 0x004b
+#define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED20 0x004c
+#define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED21 0x004d
+#define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED22 0x004e
+#define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED23 0x004f
+#define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED24 0x0050
+#define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED25 0x0051
+#define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED26 0x0052
+#define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED27 0x0053
+#define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED28 0x0054
+#define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED29 0x0055
+#define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED30 0x0056
+#define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED31 0x0057
+#define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED32 0x0058
+#define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED33 0x0059
+#define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED34 0x005a
+#define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED35 0x005b
+#define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED36 0x005c
+#define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED37 0x005d
+#define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED38 0x005e
+#define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED39 0x005f
+#define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED40 0x0060
+#define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED41 0x0061
+#define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_perfmon1_dispdec
+// base address: 0x598
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x0186
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x0187
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x0188
+#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON1_PERFMON_CNTL 0x0189
+#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON1_PERFMON_CNTL2 0x018a
+#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x018b
+#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x018c
+#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON1_PERFMON_HI 0x018d
+#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON1_PERFMON_LOW 0x018e
+#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mcif_wb0_dispdec
+// base address: 0x0
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x0272
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x0273
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x0274
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x0275
+#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x0276
+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x0277
+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x0278
+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x0279
+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x027a
+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x027b
+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x027c
+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x027d
+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x027e
+#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE 0x027f
+#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x0282
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0283
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x0284
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0285
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x0286
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0287
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x0288
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0289
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x028a
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x028b
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x028c
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x028d
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x028e
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x028f
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x0290
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0291
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x0292
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0293
+#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL 0x0294
+#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_WATERMARK 0x0295
+#define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL 0x0296
+#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL 0x0297
+#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL 0x0298
+#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
+#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0x0299
+#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0x029b
+#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0x029c
+#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mcif_wb1_dispdec
+// base address: 0x100
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x02b2
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x02b3
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x02b4
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x02b5
+#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x02b6
+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x02b7
+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x02b8
+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x02b9
+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x02ba
+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x02bb
+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x02bc
+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x02bd
+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x02be
+#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE 0x02bf
+#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x02c2
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x02c3
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x02c4
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x02c5
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x02c6
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x02c7
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x02c8
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x02c9
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x02ca
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x02cb
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x02cc
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x02cd
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x02ce
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x02cf
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x02d0
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x02d1
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x02d2
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02d3
+#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 0x02d4
+#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_WATERMARK 0x02d5
+#define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL 0x02d6
+#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL 0x02d7
+#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL 0x02d8
+#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
+#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL 0x02d9
+#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE 0x02db
+#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE 0x02dc
+#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mcif_wb2_dispdec
+// base address: 0x200
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x02f2
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x02f3
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x02f4
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x02f5
+#define mmMCIF_WB2_MCIF_WB_BUF_PITCH_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x02f6
+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x02f7
+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x02f8
+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x02f9
+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x02fa
+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x02fb
+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x02fc
+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x02fd
+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x02fe
+#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE 0x02ff
+#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x0302
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0303
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x0304
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0305
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x0306
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0307
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x0308
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0309
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x030a
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x030b
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x030c
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x030d
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x030e
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x030f
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x0310
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0311
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x0312
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0313
+#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL 0x0314
+#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_WATERMARK 0x0315
+#define mmMCIF_WB2_MCIF_WB_WATERMARK_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL 0x0316
+#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL 0x0317
+#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL 0x0318
+#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
+#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL 0x0319
+#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE 0x031b
+#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE 0x031c
+#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_cwb0_dispdec
+// base address: 0x0
+#define mmCWB0_CWB_CTRL 0x0332
+#define mmCWB0_CWB_CTRL_BASE_IDX 2
+#define mmCWB0_CWB_FENCE_PAR0 0x0334
+#define mmCWB0_CWB_FENCE_PAR0_BASE_IDX 2
+#define mmCWB0_CWB_FENCE_PAR1 0x0335
+#define mmCWB0_CWB_FENCE_PAR1_BASE_IDX 2
+#define mmCWB0_CWB_CRC_CTRL 0x0339
+#define mmCWB0_CWB_CRC_CTRL_BASE_IDX 2
+#define mmCWB0_CWB_CRC_RED_GREEN_MASK 0x033a
+#define mmCWB0_CWB_CRC_RED_GREEN_MASK_BASE_IDX 2
+#define mmCWB0_CWB_CRC_BLUE_MASK 0x033b
+#define mmCWB0_CWB_CRC_BLUE_MASK_BASE_IDX 2
+#define mmCWB0_CWB_CRC_RED_GREEN_RESULT 0x033c
+#define mmCWB0_CWB_CRC_RED_GREEN_RESULT_BASE_IDX 2
+#define mmCWB0_CWB_CRC_BLUE_RESULT 0x033d
+#define mmCWB0_CWB_CRC_BLUE_RESULT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_cwb1_dispdec
+// base address: 0x60
+#define mmCWB1_CWB_CTRL 0x034a
+#define mmCWB1_CWB_CTRL_BASE_IDX 2
+#define mmCWB1_CWB_FENCE_PAR0 0x034c
+#define mmCWB1_CWB_FENCE_PAR0_BASE_IDX 2
+#define mmCWB1_CWB_FENCE_PAR1 0x034d
+#define mmCWB1_CWB_FENCE_PAR1_BASE_IDX 2
+#define mmCWB1_CWB_CRC_CTRL 0x0351
+#define mmCWB1_CWB_CRC_CTRL_BASE_IDX 2
+#define mmCWB1_CWB_CRC_RED_GREEN_MASK 0x0352
+#define mmCWB1_CWB_CRC_RED_GREEN_MASK_BASE_IDX 2
+#define mmCWB1_CWB_CRC_BLUE_MASK 0x0353
+#define mmCWB1_CWB_CRC_BLUE_MASK_BASE_IDX 2
+#define mmCWB1_CWB_CRC_RED_GREEN_RESULT 0x0354
+#define mmCWB1_CWB_CRC_RED_GREEN_RESULT_BASE_IDX 2
+#define mmCWB1_CWB_CRC_BLUE_RESULT 0x0355
+#define mmCWB1_CWB_CRC_BLUE_RESULT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_perfmon9_dispdec
+// base address: 0xd08
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x0362
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x0363
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x0364
+#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON9_PERFMON_CNTL 0x0365
+#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON9_PERFMON_CNTL2 0x0366
+#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x0367
+#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x0368
+#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON9_PERFMON_HI 0x0369
+#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON9_PERFMON_LOW 0x036a
+#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dispdec
+// base address: 0x0
+#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000
+#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
+#define mmVGA_MEM_READ_PAGE_ADDR 0x0001
+#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
+#define mmVGA_RENDER_CONTROL 0x0000
+#define mmVGA_RENDER_CONTROL_BASE_IDX 1
+#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001
+#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1
+#define mmVGA_MODE_CONTROL 0x0002
+#define mmVGA_MODE_CONTROL_BASE_IDX 1
+#define mmVGA_SURFACE_PITCH_SELECT 0x0003
+#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1
+#define mmVGA_MEMORY_BASE_ADDRESS 0x0004
+#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1
+#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006
+#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1
+#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008
+#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1
+#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009
+#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1
+#define mmVGA_HDP_CONTROL 0x000a
+#define mmVGA_HDP_CONTROL_BASE_IDX 1
+#define mmVGA_CACHE_CONTROL 0x000b
+#define mmVGA_CACHE_CONTROL_BASE_IDX 1
+#define mmD1VGA_CONTROL 0x000c
+#define mmD1VGA_CONTROL_BASE_IDX 1
+#define mmD2VGA_CONTROL 0x000e
+#define mmD2VGA_CONTROL_BASE_IDX 1
+#define mmVGA_STATUS 0x0010
+#define mmVGA_STATUS_BASE_IDX 1
+#define mmVGA_INTERRUPT_CONTROL 0x0011
+#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1
+#define mmVGA_STATUS_CLEAR 0x0012
+#define mmVGA_STATUS_CLEAR_BASE_IDX 1
+#define mmVGA_INTERRUPT_STATUS 0x0013
+#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1
+#define mmVGA_MAIN_CONTROL 0x0014
+#define mmVGA_MAIN_CONTROL_BASE_IDX 1
+#define mmVGA_TEST_CONTROL 0x0015
+#define mmVGA_TEST_CONTROL_BASE_IDX 1
+#define mmVGA_QOS_CTRL 0x0018
+#define mmVGA_QOS_CTRL_BASE_IDX 1
+#define mmCRTC8_IDX 0x002d
+#define mmCRTC8_IDX_BASE_IDX 1
+#define mmCRTC8_DATA 0x002d
+#define mmCRTC8_DATA_BASE_IDX 1
+#define mmGENFC_WT 0x002e
+#define mmGENFC_WT_BASE_IDX 1
+#define mmGENS1 0x002e
+#define mmGENS1_BASE_IDX 1
+#define mmATTRDW 0x0030
+#define mmATTRDW_BASE_IDX 1
+#define mmATTRX 0x0030
+#define mmATTRX_BASE_IDX 1
+#define mmATTRDR 0x0030
+#define mmATTRDR_BASE_IDX 1
+#define mmGENMO_WT 0x0030
+#define mmGENMO_WT_BASE_IDX 1
+#define mmGENS0 0x0030
+#define mmGENS0_BASE_IDX 1
+#define mmGENENB 0x0030
+#define mmGENENB_BASE_IDX 1
+#define mmSEQ8_IDX 0x0031
+#define mmSEQ8_IDX_BASE_IDX 1
+#define mmSEQ8_DATA 0x0031
+#define mmSEQ8_DATA_BASE_IDX 1
+#define mmDAC_MASK 0x0031
+#define mmDAC_MASK_BASE_IDX 1
+#define mmDAC_R_INDEX 0x0031
+#define mmDAC_R_INDEX_BASE_IDX 1
+#define mmDAC_W_INDEX 0x0032
+#define mmDAC_W_INDEX_BASE_IDX 1
+#define mmDAC_DATA 0x0032
+#define mmDAC_DATA_BASE_IDX 1
+#define mmGENFC_RD 0x0032
+#define mmGENFC_RD_BASE_IDX 1
+#define mmGENMO_RD 0x0033
+#define mmGENMO_RD_BASE_IDX 1
+#define mmGRPH8_IDX 0x0033
+#define mmGRPH8_IDX_BASE_IDX 1
+#define mmGRPH8_DATA 0x0033
+#define mmGRPH8_DATA_BASE_IDX 1
+#define mmCRTC8_IDX_1 0x0035
+#define mmCRTC8_IDX_1_BASE_IDX 1
+#define mmCRTC8_DATA_1 0x0035
+#define mmCRTC8_DATA_1_BASE_IDX 1
+#define mmGENFC_WT_1 0x0036
+#define mmGENFC_WT_1_BASE_IDX 1
+#define mmGENS1_1 0x0036
+#define mmGENS1_1_BASE_IDX 1
+#define mmD3VGA_CONTROL 0x0038
+#define mmD3VGA_CONTROL_BASE_IDX 1
+#define mmD4VGA_CONTROL 0x0039
+#define mmD4VGA_CONTROL_BASE_IDX 1
+#define mmD5VGA_CONTROL 0x003a
+#define mmD5VGA_CONTROL_BASE_IDX 1
+#define mmD6VGA_CONTROL 0x003b
+#define mmD6VGA_CONTROL_BASE_IDX 1
+#define mmVGA_SOURCE_SELECT 0x003c
+#define mmVGA_SOURCE_SELECT_BASE_IDX 1
+#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
+#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
+#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+#define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
+#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+#define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
+#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL 0x0044
+#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmDCFEV1_CRTC_PIXEL_RATE_CNTL 0x0045
+#define mmDCFEV1_CRTC_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmSYMCLKLPA_CLOCK_ENABLE 0x0046
+#define mmSYMCLKLPA_CLOCK_ENABLE_BASE_IDX 1
+#define mmSYMCLKLPB_CLOCK_ENABLE 0x0047
+#define mmSYMCLKLPB_CLOCK_ENABLE_BASE_IDX 1
+#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048
+#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
+#define mmREFCLK_CNTL 0x0049
+#define mmREFCLK_CNTL_BASE_IDX 1
+#define mmMIPI_CLK_CNTL 0x004a
+#define mmMIPI_CLK_CNTL_BASE_IDX 1
+#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b
+#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
+#define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c
+#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+#define mmDCCG_PERFMON_CNTL2 0x004e
+#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1
+#define mmDSICLK_CGTT_BLK_CTRL_REG 0x004f
+#define mmDSICLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
+#define mmDCCG_CBUS_WRCMD_DELAY 0x0050
+#define mmDCCG_CBUS_WRCMD_DELAY_BASE_IDX 1
+#define mmDCCG_DS_DTO_INCR 0x0053
+#define mmDCCG_DS_DTO_INCR_BASE_IDX 1
+#define mmDCCG_DS_DTO_MODULO 0x0054
+#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1
+#define mmDCCG_DS_CNTL 0x0055
+#define mmDCCG_DS_CNTL_BASE_IDX 1
+#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056
+#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1
+#define mmSYMCLKG_CLOCK_ENABLE 0x0057
+#define mmSYMCLKG_CLOCK_ENABLE_BASE_IDX 1
+#define mmDPREFCLK_CNTL 0x0058
+#define mmDPREFCLK_CNTL_BASE_IDX 1
+#define mmAOMCLK0_CNTL 0x0059
+#define mmAOMCLK0_CNTL_BASE_IDX 1
+#define mmAOMCLK1_CNTL 0x005a
+#define mmAOMCLK1_CNTL_BASE_IDX 1
+#define mmAOMCLK2_CNTL 0x005b
+#define mmAOMCLK2_CNTL_BASE_IDX 1
+#define mmDCCG_AUDIO_DTO2_PHASE 0x005c
+#define mmDCCG_AUDIO_DTO2_PHASE_BASE_IDX 1
+#define mmDCCG_AUDIO_DTO2_MODULO 0x005d
+#define mmDCCG_AUDIO_DTO2_MODULO_BASE_IDX 1
+#define mmDCE_VERSION 0x005e
+#define mmDCE_VERSION_BASE_IDX 1
+#define mmPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f
+#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+#define mmDCCG_GTC_CNTL 0x0060
+#define mmDCCG_GTC_CNTL_BASE_IDX 1
+#define mmDCCG_GTC_DTO_INCR 0x0061
+#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1
+#define mmDCCG_GTC_DTO_MODULO 0x0062
+#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1
+#define mmDCCG_GTC_CURRENT 0x0063
+#define mmDCCG_GTC_CURRENT_BASE_IDX 1
+#define mmDENTIST_DISPCLK_CNTL 0x0064
+#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1
+#define mmMIPI_DTO_CNTL 0x0065
+#define mmMIPI_DTO_CNTL_BASE_IDX 1
+#define mmMIPI_DTO_PHASE 0x0066
+#define mmMIPI_DTO_PHASE_BASE_IDX 1
+#define mmMIPI_DTO_MODULO 0x0067
+#define mmMIPI_DTO_MODULO_BASE_IDX 1
+#define mmDAC_CLK_ENABLE 0x0068
+#define mmDAC_CLK_ENABLE_BASE_IDX 1
+#define mmDVO_CLK_ENABLE 0x0069
+#define mmDVO_CLK_ENABLE_BASE_IDX 1
+#define mmAVSYNC_COUNTER_WRITE 0x006a
+#define mmAVSYNC_COUNTER_WRITE_BASE_IDX 1
+#define mmAVSYNC_COUNTER_CONTROL 0x006b
+#define mmAVSYNC_COUNTER_CONTROL_BASE_IDX 1
+#define mmDMCU_SMU_INTERRUPT_CNTL 0x006c
+#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 1
+#define mmSMU_CONTROL 0x006d
+#define mmSMU_CONTROL_BASE_IDX 1
+#define mmSMU_INTERRUPT_CONTROL 0x006e
+#define mmSMU_INTERRUPT_CONTROL_BASE_IDX 1
+#define mmAVSYNC_COUNTER_READ 0x006f
+#define mmAVSYNC_COUNTER_READ_BASE_IDX 1
+#define mmMILLISECOND_TIME_BASE_DIV 0x0070
+#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1
+#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071
+#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1
+#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072
+#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1
+#define mmDCCG_PERFMON_CNTL 0x0073
+#define mmDCCG_PERFMON_CNTL_BASE_IDX 1
+#define mmDCCG_GATE_DISABLE_CNTL 0x0074
+#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1
+#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075
+#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
+#define mmSCLK_CGTT_BLK_CTRL_REG 0x0076
+#define mmSCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
+#define mmDCCG_CAC_STATUS 0x0077
+#define mmDCCG_CAC_STATUS_BASE_IDX 1
+#define mmPIXCLK1_RESYNC_CNTL 0x0078
+#define mmPIXCLK1_RESYNC_CNTL_BASE_IDX 1
+#define mmPIXCLK2_RESYNC_CNTL 0x0079
+#define mmPIXCLK2_RESYNC_CNTL_BASE_IDX 1
+#define mmPIXCLK0_RESYNC_CNTL 0x007a
+#define mmPIXCLK0_RESYNC_CNTL_BASE_IDX 1
+#define mmMICROSECOND_TIME_BASE_DIV 0x007b
+#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1
+#define mmDCCG_GATE_DISABLE_CNTL2 0x007c
+#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1
+#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d
+#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
+#define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e
+#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+#define mmDCCG_DISP_CNTL_REG 0x007f
+#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1
+#define mmCRTC0_PIXEL_RATE_CNTL 0x0080
+#define mmCRTC0_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmDP_DTO0_PHASE 0x0081
+#define mmDP_DTO0_PHASE_BASE_IDX 1
+#define mmDP_DTO0_MODULO 0x0082
+#define mmDP_DTO0_MODULO_BASE_IDX 1
+#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL 0x0083
+#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmCRTC1_PIXEL_RATE_CNTL 0x0084
+#define mmCRTC1_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmDP_DTO1_PHASE 0x0085
+#define mmDP_DTO1_PHASE_BASE_IDX 1
+#define mmDP_DTO1_MODULO 0x0086
+#define mmDP_DTO1_MODULO_BASE_IDX 1
+#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL 0x0087
+#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmCRTC2_PIXEL_RATE_CNTL 0x0088
+#define mmCRTC2_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmDP_DTO2_PHASE 0x0089
+#define mmDP_DTO2_PHASE_BASE_IDX 1
+#define mmDP_DTO2_MODULO 0x008a
+#define mmDP_DTO2_MODULO_BASE_IDX 1
+#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL 0x008b
+#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmCRTC3_PIXEL_RATE_CNTL 0x008c
+#define mmCRTC3_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmDP_DTO3_PHASE 0x008d
+#define mmDP_DTO3_PHASE_BASE_IDX 1
+#define mmDP_DTO3_MODULO 0x008e
+#define mmDP_DTO3_MODULO_BASE_IDX 1
+#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL 0x008f
+#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmCRTC4_PIXEL_RATE_CNTL 0x0090
+#define mmCRTC4_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmDP_DTO4_PHASE 0x0091
+#define mmDP_DTO4_PHASE_BASE_IDX 1
+#define mmDP_DTO4_MODULO 0x0092
+#define mmDP_DTO4_MODULO_BASE_IDX 1
+#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL 0x0093
+#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmCRTC5_PIXEL_RATE_CNTL 0x0094
+#define mmCRTC5_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmDP_DTO5_PHASE 0x0095
+#define mmDP_DTO5_PHASE_BASE_IDX 1
+#define mmDP_DTO5_MODULO 0x0096
+#define mmDP_DTO5_MODULO_BASE_IDX 1
+#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL 0x0097
+#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmDCCG_SOFT_RESET 0x009f
+#define mmDCCG_SOFT_RESET_BASE_IDX 1
+#define mmSYMCLKA_CLOCK_ENABLE 0x00a0
+#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1
+#define mmSYMCLKB_CLOCK_ENABLE 0x00a1
+#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1
+#define mmSYMCLKC_CLOCK_ENABLE 0x00a2
+#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1
+#define mmSYMCLKD_CLOCK_ENABLE 0x00a3
+#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1
+#define mmSYMCLKE_CLOCK_ENABLE 0x00a4
+#define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1
+#define mmSYMCLKF_CLOCK_ENABLE 0x00a5
+#define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX 1
+#define mmDVOACLKD_CNTL 0x00a8
+#define mmDVOACLKD_CNTL_BASE_IDX 1
+#define mmDVOACLKC_MVP_CNTL 0x00a9
+#define mmDVOACLKC_MVP_CNTL_BASE_IDX 1
+#define mmDVOACLKC_CNTL 0x00aa
+#define mmDVOACLKC_CNTL_BASE_IDX 1
+#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab
+#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1
+#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac
+#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1
+#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad
+#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1
+#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae
+#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1
+#define mmDCCG_AUDIO_DTO1_MODULE 0x00af
+#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1
+#define mmDCCG_TEST_CLK_SEL 0x00be
+#define mmDCCG_TEST_CLK_SEL_BASE_IDX 1
+#define mmFBC_CNTL 0x0062
+#define mmFBC_CNTL_BASE_IDX 2
+#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x0064
+#define mmFBC_IDLE_FORCE_CLEAR_MASK_BASE_IDX 2
+#define mmFBC_START_STOP_DELAY 0x0065
+#define mmFBC_START_STOP_DELAY_BASE_IDX 2
+#define mmFBC_COMP_CNTL 0x0066
+#define mmFBC_COMP_CNTL_BASE_IDX 2
+#define mmFBC_COMP_MODE 0x0067
+#define mmFBC_COMP_MODE_BASE_IDX 2
+#define mmFBC_IND_LUT0 0x006b
+#define mmFBC_IND_LUT0_BASE_IDX 2
+#define mmFBC_IND_LUT1 0x006c
+#define mmFBC_IND_LUT1_BASE_IDX 2
+#define mmFBC_IND_LUT2 0x006d
+#define mmFBC_IND_LUT2_BASE_IDX 2
+#define mmFBC_IND_LUT3 0x006e
+#define mmFBC_IND_LUT3_BASE_IDX 2
+#define mmFBC_IND_LUT4 0x006f
+#define mmFBC_IND_LUT4_BASE_IDX 2
+#define mmFBC_IND_LUT5 0x0070
+#define mmFBC_IND_LUT5_BASE_IDX 2
+#define mmFBC_IND_LUT6 0x0071
+#define mmFBC_IND_LUT6_BASE_IDX 2
+#define mmFBC_IND_LUT7 0x0072
+#define mmFBC_IND_LUT7_BASE_IDX 2
+#define mmFBC_IND_LUT8 0x0073
+#define mmFBC_IND_LUT8_BASE_IDX 2
+#define mmFBC_IND_LUT9 0x0074
+#define mmFBC_IND_LUT9_BASE_IDX 2
+#define mmFBC_IND_LUT10 0x0075
+#define mmFBC_IND_LUT10_BASE_IDX 2
+#define mmFBC_IND_LUT11 0x0076
+#define mmFBC_IND_LUT11_BASE_IDX 2
+#define mmFBC_IND_LUT12 0x0077
+#define mmFBC_IND_LUT12_BASE_IDX 2
+#define mmFBC_IND_LUT13 0x0078
+#define mmFBC_IND_LUT13_BASE_IDX 2
+#define mmFBC_IND_LUT14 0x0079
+#define mmFBC_IND_LUT14_BASE_IDX 2
+#define mmFBC_IND_LUT15 0x007a
+#define mmFBC_IND_LUT15_BASE_IDX 2
+#define mmFBC_CSM_REGION_OFFSET_01 0x007b
+#define mmFBC_CSM_REGION_OFFSET_01_BASE_IDX 2
+#define mmFBC_CSM_REGION_OFFSET_23 0x007c
+#define mmFBC_CSM_REGION_OFFSET_23_BASE_IDX 2
+#define mmFBC_CLIENT_REGION_MASK 0x007d
+#define mmFBC_CLIENT_REGION_MASK_BASE_IDX 2
+#define mmFBC_DEBUG_COMP 0x007e
+#define mmFBC_DEBUG_COMP_BASE_IDX 2
+#define mmFBC_MISC 0x0084
+#define mmFBC_MISC_BASE_IDX 2
+#define mmFBC_STATUS 0x0085
+#define mmFBC_STATUS_BASE_IDX 2
+#define mmFBC_ALPHA_CNTL 0x0088
+#define mmFBC_ALPHA_CNTL_BASE_IDX 2
+#define mmFBC_ALPHA_RGB_OVERRIDE 0x0089
+#define mmFBC_ALPHA_RGB_OVERRIDE_BASE_IDX 2
+#define mmPIPE0_PG_CONFIG 0x008e
+#define mmPIPE0_PG_CONFIG_BASE_IDX 2
+#define mmPIPE0_PG_ENABLE 0x008f
+#define mmPIPE0_PG_ENABLE_BASE_IDX 2
+#define mmPIPE0_PG_STATUS 0x0090
+#define mmPIPE0_PG_STATUS_BASE_IDX 2
+#define mmPIPE1_PG_CONFIG 0x0091
+#define mmPIPE1_PG_CONFIG_BASE_IDX 2
+#define mmPIPE1_PG_ENABLE 0x0092
+#define mmPIPE1_PG_ENABLE_BASE_IDX 2
+#define mmPIPE1_PG_STATUS 0x0093
+#define mmPIPE1_PG_STATUS_BASE_IDX 2
+#define mmPIPE2_PG_CONFIG 0x0094
+#define mmPIPE2_PG_CONFIG_BASE_IDX 2
+#define mmPIPE2_PG_ENABLE 0x0095
+#define mmPIPE2_PG_ENABLE_BASE_IDX 2
+#define mmPIPE2_PG_STATUS 0x0096
+#define mmPIPE2_PG_STATUS_BASE_IDX 2
+#define mmPIPE3_PG_CONFIG 0x0097
+#define mmPIPE3_PG_CONFIG_BASE_IDX 2
+#define mmPIPE3_PG_ENABLE 0x0098
+#define mmPIPE3_PG_ENABLE_BASE_IDX 2
+#define mmPIPE3_PG_STATUS 0x0099
+#define mmPIPE3_PG_STATUS_BASE_IDX 2
+#define mmPIPE4_PG_CONFIG 0x009a
+#define mmPIPE4_PG_CONFIG_BASE_IDX 2
+#define mmPIPE4_PG_ENABLE 0x009b
+#define mmPIPE4_PG_ENABLE_BASE_IDX 2
+#define mmPIPE4_PG_STATUS 0x009c
+#define mmPIPE4_PG_STATUS_BASE_IDX 2
+#define mmPIPE5_PG_CONFIG 0x009d
+#define mmPIPE5_PG_CONFIG_BASE_IDX 2
+#define mmPIPE5_PG_ENABLE 0x009e
+#define mmPIPE5_PG_ENABLE_BASE_IDX 2
+#define mmPIPE5_PG_STATUS 0x009f
+#define mmPIPE5_PG_STATUS_BASE_IDX 2
+#define mmDSI_PG_CONFIG 0x00a0
+#define mmDSI_PG_CONFIG_BASE_IDX 2
+#define mmDSI_PG_ENABLE 0x00a1
+#define mmDSI_PG_ENABLE_BASE_IDX 2
+#define mmDSI_PG_STATUS 0x00a2
+#define mmDSI_PG_STATUS_BASE_IDX 2
+#define mmDCFEV0_PG_CONFIG 0x00a3
+#define mmDCFEV0_PG_CONFIG_BASE_IDX 2
+#define mmDCFEV0_PG_ENABLE 0x00a4
+#define mmDCFEV0_PG_ENABLE_BASE_IDX 2
+#define mmDCFEV0_PG_STATUS 0x00a5
+#define mmDCFEV0_PG_STATUS_BASE_IDX 2
+#define mmDCPG_INTERRUPT_STATUS 0x00a6
+#define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDCPG_INTERRUPT_CONTROL 0x00a7
+#define mmDCPG_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDCPG_INTERRUPT_CONTROL2 0x00a8
+#define mmDCPG_INTERRUPT_CONTROL2_BASE_IDX 2
+#define mmDCFEV1_PG_CONFIG 0x00a9
+#define mmDCFEV1_PG_CONFIG_BASE_IDX 2
+#define mmDCFEV1_PG_ENABLE 0x00aa
+#define mmDCFEV1_PG_ENABLE_BASE_IDX 2
+#define mmDCFEV1_PG_STATUS 0x00ab
+#define mmDCFEV1_PG_STATUS_BASE_IDX 2
+#define mmDC_IP_REQUEST_CNTL 0x00ac
+#define mmDC_IP_REQUEST_CNTL_BASE_IDX 2
+#define mmDC_PGCNTL_STATUS_REG 0x00ad
+#define mmDC_PGCNTL_STATUS_REG_BASE_IDX 2
+#define mmDMIFV_STATUS 0x00c3
+#define mmDMIFV_STATUS_BASE_IDX 2
+#define mmDMIF_CONTROL 0x00c4
+#define mmDMIF_CONTROL_BASE_IDX 2
+#define mmDMIF_STATUS 0x00c5
+#define mmDMIF_STATUS_BASE_IDX 2
+#define mmDMIF_ARBITRATION_CONTROL 0x00c7
+#define mmDMIF_ARBITRATION_CONTROL_BASE_IDX 2
+#define mmPIPE0_ARBITRATION_CONTROL3 0x00c8
+#define mmPIPE0_ARBITRATION_CONTROL3_BASE_IDX 2
+#define mmPIPE1_ARBITRATION_CONTROL3 0x00c9
+#define mmPIPE1_ARBITRATION_CONTROL3_BASE_IDX 2
+#define mmPIPE2_ARBITRATION_CONTROL3 0x00ca
+#define mmPIPE2_ARBITRATION_CONTROL3_BASE_IDX 2
+#define mmPIPE3_ARBITRATION_CONTROL3 0x00cb
+#define mmPIPE3_ARBITRATION_CONTROL3_BASE_IDX 2
+#define mmPIPE4_ARBITRATION_CONTROL3 0x00cc
+#define mmPIPE4_ARBITRATION_CONTROL3_BASE_IDX 2
+#define mmPIPE5_ARBITRATION_CONTROL3 0x00cd
+#define mmPIPE5_ARBITRATION_CONTROL3_BASE_IDX 2
+#define mmDMIF_P_VMID 0x00ce
+#define mmDMIF_P_VMID_BASE_IDX 2
+#define mmDMIF_ADDR_CALC 0x00d1
+#define mmDMIF_ADDR_CALC_BASE_IDX 2
+#define mmDMIF_STATUS2 0x00d2
+#define mmDMIF_STATUS2_BASE_IDX 2
+#define mmPIPE0_MAX_REQUESTS 0x00d3
+#define mmPIPE0_MAX_REQUESTS_BASE_IDX 2
+#define mmPIPE1_MAX_REQUESTS 0x00d4
+#define mmPIPE1_MAX_REQUESTS_BASE_IDX 2
+#define mmPIPE2_MAX_REQUESTS 0x00d5
+#define mmPIPE2_MAX_REQUESTS_BASE_IDX 2
+#define mmPIPE3_MAX_REQUESTS 0x00d6
+#define mmPIPE3_MAX_REQUESTS_BASE_IDX 2
+#define mmPIPE4_MAX_REQUESTS 0x00d7
+#define mmPIPE4_MAX_REQUESTS_BASE_IDX 2
+#define mmPIPE5_MAX_REQUESTS 0x00d8
+#define mmPIPE5_MAX_REQUESTS_BASE_IDX 2
+#define mmLOW_POWER_TILING_CONTROL 0x00d9
+#define mmLOW_POWER_TILING_CONTROL_BASE_IDX 2
+#define mmMCIF_CONTROL 0x00da
+#define mmMCIF_CONTROL_BASE_IDX 2
+#define mmMCIF_WRITE_COMBINE_CONTROL 0x00db
+#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2
+#define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x00de
+#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
+#define mmCC_DC_PIPE_DIS 0x00e0
+#define mmCC_DC_PIPE_DIS_BASE_IDX 2
+#define mmSMU_WM_CONTROL 0x00e1
+#define mmSMU_WM_CONTROL_BASE_IDX 2
+#define mmRBBMIF_TIMEOUT 0x00e2
+#define mmRBBMIF_TIMEOUT_BASE_IDX 2
+#define mmRBBMIF_STATUS 0x00e3
+#define mmRBBMIF_STATUS_BASE_IDX 2
+#define mmRBBMIF_TIMEOUT_DIS 0x00e4
+#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2
+#define mmDCI_MEM_PWR_STATUS 0x00e5
+#define mmDCI_MEM_PWR_STATUS_BASE_IDX 2
+#define mmDCI_MEM_PWR_STATUS2 0x00e6
+#define mmDCI_MEM_PWR_STATUS2_BASE_IDX 2
+#define mmDCI_CLK_CNTL 0x00e7
+#define mmDCI_CLK_CNTL_BASE_IDX 2
+#define mmDCI_CLK_CNTL2 0x00e8
+#define mmDCI_CLK_CNTL2_BASE_IDX 2
+#define mmDCI_MEM_PWR_CNTL 0x00e9
+#define mmDCI_MEM_PWR_CNTL_BASE_IDX 2
+#define mmDCI_MEM_PWR_CNTL2 0x00ea
+#define mmDCI_MEM_PWR_CNTL2_BASE_IDX 2
+#define mmDCI_MEM_PWR_CNTL3 0x00eb
+#define mmDCI_MEM_PWR_CNTL3_BASE_IDX 2
+#define mmPIPE0_DMIF_BUFFER_CONTROL 0x00ef
+#define mmPIPE0_DMIF_BUFFER_CONTROL_BASE_IDX 2
+#define mmPIPE1_DMIF_BUFFER_CONTROL 0x00f0
+#define mmPIPE1_DMIF_BUFFER_CONTROL_BASE_IDX 2
+#define mmPIPE2_DMIF_BUFFER_CONTROL 0x00f1
+#define mmPIPE2_DMIF_BUFFER_CONTROL_BASE_IDX 2
+#define mmPIPE3_DMIF_BUFFER_CONTROL 0x00f2
+#define mmPIPE3_DMIF_BUFFER_CONTROL_BASE_IDX 2
+#define mmPIPE4_DMIF_BUFFER_CONTROL 0x00f3
+#define mmPIPE4_DMIF_BUFFER_CONTROL_BASE_IDX 2
+#define mmPIPE5_DMIF_BUFFER_CONTROL 0x00f4
+#define mmPIPE5_DMIF_BUFFER_CONTROL_BASE_IDX 2
+#define mmRBBMIF_STATUS_FLAG 0x00f5
+#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2
+#define mmDCI_SOFT_RESET 0x00f6
+#define mmDCI_SOFT_RESET_BASE_IDX 2
+#define mmDMIF_URG_OVERRIDE 0x00f7
+#define mmDMIF_URG_OVERRIDE_BASE_IDX 2
+#define mmPIPE6_ARBITRATION_CONTROL3 0x00f8
+#define mmPIPE6_ARBITRATION_CONTROL3_BASE_IDX 2
+#define mmPIPE7_ARBITRATION_CONTROL3 0x00f9
+#define mmPIPE7_ARBITRATION_CONTROL3_BASE_IDX 2
+#define mmPIPE6_MAX_REQUESTS 0x00fa
+#define mmPIPE6_MAX_REQUESTS_BASE_IDX 2
+#define mmPIPE7_MAX_REQUESTS 0x00fb
+#define mmPIPE7_MAX_REQUESTS_BASE_IDX 2
+#define mmDVMM_REG_RD_STATUS 0x00fc
+#define mmDVMM_REG_RD_STATUS_BASE_IDX 2
+#define mmDVMM_REG_RD_DATA 0x00fd
+#define mmDVMM_REG_RD_DATA_BASE_IDX 2
+#define mmDVMM_PTE_REQ 0x00fe
+#define mmDVMM_PTE_REQ_BASE_IDX 2
+#define mmDVMM_CNTL 0x00ff
+#define mmDVMM_CNTL_BASE_IDX 2
+#define mmDVMM_FAULT_STATUS 0x0100
+#define mmDVMM_FAULT_STATUS_BASE_IDX 2
+#define mmDVMM_FAULT_ADDR 0x0101
+#define mmDVMM_FAULT_ADDR_BASE_IDX 2
+#define mmFMON_CTRL 0x0102
+#define mmFMON_CTRL_BASE_IDX 2
+#define mmDVMM_PTE_PGMEM_CONTROL 0x0103
+#define mmDVMM_PTE_PGMEM_CONTROL_BASE_IDX 2
+#define mmDVMM_PTE_PGMEM_STATE 0x0104
+#define mmDVMM_PTE_PGMEM_STATE_BASE_IDX 2
+#define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x0105
+#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
+#define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0106
+#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2
+#define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER 0x0107
+#define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
+#define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER 0x0108
+#define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
+#define mmDCI_MEM_PWR_CNTL4 0x0109
+#define mmDCI_MEM_PWR_CNTL4_BASE_IDX 2
+#define mmMCIF_WB_MISC_CTRL 0x010a
+#define mmMCIF_WB_MISC_CTRL_BASE_IDX 2
+#define mmDCI_MEM_PWR_STATUS3 0x010b
+#define mmDCI_MEM_PWR_STATUS3_BASE_IDX 2
+#define mmDMIF_CURSOR_CONTROL 0x010c
+#define mmDMIF_CURSOR_CONTROL_BASE_IDX 2
+#define mmDMIF_CURSOR_MEM_CONTROL 0x010d
+#define mmDMIF_CURSOR_MEM_CONTROL_BASE_IDX 2
+#define mmDCHUB_FB_LOCATION 0x0126
+#define mmDCHUB_FB_LOCATION_BASE_IDX 2
+#define mmDCHUB_FB_OFFSET 0x0127
+#define mmDCHUB_FB_OFFSET_BASE_IDX 2
+#define mmDCHUB_AGP_BASE 0x0128
+#define mmDCHUB_AGP_BASE_BASE_IDX 2
+#define mmDCHUB_AGP_BOT 0x0129
+#define mmDCHUB_AGP_BOT_BASE_IDX 2
+#define mmDCHUB_AGP_TOP 0x012a
+#define mmDCHUB_AGP_TOP_BASE_IDX 2
+#define mmDCHUB_DRAM_APER_BASE 0x012b
+#define mmDCHUB_DRAM_APER_BASE_BASE_IDX 2
+#define mmDCHUB_DRAM_APER_DEF 0x012c
+#define mmDCHUB_DRAM_APER_DEF_BASE_IDX 2
+#define mmDCHUB_DRAM_APER_TOP 0x012d
+#define mmDCHUB_DRAM_APER_TOP_BASE_IDX 2
+#define mmDCHUB_CONTROL_STATUS 0x012e
+#define mmDCHUB_CONTROL_STATUS_BASE_IDX 2
+#define mmWB_ENABLE 0x0212
+#define mmWB_ENABLE_BASE_IDX 2
+#define mmWB_EC_CONFIG 0x0213
+#define mmWB_EC_CONFIG_BASE_IDX 2
+#define mmCNV_MODE 0x0214
+#define mmCNV_MODE_BASE_IDX 2
+#define mmCNV_WINDOW_START 0x0215
+#define mmCNV_WINDOW_START_BASE_IDX 2
+#define mmCNV_WINDOW_SIZE 0x0216
+#define mmCNV_WINDOW_SIZE_BASE_IDX 2
+#define mmCNV_UPDATE 0x0217
+#define mmCNV_UPDATE_BASE_IDX 2
+#define mmCNV_SOURCE_SIZE 0x0218
+#define mmCNV_SOURCE_SIZE_BASE_IDX 2
+#define mmCNV_CSC_CONTROL 0x0219
+#define mmCNV_CSC_CONTROL_BASE_IDX 2
+#define mmCNV_CSC_C11_C12 0x021a
+#define mmCNV_CSC_C11_C12_BASE_IDX 2
+#define mmCNV_CSC_C13_C14 0x021b
+#define mmCNV_CSC_C13_C14_BASE_IDX 2
+#define mmCNV_CSC_C21_C22 0x021c
+#define mmCNV_CSC_C21_C22_BASE_IDX 2
+#define mmCNV_CSC_C23_C24 0x021d
+#define mmCNV_CSC_C23_C24_BASE_IDX 2
+#define mmCNV_CSC_C31_C32 0x021e
+#define mmCNV_CSC_C31_C32_BASE_IDX 2
+#define mmCNV_CSC_C33_C34 0x021f
+#define mmCNV_CSC_C33_C34_BASE_IDX 2
+#define mmCNV_CSC_ROUND_OFFSET_R 0x0220
+#define mmCNV_CSC_ROUND_OFFSET_R_BASE_IDX 2
+#define mmCNV_CSC_ROUND_OFFSET_G 0x0221
+#define mmCNV_CSC_ROUND_OFFSET_G_BASE_IDX 2
+#define mmCNV_CSC_ROUND_OFFSET_B 0x0222
+#define mmCNV_CSC_ROUND_OFFSET_B_BASE_IDX 2
+#define mmCNV_CSC_CLAMP_R 0x0223
+#define mmCNV_CSC_CLAMP_R_BASE_IDX 2
+#define mmCNV_CSC_CLAMP_G 0x0224
+#define mmCNV_CSC_CLAMP_G_BASE_IDX 2
+#define mmCNV_CSC_CLAMP_B 0x0225
+#define mmCNV_CSC_CLAMP_B_BASE_IDX 2
+#define mmCNV_TEST_CNTL 0x0226
+#define mmCNV_TEST_CNTL_BASE_IDX 2
+#define mmCNV_TEST_CRC_RED 0x0227
+#define mmCNV_TEST_CRC_RED_BASE_IDX 2
+#define mmCNV_TEST_CRC_GREEN 0x0228
+#define mmCNV_TEST_CRC_GREEN_BASE_IDX 2
+#define mmCNV_TEST_CRC_BLUE 0x0229
+#define mmCNV_TEST_CRC_BLUE_BASE_IDX 2
+#define mmCNV_INPUT_SELECT 0x022d
+#define mmCNV_INPUT_SELECT_BASE_IDX 2
+#define mmWB_SOFT_RESET 0x0230
+#define mmWB_SOFT_RESET_BASE_IDX 2
+#define mmWB_WARM_UP_MODE_CTL1 0x0231
+#define mmWB_WARM_UP_MODE_CTL1_BASE_IDX 2
+#define mmWB_WARM_UP_MODE_CTL2 0x0232
+#define mmWB_WARM_UP_MODE_CTL2_BASE_IDX 2
+#define mmWBSCL_COEF_RAM_SELECT 0x0242
+#define mmWBSCL_COEF_RAM_SELECT_BASE_IDX 2
+#define mmWBSCL_COEF_RAM_TAP_DATA 0x0243
+#define mmWBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2
+#define mmWBSCL_MODE 0x0244
+#define mmWBSCL_MODE_BASE_IDX 2
+#define mmWBSCL_TAP_CONTROL 0x0245
+#define mmWBSCL_TAP_CONTROL_BASE_IDX 2
+#define mmWBSCL_DEST_SIZE 0x0246
+#define mmWBSCL_DEST_SIZE_BASE_IDX 2
+#define mmWBSCL_HORZ_FILTER_SCALE_RATIO 0x0247
+#define mmWBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB 0x0248
+#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2
+#define mmWBSCL_HORZ_FILTER_INIT_CBCR 0x0249
+#define mmWBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2
+#define mmWBSCL_VERT_FILTER_SCALE_RATIO 0x024a
+#define mmWBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmWBSCL_VERT_FILTER_INIT_Y_RGB 0x024b
+#define mmWBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2
+#define mmWBSCL_VERT_FILTER_INIT_CBCR 0x024c
+#define mmWBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2
+#define mmWBSCL_ROUND_OFFSET 0x024d
+#define mmWBSCL_ROUND_OFFSET_BASE_IDX 2
+#define mmWBSCL_CLAMP 0x024e
+#define mmWBSCL_CLAMP_BASE_IDX 2
+#define mmWBSCL_OVERFLOW_STATUS 0x024f
+#define mmWBSCL_OVERFLOW_STATUS_BASE_IDX 2
+#define mmWBSCL_COEF_RAM_CONFLICT_STATUS 0x0250
+#define mmWBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
+#define mmWBSCL_OUTSIDE_PIX_STRATEGY 0x0251
+#define mmWBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2
+#define mmWBSCL_TEST_CNTL 0x0252
+#define mmWBSCL_TEST_CNTL_BASE_IDX 2
+#define mmWBSCL_TEST_CRC_RED 0x0253
+#define mmWBSCL_TEST_CRC_RED_BASE_IDX 2
+#define mmWBSCL_TEST_CRC_GREEN 0x0254
+#define mmWBSCL_TEST_CRC_GREEN_BASE_IDX 2
+#define mmWBSCL_TEST_CRC_BLUE 0x0255
+#define mmWBSCL_TEST_CRC_BLUE_BASE_IDX 2
+#define mmWBSCL_BACKPRESSURE_CNT_EN 0x0256
+#define mmWBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2
+#define mmWB_MCIF_BACKPRESSURE_CNT 0x0257
+#define mmWB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2
+#define mmWBSCL_RAM_SHUTDOWN 0x025a
+#define mmWBSCL_RAM_SHUTDOWN_BASE_IDX 2
+#define mmDMCU_CTRL 0x03b6
+#define mmDMCU_CTRL_BASE_IDX 2
+#define mmDMCU_STATUS 0x03b7
+#define mmDMCU_STATUS_BASE_IDX 2
+#define mmDMCU_PC_START_ADDR 0x03b8
+#define mmDMCU_PC_START_ADDR_BASE_IDX 2
+#define mmDMCU_FW_START_ADDR 0x03b9
+#define mmDMCU_FW_START_ADDR_BASE_IDX 2
+#define mmDMCU_FW_END_ADDR 0x03ba
+#define mmDMCU_FW_END_ADDR_BASE_IDX 2
+#define mmDMCU_FW_ISR_START_ADDR 0x03bb
+#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2
+#define mmDMCU_FW_CS_HI 0x03bc
+#define mmDMCU_FW_CS_HI_BASE_IDX 2
+#define mmDMCU_FW_CS_LO 0x03bd
+#define mmDMCU_FW_CS_LO_BASE_IDX 2
+#define mmDMCU_RAM_ACCESS_CTRL 0x03be
+#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2
+#define mmDMCU_ERAM_WR_CTRL 0x03bf
+#define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2
+#define mmDMCU_ERAM_WR_DATA 0x03c0
+#define mmDMCU_ERAM_WR_DATA_BASE_IDX 2
+#define mmDMCU_ERAM_RD_CTRL 0x03c1
+#define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2
+#define mmDMCU_ERAM_RD_DATA 0x03c2
+#define mmDMCU_ERAM_RD_DATA_BASE_IDX 2
+#define mmDMCU_IRAM_WR_CTRL 0x03c3
+#define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2
+#define mmDMCU_IRAM_WR_DATA 0x03c4
+#define mmDMCU_IRAM_WR_DATA_BASE_IDX 2
+#define mmDMCU_IRAM_RD_CTRL 0x03c5
+#define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2
+#define mmDMCU_IRAM_RD_DATA 0x03c6
+#define mmDMCU_IRAM_RD_DATA_BASE_IDX 2
+#define mmDMCU_EVENT_TRIGGER 0x03c7
+#define mmDMCU_EVENT_TRIGGER_BASE_IDX 2
+#define mmDMCU_UC_INTERNAL_INT_STATUS 0x03c8
+#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2
+#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x03c9
+#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2
+#define mmDMCU_INTERRUPT_STATUS 0x03ca
+#define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x03cb
+#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x03cc
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x03cd
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2
+#define mmDC_DMCU_SCRATCH 0x03ce
+#define mmDC_DMCU_SCRATCH_BASE_IDX 2
+#define mmDMCU_INT_CNT 0x03cf
+#define mmDMCU_INT_CNT_BASE_IDX 2
+#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x03d0
+#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2
+#define mmDMCU_UC_CLK_GATING_CNTL 0x03d1
+#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2
+#define mmMASTER_COMM_DATA_REG1 0x03d2
+#define mmMASTER_COMM_DATA_REG1_BASE_IDX 2
+#define mmMASTER_COMM_DATA_REG2 0x03d3
+#define mmMASTER_COMM_DATA_REG2_BASE_IDX 2
+#define mmMASTER_COMM_DATA_REG3 0x03d4
+#define mmMASTER_COMM_DATA_REG3_BASE_IDX 2
+#define mmMASTER_COMM_CMD_REG 0x03d5
+#define mmMASTER_COMM_CMD_REG_BASE_IDX 2
+#define mmMASTER_COMM_CNTL_REG 0x03d6
+#define mmMASTER_COMM_CNTL_REG_BASE_IDX 2
+#define mmSLAVE_COMM_DATA_REG1 0x03d7
+#define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2
+#define mmSLAVE_COMM_DATA_REG2 0x03d8
+#define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2
+#define mmSLAVE_COMM_DATA_REG3 0x03d9
+#define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2
+#define mmSLAVE_COMM_CMD_REG 0x03da
+#define mmSLAVE_COMM_CMD_REG_BASE_IDX 2
+#define mmSLAVE_COMM_CNTL_REG 0x03db
+#define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2
+#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x03de
+#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2
+#define mmBL1_PWM_USER_LEVEL 0x03df
+#define mmBL1_PWM_USER_LEVEL_BASE_IDX 2
+#define mmBL1_PWM_TARGET_ABM_LEVEL 0x03e0
+#define mmBL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2
+#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x03e1
+#define mmBL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2
+#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x03e2
+#define mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2
+#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x03e3
+#define mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2
+#define mmBL1_PWM_ABM_CNTL 0x03e4
+#define mmBL1_PWM_ABM_CNTL_BASE_IDX 2
+#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x03e5
+#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2
+#define mmBL1_PWM_GRP2_REG_LOCK 0x03e6
+#define mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX 2
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x03e7
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x03e8
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2
+#define mmDMCU_INTERRUPT_STATUS_1 0x03e9
+#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2
+#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x03ea
+#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x03eb
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x03ec
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
+#define mmDC_ABM1_CNTL 0x03ee
+#define mmDC_ABM1_CNTL_BASE_IDX 2
+#define mmDC_ABM1_IPCSC_COEFF_SEL 0x03ef
+#define mmDC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x03f0
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x03f1
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x03f2
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x03f3
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x03f4
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2
+#define mmDC_ABM1_ACE_THRES_12 0x03f5
+#define mmDC_ABM1_ACE_THRES_12_BASE_IDX 2
+#define mmDC_ABM1_ACE_THRES_34 0x03f6
+#define mmDC_ABM1_ACE_THRES_34_BASE_IDX 2
+#define mmDC_ABM1_ACE_CNTL_MISC 0x03f7
+#define mmDC_ABM1_ACE_CNTL_MISC_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x03f8
+#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x03f9
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x03fa
+#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x03fb
+#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x03fc
+#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x03fd
+#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2
+#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x0400
+#define mmDC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2
+#define mmDC_ABM1_HG_MISC_CTRL 0x0401
+#define mmDC_ABM1_HG_MISC_CTRL_BASE_IDX 2
+#define mmDC_ABM1_LS_SUM_OF_LUMA 0x0402
+#define mmDC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2
+#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x0403
+#define mmDC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2
+#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0404
+#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2
+#define mmDC_ABM1_LS_PIXEL_COUNT 0x0405
+#define mmDC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2
+#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x0406
+#define mmDC_ABM1_LS_OVR_SCAN_BIN_BASE_IDX 2
+#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0407
+#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2
+#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0408
+#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2
+#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0409
+#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2
+#define mmDC_ABM1_HG_SAMPLE_RATE 0x040a
+#define mmDC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2
+#define mmDC_ABM1_LS_SAMPLE_RATE 0x040b
+#define mmDC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2
+#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x040c
+#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2
+#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x040d
+#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2
+#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x040e
+#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2
+#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x040f
+#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2
+#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0410
+#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_1 0x0411
+#define mmDC_ABM1_HG_RESULT_1_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_2 0x0412
+#define mmDC_ABM1_HG_RESULT_2_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_3 0x0413
+#define mmDC_ABM1_HG_RESULT_3_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_4 0x0414
+#define mmDC_ABM1_HG_RESULT_4_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_5 0x0415
+#define mmDC_ABM1_HG_RESULT_5_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_6 0x0416
+#define mmDC_ABM1_HG_RESULT_6_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_7 0x0417
+#define mmDC_ABM1_HG_RESULT_7_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_8 0x0418
+#define mmDC_ABM1_HG_RESULT_8_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_9 0x0419
+#define mmDC_ABM1_HG_RESULT_9_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_10 0x041a
+#define mmDC_ABM1_HG_RESULT_10_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_11 0x041b
+#define mmDC_ABM1_HG_RESULT_11_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_12 0x041c
+#define mmDC_ABM1_HG_RESULT_12_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_13 0x041d
+#define mmDC_ABM1_HG_RESULT_13_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_14 0x041e
+#define mmDC_ABM1_HG_RESULT_14_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_15 0x041f
+#define mmDC_ABM1_HG_RESULT_15_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_16 0x0420
+#define mmDC_ABM1_HG_RESULT_16_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_17 0x0421
+#define mmDC_ABM1_HG_RESULT_17_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_18 0x0422
+#define mmDC_ABM1_HG_RESULT_18_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_19 0x0423
+#define mmDC_ABM1_HG_RESULT_19_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_20 0x0424
+#define mmDC_ABM1_HG_RESULT_20_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_21 0x0425
+#define mmDC_ABM1_HG_RESULT_21_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_22 0x0426
+#define mmDC_ABM1_HG_RESULT_22_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_23 0x0427
+#define mmDC_ABM1_HG_RESULT_23_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_24 0x0428
+#define mmDC_ABM1_HG_RESULT_24_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0429
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x042a
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x042b
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x042c
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x042d
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x042e
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x042f
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0430
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0431
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2
+#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x0451
+#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE_BASE_IDX 2
+#define mmDC_ABM1_BL_MASTER_LOCK 0x0452
+#define mmDC_ABM1_BL_MASTER_LOCK_BASE_IDX 2
+#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x04bc
+#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2
+#define mmAZALIA_AUDIO_DTO 0x04bd
+#define mmAZALIA_AUDIO_DTO_BASE_IDX 2
+#define mmAZALIA_AUDIO_DTO_CONTROL 0x04be
+#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2
+#define mmAZALIA_SOCCLK_CONTROL 0x04bf
+#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2
+#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x04c0
+#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2
+#define mmAZALIA_DATA_DMA_CONTROL 0x04c1
+#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2
+#define mmAZALIA_BDL_DMA_CONTROL 0x04c2
+#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2
+#define mmAZALIA_RIRB_AND_DP_CONTROL 0x04c3
+#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2
+#define mmAZALIA_CORB_DMA_CONTROL 0x04c4
+#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2
+#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x04cb
+#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2
+#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x04cc
+#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2
+#define mmAZALIA_GLOBAL_CAPABILITIES 0x04cd
+#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2
+#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x04ce
+#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
+#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x04cf
+#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2
+#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x04d0
+#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
+#define mmAZALIA_INPUT_CRC0_CONTROL0 0x04d3
+#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2
+#define mmAZALIA_INPUT_CRC0_CONTROL1 0x04d4
+#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2
+#define mmAZALIA_INPUT_CRC0_CONTROL2 0x04d5
+#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2
+#define mmAZALIA_INPUT_CRC0_CONTROL3 0x04d6
+#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2
+#define mmAZALIA_INPUT_CRC0_RESULT 0x04d7
+#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2
+#define mmAZALIA_INPUT_CRC1_CONTROL0 0x04d8
+#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2
+#define mmAZALIA_INPUT_CRC1_CONTROL1 0x04d9
+#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2
+#define mmAZALIA_INPUT_CRC1_CONTROL2 0x04da
+#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2
+#define mmAZALIA_INPUT_CRC1_CONTROL3 0x04db
+#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2
+#define mmAZALIA_INPUT_CRC1_RESULT 0x04dc
+#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2
+#define mmAZALIA_CRC0_CONTROL0 0x04dd
+#define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2
+#define mmAZALIA_CRC0_CONTROL1 0x04de
+#define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2
+#define mmAZALIA_CRC0_CONTROL2 0x04df
+#define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2
+#define mmAZALIA_CRC0_CONTROL3 0x04e0
+#define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2
+#define mmAZALIA_CRC0_RESULT 0x04e1
+#define mmAZALIA_CRC0_RESULT_BASE_IDX 2
+#define mmAZALIA_CRC1_CONTROL0 0x04e2
+#define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2
+#define mmAZALIA_CRC1_CONTROL1 0x04e3
+#define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2
+#define mmAZALIA_CRC1_CONTROL2 0x04e4
+#define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2
+#define mmAZALIA_CRC1_CONTROL3 0x04e5
+#define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2
+#define mmAZALIA_CRC1_RESULT 0x04e6
+#define mmAZALIA_CRC1_RESULT_BASE_IDX 2
+#define mmAZALIA_MEM_PWR_CTRL 0x04e8
+#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2
+#define mmAZALIA_MEM_PWR_STATUS 0x04e9
+#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0500
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0501
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0502
+#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0503
+#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x0504
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x0505
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x0506
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x0507
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x0508
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x0509
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x050a
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x050b
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2
+#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x050c
+#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
+#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x050d
+#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x050f
+#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0510
+#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0511
+#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0512
+#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0513
+#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x0514
+#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x0515
+#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2
+#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x0516
+#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
+#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0517
+#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
+#define mmDAC_ENABLE 0x155a
+#define mmDAC_ENABLE_BASE_IDX 2
+#define mmDAC_SOURCE_SELECT 0x155b
+#define mmDAC_SOURCE_SELECT_BASE_IDX 2
+#define mmDAC_CRC_EN 0x155c
+#define mmDAC_CRC_EN_BASE_IDX 2
+#define mmDAC_CRC_CONTROL 0x155d
+#define mmDAC_CRC_CONTROL_BASE_IDX 2
+#define mmDAC_CRC_SIG_RGB_MASK 0x155e
+#define mmDAC_CRC_SIG_RGB_MASK_BASE_IDX 2
+#define mmDAC_CRC_SIG_CONTROL_MASK 0x155f
+#define mmDAC_CRC_SIG_CONTROL_MASK_BASE_IDX 2
+#define mmDAC_CRC_SIG_RGB 0x1560
+#define mmDAC_CRC_SIG_RGB_BASE_IDX 2
+#define mmDAC_CRC_SIG_CONTROL 0x1561
+#define mmDAC_CRC_SIG_CONTROL_BASE_IDX 2
+#define mmDAC_SYNC_TRISTATE_CONTROL 0x1562
+#define mmDAC_SYNC_TRISTATE_CONTROL_BASE_IDX 2
+#define mmDAC_STEREOSYNC_SELECT 0x1563
+#define mmDAC_STEREOSYNC_SELECT_BASE_IDX 2
+#define mmDAC_AUTODETECT_CONTROL 0x1564
+#define mmDAC_AUTODETECT_CONTROL_BASE_IDX 2
+#define mmDAC_AUTODETECT_CONTROL2 0x1565
+#define mmDAC_AUTODETECT_CONTROL2_BASE_IDX 2
+#define mmDAC_AUTODETECT_CONTROL3 0x1566
+#define mmDAC_AUTODETECT_CONTROL3_BASE_IDX 2
+#define mmDAC_AUTODETECT_STATUS 0x1567
+#define mmDAC_AUTODETECT_STATUS_BASE_IDX 2
+#define mmDAC_AUTODETECT_INT_CONTROL 0x1568
+#define mmDAC_AUTODETECT_INT_CONTROL_BASE_IDX 2
+#define mmDAC_FORCE_OUTPUT_CNTL 0x1569
+#define mmDAC_FORCE_OUTPUT_CNTL_BASE_IDX 2
+#define mmDAC_FORCE_DATA 0x156a
+#define mmDAC_FORCE_DATA_BASE_IDX 2
+#define mmDAC_POWERDOWN 0x156b
+#define mmDAC_POWERDOWN_BASE_IDX 2
+#define mmDAC_CONTROL 0x156c
+#define mmDAC_CONTROL_BASE_IDX 2
+#define mmDAC_COMPARATOR_ENABLE 0x156d
+#define mmDAC_COMPARATOR_ENABLE_BASE_IDX 2
+#define mmDAC_COMPARATOR_OUTPUT 0x156e
+#define mmDAC_COMPARATOR_OUTPUT_BASE_IDX 2
+#define mmDAC_PWR_CNTL 0x156f
+#define mmDAC_PWR_CNTL_BASE_IDX 2
+#define mmDAC_DFT_CONFIG 0x1570
+#define mmDAC_DFT_CONFIG_BASE_IDX 2
+#define mmDAC_FIFO_STATUS 0x1571
+#define mmDAC_FIFO_STATUS_BASE_IDX 2
+#define mmDC_I2C_CONTROL 0x1584
+#define mmDC_I2C_CONTROL_BASE_IDX 2
+#define mmDC_I2C_ARBITRATION 0x1585
+#define mmDC_I2C_ARBITRATION_BASE_IDX 2
+#define mmDC_I2C_INTERRUPT_CONTROL 0x1586
+#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDC_I2C_SW_STATUS 0x1587
+#define mmDC_I2C_SW_STATUS_BASE_IDX 2
+#define mmDC_I2C_DDC1_HW_STATUS 0x1588
+#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2
+#define mmDC_I2C_DDC2_HW_STATUS 0x1589
+#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2
+#define mmDC_I2C_DDC3_HW_STATUS 0x158a
+#define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2
+#define mmDC_I2C_DDC4_HW_STATUS 0x158b
+#define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2
+#define mmDC_I2C_DDC5_HW_STATUS 0x158c
+#define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2
+#define mmDC_I2C_DDC6_HW_STATUS 0x158d
+#define mmDC_I2C_DDC6_HW_STATUS_BASE_IDX 2
+#define mmDC_I2C_DDC1_SPEED 0x158e
+#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2
+#define mmDC_I2C_DDC1_SETUP 0x158f
+#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2
+#define mmDC_I2C_DDC2_SPEED 0x1590
+#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2
+#define mmDC_I2C_DDC2_SETUP 0x1591
+#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2
+#define mmDC_I2C_DDC3_SPEED 0x1592
+#define mmDC_I2C_DDC3_SPEED_BASE_IDX 2
+#define mmDC_I2C_DDC3_SETUP 0x1593
+#define mmDC_I2C_DDC3_SETUP_BASE_IDX 2
+#define mmDC_I2C_DDC4_SPEED 0x1594
+#define mmDC_I2C_DDC4_SPEED_BASE_IDX 2
+#define mmDC_I2C_DDC4_SETUP 0x1595
+#define mmDC_I2C_DDC4_SETUP_BASE_IDX 2
+#define mmDC_I2C_DDC5_SPEED 0x1596
+#define mmDC_I2C_DDC5_SPEED_BASE_IDX 2
+#define mmDC_I2C_DDC5_SETUP 0x1597
+#define mmDC_I2C_DDC5_SETUP_BASE_IDX 2
+#define mmDC_I2C_DDC6_SPEED 0x1598
+#define mmDC_I2C_DDC6_SPEED_BASE_IDX 2
+#define mmDC_I2C_DDC6_SETUP 0x1599
+#define mmDC_I2C_DDC6_SETUP_BASE_IDX 2
+#define mmDC_I2C_TRANSACTION0 0x159a
+#define mmDC_I2C_TRANSACTION0_BASE_IDX 2
+#define mmDC_I2C_TRANSACTION1 0x159b
+#define mmDC_I2C_TRANSACTION1_BASE_IDX 2
+#define mmDC_I2C_TRANSACTION2 0x159c
+#define mmDC_I2C_TRANSACTION2_BASE_IDX 2
+#define mmDC_I2C_TRANSACTION3 0x159d
+#define mmDC_I2C_TRANSACTION3_BASE_IDX 2
+#define mmDC_I2C_DATA 0x159e
+#define mmDC_I2C_DATA_BASE_IDX 2
+#define mmDC_I2C_DDCVGA_HW_STATUS 0x159f
+#define mmDC_I2C_DDCVGA_HW_STATUS_BASE_IDX 2
+#define mmDC_I2C_DDCVGA_SPEED 0x15a0
+#define mmDC_I2C_DDCVGA_SPEED_BASE_IDX 2
+#define mmDC_I2C_DDCVGA_SETUP 0x15a1
+#define mmDC_I2C_DDCVGA_SETUP_BASE_IDX 2
+#define mmDC_I2C_EDID_DETECT_CTRL 0x15a2
+#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2
+#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x15a3
+#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2
+#define mmGENERIC_I2C_CONTROL 0x15a4
+#define mmGENERIC_I2C_CONTROL_BASE_IDX 2
+#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x15a5
+#define mmGENERIC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmGENERIC_I2C_STATUS 0x15a6
+#define mmGENERIC_I2C_STATUS_BASE_IDX 2
+#define mmGENERIC_I2C_SPEED 0x15a7
+#define mmGENERIC_I2C_SPEED_BASE_IDX 2
+#define mmGENERIC_I2C_SETUP 0x15a8
+#define mmGENERIC_I2C_SETUP_BASE_IDX 2
+#define mmGENERIC_I2C_TRANSACTION 0x15a9
+#define mmGENERIC_I2C_TRANSACTION_BASE_IDX 2
+#define mmGENERIC_I2C_DATA 0x15aa
+#define mmGENERIC_I2C_DATA_BASE_IDX 2
+#define mmGENERIC_I2C_PIN_SELECTION 0x15ab
+#define mmGENERIC_I2C_PIN_SELECTION_BASE_IDX 2
+#define mmDCO_SCRATCH0 0x15b6
+#define mmDCO_SCRATCH0_BASE_IDX 2
+#define mmDCO_SCRATCH1 0x15b7
+#define mmDCO_SCRATCH1_BASE_IDX 2
+#define mmDCO_SCRATCH2 0x15b8
+#define mmDCO_SCRATCH2_BASE_IDX 2
+#define mmDCO_SCRATCH3 0x15b9
+#define mmDCO_SCRATCH3_BASE_IDX 2
+#define mmDCO_SCRATCH4 0x15ba
+#define mmDCO_SCRATCH4_BASE_IDX 2
+#define mmDCO_SCRATCH5 0x15bb
+#define mmDCO_SCRATCH5_BASE_IDX 2
+#define mmDCO_SCRATCH6 0x15bc
+#define mmDCO_SCRATCH6_BASE_IDX 2
+#define mmDCO_SCRATCH7 0x15bd
+#define mmDCO_SCRATCH7_BASE_IDX 2
+#define mmDCE_VCE_CONTROL 0x15be
+#define mmDCE_VCE_CONTROL_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS 0x15bf
+#define mmDISP_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x15c0
+#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x15c1
+#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x15c2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x15c3
+#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x15c4
+#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x15c5
+#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x15c6
+#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x15c7
+#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x15c8
+#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2
+#define mmDCO_MEM_PWR_STATUS 0x15c9
+#define mmDCO_MEM_PWR_STATUS_BASE_IDX 2
+#define mmDCO_MEM_PWR_CTRL 0x15ca
+#define mmDCO_MEM_PWR_CTRL_BASE_IDX 2
+#define mmDCO_MEM_PWR_CTRL2 0x15cb
+#define mmDCO_MEM_PWR_CTRL2_BASE_IDX 2
+#define mmDCO_CLK_CNTL 0x15cc
+#define mmDCO_CLK_CNTL_BASE_IDX 2
+#define mmDCO_POWER_MANAGEMENT_CNTL 0x15d0
+#define mmDCO_POWER_MANAGEMENT_CNTL_BASE_IDX 2
+#define mmDIG_SOFT_RESET_2 0x15d2
+#define mmDIG_SOFT_RESET_2_BASE_IDX 2
+#define mmDCO_STEREOSYNC_SEL 0x15d6
+#define mmDCO_STEREOSYNC_SEL_BASE_IDX 2
+#define mmDCO_SOFT_RESET 0x15d9
+#define mmDCO_SOFT_RESET_BASE_IDX 2
+#define mmDIG_SOFT_RESET 0x15da
+#define mmDIG_SOFT_RESET_BASE_IDX 2
+#define mmDCO_MEM_PWR_STATUS1 0x15dc
+#define mmDCO_MEM_PWR_STATUS1_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x15dd
+#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2
+#define mmDCO_CLK_CNTL2 0x15de
+#define mmDCO_CLK_CNTL2_BASE_IDX 2
+#define mmDCO_CLK_CNTL3 0x15df
+#define mmDCO_CLK_CNTL3_BASE_IDX 2
+#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL 0x15eb
+#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2
+#define mmDCO_PSP_INTERRUPT_STATUS 0x15ec
+#define mmDCO_PSP_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDCO_PSP_INTERRUPT_CLEAR 0x15ed
+#define mmDCO_PSP_INTERRUPT_CLEAR_BASE_IDX 2
+#define mmDCO_GENERIC_INTERRUPT_MESSAGE 0x15ee
+#define mmDCO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2
+#define mmDCO_GENERIC_INTERRUPT_CLEAR 0x15ef
+#define mmDCO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2
+#define mmFMT_MEMORY0_CONTROL 0x15f0
+#define mmFMT_MEMORY0_CONTROL_BASE_IDX 2
+#define mmFMT_MEMORY1_CONTROL 0x15f1
+#define mmFMT_MEMORY1_CONTROL_BASE_IDX 2
+#define mmFMT_MEMORY2_CONTROL 0x15f2
+#define mmFMT_MEMORY2_CONTROL_BASE_IDX 2
+#define mmFMT_MEMORY3_CONTROL 0x15f3
+#define mmFMT_MEMORY3_CONTROL_BASE_IDX 2
+#define mmFMT_MEMORY4_CONTROL 0x15f4
+#define mmFMT_MEMORY4_CONTROL_BASE_IDX 2
+#define mmFMT_MEMORY5_CONTROL 0x15f5
+#define mmFMT_MEMORY5_CONTROL_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x15f6
+#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2
+#define mmDC_GENERICA 0x207e
+#define mmDC_GENERICA_BASE_IDX 2
+#define mmDC_GENERICB 0x207f
+#define mmDC_GENERICB_BASE_IDX 2
+#define mmDC_PAD_EXTERN_SIG 0x2080
+#define mmDC_PAD_EXTERN_SIG_BASE_IDX 2
+#define mmDC_REF_CLK_CNTL 0x2081
+#define mmDC_REF_CLK_CNTL_BASE_IDX 2
+#define mmDC_GPIO_DEBUG 0x2082
+#define mmDC_GPIO_DEBUG_BASE_IDX 2
+#define mmUNIPHYA_LINK_CNTL 0x2083
+#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2
+#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x2084
+#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2
+#define mmUNIPHYB_LINK_CNTL 0x2085
+#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2
+#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2086
+#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2
+#define mmUNIPHYC_LINK_CNTL 0x2087
+#define mmUNIPHYC_LINK_CNTL_BASE_IDX 2
+#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2088
+#define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2
+#define mmUNIPHYD_LINK_CNTL 0x2089
+#define mmUNIPHYD_LINK_CNTL_BASE_IDX 2
+#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x208a
+#define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2
+#define mmUNIPHYE_LINK_CNTL 0x208b
+#define mmUNIPHYE_LINK_CNTL_BASE_IDX 2
+#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x208c
+#define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2
+#define mmUNIPHYF_LINK_CNTL 0x208d
+#define mmUNIPHYF_LINK_CNTL_BASE_IDX 2
+#define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x208e
+#define mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2
+#define mmUNIPHYG_LINK_CNTL 0x208f
+#define mmUNIPHYG_LINK_CNTL_BASE_IDX 2
+#define mmUNIPHYG_CHANNEL_XBAR_CNTL 0x2090
+#define mmUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX 2
+#define mmDCIO_WRCMD_DELAY 0x2094
+#define mmDCIO_WRCMD_DELAY_BASE_IDX 2
+#define mmDC_DVODATA_CONFIG 0x2098
+#define mmDC_DVODATA_CONFIG_BASE_IDX 2
+#define mmLVTMA_PWRSEQ_CNTL 0x2099
+#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2
+#define mmLVTMA_PWRSEQ_STATE 0x209a
+#define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2
+#define mmLVTMA_PWRSEQ_REF_DIV 0x209b
+#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2
+#define mmLVTMA_PWRSEQ_DELAY1 0x209c
+#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2
+#define mmLVTMA_PWRSEQ_DELAY2 0x209d
+#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2
+#define mmBL_PWM_CNTL 0x209e
+#define mmBL_PWM_CNTL_BASE_IDX 2
+#define mmBL_PWM_CNTL2 0x209f
+#define mmBL_PWM_CNTL2_BASE_IDX 2
+#define mmBL_PWM_PERIOD_CNTL 0x20a0
+#define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2
+#define mmBL_PWM_GRP1_REG_LOCK 0x20a1
+#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2
+#define mmDCIO_GSL_GENLK_PAD_CNTL 0x20a2
+#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2
+#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x20a3
+#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2
+#define mmDCIO_GSL0_CNTL 0x20a4
+#define mmDCIO_GSL0_CNTL_BASE_IDX 2
+#define mmDCIO_GSL1_CNTL 0x20a5
+#define mmDCIO_GSL1_CNTL_BASE_IDX 2
+#define mmDCIO_GSL2_CNTL 0x20a6
+#define mmDCIO_GSL2_CNTL_BASE_IDX 2
+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x20a7
+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2
+#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x20a8
+#define mmDC_GPU_TIMER_START_POSITION_P_FLIP_BASE_IDX 2
+#define mmDC_GPU_TIMER_READ 0x20a9
+#define mmDC_GPU_TIMER_READ_BASE_IDX 2
+#define mmDC_GPU_TIMER_READ_CNTL 0x20aa
+#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2
+#define mmDCIO_CLOCK_CNTL 0x20ab
+#define mmDCIO_CLOCK_CNTL_BASE_IDX 2
+#define mmDCO_DCFE_EXT_VSYNC_CNTL 0x20ae
+#define mmDCO_DCFE_EXT_VSYNC_CNTL_BASE_IDX 2
+#define mmDCIO_SOFT_RESET 0x20b4
+#define mmDCIO_SOFT_RESET_BASE_IDX 2
+#define mmDCIO_DPHY_SEL 0x20b5
+#define mmDCIO_DPHY_SEL_BASE_IDX 2
+#define mmUNIPHY_IMPCAL_LINKA 0x20b6
+#define mmUNIPHY_IMPCAL_LINKA_BASE_IDX 2
+#define mmUNIPHY_IMPCAL_LINKB 0x20b7
+#define mmUNIPHY_IMPCAL_LINKB_BASE_IDX 2
+#define mmUNIPHY_IMPCAL_PERIOD 0x20b8
+#define mmUNIPHY_IMPCAL_PERIOD_BASE_IDX 2
+#define mmAUXP_IMPCAL 0x20b9
+#define mmAUXP_IMPCAL_BASE_IDX 2
+#define mmAUXN_IMPCAL 0x20ba
+#define mmAUXN_IMPCAL_BASE_IDX 2
+#define mmDCIO_IMPCAL_CNTL 0x20bb
+#define mmDCIO_IMPCAL_CNTL_BASE_IDX 2
+#define mmUNIPHY_IMPCAL_PSW_AB 0x20bc
+#define mmUNIPHY_IMPCAL_PSW_AB_BASE_IDX 2
+#define mmUNIPHY_IMPCAL_LINKC 0x20bd
+#define mmUNIPHY_IMPCAL_LINKC_BASE_IDX 2
+#define mmUNIPHY_IMPCAL_LINKD 0x20be
+#define mmUNIPHY_IMPCAL_LINKD_BASE_IDX 2
+#define mmDCIO_IMPCAL_CNTL_CD 0x20bf
+#define mmDCIO_IMPCAL_CNTL_CD_BASE_IDX 2
+#define mmUNIPHY_IMPCAL_PSW_CD 0x20c0
+#define mmUNIPHY_IMPCAL_PSW_CD_BASE_IDX 2
+#define mmUNIPHY_IMPCAL_LINKE 0x20c1
+#define mmUNIPHY_IMPCAL_LINKE_BASE_IDX 2
+#define mmUNIPHY_IMPCAL_LINKF 0x20c2
+#define mmUNIPHY_IMPCAL_LINKF_BASE_IDX 2
+#define mmDCIO_IMPCAL_CNTL_EF 0x20c3
+#define mmDCIO_IMPCAL_CNTL_EF_BASE_IDX 2
+#define mmUNIPHY_IMPCAL_PSW_EF 0x20c4
+#define mmUNIPHY_IMPCAL_PSW_EF_BASE_IDX 2
+#define mmUNIPHYLPA_LINK_CNTL 0x20c5
+#define mmUNIPHYLPA_LINK_CNTL_BASE_IDX 2
+#define mmUNIPHYLPB_LINK_CNTL 0x20c6
+#define mmUNIPHYLPB_LINK_CNTL_BASE_IDX 2
+#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL 0x20c7
+#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL_BASE_IDX 2
+#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL 0x20c8
+#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL_BASE_IDX 2
+#define mmDCIO_DPCS_TX_INTERRUPT 0x20c9
+#define mmDCIO_DPCS_TX_INTERRUPT_BASE_IDX 2
+#define mmDCIO_DPCS_RX_INTERRUPT 0x20ca
+#define mmDCIO_DPCS_RX_INTERRUPT_BASE_IDX 2
+#define mmDCIO_SEMAPHORE0 0x20cb
+#define mmDCIO_SEMAPHORE0_BASE_IDX 2
+#define mmDCIO_SEMAPHORE1 0x20cc
+#define mmDCIO_SEMAPHORE1_BASE_IDX 2
+#define mmDCIO_SEMAPHORE2 0x20cd
+#define mmDCIO_SEMAPHORE2_BASE_IDX 2
+#define mmDCIO_SEMAPHORE3 0x20ce
+#define mmDCIO_SEMAPHORE3_BASE_IDX 2
+#define mmDCIO_SEMAPHORE4 0x20cf
+#define mmDCIO_SEMAPHORE4_BASE_IDX 2
+#define mmDCIO_SEMAPHORE5 0x20d0
+#define mmDCIO_SEMAPHORE5_BASE_IDX 2
+#define mmDCIO_SEMAPHORE6 0x20d1
+#define mmDCIO_SEMAPHORE6_BASE_IDX 2
+#define mmDCIO_SEMAPHORE7 0x20d2
+#define mmDCIO_SEMAPHORE7_BASE_IDX 2
+#define mmDC_GPIO_GENERIC_MASK 0x20de
+#define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2
+#define mmDC_GPIO_GENERIC_A 0x20df
+#define mmDC_GPIO_GENERIC_A_BASE_IDX 2
+#define mmDC_GPIO_GENERIC_EN 0x20e0
+#define mmDC_GPIO_GENERIC_EN_BASE_IDX 2
+#define mmDC_GPIO_GENERIC_Y 0x20e1
+#define mmDC_GPIO_GENERIC_Y_BASE_IDX 2
+#define mmDC_GPIO_DVODATA_MASK 0x20e2
+#define mmDC_GPIO_DVODATA_MASK_BASE_IDX 2
+#define mmDC_GPIO_DVODATA_A 0x20e3
+#define mmDC_GPIO_DVODATA_A_BASE_IDX 2
+#define mmDC_GPIO_DVODATA_EN 0x20e4
+#define mmDC_GPIO_DVODATA_EN_BASE_IDX 2
+#define mmDC_GPIO_DVODATA_Y 0x20e5
+#define mmDC_GPIO_DVODATA_Y_BASE_IDX 2
+#define mmDC_GPIO_DDC1_MASK 0x20e6
+#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2
+#define mmDC_GPIO_DDC1_A 0x20e7
+#define mmDC_GPIO_DDC1_A_BASE_IDX 2
+#define mmDC_GPIO_DDC1_EN 0x20e8
+#define mmDC_GPIO_DDC1_EN_BASE_IDX 2
+#define mmDC_GPIO_DDC1_Y 0x20e9
+#define mmDC_GPIO_DDC1_Y_BASE_IDX 2
+#define mmDC_GPIO_DDC2_MASK 0x20ea
+#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2
+#define mmDC_GPIO_DDC2_A 0x20eb
+#define mmDC_GPIO_DDC2_A_BASE_IDX 2
+#define mmDC_GPIO_DDC2_EN 0x20ec
+#define mmDC_GPIO_DDC2_EN_BASE_IDX 2
+#define mmDC_GPIO_DDC2_Y 0x20ed
+#define mmDC_GPIO_DDC2_Y_BASE_IDX 2
+#define mmDC_GPIO_DDC3_MASK 0x20ee
+#define mmDC_GPIO_DDC3_MASK_BASE_IDX 2
+#define mmDC_GPIO_DDC3_A 0x20ef
+#define mmDC_GPIO_DDC3_A_BASE_IDX 2
+#define mmDC_GPIO_DDC3_EN 0x20f0
+#define mmDC_GPIO_DDC3_EN_BASE_IDX 2
+#define mmDC_GPIO_DDC3_Y 0x20f1
+#define mmDC_GPIO_DDC3_Y_BASE_IDX 2
+#define mmDC_GPIO_DDC4_MASK 0x20f2
+#define mmDC_GPIO_DDC4_MASK_BASE_IDX 2
+#define mmDC_GPIO_DDC4_A 0x20f3
+#define mmDC_GPIO_DDC4_A_BASE_IDX 2
+#define mmDC_GPIO_DDC4_EN 0x20f4
+#define mmDC_GPIO_DDC4_EN_BASE_IDX 2
+#define mmDC_GPIO_DDC4_Y 0x20f5
+#define mmDC_GPIO_DDC4_Y_BASE_IDX 2
+#define mmDC_GPIO_DDC5_MASK 0x20f6
+#define mmDC_GPIO_DDC5_MASK_BASE_IDX 2
+#define mmDC_GPIO_DDC5_A 0x20f7
+#define mmDC_GPIO_DDC5_A_BASE_IDX 2
+#define mmDC_GPIO_DDC5_EN 0x20f8
+#define mmDC_GPIO_DDC5_EN_BASE_IDX 2
+#define mmDC_GPIO_DDC5_Y 0x20f9
+#define mmDC_GPIO_DDC5_Y_BASE_IDX 2
+#define mmDC_GPIO_DDC6_MASK 0x20fa
+#define mmDC_GPIO_DDC6_MASK_BASE_IDX 2
+#define mmDC_GPIO_DDC6_A 0x20fb
+#define mmDC_GPIO_DDC6_A_BASE_IDX 2
+#define mmDC_GPIO_DDC6_EN 0x20fc
+#define mmDC_GPIO_DDC6_EN_BASE_IDX 2
+#define mmDC_GPIO_DDC6_Y 0x20fd
+#define mmDC_GPIO_DDC6_Y_BASE_IDX 2
+#define mmDC_GPIO_DDCVGA_MASK 0x20fe
+#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2
+#define mmDC_GPIO_DDCVGA_A 0x20ff
+#define mmDC_GPIO_DDCVGA_A_BASE_IDX 2
+#define mmDC_GPIO_DDCVGA_EN 0x2100
+#define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2
+#define mmDC_GPIO_DDCVGA_Y 0x2101
+#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2
+#define mmDC_GPIO_SYNCA_MASK 0x2102
+#define mmDC_GPIO_SYNCA_MASK_BASE_IDX 2
+#define mmDC_GPIO_SYNCA_A 0x2103
+#define mmDC_GPIO_SYNCA_A_BASE_IDX 2
+#define mmDC_GPIO_SYNCA_EN 0x2104
+#define mmDC_GPIO_SYNCA_EN_BASE_IDX 2
+#define mmDC_GPIO_SYNCA_Y 0x2105
+#define mmDC_GPIO_SYNCA_Y_BASE_IDX 2
+#define mmDC_GPIO_GENLK_MASK 0x2106
+#define mmDC_GPIO_GENLK_MASK_BASE_IDX 2
+#define mmDC_GPIO_GENLK_A 0x2107
+#define mmDC_GPIO_GENLK_A_BASE_IDX 2
+#define mmDC_GPIO_GENLK_EN 0x2108
+#define mmDC_GPIO_GENLK_EN_BASE_IDX 2
+#define mmDC_GPIO_GENLK_Y 0x2109
+#define mmDC_GPIO_GENLK_Y_BASE_IDX 2
+#define mmDC_GPIO_HPD_MASK 0x210a
+#define mmDC_GPIO_HPD_MASK_BASE_IDX 2
+#define mmDC_GPIO_HPD_A 0x210b
+#define mmDC_GPIO_HPD_A_BASE_IDX 2
+#define mmDC_GPIO_HPD_EN 0x210c
+#define mmDC_GPIO_HPD_EN_BASE_IDX 2
+#define mmDC_GPIO_HPD_Y 0x210d
+#define mmDC_GPIO_HPD_Y_BASE_IDX 2
+#define mmDC_GPIO_PWRSEQ_MASK 0x210e
+#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2
+#define mmDC_GPIO_PWRSEQ_A 0x210f
+#define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2
+#define mmDC_GPIO_PWRSEQ_EN 0x2110
+#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2
+#define mmDC_GPIO_PWRSEQ_Y 0x2111
+#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2
+#define mmDC_GPIO_PAD_STRENGTH_1 0x2112
+#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2
+#define mmDC_GPIO_PAD_STRENGTH_2 0x2113
+#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2
+#define mmPHY_AUX_CNTL 0x2115
+#define mmPHY_AUX_CNTL_BASE_IDX 2
+#define mmDC_GPIO_I2CPAD_MASK 0x2116
+#define mmDC_GPIO_I2CPAD_MASK_BASE_IDX 2
+#define mmDC_GPIO_I2CPAD_A 0x2117
+#define mmDC_GPIO_I2CPAD_A_BASE_IDX 2
+#define mmDC_GPIO_I2CPAD_EN 0x2118
+#define mmDC_GPIO_I2CPAD_EN_BASE_IDX 2
+#define mmDC_GPIO_I2CPAD_Y 0x2119
+#define mmDC_GPIO_I2CPAD_Y_BASE_IDX 2
+#define mmDC_GPIO_I2CPAD_STRENGTH 0x211a
+#define mmDC_GPIO_I2CPAD_STRENGTH_BASE_IDX 2
+#define mmDVO_STRENGTH_CONTROL 0x211b
+#define mmDVO_STRENGTH_CONTROL_BASE_IDX 2
+#define mmDVO_VREF_CONTROL 0x211c
+#define mmDVO_VREF_CONTROL_BASE_IDX 2
+#define mmDVO_SKEW_ADJUST 0x211d
+#define mmDVO_SKEW_ADJUST_BASE_IDX 2
+#define mmDC_GPIO_I2S_SPDIF_MASK 0x2126
+#define mmDC_GPIO_I2S_SPDIF_MASK_BASE_IDX 2
+#define mmDC_GPIO_I2S_SPDIF_A 0x2127
+#define mmDC_GPIO_I2S_SPDIF_A_BASE_IDX 2
+#define mmDC_GPIO_I2S_SPDIF_EN 0x2128
+#define mmDC_GPIO_I2S_SPDIF_EN_BASE_IDX 2
+#define mmDC_GPIO_I2S_SPDIF_Y 0x2129
+#define mmDC_GPIO_I2S_SPDIF_Y_BASE_IDX 2
+#define mmDC_GPIO_I2S_SPDIF_STRENGTH 0x212a
+#define mmDC_GPIO_I2S_SPDIF_STRENGTH_BASE_IDX 2
+#define mmDC_GPIO_TX12_EN 0x212b
+#define mmDC_GPIO_TX12_EN_BASE_IDX 2
+#define mmDC_GPIO_AUX_CTRL_0 0x212c
+#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2
+#define mmDC_GPIO_AUX_CTRL_1 0x212d
+#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2
+#define mmDC_GPIO_AUX_CTRL_2 0x212e
+#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2
+#define mmDC_GPIO_RXEN 0x212f
+#define mmDC_GPIO_RXEN_BASE_IDX 2
+#define mmBPHYC_DAC_MACRO_CNTL 0x2136
+#define mmBPHYC_DAC_MACRO_CNTL_BASE_IDX 2
+#define mmDAC_MACRO_CNTL_RESERVED0 0x2136
+#define mmDAC_MACRO_CNTL_RESERVED0_BASE_IDX 2
+#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x2137
+#define mmBPHYC_DAC_AUTO_CALIB_CONTROL_BASE_IDX 2
+#define mmDAC_MACRO_CNTL_RESERVED1 0x2137
+#define mmDAC_MACRO_CNTL_RESERVED1_BASE_IDX 2
+#define mmDAC_MACRO_CNTL_RESERVED2 0x2138
+#define mmDAC_MACRO_CNTL_RESERVED2_BASE_IDX 2
+#define mmDAC_MACRO_CNTL_RESERVED3 0x2139
+#define mmDAC_MACRO_CNTL_RESERVED3_BASE_IDX 2
+#define mmDISP_DSI_DUAL_CTRL 0x277e
+#define mmDISP_DSI_DUAL_CTRL_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED0 0x283e
+#define mmDPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED1 0x283f
+#define mmDPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED2 0x2840
+#define mmDPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED3 0x2841
+#define mmDPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED4 0x2842
+#define mmDPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED5 0x2843
+#define mmDPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED6 0x2844
+#define mmDPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED7 0x2845
+#define mmDPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED8 0x2846
+#define mmDPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED9 0x2847
+#define mmDPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED10 0x2848
+#define mmDPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED11 0x2849
+#define mmDPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED12 0x284a
+#define mmDPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED13 0x284b
+#define mmDPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED14 0x284c
+#define mmDPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED15 0x284d
+#define mmDPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED16 0x284e
+#define mmDPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED17 0x284f
+#define mmDPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED18 0x2850
+#define mmDPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED19 0x2851
+#define mmDPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED20 0x2852
+#define mmDPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED21 0x2853
+#define mmDPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED22 0x2854
+#define mmDPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED23 0x2855
+#define mmDPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED24 0x2856
+#define mmDPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED25 0x2857
+#define mmDPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED26 0x2858
+#define mmDPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED27 0x2859
+#define mmDPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED28 0x285a
+#define mmDPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED29 0x285b
+#define mmDPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED30 0x285c
+#define mmDPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED31 0x285d
+#define mmDPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED32 0x285e
+#define mmDPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED33 0x285f
+#define mmDPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED34 0x2860
+#define mmDPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED35 0x2861
+#define mmDPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED36 0x2862
+#define mmDPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED37 0x2863
+#define mmDPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED38 0x2864
+#define mmDPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED39 0x2865
+#define mmDPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED40 0x2866
+#define mmDPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED41 0x2867
+#define mmDPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED42 0x2868
+#define mmDPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED43 0x2869
+#define mmDPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED44 0x286a
+#define mmDPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED45 0x286b
+#define mmDPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED46 0x286c
+#define mmDPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED47 0x286d
+#define mmDPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED48 0x286e
+#define mmDPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED49 0x286f
+#define mmDPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED50 0x2870
+#define mmDPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED51 0x2871
+#define mmDPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED52 0x2872
+#define mmDPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED53 0x2873
+#define mmDPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED54 0x2874
+#define mmDPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED55 0x2875
+#define mmDPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED56 0x2876
+#define mmDPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED57 0x2877
+#define mmDPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED58 0x2878
+#define mmDPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED59 0x2879
+#define mmDPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED60 0x287a
+#define mmDPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED61 0x287b
+#define mmDPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED62 0x287c
+#define mmDPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
+#define mmDPHY_MACRO_CNTL_RESERVED63 0x287d
+#define mmDPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
+#define mmDPRX_AUX_REFERENCE_PULSE_DIV 0x2a7e
+#define mmDPRX_AUX_REFERENCE_PULSE_DIV_BASE_IDX 2
+#define mmDPRX_AUX_CONTROL 0x2a7f
+#define mmDPRX_AUX_CONTROL_BASE_IDX 2
+#define mmDPRX_AUX_HPD_CONTROL1 0x2a80
+#define mmDPRX_AUX_HPD_CONTROL1_BASE_IDX 2
+#define mmDPRX_AUX_HPD_CONTROL2 0x2a81
+#define mmDPRX_AUX_HPD_CONTROL2_BASE_IDX 2
+#define mmDPRX_AUX_RX_STATUS 0x2a82
+#define mmDPRX_AUX_RX_STATUS_BASE_IDX 2
+#define mmDPRX_AUX_RX_ERROR_MASK 0x2a83
+#define mmDPRX_AUX_RX_ERROR_MASK_BASE_IDX 2
+#define mmDPRX_AUX_DPHY_TX_REF_CONTROL 0x2a84
+#define mmDPRX_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
+#define mmDPRX_AUX_DPHY_TX_CONTROL 0x2a85
+#define mmDPRX_AUX_DPHY_TX_CONTROL_BASE_IDX 2
+#define mmDPRX_AUX_DPHY_RX_CONTROL0 0x2a86
+#define mmDPRX_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
+#define mmDPRX_AUX_DPHY_RX_CONTROL1 0x2a87
+#define mmDPRX_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
+#define mmDPRX_AUX_DPHY_TX_STATUS 0x2a88
+#define mmDPRX_AUX_DPHY_TX_STATUS_BASE_IDX 2
+#define mmDPRX_AUX_DPHY_RX_STATUS 0x2a89
+#define mmDPRX_AUX_DPHY_RX_STATUS_BASE_IDX 2
+#define mmDPRX_AUX_DMCU_HW_INT_STATUS 0x2a8a
+#define mmDPRX_AUX_DMCU_HW_INT_STATUS_BASE_IDX 2
+#define mmDPRX_AUX_DMCU_HW_INT_ACK 0x2a8b
+#define mmDPRX_AUX_DMCU_HW_INT_ACK_BASE_IDX 2
+#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1 0x2a8c
+#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1_BASE_IDX 2
+#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2 0x2a8d
+#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2_BASE_IDX 2
+#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1 0x2a8e
+#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1_BASE_IDX 2
+#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2 0x2a8f
+#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2_BASE_IDX 2
+#define mmDPRX_AUX_AUX_BUF_INDEX 0x2a90
+#define mmDPRX_AUX_AUX_BUF_INDEX_BASE_IDX 2
+#define mmDPRX_AUX_AUX_BUF_DATA 0x2a91
+#define mmDPRX_AUX_AUX_BUF_DATA_BASE_IDX 2
+#define mmDPRX_AUX_EDID_INDEX 0x2a92
+#define mmDPRX_AUX_EDID_INDEX_BASE_IDX 2
+#define mmDPRX_AUX_EDID_DATA 0x2a93
+#define mmDPRX_AUX_EDID_DATA_BASE_IDX 2
+#define mmDPRX_AUX_DPCD_INDEX1 0x2a94
+#define mmDPRX_AUX_DPCD_INDEX1_BASE_IDX 2
+#define mmDPRX_AUX_DPCD_DATA1 0x2a95
+#define mmDPRX_AUX_DPCD_DATA1_BASE_IDX 2
+#define mmDPRX_AUX_DPCD_INDEX2 0x2a96
+#define mmDPRX_AUX_DPCD_INDEX2_BASE_IDX 2
+#define mmDPRX_AUX_DPCD_DATA2 0x2a97
+#define mmDPRX_AUX_DPCD_DATA2_BASE_IDX 2
+#define mmDPRX_AUX_MSG_INDEX1 0x2a98
+#define mmDPRX_AUX_MSG_INDEX1_BASE_IDX 2
+#define mmDPRX_AUX_MSG_DATA1 0x2a99
+#define mmDPRX_AUX_MSG_DATA1_BASE_IDX 2
+#define mmDPRX_AUX_MSG_INDEX2 0x2a9a
+#define mmDPRX_AUX_MSG_INDEX2_BASE_IDX 2
+#define mmDPRX_AUX_MSG_DATA2 0x2a9b
+#define mmDPRX_AUX_MSG_DATA2_BASE_IDX 2
+#define mmDPRX_AUX_KSV_INDEX1 0x2a9c
+#define mmDPRX_AUX_KSV_INDEX1_BASE_IDX 2
+#define mmDPRX_AUX_KSV_DATA1 0x2a9d
+#define mmDPRX_AUX_KSV_DATA1_BASE_IDX 2
+#define mmDPRX_AUX_KSV_INDEX2 0x2a9e
+#define mmDPRX_AUX_KSV_INDEX2_BASE_IDX 2
+#define mmDPRX_AUX_KSV_DATA2 0x2a9f
+#define mmDPRX_AUX_KSV_DATA2_BASE_IDX 2
+#define mmDPRX_AUX_MSG_TIMEOUT_CONTROL 0x2aa0
+#define mmDPRX_AUX_MSG_TIMEOUT_CONTROL_BASE_IDX 2
+#define mmDPRX_AUX_MSG_BUF_CONTROL1 0x2aa1
+#define mmDPRX_AUX_MSG_BUF_CONTROL1_BASE_IDX 2
+#define mmDPRX_AUX_MSG_BUF_CONTROL2 0x2aa2
+#define mmDPRX_AUX_MSG_BUF_CONTROL2_BASE_IDX 2
+#define mmDPRX_AUX_SCRATCH1 0x2aa3
+#define mmDPRX_AUX_SCRATCH1_BASE_IDX 2
+#define mmDPRX_AUX_SCRATCH2 0x2aa4
+#define mmDPRX_AUX_SCRATCH2_BASE_IDX 2
+#define mmDPRX_AUX_MSG1_PENDING 0x2aa5
+#define mmDPRX_AUX_MSG1_PENDING_BASE_IDX 2
+#define mmDPRX_AUX_MSG2_PENDING 0x2aa6
+#define mmDPRX_AUX_MSG2_PENDING_BASE_IDX 2
+#define mmDPRX_AUX_MSG3_PENDING 0x2aa7
+#define mmDPRX_AUX_MSG3_PENDING_BASE_IDX 2
+#define mmDPRX_AUX_MSG4_PENDING 0x2aa8
+#define mmDPRX_AUX_MSG4_PENDING_BASE_IDX 2
+#define mmDPRX_DPHY_DPCD_LANE_COUNT_SET 0x2afe
+#define mmDPRX_DPHY_DPCD_LANE_COUNT_SET_BASE_IDX 2
+#define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET 0x2aff
+#define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET_BASE_IDX 2
+#define mmDPRX_DPHY_DPCD_MSTM_CTRL 0x2b00
+#define mmDPRX_DPHY_DPCD_MSTM_CTRL_BASE_IDX 2
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET 0x2b01
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET_BASE_IDX 2
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS 0x2b02
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS_BASE_IDX 2
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET 0x2b03
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET_BASE_IDX 2
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS 0x2b04
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS_BASE_IDX 2
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET 0x2b05
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET_BASE_IDX 2
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS 0x2b06
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS_BASE_IDX 2
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET 0x2b07
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET_BASE_IDX 2
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS 0x2b08
+#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS_BASE_IDX 2
+#define mmDPRX_DPHY_READY 0x2b09
+#define mmDPRX_DPHY_READY_BASE_IDX 2
+#define mmDPRX_DPHY_COMMA_STATUS 0x2b0b
+#define mmDPRX_DPHY_COMMA_STATUS_BASE_IDX 2
+#define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED 0x2b0c
+#define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED_BASE_IDX 2
+#define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED 0x2b0d
+#define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED_BASE_IDX 2
+#define mmDPRX_DPHY_ERROR_THRESH_A_LANE0 0x2b0f
+#define mmDPRX_DPHY_ERROR_THRESH_A_LANE0_BASE_IDX 2
+#define mmDPRX_DPHY_ERROR_COUNT_A_LANE0 0x2b11
+#define mmDPRX_DPHY_ERROR_COUNT_A_LANE0_BASE_IDX 2
+#define mmDPRX_DPHY_ERROR_COUNT_B_LANE0 0x2b12
+#define mmDPRX_DPHY_ERROR_COUNT_B_LANE0_BASE_IDX 2
+#define mmDPRX_DPHY_ERROR_COUNT_C_LANE0 0x2b13
+#define mmDPRX_DPHY_ERROR_COUNT_C_LANE0_BASE_IDX 2
+#define mmDPRX_DPHY_ERROR_THRESH_A_LANE1 0x2b14
+#define mmDPRX_DPHY_ERROR_THRESH_A_LANE1_BASE_IDX 2
+#define mmDPRX_DPHY_ERROR_COUNT_A_LANE1 0x2b16
+#define mmDPRX_DPHY_ERROR_COUNT_A_LANE1_BASE_IDX 2
+#define mmDPRX_DPHY_ERROR_COUNT_B_LANE1 0x2b17
+#define mmDPRX_DPHY_ERROR_COUNT_B_LANE1_BASE_IDX 2
+#define mmDPRX_DPHY_ERROR_COUNT_C_LANE1 0x2b18
+#define mmDPRX_DPHY_ERROR_COUNT_C_LANE1_BASE_IDX 2
+#define mmDPRX_DPHY_ERROR_THRESH_A_LANE2 0x2b19
+#define mmDPRX_DPHY_ERROR_THRESH_A_LANE2_BASE_IDX 2
+#define mmDPRX_DPHY_ERROR_COUNT_A_LANE2 0x2b1b
+#define mmDPRX_DPHY_ERROR_COUNT_A_LANE2_BASE_IDX 2
+#define mmDPRX_DPHY_ERROR_COUNT_B_LANE2 0x2b1c
+#define mmDPRX_DPHY_ERROR_COUNT_B_LANE2_BASE_IDX 2
+#define mmDPRX_DPHY_ERROR_COUNT_C_LANE2 0x2b1d
+#define mmDPRX_DPHY_ERROR_COUNT_C_LANE2_BASE_IDX 2
+#define mmDPRX_DPHY_ERROR_THRESH_A_LANE3 0x2b1e
+#define mmDPRX_DPHY_ERROR_THRESH_A_LANE3_BASE_IDX 2
+#define mmDPRX_DPHY_ERROR_COUNT_A_LANE3 0x2b20
+#define mmDPRX_DPHY_ERROR_COUNT_A_LANE3_BASE_IDX 2
+#define mmDPRX_DPHY_ERROR_COUNT_B_LANE3 0x2b21
+#define mmDPRX_DPHY_ERROR_COUNT_B_LANE3_BASE_IDX 2
+#define mmDPRX_DPHY_ERROR_COUNT_C_LANE3 0x2b22
+#define mmDPRX_DPHY_ERROR_COUNT_C_LANE3_BASE_IDX 2
+#define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL 0x2b24
+#define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL_BASE_IDX 2
+#define mmDPRX_DPHY_SR_ERROR_COUNT_A 0x2b25
+#define mmDPRX_DPHY_SR_ERROR_COUNT_A_BASE_IDX 2
+#define mmDPRX_DPHY_BS_ERROR_COUNT_A 0x2b27
+#define mmDPRX_DPHY_BS_ERROR_COUNT_A_BASE_IDX 2
+#define mmDPRX_DPHY_BS_ERROR_COUNT_B 0x2b28
+#define mmDPRX_DPHY_BS_ERROR_COUNT_B_BASE_IDX 2
+#define mmDPRX_DPHY_LANESETUP0 0x2b2d
+#define mmDPRX_DPHY_LANESETUP0_BASE_IDX 2
+#define mmDPRX_DPHY_LANESETUP1 0x2b2e
+#define mmDPRX_DPHY_LANESETUP1_BASE_IDX 2
+#define mmDPRX_DPHY_LFSRADV 0x2b31
+#define mmDPRX_DPHY_LFSRADV_BASE_IDX 2
+#define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT 0x2b32
+#define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT_BASE_IDX 2
+#define mmDPRX_DPHY_SET_ENABLE 0x2b33
+#define mmDPRX_DPHY_SET_ENABLE_BASE_IDX 2
+#define mmDPRX_DPHY_ECF_LSB 0x2b34
+#define mmDPRX_DPHY_ECF_LSB_BASE_IDX 2
+#define mmDPRX_DPHY_ECF_MSB 0x2b35
+#define mmDPRX_DPHY_ECF_MSB_BASE_IDX 2
+#define mmDPRX_DPHY_ENHANCED_FRAME_EN 0x2b36
+#define mmDPRX_DPHY_ENHANCED_FRAME_EN_BASE_IDX 2
+#define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE 0x2b3c
+#define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE_BASE_IDX 2
+#define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA 0x2b3d
+#define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA_BASE_IDX 2
+#define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL 0x2b3e
+#define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL_BASE_IDX 2
+#define mmDPRX_DPHY_BYPASS 0x2b3f
+#define mmDPRX_DPHY_BYPASS_BASE_IDX 2
+#define mmDPRX_DPHY_INT_RESET 0x2b40
+#define mmDPRX_DPHY_INT_RESET_BASE_IDX 2
+#define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS 0x2b41
+#define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
+#define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS 0x2b43
+#define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
+#define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS 0x2b44
+#define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
+#define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS 0x2b46
+#define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
+#define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS 0x2b48
+#define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS_BASE_IDX 2
+#define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS 0x2b49
+#define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS_BASE_IDX 2
+#define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS 0x2b4a
+#define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS_BASE_IDX 2
+#define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS 0x2b4b
+#define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS_BASE_IDX 2
+#define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS 0x2b4c
+#define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS_BASE_IDX 2
+#define mmDPRX_DPHY_SPARE 0x2b4d
+#define mmDPRX_DPHY_SPARE_BASE_IDX 2
+#define mmDCRX_GATE_DISABLE_CNTL 0x2b6e
+#define mmDCRX_GATE_DISABLE_CNTL_BASE_IDX 2
+#define mmDCRX_SOFT_RESET 0x2b6f
+#define mmDCRX_SOFT_RESET_BASE_IDX 2
+#define mmDCRX_LIGHT_SLEEP_CNTL 0x2b70
+#define mmDCRX_LIGHT_SLEEP_CNTL_BASE_IDX 2
+#define mmDCRX_DISPCLK_GATE_CNTL 0x2b73
+#define mmDCRX_DISPCLK_GATE_CNTL_BASE_IDX 2
+#define mmDCRX_CLK_CNTL 0x2b74
+#define mmDCRX_CLK_CNTL_BASE_IDX 2
+#define mmDCRX_TEST_CLK_CNTL 0x2b75
+#define mmDCRX_TEST_CLK_CNTL_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x2c06
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x2c07
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x2c08
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x2c09
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x2c0a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x2c0b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x2c0c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x2c0d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x2c0e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x2c0f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x2c10
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x2c11
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x2c12
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x2c13
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x2c14
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x2c15
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x2c16
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x2c17
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x2c18
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x2c19
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x2c1a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x2c1b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x2c1c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x2c1d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x2c1e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x2c1f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x2c20
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x2c21
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x2c22
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x2c23
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x2c24
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x2c25
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x2c26
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x2c27
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x2c28
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x2c29
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x2c2a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x2c2b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x2c2c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x2c2d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x2c2e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x2c2f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x2c30
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x2c31
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x2c32
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x2c33
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x2c34
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x2c35
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x2c36
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x2c37
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x2c38
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x2c39
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x2c3a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x2c3b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x2c3c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x2c3d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x2c3e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x2c3f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x2c40
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x2c41
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x2c42
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED61 0x2c43
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED62 0x2c44
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED63 0x2c45
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED64 0x2c46
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED65 0x2c47
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED66 0x2c48
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED67 0x2c49
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED68 0x2c4a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED69 0x2c4b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED70 0x2c4c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED71 0x2c4d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED72 0x2c4e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED73 0x2c4f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED74 0x2c50
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED75 0x2c51
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED76 0x2c52
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED77 0x2c53
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED78 0x2c54
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED79 0x2c55
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED80 0x2c56
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED81 0x2c57
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED82 0x2c58
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED83 0x2c59
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED84 0x2c5a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED85 0x2c5b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED86 0x2c5c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED87 0x2c5d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED88 0x2c5e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED89 0x2c5f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED90 0x2c60
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED91 0x2c61
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED92 0x2c62
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED93 0x2c63
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED94 0x2c64
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED95 0x2c65
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED96 0x2c66
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED97 0x2c67
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED98 0x2c68
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED99 0x2c69
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED100 0x2c6a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED101 0x2c6b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED102 0x2c6c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED103 0x2c6d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED104 0x2c6e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED105 0x2c6f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED106 0x2c70
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED107 0x2c71
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED108 0x2c72
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED109 0x2c73
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED110 0x2c74
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED111 0x2c75
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED112 0x2c76
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED113 0x2c77
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED114 0x2c78
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED115 0x2c79
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED116 0x2c7a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED117 0x2c7b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED118 0x2c7c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED119 0x2c7d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED120 0x2c7e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED121 0x2c7f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED122 0x2c80
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED123 0x2c81
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED124 0x2c82
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED125 0x2c83
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED126 0x2c84
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED127 0x2c85
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED128 0x2c86
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED129 0x2c87
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED130 0x2c88
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED131 0x2c89
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED132 0x2c8a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED133 0x2c8b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED134 0x2c8c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED135 0x2c8d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED136 0x2c8e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED137 0x2c8f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED138 0x2c90
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED139 0x2c91
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED140 0x2c92
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED141 0x2c93
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED142 0x2c94
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED143 0x2c95
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED144 0x2c96
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED145 0x2c97
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED146 0x2c98
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED147 0x2c99
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED148 0x2c9a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED149 0x2c9b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED150 0x2c9c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED151 0x2c9d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED152 0x2c9e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED153 0x2c9f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED154 0x2ca0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED155 0x2ca1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED156 0x2ca2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED157 0x2ca3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED158 0x2ca4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED159 0x2ca5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED160 0x2ca6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED160_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED161 0x2ca7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED161_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED162 0x2ca8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED162_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED163 0x2ca9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED163_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED164 0x2caa
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED164_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED165 0x2cab
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED165_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED166 0x2cac
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED166_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED167 0x2cad
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED167_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED168 0x2cae
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED168_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED169 0x2caf
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED169_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED170 0x2cb0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED170_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED171 0x2cb1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED171_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED172 0x2cb2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED172_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED173 0x2cb3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED173_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED174 0x2cb4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED174_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED175 0x2cb5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED175_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED176 0x2cb6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED176_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED177 0x2cb7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED177_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED178 0x2cb8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED178_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED179 0x2cb9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED179_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED180 0x2cba
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED180_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED181 0x2cbb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED181_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED182 0x2cbc
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED182_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED183 0x2cbd
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED183_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED184 0x2cbe
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED184_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED185 0x2cbf
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED185_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED186 0x2cc0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED186_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED187 0x2cc1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED187_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED188 0x2cc2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED188_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED189 0x2cc3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED189_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED190 0x2cc4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED190_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED191 0x2cc5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED191_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED192 0x2cc6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED192_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED193 0x2cc7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED193_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED194 0x2cc8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED194_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED195 0x2cc9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED195_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED196 0x2cca
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED196_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED197 0x2ccb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED197_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED198 0x2ccc
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED198_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED199 0x2ccd
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED199_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED200 0x2cce
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED200_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED201 0x2ccf
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED201_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED202 0x2cd0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED202_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED203 0x2cd1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED203_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED204 0x2cd2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED204_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED205 0x2cd3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED205_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED206 0x2cd4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED206_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED207 0x2cd5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED207_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED208 0x2cd6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED208_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED209 0x2cd7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED209_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED210 0x2cd8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED210_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED211 0x2cd9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED211_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED212 0x2cda
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED212_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED213 0x2cdb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED213_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED214 0x2cdc
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED214_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED215 0x2cdd
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED215_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED216 0x2cde
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED216_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED217 0x2cdf
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED217_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED218 0x2ce0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED218_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED219 0x2ce1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED219_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED220 0x2ce2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED220_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED221 0x2ce3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED221_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED222 0x2ce4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED222_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED223 0x2ce5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED223_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED224 0x2ce6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED224_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED225 0x2ce7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED225_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED226 0x2ce8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED226_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED227 0x2ce9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED227_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED228 0x2cea
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED228_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED229 0x2ceb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED229_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED230 0x2cec
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED230_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED231 0x2ced
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED231_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED232 0x2cee
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED232_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED233 0x2cef
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED233_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED234 0x2cf0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED234_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED235 0x2cf1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED235_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED236 0x2cf2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED236_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED237 0x2cf3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED237_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED238 0x2cf4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED238_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED239 0x2cf5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED239_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED240 0x2cf6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED240_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED241 0x2cf7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED241_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED242 0x2cf8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED242_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED243 0x2cf9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED243_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED244 0x2cfa
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED244_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED245 0x2cfb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED245_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED246 0x2cfc
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED246_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED247 0x2cfd
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED247_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED248 0x2cfe
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED248_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED249 0x2cff
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED249_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED250 0x2d00
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED250_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED251 0x2d01
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED251_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED252 0x2d02
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED252_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED253 0x2d03
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED253_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED254 0x2d04
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED254_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED255 0x2d05
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED255_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED256 0x2d06
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED256_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED257 0x2d07
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED257_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED258 0x2d08
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED258_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED259 0x2d09
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED259_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED260 0x2d0a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED260_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED261 0x2d0b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED261_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED262 0x2d0c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED262_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED263 0x2d0d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED263_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED264 0x2d0e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED264_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED265 0x2d0f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED265_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED266 0x2d10
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED266_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED267 0x2d11
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED267_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED268 0x2d12
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED268_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED269 0x2d13
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED269_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED270 0x2d14
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED270_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED271 0x2d15
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED271_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED272 0x2d16
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED272_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED273 0x2d17
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED273_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED274 0x2d18
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED274_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED275 0x2d19
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED275_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED276 0x2d1a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED276_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED277 0x2d1b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED277_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED278 0x2d1c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED278_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED279 0x2d1d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED279_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED280 0x2d1e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED280_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED281 0x2d1f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED281_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED282 0x2d20
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED282_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED283 0x2d21
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED283_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED284 0x2d22
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED284_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED285 0x2d23
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED285_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED286 0x2d24
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED286_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED287 0x2d25
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED287_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED288 0x2d26
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED288_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED289 0x2d27
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED289_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED290 0x2d28
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED290_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED291 0x2d29
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED291_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED292 0x2d2a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED292_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED293 0x2d2b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED293_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED294 0x2d2c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED294_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED295 0x2d2d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED295_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED296 0x2d2e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED296_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED297 0x2d2f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED297_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED298 0x2d30
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED298_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED299 0x2d31
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED299_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED300 0x2d32
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED300_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED301 0x2d33
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED301_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED302 0x2d34
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED302_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED303 0x2d35
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED303_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED304 0x2d36
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED304_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED305 0x2d37
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED305_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED306 0x2d38
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED306_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED307 0x2d39
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED307_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED308 0x2d3a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED308_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED309 0x2d3b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED309_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED310 0x2d3c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED310_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED311 0x2d3d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED311_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED312 0x2d3e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED312_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED313 0x2d3f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED313_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED314 0x2d40
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED314_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED315 0x2d41
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED315_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED316 0x2d42
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED316_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED317 0x2d43
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED317_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED318 0x2d44
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED318_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED319 0x2d45
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED319_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED320 0x2d46
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED320_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED321 0x2d47
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED321_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED322 0x2d48
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED322_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED323 0x2d49
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED323_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED324 0x2d4a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED324_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED325 0x2d4b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED325_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED326 0x2d4c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED326_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED327 0x2d4d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED327_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED328 0x2d4e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED328_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED329 0x2d4f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED329_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED330 0x2d50
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED330_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED331 0x2d51
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED331_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED332 0x2d52
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED332_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED333 0x2d53
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED333_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED334 0x2d54
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED334_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED335 0x2d55
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED335_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED336 0x2d56
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED336_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED337 0x2d57
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED337_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED338 0x2d58
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED338_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED339 0x2d59
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED339_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED340 0x2d5a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED340_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED341 0x2d5b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED341_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED342 0x2d5c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED342_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED343 0x2d5d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED343_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED344 0x2d5e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED344_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED345 0x2d5f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED345_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED346 0x2d60
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED346_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED347 0x2d61
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED347_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED348 0x2d62
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED348_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED349 0x2d63
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED349_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED350 0x2d64
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED350_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED351 0x2d65
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED351_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED352 0x2d66
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED352_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED353 0x2d67
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED353_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED354 0x2d68
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED354_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED355 0x2d69
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED355_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED356 0x2d6a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED356_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED357 0x2d6b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED357_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED358 0x2d6c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED358_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED359 0x2d6d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED359_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED360 0x2d6e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED360_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED361 0x2d6f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED361_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED362 0x2d70
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED362_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED363 0x2d71
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED363_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED364 0x2d72
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED364_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED365 0x2d73
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED365_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED366 0x2d74
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED366_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED367 0x2d75
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED367_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED368 0x2d76
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED368_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED369 0x2d77
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED369_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED370 0x2d78
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED370_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED371 0x2d79
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED371_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED372 0x2d7a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED372_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED373 0x2d7b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED373_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED374 0x2d7c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED374_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED375 0x2d7d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED375_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED376 0x2d7e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED376_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED377 0x2d7f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED377_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED378 0x2d80
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED378_BASE_IDX 2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED379 0x2d81
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED379_BASE_IDX 2
+#define mmI2S0_CNTL 0x2d82
+#define mmI2S0_CNTL_BASE_IDX 2
+#define mmSPDIF0_CNTL 0x2d83
+#define mmSPDIF0_CNTL_BASE_IDX 2
+#define mmI2S1_CNTL 0x2d84
+#define mmI2S1_CNTL_BASE_IDX 2
+#define mmSPDIF1_CNTL 0x2d85
+#define mmSPDIF1_CNTL_BASE_IDX 2
+#define mmI2S0_STATUS 0x2d86
+#define mmI2S0_STATUS_BASE_IDX 2
+#define mmI2S1_STATUS 0x2d87
+#define mmI2S1_STATUS_BASE_IDX 2
+#define mmI2S0_CRC_TEST_CNTL 0x2d8a
+#define mmI2S0_CRC_TEST_CNTL_BASE_IDX 2
+#define mmI2S0_CRC_TEST_DATA_01 0x2d8b
+#define mmI2S0_CRC_TEST_DATA_01_BASE_IDX 2
+#define mmI2S0_CRC_TEST_DATA_23 0x2d8c
+#define mmI2S0_CRC_TEST_DATA_23_BASE_IDX 2
+#define mmI2S1_CRC_TEST_CNTL 0x2d8d
+#define mmI2S1_CRC_TEST_CNTL_BASE_IDX 2
+#define mmI2S1_CRC_TEST_DATA_0 0x2d8e
+#define mmI2S1_CRC_TEST_DATA_0_BASE_IDX 2
+#define mmSPDIF0_CRC_TEST_CNTL 0x2d8f
+#define mmSPDIF0_CRC_TEST_CNTL_BASE_IDX 2
+#define mmSPDIF0_CRC_TEST_DATA_0 0x2d90
+#define mmSPDIF0_CRC_TEST_DATA_0_BASE_IDX 2
+#define mmSPDIF1_CRC_TEST_CNTL 0x2d91
+#define mmSPDIF1_CRC_TEST_CNTL_BASE_IDX 2
+#define mmSPDIF1_CRC_TEST_DATA 0x2d92
+#define mmSPDIF1_CRC_TEST_DATA_BASE_IDX 2
+#define mmCRC_I2S_CONT_REPEAT_NUM 0x2d93
+#define mmCRC_I2S_CONT_REPEAT_NUM_BASE_IDX 2
+#define mmCRC_SPDIF_CONT_REPEAT_NUM 0x2d94
+#define mmCRC_SPDIF_CONT_REPEAT_NUM_BASE_IDX 2
+#define mmZCAL_MACRO_CNTL_RESERVED0 0x2d96
+#define mmZCAL_MACRO_CNTL_RESERVED0_BASE_IDX 2
+#define mmZCAL_MACRO_CNTL_RESERVED1 0x2d97
+#define mmZCAL_MACRO_CNTL_RESERVED1_BASE_IDX 2
+#define mmZCAL_MACRO_CNTL_RESERVED2 0x2d98
+#define mmZCAL_MACRO_CNTL_RESERVED2_BASE_IDX 2
+#define mmZCAL_MACRO_CNTL_RESERVED3 0x2d99
+#define mmZCAL_MACRO_CNTL_RESERVED3_BASE_IDX 2
+#define mmZCAL_MACRO_CNTL_RESERVED4 0x2d9a
+#define mmZCAL_MACRO_CNTL_RESERVED4_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0stream0_dispdec
+// base address: 0x0
+#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x0458
+#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x0459
+#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0stream1_dispdec
+// base address: 0x8
+#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x045a
+#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x045b
+#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0stream2_dispdec
+// base address: 0x10
+#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x045c
+#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x045d
+#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0stream3_dispdec
+// base address: 0x18
+#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x045e
+#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x045f
+#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0stream4_dispdec
+// base address: 0x20
+#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0460
+#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0461
+#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0stream5_dispdec
+// base address: 0x28
+#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0462
+#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0463
+#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0stream6_dispdec
+// base address: 0x30
+#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x0464
+#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x0465
+#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0stream7_dispdec
+// base address: 0x38
+#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x0466
+#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x0467
+#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0endpoint0_dispdec
+// base address: 0x0
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0480
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0481
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0endpoint1_dispdec
+// base address: 0x18
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0486
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0487
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0endpoint2_dispdec
+// base address: 0x30
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x048c
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x048d
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0endpoint3_dispdec
+// base address: 0x48
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0492
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0493
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0endpoint4_dispdec
+// base address: 0x60
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0498
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0499
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0endpoint5_dispdec
+// base address: 0x78
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x049e
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x049f
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0endpoint6_dispdec
+// base address: 0x90
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x04a4
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x04a5
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0endpoint7_dispdec
+// base address: 0xa8
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x04aa
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x04ab
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0stream8_dispdec
+// base address: 0x320
+#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0520
+#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0521
+#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0stream9_dispdec
+// base address: 0x328
+#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0522
+#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0523
+#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0stream10_dispdec
+// base address: 0x330
+#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x0524
+#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x0525
+#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0stream11_dispdec
+// base address: 0x338
+#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x0526
+#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x0527
+#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0stream12_dispdec
+// base address: 0x340
+#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x0528
+#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x0529
+#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0stream13_dispdec
+// base address: 0x348
+#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x052a
+#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x052b
+#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0stream14_dispdec
+// base address: 0x350
+#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x052c
+#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x052d
+#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0stream15_dispdec
+// base address: 0x358
+#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x052e
+#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x052f
+#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0inputendpoint0_dispdec
+// base address: 0x0
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0534
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0535
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0inputendpoint1_dispdec
+// base address: 0x10
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0538
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0539
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0inputendpoint2_dispdec
+// base address: 0x20
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x053c
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x053d
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0inputendpoint3_dispdec
+// base address: 0x30
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0540
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0541
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0inputendpoint4_dispdec
+// base address: 0x40
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0544
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0545
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0inputendpoint5_dispdec
+// base address: 0x50
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0548
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0549
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0inputendpoint6_dispdec
+// base address: 0x60
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x054c
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x054d
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_azf0inputendpoint7_dispdec
+// base address: 0x70
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0550
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0551
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcp0_dispdec
+// base address: 0x0
+#define mmDCP0_GRPH_ENABLE 0x055a
+#define mmDCP0_GRPH_ENABLE_BASE_IDX 2
+#define mmDCP0_GRPH_CONTROL 0x055b
+#define mmDCP0_GRPH_CONTROL_BASE_IDX 2
+#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x055c
+#define mmDCP0_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
+#define mmDCP0_GRPH_SWAP_CNTL 0x055d
+#define mmDCP0_GRPH_SWAP_CNTL_BASE_IDX 2
+#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x055e
+#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x055f
+#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP0_GRPH_PITCH 0x0560
+#define mmDCP0_GRPH_PITCH_BASE_IDX 2
+#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0561
+#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0562
+#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x0563
+#define mmDCP0_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
+#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x0564
+#define mmDCP0_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
+#define mmDCP0_GRPH_X_START 0x0565
+#define mmDCP0_GRPH_X_START_BASE_IDX 2
+#define mmDCP0_GRPH_Y_START 0x0566
+#define mmDCP0_GRPH_Y_START_BASE_IDX 2
+#define mmDCP0_GRPH_X_END 0x0567
+#define mmDCP0_GRPH_X_END_BASE_IDX 2
+#define mmDCP0_GRPH_Y_END 0x0568
+#define mmDCP0_GRPH_Y_END_BASE_IDX 2
+#define mmDCP0_INPUT_GAMMA_CONTROL 0x0569
+#define mmDCP0_INPUT_GAMMA_CONTROL_BASE_IDX 2
+#define mmDCP0_GRPH_UPDATE 0x056a
+#define mmDCP0_GRPH_UPDATE_BASE_IDX 2
+#define mmDCP0_GRPH_FLIP_CONTROL 0x056b
+#define mmDCP0_GRPH_FLIP_CONTROL_BASE_IDX 2
+#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x056c
+#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
+#define mmDCP0_GRPH_DFQ_CONTROL 0x056d
+#define mmDCP0_GRPH_DFQ_CONTROL_BASE_IDX 2
+#define mmDCP0_GRPH_DFQ_STATUS 0x056e
+#define mmDCP0_GRPH_DFQ_STATUS_BASE_IDX 2
+#define mmDCP0_GRPH_INTERRUPT_STATUS 0x056f
+#define mmDCP0_GRPH_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x0570
+#define mmDCP0_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0571
+#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
+#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x0572
+#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP0_GRPH_COMPRESS_PITCH 0x0573
+#define mmDCP0_GRPH_COMPRESS_PITCH_BASE_IDX 2
+#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0574
+#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0575
+#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
+#define mmDCP0_PRESCALE_GRPH_CONTROL 0x0576
+#define mmDCP0_PRESCALE_GRPH_CONTROL_BASE_IDX 2
+#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x0577
+#define mmDCP0_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
+#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x0578
+#define mmDCP0_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
+#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x0579
+#define mmDCP0_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
+#define mmDCP0_INPUT_CSC_CONTROL 0x057a
+#define mmDCP0_INPUT_CSC_CONTROL_BASE_IDX 2
+#define mmDCP0_INPUT_CSC_C11_C12 0x057b
+#define mmDCP0_INPUT_CSC_C11_C12_BASE_IDX 2
+#define mmDCP0_INPUT_CSC_C13_C14 0x057c
+#define mmDCP0_INPUT_CSC_C13_C14_BASE_IDX 2
+#define mmDCP0_INPUT_CSC_C21_C22 0x057d
+#define mmDCP0_INPUT_CSC_C21_C22_BASE_IDX 2
+#define mmDCP0_INPUT_CSC_C23_C24 0x057e
+#define mmDCP0_INPUT_CSC_C23_C24_BASE_IDX 2
+#define mmDCP0_INPUT_CSC_C31_C32 0x057f
+#define mmDCP0_INPUT_CSC_C31_C32_BASE_IDX 2
+#define mmDCP0_INPUT_CSC_C33_C34 0x0580
+#define mmDCP0_INPUT_CSC_C33_C34_BASE_IDX 2
+#define mmDCP0_OUTPUT_CSC_CONTROL 0x0581
+#define mmDCP0_OUTPUT_CSC_CONTROL_BASE_IDX 2
+#define mmDCP0_OUTPUT_CSC_C11_C12 0x0582
+#define mmDCP0_OUTPUT_CSC_C11_C12_BASE_IDX 2
+#define mmDCP0_OUTPUT_CSC_C13_C14 0x0583
+#define mmDCP0_OUTPUT_CSC_C13_C14_BASE_IDX 2
+#define mmDCP0_OUTPUT_CSC_C21_C22 0x0584
+#define mmDCP0_OUTPUT_CSC_C21_C22_BASE_IDX 2
+#define mmDCP0_OUTPUT_CSC_C23_C24 0x0585
+#define mmDCP0_OUTPUT_CSC_C23_C24_BASE_IDX 2
+#define mmDCP0_OUTPUT_CSC_C31_C32 0x0586
+#define mmDCP0_OUTPUT_CSC_C31_C32_BASE_IDX 2
+#define mmDCP0_OUTPUT_CSC_C33_C34 0x0587
+#define mmDCP0_OUTPUT_CSC_C33_C34_BASE_IDX 2
+#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x0588
+#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
+#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x0589
+#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
+#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x058a
+#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
+#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x058b
+#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
+#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x058c
+#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
+#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x058d
+#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
+#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x058e
+#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
+#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x058f
+#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
+#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x0590
+#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
+#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x0591
+#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
+#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x0592
+#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
+#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x0593
+#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
+#define mmDCP0_DENORM_CONTROL 0x0594
+#define mmDCP0_DENORM_CONTROL_BASE_IDX 2
+#define mmDCP0_OUT_ROUND_CONTROL 0x0595
+#define mmDCP0_OUT_ROUND_CONTROL_BASE_IDX 2
+#define mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x0596
+#define mmDCP0_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
+#define mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x0597
+#define mmDCP0_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
+#define mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x0598
+#define mmDCP0_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
+#define mmDCP0_KEY_CONTROL 0x0599
+#define mmDCP0_KEY_CONTROL_BASE_IDX 2
+#define mmDCP0_KEY_RANGE_ALPHA 0x059a
+#define mmDCP0_KEY_RANGE_ALPHA_BASE_IDX 2
+#define mmDCP0_KEY_RANGE_RED 0x059b
+#define mmDCP0_KEY_RANGE_RED_BASE_IDX 2
+#define mmDCP0_KEY_RANGE_GREEN 0x059c
+#define mmDCP0_KEY_RANGE_GREEN_BASE_IDX 2
+#define mmDCP0_KEY_RANGE_BLUE 0x059d
+#define mmDCP0_KEY_RANGE_BLUE_BASE_IDX 2
+#define mmDCP0_DEGAMMA_CONTROL 0x059e
+#define mmDCP0_DEGAMMA_CONTROL_BASE_IDX 2
+#define mmDCP0_GAMUT_REMAP_CONTROL 0x059f
+#define mmDCP0_GAMUT_REMAP_CONTROL_BASE_IDX 2
+#define mmDCP0_GAMUT_REMAP_C11_C12 0x05a0
+#define mmDCP0_GAMUT_REMAP_C11_C12_BASE_IDX 2
+#define mmDCP0_GAMUT_REMAP_C13_C14 0x05a1
+#define mmDCP0_GAMUT_REMAP_C13_C14_BASE_IDX 2
+#define mmDCP0_GAMUT_REMAP_C21_C22 0x05a2
+#define mmDCP0_GAMUT_REMAP_C21_C22_BASE_IDX 2
+#define mmDCP0_GAMUT_REMAP_C23_C24 0x05a3
+#define mmDCP0_GAMUT_REMAP_C23_C24_BASE_IDX 2
+#define mmDCP0_GAMUT_REMAP_C31_C32 0x05a4
+#define mmDCP0_GAMUT_REMAP_C31_C32_BASE_IDX 2
+#define mmDCP0_GAMUT_REMAP_C33_C34 0x05a5
+#define mmDCP0_GAMUT_REMAP_C33_C34_BASE_IDX 2
+#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x05a6
+#define mmDCP0_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
+#define mmDCP0_DCP_RANDOM_SEEDS 0x05a7
+#define mmDCP0_DCP_RANDOM_SEEDS_BASE_IDX 2
+#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x05a8
+#define mmDCP0_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
+#define mmDCP0_CUR_CONTROL 0x05a9
+#define mmDCP0_CUR_CONTROL_BASE_IDX 2
+#define mmDCP0_CUR_SURFACE_ADDRESS 0x05aa
+#define mmDCP0_CUR_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP0_CUR_SIZE 0x05ab
+#define mmDCP0_CUR_SIZE_BASE_IDX 2
+#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x05ac
+#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP0_CUR_POSITION 0x05ad
+#define mmDCP0_CUR_POSITION_BASE_IDX 2
+#define mmDCP0_CUR_HOT_SPOT 0x05ae
+#define mmDCP0_CUR_HOT_SPOT_BASE_IDX 2
+#define mmDCP0_CUR_COLOR1 0x05af
+#define mmDCP0_CUR_COLOR1_BASE_IDX 2
+#define mmDCP0_CUR_COLOR2 0x05b0
+#define mmDCP0_CUR_COLOR2_BASE_IDX 2
+#define mmDCP0_CUR_UPDATE 0x05b1
+#define mmDCP0_CUR_UPDATE_BASE_IDX 2
+#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x05bb
+#define mmDCP0_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
+#define mmDCP0_CUR_STEREO_CONTROL 0x05bc
+#define mmDCP0_CUR_STEREO_CONTROL_BASE_IDX 2
+#define mmDCP0_DC_LUT_RW_MODE 0x05be
+#define mmDCP0_DC_LUT_RW_MODE_BASE_IDX 2
+#define mmDCP0_DC_LUT_RW_INDEX 0x05bf
+#define mmDCP0_DC_LUT_RW_INDEX_BASE_IDX 2
+#define mmDCP0_DC_LUT_SEQ_COLOR 0x05c0
+#define mmDCP0_DC_LUT_SEQ_COLOR_BASE_IDX 2
+#define mmDCP0_DC_LUT_PWL_DATA 0x05c1
+#define mmDCP0_DC_LUT_PWL_DATA_BASE_IDX 2
+#define mmDCP0_DC_LUT_30_COLOR 0x05c2
+#define mmDCP0_DC_LUT_30_COLOR_BASE_IDX 2
+#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x05c3
+#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
+#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x05c4
+#define mmDCP0_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmDCP0_DC_LUT_AUTOFILL 0x05c5
+#define mmDCP0_DC_LUT_AUTOFILL_BASE_IDX 2
+#define mmDCP0_DC_LUT_CONTROL 0x05c6
+#define mmDCP0_DC_LUT_CONTROL_BASE_IDX 2
+#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x05c7
+#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
+#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x05c8
+#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
+#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x05c9
+#define mmDCP0_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
+#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x05ca
+#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
+#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x05cb
+#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
+#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x05cc
+#define mmDCP0_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
+#define mmDCP0_DCP_CRC_CONTROL 0x05cd
+#define mmDCP0_DCP_CRC_CONTROL_BASE_IDX 2
+#define mmDCP0_DCP_CRC_MASK 0x05ce
+#define mmDCP0_DCP_CRC_MASK_BASE_IDX 2
+#define mmDCP0_DCP_CRC_CURRENT 0x05cf
+#define mmDCP0_DCP_CRC_CURRENT_BASE_IDX 2
+#define mmDCP0_DVMM_PTE_CONTROL 0x05d0
+#define mmDCP0_DVMM_PTE_CONTROL_BASE_IDX 2
+#define mmDCP0_DCP_CRC_LAST 0x05d1
+#define mmDCP0_DCP_CRC_LAST_BASE_IDX 2
+#define mmDCP0_DVMM_PTE_ARB_CONTROL 0x05d2
+#define mmDCP0_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
+#define mmDCP0_GRPH_FLIP_RATE_CNTL 0x05d4
+#define mmDCP0_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
+#define mmDCP0_DCP_GSL_CONTROL 0x05d5
+#define mmDCP0_DCP_GSL_CONTROL_BASE_IDX 2
+#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x05d6
+#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
+#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x05dc
+#define mmDCP0_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
+#define mmDCP0_HW_ROTATION 0x05de
+#define mmDCP0_HW_ROTATION_BASE_IDX 2
+#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x05df
+#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
+#define mmDCP0_REGAMMA_CONTROL 0x05e0
+#define mmDCP0_REGAMMA_CONTROL_BASE_IDX 2
+#define mmDCP0_REGAMMA_LUT_INDEX 0x05e1
+#define mmDCP0_REGAMMA_LUT_INDEX_BASE_IDX 2
+#define mmDCP0_REGAMMA_LUT_DATA 0x05e2
+#define mmDCP0_REGAMMA_LUT_DATA_BASE_IDX 2
+#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x05e3
+#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x05e4
+#define mmDCP0_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x05e5
+#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x05e6
+#define mmDCP0_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x05e7
+#define mmDCP0_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x05e8
+#define mmDCP0_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x05e9
+#define mmDCP0_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x05ea
+#define mmDCP0_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x05eb
+#define mmDCP0_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x05ec
+#define mmDCP0_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x05ed
+#define mmDCP0_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x05ee
+#define mmDCP0_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x05ef
+#define mmDCP0_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x05f0
+#define mmDCP0_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x05f1
+#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x05f2
+#define mmDCP0_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x05f3
+#define mmDCP0_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x05f4
+#define mmDCP0_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x05f5
+#define mmDCP0_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x05f6
+#define mmDCP0_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x05f7
+#define mmDCP0_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x05f8
+#define mmDCP0_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x05f9
+#define mmDCP0_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x05fa
+#define mmDCP0_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
+#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x05fb
+#define mmDCP0_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
+#define mmDCP0_ALPHA_CONTROL 0x05fc
+#define mmDCP0_ALPHA_CONTROL_BASE_IDX 2
+#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x05fd
+#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x05fe
+#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x05ff
+#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
+#define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT 0x0600
+#define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
+#define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY 0x0601
+#define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
+#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL 0x0602
+#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
+#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT 0x0603
+#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_lb0_dispdec
+// base address: 0x0
+#define mmLB0_LB_DATA_FORMAT 0x061a
+#define mmLB0_LB_DATA_FORMAT_BASE_IDX 2
+#define mmLB0_LB_MEMORY_CTRL 0x061b
+#define mmLB0_LB_MEMORY_CTRL_BASE_IDX 2
+#define mmLB0_LB_MEMORY_SIZE_STATUS 0x061c
+#define mmLB0_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
+#define mmLB0_LB_DESKTOP_HEIGHT 0x061d
+#define mmLB0_LB_DESKTOP_HEIGHT_BASE_IDX 2
+#define mmLB0_LB_VLINE_START_END 0x061e
+#define mmLB0_LB_VLINE_START_END_BASE_IDX 2
+#define mmLB0_LB_VLINE2_START_END 0x061f
+#define mmLB0_LB_VLINE2_START_END_BASE_IDX 2
+#define mmLB0_LB_V_COUNTER 0x0620
+#define mmLB0_LB_V_COUNTER_BASE_IDX 2
+#define mmLB0_LB_SNAPSHOT_V_COUNTER 0x0621
+#define mmLB0_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
+#define mmLB0_LB_INTERRUPT_MASK 0x0622
+#define mmLB0_LB_INTERRUPT_MASK_BASE_IDX 2
+#define mmLB0_LB_VLINE_STATUS 0x0623
+#define mmLB0_LB_VLINE_STATUS_BASE_IDX 2
+#define mmLB0_LB_VLINE2_STATUS 0x0624
+#define mmLB0_LB_VLINE2_STATUS_BASE_IDX 2
+#define mmLB0_LB_VBLANK_STATUS 0x0625
+#define mmLB0_LB_VBLANK_STATUS_BASE_IDX 2
+#define mmLB0_LB_SYNC_RESET_SEL 0x0626
+#define mmLB0_LB_SYNC_RESET_SEL_BASE_IDX 2
+#define mmLB0_LB_BLACK_KEYER_R_CR 0x0627
+#define mmLB0_LB_BLACK_KEYER_R_CR_BASE_IDX 2
+#define mmLB0_LB_BLACK_KEYER_G_Y 0x0628
+#define mmLB0_LB_BLACK_KEYER_G_Y_BASE_IDX 2
+#define mmLB0_LB_BLACK_KEYER_B_CB 0x0629
+#define mmLB0_LB_BLACK_KEYER_B_CB_BASE_IDX 2
+#define mmLB0_LB_KEYER_COLOR_CTRL 0x062a
+#define mmLB0_LB_KEYER_COLOR_CTRL_BASE_IDX 2
+#define mmLB0_LB_KEYER_COLOR_R_CR 0x062b
+#define mmLB0_LB_KEYER_COLOR_R_CR_BASE_IDX 2
+#define mmLB0_LB_KEYER_COLOR_G_Y 0x062c
+#define mmLB0_LB_KEYER_COLOR_G_Y_BASE_IDX 2
+#define mmLB0_LB_KEYER_COLOR_B_CB 0x062d
+#define mmLB0_LB_KEYER_COLOR_B_CB_BASE_IDX 2
+#define mmLB0_LB_KEYER_COLOR_REP_R_CR 0x062e
+#define mmLB0_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
+#define mmLB0_LB_KEYER_COLOR_REP_G_Y 0x062f
+#define mmLB0_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
+#define mmLB0_LB_KEYER_COLOR_REP_B_CB 0x0630
+#define mmLB0_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
+#define mmLB0_LB_BUFFER_LEVEL_STATUS 0x0631
+#define mmLB0_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
+#define mmLB0_LB_BUFFER_URGENCY_CTRL 0x0632
+#define mmLB0_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
+#define mmLB0_LB_BUFFER_URGENCY_STATUS 0x0633
+#define mmLB0_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
+#define mmLB0_LB_BUFFER_STATUS 0x0634
+#define mmLB0_LB_BUFFER_STATUS_BASE_IDX 2
+#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x0635
+#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
+#define mmLB0_MVP_AFR_FLIP_MODE 0x0636
+#define mmLB0_MVP_AFR_FLIP_MODE_BASE_IDX 2
+#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x0637
+#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
+#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x0638
+#define mmLB0_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
+#define mmLB0_DC_MVP_LB_CONTROL 0x0639
+#define mmLB0_DC_MVP_LB_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcfe0_dispdec
+// base address: 0x0
+#define mmDCFE0_DCFE_CLOCK_CONTROL 0x065a
+#define mmDCFE0_DCFE_CLOCK_CONTROL_BASE_IDX 2
+#define mmDCFE0_DCFE_SOFT_RESET 0x065b
+#define mmDCFE0_DCFE_SOFT_RESET_BASE_IDX 2
+#define mmDCFE0_DCFE_MEM_PWR_CTRL 0x065d
+#define mmDCFE0_DCFE_MEM_PWR_CTRL_BASE_IDX 2
+#define mmDCFE0_DCFE_MEM_PWR_CTRL2 0x065e
+#define mmDCFE0_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
+#define mmDCFE0_DCFE_MEM_PWR_STATUS 0x065f
+#define mmDCFE0_DCFE_MEM_PWR_STATUS_BASE_IDX 2
+#define mmDCFE0_DCFE_MISC 0x0660
+#define mmDCFE0_DCFE_MISC_BASE_IDX 2
+#define mmDCFE0_DCFE_FLUSH 0x0661
+#define mmDCFE0_DCFE_FLUSH_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_perfmon3_dispdec
+// base address: 0x1938
+#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x066e
+#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x066f
+#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x0670
+#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON3_PERFMON_CNTL 0x0671
+#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON3_PERFMON_CNTL2 0x0672
+#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x0673
+#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0674
+#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON3_PERFMON_HI 0x0675
+#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON3_PERFMON_LOW 0x0676
+#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dmif_pg0_dispdec
+// base address: 0x0
+#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x067a
+#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
+#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x067b
+#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
+#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x067c
+#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
+#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x067d
+#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
+#define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL 0x067e
+#define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
+#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x067f
+#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
+#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2 0x0680
+#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
+#define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL 0x0681
+#define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
+#define mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x0682
+#define mmDMIF_PG0_DPG_REPEATER_PROGRAM_BASE_IDX 2
+#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL 0x0686
+#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
+#define mmDMIF_PG0_DPG_DVMM_STATUS 0x0687
+#define mmDMIF_PG0_DPG_DVMM_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_scl0_dispdec
+// base address: 0x0
+#define mmSCL0_SCL_COEF_RAM_SELECT 0x069a
+#define mmSCL0_SCL_COEF_RAM_SELECT_BASE_IDX 2
+#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x069b
+#define mmSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
+#define mmSCL0_SCL_MODE 0x069c
+#define mmSCL0_SCL_MODE_BASE_IDX 2
+#define mmSCL0_SCL_TAP_CONTROL 0x069d
+#define mmSCL0_SCL_TAP_CONTROL_BASE_IDX 2
+#define mmSCL0_SCL_CONTROL 0x069e
+#define mmSCL0_SCL_CONTROL_BASE_IDX 2
+#define mmSCL0_SCL_BYPASS_CONTROL 0x069f
+#define mmSCL0_SCL_BYPASS_CONTROL_BASE_IDX 2
+#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x06a0
+#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x06a1
+#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
+#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x06a2
+#define mmSCL0_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
+#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x06a3
+#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmSCL0_SCL_HORZ_FILTER_INIT 0x06a4
+#define mmSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2
+#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x06a5
+#define mmSCL0_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
+#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x06a6
+#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmSCL0_SCL_VERT_FILTER_INIT 0x06a7
+#define mmSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2
+#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x06a8
+#define mmSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
+#define mmSCL0_SCL_ROUND_OFFSET 0x06a9
+#define mmSCL0_SCL_ROUND_OFFSET_BASE_IDX 2
+#define mmSCL0_SCL_UPDATE 0x06aa
+#define mmSCL0_SCL_UPDATE_BASE_IDX 2
+#define mmSCL0_SCL_F_SHARP_CONTROL 0x06ab
+#define mmSCL0_SCL_F_SHARP_CONTROL_BASE_IDX 2
+#define mmSCL0_SCL_ALU_CONTROL 0x06ac
+#define mmSCL0_SCL_ALU_CONTROL_BASE_IDX 2
+#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x06ad
+#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
+#define mmSCL0_VIEWPORT_START_SECONDARY 0x06ae
+#define mmSCL0_VIEWPORT_START_SECONDARY_BASE_IDX 2
+#define mmSCL0_VIEWPORT_START 0x06af
+#define mmSCL0_VIEWPORT_START_BASE_IDX 2
+#define mmSCL0_VIEWPORT_SIZE 0x06b0
+#define mmSCL0_VIEWPORT_SIZE_BASE_IDX 2
+#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x06b1
+#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x06b2
+#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+#define mmSCL0_SCL_MODE_CHANGE_DET1 0x06b3
+#define mmSCL0_SCL_MODE_CHANGE_DET1_BASE_IDX 2
+#define mmSCL0_SCL_MODE_CHANGE_DET2 0x06b4
+#define mmSCL0_SCL_MODE_CHANGE_DET2_BASE_IDX 2
+#define mmSCL0_SCL_MODE_CHANGE_DET3 0x06b5
+#define mmSCL0_SCL_MODE_CHANGE_DET3_BASE_IDX 2
+#define mmSCL0_SCL_MODE_CHANGE_MASK 0x06b6
+#define mmSCL0_SCL_MODE_CHANGE_MASK_BASE_IDX 2
+
+
+// addressBlock: dce_dc_blnd0_dispdec
+// base address: 0x0
+#define mmBLND0_BLND_CONTROL 0x06c7
+#define mmBLND0_BLND_CONTROL_BASE_IDX 2
+#define mmBLND0_BLND_SM_CONTROL2 0x06c8
+#define mmBLND0_BLND_SM_CONTROL2_BASE_IDX 2
+#define mmBLND0_BLND_CONTROL2 0x06c9
+#define mmBLND0_BLND_CONTROL2_BASE_IDX 2
+#define mmBLND0_BLND_UPDATE 0x06ca
+#define mmBLND0_BLND_UPDATE_BASE_IDX 2
+#define mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x06cb
+#define mmBLND0_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
+#define mmBLND0_BLND_V_UPDATE_LOCK 0x06cc
+#define mmBLND0_BLND_V_UPDATE_LOCK_BASE_IDX 2
+#define mmBLND0_BLND_REG_UPDATE_STATUS 0x06cd
+#define mmBLND0_BLND_REG_UPDATE_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_crtc0_dispdec
+// base address: 0x0
+#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x06d2
+#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
+#define mmCRTC0_CRTC_H_TOTAL 0x06d3
+#define mmCRTC0_CRTC_H_TOTAL_BASE_IDX 2
+#define mmCRTC0_CRTC_H_BLANK_START_END 0x06d4
+#define mmCRTC0_CRTC_H_BLANK_START_END_BASE_IDX 2
+#define mmCRTC0_CRTC_H_SYNC_A 0x06d5
+#define mmCRTC0_CRTC_H_SYNC_A_BASE_IDX 2
+#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x06d6
+#define mmCRTC0_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
+#define mmCRTC0_CRTC_H_SYNC_B 0x06d7
+#define mmCRTC0_CRTC_H_SYNC_B_BASE_IDX 2
+#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x06d8
+#define mmCRTC0_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
+#define mmCRTC0_CRTC_VBI_END 0x06d9
+#define mmCRTC0_CRTC_VBI_END_BASE_IDX 2
+#define mmCRTC0_CRTC_V_TOTAL 0x06da
+#define mmCRTC0_CRTC_V_TOTAL_BASE_IDX 2
+#define mmCRTC0_CRTC_V_TOTAL_MIN 0x06db
+#define mmCRTC0_CRTC_V_TOTAL_MIN_BASE_IDX 2
+#define mmCRTC0_CRTC_V_TOTAL_MAX 0x06dc
+#define mmCRTC0_CRTC_V_TOTAL_MAX_BASE_IDX 2
+#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x06dd
+#define mmCRTC0_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x06de
+#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
+#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x06df
+#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+#define mmCRTC0_CRTC_V_BLANK_START_END 0x06e0
+#define mmCRTC0_CRTC_V_BLANK_START_END_BASE_IDX 2
+#define mmCRTC0_CRTC_V_SYNC_A 0x06e1
+#define mmCRTC0_CRTC_V_SYNC_A_BASE_IDX 2
+#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x06e2
+#define mmCRTC0_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
+#define mmCRTC0_CRTC_V_SYNC_B 0x06e3
+#define mmCRTC0_CRTC_V_SYNC_B_BASE_IDX 2
+#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x06e4
+#define mmCRTC0_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
+#define mmCRTC0_CRTC_DTMTEST_CNTL 0x06e5
+#define mmCRTC0_CRTC_DTMTEST_CNTL_BASE_IDX 2
+#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x06e6
+#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
+#define mmCRTC0_CRTC_TRIGA_CNTL 0x06e7
+#define mmCRTC0_CRTC_TRIGA_CNTL_BASE_IDX 2
+#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x06e8
+#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
+#define mmCRTC0_CRTC_TRIGB_CNTL 0x06e9
+#define mmCRTC0_CRTC_TRIGB_CNTL_BASE_IDX 2
+#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x06ea
+#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
+#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x06eb
+#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+#define mmCRTC0_CRTC_FLOW_CONTROL 0x06ec
+#define mmCRTC0_CRTC_FLOW_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x06ed
+#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+#define mmCRTC0_CRTC_AVSYNC_COUNTER 0x06ee
+#define mmCRTC0_CRTC_AVSYNC_COUNTER_BASE_IDX 2
+#define mmCRTC0_CRTC_CONTROL 0x06ef
+#define mmCRTC0_CRTC_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_BLANK_CONTROL 0x06f0
+#define mmCRTC0_CRTC_BLANK_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x06f1
+#define mmCRTC0_CRTC_INTERLACE_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_INTERLACE_STATUS 0x06f2
+#define mmCRTC0_CRTC_INTERLACE_STATUS_BASE_IDX 2
+#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x06f3
+#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x06f4
+#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
+#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x06f5
+#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
+#define mmCRTC0_CRTC_STATUS 0x06f6
+#define mmCRTC0_CRTC_STATUS_BASE_IDX 2
+#define mmCRTC0_CRTC_STATUS_POSITION 0x06f7
+#define mmCRTC0_CRTC_STATUS_POSITION_BASE_IDX 2
+#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x06f8
+#define mmCRTC0_CRTC_NOM_VERT_POSITION_BASE_IDX 2
+#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x06f9
+#define mmCRTC0_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
+#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x06fa
+#define mmCRTC0_CRTC_STATUS_VF_COUNT_BASE_IDX 2
+#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x06fb
+#define mmCRTC0_CRTC_STATUS_HV_COUNT_BASE_IDX 2
+#define mmCRTC0_CRTC_COUNT_CONTROL 0x06fc
+#define mmCRTC0_CRTC_COUNT_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_COUNT_RESET 0x06fd
+#define mmCRTC0_CRTC_COUNT_RESET_BASE_IDX 2
+#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x06fe
+#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x06ff
+#define mmCRTC0_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_STEREO_STATUS 0x0700
+#define mmCRTC0_CRTC_STEREO_STATUS_BASE_IDX 2
+#define mmCRTC0_CRTC_STEREO_CONTROL 0x0701
+#define mmCRTC0_CRTC_STEREO_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x0702
+#define mmCRTC0_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
+#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x0703
+#define mmCRTC0_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x0704
+#define mmCRTC0_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
+#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x0705
+#define mmCRTC0_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
+#define mmCRTC0_CRTC_START_LINE_CONTROL 0x0706
+#define mmCRTC0_CRTC_START_LINE_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x0707
+#define mmCRTC0_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_UPDATE_LOCK 0x0708
+#define mmCRTC0_CRTC_UPDATE_LOCK_BASE_IDX 2
+#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x0709
+#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x070a
+#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
+#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x070b
+#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x070c
+#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
+#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x070d
+#define mmCRTC0_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
+#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK 0x070e
+#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
+#define mmCRTC0_CRTC_MASTER_UPDATE_MODE 0x070f
+#define mmCRTC0_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
+#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x0710
+#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
+#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0711
+#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
+#define mmCRTC0_CRTC_MVP_STATUS 0x0712
+#define mmCRTC0_CRTC_MVP_STATUS_BASE_IDX 2
+#define mmCRTC0_CRTC_MASTER_EN 0x0713
+#define mmCRTC0_CRTC_MASTER_EN_BASE_IDX 2
+#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x0714
+#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
+#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x0715
+#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
+#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x0717
+#define mmCRTC0_CRTC_OVERSCAN_COLOR_BASE_IDX 2
+#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x0718
+#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
+#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x0719
+#define mmCRTC0_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
+#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x071a
+#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+#define mmCRTC0_CRTC_BLACK_COLOR 0x071b
+#define mmCRTC0_CRTC_BLACK_COLOR_BASE_IDX 2
+#define mmCRTC0_CRTC_BLACK_COLOR_EXT 0x071c
+#define mmCRTC0_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x071d
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x071e
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x071f
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0720
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0721
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0722
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_CRC_CNTL 0x0723
+#define mmCRTC0_CRTC_CRC_CNTL_BASE_IDX 2
+#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x0724
+#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0725
+#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x0726
+#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0727
+#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_CRC0_DATA_RG 0x0728
+#define mmCRTC0_CRTC_CRC0_DATA_RG_BASE_IDX 2
+#define mmCRTC0_CRTC_CRC0_DATA_B 0x0729
+#define mmCRTC0_CRTC_CRC0_DATA_B_BASE_IDX 2
+#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x072a
+#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x072b
+#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x072c
+#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x072d
+#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_CRC1_DATA_RG 0x072e
+#define mmCRTC0_CRTC_CRC1_DATA_RG_BASE_IDX 2
+#define mmCRTC0_CRTC_CRC1_DATA_B 0x072f
+#define mmCRTC0_CRTC_CRC1_DATA_B_BASE_IDX 2
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x0730
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0731
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0732
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0733
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0734
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0735
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x0736
+#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x0737
+#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x0738
+#define mmCRTC0_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
+#define mmCRTC0_CRTC_GSL_WINDOW 0x0739
+#define mmCRTC0_CRTC_GSL_WINDOW_BASE_IDX 2
+#define mmCRTC0_CRTC_GSL_CONTROL 0x073a
+#define mmCRTC0_CRTC_GSL_CONTROL_BASE_IDX 2
+#define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS 0x073d
+#define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
+#define mmCRTC0_CRTC_DRR_CONTROL 0x073e
+#define mmCRTC0_CRTC_DRR_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_fmt0_dispdec
+// base address: 0x0
+#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x0742
+#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
+#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x0743
+#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
+#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x0744
+#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
+#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x0745
+#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
+#define mmFMT0_FMT_CONTROL 0x0746
+#define mmFMT0_FMT_CONTROL_BASE_IDX 2
+#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x0747
+#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
+#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x0748
+#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
+#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x0749
+#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
+#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x074a
+#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
+#define mmFMT0_FMT_CLAMP_CNTL 0x074e
+#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2
+#define mmFMT0_FMT_CRC_CNTL 0x074f
+#define mmFMT0_FMT_CRC_CNTL_BASE_IDX 2
+#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x0750
+#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
+#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0751
+#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
+#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x0752
+#define mmFMT0_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
+#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x0753
+#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
+#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0754
+#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
+#define mmFMT0_FMT_420_HBLANK_EARLY_START 0x0755
+#define mmFMT0_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcp1_dispdec
+// base address: 0x800
+#define mmDCP1_GRPH_ENABLE 0x075a
+#define mmDCP1_GRPH_ENABLE_BASE_IDX 2
+#define mmDCP1_GRPH_CONTROL 0x075b
+#define mmDCP1_GRPH_CONTROL_BASE_IDX 2
+#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x075c
+#define mmDCP1_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
+#define mmDCP1_GRPH_SWAP_CNTL 0x075d
+#define mmDCP1_GRPH_SWAP_CNTL_BASE_IDX 2
+#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x075e
+#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x075f
+#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP1_GRPH_PITCH 0x0760
+#define mmDCP1_GRPH_PITCH_BASE_IDX 2
+#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0761
+#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0762
+#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x0763
+#define mmDCP1_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
+#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x0764
+#define mmDCP1_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
+#define mmDCP1_GRPH_X_START 0x0765
+#define mmDCP1_GRPH_X_START_BASE_IDX 2
+#define mmDCP1_GRPH_Y_START 0x0766
+#define mmDCP1_GRPH_Y_START_BASE_IDX 2
+#define mmDCP1_GRPH_X_END 0x0767
+#define mmDCP1_GRPH_X_END_BASE_IDX 2
+#define mmDCP1_GRPH_Y_END 0x0768
+#define mmDCP1_GRPH_Y_END_BASE_IDX 2
+#define mmDCP1_INPUT_GAMMA_CONTROL 0x0769
+#define mmDCP1_INPUT_GAMMA_CONTROL_BASE_IDX 2
+#define mmDCP1_GRPH_UPDATE 0x076a
+#define mmDCP1_GRPH_UPDATE_BASE_IDX 2
+#define mmDCP1_GRPH_FLIP_CONTROL 0x076b
+#define mmDCP1_GRPH_FLIP_CONTROL_BASE_IDX 2
+#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x076c
+#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
+#define mmDCP1_GRPH_DFQ_CONTROL 0x076d
+#define mmDCP1_GRPH_DFQ_CONTROL_BASE_IDX 2
+#define mmDCP1_GRPH_DFQ_STATUS 0x076e
+#define mmDCP1_GRPH_DFQ_STATUS_BASE_IDX 2
+#define mmDCP1_GRPH_INTERRUPT_STATUS 0x076f
+#define mmDCP1_GRPH_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x0770
+#define mmDCP1_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0771
+#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
+#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x0772
+#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP1_GRPH_COMPRESS_PITCH 0x0773
+#define mmDCP1_GRPH_COMPRESS_PITCH_BASE_IDX 2
+#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0774
+#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0775
+#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
+#define mmDCP1_PRESCALE_GRPH_CONTROL 0x0776
+#define mmDCP1_PRESCALE_GRPH_CONTROL_BASE_IDX 2
+#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x0777
+#define mmDCP1_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
+#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x0778
+#define mmDCP1_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
+#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x0779
+#define mmDCP1_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
+#define mmDCP1_INPUT_CSC_CONTROL 0x077a
+#define mmDCP1_INPUT_CSC_CONTROL_BASE_IDX 2
+#define mmDCP1_INPUT_CSC_C11_C12 0x077b
+#define mmDCP1_INPUT_CSC_C11_C12_BASE_IDX 2
+#define mmDCP1_INPUT_CSC_C13_C14 0x077c
+#define mmDCP1_INPUT_CSC_C13_C14_BASE_IDX 2
+#define mmDCP1_INPUT_CSC_C21_C22 0x077d
+#define mmDCP1_INPUT_CSC_C21_C22_BASE_IDX 2
+#define mmDCP1_INPUT_CSC_C23_C24 0x077e
+#define mmDCP1_INPUT_CSC_C23_C24_BASE_IDX 2
+#define mmDCP1_INPUT_CSC_C31_C32 0x077f
+#define mmDCP1_INPUT_CSC_C31_C32_BASE_IDX 2
+#define mmDCP1_INPUT_CSC_C33_C34 0x0780
+#define mmDCP1_INPUT_CSC_C33_C34_BASE_IDX 2
+#define mmDCP1_OUTPUT_CSC_CONTROL 0x0781
+#define mmDCP1_OUTPUT_CSC_CONTROL_BASE_IDX 2
+#define mmDCP1_OUTPUT_CSC_C11_C12 0x0782
+#define mmDCP1_OUTPUT_CSC_C11_C12_BASE_IDX 2
+#define mmDCP1_OUTPUT_CSC_C13_C14 0x0783
+#define mmDCP1_OUTPUT_CSC_C13_C14_BASE_IDX 2
+#define mmDCP1_OUTPUT_CSC_C21_C22 0x0784
+#define mmDCP1_OUTPUT_CSC_C21_C22_BASE_IDX 2
+#define mmDCP1_OUTPUT_CSC_C23_C24 0x0785
+#define mmDCP1_OUTPUT_CSC_C23_C24_BASE_IDX 2
+#define mmDCP1_OUTPUT_CSC_C31_C32 0x0786
+#define mmDCP1_OUTPUT_CSC_C31_C32_BASE_IDX 2
+#define mmDCP1_OUTPUT_CSC_C33_C34 0x0787
+#define mmDCP1_OUTPUT_CSC_C33_C34_BASE_IDX 2
+#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x0788
+#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
+#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x0789
+#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
+#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x078a
+#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
+#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x078b
+#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
+#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x078c
+#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
+#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x078d
+#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
+#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x078e
+#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
+#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x078f
+#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
+#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x0790
+#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
+#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x0791
+#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
+#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x0792
+#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
+#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x0793
+#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
+#define mmDCP1_DENORM_CONTROL 0x0794
+#define mmDCP1_DENORM_CONTROL_BASE_IDX 2
+#define mmDCP1_OUT_ROUND_CONTROL 0x0795
+#define mmDCP1_OUT_ROUND_CONTROL_BASE_IDX 2
+#define mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x0796
+#define mmDCP1_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
+#define mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x0797
+#define mmDCP1_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
+#define mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x0798
+#define mmDCP1_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
+#define mmDCP1_KEY_CONTROL 0x0799
+#define mmDCP1_KEY_CONTROL_BASE_IDX 2
+#define mmDCP1_KEY_RANGE_ALPHA 0x079a
+#define mmDCP1_KEY_RANGE_ALPHA_BASE_IDX 2
+#define mmDCP1_KEY_RANGE_RED 0x079b
+#define mmDCP1_KEY_RANGE_RED_BASE_IDX 2
+#define mmDCP1_KEY_RANGE_GREEN 0x079c
+#define mmDCP1_KEY_RANGE_GREEN_BASE_IDX 2
+#define mmDCP1_KEY_RANGE_BLUE 0x079d
+#define mmDCP1_KEY_RANGE_BLUE_BASE_IDX 2
+#define mmDCP1_DEGAMMA_CONTROL 0x079e
+#define mmDCP1_DEGAMMA_CONTROL_BASE_IDX 2
+#define mmDCP1_GAMUT_REMAP_CONTROL 0x079f
+#define mmDCP1_GAMUT_REMAP_CONTROL_BASE_IDX 2
+#define mmDCP1_GAMUT_REMAP_C11_C12 0x07a0
+#define mmDCP1_GAMUT_REMAP_C11_C12_BASE_IDX 2
+#define mmDCP1_GAMUT_REMAP_C13_C14 0x07a1
+#define mmDCP1_GAMUT_REMAP_C13_C14_BASE_IDX 2
+#define mmDCP1_GAMUT_REMAP_C21_C22 0x07a2
+#define mmDCP1_GAMUT_REMAP_C21_C22_BASE_IDX 2
+#define mmDCP1_GAMUT_REMAP_C23_C24 0x07a3
+#define mmDCP1_GAMUT_REMAP_C23_C24_BASE_IDX 2
+#define mmDCP1_GAMUT_REMAP_C31_C32 0x07a4
+#define mmDCP1_GAMUT_REMAP_C31_C32_BASE_IDX 2
+#define mmDCP1_GAMUT_REMAP_C33_C34 0x07a5
+#define mmDCP1_GAMUT_REMAP_C33_C34_BASE_IDX 2
+#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x07a6
+#define mmDCP1_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
+#define mmDCP1_DCP_RANDOM_SEEDS 0x07a7
+#define mmDCP1_DCP_RANDOM_SEEDS_BASE_IDX 2
+#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x07a8
+#define mmDCP1_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
+#define mmDCP1_CUR_CONTROL 0x07a9
+#define mmDCP1_CUR_CONTROL_BASE_IDX 2
+#define mmDCP1_CUR_SURFACE_ADDRESS 0x07aa
+#define mmDCP1_CUR_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP1_CUR_SIZE 0x07ab
+#define mmDCP1_CUR_SIZE_BASE_IDX 2
+#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x07ac
+#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP1_CUR_POSITION 0x07ad
+#define mmDCP1_CUR_POSITION_BASE_IDX 2
+#define mmDCP1_CUR_HOT_SPOT 0x07ae
+#define mmDCP1_CUR_HOT_SPOT_BASE_IDX 2
+#define mmDCP1_CUR_COLOR1 0x07af
+#define mmDCP1_CUR_COLOR1_BASE_IDX 2
+#define mmDCP1_CUR_COLOR2 0x07b0
+#define mmDCP1_CUR_COLOR2_BASE_IDX 2
+#define mmDCP1_CUR_UPDATE 0x07b1
+#define mmDCP1_CUR_UPDATE_BASE_IDX 2
+#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x07bb
+#define mmDCP1_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
+#define mmDCP1_CUR_STEREO_CONTROL 0x07bc
+#define mmDCP1_CUR_STEREO_CONTROL_BASE_IDX 2
+#define mmDCP1_DC_LUT_RW_MODE 0x07be
+#define mmDCP1_DC_LUT_RW_MODE_BASE_IDX 2
+#define mmDCP1_DC_LUT_RW_INDEX 0x07bf
+#define mmDCP1_DC_LUT_RW_INDEX_BASE_IDX 2
+#define mmDCP1_DC_LUT_SEQ_COLOR 0x07c0
+#define mmDCP1_DC_LUT_SEQ_COLOR_BASE_IDX 2
+#define mmDCP1_DC_LUT_PWL_DATA 0x07c1
+#define mmDCP1_DC_LUT_PWL_DATA_BASE_IDX 2
+#define mmDCP1_DC_LUT_30_COLOR 0x07c2
+#define mmDCP1_DC_LUT_30_COLOR_BASE_IDX 2
+#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x07c3
+#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
+#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x07c4
+#define mmDCP1_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmDCP1_DC_LUT_AUTOFILL 0x07c5
+#define mmDCP1_DC_LUT_AUTOFILL_BASE_IDX 2
+#define mmDCP1_DC_LUT_CONTROL 0x07c6
+#define mmDCP1_DC_LUT_CONTROL_BASE_IDX 2
+#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x07c7
+#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
+#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x07c8
+#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
+#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x07c9
+#define mmDCP1_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
+#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x07ca
+#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
+#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x07cb
+#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
+#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x07cc
+#define mmDCP1_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
+#define mmDCP1_DCP_CRC_CONTROL 0x07cd
+#define mmDCP1_DCP_CRC_CONTROL_BASE_IDX 2
+#define mmDCP1_DCP_CRC_MASK 0x07ce
+#define mmDCP1_DCP_CRC_MASK_BASE_IDX 2
+#define mmDCP1_DCP_CRC_CURRENT 0x07cf
+#define mmDCP1_DCP_CRC_CURRENT_BASE_IDX 2
+#define mmDCP1_DVMM_PTE_CONTROL 0x07d0
+#define mmDCP1_DVMM_PTE_CONTROL_BASE_IDX 2
+#define mmDCP1_DCP_CRC_LAST 0x07d1
+#define mmDCP1_DCP_CRC_LAST_BASE_IDX 2
+#define mmDCP1_DVMM_PTE_ARB_CONTROL 0x07d2
+#define mmDCP1_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
+#define mmDCP1_GRPH_FLIP_RATE_CNTL 0x07d4
+#define mmDCP1_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
+#define mmDCP1_DCP_GSL_CONTROL 0x07d5
+#define mmDCP1_DCP_GSL_CONTROL_BASE_IDX 2
+#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x07d6
+#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
+#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x07dc
+#define mmDCP1_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
+#define mmDCP1_HW_ROTATION 0x07de
+#define mmDCP1_HW_ROTATION_BASE_IDX 2
+#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x07df
+#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
+#define mmDCP1_REGAMMA_CONTROL 0x07e0
+#define mmDCP1_REGAMMA_CONTROL_BASE_IDX 2
+#define mmDCP1_REGAMMA_LUT_INDEX 0x07e1
+#define mmDCP1_REGAMMA_LUT_INDEX_BASE_IDX 2
+#define mmDCP1_REGAMMA_LUT_DATA 0x07e2
+#define mmDCP1_REGAMMA_LUT_DATA_BASE_IDX 2
+#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x07e3
+#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x07e4
+#define mmDCP1_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x07e5
+#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x07e6
+#define mmDCP1_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x07e7
+#define mmDCP1_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x07e8
+#define mmDCP1_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x07e9
+#define mmDCP1_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x07ea
+#define mmDCP1_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x07eb
+#define mmDCP1_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x07ec
+#define mmDCP1_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x07ed
+#define mmDCP1_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x07ee
+#define mmDCP1_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x07ef
+#define mmDCP1_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x07f0
+#define mmDCP1_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x07f1
+#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x07f2
+#define mmDCP1_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x07f3
+#define mmDCP1_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x07f4
+#define mmDCP1_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x07f5
+#define mmDCP1_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x07f6
+#define mmDCP1_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x07f7
+#define mmDCP1_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x07f8
+#define mmDCP1_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x07f9
+#define mmDCP1_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x07fa
+#define mmDCP1_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
+#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x07fb
+#define mmDCP1_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
+#define mmDCP1_ALPHA_CONTROL 0x07fc
+#define mmDCP1_ALPHA_CONTROL_BASE_IDX 2
+#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x07fd
+#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x07fe
+#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x07ff
+#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
+#define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT 0x0800
+#define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
+#define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY 0x0801
+#define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
+#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL 0x0802
+#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
+#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT 0x0803
+#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_lb1_dispdec
+// base address: 0x800
+#define mmLB1_LB_DATA_FORMAT 0x081a
+#define mmLB1_LB_DATA_FORMAT_BASE_IDX 2
+#define mmLB1_LB_MEMORY_CTRL 0x081b
+#define mmLB1_LB_MEMORY_CTRL_BASE_IDX 2
+#define mmLB1_LB_MEMORY_SIZE_STATUS 0x081c
+#define mmLB1_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
+#define mmLB1_LB_DESKTOP_HEIGHT 0x081d
+#define mmLB1_LB_DESKTOP_HEIGHT_BASE_IDX 2
+#define mmLB1_LB_VLINE_START_END 0x081e
+#define mmLB1_LB_VLINE_START_END_BASE_IDX 2
+#define mmLB1_LB_VLINE2_START_END 0x081f
+#define mmLB1_LB_VLINE2_START_END_BASE_IDX 2
+#define mmLB1_LB_V_COUNTER 0x0820
+#define mmLB1_LB_V_COUNTER_BASE_IDX 2
+#define mmLB1_LB_SNAPSHOT_V_COUNTER 0x0821
+#define mmLB1_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
+#define mmLB1_LB_INTERRUPT_MASK 0x0822
+#define mmLB1_LB_INTERRUPT_MASK_BASE_IDX 2
+#define mmLB1_LB_VLINE_STATUS 0x0823
+#define mmLB1_LB_VLINE_STATUS_BASE_IDX 2
+#define mmLB1_LB_VLINE2_STATUS 0x0824
+#define mmLB1_LB_VLINE2_STATUS_BASE_IDX 2
+#define mmLB1_LB_VBLANK_STATUS 0x0825
+#define mmLB1_LB_VBLANK_STATUS_BASE_IDX 2
+#define mmLB1_LB_SYNC_RESET_SEL 0x0826
+#define mmLB1_LB_SYNC_RESET_SEL_BASE_IDX 2
+#define mmLB1_LB_BLACK_KEYER_R_CR 0x0827
+#define mmLB1_LB_BLACK_KEYER_R_CR_BASE_IDX 2
+#define mmLB1_LB_BLACK_KEYER_G_Y 0x0828
+#define mmLB1_LB_BLACK_KEYER_G_Y_BASE_IDX 2
+#define mmLB1_LB_BLACK_KEYER_B_CB 0x0829
+#define mmLB1_LB_BLACK_KEYER_B_CB_BASE_IDX 2
+#define mmLB1_LB_KEYER_COLOR_CTRL 0x082a
+#define mmLB1_LB_KEYER_COLOR_CTRL_BASE_IDX 2
+#define mmLB1_LB_KEYER_COLOR_R_CR 0x082b
+#define mmLB1_LB_KEYER_COLOR_R_CR_BASE_IDX 2
+#define mmLB1_LB_KEYER_COLOR_G_Y 0x082c
+#define mmLB1_LB_KEYER_COLOR_G_Y_BASE_IDX 2
+#define mmLB1_LB_KEYER_COLOR_B_CB 0x082d
+#define mmLB1_LB_KEYER_COLOR_B_CB_BASE_IDX 2
+#define mmLB1_LB_KEYER_COLOR_REP_R_CR 0x082e
+#define mmLB1_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
+#define mmLB1_LB_KEYER_COLOR_REP_G_Y 0x082f
+#define mmLB1_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
+#define mmLB1_LB_KEYER_COLOR_REP_B_CB 0x0830
+#define mmLB1_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
+#define mmLB1_LB_BUFFER_LEVEL_STATUS 0x0831
+#define mmLB1_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
+#define mmLB1_LB_BUFFER_URGENCY_CTRL 0x0832
+#define mmLB1_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
+#define mmLB1_LB_BUFFER_URGENCY_STATUS 0x0833
+#define mmLB1_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
+#define mmLB1_LB_BUFFER_STATUS 0x0834
+#define mmLB1_LB_BUFFER_STATUS_BASE_IDX 2
+#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x0835
+#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
+#define mmLB1_MVP_AFR_FLIP_MODE 0x0836
+#define mmLB1_MVP_AFR_FLIP_MODE_BASE_IDX 2
+#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x0837
+#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
+#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x0838
+#define mmLB1_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
+#define mmLB1_DC_MVP_LB_CONTROL 0x0839
+#define mmLB1_DC_MVP_LB_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcfe1_dispdec
+// base address: 0x800
+#define mmDCFE1_DCFE_CLOCK_CONTROL 0x085a
+#define mmDCFE1_DCFE_CLOCK_CONTROL_BASE_IDX 2
+#define mmDCFE1_DCFE_SOFT_RESET 0x085b
+#define mmDCFE1_DCFE_SOFT_RESET_BASE_IDX 2
+#define mmDCFE1_DCFE_MEM_PWR_CTRL 0x085d
+#define mmDCFE1_DCFE_MEM_PWR_CTRL_BASE_IDX 2
+#define mmDCFE1_DCFE_MEM_PWR_CTRL2 0x085e
+#define mmDCFE1_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
+#define mmDCFE1_DCFE_MEM_PWR_STATUS 0x085f
+#define mmDCFE1_DCFE_MEM_PWR_STATUS_BASE_IDX 2
+#define mmDCFE1_DCFE_MISC 0x0860
+#define mmDCFE1_DCFE_MISC_BASE_IDX 2
+#define mmDCFE1_DCFE_FLUSH 0x0861
+#define mmDCFE1_DCFE_FLUSH_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_perfmon4_dispdec
+// base address: 0x2138
+#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x086e
+#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x086f
+#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x0870
+#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON4_PERFMON_CNTL 0x0871
+#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON4_PERFMON_CNTL2 0x0872
+#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0873
+#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x0874
+#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON4_PERFMON_HI 0x0875
+#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON4_PERFMON_LOW 0x0876
+#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dmif_pg1_dispdec
+// base address: 0x800
+#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x087a
+#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
+#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x087b
+#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
+#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x087c
+#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
+#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x087d
+#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
+#define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL 0x087e
+#define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
+#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x087f
+#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
+#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2 0x0880
+#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
+#define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL 0x0881
+#define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
+#define mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x0882
+#define mmDMIF_PG1_DPG_REPEATER_PROGRAM_BASE_IDX 2
+#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL 0x0886
+#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
+#define mmDMIF_PG1_DPG_DVMM_STATUS 0x0887
+#define mmDMIF_PG1_DPG_DVMM_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_scl1_dispdec
+// base address: 0x800
+#define mmSCL1_SCL_COEF_RAM_SELECT 0x089a
+#define mmSCL1_SCL_COEF_RAM_SELECT_BASE_IDX 2
+#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x089b
+#define mmSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
+#define mmSCL1_SCL_MODE 0x089c
+#define mmSCL1_SCL_MODE_BASE_IDX 2
+#define mmSCL1_SCL_TAP_CONTROL 0x089d
+#define mmSCL1_SCL_TAP_CONTROL_BASE_IDX 2
+#define mmSCL1_SCL_CONTROL 0x089e
+#define mmSCL1_SCL_CONTROL_BASE_IDX 2
+#define mmSCL1_SCL_BYPASS_CONTROL 0x089f
+#define mmSCL1_SCL_BYPASS_CONTROL_BASE_IDX 2
+#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x08a0
+#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x08a1
+#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
+#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x08a2
+#define mmSCL1_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
+#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x08a3
+#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmSCL1_SCL_HORZ_FILTER_INIT 0x08a4
+#define mmSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2
+#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x08a5
+#define mmSCL1_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
+#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x08a6
+#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmSCL1_SCL_VERT_FILTER_INIT 0x08a7
+#define mmSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2
+#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x08a8
+#define mmSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
+#define mmSCL1_SCL_ROUND_OFFSET 0x08a9
+#define mmSCL1_SCL_ROUND_OFFSET_BASE_IDX 2
+#define mmSCL1_SCL_UPDATE 0x08aa
+#define mmSCL1_SCL_UPDATE_BASE_IDX 2
+#define mmSCL1_SCL_F_SHARP_CONTROL 0x08ab
+#define mmSCL1_SCL_F_SHARP_CONTROL_BASE_IDX 2
+#define mmSCL1_SCL_ALU_CONTROL 0x08ac
+#define mmSCL1_SCL_ALU_CONTROL_BASE_IDX 2
+#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x08ad
+#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
+#define mmSCL1_VIEWPORT_START_SECONDARY 0x08ae
+#define mmSCL1_VIEWPORT_START_SECONDARY_BASE_IDX 2
+#define mmSCL1_VIEWPORT_START 0x08af
+#define mmSCL1_VIEWPORT_START_BASE_IDX 2
+#define mmSCL1_VIEWPORT_SIZE 0x08b0
+#define mmSCL1_VIEWPORT_SIZE_BASE_IDX 2
+#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x08b1
+#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x08b2
+#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+#define mmSCL1_SCL_MODE_CHANGE_DET1 0x08b3
+#define mmSCL1_SCL_MODE_CHANGE_DET1_BASE_IDX 2
+#define mmSCL1_SCL_MODE_CHANGE_DET2 0x08b4
+#define mmSCL1_SCL_MODE_CHANGE_DET2_BASE_IDX 2
+#define mmSCL1_SCL_MODE_CHANGE_DET3 0x08b5
+#define mmSCL1_SCL_MODE_CHANGE_DET3_BASE_IDX 2
+#define mmSCL1_SCL_MODE_CHANGE_MASK 0x08b6
+#define mmSCL1_SCL_MODE_CHANGE_MASK_BASE_IDX 2
+
+
+// addressBlock: dce_dc_blnd1_dispdec
+// base address: 0x800
+#define mmBLND1_BLND_CONTROL 0x08c7
+#define mmBLND1_BLND_CONTROL_BASE_IDX 2
+#define mmBLND1_BLND_SM_CONTROL2 0x08c8
+#define mmBLND1_BLND_SM_CONTROL2_BASE_IDX 2
+#define mmBLND1_BLND_CONTROL2 0x08c9
+#define mmBLND1_BLND_CONTROL2_BASE_IDX 2
+#define mmBLND1_BLND_UPDATE 0x08ca
+#define mmBLND1_BLND_UPDATE_BASE_IDX 2
+#define mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x08cb
+#define mmBLND1_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
+#define mmBLND1_BLND_V_UPDATE_LOCK 0x08cc
+#define mmBLND1_BLND_V_UPDATE_LOCK_BASE_IDX 2
+#define mmBLND1_BLND_REG_UPDATE_STATUS 0x08cd
+#define mmBLND1_BLND_REG_UPDATE_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_crtc1_dispdec
+// base address: 0x800
+#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x08d2
+#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
+#define mmCRTC1_CRTC_H_TOTAL 0x08d3
+#define mmCRTC1_CRTC_H_TOTAL_BASE_IDX 2
+#define mmCRTC1_CRTC_H_BLANK_START_END 0x08d4
+#define mmCRTC1_CRTC_H_BLANK_START_END_BASE_IDX 2
+#define mmCRTC1_CRTC_H_SYNC_A 0x08d5
+#define mmCRTC1_CRTC_H_SYNC_A_BASE_IDX 2
+#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x08d6
+#define mmCRTC1_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
+#define mmCRTC1_CRTC_H_SYNC_B 0x08d7
+#define mmCRTC1_CRTC_H_SYNC_B_BASE_IDX 2
+#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x08d8
+#define mmCRTC1_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
+#define mmCRTC1_CRTC_VBI_END 0x08d9
+#define mmCRTC1_CRTC_VBI_END_BASE_IDX 2
+#define mmCRTC1_CRTC_V_TOTAL 0x08da
+#define mmCRTC1_CRTC_V_TOTAL_BASE_IDX 2
+#define mmCRTC1_CRTC_V_TOTAL_MIN 0x08db
+#define mmCRTC1_CRTC_V_TOTAL_MIN_BASE_IDX 2
+#define mmCRTC1_CRTC_V_TOTAL_MAX 0x08dc
+#define mmCRTC1_CRTC_V_TOTAL_MAX_BASE_IDX 2
+#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x08dd
+#define mmCRTC1_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x08de
+#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
+#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x08df
+#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+#define mmCRTC1_CRTC_V_BLANK_START_END 0x08e0
+#define mmCRTC1_CRTC_V_BLANK_START_END_BASE_IDX 2
+#define mmCRTC1_CRTC_V_SYNC_A 0x08e1
+#define mmCRTC1_CRTC_V_SYNC_A_BASE_IDX 2
+#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x08e2
+#define mmCRTC1_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
+#define mmCRTC1_CRTC_V_SYNC_B 0x08e3
+#define mmCRTC1_CRTC_V_SYNC_B_BASE_IDX 2
+#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x08e4
+#define mmCRTC1_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
+#define mmCRTC1_CRTC_DTMTEST_CNTL 0x08e5
+#define mmCRTC1_CRTC_DTMTEST_CNTL_BASE_IDX 2
+#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x08e6
+#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
+#define mmCRTC1_CRTC_TRIGA_CNTL 0x08e7
+#define mmCRTC1_CRTC_TRIGA_CNTL_BASE_IDX 2
+#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x08e8
+#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
+#define mmCRTC1_CRTC_TRIGB_CNTL 0x08e9
+#define mmCRTC1_CRTC_TRIGB_CNTL_BASE_IDX 2
+#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x08ea
+#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
+#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x08eb
+#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+#define mmCRTC1_CRTC_FLOW_CONTROL 0x08ec
+#define mmCRTC1_CRTC_FLOW_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x08ed
+#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+#define mmCRTC1_CRTC_AVSYNC_COUNTER 0x08ee
+#define mmCRTC1_CRTC_AVSYNC_COUNTER_BASE_IDX 2
+#define mmCRTC1_CRTC_CONTROL 0x08ef
+#define mmCRTC1_CRTC_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_BLANK_CONTROL 0x08f0
+#define mmCRTC1_CRTC_BLANK_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x08f1
+#define mmCRTC1_CRTC_INTERLACE_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_INTERLACE_STATUS 0x08f2
+#define mmCRTC1_CRTC_INTERLACE_STATUS_BASE_IDX 2
+#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x08f3
+#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x08f4
+#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
+#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x08f5
+#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
+#define mmCRTC1_CRTC_STATUS 0x08f6
+#define mmCRTC1_CRTC_STATUS_BASE_IDX 2
+#define mmCRTC1_CRTC_STATUS_POSITION 0x08f7
+#define mmCRTC1_CRTC_STATUS_POSITION_BASE_IDX 2
+#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x08f8
+#define mmCRTC1_CRTC_NOM_VERT_POSITION_BASE_IDX 2
+#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x08f9
+#define mmCRTC1_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
+#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x08fa
+#define mmCRTC1_CRTC_STATUS_VF_COUNT_BASE_IDX 2
+#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x08fb
+#define mmCRTC1_CRTC_STATUS_HV_COUNT_BASE_IDX 2
+#define mmCRTC1_CRTC_COUNT_CONTROL 0x08fc
+#define mmCRTC1_CRTC_COUNT_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_COUNT_RESET 0x08fd
+#define mmCRTC1_CRTC_COUNT_RESET_BASE_IDX 2
+#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x08fe
+#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x08ff
+#define mmCRTC1_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_STEREO_STATUS 0x0900
+#define mmCRTC1_CRTC_STEREO_STATUS_BASE_IDX 2
+#define mmCRTC1_CRTC_STEREO_CONTROL 0x0901
+#define mmCRTC1_CRTC_STEREO_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x0902
+#define mmCRTC1_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
+#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x0903
+#define mmCRTC1_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x0904
+#define mmCRTC1_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
+#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x0905
+#define mmCRTC1_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
+#define mmCRTC1_CRTC_START_LINE_CONTROL 0x0906
+#define mmCRTC1_CRTC_START_LINE_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x0907
+#define mmCRTC1_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_UPDATE_LOCK 0x0908
+#define mmCRTC1_CRTC_UPDATE_LOCK_BASE_IDX 2
+#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x0909
+#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x090a
+#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
+#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x090b
+#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x090c
+#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
+#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x090d
+#define mmCRTC1_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
+#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK 0x090e
+#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
+#define mmCRTC1_CRTC_MASTER_UPDATE_MODE 0x090f
+#define mmCRTC1_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
+#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x0910
+#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
+#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0911
+#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
+#define mmCRTC1_CRTC_MVP_STATUS 0x0912
+#define mmCRTC1_CRTC_MVP_STATUS_BASE_IDX 2
+#define mmCRTC1_CRTC_MASTER_EN 0x0913
+#define mmCRTC1_CRTC_MASTER_EN_BASE_IDX 2
+#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x0914
+#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
+#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x0915
+#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
+#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x0917
+#define mmCRTC1_CRTC_OVERSCAN_COLOR_BASE_IDX 2
+#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x0918
+#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
+#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x0919
+#define mmCRTC1_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
+#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x091a
+#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+#define mmCRTC1_CRTC_BLACK_COLOR 0x091b
+#define mmCRTC1_CRTC_BLACK_COLOR_BASE_IDX 2
+#define mmCRTC1_CRTC_BLACK_COLOR_EXT 0x091c
+#define mmCRTC1_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x091d
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x091e
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x091f
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0920
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0921
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0922
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_CRC_CNTL 0x0923
+#define mmCRTC1_CRTC_CRC_CNTL_BASE_IDX 2
+#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x0924
+#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0925
+#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x0926
+#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0927
+#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_CRC0_DATA_RG 0x0928
+#define mmCRTC1_CRTC_CRC0_DATA_RG_BASE_IDX 2
+#define mmCRTC1_CRTC_CRC0_DATA_B 0x0929
+#define mmCRTC1_CRTC_CRC0_DATA_B_BASE_IDX 2
+#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x092a
+#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x092b
+#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x092c
+#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x092d
+#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_CRC1_DATA_RG 0x092e
+#define mmCRTC1_CRTC_CRC1_DATA_RG_BASE_IDX 2
+#define mmCRTC1_CRTC_CRC1_DATA_B 0x092f
+#define mmCRTC1_CRTC_CRC1_DATA_B_BASE_IDX 2
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x0930
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0931
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0932
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0933
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0934
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0935
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x0936
+#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x0937
+#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x0938
+#define mmCRTC1_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
+#define mmCRTC1_CRTC_GSL_WINDOW 0x0939
+#define mmCRTC1_CRTC_GSL_WINDOW_BASE_IDX 2
+#define mmCRTC1_CRTC_GSL_CONTROL 0x093a
+#define mmCRTC1_CRTC_GSL_CONTROL_BASE_IDX 2
+#define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS 0x093d
+#define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
+#define mmCRTC1_CRTC_DRR_CONTROL 0x093e
+#define mmCRTC1_CRTC_DRR_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_fmt1_dispdec
+// base address: 0x800
+#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x0942
+#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
+#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x0943
+#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
+#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x0944
+#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
+#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x0945
+#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
+#define mmFMT1_FMT_CONTROL 0x0946
+#define mmFMT1_FMT_CONTROL_BASE_IDX 2
+#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x0947
+#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
+#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x0948
+#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
+#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x0949
+#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
+#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x094a
+#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
+#define mmFMT1_FMT_CLAMP_CNTL 0x094e
+#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2
+#define mmFMT1_FMT_CRC_CNTL 0x094f
+#define mmFMT1_FMT_CRC_CNTL_BASE_IDX 2
+#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x0950
+#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
+#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0951
+#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
+#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x0952
+#define mmFMT1_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
+#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x0953
+#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
+#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0954
+#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
+#define mmFMT1_FMT_420_HBLANK_EARLY_START 0x0955
+#define mmFMT1_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcp2_dispdec
+// base address: 0x1000
+#define mmDCP2_GRPH_ENABLE 0x095a
+#define mmDCP2_GRPH_ENABLE_BASE_IDX 2
+#define mmDCP2_GRPH_CONTROL 0x095b
+#define mmDCP2_GRPH_CONTROL_BASE_IDX 2
+#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x095c
+#define mmDCP2_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
+#define mmDCP2_GRPH_SWAP_CNTL 0x095d
+#define mmDCP2_GRPH_SWAP_CNTL_BASE_IDX 2
+#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x095e
+#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x095f
+#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP2_GRPH_PITCH 0x0960
+#define mmDCP2_GRPH_PITCH_BASE_IDX 2
+#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0961
+#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0962
+#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x0963
+#define mmDCP2_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
+#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x0964
+#define mmDCP2_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
+#define mmDCP2_GRPH_X_START 0x0965
+#define mmDCP2_GRPH_X_START_BASE_IDX 2
+#define mmDCP2_GRPH_Y_START 0x0966
+#define mmDCP2_GRPH_Y_START_BASE_IDX 2
+#define mmDCP2_GRPH_X_END 0x0967
+#define mmDCP2_GRPH_X_END_BASE_IDX 2
+#define mmDCP2_GRPH_Y_END 0x0968
+#define mmDCP2_GRPH_Y_END_BASE_IDX 2
+#define mmDCP2_INPUT_GAMMA_CONTROL 0x0969
+#define mmDCP2_INPUT_GAMMA_CONTROL_BASE_IDX 2
+#define mmDCP2_GRPH_UPDATE 0x096a
+#define mmDCP2_GRPH_UPDATE_BASE_IDX 2
+#define mmDCP2_GRPH_FLIP_CONTROL 0x096b
+#define mmDCP2_GRPH_FLIP_CONTROL_BASE_IDX 2
+#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x096c
+#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
+#define mmDCP2_GRPH_DFQ_CONTROL 0x096d
+#define mmDCP2_GRPH_DFQ_CONTROL_BASE_IDX 2
+#define mmDCP2_GRPH_DFQ_STATUS 0x096e
+#define mmDCP2_GRPH_DFQ_STATUS_BASE_IDX 2
+#define mmDCP2_GRPH_INTERRUPT_STATUS 0x096f
+#define mmDCP2_GRPH_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x0970
+#define mmDCP2_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0971
+#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
+#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x0972
+#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP2_GRPH_COMPRESS_PITCH 0x0973
+#define mmDCP2_GRPH_COMPRESS_PITCH_BASE_IDX 2
+#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0974
+#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0975
+#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
+#define mmDCP2_PRESCALE_GRPH_CONTROL 0x0976
+#define mmDCP2_PRESCALE_GRPH_CONTROL_BASE_IDX 2
+#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x0977
+#define mmDCP2_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
+#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x0978
+#define mmDCP2_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
+#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x0979
+#define mmDCP2_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
+#define mmDCP2_INPUT_CSC_CONTROL 0x097a
+#define mmDCP2_INPUT_CSC_CONTROL_BASE_IDX 2
+#define mmDCP2_INPUT_CSC_C11_C12 0x097b
+#define mmDCP2_INPUT_CSC_C11_C12_BASE_IDX 2
+#define mmDCP2_INPUT_CSC_C13_C14 0x097c
+#define mmDCP2_INPUT_CSC_C13_C14_BASE_IDX 2
+#define mmDCP2_INPUT_CSC_C21_C22 0x097d
+#define mmDCP2_INPUT_CSC_C21_C22_BASE_IDX 2
+#define mmDCP2_INPUT_CSC_C23_C24 0x097e
+#define mmDCP2_INPUT_CSC_C23_C24_BASE_IDX 2
+#define mmDCP2_INPUT_CSC_C31_C32 0x097f
+#define mmDCP2_INPUT_CSC_C31_C32_BASE_IDX 2
+#define mmDCP2_INPUT_CSC_C33_C34 0x0980
+#define mmDCP2_INPUT_CSC_C33_C34_BASE_IDX 2
+#define mmDCP2_OUTPUT_CSC_CONTROL 0x0981
+#define mmDCP2_OUTPUT_CSC_CONTROL_BASE_IDX 2
+#define mmDCP2_OUTPUT_CSC_C11_C12 0x0982
+#define mmDCP2_OUTPUT_CSC_C11_C12_BASE_IDX 2
+#define mmDCP2_OUTPUT_CSC_C13_C14 0x0983
+#define mmDCP2_OUTPUT_CSC_C13_C14_BASE_IDX 2
+#define mmDCP2_OUTPUT_CSC_C21_C22 0x0984
+#define mmDCP2_OUTPUT_CSC_C21_C22_BASE_IDX 2
+#define mmDCP2_OUTPUT_CSC_C23_C24 0x0985
+#define mmDCP2_OUTPUT_CSC_C23_C24_BASE_IDX 2
+#define mmDCP2_OUTPUT_CSC_C31_C32 0x0986
+#define mmDCP2_OUTPUT_CSC_C31_C32_BASE_IDX 2
+#define mmDCP2_OUTPUT_CSC_C33_C34 0x0987
+#define mmDCP2_OUTPUT_CSC_C33_C34_BASE_IDX 2
+#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x0988
+#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
+#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x0989
+#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
+#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x098a
+#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
+#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x098b
+#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
+#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x098c
+#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
+#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x098d
+#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
+#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x098e
+#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
+#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x098f
+#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
+#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x0990
+#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
+#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x0991
+#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
+#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x0992
+#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
+#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x0993
+#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
+#define mmDCP2_DENORM_CONTROL 0x0994
+#define mmDCP2_DENORM_CONTROL_BASE_IDX 2
+#define mmDCP2_OUT_ROUND_CONTROL 0x0995
+#define mmDCP2_OUT_ROUND_CONTROL_BASE_IDX 2
+#define mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x0996
+#define mmDCP2_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
+#define mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x0997
+#define mmDCP2_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
+#define mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x0998
+#define mmDCP2_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
+#define mmDCP2_KEY_CONTROL 0x0999
+#define mmDCP2_KEY_CONTROL_BASE_IDX 2
+#define mmDCP2_KEY_RANGE_ALPHA 0x099a
+#define mmDCP2_KEY_RANGE_ALPHA_BASE_IDX 2
+#define mmDCP2_KEY_RANGE_RED 0x099b
+#define mmDCP2_KEY_RANGE_RED_BASE_IDX 2
+#define mmDCP2_KEY_RANGE_GREEN 0x099c
+#define mmDCP2_KEY_RANGE_GREEN_BASE_IDX 2
+#define mmDCP2_KEY_RANGE_BLUE 0x099d
+#define mmDCP2_KEY_RANGE_BLUE_BASE_IDX 2
+#define mmDCP2_DEGAMMA_CONTROL 0x099e
+#define mmDCP2_DEGAMMA_CONTROL_BASE_IDX 2
+#define mmDCP2_GAMUT_REMAP_CONTROL 0x099f
+#define mmDCP2_GAMUT_REMAP_CONTROL_BASE_IDX 2
+#define mmDCP2_GAMUT_REMAP_C11_C12 0x09a0
+#define mmDCP2_GAMUT_REMAP_C11_C12_BASE_IDX 2
+#define mmDCP2_GAMUT_REMAP_C13_C14 0x09a1
+#define mmDCP2_GAMUT_REMAP_C13_C14_BASE_IDX 2
+#define mmDCP2_GAMUT_REMAP_C21_C22 0x09a2
+#define mmDCP2_GAMUT_REMAP_C21_C22_BASE_IDX 2
+#define mmDCP2_GAMUT_REMAP_C23_C24 0x09a3
+#define mmDCP2_GAMUT_REMAP_C23_C24_BASE_IDX 2
+#define mmDCP2_GAMUT_REMAP_C31_C32 0x09a4
+#define mmDCP2_GAMUT_REMAP_C31_C32_BASE_IDX 2
+#define mmDCP2_GAMUT_REMAP_C33_C34 0x09a5
+#define mmDCP2_GAMUT_REMAP_C33_C34_BASE_IDX 2
+#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x09a6
+#define mmDCP2_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
+#define mmDCP2_DCP_RANDOM_SEEDS 0x09a7
+#define mmDCP2_DCP_RANDOM_SEEDS_BASE_IDX 2
+#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x09a8
+#define mmDCP2_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
+#define mmDCP2_CUR_CONTROL 0x09a9
+#define mmDCP2_CUR_CONTROL_BASE_IDX 2
+#define mmDCP2_CUR_SURFACE_ADDRESS 0x09aa
+#define mmDCP2_CUR_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP2_CUR_SIZE 0x09ab
+#define mmDCP2_CUR_SIZE_BASE_IDX 2
+#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x09ac
+#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP2_CUR_POSITION 0x09ad
+#define mmDCP2_CUR_POSITION_BASE_IDX 2
+#define mmDCP2_CUR_HOT_SPOT 0x09ae
+#define mmDCP2_CUR_HOT_SPOT_BASE_IDX 2
+#define mmDCP2_CUR_COLOR1 0x09af
+#define mmDCP2_CUR_COLOR1_BASE_IDX 2
+#define mmDCP2_CUR_COLOR2 0x09b0
+#define mmDCP2_CUR_COLOR2_BASE_IDX 2
+#define mmDCP2_CUR_UPDATE 0x09b1
+#define mmDCP2_CUR_UPDATE_BASE_IDX 2
+#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x09bb
+#define mmDCP2_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
+#define mmDCP2_CUR_STEREO_CONTROL 0x09bc
+#define mmDCP2_CUR_STEREO_CONTROL_BASE_IDX 2
+#define mmDCP2_DC_LUT_RW_MODE 0x09be
+#define mmDCP2_DC_LUT_RW_MODE_BASE_IDX 2
+#define mmDCP2_DC_LUT_RW_INDEX 0x09bf
+#define mmDCP2_DC_LUT_RW_INDEX_BASE_IDX 2
+#define mmDCP2_DC_LUT_SEQ_COLOR 0x09c0
+#define mmDCP2_DC_LUT_SEQ_COLOR_BASE_IDX 2
+#define mmDCP2_DC_LUT_PWL_DATA 0x09c1
+#define mmDCP2_DC_LUT_PWL_DATA_BASE_IDX 2
+#define mmDCP2_DC_LUT_30_COLOR 0x09c2
+#define mmDCP2_DC_LUT_30_COLOR_BASE_IDX 2
+#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x09c3
+#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
+#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x09c4
+#define mmDCP2_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmDCP2_DC_LUT_AUTOFILL 0x09c5
+#define mmDCP2_DC_LUT_AUTOFILL_BASE_IDX 2
+#define mmDCP2_DC_LUT_CONTROL 0x09c6
+#define mmDCP2_DC_LUT_CONTROL_BASE_IDX 2
+#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x09c7
+#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
+#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x09c8
+#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
+#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x09c9
+#define mmDCP2_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
+#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x09ca
+#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
+#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x09cb
+#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
+#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x09cc
+#define mmDCP2_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
+#define mmDCP2_DCP_CRC_CONTROL 0x09cd
+#define mmDCP2_DCP_CRC_CONTROL_BASE_IDX 2
+#define mmDCP2_DCP_CRC_MASK 0x09ce
+#define mmDCP2_DCP_CRC_MASK_BASE_IDX 2
+#define mmDCP2_DCP_CRC_CURRENT 0x09cf
+#define mmDCP2_DCP_CRC_CURRENT_BASE_IDX 2
+#define mmDCP2_DVMM_PTE_CONTROL 0x09d0
+#define mmDCP2_DVMM_PTE_CONTROL_BASE_IDX 2
+#define mmDCP2_DCP_CRC_LAST 0x09d1
+#define mmDCP2_DCP_CRC_LAST_BASE_IDX 2
+#define mmDCP2_DVMM_PTE_ARB_CONTROL 0x09d2
+#define mmDCP2_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
+#define mmDCP2_GRPH_FLIP_RATE_CNTL 0x09d4
+#define mmDCP2_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
+#define mmDCP2_DCP_GSL_CONTROL 0x09d5
+#define mmDCP2_DCP_GSL_CONTROL_BASE_IDX 2
+#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x09d6
+#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
+#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x09dc
+#define mmDCP2_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
+#define mmDCP2_HW_ROTATION 0x09de
+#define mmDCP2_HW_ROTATION_BASE_IDX 2
+#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x09df
+#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
+#define mmDCP2_REGAMMA_CONTROL 0x09e0
+#define mmDCP2_REGAMMA_CONTROL_BASE_IDX 2
+#define mmDCP2_REGAMMA_LUT_INDEX 0x09e1
+#define mmDCP2_REGAMMA_LUT_INDEX_BASE_IDX 2
+#define mmDCP2_REGAMMA_LUT_DATA 0x09e2
+#define mmDCP2_REGAMMA_LUT_DATA_BASE_IDX 2
+#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x09e3
+#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x09e4
+#define mmDCP2_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x09e5
+#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x09e6
+#define mmDCP2_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x09e7
+#define mmDCP2_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x09e8
+#define mmDCP2_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x09e9
+#define mmDCP2_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x09ea
+#define mmDCP2_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x09eb
+#define mmDCP2_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x09ec
+#define mmDCP2_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x09ed
+#define mmDCP2_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x09ee
+#define mmDCP2_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x09ef
+#define mmDCP2_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x09f0
+#define mmDCP2_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x09f1
+#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x09f2
+#define mmDCP2_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x09f3
+#define mmDCP2_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x09f4
+#define mmDCP2_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x09f5
+#define mmDCP2_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x09f6
+#define mmDCP2_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x09f7
+#define mmDCP2_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x09f8
+#define mmDCP2_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x09f9
+#define mmDCP2_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x09fa
+#define mmDCP2_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
+#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x09fb
+#define mmDCP2_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
+#define mmDCP2_ALPHA_CONTROL 0x09fc
+#define mmDCP2_ALPHA_CONTROL_BASE_IDX 2
+#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x09fd
+#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x09fe
+#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x09ff
+#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
+#define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT 0x0a00
+#define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
+#define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY 0x0a01
+#define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
+#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL 0x0a02
+#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
+#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT 0x0a03
+#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_lb2_dispdec
+// base address: 0x1000
+#define mmLB2_LB_DATA_FORMAT 0x0a1a
+#define mmLB2_LB_DATA_FORMAT_BASE_IDX 2
+#define mmLB2_LB_MEMORY_CTRL 0x0a1b
+#define mmLB2_LB_MEMORY_CTRL_BASE_IDX 2
+#define mmLB2_LB_MEMORY_SIZE_STATUS 0x0a1c
+#define mmLB2_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
+#define mmLB2_LB_DESKTOP_HEIGHT 0x0a1d
+#define mmLB2_LB_DESKTOP_HEIGHT_BASE_IDX 2
+#define mmLB2_LB_VLINE_START_END 0x0a1e
+#define mmLB2_LB_VLINE_START_END_BASE_IDX 2
+#define mmLB2_LB_VLINE2_START_END 0x0a1f
+#define mmLB2_LB_VLINE2_START_END_BASE_IDX 2
+#define mmLB2_LB_V_COUNTER 0x0a20
+#define mmLB2_LB_V_COUNTER_BASE_IDX 2
+#define mmLB2_LB_SNAPSHOT_V_COUNTER 0x0a21
+#define mmLB2_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
+#define mmLB2_LB_INTERRUPT_MASK 0x0a22
+#define mmLB2_LB_INTERRUPT_MASK_BASE_IDX 2
+#define mmLB2_LB_VLINE_STATUS 0x0a23
+#define mmLB2_LB_VLINE_STATUS_BASE_IDX 2
+#define mmLB2_LB_VLINE2_STATUS 0x0a24
+#define mmLB2_LB_VLINE2_STATUS_BASE_IDX 2
+#define mmLB2_LB_VBLANK_STATUS 0x0a25
+#define mmLB2_LB_VBLANK_STATUS_BASE_IDX 2
+#define mmLB2_LB_SYNC_RESET_SEL 0x0a26
+#define mmLB2_LB_SYNC_RESET_SEL_BASE_IDX 2
+#define mmLB2_LB_BLACK_KEYER_R_CR 0x0a27
+#define mmLB2_LB_BLACK_KEYER_R_CR_BASE_IDX 2
+#define mmLB2_LB_BLACK_KEYER_G_Y 0x0a28
+#define mmLB2_LB_BLACK_KEYER_G_Y_BASE_IDX 2
+#define mmLB2_LB_BLACK_KEYER_B_CB 0x0a29
+#define mmLB2_LB_BLACK_KEYER_B_CB_BASE_IDX 2
+#define mmLB2_LB_KEYER_COLOR_CTRL 0x0a2a
+#define mmLB2_LB_KEYER_COLOR_CTRL_BASE_IDX 2
+#define mmLB2_LB_KEYER_COLOR_R_CR 0x0a2b
+#define mmLB2_LB_KEYER_COLOR_R_CR_BASE_IDX 2
+#define mmLB2_LB_KEYER_COLOR_G_Y 0x0a2c
+#define mmLB2_LB_KEYER_COLOR_G_Y_BASE_IDX 2
+#define mmLB2_LB_KEYER_COLOR_B_CB 0x0a2d
+#define mmLB2_LB_KEYER_COLOR_B_CB_BASE_IDX 2
+#define mmLB2_LB_KEYER_COLOR_REP_R_CR 0x0a2e
+#define mmLB2_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
+#define mmLB2_LB_KEYER_COLOR_REP_G_Y 0x0a2f
+#define mmLB2_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
+#define mmLB2_LB_KEYER_COLOR_REP_B_CB 0x0a30
+#define mmLB2_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
+#define mmLB2_LB_BUFFER_LEVEL_STATUS 0x0a31
+#define mmLB2_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
+#define mmLB2_LB_BUFFER_URGENCY_CTRL 0x0a32
+#define mmLB2_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
+#define mmLB2_LB_BUFFER_URGENCY_STATUS 0x0a33
+#define mmLB2_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
+#define mmLB2_LB_BUFFER_STATUS 0x0a34
+#define mmLB2_LB_BUFFER_STATUS_BASE_IDX 2
+#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x0a35
+#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
+#define mmLB2_MVP_AFR_FLIP_MODE 0x0a36
+#define mmLB2_MVP_AFR_FLIP_MODE_BASE_IDX 2
+#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x0a37
+#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
+#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x0a38
+#define mmLB2_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
+#define mmLB2_DC_MVP_LB_CONTROL 0x0a39
+#define mmLB2_DC_MVP_LB_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcfe2_dispdec
+// base address: 0x1000
+#define mmDCFE2_DCFE_CLOCK_CONTROL 0x0a5a
+#define mmDCFE2_DCFE_CLOCK_CONTROL_BASE_IDX 2
+#define mmDCFE2_DCFE_SOFT_RESET 0x0a5b
+#define mmDCFE2_DCFE_SOFT_RESET_BASE_IDX 2
+#define mmDCFE2_DCFE_MEM_PWR_CTRL 0x0a5d
+#define mmDCFE2_DCFE_MEM_PWR_CTRL_BASE_IDX 2
+#define mmDCFE2_DCFE_MEM_PWR_CTRL2 0x0a5e
+#define mmDCFE2_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
+#define mmDCFE2_DCFE_MEM_PWR_STATUS 0x0a5f
+#define mmDCFE2_DCFE_MEM_PWR_STATUS_BASE_IDX 2
+#define mmDCFE2_DCFE_MISC 0x0a60
+#define mmDCFE2_DCFE_MISC_BASE_IDX 2
+#define mmDCFE2_DCFE_FLUSH 0x0a61
+#define mmDCFE2_DCFE_FLUSH_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_perfmon5_dispdec
+// base address: 0x2938
+#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x0a6e
+#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x0a6f
+#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x0a70
+#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON5_PERFMON_CNTL 0x0a71
+#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON5_PERFMON_CNTL2 0x0a72
+#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x0a73
+#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0a74
+#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON5_PERFMON_HI 0x0a75
+#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON5_PERFMON_LOW 0x0a76
+#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dmif_pg2_dispdec
+// base address: 0x1000
+#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x0a7a
+#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
+#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x0a7b
+#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
+#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x0a7c
+#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
+#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x0a7d
+#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
+#define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL 0x0a7e
+#define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
+#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x0a7f
+#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
+#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2 0x0a80
+#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
+#define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL 0x0a81
+#define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
+#define mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x0a82
+#define mmDMIF_PG2_DPG_REPEATER_PROGRAM_BASE_IDX 2
+#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL 0x0a86
+#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
+#define mmDMIF_PG2_DPG_DVMM_STATUS 0x0a87
+#define mmDMIF_PG2_DPG_DVMM_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_scl2_dispdec
+// base address: 0x1000
+#define mmSCL2_SCL_COEF_RAM_SELECT 0x0a9a
+#define mmSCL2_SCL_COEF_RAM_SELECT_BASE_IDX 2
+#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x0a9b
+#define mmSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
+#define mmSCL2_SCL_MODE 0x0a9c
+#define mmSCL2_SCL_MODE_BASE_IDX 2
+#define mmSCL2_SCL_TAP_CONTROL 0x0a9d
+#define mmSCL2_SCL_TAP_CONTROL_BASE_IDX 2
+#define mmSCL2_SCL_CONTROL 0x0a9e
+#define mmSCL2_SCL_CONTROL_BASE_IDX 2
+#define mmSCL2_SCL_BYPASS_CONTROL 0x0a9f
+#define mmSCL2_SCL_BYPASS_CONTROL_BASE_IDX 2
+#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0aa0
+#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x0aa1
+#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
+#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x0aa2
+#define mmSCL2_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
+#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0aa3
+#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmSCL2_SCL_HORZ_FILTER_INIT 0x0aa4
+#define mmSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2
+#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x0aa5
+#define mmSCL2_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
+#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0aa6
+#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmSCL2_SCL_VERT_FILTER_INIT 0x0aa7
+#define mmSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2
+#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x0aa8
+#define mmSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
+#define mmSCL2_SCL_ROUND_OFFSET 0x0aa9
+#define mmSCL2_SCL_ROUND_OFFSET_BASE_IDX 2
+#define mmSCL2_SCL_UPDATE 0x0aaa
+#define mmSCL2_SCL_UPDATE_BASE_IDX 2
+#define mmSCL2_SCL_F_SHARP_CONTROL 0x0aab
+#define mmSCL2_SCL_F_SHARP_CONTROL_BASE_IDX 2
+#define mmSCL2_SCL_ALU_CONTROL 0x0aac
+#define mmSCL2_SCL_ALU_CONTROL_BASE_IDX 2
+#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x0aad
+#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
+#define mmSCL2_VIEWPORT_START_SECONDARY 0x0aae
+#define mmSCL2_VIEWPORT_START_SECONDARY_BASE_IDX 2
+#define mmSCL2_VIEWPORT_START 0x0aaf
+#define mmSCL2_VIEWPORT_START_BASE_IDX 2
+#define mmSCL2_VIEWPORT_SIZE 0x0ab0
+#define mmSCL2_VIEWPORT_SIZE_BASE_IDX 2
+#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x0ab1
+#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x0ab2
+#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+#define mmSCL2_SCL_MODE_CHANGE_DET1 0x0ab3
+#define mmSCL2_SCL_MODE_CHANGE_DET1_BASE_IDX 2
+#define mmSCL2_SCL_MODE_CHANGE_DET2 0x0ab4
+#define mmSCL2_SCL_MODE_CHANGE_DET2_BASE_IDX 2
+#define mmSCL2_SCL_MODE_CHANGE_DET3 0x0ab5
+#define mmSCL2_SCL_MODE_CHANGE_DET3_BASE_IDX 2
+#define mmSCL2_SCL_MODE_CHANGE_MASK 0x0ab6
+#define mmSCL2_SCL_MODE_CHANGE_MASK_BASE_IDX 2
+
+
+// addressBlock: dce_dc_blnd2_dispdec
+// base address: 0x1000
+#define mmBLND2_BLND_CONTROL 0x0ac7
+#define mmBLND2_BLND_CONTROL_BASE_IDX 2
+#define mmBLND2_BLND_SM_CONTROL2 0x0ac8
+#define mmBLND2_BLND_SM_CONTROL2_BASE_IDX 2
+#define mmBLND2_BLND_CONTROL2 0x0ac9
+#define mmBLND2_BLND_CONTROL2_BASE_IDX 2
+#define mmBLND2_BLND_UPDATE 0x0aca
+#define mmBLND2_BLND_UPDATE_BASE_IDX 2
+#define mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x0acb
+#define mmBLND2_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
+#define mmBLND2_BLND_V_UPDATE_LOCK 0x0acc
+#define mmBLND2_BLND_V_UPDATE_LOCK_BASE_IDX 2
+#define mmBLND2_BLND_REG_UPDATE_STATUS 0x0acd
+#define mmBLND2_BLND_REG_UPDATE_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_crtc2_dispdec
+// base address: 0x1000
+#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x0ad2
+#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
+#define mmCRTC2_CRTC_H_TOTAL 0x0ad3
+#define mmCRTC2_CRTC_H_TOTAL_BASE_IDX 2
+#define mmCRTC2_CRTC_H_BLANK_START_END 0x0ad4
+#define mmCRTC2_CRTC_H_BLANK_START_END_BASE_IDX 2
+#define mmCRTC2_CRTC_H_SYNC_A 0x0ad5
+#define mmCRTC2_CRTC_H_SYNC_A_BASE_IDX 2
+#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x0ad6
+#define mmCRTC2_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
+#define mmCRTC2_CRTC_H_SYNC_B 0x0ad7
+#define mmCRTC2_CRTC_H_SYNC_B_BASE_IDX 2
+#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x0ad8
+#define mmCRTC2_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
+#define mmCRTC2_CRTC_VBI_END 0x0ad9
+#define mmCRTC2_CRTC_VBI_END_BASE_IDX 2
+#define mmCRTC2_CRTC_V_TOTAL 0x0ada
+#define mmCRTC2_CRTC_V_TOTAL_BASE_IDX 2
+#define mmCRTC2_CRTC_V_TOTAL_MIN 0x0adb
+#define mmCRTC2_CRTC_V_TOTAL_MIN_BASE_IDX 2
+#define mmCRTC2_CRTC_V_TOTAL_MAX 0x0adc
+#define mmCRTC2_CRTC_V_TOTAL_MAX_BASE_IDX 2
+#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x0add
+#define mmCRTC2_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x0ade
+#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
+#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x0adf
+#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+#define mmCRTC2_CRTC_V_BLANK_START_END 0x0ae0
+#define mmCRTC2_CRTC_V_BLANK_START_END_BASE_IDX 2
+#define mmCRTC2_CRTC_V_SYNC_A 0x0ae1
+#define mmCRTC2_CRTC_V_SYNC_A_BASE_IDX 2
+#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x0ae2
+#define mmCRTC2_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
+#define mmCRTC2_CRTC_V_SYNC_B 0x0ae3
+#define mmCRTC2_CRTC_V_SYNC_B_BASE_IDX 2
+#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x0ae4
+#define mmCRTC2_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
+#define mmCRTC2_CRTC_DTMTEST_CNTL 0x0ae5
+#define mmCRTC2_CRTC_DTMTEST_CNTL_BASE_IDX 2
+#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x0ae6
+#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
+#define mmCRTC2_CRTC_TRIGA_CNTL 0x0ae7
+#define mmCRTC2_CRTC_TRIGA_CNTL_BASE_IDX 2
+#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x0ae8
+#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
+#define mmCRTC2_CRTC_TRIGB_CNTL 0x0ae9
+#define mmCRTC2_CRTC_TRIGB_CNTL_BASE_IDX 2
+#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x0aea
+#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
+#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x0aeb
+#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+#define mmCRTC2_CRTC_FLOW_CONTROL 0x0aec
+#define mmCRTC2_CRTC_FLOW_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x0aed
+#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+#define mmCRTC2_CRTC_AVSYNC_COUNTER 0x0aee
+#define mmCRTC2_CRTC_AVSYNC_COUNTER_BASE_IDX 2
+#define mmCRTC2_CRTC_CONTROL 0x0aef
+#define mmCRTC2_CRTC_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_BLANK_CONTROL 0x0af0
+#define mmCRTC2_CRTC_BLANK_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x0af1
+#define mmCRTC2_CRTC_INTERLACE_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_INTERLACE_STATUS 0x0af2
+#define mmCRTC2_CRTC_INTERLACE_STATUS_BASE_IDX 2
+#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x0af3
+#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x0af4
+#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
+#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x0af5
+#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
+#define mmCRTC2_CRTC_STATUS 0x0af6
+#define mmCRTC2_CRTC_STATUS_BASE_IDX 2
+#define mmCRTC2_CRTC_STATUS_POSITION 0x0af7
+#define mmCRTC2_CRTC_STATUS_POSITION_BASE_IDX 2
+#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x0af8
+#define mmCRTC2_CRTC_NOM_VERT_POSITION_BASE_IDX 2
+#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x0af9
+#define mmCRTC2_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
+#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x0afa
+#define mmCRTC2_CRTC_STATUS_VF_COUNT_BASE_IDX 2
+#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x0afb
+#define mmCRTC2_CRTC_STATUS_HV_COUNT_BASE_IDX 2
+#define mmCRTC2_CRTC_COUNT_CONTROL 0x0afc
+#define mmCRTC2_CRTC_COUNT_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_COUNT_RESET 0x0afd
+#define mmCRTC2_CRTC_COUNT_RESET_BASE_IDX 2
+#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x0afe
+#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x0aff
+#define mmCRTC2_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_STEREO_STATUS 0x0b00
+#define mmCRTC2_CRTC_STEREO_STATUS_BASE_IDX 2
+#define mmCRTC2_CRTC_STEREO_CONTROL 0x0b01
+#define mmCRTC2_CRTC_STEREO_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x0b02
+#define mmCRTC2_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
+#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x0b03
+#define mmCRTC2_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x0b04
+#define mmCRTC2_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
+#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x0b05
+#define mmCRTC2_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
+#define mmCRTC2_CRTC_START_LINE_CONTROL 0x0b06
+#define mmCRTC2_CRTC_START_LINE_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x0b07
+#define mmCRTC2_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_UPDATE_LOCK 0x0b08
+#define mmCRTC2_CRTC_UPDATE_LOCK_BASE_IDX 2
+#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x0b09
+#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x0b0a
+#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
+#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x0b0b
+#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x0b0c
+#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
+#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x0b0d
+#define mmCRTC2_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
+#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK 0x0b0e
+#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
+#define mmCRTC2_CRTC_MASTER_UPDATE_MODE 0x0b0f
+#define mmCRTC2_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
+#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x0b10
+#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
+#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0b11
+#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
+#define mmCRTC2_CRTC_MVP_STATUS 0x0b12
+#define mmCRTC2_CRTC_MVP_STATUS_BASE_IDX 2
+#define mmCRTC2_CRTC_MASTER_EN 0x0b13
+#define mmCRTC2_CRTC_MASTER_EN_BASE_IDX 2
+#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x0b14
+#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
+#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x0b15
+#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
+#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x0b17
+#define mmCRTC2_CRTC_OVERSCAN_COLOR_BASE_IDX 2
+#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x0b18
+#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
+#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x0b19
+#define mmCRTC2_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
+#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x0b1a
+#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+#define mmCRTC2_CRTC_BLACK_COLOR 0x0b1b
+#define mmCRTC2_CRTC_BLACK_COLOR_BASE_IDX 2
+#define mmCRTC2_CRTC_BLACK_COLOR_EXT 0x0b1c
+#define mmCRTC2_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x0b1d
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x0b1e
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x0b1f
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0b20
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0b21
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0b22
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_CRC_CNTL 0x0b23
+#define mmCRTC2_CRTC_CRC_CNTL_BASE_IDX 2
+#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x0b24
+#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0b25
+#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x0b26
+#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0b27
+#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_CRC0_DATA_RG 0x0b28
+#define mmCRTC2_CRTC_CRC0_DATA_RG_BASE_IDX 2
+#define mmCRTC2_CRTC_CRC0_DATA_B 0x0b29
+#define mmCRTC2_CRTC_CRC0_DATA_B_BASE_IDX 2
+#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x0b2a
+#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x0b2b
+#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x0b2c
+#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x0b2d
+#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_CRC1_DATA_RG 0x0b2e
+#define mmCRTC2_CRTC_CRC1_DATA_RG_BASE_IDX 2
+#define mmCRTC2_CRTC_CRC1_DATA_B 0x0b2f
+#define mmCRTC2_CRTC_CRC1_DATA_B_BASE_IDX 2
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x0b30
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0b31
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0b32
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0b33
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0b34
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0b35
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x0b36
+#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x0b37
+#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x0b38
+#define mmCRTC2_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
+#define mmCRTC2_CRTC_GSL_WINDOW 0x0b39
+#define mmCRTC2_CRTC_GSL_WINDOW_BASE_IDX 2
+#define mmCRTC2_CRTC_GSL_CONTROL 0x0b3a
+#define mmCRTC2_CRTC_GSL_CONTROL_BASE_IDX 2
+#define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS 0x0b3d
+#define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
+#define mmCRTC2_CRTC_DRR_CONTROL 0x0b3e
+#define mmCRTC2_CRTC_DRR_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_fmt2_dispdec
+// base address: 0x1000
+#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x0b42
+#define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
+#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x0b43
+#define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
+#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x0b44
+#define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
+#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x0b45
+#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
+#define mmFMT2_FMT_CONTROL 0x0b46
+#define mmFMT2_FMT_CONTROL_BASE_IDX 2
+#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x0b47
+#define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
+#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x0b48
+#define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
+#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x0b49
+#define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
+#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x0b4a
+#define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
+#define mmFMT2_FMT_CLAMP_CNTL 0x0b4e
+#define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX 2
+#define mmFMT2_FMT_CRC_CNTL 0x0b4f
+#define mmFMT2_FMT_CRC_CNTL_BASE_IDX 2
+#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x0b50
+#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
+#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0b51
+#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
+#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x0b52
+#define mmFMT2_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
+#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x0b53
+#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
+#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0b54
+#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
+#define mmFMT2_FMT_420_HBLANK_EARLY_START 0x0b55
+#define mmFMT2_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcp3_dispdec
+// base address: 0x1800
+#define mmDCP3_GRPH_ENABLE 0x0b5a
+#define mmDCP3_GRPH_ENABLE_BASE_IDX 2
+#define mmDCP3_GRPH_CONTROL 0x0b5b
+#define mmDCP3_GRPH_CONTROL_BASE_IDX 2
+#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x0b5c
+#define mmDCP3_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
+#define mmDCP3_GRPH_SWAP_CNTL 0x0b5d
+#define mmDCP3_GRPH_SWAP_CNTL_BASE_IDX 2
+#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x0b5e
+#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x0b5f
+#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP3_GRPH_PITCH 0x0b60
+#define mmDCP3_GRPH_PITCH_BASE_IDX 2
+#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0b61
+#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0b62
+#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x0b63
+#define mmDCP3_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
+#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x0b64
+#define mmDCP3_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
+#define mmDCP3_GRPH_X_START 0x0b65
+#define mmDCP3_GRPH_X_START_BASE_IDX 2
+#define mmDCP3_GRPH_Y_START 0x0b66
+#define mmDCP3_GRPH_Y_START_BASE_IDX 2
+#define mmDCP3_GRPH_X_END 0x0b67
+#define mmDCP3_GRPH_X_END_BASE_IDX 2
+#define mmDCP3_GRPH_Y_END 0x0b68
+#define mmDCP3_GRPH_Y_END_BASE_IDX 2
+#define mmDCP3_INPUT_GAMMA_CONTROL 0x0b69
+#define mmDCP3_INPUT_GAMMA_CONTROL_BASE_IDX 2
+#define mmDCP3_GRPH_UPDATE 0x0b6a
+#define mmDCP3_GRPH_UPDATE_BASE_IDX 2
+#define mmDCP3_GRPH_FLIP_CONTROL 0x0b6b
+#define mmDCP3_GRPH_FLIP_CONTROL_BASE_IDX 2
+#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x0b6c
+#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
+#define mmDCP3_GRPH_DFQ_CONTROL 0x0b6d
+#define mmDCP3_GRPH_DFQ_CONTROL_BASE_IDX 2
+#define mmDCP3_GRPH_DFQ_STATUS 0x0b6e
+#define mmDCP3_GRPH_DFQ_STATUS_BASE_IDX 2
+#define mmDCP3_GRPH_INTERRUPT_STATUS 0x0b6f
+#define mmDCP3_GRPH_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x0b70
+#define mmDCP3_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0b71
+#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
+#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x0b72
+#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP3_GRPH_COMPRESS_PITCH 0x0b73
+#define mmDCP3_GRPH_COMPRESS_PITCH_BASE_IDX 2
+#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0b74
+#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0b75
+#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
+#define mmDCP3_PRESCALE_GRPH_CONTROL 0x0b76
+#define mmDCP3_PRESCALE_GRPH_CONTROL_BASE_IDX 2
+#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x0b77
+#define mmDCP3_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
+#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x0b78
+#define mmDCP3_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
+#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x0b79
+#define mmDCP3_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
+#define mmDCP3_INPUT_CSC_CONTROL 0x0b7a
+#define mmDCP3_INPUT_CSC_CONTROL_BASE_IDX 2
+#define mmDCP3_INPUT_CSC_C11_C12 0x0b7b
+#define mmDCP3_INPUT_CSC_C11_C12_BASE_IDX 2
+#define mmDCP3_INPUT_CSC_C13_C14 0x0b7c
+#define mmDCP3_INPUT_CSC_C13_C14_BASE_IDX 2
+#define mmDCP3_INPUT_CSC_C21_C22 0x0b7d
+#define mmDCP3_INPUT_CSC_C21_C22_BASE_IDX 2
+#define mmDCP3_INPUT_CSC_C23_C24 0x0b7e
+#define mmDCP3_INPUT_CSC_C23_C24_BASE_IDX 2
+#define mmDCP3_INPUT_CSC_C31_C32 0x0b7f
+#define mmDCP3_INPUT_CSC_C31_C32_BASE_IDX 2
+#define mmDCP3_INPUT_CSC_C33_C34 0x0b80
+#define mmDCP3_INPUT_CSC_C33_C34_BASE_IDX 2
+#define mmDCP3_OUTPUT_CSC_CONTROL 0x0b81
+#define mmDCP3_OUTPUT_CSC_CONTROL_BASE_IDX 2
+#define mmDCP3_OUTPUT_CSC_C11_C12 0x0b82
+#define mmDCP3_OUTPUT_CSC_C11_C12_BASE_IDX 2
+#define mmDCP3_OUTPUT_CSC_C13_C14 0x0b83
+#define mmDCP3_OUTPUT_CSC_C13_C14_BASE_IDX 2
+#define mmDCP3_OUTPUT_CSC_C21_C22 0x0b84
+#define mmDCP3_OUTPUT_CSC_C21_C22_BASE_IDX 2
+#define mmDCP3_OUTPUT_CSC_C23_C24 0x0b85
+#define mmDCP3_OUTPUT_CSC_C23_C24_BASE_IDX 2
+#define mmDCP3_OUTPUT_CSC_C31_C32 0x0b86
+#define mmDCP3_OUTPUT_CSC_C31_C32_BASE_IDX 2
+#define mmDCP3_OUTPUT_CSC_C33_C34 0x0b87
+#define mmDCP3_OUTPUT_CSC_C33_C34_BASE_IDX 2
+#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x0b88
+#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
+#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x0b89
+#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
+#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x0b8a
+#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
+#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x0b8b
+#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
+#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x0b8c
+#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
+#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x0b8d
+#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
+#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x0b8e
+#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
+#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x0b8f
+#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
+#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x0b90
+#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
+#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x0b91
+#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
+#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x0b92
+#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
+#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x0b93
+#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
+#define mmDCP3_DENORM_CONTROL 0x0b94
+#define mmDCP3_DENORM_CONTROL_BASE_IDX 2
+#define mmDCP3_OUT_ROUND_CONTROL 0x0b95
+#define mmDCP3_OUT_ROUND_CONTROL_BASE_IDX 2
+#define mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x0b96
+#define mmDCP3_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
+#define mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x0b97
+#define mmDCP3_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
+#define mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x0b98
+#define mmDCP3_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
+#define mmDCP3_KEY_CONTROL 0x0b99
+#define mmDCP3_KEY_CONTROL_BASE_IDX 2
+#define mmDCP3_KEY_RANGE_ALPHA 0x0b9a
+#define mmDCP3_KEY_RANGE_ALPHA_BASE_IDX 2
+#define mmDCP3_KEY_RANGE_RED 0x0b9b
+#define mmDCP3_KEY_RANGE_RED_BASE_IDX 2
+#define mmDCP3_KEY_RANGE_GREEN 0x0b9c
+#define mmDCP3_KEY_RANGE_GREEN_BASE_IDX 2
+#define mmDCP3_KEY_RANGE_BLUE 0x0b9d
+#define mmDCP3_KEY_RANGE_BLUE_BASE_IDX 2
+#define mmDCP3_DEGAMMA_CONTROL 0x0b9e
+#define mmDCP3_DEGAMMA_CONTROL_BASE_IDX 2
+#define mmDCP3_GAMUT_REMAP_CONTROL 0x0b9f
+#define mmDCP3_GAMUT_REMAP_CONTROL_BASE_IDX 2
+#define mmDCP3_GAMUT_REMAP_C11_C12 0x0ba0
+#define mmDCP3_GAMUT_REMAP_C11_C12_BASE_IDX 2
+#define mmDCP3_GAMUT_REMAP_C13_C14 0x0ba1
+#define mmDCP3_GAMUT_REMAP_C13_C14_BASE_IDX 2
+#define mmDCP3_GAMUT_REMAP_C21_C22 0x0ba2
+#define mmDCP3_GAMUT_REMAP_C21_C22_BASE_IDX 2
+#define mmDCP3_GAMUT_REMAP_C23_C24 0x0ba3
+#define mmDCP3_GAMUT_REMAP_C23_C24_BASE_IDX 2
+#define mmDCP3_GAMUT_REMAP_C31_C32 0x0ba4
+#define mmDCP3_GAMUT_REMAP_C31_C32_BASE_IDX 2
+#define mmDCP3_GAMUT_REMAP_C33_C34 0x0ba5
+#define mmDCP3_GAMUT_REMAP_C33_C34_BASE_IDX 2
+#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x0ba6
+#define mmDCP3_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
+#define mmDCP3_DCP_RANDOM_SEEDS 0x0ba7
+#define mmDCP3_DCP_RANDOM_SEEDS_BASE_IDX 2
+#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x0ba8
+#define mmDCP3_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
+#define mmDCP3_CUR_CONTROL 0x0ba9
+#define mmDCP3_CUR_CONTROL_BASE_IDX 2
+#define mmDCP3_CUR_SURFACE_ADDRESS 0x0baa
+#define mmDCP3_CUR_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP3_CUR_SIZE 0x0bab
+#define mmDCP3_CUR_SIZE_BASE_IDX 2
+#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x0bac
+#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP3_CUR_POSITION 0x0bad
+#define mmDCP3_CUR_POSITION_BASE_IDX 2
+#define mmDCP3_CUR_HOT_SPOT 0x0bae
+#define mmDCP3_CUR_HOT_SPOT_BASE_IDX 2
+#define mmDCP3_CUR_COLOR1 0x0baf
+#define mmDCP3_CUR_COLOR1_BASE_IDX 2
+#define mmDCP3_CUR_COLOR2 0x0bb0
+#define mmDCP3_CUR_COLOR2_BASE_IDX 2
+#define mmDCP3_CUR_UPDATE 0x0bb1
+#define mmDCP3_CUR_UPDATE_BASE_IDX 2
+#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x0bbb
+#define mmDCP3_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
+#define mmDCP3_CUR_STEREO_CONTROL 0x0bbc
+#define mmDCP3_CUR_STEREO_CONTROL_BASE_IDX 2
+#define mmDCP3_DC_LUT_RW_MODE 0x0bbe
+#define mmDCP3_DC_LUT_RW_MODE_BASE_IDX 2
+#define mmDCP3_DC_LUT_RW_INDEX 0x0bbf
+#define mmDCP3_DC_LUT_RW_INDEX_BASE_IDX 2
+#define mmDCP3_DC_LUT_SEQ_COLOR 0x0bc0
+#define mmDCP3_DC_LUT_SEQ_COLOR_BASE_IDX 2
+#define mmDCP3_DC_LUT_PWL_DATA 0x0bc1
+#define mmDCP3_DC_LUT_PWL_DATA_BASE_IDX 2
+#define mmDCP3_DC_LUT_30_COLOR 0x0bc2
+#define mmDCP3_DC_LUT_30_COLOR_BASE_IDX 2
+#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x0bc3
+#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
+#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x0bc4
+#define mmDCP3_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmDCP3_DC_LUT_AUTOFILL 0x0bc5
+#define mmDCP3_DC_LUT_AUTOFILL_BASE_IDX 2
+#define mmDCP3_DC_LUT_CONTROL 0x0bc6
+#define mmDCP3_DC_LUT_CONTROL_BASE_IDX 2
+#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x0bc7
+#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
+#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x0bc8
+#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
+#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x0bc9
+#define mmDCP3_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
+#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x0bca
+#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
+#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x0bcb
+#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
+#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x0bcc
+#define mmDCP3_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
+#define mmDCP3_DCP_CRC_CONTROL 0x0bcd
+#define mmDCP3_DCP_CRC_CONTROL_BASE_IDX 2
+#define mmDCP3_DCP_CRC_MASK 0x0bce
+#define mmDCP3_DCP_CRC_MASK_BASE_IDX 2
+#define mmDCP3_DCP_CRC_CURRENT 0x0bcf
+#define mmDCP3_DCP_CRC_CURRENT_BASE_IDX 2
+#define mmDCP3_DVMM_PTE_CONTROL 0x0bd0
+#define mmDCP3_DVMM_PTE_CONTROL_BASE_IDX 2
+#define mmDCP3_DCP_CRC_LAST 0x0bd1
+#define mmDCP3_DCP_CRC_LAST_BASE_IDX 2
+#define mmDCP3_DVMM_PTE_ARB_CONTROL 0x0bd2
+#define mmDCP3_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
+#define mmDCP3_GRPH_FLIP_RATE_CNTL 0x0bd4
+#define mmDCP3_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
+#define mmDCP3_DCP_GSL_CONTROL 0x0bd5
+#define mmDCP3_DCP_GSL_CONTROL_BASE_IDX 2
+#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x0bd6
+#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
+#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x0bdc
+#define mmDCP3_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
+#define mmDCP3_HW_ROTATION 0x0bde
+#define mmDCP3_HW_ROTATION_BASE_IDX 2
+#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x0bdf
+#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
+#define mmDCP3_REGAMMA_CONTROL 0x0be0
+#define mmDCP3_REGAMMA_CONTROL_BASE_IDX 2
+#define mmDCP3_REGAMMA_LUT_INDEX 0x0be1
+#define mmDCP3_REGAMMA_LUT_INDEX_BASE_IDX 2
+#define mmDCP3_REGAMMA_LUT_DATA 0x0be2
+#define mmDCP3_REGAMMA_LUT_DATA_BASE_IDX 2
+#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x0be3
+#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x0be4
+#define mmDCP3_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x0be5
+#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x0be6
+#define mmDCP3_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x0be7
+#define mmDCP3_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x0be8
+#define mmDCP3_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x0be9
+#define mmDCP3_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x0bea
+#define mmDCP3_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x0beb
+#define mmDCP3_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x0bec
+#define mmDCP3_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x0bed
+#define mmDCP3_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x0bee
+#define mmDCP3_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x0bef
+#define mmDCP3_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x0bf0
+#define mmDCP3_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x0bf1
+#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x0bf2
+#define mmDCP3_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x0bf3
+#define mmDCP3_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x0bf4
+#define mmDCP3_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x0bf5
+#define mmDCP3_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x0bf6
+#define mmDCP3_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x0bf7
+#define mmDCP3_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x0bf8
+#define mmDCP3_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x0bf9
+#define mmDCP3_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x0bfa
+#define mmDCP3_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
+#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x0bfb
+#define mmDCP3_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
+#define mmDCP3_ALPHA_CONTROL 0x0bfc
+#define mmDCP3_ALPHA_CONTROL_BASE_IDX 2
+#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x0bfd
+#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x0bfe
+#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x0bff
+#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
+#define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT 0x0c00
+#define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
+#define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY 0x0c01
+#define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
+#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL 0x0c02
+#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
+#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT 0x0c03
+#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_lb3_dispdec
+// base address: 0x1800
+#define mmLB3_LB_DATA_FORMAT 0x0c1a
+#define mmLB3_LB_DATA_FORMAT_BASE_IDX 2
+#define mmLB3_LB_MEMORY_CTRL 0x0c1b
+#define mmLB3_LB_MEMORY_CTRL_BASE_IDX 2
+#define mmLB3_LB_MEMORY_SIZE_STATUS 0x0c1c
+#define mmLB3_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
+#define mmLB3_LB_DESKTOP_HEIGHT 0x0c1d
+#define mmLB3_LB_DESKTOP_HEIGHT_BASE_IDX 2
+#define mmLB3_LB_VLINE_START_END 0x0c1e
+#define mmLB3_LB_VLINE_START_END_BASE_IDX 2
+#define mmLB3_LB_VLINE2_START_END 0x0c1f
+#define mmLB3_LB_VLINE2_START_END_BASE_IDX 2
+#define mmLB3_LB_V_COUNTER 0x0c20
+#define mmLB3_LB_V_COUNTER_BASE_IDX 2
+#define mmLB3_LB_SNAPSHOT_V_COUNTER 0x0c21
+#define mmLB3_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
+#define mmLB3_LB_INTERRUPT_MASK 0x0c22
+#define mmLB3_LB_INTERRUPT_MASK_BASE_IDX 2
+#define mmLB3_LB_VLINE_STATUS 0x0c23
+#define mmLB3_LB_VLINE_STATUS_BASE_IDX 2
+#define mmLB3_LB_VLINE2_STATUS 0x0c24
+#define mmLB3_LB_VLINE2_STATUS_BASE_IDX 2
+#define mmLB3_LB_VBLANK_STATUS 0x0c25
+#define mmLB3_LB_VBLANK_STATUS_BASE_IDX 2
+#define mmLB3_LB_SYNC_RESET_SEL 0x0c26
+#define mmLB3_LB_SYNC_RESET_SEL_BASE_IDX 2
+#define mmLB3_LB_BLACK_KEYER_R_CR 0x0c27
+#define mmLB3_LB_BLACK_KEYER_R_CR_BASE_IDX 2
+#define mmLB3_LB_BLACK_KEYER_G_Y 0x0c28
+#define mmLB3_LB_BLACK_KEYER_G_Y_BASE_IDX 2
+#define mmLB3_LB_BLACK_KEYER_B_CB 0x0c29
+#define mmLB3_LB_BLACK_KEYER_B_CB_BASE_IDX 2
+#define mmLB3_LB_KEYER_COLOR_CTRL 0x0c2a
+#define mmLB3_LB_KEYER_COLOR_CTRL_BASE_IDX 2
+#define mmLB3_LB_KEYER_COLOR_R_CR 0x0c2b
+#define mmLB3_LB_KEYER_COLOR_R_CR_BASE_IDX 2
+#define mmLB3_LB_KEYER_COLOR_G_Y 0x0c2c
+#define mmLB3_LB_KEYER_COLOR_G_Y_BASE_IDX 2
+#define mmLB3_LB_KEYER_COLOR_B_CB 0x0c2d
+#define mmLB3_LB_KEYER_COLOR_B_CB_BASE_IDX 2
+#define mmLB3_LB_KEYER_COLOR_REP_R_CR 0x0c2e
+#define mmLB3_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
+#define mmLB3_LB_KEYER_COLOR_REP_G_Y 0x0c2f
+#define mmLB3_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
+#define mmLB3_LB_KEYER_COLOR_REP_B_CB 0x0c30
+#define mmLB3_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
+#define mmLB3_LB_BUFFER_LEVEL_STATUS 0x0c31
+#define mmLB3_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
+#define mmLB3_LB_BUFFER_URGENCY_CTRL 0x0c32
+#define mmLB3_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
+#define mmLB3_LB_BUFFER_URGENCY_STATUS 0x0c33
+#define mmLB3_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
+#define mmLB3_LB_BUFFER_STATUS 0x0c34
+#define mmLB3_LB_BUFFER_STATUS_BASE_IDX 2
+#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x0c35
+#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
+#define mmLB3_MVP_AFR_FLIP_MODE 0x0c36
+#define mmLB3_MVP_AFR_FLIP_MODE_BASE_IDX 2
+#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x0c37
+#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
+#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x0c38
+#define mmLB3_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
+#define mmLB3_DC_MVP_LB_CONTROL 0x0c39
+#define mmLB3_DC_MVP_LB_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcfe3_dispdec
+// base address: 0x1800
+#define mmDCFE3_DCFE_CLOCK_CONTROL 0x0c5a
+#define mmDCFE3_DCFE_CLOCK_CONTROL_BASE_IDX 2
+#define mmDCFE3_DCFE_SOFT_RESET 0x0c5b
+#define mmDCFE3_DCFE_SOFT_RESET_BASE_IDX 2
+#define mmDCFE3_DCFE_MEM_PWR_CTRL 0x0c5d
+#define mmDCFE3_DCFE_MEM_PWR_CTRL_BASE_IDX 2
+#define mmDCFE3_DCFE_MEM_PWR_CTRL2 0x0c5e
+#define mmDCFE3_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
+#define mmDCFE3_DCFE_MEM_PWR_STATUS 0x0c5f
+#define mmDCFE3_DCFE_MEM_PWR_STATUS_BASE_IDX 2
+#define mmDCFE3_DCFE_MISC 0x0c60
+#define mmDCFE3_DCFE_MISC_BASE_IDX 2
+#define mmDCFE3_DCFE_FLUSH 0x0c61
+#define mmDCFE3_DCFE_FLUSH_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_perfmon6_dispdec
+// base address: 0x3138
+#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x0c6e
+#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x0c6f
+#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x0c70
+#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON6_PERFMON_CNTL 0x0c71
+#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON6_PERFMON_CNTL2 0x0c72
+#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x0c73
+#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x0c74
+#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON6_PERFMON_HI 0x0c75
+#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON6_PERFMON_LOW 0x0c76
+#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dmif_pg3_dispdec
+// base address: 0x1800
+#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x0c7a
+#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
+#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x0c7b
+#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
+#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x0c7c
+#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
+#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x0c7d
+#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
+#define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL 0x0c7e
+#define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
+#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x0c7f
+#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
+#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2 0x0c80
+#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
+#define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL 0x0c81
+#define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
+#define mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x0c82
+#define mmDMIF_PG3_DPG_REPEATER_PROGRAM_BASE_IDX 2
+#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL 0x0c86
+#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
+#define mmDMIF_PG3_DPG_DVMM_STATUS 0x0c87
+#define mmDMIF_PG3_DPG_DVMM_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_scl3_dispdec
+// base address: 0x1800
+#define mmSCL3_SCL_COEF_RAM_SELECT 0x0c9a
+#define mmSCL3_SCL_COEF_RAM_SELECT_BASE_IDX 2
+#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x0c9b
+#define mmSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
+#define mmSCL3_SCL_MODE 0x0c9c
+#define mmSCL3_SCL_MODE_BASE_IDX 2
+#define mmSCL3_SCL_TAP_CONTROL 0x0c9d
+#define mmSCL3_SCL_TAP_CONTROL_BASE_IDX 2
+#define mmSCL3_SCL_CONTROL 0x0c9e
+#define mmSCL3_SCL_CONTROL_BASE_IDX 2
+#define mmSCL3_SCL_BYPASS_CONTROL 0x0c9f
+#define mmSCL3_SCL_BYPASS_CONTROL_BASE_IDX 2
+#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x0ca0
+#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x0ca1
+#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
+#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x0ca2
+#define mmSCL3_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
+#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x0ca3
+#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmSCL3_SCL_HORZ_FILTER_INIT 0x0ca4
+#define mmSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2
+#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x0ca5
+#define mmSCL3_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
+#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x0ca6
+#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmSCL3_SCL_VERT_FILTER_INIT 0x0ca7
+#define mmSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2
+#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x0ca8
+#define mmSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
+#define mmSCL3_SCL_ROUND_OFFSET 0x0ca9
+#define mmSCL3_SCL_ROUND_OFFSET_BASE_IDX 2
+#define mmSCL3_SCL_UPDATE 0x0caa
+#define mmSCL3_SCL_UPDATE_BASE_IDX 2
+#define mmSCL3_SCL_F_SHARP_CONTROL 0x0cab
+#define mmSCL3_SCL_F_SHARP_CONTROL_BASE_IDX 2
+#define mmSCL3_SCL_ALU_CONTROL 0x0cac
+#define mmSCL3_SCL_ALU_CONTROL_BASE_IDX 2
+#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x0cad
+#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
+#define mmSCL3_VIEWPORT_START_SECONDARY 0x0cae
+#define mmSCL3_VIEWPORT_START_SECONDARY_BASE_IDX 2
+#define mmSCL3_VIEWPORT_START 0x0caf
+#define mmSCL3_VIEWPORT_START_BASE_IDX 2
+#define mmSCL3_VIEWPORT_SIZE 0x0cb0
+#define mmSCL3_VIEWPORT_SIZE_BASE_IDX 2
+#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x0cb1
+#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x0cb2
+#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+#define mmSCL3_SCL_MODE_CHANGE_DET1 0x0cb3
+#define mmSCL3_SCL_MODE_CHANGE_DET1_BASE_IDX 2
+#define mmSCL3_SCL_MODE_CHANGE_DET2 0x0cb4
+#define mmSCL3_SCL_MODE_CHANGE_DET2_BASE_IDX 2
+#define mmSCL3_SCL_MODE_CHANGE_DET3 0x0cb5
+#define mmSCL3_SCL_MODE_CHANGE_DET3_BASE_IDX 2
+#define mmSCL3_SCL_MODE_CHANGE_MASK 0x0cb6
+#define mmSCL3_SCL_MODE_CHANGE_MASK_BASE_IDX 2
+
+
+// addressBlock: dce_dc_blnd3_dispdec
+// base address: 0x1800
+#define mmBLND3_BLND_CONTROL 0x0cc7
+#define mmBLND3_BLND_CONTROL_BASE_IDX 2
+#define mmBLND3_BLND_SM_CONTROL2 0x0cc8
+#define mmBLND3_BLND_SM_CONTROL2_BASE_IDX 2
+#define mmBLND3_BLND_CONTROL2 0x0cc9
+#define mmBLND3_BLND_CONTROL2_BASE_IDX 2
+#define mmBLND3_BLND_UPDATE 0x0cca
+#define mmBLND3_BLND_UPDATE_BASE_IDX 2
+#define mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x0ccb
+#define mmBLND3_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
+#define mmBLND3_BLND_V_UPDATE_LOCK 0x0ccc
+#define mmBLND3_BLND_V_UPDATE_LOCK_BASE_IDX 2
+#define mmBLND3_BLND_REG_UPDATE_STATUS 0x0ccd
+#define mmBLND3_BLND_REG_UPDATE_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_crtc3_dispdec
+// base address: 0x1800
+#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x0cd2
+#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
+#define mmCRTC3_CRTC_H_TOTAL 0x0cd3
+#define mmCRTC3_CRTC_H_TOTAL_BASE_IDX 2
+#define mmCRTC3_CRTC_H_BLANK_START_END 0x0cd4
+#define mmCRTC3_CRTC_H_BLANK_START_END_BASE_IDX 2
+#define mmCRTC3_CRTC_H_SYNC_A 0x0cd5
+#define mmCRTC3_CRTC_H_SYNC_A_BASE_IDX 2
+#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x0cd6
+#define mmCRTC3_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
+#define mmCRTC3_CRTC_H_SYNC_B 0x0cd7
+#define mmCRTC3_CRTC_H_SYNC_B_BASE_IDX 2
+#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x0cd8
+#define mmCRTC3_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
+#define mmCRTC3_CRTC_VBI_END 0x0cd9
+#define mmCRTC3_CRTC_VBI_END_BASE_IDX 2
+#define mmCRTC3_CRTC_V_TOTAL 0x0cda
+#define mmCRTC3_CRTC_V_TOTAL_BASE_IDX 2
+#define mmCRTC3_CRTC_V_TOTAL_MIN 0x0cdb
+#define mmCRTC3_CRTC_V_TOTAL_MIN_BASE_IDX 2
+#define mmCRTC3_CRTC_V_TOTAL_MAX 0x0cdc
+#define mmCRTC3_CRTC_V_TOTAL_MAX_BASE_IDX 2
+#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x0cdd
+#define mmCRTC3_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x0cde
+#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
+#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x0cdf
+#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+#define mmCRTC3_CRTC_V_BLANK_START_END 0x0ce0
+#define mmCRTC3_CRTC_V_BLANK_START_END_BASE_IDX 2
+#define mmCRTC3_CRTC_V_SYNC_A 0x0ce1
+#define mmCRTC3_CRTC_V_SYNC_A_BASE_IDX 2
+#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x0ce2
+#define mmCRTC3_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
+#define mmCRTC3_CRTC_V_SYNC_B 0x0ce3
+#define mmCRTC3_CRTC_V_SYNC_B_BASE_IDX 2
+#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x0ce4
+#define mmCRTC3_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
+#define mmCRTC3_CRTC_DTMTEST_CNTL 0x0ce5
+#define mmCRTC3_CRTC_DTMTEST_CNTL_BASE_IDX 2
+#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x0ce6
+#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
+#define mmCRTC3_CRTC_TRIGA_CNTL 0x0ce7
+#define mmCRTC3_CRTC_TRIGA_CNTL_BASE_IDX 2
+#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x0ce8
+#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
+#define mmCRTC3_CRTC_TRIGB_CNTL 0x0ce9
+#define mmCRTC3_CRTC_TRIGB_CNTL_BASE_IDX 2
+#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x0cea
+#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
+#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x0ceb
+#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+#define mmCRTC3_CRTC_FLOW_CONTROL 0x0cec
+#define mmCRTC3_CRTC_FLOW_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x0ced
+#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+#define mmCRTC3_CRTC_AVSYNC_COUNTER 0x0cee
+#define mmCRTC3_CRTC_AVSYNC_COUNTER_BASE_IDX 2
+#define mmCRTC3_CRTC_CONTROL 0x0cef
+#define mmCRTC3_CRTC_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_BLANK_CONTROL 0x0cf0
+#define mmCRTC3_CRTC_BLANK_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x0cf1
+#define mmCRTC3_CRTC_INTERLACE_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_INTERLACE_STATUS 0x0cf2
+#define mmCRTC3_CRTC_INTERLACE_STATUS_BASE_IDX 2
+#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x0cf3
+#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x0cf4
+#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
+#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x0cf5
+#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
+#define mmCRTC3_CRTC_STATUS 0x0cf6
+#define mmCRTC3_CRTC_STATUS_BASE_IDX 2
+#define mmCRTC3_CRTC_STATUS_POSITION 0x0cf7
+#define mmCRTC3_CRTC_STATUS_POSITION_BASE_IDX 2
+#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x0cf8
+#define mmCRTC3_CRTC_NOM_VERT_POSITION_BASE_IDX 2
+#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x0cf9
+#define mmCRTC3_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
+#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x0cfa
+#define mmCRTC3_CRTC_STATUS_VF_COUNT_BASE_IDX 2
+#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x0cfb
+#define mmCRTC3_CRTC_STATUS_HV_COUNT_BASE_IDX 2
+#define mmCRTC3_CRTC_COUNT_CONTROL 0x0cfc
+#define mmCRTC3_CRTC_COUNT_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_COUNT_RESET 0x0cfd
+#define mmCRTC3_CRTC_COUNT_RESET_BASE_IDX 2
+#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x0cfe
+#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x0cff
+#define mmCRTC3_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_STEREO_STATUS 0x0d00
+#define mmCRTC3_CRTC_STEREO_STATUS_BASE_IDX 2
+#define mmCRTC3_CRTC_STEREO_CONTROL 0x0d01
+#define mmCRTC3_CRTC_STEREO_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x0d02
+#define mmCRTC3_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
+#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x0d03
+#define mmCRTC3_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x0d04
+#define mmCRTC3_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
+#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x0d05
+#define mmCRTC3_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
+#define mmCRTC3_CRTC_START_LINE_CONTROL 0x0d06
+#define mmCRTC3_CRTC_START_LINE_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x0d07
+#define mmCRTC3_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_UPDATE_LOCK 0x0d08
+#define mmCRTC3_CRTC_UPDATE_LOCK_BASE_IDX 2
+#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x0d09
+#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x0d0a
+#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
+#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x0d0b
+#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x0d0c
+#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
+#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x0d0d
+#define mmCRTC3_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
+#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK 0x0d0e
+#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
+#define mmCRTC3_CRTC_MASTER_UPDATE_MODE 0x0d0f
+#define mmCRTC3_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
+#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x0d10
+#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
+#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0d11
+#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
+#define mmCRTC3_CRTC_MVP_STATUS 0x0d12
+#define mmCRTC3_CRTC_MVP_STATUS_BASE_IDX 2
+#define mmCRTC3_CRTC_MASTER_EN 0x0d13
+#define mmCRTC3_CRTC_MASTER_EN_BASE_IDX 2
+#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x0d14
+#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
+#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x0d15
+#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
+#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x0d17
+#define mmCRTC3_CRTC_OVERSCAN_COLOR_BASE_IDX 2
+#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x0d18
+#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
+#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x0d19
+#define mmCRTC3_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
+#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x0d1a
+#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+#define mmCRTC3_CRTC_BLACK_COLOR 0x0d1b
+#define mmCRTC3_CRTC_BLACK_COLOR_BASE_IDX 2
+#define mmCRTC3_CRTC_BLACK_COLOR_EXT 0x0d1c
+#define mmCRTC3_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x0d1d
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x0d1e
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x0d1f
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0d20
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0d21
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0d22
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_CRC_CNTL 0x0d23
+#define mmCRTC3_CRTC_CRC_CNTL_BASE_IDX 2
+#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x0d24
+#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0d25
+#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x0d26
+#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0d27
+#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_CRC0_DATA_RG 0x0d28
+#define mmCRTC3_CRTC_CRC0_DATA_RG_BASE_IDX 2
+#define mmCRTC3_CRTC_CRC0_DATA_B 0x0d29
+#define mmCRTC3_CRTC_CRC0_DATA_B_BASE_IDX 2
+#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x0d2a
+#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x0d2b
+#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x0d2c
+#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x0d2d
+#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_CRC1_DATA_RG 0x0d2e
+#define mmCRTC3_CRTC_CRC1_DATA_RG_BASE_IDX 2
+#define mmCRTC3_CRTC_CRC1_DATA_B 0x0d2f
+#define mmCRTC3_CRTC_CRC1_DATA_B_BASE_IDX 2
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x0d30
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0d31
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0d32
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0d33
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0d34
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0d35
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x0d36
+#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x0d37
+#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x0d38
+#define mmCRTC3_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
+#define mmCRTC3_CRTC_GSL_WINDOW 0x0d39
+#define mmCRTC3_CRTC_GSL_WINDOW_BASE_IDX 2
+#define mmCRTC3_CRTC_GSL_CONTROL 0x0d3a
+#define mmCRTC3_CRTC_GSL_CONTROL_BASE_IDX 2
+#define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS 0x0d3d
+#define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
+#define mmCRTC3_CRTC_DRR_CONTROL 0x0d3e
+#define mmCRTC3_CRTC_DRR_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_fmt3_dispdec
+// base address: 0x1800
+#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x0d42
+#define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
+#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x0d43
+#define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
+#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x0d44
+#define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
+#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x0d45
+#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
+#define mmFMT3_FMT_CONTROL 0x0d46
+#define mmFMT3_FMT_CONTROL_BASE_IDX 2
+#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x0d47
+#define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
+#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x0d48
+#define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
+#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x0d49
+#define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
+#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x0d4a
+#define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
+#define mmFMT3_FMT_CLAMP_CNTL 0x0d4e
+#define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX 2
+#define mmFMT3_FMT_CRC_CNTL 0x0d4f
+#define mmFMT3_FMT_CRC_CNTL_BASE_IDX 2
+#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x0d50
+#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
+#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0d51
+#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
+#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x0d52
+#define mmFMT3_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
+#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x0d53
+#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
+#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0d54
+#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
+#define mmFMT3_FMT_420_HBLANK_EARLY_START 0x0d55
+#define mmFMT3_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcp4_dispdec
+// base address: 0x2000
+#define mmDCP4_GRPH_ENABLE 0x0d5a
+#define mmDCP4_GRPH_ENABLE_BASE_IDX 2
+#define mmDCP4_GRPH_CONTROL 0x0d5b
+#define mmDCP4_GRPH_CONTROL_BASE_IDX 2
+#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x0d5c
+#define mmDCP4_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
+#define mmDCP4_GRPH_SWAP_CNTL 0x0d5d
+#define mmDCP4_GRPH_SWAP_CNTL_BASE_IDX 2
+#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x0d5e
+#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x0d5f
+#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP4_GRPH_PITCH 0x0d60
+#define mmDCP4_GRPH_PITCH_BASE_IDX 2
+#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0d61
+#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0d62
+#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x0d63
+#define mmDCP4_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
+#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x0d64
+#define mmDCP4_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
+#define mmDCP4_GRPH_X_START 0x0d65
+#define mmDCP4_GRPH_X_START_BASE_IDX 2
+#define mmDCP4_GRPH_Y_START 0x0d66
+#define mmDCP4_GRPH_Y_START_BASE_IDX 2
+#define mmDCP4_GRPH_X_END 0x0d67
+#define mmDCP4_GRPH_X_END_BASE_IDX 2
+#define mmDCP4_GRPH_Y_END 0x0d68
+#define mmDCP4_GRPH_Y_END_BASE_IDX 2
+#define mmDCP4_INPUT_GAMMA_CONTROL 0x0d69
+#define mmDCP4_INPUT_GAMMA_CONTROL_BASE_IDX 2
+#define mmDCP4_GRPH_UPDATE 0x0d6a
+#define mmDCP4_GRPH_UPDATE_BASE_IDX 2
+#define mmDCP4_GRPH_FLIP_CONTROL 0x0d6b
+#define mmDCP4_GRPH_FLIP_CONTROL_BASE_IDX 2
+#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x0d6c
+#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
+#define mmDCP4_GRPH_DFQ_CONTROL 0x0d6d
+#define mmDCP4_GRPH_DFQ_CONTROL_BASE_IDX 2
+#define mmDCP4_GRPH_DFQ_STATUS 0x0d6e
+#define mmDCP4_GRPH_DFQ_STATUS_BASE_IDX 2
+#define mmDCP4_GRPH_INTERRUPT_STATUS 0x0d6f
+#define mmDCP4_GRPH_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x0d70
+#define mmDCP4_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0d71
+#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
+#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x0d72
+#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP4_GRPH_COMPRESS_PITCH 0x0d73
+#define mmDCP4_GRPH_COMPRESS_PITCH_BASE_IDX 2
+#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0d74
+#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0d75
+#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
+#define mmDCP4_PRESCALE_GRPH_CONTROL 0x0d76
+#define mmDCP4_PRESCALE_GRPH_CONTROL_BASE_IDX 2
+#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x0d77
+#define mmDCP4_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
+#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x0d78
+#define mmDCP4_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
+#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x0d79
+#define mmDCP4_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
+#define mmDCP4_INPUT_CSC_CONTROL 0x0d7a
+#define mmDCP4_INPUT_CSC_CONTROL_BASE_IDX 2
+#define mmDCP4_INPUT_CSC_C11_C12 0x0d7b
+#define mmDCP4_INPUT_CSC_C11_C12_BASE_IDX 2
+#define mmDCP4_INPUT_CSC_C13_C14 0x0d7c
+#define mmDCP4_INPUT_CSC_C13_C14_BASE_IDX 2
+#define mmDCP4_INPUT_CSC_C21_C22 0x0d7d
+#define mmDCP4_INPUT_CSC_C21_C22_BASE_IDX 2
+#define mmDCP4_INPUT_CSC_C23_C24 0x0d7e
+#define mmDCP4_INPUT_CSC_C23_C24_BASE_IDX 2
+#define mmDCP4_INPUT_CSC_C31_C32 0x0d7f
+#define mmDCP4_INPUT_CSC_C31_C32_BASE_IDX 2
+#define mmDCP4_INPUT_CSC_C33_C34 0x0d80
+#define mmDCP4_INPUT_CSC_C33_C34_BASE_IDX 2
+#define mmDCP4_OUTPUT_CSC_CONTROL 0x0d81
+#define mmDCP4_OUTPUT_CSC_CONTROL_BASE_IDX 2
+#define mmDCP4_OUTPUT_CSC_C11_C12 0x0d82
+#define mmDCP4_OUTPUT_CSC_C11_C12_BASE_IDX 2
+#define mmDCP4_OUTPUT_CSC_C13_C14 0x0d83
+#define mmDCP4_OUTPUT_CSC_C13_C14_BASE_IDX 2
+#define mmDCP4_OUTPUT_CSC_C21_C22 0x0d84
+#define mmDCP4_OUTPUT_CSC_C21_C22_BASE_IDX 2
+#define mmDCP4_OUTPUT_CSC_C23_C24 0x0d85
+#define mmDCP4_OUTPUT_CSC_C23_C24_BASE_IDX 2
+#define mmDCP4_OUTPUT_CSC_C31_C32 0x0d86
+#define mmDCP4_OUTPUT_CSC_C31_C32_BASE_IDX 2
+#define mmDCP4_OUTPUT_CSC_C33_C34 0x0d87
+#define mmDCP4_OUTPUT_CSC_C33_C34_BASE_IDX 2
+#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x0d88
+#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
+#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x0d89
+#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
+#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x0d8a
+#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
+#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x0d8b
+#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
+#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x0d8c
+#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
+#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x0d8d
+#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
+#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x0d8e
+#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
+#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x0d8f
+#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
+#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x0d90
+#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
+#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x0d91
+#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
+#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x0d92
+#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
+#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x0d93
+#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
+#define mmDCP4_DENORM_CONTROL 0x0d94
+#define mmDCP4_DENORM_CONTROL_BASE_IDX 2
+#define mmDCP4_OUT_ROUND_CONTROL 0x0d95
+#define mmDCP4_OUT_ROUND_CONTROL_BASE_IDX 2
+#define mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x0d96
+#define mmDCP4_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
+#define mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x0d97
+#define mmDCP4_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
+#define mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x0d98
+#define mmDCP4_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
+#define mmDCP4_KEY_CONTROL 0x0d99
+#define mmDCP4_KEY_CONTROL_BASE_IDX 2
+#define mmDCP4_KEY_RANGE_ALPHA 0x0d9a
+#define mmDCP4_KEY_RANGE_ALPHA_BASE_IDX 2
+#define mmDCP4_KEY_RANGE_RED 0x0d9b
+#define mmDCP4_KEY_RANGE_RED_BASE_IDX 2
+#define mmDCP4_KEY_RANGE_GREEN 0x0d9c
+#define mmDCP4_KEY_RANGE_GREEN_BASE_IDX 2
+#define mmDCP4_KEY_RANGE_BLUE 0x0d9d
+#define mmDCP4_KEY_RANGE_BLUE_BASE_IDX 2
+#define mmDCP4_DEGAMMA_CONTROL 0x0d9e
+#define mmDCP4_DEGAMMA_CONTROL_BASE_IDX 2
+#define mmDCP4_GAMUT_REMAP_CONTROL 0x0d9f
+#define mmDCP4_GAMUT_REMAP_CONTROL_BASE_IDX 2
+#define mmDCP4_GAMUT_REMAP_C11_C12 0x0da0
+#define mmDCP4_GAMUT_REMAP_C11_C12_BASE_IDX 2
+#define mmDCP4_GAMUT_REMAP_C13_C14 0x0da1
+#define mmDCP4_GAMUT_REMAP_C13_C14_BASE_IDX 2
+#define mmDCP4_GAMUT_REMAP_C21_C22 0x0da2
+#define mmDCP4_GAMUT_REMAP_C21_C22_BASE_IDX 2
+#define mmDCP4_GAMUT_REMAP_C23_C24 0x0da3
+#define mmDCP4_GAMUT_REMAP_C23_C24_BASE_IDX 2
+#define mmDCP4_GAMUT_REMAP_C31_C32 0x0da4
+#define mmDCP4_GAMUT_REMAP_C31_C32_BASE_IDX 2
+#define mmDCP4_GAMUT_REMAP_C33_C34 0x0da5
+#define mmDCP4_GAMUT_REMAP_C33_C34_BASE_IDX 2
+#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x0da6
+#define mmDCP4_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
+#define mmDCP4_DCP_RANDOM_SEEDS 0x0da7
+#define mmDCP4_DCP_RANDOM_SEEDS_BASE_IDX 2
+#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x0da8
+#define mmDCP4_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
+#define mmDCP4_CUR_CONTROL 0x0da9
+#define mmDCP4_CUR_CONTROL_BASE_IDX 2
+#define mmDCP4_CUR_SURFACE_ADDRESS 0x0daa
+#define mmDCP4_CUR_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP4_CUR_SIZE 0x0dab
+#define mmDCP4_CUR_SIZE_BASE_IDX 2
+#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x0dac
+#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP4_CUR_POSITION 0x0dad
+#define mmDCP4_CUR_POSITION_BASE_IDX 2
+#define mmDCP4_CUR_HOT_SPOT 0x0dae
+#define mmDCP4_CUR_HOT_SPOT_BASE_IDX 2
+#define mmDCP4_CUR_COLOR1 0x0daf
+#define mmDCP4_CUR_COLOR1_BASE_IDX 2
+#define mmDCP4_CUR_COLOR2 0x0db0
+#define mmDCP4_CUR_COLOR2_BASE_IDX 2
+#define mmDCP4_CUR_UPDATE 0x0db1
+#define mmDCP4_CUR_UPDATE_BASE_IDX 2
+#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x0dbb
+#define mmDCP4_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
+#define mmDCP4_CUR_STEREO_CONTROL 0x0dbc
+#define mmDCP4_CUR_STEREO_CONTROL_BASE_IDX 2
+#define mmDCP4_DC_LUT_RW_MODE 0x0dbe
+#define mmDCP4_DC_LUT_RW_MODE_BASE_IDX 2
+#define mmDCP4_DC_LUT_RW_INDEX 0x0dbf
+#define mmDCP4_DC_LUT_RW_INDEX_BASE_IDX 2
+#define mmDCP4_DC_LUT_SEQ_COLOR 0x0dc0
+#define mmDCP4_DC_LUT_SEQ_COLOR_BASE_IDX 2
+#define mmDCP4_DC_LUT_PWL_DATA 0x0dc1
+#define mmDCP4_DC_LUT_PWL_DATA_BASE_IDX 2
+#define mmDCP4_DC_LUT_30_COLOR 0x0dc2
+#define mmDCP4_DC_LUT_30_COLOR_BASE_IDX 2
+#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x0dc3
+#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
+#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x0dc4
+#define mmDCP4_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmDCP4_DC_LUT_AUTOFILL 0x0dc5
+#define mmDCP4_DC_LUT_AUTOFILL_BASE_IDX 2
+#define mmDCP4_DC_LUT_CONTROL 0x0dc6
+#define mmDCP4_DC_LUT_CONTROL_BASE_IDX 2
+#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x0dc7
+#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
+#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x0dc8
+#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
+#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x0dc9
+#define mmDCP4_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
+#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x0dca
+#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
+#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x0dcb
+#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
+#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x0dcc
+#define mmDCP4_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
+#define mmDCP4_DCP_CRC_CONTROL 0x0dcd
+#define mmDCP4_DCP_CRC_CONTROL_BASE_IDX 2
+#define mmDCP4_DCP_CRC_MASK 0x0dce
+#define mmDCP4_DCP_CRC_MASK_BASE_IDX 2
+#define mmDCP4_DCP_CRC_CURRENT 0x0dcf
+#define mmDCP4_DCP_CRC_CURRENT_BASE_IDX 2
+#define mmDCP4_DVMM_PTE_CONTROL 0x0dd0
+#define mmDCP4_DVMM_PTE_CONTROL_BASE_IDX 2
+#define mmDCP4_DCP_CRC_LAST 0x0dd1
+#define mmDCP4_DCP_CRC_LAST_BASE_IDX 2
+#define mmDCP4_DVMM_PTE_ARB_CONTROL 0x0dd2
+#define mmDCP4_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
+#define mmDCP4_GRPH_FLIP_RATE_CNTL 0x0dd4
+#define mmDCP4_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
+#define mmDCP4_DCP_GSL_CONTROL 0x0dd5
+#define mmDCP4_DCP_GSL_CONTROL_BASE_IDX 2
+#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x0dd6
+#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
+#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x0ddc
+#define mmDCP4_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
+#define mmDCP4_HW_ROTATION 0x0dde
+#define mmDCP4_HW_ROTATION_BASE_IDX 2
+#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x0ddf
+#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
+#define mmDCP4_REGAMMA_CONTROL 0x0de0
+#define mmDCP4_REGAMMA_CONTROL_BASE_IDX 2
+#define mmDCP4_REGAMMA_LUT_INDEX 0x0de1
+#define mmDCP4_REGAMMA_LUT_INDEX_BASE_IDX 2
+#define mmDCP4_REGAMMA_LUT_DATA 0x0de2
+#define mmDCP4_REGAMMA_LUT_DATA_BASE_IDX 2
+#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x0de3
+#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x0de4
+#define mmDCP4_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x0de5
+#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x0de6
+#define mmDCP4_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x0de7
+#define mmDCP4_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x0de8
+#define mmDCP4_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x0de9
+#define mmDCP4_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x0dea
+#define mmDCP4_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x0deb
+#define mmDCP4_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x0dec
+#define mmDCP4_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x0ded
+#define mmDCP4_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x0dee
+#define mmDCP4_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x0def
+#define mmDCP4_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x0df0
+#define mmDCP4_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x0df1
+#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x0df2
+#define mmDCP4_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x0df3
+#define mmDCP4_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x0df4
+#define mmDCP4_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x0df5
+#define mmDCP4_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x0df6
+#define mmDCP4_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x0df7
+#define mmDCP4_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x0df8
+#define mmDCP4_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x0df9
+#define mmDCP4_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x0dfa
+#define mmDCP4_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
+#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x0dfb
+#define mmDCP4_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
+#define mmDCP4_ALPHA_CONTROL 0x0dfc
+#define mmDCP4_ALPHA_CONTROL_BASE_IDX 2
+#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x0dfd
+#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x0dfe
+#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x0dff
+#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
+#define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT 0x0e00
+#define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
+#define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY 0x0e01
+#define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
+#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL 0x0e02
+#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
+#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT 0x0e03
+#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_lb4_dispdec
+// base address: 0x2000
+#define mmLB4_LB_DATA_FORMAT 0x0e1a
+#define mmLB4_LB_DATA_FORMAT_BASE_IDX 2
+#define mmLB4_LB_MEMORY_CTRL 0x0e1b
+#define mmLB4_LB_MEMORY_CTRL_BASE_IDX 2
+#define mmLB4_LB_MEMORY_SIZE_STATUS 0x0e1c
+#define mmLB4_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
+#define mmLB4_LB_DESKTOP_HEIGHT 0x0e1d
+#define mmLB4_LB_DESKTOP_HEIGHT_BASE_IDX 2
+#define mmLB4_LB_VLINE_START_END 0x0e1e
+#define mmLB4_LB_VLINE_START_END_BASE_IDX 2
+#define mmLB4_LB_VLINE2_START_END 0x0e1f
+#define mmLB4_LB_VLINE2_START_END_BASE_IDX 2
+#define mmLB4_LB_V_COUNTER 0x0e20
+#define mmLB4_LB_V_COUNTER_BASE_IDX 2
+#define mmLB4_LB_SNAPSHOT_V_COUNTER 0x0e21
+#define mmLB4_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
+#define mmLB4_LB_INTERRUPT_MASK 0x0e22
+#define mmLB4_LB_INTERRUPT_MASK_BASE_IDX 2
+#define mmLB4_LB_VLINE_STATUS 0x0e23
+#define mmLB4_LB_VLINE_STATUS_BASE_IDX 2
+#define mmLB4_LB_VLINE2_STATUS 0x0e24
+#define mmLB4_LB_VLINE2_STATUS_BASE_IDX 2
+#define mmLB4_LB_VBLANK_STATUS 0x0e25
+#define mmLB4_LB_VBLANK_STATUS_BASE_IDX 2
+#define mmLB4_LB_SYNC_RESET_SEL 0x0e26
+#define mmLB4_LB_SYNC_RESET_SEL_BASE_IDX 2
+#define mmLB4_LB_BLACK_KEYER_R_CR 0x0e27
+#define mmLB4_LB_BLACK_KEYER_R_CR_BASE_IDX 2
+#define mmLB4_LB_BLACK_KEYER_G_Y 0x0e28
+#define mmLB4_LB_BLACK_KEYER_G_Y_BASE_IDX 2
+#define mmLB4_LB_BLACK_KEYER_B_CB 0x0e29
+#define mmLB4_LB_BLACK_KEYER_B_CB_BASE_IDX 2
+#define mmLB4_LB_KEYER_COLOR_CTRL 0x0e2a
+#define mmLB4_LB_KEYER_COLOR_CTRL_BASE_IDX 2
+#define mmLB4_LB_KEYER_COLOR_R_CR 0x0e2b
+#define mmLB4_LB_KEYER_COLOR_R_CR_BASE_IDX 2
+#define mmLB4_LB_KEYER_COLOR_G_Y 0x0e2c
+#define mmLB4_LB_KEYER_COLOR_G_Y_BASE_IDX 2
+#define mmLB4_LB_KEYER_COLOR_B_CB 0x0e2d
+#define mmLB4_LB_KEYER_COLOR_B_CB_BASE_IDX 2
+#define mmLB4_LB_KEYER_COLOR_REP_R_CR 0x0e2e
+#define mmLB4_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
+#define mmLB4_LB_KEYER_COLOR_REP_G_Y 0x0e2f
+#define mmLB4_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
+#define mmLB4_LB_KEYER_COLOR_REP_B_CB 0x0e30
+#define mmLB4_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
+#define mmLB4_LB_BUFFER_LEVEL_STATUS 0x0e31
+#define mmLB4_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
+#define mmLB4_LB_BUFFER_URGENCY_CTRL 0x0e32
+#define mmLB4_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
+#define mmLB4_LB_BUFFER_URGENCY_STATUS 0x0e33
+#define mmLB4_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
+#define mmLB4_LB_BUFFER_STATUS 0x0e34
+#define mmLB4_LB_BUFFER_STATUS_BASE_IDX 2
+#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x0e35
+#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
+#define mmLB4_MVP_AFR_FLIP_MODE 0x0e36
+#define mmLB4_MVP_AFR_FLIP_MODE_BASE_IDX 2
+#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x0e37
+#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
+#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x0e38
+#define mmLB4_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
+#define mmLB4_DC_MVP_LB_CONTROL 0x0e39
+#define mmLB4_DC_MVP_LB_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcfe4_dispdec
+// base address: 0x2000
+#define mmDCFE4_DCFE_CLOCK_CONTROL 0x0e5a
+#define mmDCFE4_DCFE_CLOCK_CONTROL_BASE_IDX 2
+#define mmDCFE4_DCFE_SOFT_RESET 0x0e5b
+#define mmDCFE4_DCFE_SOFT_RESET_BASE_IDX 2
+#define mmDCFE4_DCFE_MEM_PWR_CTRL 0x0e5d
+#define mmDCFE4_DCFE_MEM_PWR_CTRL_BASE_IDX 2
+#define mmDCFE4_DCFE_MEM_PWR_CTRL2 0x0e5e
+#define mmDCFE4_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
+#define mmDCFE4_DCFE_MEM_PWR_STATUS 0x0e5f
+#define mmDCFE4_DCFE_MEM_PWR_STATUS_BASE_IDX 2
+#define mmDCFE4_DCFE_MISC 0x0e60
+#define mmDCFE4_DCFE_MISC_BASE_IDX 2
+#define mmDCFE4_DCFE_FLUSH 0x0e61
+#define mmDCFE4_DCFE_FLUSH_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_perfmon7_dispdec
+// base address: 0x3938
+#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x0e6e
+#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x0e6f
+#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x0e70
+#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON7_PERFMON_CNTL 0x0e71
+#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON7_PERFMON_CNTL2 0x0e72
+#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x0e73
+#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x0e74
+#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON7_PERFMON_HI 0x0e75
+#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON7_PERFMON_LOW 0x0e76
+#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dmif_pg4_dispdec
+// base address: 0x2000
+#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x0e7a
+#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
+#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x0e7b
+#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
+#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x0e7c
+#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
+#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x0e7d
+#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
+#define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL 0x0e7e
+#define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
+#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x0e7f
+#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
+#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2 0x0e80
+#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
+#define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL 0x0e81
+#define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
+#define mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x0e82
+#define mmDMIF_PG4_DPG_REPEATER_PROGRAM_BASE_IDX 2
+#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL 0x0e86
+#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
+#define mmDMIF_PG4_DPG_DVMM_STATUS 0x0e87
+#define mmDMIF_PG4_DPG_DVMM_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_scl4_dispdec
+// base address: 0x2000
+#define mmSCL4_SCL_COEF_RAM_SELECT 0x0e9a
+#define mmSCL4_SCL_COEF_RAM_SELECT_BASE_IDX 2
+#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x0e9b
+#define mmSCL4_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
+#define mmSCL4_SCL_MODE 0x0e9c
+#define mmSCL4_SCL_MODE_BASE_IDX 2
+#define mmSCL4_SCL_TAP_CONTROL 0x0e9d
+#define mmSCL4_SCL_TAP_CONTROL_BASE_IDX 2
+#define mmSCL4_SCL_CONTROL 0x0e9e
+#define mmSCL4_SCL_CONTROL_BASE_IDX 2
+#define mmSCL4_SCL_BYPASS_CONTROL 0x0e9f
+#define mmSCL4_SCL_BYPASS_CONTROL_BASE_IDX 2
+#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x0ea0
+#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x0ea1
+#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
+#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x0ea2
+#define mmSCL4_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
+#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x0ea3
+#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmSCL4_SCL_HORZ_FILTER_INIT 0x0ea4
+#define mmSCL4_SCL_HORZ_FILTER_INIT_BASE_IDX 2
+#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x0ea5
+#define mmSCL4_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
+#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x0ea6
+#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmSCL4_SCL_VERT_FILTER_INIT 0x0ea7
+#define mmSCL4_SCL_VERT_FILTER_INIT_BASE_IDX 2
+#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x0ea8
+#define mmSCL4_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
+#define mmSCL4_SCL_ROUND_OFFSET 0x0ea9
+#define mmSCL4_SCL_ROUND_OFFSET_BASE_IDX 2
+#define mmSCL4_SCL_UPDATE 0x0eaa
+#define mmSCL4_SCL_UPDATE_BASE_IDX 2
+#define mmSCL4_SCL_F_SHARP_CONTROL 0x0eab
+#define mmSCL4_SCL_F_SHARP_CONTROL_BASE_IDX 2
+#define mmSCL4_SCL_ALU_CONTROL 0x0eac
+#define mmSCL4_SCL_ALU_CONTROL_BASE_IDX 2
+#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x0ead
+#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
+#define mmSCL4_VIEWPORT_START_SECONDARY 0x0eae
+#define mmSCL4_VIEWPORT_START_SECONDARY_BASE_IDX 2
+#define mmSCL4_VIEWPORT_START 0x0eaf
+#define mmSCL4_VIEWPORT_START_BASE_IDX 2
+#define mmSCL4_VIEWPORT_SIZE 0x0eb0
+#define mmSCL4_VIEWPORT_SIZE_BASE_IDX 2
+#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x0eb1
+#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x0eb2
+#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+#define mmSCL4_SCL_MODE_CHANGE_DET1 0x0eb3
+#define mmSCL4_SCL_MODE_CHANGE_DET1_BASE_IDX 2
+#define mmSCL4_SCL_MODE_CHANGE_DET2 0x0eb4
+#define mmSCL4_SCL_MODE_CHANGE_DET2_BASE_IDX 2
+#define mmSCL4_SCL_MODE_CHANGE_DET3 0x0eb5
+#define mmSCL4_SCL_MODE_CHANGE_DET3_BASE_IDX 2
+#define mmSCL4_SCL_MODE_CHANGE_MASK 0x0eb6
+#define mmSCL4_SCL_MODE_CHANGE_MASK_BASE_IDX 2
+
+
+// addressBlock: dce_dc_blnd4_dispdec
+// base address: 0x2000
+#define mmBLND4_BLND_CONTROL 0x0ec7
+#define mmBLND4_BLND_CONTROL_BASE_IDX 2
+#define mmBLND4_BLND_SM_CONTROL2 0x0ec8
+#define mmBLND4_BLND_SM_CONTROL2_BASE_IDX 2
+#define mmBLND4_BLND_CONTROL2 0x0ec9
+#define mmBLND4_BLND_CONTROL2_BASE_IDX 2
+#define mmBLND4_BLND_UPDATE 0x0eca
+#define mmBLND4_BLND_UPDATE_BASE_IDX 2
+#define mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x0ecb
+#define mmBLND4_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
+#define mmBLND4_BLND_V_UPDATE_LOCK 0x0ecc
+#define mmBLND4_BLND_V_UPDATE_LOCK_BASE_IDX 2
+#define mmBLND4_BLND_REG_UPDATE_STATUS 0x0ecd
+#define mmBLND4_BLND_REG_UPDATE_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_crtc4_dispdec
+// base address: 0x2000
+#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x0ed2
+#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
+#define mmCRTC4_CRTC_H_TOTAL 0x0ed3
+#define mmCRTC4_CRTC_H_TOTAL_BASE_IDX 2
+#define mmCRTC4_CRTC_H_BLANK_START_END 0x0ed4
+#define mmCRTC4_CRTC_H_BLANK_START_END_BASE_IDX 2
+#define mmCRTC4_CRTC_H_SYNC_A 0x0ed5
+#define mmCRTC4_CRTC_H_SYNC_A_BASE_IDX 2
+#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x0ed6
+#define mmCRTC4_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
+#define mmCRTC4_CRTC_H_SYNC_B 0x0ed7
+#define mmCRTC4_CRTC_H_SYNC_B_BASE_IDX 2
+#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x0ed8
+#define mmCRTC4_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
+#define mmCRTC4_CRTC_VBI_END 0x0ed9
+#define mmCRTC4_CRTC_VBI_END_BASE_IDX 2
+#define mmCRTC4_CRTC_V_TOTAL 0x0eda
+#define mmCRTC4_CRTC_V_TOTAL_BASE_IDX 2
+#define mmCRTC4_CRTC_V_TOTAL_MIN 0x0edb
+#define mmCRTC4_CRTC_V_TOTAL_MIN_BASE_IDX 2
+#define mmCRTC4_CRTC_V_TOTAL_MAX 0x0edc
+#define mmCRTC4_CRTC_V_TOTAL_MAX_BASE_IDX 2
+#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x0edd
+#define mmCRTC4_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x0ede
+#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
+#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x0edf
+#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+#define mmCRTC4_CRTC_V_BLANK_START_END 0x0ee0
+#define mmCRTC4_CRTC_V_BLANK_START_END_BASE_IDX 2
+#define mmCRTC4_CRTC_V_SYNC_A 0x0ee1
+#define mmCRTC4_CRTC_V_SYNC_A_BASE_IDX 2
+#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x0ee2
+#define mmCRTC4_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
+#define mmCRTC4_CRTC_V_SYNC_B 0x0ee3
+#define mmCRTC4_CRTC_V_SYNC_B_BASE_IDX 2
+#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x0ee4
+#define mmCRTC4_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
+#define mmCRTC4_CRTC_DTMTEST_CNTL 0x0ee5
+#define mmCRTC4_CRTC_DTMTEST_CNTL_BASE_IDX 2
+#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x0ee6
+#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
+#define mmCRTC4_CRTC_TRIGA_CNTL 0x0ee7
+#define mmCRTC4_CRTC_TRIGA_CNTL_BASE_IDX 2
+#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x0ee8
+#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
+#define mmCRTC4_CRTC_TRIGB_CNTL 0x0ee9
+#define mmCRTC4_CRTC_TRIGB_CNTL_BASE_IDX 2
+#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x0eea
+#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
+#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x0eeb
+#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+#define mmCRTC4_CRTC_FLOW_CONTROL 0x0eec
+#define mmCRTC4_CRTC_FLOW_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x0eed
+#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+#define mmCRTC4_CRTC_AVSYNC_COUNTER 0x0eee
+#define mmCRTC4_CRTC_AVSYNC_COUNTER_BASE_IDX 2
+#define mmCRTC4_CRTC_CONTROL 0x0eef
+#define mmCRTC4_CRTC_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_BLANK_CONTROL 0x0ef0
+#define mmCRTC4_CRTC_BLANK_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x0ef1
+#define mmCRTC4_CRTC_INTERLACE_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_INTERLACE_STATUS 0x0ef2
+#define mmCRTC4_CRTC_INTERLACE_STATUS_BASE_IDX 2
+#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x0ef3
+#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x0ef4
+#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
+#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x0ef5
+#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
+#define mmCRTC4_CRTC_STATUS 0x0ef6
+#define mmCRTC4_CRTC_STATUS_BASE_IDX 2
+#define mmCRTC4_CRTC_STATUS_POSITION 0x0ef7
+#define mmCRTC4_CRTC_STATUS_POSITION_BASE_IDX 2
+#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x0ef8
+#define mmCRTC4_CRTC_NOM_VERT_POSITION_BASE_IDX 2
+#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x0ef9
+#define mmCRTC4_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
+#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x0efa
+#define mmCRTC4_CRTC_STATUS_VF_COUNT_BASE_IDX 2
+#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x0efb
+#define mmCRTC4_CRTC_STATUS_HV_COUNT_BASE_IDX 2
+#define mmCRTC4_CRTC_COUNT_CONTROL 0x0efc
+#define mmCRTC4_CRTC_COUNT_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_COUNT_RESET 0x0efd
+#define mmCRTC4_CRTC_COUNT_RESET_BASE_IDX 2
+#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x0efe
+#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x0eff
+#define mmCRTC4_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_STEREO_STATUS 0x0f00
+#define mmCRTC4_CRTC_STEREO_STATUS_BASE_IDX 2
+#define mmCRTC4_CRTC_STEREO_CONTROL 0x0f01
+#define mmCRTC4_CRTC_STEREO_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x0f02
+#define mmCRTC4_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
+#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x0f03
+#define mmCRTC4_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x0f04
+#define mmCRTC4_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
+#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x0f05
+#define mmCRTC4_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
+#define mmCRTC4_CRTC_START_LINE_CONTROL 0x0f06
+#define mmCRTC4_CRTC_START_LINE_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x0f07
+#define mmCRTC4_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_UPDATE_LOCK 0x0f08
+#define mmCRTC4_CRTC_UPDATE_LOCK_BASE_IDX 2
+#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x0f09
+#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x0f0a
+#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
+#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x0f0b
+#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x0f0c
+#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
+#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x0f0d
+#define mmCRTC4_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
+#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK 0x0f0e
+#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
+#define mmCRTC4_CRTC_MASTER_UPDATE_MODE 0x0f0f
+#define mmCRTC4_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
+#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x0f10
+#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
+#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0f11
+#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
+#define mmCRTC4_CRTC_MVP_STATUS 0x0f12
+#define mmCRTC4_CRTC_MVP_STATUS_BASE_IDX 2
+#define mmCRTC4_CRTC_MASTER_EN 0x0f13
+#define mmCRTC4_CRTC_MASTER_EN_BASE_IDX 2
+#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x0f14
+#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
+#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x0f15
+#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
+#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x0f17
+#define mmCRTC4_CRTC_OVERSCAN_COLOR_BASE_IDX 2
+#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x0f18
+#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
+#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x0f19
+#define mmCRTC4_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
+#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x0f1a
+#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+#define mmCRTC4_CRTC_BLACK_COLOR 0x0f1b
+#define mmCRTC4_CRTC_BLACK_COLOR_BASE_IDX 2
+#define mmCRTC4_CRTC_BLACK_COLOR_EXT 0x0f1c
+#define mmCRTC4_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x0f1d
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x0f1e
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x0f1f
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0f20
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0f21
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0f22
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_CRC_CNTL 0x0f23
+#define mmCRTC4_CRTC_CRC_CNTL_BASE_IDX 2
+#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x0f24
+#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0f25
+#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x0f26
+#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0f27
+#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_CRC0_DATA_RG 0x0f28
+#define mmCRTC4_CRTC_CRC0_DATA_RG_BASE_IDX 2
+#define mmCRTC4_CRTC_CRC0_DATA_B 0x0f29
+#define mmCRTC4_CRTC_CRC0_DATA_B_BASE_IDX 2
+#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x0f2a
+#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x0f2b
+#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x0f2c
+#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x0f2d
+#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_CRC1_DATA_RG 0x0f2e
+#define mmCRTC4_CRTC_CRC1_DATA_RG_BASE_IDX 2
+#define mmCRTC4_CRTC_CRC1_DATA_B 0x0f2f
+#define mmCRTC4_CRTC_CRC1_DATA_B_BASE_IDX 2
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x0f30
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0f31
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0f32
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0f33
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0f34
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0f35
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x0f36
+#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x0f37
+#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x0f38
+#define mmCRTC4_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
+#define mmCRTC4_CRTC_GSL_WINDOW 0x0f39
+#define mmCRTC4_CRTC_GSL_WINDOW_BASE_IDX 2
+#define mmCRTC4_CRTC_GSL_CONTROL 0x0f3a
+#define mmCRTC4_CRTC_GSL_CONTROL_BASE_IDX 2
+#define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS 0x0f3d
+#define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
+#define mmCRTC4_CRTC_DRR_CONTROL 0x0f3e
+#define mmCRTC4_CRTC_DRR_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_fmt4_dispdec
+// base address: 0x2000
+#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x0f42
+#define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
+#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x0f43
+#define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
+#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x0f44
+#define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
+#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x0f45
+#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
+#define mmFMT4_FMT_CONTROL 0x0f46
+#define mmFMT4_FMT_CONTROL_BASE_IDX 2
+#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x0f47
+#define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
+#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x0f48
+#define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
+#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x0f49
+#define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
+#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x0f4a
+#define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
+#define mmFMT4_FMT_CLAMP_CNTL 0x0f4e
+#define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX 2
+#define mmFMT4_FMT_CRC_CNTL 0x0f4f
+#define mmFMT4_FMT_CRC_CNTL_BASE_IDX 2
+#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x0f50
+#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
+#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0f51
+#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
+#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x0f52
+#define mmFMT4_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
+#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x0f53
+#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
+#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0f54
+#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
+#define mmFMT4_FMT_420_HBLANK_EARLY_START 0x0f55
+#define mmFMT4_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcp5_dispdec
+// base address: 0x2800
+#define mmDCP5_GRPH_ENABLE 0x0f5a
+#define mmDCP5_GRPH_ENABLE_BASE_IDX 2
+#define mmDCP5_GRPH_CONTROL 0x0f5b
+#define mmDCP5_GRPH_CONTROL_BASE_IDX 2
+#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x0f5c
+#define mmDCP5_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
+#define mmDCP5_GRPH_SWAP_CNTL 0x0f5d
+#define mmDCP5_GRPH_SWAP_CNTL_BASE_IDX 2
+#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x0f5e
+#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x0f5f
+#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP5_GRPH_PITCH 0x0f60
+#define mmDCP5_GRPH_PITCH_BASE_IDX 2
+#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0f61
+#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0f62
+#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x0f63
+#define mmDCP5_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
+#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x0f64
+#define mmDCP5_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
+#define mmDCP5_GRPH_X_START 0x0f65
+#define mmDCP5_GRPH_X_START_BASE_IDX 2
+#define mmDCP5_GRPH_Y_START 0x0f66
+#define mmDCP5_GRPH_Y_START_BASE_IDX 2
+#define mmDCP5_GRPH_X_END 0x0f67
+#define mmDCP5_GRPH_X_END_BASE_IDX 2
+#define mmDCP5_GRPH_Y_END 0x0f68
+#define mmDCP5_GRPH_Y_END_BASE_IDX 2
+#define mmDCP5_INPUT_GAMMA_CONTROL 0x0f69
+#define mmDCP5_INPUT_GAMMA_CONTROL_BASE_IDX 2
+#define mmDCP5_GRPH_UPDATE 0x0f6a
+#define mmDCP5_GRPH_UPDATE_BASE_IDX 2
+#define mmDCP5_GRPH_FLIP_CONTROL 0x0f6b
+#define mmDCP5_GRPH_FLIP_CONTROL_BASE_IDX 2
+#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x0f6c
+#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
+#define mmDCP5_GRPH_DFQ_CONTROL 0x0f6d
+#define mmDCP5_GRPH_DFQ_CONTROL_BASE_IDX 2
+#define mmDCP5_GRPH_DFQ_STATUS 0x0f6e
+#define mmDCP5_GRPH_DFQ_STATUS_BASE_IDX 2
+#define mmDCP5_GRPH_INTERRUPT_STATUS 0x0f6f
+#define mmDCP5_GRPH_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x0f70
+#define mmDCP5_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0f71
+#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
+#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x0f72
+#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP5_GRPH_COMPRESS_PITCH 0x0f73
+#define mmDCP5_GRPH_COMPRESS_PITCH_BASE_IDX 2
+#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0f74
+#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0f75
+#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
+#define mmDCP5_PRESCALE_GRPH_CONTROL 0x0f76
+#define mmDCP5_PRESCALE_GRPH_CONTROL_BASE_IDX 2
+#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x0f77
+#define mmDCP5_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
+#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x0f78
+#define mmDCP5_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
+#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x0f79
+#define mmDCP5_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
+#define mmDCP5_INPUT_CSC_CONTROL 0x0f7a
+#define mmDCP5_INPUT_CSC_CONTROL_BASE_IDX 2
+#define mmDCP5_INPUT_CSC_C11_C12 0x0f7b
+#define mmDCP5_INPUT_CSC_C11_C12_BASE_IDX 2
+#define mmDCP5_INPUT_CSC_C13_C14 0x0f7c
+#define mmDCP5_INPUT_CSC_C13_C14_BASE_IDX 2
+#define mmDCP5_INPUT_CSC_C21_C22 0x0f7d
+#define mmDCP5_INPUT_CSC_C21_C22_BASE_IDX 2
+#define mmDCP5_INPUT_CSC_C23_C24 0x0f7e
+#define mmDCP5_INPUT_CSC_C23_C24_BASE_IDX 2
+#define mmDCP5_INPUT_CSC_C31_C32 0x0f7f
+#define mmDCP5_INPUT_CSC_C31_C32_BASE_IDX 2
+#define mmDCP5_INPUT_CSC_C33_C34 0x0f80
+#define mmDCP5_INPUT_CSC_C33_C34_BASE_IDX 2
+#define mmDCP5_OUTPUT_CSC_CONTROL 0x0f81
+#define mmDCP5_OUTPUT_CSC_CONTROL_BASE_IDX 2
+#define mmDCP5_OUTPUT_CSC_C11_C12 0x0f82
+#define mmDCP5_OUTPUT_CSC_C11_C12_BASE_IDX 2
+#define mmDCP5_OUTPUT_CSC_C13_C14 0x0f83
+#define mmDCP5_OUTPUT_CSC_C13_C14_BASE_IDX 2
+#define mmDCP5_OUTPUT_CSC_C21_C22 0x0f84
+#define mmDCP5_OUTPUT_CSC_C21_C22_BASE_IDX 2
+#define mmDCP5_OUTPUT_CSC_C23_C24 0x0f85
+#define mmDCP5_OUTPUT_CSC_C23_C24_BASE_IDX 2
+#define mmDCP5_OUTPUT_CSC_C31_C32 0x0f86
+#define mmDCP5_OUTPUT_CSC_C31_C32_BASE_IDX 2
+#define mmDCP5_OUTPUT_CSC_C33_C34 0x0f87
+#define mmDCP5_OUTPUT_CSC_C33_C34_BASE_IDX 2
+#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x0f88
+#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
+#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x0f89
+#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
+#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x0f8a
+#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
+#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x0f8b
+#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
+#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x0f8c
+#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
+#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x0f8d
+#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
+#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x0f8e
+#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
+#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x0f8f
+#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
+#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x0f90
+#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
+#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x0f91
+#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
+#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x0f92
+#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
+#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x0f93
+#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
+#define mmDCP5_DENORM_CONTROL 0x0f94
+#define mmDCP5_DENORM_CONTROL_BASE_IDX 2
+#define mmDCP5_OUT_ROUND_CONTROL 0x0f95
+#define mmDCP5_OUT_ROUND_CONTROL_BASE_IDX 2
+#define mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x0f96
+#define mmDCP5_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
+#define mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x0f97
+#define mmDCP5_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
+#define mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x0f98
+#define mmDCP5_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
+#define mmDCP5_KEY_CONTROL 0x0f99
+#define mmDCP5_KEY_CONTROL_BASE_IDX 2
+#define mmDCP5_KEY_RANGE_ALPHA 0x0f9a
+#define mmDCP5_KEY_RANGE_ALPHA_BASE_IDX 2
+#define mmDCP5_KEY_RANGE_RED 0x0f9b
+#define mmDCP5_KEY_RANGE_RED_BASE_IDX 2
+#define mmDCP5_KEY_RANGE_GREEN 0x0f9c
+#define mmDCP5_KEY_RANGE_GREEN_BASE_IDX 2
+#define mmDCP5_KEY_RANGE_BLUE 0x0f9d
+#define mmDCP5_KEY_RANGE_BLUE_BASE_IDX 2
+#define mmDCP5_DEGAMMA_CONTROL 0x0f9e
+#define mmDCP5_DEGAMMA_CONTROL_BASE_IDX 2
+#define mmDCP5_GAMUT_REMAP_CONTROL 0x0f9f
+#define mmDCP5_GAMUT_REMAP_CONTROL_BASE_IDX 2
+#define mmDCP5_GAMUT_REMAP_C11_C12 0x0fa0
+#define mmDCP5_GAMUT_REMAP_C11_C12_BASE_IDX 2
+#define mmDCP5_GAMUT_REMAP_C13_C14 0x0fa1
+#define mmDCP5_GAMUT_REMAP_C13_C14_BASE_IDX 2
+#define mmDCP5_GAMUT_REMAP_C21_C22 0x0fa2
+#define mmDCP5_GAMUT_REMAP_C21_C22_BASE_IDX 2
+#define mmDCP5_GAMUT_REMAP_C23_C24 0x0fa3
+#define mmDCP5_GAMUT_REMAP_C23_C24_BASE_IDX 2
+#define mmDCP5_GAMUT_REMAP_C31_C32 0x0fa4
+#define mmDCP5_GAMUT_REMAP_C31_C32_BASE_IDX 2
+#define mmDCP5_GAMUT_REMAP_C33_C34 0x0fa5
+#define mmDCP5_GAMUT_REMAP_C33_C34_BASE_IDX 2
+#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x0fa6
+#define mmDCP5_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
+#define mmDCP5_DCP_RANDOM_SEEDS 0x0fa7
+#define mmDCP5_DCP_RANDOM_SEEDS_BASE_IDX 2
+#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x0fa8
+#define mmDCP5_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
+#define mmDCP5_CUR_CONTROL 0x0fa9
+#define mmDCP5_CUR_CONTROL_BASE_IDX 2
+#define mmDCP5_CUR_SURFACE_ADDRESS 0x0faa
+#define mmDCP5_CUR_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP5_CUR_SIZE 0x0fab
+#define mmDCP5_CUR_SIZE_BASE_IDX 2
+#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x0fac
+#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP5_CUR_POSITION 0x0fad
+#define mmDCP5_CUR_POSITION_BASE_IDX 2
+#define mmDCP5_CUR_HOT_SPOT 0x0fae
+#define mmDCP5_CUR_HOT_SPOT_BASE_IDX 2
+#define mmDCP5_CUR_COLOR1 0x0faf
+#define mmDCP5_CUR_COLOR1_BASE_IDX 2
+#define mmDCP5_CUR_COLOR2 0x0fb0
+#define mmDCP5_CUR_COLOR2_BASE_IDX 2
+#define mmDCP5_CUR_UPDATE 0x0fb1
+#define mmDCP5_CUR_UPDATE_BASE_IDX 2
+#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x0fbb
+#define mmDCP5_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
+#define mmDCP5_CUR_STEREO_CONTROL 0x0fbc
+#define mmDCP5_CUR_STEREO_CONTROL_BASE_IDX 2
+#define mmDCP5_DC_LUT_RW_MODE 0x0fbe
+#define mmDCP5_DC_LUT_RW_MODE_BASE_IDX 2
+#define mmDCP5_DC_LUT_RW_INDEX 0x0fbf
+#define mmDCP5_DC_LUT_RW_INDEX_BASE_IDX 2
+#define mmDCP5_DC_LUT_SEQ_COLOR 0x0fc0
+#define mmDCP5_DC_LUT_SEQ_COLOR_BASE_IDX 2
+#define mmDCP5_DC_LUT_PWL_DATA 0x0fc1
+#define mmDCP5_DC_LUT_PWL_DATA_BASE_IDX 2
+#define mmDCP5_DC_LUT_30_COLOR 0x0fc2
+#define mmDCP5_DC_LUT_30_COLOR_BASE_IDX 2
+#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x0fc3
+#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
+#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x0fc4
+#define mmDCP5_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmDCP5_DC_LUT_AUTOFILL 0x0fc5
+#define mmDCP5_DC_LUT_AUTOFILL_BASE_IDX 2
+#define mmDCP5_DC_LUT_CONTROL 0x0fc6
+#define mmDCP5_DC_LUT_CONTROL_BASE_IDX 2
+#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x0fc7
+#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
+#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x0fc8
+#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
+#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x0fc9
+#define mmDCP5_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
+#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x0fca
+#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
+#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x0fcb
+#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
+#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x0fcc
+#define mmDCP5_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
+#define mmDCP5_DCP_CRC_CONTROL 0x0fcd
+#define mmDCP5_DCP_CRC_CONTROL_BASE_IDX 2
+#define mmDCP5_DCP_CRC_MASK 0x0fce
+#define mmDCP5_DCP_CRC_MASK_BASE_IDX 2
+#define mmDCP5_DCP_CRC_CURRENT 0x0fcf
+#define mmDCP5_DCP_CRC_CURRENT_BASE_IDX 2
+#define mmDCP5_DVMM_PTE_CONTROL 0x0fd0
+#define mmDCP5_DVMM_PTE_CONTROL_BASE_IDX 2
+#define mmDCP5_DCP_CRC_LAST 0x0fd1
+#define mmDCP5_DCP_CRC_LAST_BASE_IDX 2
+#define mmDCP5_DVMM_PTE_ARB_CONTROL 0x0fd2
+#define mmDCP5_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
+#define mmDCP5_GRPH_FLIP_RATE_CNTL 0x0fd4
+#define mmDCP5_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
+#define mmDCP5_DCP_GSL_CONTROL 0x0fd5
+#define mmDCP5_DCP_GSL_CONTROL_BASE_IDX 2
+#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x0fd6
+#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
+#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x0fdc
+#define mmDCP5_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
+#define mmDCP5_HW_ROTATION 0x0fde
+#define mmDCP5_HW_ROTATION_BASE_IDX 2
+#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x0fdf
+#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
+#define mmDCP5_REGAMMA_CONTROL 0x0fe0
+#define mmDCP5_REGAMMA_CONTROL_BASE_IDX 2
+#define mmDCP5_REGAMMA_LUT_INDEX 0x0fe1
+#define mmDCP5_REGAMMA_LUT_INDEX_BASE_IDX 2
+#define mmDCP5_REGAMMA_LUT_DATA 0x0fe2
+#define mmDCP5_REGAMMA_LUT_DATA_BASE_IDX 2
+#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x0fe3
+#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x0fe4
+#define mmDCP5_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x0fe5
+#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x0fe6
+#define mmDCP5_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x0fe7
+#define mmDCP5_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x0fe8
+#define mmDCP5_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x0fe9
+#define mmDCP5_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x0fea
+#define mmDCP5_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x0feb
+#define mmDCP5_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x0fec
+#define mmDCP5_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x0fed
+#define mmDCP5_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x0fee
+#define mmDCP5_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x0fef
+#define mmDCP5_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x0ff0
+#define mmDCP5_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x0ff1
+#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x0ff2
+#define mmDCP5_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x0ff3
+#define mmDCP5_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x0ff4
+#define mmDCP5_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x0ff5
+#define mmDCP5_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x0ff6
+#define mmDCP5_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x0ff7
+#define mmDCP5_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x0ff8
+#define mmDCP5_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x0ff9
+#define mmDCP5_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x0ffa
+#define mmDCP5_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
+#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x0ffb
+#define mmDCP5_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
+#define mmDCP5_ALPHA_CONTROL 0x0ffc
+#define mmDCP5_ALPHA_CONTROL_BASE_IDX 2
+#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x0ffd
+#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x0ffe
+#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x0fff
+#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
+#define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT 0x1000
+#define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
+#define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY 0x1001
+#define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
+#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL 0x1002
+#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
+#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT 0x1003
+#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_lb5_dispdec
+// base address: 0x2800
+#define mmLB5_LB_DATA_FORMAT 0x101a
+#define mmLB5_LB_DATA_FORMAT_BASE_IDX 2
+#define mmLB5_LB_MEMORY_CTRL 0x101b
+#define mmLB5_LB_MEMORY_CTRL_BASE_IDX 2
+#define mmLB5_LB_MEMORY_SIZE_STATUS 0x101c
+#define mmLB5_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
+#define mmLB5_LB_DESKTOP_HEIGHT 0x101d
+#define mmLB5_LB_DESKTOP_HEIGHT_BASE_IDX 2
+#define mmLB5_LB_VLINE_START_END 0x101e
+#define mmLB5_LB_VLINE_START_END_BASE_IDX 2
+#define mmLB5_LB_VLINE2_START_END 0x101f
+#define mmLB5_LB_VLINE2_START_END_BASE_IDX 2
+#define mmLB5_LB_V_COUNTER 0x1020
+#define mmLB5_LB_V_COUNTER_BASE_IDX 2
+#define mmLB5_LB_SNAPSHOT_V_COUNTER 0x1021
+#define mmLB5_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
+#define mmLB5_LB_INTERRUPT_MASK 0x1022
+#define mmLB5_LB_INTERRUPT_MASK_BASE_IDX 2
+#define mmLB5_LB_VLINE_STATUS 0x1023
+#define mmLB5_LB_VLINE_STATUS_BASE_IDX 2
+#define mmLB5_LB_VLINE2_STATUS 0x1024
+#define mmLB5_LB_VLINE2_STATUS_BASE_IDX 2
+#define mmLB5_LB_VBLANK_STATUS 0x1025
+#define mmLB5_LB_VBLANK_STATUS_BASE_IDX 2
+#define mmLB5_LB_SYNC_RESET_SEL 0x1026
+#define mmLB5_LB_SYNC_RESET_SEL_BASE_IDX 2
+#define mmLB5_LB_BLACK_KEYER_R_CR 0x1027
+#define mmLB5_LB_BLACK_KEYER_R_CR_BASE_IDX 2
+#define mmLB5_LB_BLACK_KEYER_G_Y 0x1028
+#define mmLB5_LB_BLACK_KEYER_G_Y_BASE_IDX 2
+#define mmLB5_LB_BLACK_KEYER_B_CB 0x1029
+#define mmLB5_LB_BLACK_KEYER_B_CB_BASE_IDX 2
+#define mmLB5_LB_KEYER_COLOR_CTRL 0x102a
+#define mmLB5_LB_KEYER_COLOR_CTRL_BASE_IDX 2
+#define mmLB5_LB_KEYER_COLOR_R_CR 0x102b
+#define mmLB5_LB_KEYER_COLOR_R_CR_BASE_IDX 2
+#define mmLB5_LB_KEYER_COLOR_G_Y 0x102c
+#define mmLB5_LB_KEYER_COLOR_G_Y_BASE_IDX 2
+#define mmLB5_LB_KEYER_COLOR_B_CB 0x102d
+#define mmLB5_LB_KEYER_COLOR_B_CB_BASE_IDX 2
+#define mmLB5_LB_KEYER_COLOR_REP_R_CR 0x102e
+#define mmLB5_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
+#define mmLB5_LB_KEYER_COLOR_REP_G_Y 0x102f
+#define mmLB5_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
+#define mmLB5_LB_KEYER_COLOR_REP_B_CB 0x1030
+#define mmLB5_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
+#define mmLB5_LB_BUFFER_LEVEL_STATUS 0x1031
+#define mmLB5_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
+#define mmLB5_LB_BUFFER_URGENCY_CTRL 0x1032
+#define mmLB5_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
+#define mmLB5_LB_BUFFER_URGENCY_STATUS 0x1033
+#define mmLB5_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
+#define mmLB5_LB_BUFFER_STATUS 0x1034
+#define mmLB5_LB_BUFFER_STATUS_BASE_IDX 2
+#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x1035
+#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
+#define mmLB5_MVP_AFR_FLIP_MODE 0x1036
+#define mmLB5_MVP_AFR_FLIP_MODE_BASE_IDX 2
+#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x1037
+#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
+#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x1038
+#define mmLB5_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
+#define mmLB5_DC_MVP_LB_CONTROL 0x1039
+#define mmLB5_DC_MVP_LB_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcfe5_dispdec
+// base address: 0x2800
+#define mmDCFE5_DCFE_CLOCK_CONTROL 0x105a
+#define mmDCFE5_DCFE_CLOCK_CONTROL_BASE_IDX 2
+#define mmDCFE5_DCFE_SOFT_RESET 0x105b
+#define mmDCFE5_DCFE_SOFT_RESET_BASE_IDX 2
+#define mmDCFE5_DCFE_MEM_PWR_CTRL 0x105d
+#define mmDCFE5_DCFE_MEM_PWR_CTRL_BASE_IDX 2
+#define mmDCFE5_DCFE_MEM_PWR_CTRL2 0x105e
+#define mmDCFE5_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
+#define mmDCFE5_DCFE_MEM_PWR_STATUS 0x105f
+#define mmDCFE5_DCFE_MEM_PWR_STATUS_BASE_IDX 2
+#define mmDCFE5_DCFE_MISC 0x1060
+#define mmDCFE5_DCFE_MISC_BASE_IDX 2
+#define mmDCFE5_DCFE_FLUSH 0x1061
+#define mmDCFE5_DCFE_FLUSH_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_perfmon8_dispdec
+// base address: 0x4138
+#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x106e
+#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x106f
+#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x1070
+#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON8_PERFMON_CNTL 0x1071
+#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON8_PERFMON_CNTL2 0x1072
+#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x1073
+#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x1074
+#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON8_PERFMON_HI 0x1075
+#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON8_PERFMON_LOW 0x1076
+#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dmif_pg5_dispdec
+// base address: 0x2800
+#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x107a
+#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
+#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x107b
+#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
+#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x107c
+#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
+#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x107d
+#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
+#define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL 0x107e
+#define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
+#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x107f
+#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
+#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2 0x1080
+#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
+#define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL 0x1081
+#define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
+#define mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x1082
+#define mmDMIF_PG5_DPG_REPEATER_PROGRAM_BASE_IDX 2
+#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL 0x1086
+#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
+#define mmDMIF_PG5_DPG_DVMM_STATUS 0x1087
+#define mmDMIF_PG5_DPG_DVMM_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_scl5_dispdec
+// base address: 0x2800
+#define mmSCL5_SCL_COEF_RAM_SELECT 0x109a
+#define mmSCL5_SCL_COEF_RAM_SELECT_BASE_IDX 2
+#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x109b
+#define mmSCL5_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
+#define mmSCL5_SCL_MODE 0x109c
+#define mmSCL5_SCL_MODE_BASE_IDX 2
+#define mmSCL5_SCL_TAP_CONTROL 0x109d
+#define mmSCL5_SCL_TAP_CONTROL_BASE_IDX 2
+#define mmSCL5_SCL_CONTROL 0x109e
+#define mmSCL5_SCL_CONTROL_BASE_IDX 2
+#define mmSCL5_SCL_BYPASS_CONTROL 0x109f
+#define mmSCL5_SCL_BYPASS_CONTROL_BASE_IDX 2
+#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x10a0
+#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x10a1
+#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
+#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x10a2
+#define mmSCL5_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
+#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x10a3
+#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmSCL5_SCL_HORZ_FILTER_INIT 0x10a4
+#define mmSCL5_SCL_HORZ_FILTER_INIT_BASE_IDX 2
+#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x10a5
+#define mmSCL5_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
+#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x10a6
+#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmSCL5_SCL_VERT_FILTER_INIT 0x10a7
+#define mmSCL5_SCL_VERT_FILTER_INIT_BASE_IDX 2
+#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x10a8
+#define mmSCL5_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
+#define mmSCL5_SCL_ROUND_OFFSET 0x10a9
+#define mmSCL5_SCL_ROUND_OFFSET_BASE_IDX 2
+#define mmSCL5_SCL_UPDATE 0x10aa
+#define mmSCL5_SCL_UPDATE_BASE_IDX 2
+#define mmSCL5_SCL_F_SHARP_CONTROL 0x10ab
+#define mmSCL5_SCL_F_SHARP_CONTROL_BASE_IDX 2
+#define mmSCL5_SCL_ALU_CONTROL 0x10ac
+#define mmSCL5_SCL_ALU_CONTROL_BASE_IDX 2
+#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x10ad
+#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
+#define mmSCL5_VIEWPORT_START_SECONDARY 0x10ae
+#define mmSCL5_VIEWPORT_START_SECONDARY_BASE_IDX 2
+#define mmSCL5_VIEWPORT_START 0x10af
+#define mmSCL5_VIEWPORT_START_BASE_IDX 2
+#define mmSCL5_VIEWPORT_SIZE 0x10b0
+#define mmSCL5_VIEWPORT_SIZE_BASE_IDX 2
+#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x10b1
+#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x10b2
+#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+#define mmSCL5_SCL_MODE_CHANGE_DET1 0x10b3
+#define mmSCL5_SCL_MODE_CHANGE_DET1_BASE_IDX 2
+#define mmSCL5_SCL_MODE_CHANGE_DET2 0x10b4
+#define mmSCL5_SCL_MODE_CHANGE_DET2_BASE_IDX 2
+#define mmSCL5_SCL_MODE_CHANGE_DET3 0x10b5
+#define mmSCL5_SCL_MODE_CHANGE_DET3_BASE_IDX 2
+#define mmSCL5_SCL_MODE_CHANGE_MASK 0x10b6
+#define mmSCL5_SCL_MODE_CHANGE_MASK_BASE_IDX 2
+
+
+// addressBlock: dce_dc_blnd5_dispdec
+// base address: 0x2800
+#define mmBLND5_BLND_CONTROL 0x10c7
+#define mmBLND5_BLND_CONTROL_BASE_IDX 2
+#define mmBLND5_BLND_SM_CONTROL2 0x10c8
+#define mmBLND5_BLND_SM_CONTROL2_BASE_IDX 2
+#define mmBLND5_BLND_CONTROL2 0x10c9
+#define mmBLND5_BLND_CONTROL2_BASE_IDX 2
+#define mmBLND5_BLND_UPDATE 0x10ca
+#define mmBLND5_BLND_UPDATE_BASE_IDX 2
+#define mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x10cb
+#define mmBLND5_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
+#define mmBLND5_BLND_V_UPDATE_LOCK 0x10cc
+#define mmBLND5_BLND_V_UPDATE_LOCK_BASE_IDX 2
+#define mmBLND5_BLND_REG_UPDATE_STATUS 0x10cd
+#define mmBLND5_BLND_REG_UPDATE_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_crtc5_dispdec
+// base address: 0x2800
+#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x10d2
+#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
+#define mmCRTC5_CRTC_H_TOTAL 0x10d3
+#define mmCRTC5_CRTC_H_TOTAL_BASE_IDX 2
+#define mmCRTC5_CRTC_H_BLANK_START_END 0x10d4
+#define mmCRTC5_CRTC_H_BLANK_START_END_BASE_IDX 2
+#define mmCRTC5_CRTC_H_SYNC_A 0x10d5
+#define mmCRTC5_CRTC_H_SYNC_A_BASE_IDX 2
+#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x10d6
+#define mmCRTC5_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
+#define mmCRTC5_CRTC_H_SYNC_B 0x10d7
+#define mmCRTC5_CRTC_H_SYNC_B_BASE_IDX 2
+#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x10d8
+#define mmCRTC5_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
+#define mmCRTC5_CRTC_VBI_END 0x10d9
+#define mmCRTC5_CRTC_VBI_END_BASE_IDX 2
+#define mmCRTC5_CRTC_V_TOTAL 0x10da
+#define mmCRTC5_CRTC_V_TOTAL_BASE_IDX 2
+#define mmCRTC5_CRTC_V_TOTAL_MIN 0x10db
+#define mmCRTC5_CRTC_V_TOTAL_MIN_BASE_IDX 2
+#define mmCRTC5_CRTC_V_TOTAL_MAX 0x10dc
+#define mmCRTC5_CRTC_V_TOTAL_MAX_BASE_IDX 2
+#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x10dd
+#define mmCRTC5_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x10de
+#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
+#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x10df
+#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+#define mmCRTC5_CRTC_V_BLANK_START_END 0x10e0
+#define mmCRTC5_CRTC_V_BLANK_START_END_BASE_IDX 2
+#define mmCRTC5_CRTC_V_SYNC_A 0x10e1
+#define mmCRTC5_CRTC_V_SYNC_A_BASE_IDX 2
+#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x10e2
+#define mmCRTC5_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
+#define mmCRTC5_CRTC_V_SYNC_B 0x10e3
+#define mmCRTC5_CRTC_V_SYNC_B_BASE_IDX 2
+#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x10e4
+#define mmCRTC5_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
+#define mmCRTC5_CRTC_DTMTEST_CNTL 0x10e5
+#define mmCRTC5_CRTC_DTMTEST_CNTL_BASE_IDX 2
+#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x10e6
+#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
+#define mmCRTC5_CRTC_TRIGA_CNTL 0x10e7
+#define mmCRTC5_CRTC_TRIGA_CNTL_BASE_IDX 2
+#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x10e8
+#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
+#define mmCRTC5_CRTC_TRIGB_CNTL 0x10e9
+#define mmCRTC5_CRTC_TRIGB_CNTL_BASE_IDX 2
+#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x10ea
+#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
+#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x10eb
+#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+#define mmCRTC5_CRTC_FLOW_CONTROL 0x10ec
+#define mmCRTC5_CRTC_FLOW_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x10ed
+#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+#define mmCRTC5_CRTC_AVSYNC_COUNTER 0x10ee
+#define mmCRTC5_CRTC_AVSYNC_COUNTER_BASE_IDX 2
+#define mmCRTC5_CRTC_CONTROL 0x10ef
+#define mmCRTC5_CRTC_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_BLANK_CONTROL 0x10f0
+#define mmCRTC5_CRTC_BLANK_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x10f1
+#define mmCRTC5_CRTC_INTERLACE_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_INTERLACE_STATUS 0x10f2
+#define mmCRTC5_CRTC_INTERLACE_STATUS_BASE_IDX 2
+#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x10f3
+#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x10f4
+#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
+#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x10f5
+#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
+#define mmCRTC5_CRTC_STATUS 0x10f6
+#define mmCRTC5_CRTC_STATUS_BASE_IDX 2
+#define mmCRTC5_CRTC_STATUS_POSITION 0x10f7
+#define mmCRTC5_CRTC_STATUS_POSITION_BASE_IDX 2
+#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x10f8
+#define mmCRTC5_CRTC_NOM_VERT_POSITION_BASE_IDX 2
+#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x10f9
+#define mmCRTC5_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
+#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x10fa
+#define mmCRTC5_CRTC_STATUS_VF_COUNT_BASE_IDX 2
+#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x10fb
+#define mmCRTC5_CRTC_STATUS_HV_COUNT_BASE_IDX 2
+#define mmCRTC5_CRTC_COUNT_CONTROL 0x10fc
+#define mmCRTC5_CRTC_COUNT_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_COUNT_RESET 0x10fd
+#define mmCRTC5_CRTC_COUNT_RESET_BASE_IDX 2
+#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x10fe
+#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x10ff
+#define mmCRTC5_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_STEREO_STATUS 0x1100
+#define mmCRTC5_CRTC_STEREO_STATUS_BASE_IDX 2
+#define mmCRTC5_CRTC_STEREO_CONTROL 0x1101
+#define mmCRTC5_CRTC_STEREO_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x1102
+#define mmCRTC5_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
+#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x1103
+#define mmCRTC5_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x1104
+#define mmCRTC5_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
+#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x1105
+#define mmCRTC5_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
+#define mmCRTC5_CRTC_START_LINE_CONTROL 0x1106
+#define mmCRTC5_CRTC_START_LINE_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x1107
+#define mmCRTC5_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_UPDATE_LOCK 0x1108
+#define mmCRTC5_CRTC_UPDATE_LOCK_BASE_IDX 2
+#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x1109
+#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x110a
+#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
+#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x110b
+#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x110c
+#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
+#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x110d
+#define mmCRTC5_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
+#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK 0x110e
+#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
+#define mmCRTC5_CRTC_MASTER_UPDATE_MODE 0x110f
+#define mmCRTC5_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
+#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x1110
+#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
+#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1111
+#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
+#define mmCRTC5_CRTC_MVP_STATUS 0x1112
+#define mmCRTC5_CRTC_MVP_STATUS_BASE_IDX 2
+#define mmCRTC5_CRTC_MASTER_EN 0x1113
+#define mmCRTC5_CRTC_MASTER_EN_BASE_IDX 2
+#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x1114
+#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
+#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x1115
+#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
+#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x1117
+#define mmCRTC5_CRTC_OVERSCAN_COLOR_BASE_IDX 2
+#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x1118
+#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
+#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x1119
+#define mmCRTC5_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
+#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x111a
+#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+#define mmCRTC5_CRTC_BLACK_COLOR 0x111b
+#define mmCRTC5_CRTC_BLACK_COLOR_BASE_IDX 2
+#define mmCRTC5_CRTC_BLACK_COLOR_EXT 0x111c
+#define mmCRTC5_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x111d
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x111e
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x111f
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1120
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1121
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1122
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_CRC_CNTL 0x1123
+#define mmCRTC5_CRTC_CRC_CNTL_BASE_IDX 2
+#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x1124
+#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1125
+#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x1126
+#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1127
+#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_CRC0_DATA_RG 0x1128
+#define mmCRTC5_CRTC_CRC0_DATA_RG_BASE_IDX 2
+#define mmCRTC5_CRTC_CRC0_DATA_B 0x1129
+#define mmCRTC5_CRTC_CRC0_DATA_B_BASE_IDX 2
+#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x112a
+#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x112b
+#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x112c
+#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x112d
+#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_CRC1_DATA_RG 0x112e
+#define mmCRTC5_CRTC_CRC1_DATA_RG_BASE_IDX 2
+#define mmCRTC5_CRTC_CRC1_DATA_B 0x112f
+#define mmCRTC5_CRTC_CRC1_DATA_B_BASE_IDX 2
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x1130
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1131
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1132
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1133
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1134
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1135
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x1136
+#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x1137
+#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x1138
+#define mmCRTC5_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
+#define mmCRTC5_CRTC_GSL_WINDOW 0x1139
+#define mmCRTC5_CRTC_GSL_WINDOW_BASE_IDX 2
+#define mmCRTC5_CRTC_GSL_CONTROL 0x113a
+#define mmCRTC5_CRTC_GSL_CONTROL_BASE_IDX 2
+#define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS 0x113d
+#define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
+#define mmCRTC5_CRTC_DRR_CONTROL 0x113e
+#define mmCRTC5_CRTC_DRR_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_fmt5_dispdec
+// base address: 0x2800
+#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x1142
+#define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
+#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x1143
+#define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
+#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x1144
+#define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
+#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x1145
+#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
+#define mmFMT5_FMT_CONTROL 0x1146
+#define mmFMT5_FMT_CONTROL_BASE_IDX 2
+#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x1147
+#define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
+#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x1148
+#define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
+#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x1149
+#define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
+#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x114a
+#define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
+#define mmFMT5_FMT_CLAMP_CNTL 0x114e
+#define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX 2
+#define mmFMT5_FMT_CRC_CNTL 0x114f
+#define mmFMT5_FMT_CRC_CNTL_BASE_IDX 2
+#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x1150
+#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
+#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1151
+#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
+#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x1152
+#define mmFMT5_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
+#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x1153
+#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
+#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1154
+#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
+#define mmFMT5_FMT_420_HBLANK_EARLY_START 0x1155
+#define mmFMT5_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
+
+
+// addressBlock: dce_dc_unp0_dispdec
+// base address: 0x0
+#define mmUNP0_UNP_GRPH_ENABLE 0x115a
+#define mmUNP0_UNP_GRPH_ENABLE_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_CONTROL 0x115b
+#define mmUNP0_UNP_GRPH_CONTROL_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_CONTROL_C 0x115c
+#define mmUNP0_UNP_GRPH_CONTROL_C_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_CONTROL_EXP 0x115d
+#define mmUNP0_UNP_GRPH_CONTROL_EXP_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_SWAP_CNTL 0x115e
+#define mmUNP0_UNP_GRPH_SWAP_CNTL_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x115f
+#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x1160
+#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x1161
+#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x1162
+#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x1163
+#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x1164
+#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x1165
+#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x1166
+#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x1167
+#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x1168
+#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x1169
+#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x116a
+#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x116b
+#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x116c
+#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x116d
+#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x116e
+#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_PITCH_L 0x116f
+#define mmUNP0_UNP_GRPH_PITCH_L_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_PITCH_C 0x1170
+#define mmUNP0_UNP_GRPH_PITCH_C_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L 0x1171
+#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C 0x1172
+#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L 0x1173
+#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C 0x1174
+#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_X_START_L 0x1175
+#define mmUNP0_UNP_GRPH_X_START_L_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_X_START_C 0x1176
+#define mmUNP0_UNP_GRPH_X_START_C_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_Y_START_L 0x1177
+#define mmUNP0_UNP_GRPH_Y_START_L_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_Y_START_C 0x1178
+#define mmUNP0_UNP_GRPH_Y_START_C_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_X_END_L 0x1179
+#define mmUNP0_UNP_GRPH_X_END_L_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_X_END_C 0x117a
+#define mmUNP0_UNP_GRPH_X_END_C_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_Y_END_L 0x117b
+#define mmUNP0_UNP_GRPH_Y_END_L_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_Y_END_C 0x117c
+#define mmUNP0_UNP_GRPH_Y_END_C_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_UPDATE 0x117d
+#define mmUNP0_UNP_GRPH_UPDATE_BASE_IDX 2
+#define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x117e
+#define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x117f
+#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x1180
+#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x1181
+#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x1182
+#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_BASE_IDX 2
+#define mmUNP0_UNP_DVMM_PTE_CONTROL 0x1183
+#define mmUNP0_UNP_DVMM_PTE_CONTROL_BASE_IDX 2
+#define mmUNP0_UNP_DVMM_PTE_CONTROL_C 0x1184
+#define mmUNP0_UNP_DVMM_PTE_CONTROL_C_BASE_IDX 2
+#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL 0x1185
+#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
+#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C 0x1186
+#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_INTERRUPT_STATUS 0x1187
+#define mmUNP0_UNP_GRPH_INTERRUPT_STATUS_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL 0x1188
+#define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP 0x1189
+#define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
+#define mmUNP0_UNP_FLIP_CONTROL 0x118a
+#define mmUNP0_UNP_FLIP_CONTROL_BASE_IDX 2
+#define mmUNP0_UNP_CRC_CONTROL 0x118b
+#define mmUNP0_UNP_CRC_CONTROL_BASE_IDX 2
+#define mmUNP0_UNP_CRC_MASK 0x118c
+#define mmUNP0_UNP_CRC_MASK_BASE_IDX 2
+#define mmUNP0_UNP_CRC_CURRENT 0x118d
+#define mmUNP0_UNP_CRC_CURRENT_BASE_IDX 2
+#define mmUNP0_UNP_CRC_LAST 0x118e
+#define mmUNP0_UNP_CRC_LAST_BASE_IDX 2
+#define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK 0x118f
+#define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
+#define mmUNP0_UNP_HW_ROTATION 0x1190
+#define mmUNP0_UNP_HW_ROTATION_BASE_IDX 2
+
+
+// addressBlock: dce_dc_lbv0_dispdec
+// base address: 0x0
+#define mmLBV0_LBV_DATA_FORMAT 0x1196
+#define mmLBV0_LBV_DATA_FORMAT_BASE_IDX 2
+#define mmLBV0_LBV_MEMORY_CTRL 0x1197
+#define mmLBV0_LBV_MEMORY_CTRL_BASE_IDX 2
+#define mmLBV0_LBV_MEMORY_SIZE_STATUS 0x1198
+#define mmLBV0_LBV_MEMORY_SIZE_STATUS_BASE_IDX 2
+#define mmLBV0_LBV_DESKTOP_HEIGHT 0x1199
+#define mmLBV0_LBV_DESKTOP_HEIGHT_BASE_IDX 2
+#define mmLBV0_LBV_VLINE_START_END 0x119a
+#define mmLBV0_LBV_VLINE_START_END_BASE_IDX 2
+#define mmLBV0_LBV_VLINE2_START_END 0x119b
+#define mmLBV0_LBV_VLINE2_START_END_BASE_IDX 2
+#define mmLBV0_LBV_V_COUNTER 0x119c
+#define mmLBV0_LBV_V_COUNTER_BASE_IDX 2
+#define mmLBV0_LBV_SNAPSHOT_V_COUNTER 0x119d
+#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_BASE_IDX 2
+#define mmLBV0_LBV_V_COUNTER_CHROMA 0x119e
+#define mmLBV0_LBV_V_COUNTER_CHROMA_BASE_IDX 2
+#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA 0x119f
+#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA_BASE_IDX 2
+#define mmLBV0_LBV_INTERRUPT_MASK 0x11a0
+#define mmLBV0_LBV_INTERRUPT_MASK_BASE_IDX 2
+#define mmLBV0_LBV_VLINE_STATUS 0x11a1
+#define mmLBV0_LBV_VLINE_STATUS_BASE_IDX 2
+#define mmLBV0_LBV_VLINE2_STATUS 0x11a2
+#define mmLBV0_LBV_VLINE2_STATUS_BASE_IDX 2
+#define mmLBV0_LBV_VBLANK_STATUS 0x11a3
+#define mmLBV0_LBV_VBLANK_STATUS_BASE_IDX 2
+#define mmLBV0_LBV_SYNC_RESET_SEL 0x11a4
+#define mmLBV0_LBV_SYNC_RESET_SEL_BASE_IDX 2
+#define mmLBV0_LBV_BLACK_KEYER_R_CR 0x11a5
+#define mmLBV0_LBV_BLACK_KEYER_R_CR_BASE_IDX 2
+#define mmLBV0_LBV_BLACK_KEYER_G_Y 0x11a6
+#define mmLBV0_LBV_BLACK_KEYER_G_Y_BASE_IDX 2
+#define mmLBV0_LBV_BLACK_KEYER_B_CB 0x11a7
+#define mmLBV0_LBV_BLACK_KEYER_B_CB_BASE_IDX 2
+#define mmLBV0_LBV_KEYER_COLOR_CTRL 0x11a8
+#define mmLBV0_LBV_KEYER_COLOR_CTRL_BASE_IDX 2
+#define mmLBV0_LBV_KEYER_COLOR_R_CR 0x11a9
+#define mmLBV0_LBV_KEYER_COLOR_R_CR_BASE_IDX 2
+#define mmLBV0_LBV_KEYER_COLOR_G_Y 0x11aa
+#define mmLBV0_LBV_KEYER_COLOR_G_Y_BASE_IDX 2
+#define mmLBV0_LBV_KEYER_COLOR_B_CB 0x11ab
+#define mmLBV0_LBV_KEYER_COLOR_B_CB_BASE_IDX 2
+#define mmLBV0_LBV_KEYER_COLOR_REP_R_CR 0x11ac
+#define mmLBV0_LBV_KEYER_COLOR_REP_R_CR_BASE_IDX 2
+#define mmLBV0_LBV_KEYER_COLOR_REP_G_Y 0x11ad
+#define mmLBV0_LBV_KEYER_COLOR_REP_G_Y_BASE_IDX 2
+#define mmLBV0_LBV_KEYER_COLOR_REP_B_CB 0x11ae
+#define mmLBV0_LBV_KEYER_COLOR_REP_B_CB_BASE_IDX 2
+#define mmLBV0_LBV_BUFFER_LEVEL_STATUS 0x11af
+#define mmLBV0_LBV_BUFFER_LEVEL_STATUS_BASE_IDX 2
+#define mmLBV0_LBV_BUFFER_URGENCY_CTRL 0x11b0
+#define mmLBV0_LBV_BUFFER_URGENCY_CTRL_BASE_IDX 2
+#define mmLBV0_LBV_BUFFER_URGENCY_STATUS 0x11b1
+#define mmLBV0_LBV_BUFFER_URGENCY_STATUS_BASE_IDX 2
+#define mmLBV0_LBV_BUFFER_STATUS 0x11b2
+#define mmLBV0_LBV_BUFFER_STATUS_BASE_IDX 2
+#define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS 0x11b3
+#define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_sclv0_dispdec
+// base address: 0x0
+#define mmSCLV0_SCLV_COEF_RAM_SELECT 0x11ca
+#define mmSCLV0_SCLV_COEF_RAM_SELECT_BASE_IDX 2
+#define mmSCLV0_SCLV_COEF_RAM_TAP_DATA 0x11cb
+#define mmSCLV0_SCLV_COEF_RAM_TAP_DATA_BASE_IDX 2
+#define mmSCLV0_SCLV_MODE 0x11cc
+#define mmSCLV0_SCLV_MODE_BASE_IDX 2
+#define mmSCLV0_SCLV_TAP_CONTROL 0x11cd
+#define mmSCLV0_SCLV_TAP_CONTROL_BASE_IDX 2
+#define mmSCLV0_SCLV_CONTROL 0x11ce
+#define mmSCLV0_SCLV_CONTROL_BASE_IDX 2
+#define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL 0x11cf
+#define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+#define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL 0x11d0
+#define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
+#define mmSCLV0_SCLV_HORZ_FILTER_CONTROL 0x11d1
+#define mmSCLV0_SCLV_HORZ_FILTER_CONTROL_BASE_IDX 2
+#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO 0x11d2
+#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmSCLV0_SCLV_HORZ_FILTER_INIT 0x11d3
+#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BASE_IDX 2
+#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C 0x11d4
+#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
+#define mmSCLV0_SCLV_HORZ_FILTER_INIT_C 0x11d5
+#define mmSCLV0_SCLV_HORZ_FILTER_INIT_C_BASE_IDX 2
+#define mmSCLV0_SCLV_VERT_FILTER_CONTROL 0x11d6
+#define mmSCLV0_SCLV_VERT_FILTER_CONTROL_BASE_IDX 2
+#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO 0x11d7
+#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmSCLV0_SCLV_VERT_FILTER_INIT 0x11d8
+#define mmSCLV0_SCLV_VERT_FILTER_INIT_BASE_IDX 2
+#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT 0x11d9
+#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_BASE_IDX 2
+#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C 0x11da
+#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
+#define mmSCLV0_SCLV_VERT_FILTER_INIT_C 0x11db
+#define mmSCLV0_SCLV_VERT_FILTER_INIT_C_BASE_IDX 2
+#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C 0x11dc
+#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
+#define mmSCLV0_SCLV_ROUND_OFFSET 0x11dd
+#define mmSCLV0_SCLV_ROUND_OFFSET_BASE_IDX 2
+#define mmSCLV0_SCLV_UPDATE 0x11de
+#define mmSCLV0_SCLV_UPDATE_BASE_IDX 2
+#define mmSCLV0_SCLV_ALU_CONTROL 0x11df
+#define mmSCLV0_SCLV_ALU_CONTROL_BASE_IDX 2
+#define mmSCLV0_SCLV_VIEWPORT_START 0x11e0
+#define mmSCLV0_SCLV_VIEWPORT_START_BASE_IDX 2
+#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY 0x11e1
+#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_BASE_IDX 2
+#define mmSCLV0_SCLV_VIEWPORT_SIZE 0x11e2
+#define mmSCLV0_SCLV_VIEWPORT_SIZE_BASE_IDX 2
+#define mmSCLV0_SCLV_VIEWPORT_START_C 0x11e3
+#define mmSCLV0_SCLV_VIEWPORT_START_C_BASE_IDX 2
+#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C 0x11e4
+#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C_BASE_IDX 2
+#define mmSCLV0_SCLV_VIEWPORT_SIZE_C 0x11e5
+#define mmSCLV0_SCLV_VIEWPORT_SIZE_C_BASE_IDX 2
+#define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT 0x11e6
+#define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+#define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM 0x11e7
+#define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+#define mmSCLV0_SCLV_MODE_CHANGE_DET1 0x11e8
+#define mmSCLV0_SCLV_MODE_CHANGE_DET1_BASE_IDX 2
+#define mmSCLV0_SCLV_MODE_CHANGE_DET2 0x11e9
+#define mmSCLV0_SCLV_MODE_CHANGE_DET2_BASE_IDX 2
+#define mmSCLV0_SCLV_MODE_CHANGE_DET3 0x11ea
+#define mmSCLV0_SCLV_MODE_CHANGE_DET3_BASE_IDX 2
+#define mmSCLV0_SCLV_MODE_CHANGE_MASK 0x11eb
+#define mmSCLV0_SCLV_MODE_CHANGE_MASK_BASE_IDX 2
+#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT 0x11ec
+#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_BASE_IDX 2
+#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C 0x11ed
+#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C_BASE_IDX 2
+
+
+// addressBlock: dce_dc_col_man0_dispdec
+// base address: 0x0
+#define mmCOL_MAN0_COL_MAN_UPDATE 0x11fe
+#define mmCOL_MAN0_COL_MAN_UPDATE_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL 0x11ff
+#define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL_BASE_IDX 2
+#define mmCOL_MAN0_INPUT_CSC_C11_C12_A 0x1200
+#define mmCOL_MAN0_INPUT_CSC_C11_C12_A_BASE_IDX 2
+#define mmCOL_MAN0_INPUT_CSC_C13_C14_A 0x1201
+#define mmCOL_MAN0_INPUT_CSC_C13_C14_A_BASE_IDX 2
+#define mmCOL_MAN0_INPUT_CSC_C21_C22_A 0x1202
+#define mmCOL_MAN0_INPUT_CSC_C21_C22_A_BASE_IDX 2
+#define mmCOL_MAN0_INPUT_CSC_C23_C24_A 0x1203
+#define mmCOL_MAN0_INPUT_CSC_C23_C24_A_BASE_IDX 2
+#define mmCOL_MAN0_INPUT_CSC_C31_C32_A 0x1204
+#define mmCOL_MAN0_INPUT_CSC_C31_C32_A_BASE_IDX 2
+#define mmCOL_MAN0_INPUT_CSC_C33_C34_A 0x1205
+#define mmCOL_MAN0_INPUT_CSC_C33_C34_A_BASE_IDX 2
+#define mmCOL_MAN0_INPUT_CSC_C11_C12_B 0x1206
+#define mmCOL_MAN0_INPUT_CSC_C11_C12_B_BASE_IDX 2
+#define mmCOL_MAN0_INPUT_CSC_C13_C14_B 0x1207
+#define mmCOL_MAN0_INPUT_CSC_C13_C14_B_BASE_IDX 2
+#define mmCOL_MAN0_INPUT_CSC_C21_C22_B 0x1208
+#define mmCOL_MAN0_INPUT_CSC_C21_C22_B_BASE_IDX 2
+#define mmCOL_MAN0_INPUT_CSC_C23_C24_B 0x1209
+#define mmCOL_MAN0_INPUT_CSC_C23_C24_B_BASE_IDX 2
+#define mmCOL_MAN0_INPUT_CSC_C31_C32_B 0x120a
+#define mmCOL_MAN0_INPUT_CSC_C31_C32_B_BASE_IDX 2
+#define mmCOL_MAN0_INPUT_CSC_C33_C34_B 0x120b
+#define mmCOL_MAN0_INPUT_CSC_C33_C34_B_BASE_IDX 2
+#define mmCOL_MAN0_PRESCALE_CONTROL 0x120c
+#define mmCOL_MAN0_PRESCALE_CONTROL_BASE_IDX 2
+#define mmCOL_MAN0_PRESCALE_VALUES_R 0x120d
+#define mmCOL_MAN0_PRESCALE_VALUES_R_BASE_IDX 2
+#define mmCOL_MAN0_PRESCALE_VALUES_G 0x120e
+#define mmCOL_MAN0_PRESCALE_VALUES_G_BASE_IDX 2
+#define mmCOL_MAN0_PRESCALE_VALUES_B 0x120f
+#define mmCOL_MAN0_PRESCALE_VALUES_B_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL 0x1210
+#define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL_BASE_IDX 2
+#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A 0x1211
+#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A_BASE_IDX 2
+#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A 0x1212
+#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A_BASE_IDX 2
+#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A 0x1213
+#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A_BASE_IDX 2
+#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A 0x1214
+#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A_BASE_IDX 2
+#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A 0x1215
+#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A_BASE_IDX 2
+#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A 0x1216
+#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A_BASE_IDX 2
+#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B 0x1217
+#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B_BASE_IDX 2
+#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B 0x1218
+#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B_BASE_IDX 2
+#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B 0x1219
+#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B_BASE_IDX 2
+#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B 0x121a
+#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B_BASE_IDX 2
+#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B 0x121b
+#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B_BASE_IDX 2
+#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B 0x121c
+#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B_BASE_IDX 2
+#define mmCOL_MAN0_DENORM_CLAMP_CONTROL 0x121d
+#define mmCOL_MAN0_DENORM_CLAMP_CONTROL_BASE_IDX 2
+#define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR 0x121e
+#define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR_BASE_IDX 2
+#define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y 0x121f
+#define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y_BASE_IDX 2
+#define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB 0x1220
+#define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD 0x1221
+#define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL 0x1222
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX 0x1223
+#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA 0x1224
+#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK 0x1225
+#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL 0x1226
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL 0x1227
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1 0x1228
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2 0x1229
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1 0x122a
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3 0x122b
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5 0x122c
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7 0x122d
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9 0x122e
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11 0x122f
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13 0x1230
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15 0x1231
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL 0x1232
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL 0x1233
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1 0x1234
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2 0x1235
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1 0x1236
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3 0x1237
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5 0x1238
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7 0x1239
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9 0x123a
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11 0x123b
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13 0x123c
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15 0x123d
+#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
+#define mmCOL_MAN0_PACK_FIFO_ERROR 0x123e
+#define mmCOL_MAN0_PACK_FIFO_ERROR_BASE_IDX 2
+#define mmCOL_MAN0_OUTPUT_FIFO_ERROR 0x123f
+#define mmCOL_MAN0_OUTPUT_FIFO_ERROR_BASE_IDX 2
+#define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL 0x1240
+#define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL_BASE_IDX 2
+#define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX 0x1241
+#define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX_BASE_IDX 2
+#define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR 0x1242
+#define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR_BASE_IDX 2
+#define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA 0x1243
+#define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA_BASE_IDX 2
+#define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR 0x1244
+#define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1 0x1245
+#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2 0x1246
+#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2_BASE_IDX 2
+#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B 0x1247
+#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B_BASE_IDX 2
+#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G 0x1248
+#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G_BASE_IDX 2
+#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R 0x1249
+#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL 0x124a
+#define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL 0x124b
+#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12 0x124c
+#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14 0x124d
+#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22 0x124e
+#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24 0x124f
+#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32 0x1250
+#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32_BASE_IDX 2
+#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34 0x1251
+#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcfev0_dispdec
+// base address: 0x0
+#define mmDCFEV0_DCFEV_CLOCK_CONTROL 0x127e
+#define mmDCFEV0_DCFEV_CLOCK_CONTROL_BASE_IDX 2
+#define mmDCFEV0_DCFEV_SOFT_RESET 0x127f
+#define mmDCFEV0_DCFEV_SOFT_RESET_BASE_IDX 2
+#define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL 0x1280
+#define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL_BASE_IDX 2
+#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL 0x1282
+#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL_BASE_IDX 2
+#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS 0x1283
+#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS_BASE_IDX 2
+#define mmDCFEV0_DCFEV_MEM_PWR_CTRL 0x1284
+#define mmDCFEV0_DCFEV_MEM_PWR_CTRL_BASE_IDX 2
+#define mmDCFEV0_DCFEV_MEM_PWR_CTRL2 0x1285
+#define mmDCFEV0_DCFEV_MEM_PWR_CTRL2_BASE_IDX 2
+#define mmDCFEV0_DCFEV_MEM_PWR_STATUS 0x1286
+#define mmDCFEV0_DCFEV_MEM_PWR_STATUS_BASE_IDX 2
+#define mmDCFEV0_DCFEV_L_FLUSH 0x1287
+#define mmDCFEV0_DCFEV_L_FLUSH_BASE_IDX 2
+#define mmDCFEV0_DCFEV_C_FLUSH 0x1288
+#define mmDCFEV0_DCFEV_C_FLUSH_BASE_IDX 2
+#define mmDCFEV0_DCFEV_MISC 0x128a
+#define mmDCFEV0_DCFEV_MISC_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_perfmon11_dispdec
+// base address: 0x49c8
+#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x1292
+#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x1293
+#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x1294
+#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON11_PERFMON_CNTL 0x1295
+#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON11_PERFMON_CNTL2 0x1296
+#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x1297
+#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x1298
+#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON11_PERFMON_HI 0x1299
+#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON11_PERFMON_LOW 0x129a
+#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dmifv_pg0_dispdec
+// base address: 0x0
+#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1 0x129e
+#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
+#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2 0x129f
+#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
+#define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL 0x12a0
+#define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL_BASE_IDX 2
+#define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL 0x12a1
+#define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL_BASE_IDX 2
+#define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL 0x12a2
+#define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL_BASE_IDX 2
+#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL 0x12a3
+#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_BASE_IDX 2
+#define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x12a4
+#define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2
+#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x12a5
+#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2
+#define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM 0x12a6
+#define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM_BASE_IDX 2
+#define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL 0x12aa
+#define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL_BASE_IDX 2
+#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1 0x12ab
+#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
+#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2 0x12ac
+#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
+#define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL 0x12ad
+#define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL_BASE_IDX 2
+#define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL 0x12ae
+#define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL_BASE_IDX 2
+#define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL 0x12af
+#define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL_BASE_IDX 2
+#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL 0x12b0
+#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_BASE_IDX 2
+#define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x12b1
+#define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2
+#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x12b2
+#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2
+#define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM 0x12b3
+#define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM_BASE_IDX 2
+#define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL 0x12b7
+#define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_blndv0_dispdec
+// base address: 0x0
+#define mmBLNDV0_BLNDV_CONTROL 0x12db
+#define mmBLNDV0_BLNDV_CONTROL_BASE_IDX 2
+#define mmBLNDV0_BLNDV_SM_CONTROL2 0x12dc
+#define mmBLNDV0_BLNDV_SM_CONTROL2_BASE_IDX 2
+#define mmBLNDV0_BLNDV_CONTROL2 0x12dd
+#define mmBLNDV0_BLNDV_CONTROL2_BASE_IDX 2
+#define mmBLNDV0_BLNDV_UPDATE 0x12de
+#define mmBLNDV0_BLNDV_UPDATE_BASE_IDX 2
+#define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT 0x12df
+#define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT_BASE_IDX 2
+#define mmBLNDV0_BLNDV_V_UPDATE_LOCK 0x12e0
+#define mmBLNDV0_BLNDV_V_UPDATE_LOCK_BASE_IDX 2
+#define mmBLNDV0_BLNDV_REG_UPDATE_STATUS 0x12e1
+#define mmBLNDV0_BLNDV_REG_UPDATE_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_crtcv0_dispdec
+// base address: 0x0
+#define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM 0x12e6
+#define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM_BASE_IDX 2
+#define mmCRTCV0_CRTCV_H_TOTAL 0x12e7
+#define mmCRTCV0_CRTCV_H_TOTAL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_H_BLANK_START_END 0x12e8
+#define mmCRTCV0_CRTCV_H_BLANK_START_END_BASE_IDX 2
+#define mmCRTCV0_CRTCV_H_SYNC_A 0x12e9
+#define mmCRTCV0_CRTCV_H_SYNC_A_BASE_IDX 2
+#define mmCRTCV0_CRTCV_H_SYNC_A_CNTL 0x12ea
+#define mmCRTCV0_CRTCV_H_SYNC_A_CNTL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_H_SYNC_B 0x12eb
+#define mmCRTCV0_CRTCV_H_SYNC_B_BASE_IDX 2
+#define mmCRTCV0_CRTCV_H_SYNC_B_CNTL 0x12ec
+#define mmCRTCV0_CRTCV_H_SYNC_B_CNTL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_VBI_END 0x12ed
+#define mmCRTCV0_CRTCV_VBI_END_BASE_IDX 2
+#define mmCRTCV0_CRTCV_V_TOTAL 0x12ee
+#define mmCRTCV0_CRTCV_V_TOTAL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_V_TOTAL_MIN 0x12ef
+#define mmCRTCV0_CRTCV_V_TOTAL_MIN_BASE_IDX 2
+#define mmCRTCV0_CRTCV_V_TOTAL_MAX 0x12f0
+#define mmCRTCV0_CRTCV_V_TOTAL_MAX_BASE_IDX 2
+#define mmCRTCV0_CRTCV_V_TOTAL_CONTROL 0x12f1
+#define mmCRTCV0_CRTCV_V_TOTAL_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS 0x12f2
+#define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS_BASE_IDX 2
+#define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS 0x12f3
+#define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+#define mmCRTCV0_CRTCV_V_BLANK_START_END 0x12f4
+#define mmCRTCV0_CRTCV_V_BLANK_START_END_BASE_IDX 2
+#define mmCRTCV0_CRTCV_V_SYNC_A 0x12f5
+#define mmCRTCV0_CRTCV_V_SYNC_A_BASE_IDX 2
+#define mmCRTCV0_CRTCV_V_SYNC_A_CNTL 0x12f6
+#define mmCRTCV0_CRTCV_V_SYNC_A_CNTL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_V_SYNC_B 0x12f7
+#define mmCRTCV0_CRTCV_V_SYNC_B_BASE_IDX 2
+#define mmCRTCV0_CRTCV_V_SYNC_B_CNTL 0x12f8
+#define mmCRTCV0_CRTCV_V_SYNC_B_CNTL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_DTMTEST_CNTL 0x12f9
+#define mmCRTCV0_CRTCV_DTMTEST_CNTL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION 0x12fa
+#define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION_BASE_IDX 2
+#define mmCRTCV0_CRTCV_TRIGA_CNTL 0x12fb
+#define mmCRTCV0_CRTCV_TRIGA_CNTL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG 0x12fc
+#define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG_BASE_IDX 2
+#define mmCRTCV0_CRTCV_TRIGB_CNTL 0x12fd
+#define mmCRTCV0_CRTCV_TRIGB_CNTL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG 0x12fe
+#define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG_BASE_IDX 2
+#define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL 0x12ff
+#define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_FLOW_CONTROL 0x1300
+#define mmCRTCV0_CRTCV_FLOW_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE 0x1301
+#define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+#define mmCRTCV0_CRTCV_AVSYNC_COUNTER 0x1302
+#define mmCRTCV0_CRTCV_AVSYNC_COUNTER_BASE_IDX 2
+#define mmCRTCV0_CRTCV_CONTROL 0x1303
+#define mmCRTCV0_CRTCV_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_BLANK_CONTROL 0x1304
+#define mmCRTCV0_CRTCV_BLANK_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_INTERLACE_CONTROL 0x1305
+#define mmCRTCV0_CRTCV_INTERLACE_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_INTERLACE_STATUS 0x1306
+#define mmCRTCV0_CRTCV_INTERLACE_STATUS_BASE_IDX 2
+#define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL 0x1307
+#define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0 0x1308
+#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0_BASE_IDX 2
+#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1 0x1309
+#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1_BASE_IDX 2
+#define mmCRTCV0_CRTCV_STATUS 0x130a
+#define mmCRTCV0_CRTCV_STATUS_BASE_IDX 2
+#define mmCRTCV0_CRTCV_STATUS_POSITION 0x130b
+#define mmCRTCV0_CRTCV_STATUS_POSITION_BASE_IDX 2
+#define mmCRTCV0_CRTCV_NOM_VERT_POSITION 0x130c
+#define mmCRTCV0_CRTCV_NOM_VERT_POSITION_BASE_IDX 2
+#define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT 0x130d
+#define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT_BASE_IDX 2
+#define mmCRTCV0_CRTCV_STATUS_VF_COUNT 0x130e
+#define mmCRTCV0_CRTCV_STATUS_VF_COUNT_BASE_IDX 2
+#define mmCRTCV0_CRTCV_STATUS_HV_COUNT 0x130f
+#define mmCRTCV0_CRTCV_STATUS_HV_COUNT_BASE_IDX 2
+#define mmCRTCV0_CRTCV_COUNT_CONTROL 0x1310
+#define mmCRTCV0_CRTCV_COUNT_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_COUNT_RESET 0x1311
+#define mmCRTCV0_CRTCV_COUNT_RESET_BASE_IDX 2
+#define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1312
+#define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+#define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL 0x1313
+#define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_STEREO_STATUS 0x1314
+#define mmCRTCV0_CRTCV_STEREO_STATUS_BASE_IDX 2
+#define mmCRTCV0_CRTCV_STEREO_CONTROL 0x1315
+#define mmCRTCV0_CRTCV_STEREO_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_SNAPSHOT_STATUS 0x1316
+#define mmCRTCV0_CRTCV_SNAPSHOT_STATUS_BASE_IDX 2
+#define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL 0x1317
+#define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_SNAPSHOT_POSITION 0x1318
+#define mmCRTCV0_CRTCV_SNAPSHOT_POSITION_BASE_IDX 2
+#define mmCRTCV0_CRTCV_SNAPSHOT_FRAME 0x1319
+#define mmCRTCV0_CRTCV_SNAPSHOT_FRAME_BASE_IDX 2
+#define mmCRTCV0_CRTCV_START_LINE_CONTROL 0x131a
+#define mmCRTCV0_CRTCV_START_LINE_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_INTERRUPT_CONTROL 0x131b
+#define mmCRTCV0_CRTCV_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_UPDATE_LOCK 0x131c
+#define mmCRTCV0_CRTCV_UPDATE_LOCK_BASE_IDX 2
+#define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL 0x131d
+#define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE 0x131e
+#define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
+#define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL 0x131f
+#define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS 0x1320
+#define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS_BASE_IDX 2
+#define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR 0x1321
+#define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR_BASE_IDX 2
+#define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK 0x1322
+#define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK_BASE_IDX 2
+#define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE 0x1323
+#define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE_BASE_IDX 2
+#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT 0x1324
+#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
+#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0x1325
+#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
+#define mmCRTCV0_CRTCV_MVP_STATUS 0x1326
+#define mmCRTCV0_CRTCV_MVP_STATUS_BASE_IDX 2
+#define mmCRTCV0_CRTCV_MASTER_EN 0x1327
+#define mmCRTCV0_CRTCV_MASTER_EN_BASE_IDX 2
+#define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT 0x1328
+#define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
+#define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS 0x1329
+#define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS_BASE_IDX 2
+#define mmCRTCV0_CRTCV_OVERSCAN_COLOR 0x132b
+#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_BASE_IDX 2
+#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT 0x132c
+#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT_BASE_IDX 2
+#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR 0x132d
+#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_BASE_IDX 2
+#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT 0x132e
+#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+#define mmCRTCV0_CRTCV_BLACK_COLOR 0x132f
+#define mmCRTCV0_CRTCV_BLACK_COLOR_BASE_IDX 2
+#define mmCRTCV0_CRTCV_BLACK_COLOR_EXT 0x1330
+#define mmCRTCV0_CRTCV_BLACK_COLOR_EXT_BASE_IDX 2
+#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION 0x1331
+#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL 0x1332
+#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION 0x1333
+#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL 0x1334
+#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION 0x1335
+#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL 0x1336
+#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_CRC_CNTL 0x1337
+#define mmCRTCV0_CRTCV_CRC_CNTL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL 0x1338
+#define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL 0x1339
+#define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL 0x133a
+#define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL 0x133b
+#define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_CRC0_DATA_RG 0x133c
+#define mmCRTCV0_CRTCV_CRC0_DATA_RG_BASE_IDX 2
+#define mmCRTCV0_CRTCV_CRC0_DATA_B 0x133d
+#define mmCRTCV0_CRTCV_CRC0_DATA_B_BASE_IDX 2
+#define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL 0x133e
+#define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL 0x133f
+#define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL 0x1340
+#define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL 0x1341
+#define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_CRC1_DATA_RG 0x1342
+#define mmCRTCV0_CRTCV_CRC1_DATA_RG_BASE_IDX 2
+#define mmCRTCV0_CRTCV_CRC1_DATA_B 0x1343
+#define mmCRTCV0_CRTCV_CRC1_DATA_B_BASE_IDX 2
+#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL 0x1344
+#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START 0x1345
+#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
+#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END 0x1346
+#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
+#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1347
+#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1348
+#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1349
+#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL 0x134a
+#define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL 0x134b
+#define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL_BASE_IDX 2
+#define mmCRTCV0_CRTCV_GSL_VSYNC_GAP 0x134c
+#define mmCRTCV0_CRTCV_GSL_VSYNC_GAP_BASE_IDX 2
+#define mmCRTCV0_CRTCV_GSL_WINDOW 0x134d
+#define mmCRTCV0_CRTCV_GSL_WINDOW_BASE_IDX 2
+#define mmCRTCV0_CRTCV_GSL_CONTROL 0x134e
+#define mmCRTCV0_CRTCV_GSL_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_unp1_dispdec
+// base address: 0x800
+#define mmUNP1_UNP_GRPH_ENABLE 0x135a
+#define mmUNP1_UNP_GRPH_ENABLE_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_CONTROL 0x135b
+#define mmUNP1_UNP_GRPH_CONTROL_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_CONTROL_C 0x135c
+#define mmUNP1_UNP_GRPH_CONTROL_C_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_CONTROL_EXP 0x135d
+#define mmUNP1_UNP_GRPH_CONTROL_EXP_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_SWAP_CNTL 0x135e
+#define mmUNP1_UNP_GRPH_SWAP_CNTL_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x135f
+#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x1360
+#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x1361
+#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x1362
+#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x1363
+#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x1364
+#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x1365
+#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x1366
+#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x1367
+#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x1368
+#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x1369
+#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x136a
+#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x136b
+#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x136c
+#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x136d
+#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x136e
+#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_PITCH_L 0x136f
+#define mmUNP1_UNP_GRPH_PITCH_L_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_PITCH_C 0x1370
+#define mmUNP1_UNP_GRPH_PITCH_C_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L 0x1371
+#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C 0x1372
+#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L 0x1373
+#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C 0x1374
+#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_X_START_L 0x1375
+#define mmUNP1_UNP_GRPH_X_START_L_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_X_START_C 0x1376
+#define mmUNP1_UNP_GRPH_X_START_C_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_Y_START_L 0x1377
+#define mmUNP1_UNP_GRPH_Y_START_L_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_Y_START_C 0x1378
+#define mmUNP1_UNP_GRPH_Y_START_C_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_X_END_L 0x1379
+#define mmUNP1_UNP_GRPH_X_END_L_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_X_END_C 0x137a
+#define mmUNP1_UNP_GRPH_X_END_C_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_Y_END_L 0x137b
+#define mmUNP1_UNP_GRPH_Y_END_L_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_Y_END_C 0x137c
+#define mmUNP1_UNP_GRPH_Y_END_C_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_UPDATE 0x137d
+#define mmUNP1_UNP_GRPH_UPDATE_BASE_IDX 2
+#define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x137e
+#define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x137f
+#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x1380
+#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x1381
+#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x1382
+#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_BASE_IDX 2
+#define mmUNP1_UNP_DVMM_PTE_CONTROL 0x1383
+#define mmUNP1_UNP_DVMM_PTE_CONTROL_BASE_IDX 2
+#define mmUNP1_UNP_DVMM_PTE_CONTROL_C 0x1384
+#define mmUNP1_UNP_DVMM_PTE_CONTROL_C_BASE_IDX 2
+#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL 0x1385
+#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
+#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C 0x1386
+#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_INTERRUPT_STATUS 0x1387
+#define mmUNP1_UNP_GRPH_INTERRUPT_STATUS_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL 0x1388
+#define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP 0x1389
+#define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
+#define mmUNP1_UNP_FLIP_CONTROL 0x138a
+#define mmUNP1_UNP_FLIP_CONTROL_BASE_IDX 2
+#define mmUNP1_UNP_CRC_CONTROL 0x138b
+#define mmUNP1_UNP_CRC_CONTROL_BASE_IDX 2
+#define mmUNP1_UNP_CRC_MASK 0x138c
+#define mmUNP1_UNP_CRC_MASK_BASE_IDX 2
+#define mmUNP1_UNP_CRC_CURRENT 0x138d
+#define mmUNP1_UNP_CRC_CURRENT_BASE_IDX 2
+#define mmUNP1_UNP_CRC_LAST 0x138e
+#define mmUNP1_UNP_CRC_LAST_BASE_IDX 2
+#define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK 0x138f
+#define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
+#define mmUNP1_UNP_HW_ROTATION 0x1390
+#define mmUNP1_UNP_HW_ROTATION_BASE_IDX 2
+
+
+// addressBlock: dce_dc_lbv1_dispdec
+// base address: 0x800
+#define mmLBV1_LBV_DATA_FORMAT 0x1396
+#define mmLBV1_LBV_DATA_FORMAT_BASE_IDX 2
+#define mmLBV1_LBV_MEMORY_CTRL 0x1397
+#define mmLBV1_LBV_MEMORY_CTRL_BASE_IDX 2
+#define mmLBV1_LBV_MEMORY_SIZE_STATUS 0x1398
+#define mmLBV1_LBV_MEMORY_SIZE_STATUS_BASE_IDX 2
+#define mmLBV1_LBV_DESKTOP_HEIGHT 0x1399
+#define mmLBV1_LBV_DESKTOP_HEIGHT_BASE_IDX 2
+#define mmLBV1_LBV_VLINE_START_END 0x139a
+#define mmLBV1_LBV_VLINE_START_END_BASE_IDX 2
+#define mmLBV1_LBV_VLINE2_START_END 0x139b
+#define mmLBV1_LBV_VLINE2_START_END_BASE_IDX 2
+#define mmLBV1_LBV_V_COUNTER 0x139c
+#define mmLBV1_LBV_V_COUNTER_BASE_IDX 2
+#define mmLBV1_LBV_SNAPSHOT_V_COUNTER 0x139d
+#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_BASE_IDX 2
+#define mmLBV1_LBV_V_COUNTER_CHROMA 0x139e
+#define mmLBV1_LBV_V_COUNTER_CHROMA_BASE_IDX 2
+#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA 0x139f
+#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA_BASE_IDX 2
+#define mmLBV1_LBV_INTERRUPT_MASK 0x13a0
+#define mmLBV1_LBV_INTERRUPT_MASK_BASE_IDX 2
+#define mmLBV1_LBV_VLINE_STATUS 0x13a1
+#define mmLBV1_LBV_VLINE_STATUS_BASE_IDX 2
+#define mmLBV1_LBV_VLINE2_STATUS 0x13a2
+#define mmLBV1_LBV_VLINE2_STATUS_BASE_IDX 2
+#define mmLBV1_LBV_VBLANK_STATUS 0x13a3
+#define mmLBV1_LBV_VBLANK_STATUS_BASE_IDX 2
+#define mmLBV1_LBV_SYNC_RESET_SEL 0x13a4
+#define mmLBV1_LBV_SYNC_RESET_SEL_BASE_IDX 2
+#define mmLBV1_LBV_BLACK_KEYER_R_CR 0x13a5
+#define mmLBV1_LBV_BLACK_KEYER_R_CR_BASE_IDX 2
+#define mmLBV1_LBV_BLACK_KEYER_G_Y 0x13a6
+#define mmLBV1_LBV_BLACK_KEYER_G_Y_BASE_IDX 2
+#define mmLBV1_LBV_BLACK_KEYER_B_CB 0x13a7
+#define mmLBV1_LBV_BLACK_KEYER_B_CB_BASE_IDX 2
+#define mmLBV1_LBV_KEYER_COLOR_CTRL 0x13a8
+#define mmLBV1_LBV_KEYER_COLOR_CTRL_BASE_IDX 2
+#define mmLBV1_LBV_KEYER_COLOR_R_CR 0x13a9
+#define mmLBV1_LBV_KEYER_COLOR_R_CR_BASE_IDX 2
+#define mmLBV1_LBV_KEYER_COLOR_G_Y 0x13aa
+#define mmLBV1_LBV_KEYER_COLOR_G_Y_BASE_IDX 2
+#define mmLBV1_LBV_KEYER_COLOR_B_CB 0x13ab
+#define mmLBV1_LBV_KEYER_COLOR_B_CB_BASE_IDX 2
+#define mmLBV1_LBV_KEYER_COLOR_REP_R_CR 0x13ac
+#define mmLBV1_LBV_KEYER_COLOR_REP_R_CR_BASE_IDX 2
+#define mmLBV1_LBV_KEYER_COLOR_REP_G_Y 0x13ad
+#define mmLBV1_LBV_KEYER_COLOR_REP_G_Y_BASE_IDX 2
+#define mmLBV1_LBV_KEYER_COLOR_REP_B_CB 0x13ae
+#define mmLBV1_LBV_KEYER_COLOR_REP_B_CB_BASE_IDX 2
+#define mmLBV1_LBV_BUFFER_LEVEL_STATUS 0x13af
+#define mmLBV1_LBV_BUFFER_LEVEL_STATUS_BASE_IDX 2
+#define mmLBV1_LBV_BUFFER_URGENCY_CTRL 0x13b0
+#define mmLBV1_LBV_BUFFER_URGENCY_CTRL_BASE_IDX 2
+#define mmLBV1_LBV_BUFFER_URGENCY_STATUS 0x13b1
+#define mmLBV1_LBV_BUFFER_URGENCY_STATUS_BASE_IDX 2
+#define mmLBV1_LBV_BUFFER_STATUS 0x13b2
+#define mmLBV1_LBV_BUFFER_STATUS_BASE_IDX 2
+#define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS 0x13b3
+#define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_sclv1_dispdec
+// base address: 0x800
+#define mmSCLV1_SCLV_COEF_RAM_SELECT 0x13ca
+#define mmSCLV1_SCLV_COEF_RAM_SELECT_BASE_IDX 2
+#define mmSCLV1_SCLV_COEF_RAM_TAP_DATA 0x13cb
+#define mmSCLV1_SCLV_COEF_RAM_TAP_DATA_BASE_IDX 2
+#define mmSCLV1_SCLV_MODE 0x13cc
+#define mmSCLV1_SCLV_MODE_BASE_IDX 2
+#define mmSCLV1_SCLV_TAP_CONTROL 0x13cd
+#define mmSCLV1_SCLV_TAP_CONTROL_BASE_IDX 2
+#define mmSCLV1_SCLV_CONTROL 0x13ce
+#define mmSCLV1_SCLV_CONTROL_BASE_IDX 2
+#define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL 0x13cf
+#define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+#define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL 0x13d0
+#define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
+#define mmSCLV1_SCLV_HORZ_FILTER_CONTROL 0x13d1
+#define mmSCLV1_SCLV_HORZ_FILTER_CONTROL_BASE_IDX 2
+#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO 0x13d2
+#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmSCLV1_SCLV_HORZ_FILTER_INIT 0x13d3
+#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BASE_IDX 2
+#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C 0x13d4
+#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
+#define mmSCLV1_SCLV_HORZ_FILTER_INIT_C 0x13d5
+#define mmSCLV1_SCLV_HORZ_FILTER_INIT_C_BASE_IDX 2
+#define mmSCLV1_SCLV_VERT_FILTER_CONTROL 0x13d6
+#define mmSCLV1_SCLV_VERT_FILTER_CONTROL_BASE_IDX 2
+#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO 0x13d7
+#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmSCLV1_SCLV_VERT_FILTER_INIT 0x13d8
+#define mmSCLV1_SCLV_VERT_FILTER_INIT_BASE_IDX 2
+#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT 0x13d9
+#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_BASE_IDX 2
+#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C 0x13da
+#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
+#define mmSCLV1_SCLV_VERT_FILTER_INIT_C 0x13db
+#define mmSCLV1_SCLV_VERT_FILTER_INIT_C_BASE_IDX 2
+#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C 0x13dc
+#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
+#define mmSCLV1_SCLV_ROUND_OFFSET 0x13dd
+#define mmSCLV1_SCLV_ROUND_OFFSET_BASE_IDX 2
+#define mmSCLV1_SCLV_UPDATE 0x13de
+#define mmSCLV1_SCLV_UPDATE_BASE_IDX 2
+#define mmSCLV1_SCLV_ALU_CONTROL 0x13df
+#define mmSCLV1_SCLV_ALU_CONTROL_BASE_IDX 2
+#define mmSCLV1_SCLV_VIEWPORT_START 0x13e0
+#define mmSCLV1_SCLV_VIEWPORT_START_BASE_IDX 2
+#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY 0x13e1
+#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_BASE_IDX 2
+#define mmSCLV1_SCLV_VIEWPORT_SIZE 0x13e2
+#define mmSCLV1_SCLV_VIEWPORT_SIZE_BASE_IDX 2
+#define mmSCLV1_SCLV_VIEWPORT_START_C 0x13e3
+#define mmSCLV1_SCLV_VIEWPORT_START_C_BASE_IDX 2
+#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C 0x13e4
+#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C_BASE_IDX 2
+#define mmSCLV1_SCLV_VIEWPORT_SIZE_C 0x13e5
+#define mmSCLV1_SCLV_VIEWPORT_SIZE_C_BASE_IDX 2
+#define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT 0x13e6
+#define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+#define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM 0x13e7
+#define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+#define mmSCLV1_SCLV_MODE_CHANGE_DET1 0x13e8
+#define mmSCLV1_SCLV_MODE_CHANGE_DET1_BASE_IDX 2
+#define mmSCLV1_SCLV_MODE_CHANGE_DET2 0x13e9
+#define mmSCLV1_SCLV_MODE_CHANGE_DET2_BASE_IDX 2
+#define mmSCLV1_SCLV_MODE_CHANGE_DET3 0x13ea
+#define mmSCLV1_SCLV_MODE_CHANGE_DET3_BASE_IDX 2
+#define mmSCLV1_SCLV_MODE_CHANGE_MASK 0x13eb
+#define mmSCLV1_SCLV_MODE_CHANGE_MASK_BASE_IDX 2
+#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT 0x13ec
+#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_BASE_IDX 2
+#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C 0x13ed
+#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C_BASE_IDX 2
+
+
+// addressBlock: dce_dc_col_man1_dispdec
+// base address: 0x800
+#define mmCOL_MAN1_COL_MAN_UPDATE 0x13fe
+#define mmCOL_MAN1_COL_MAN_UPDATE_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL 0x13ff
+#define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL_BASE_IDX 2
+#define mmCOL_MAN1_INPUT_CSC_C11_C12_A 0x1400
+#define mmCOL_MAN1_INPUT_CSC_C11_C12_A_BASE_IDX 2
+#define mmCOL_MAN1_INPUT_CSC_C13_C14_A 0x1401
+#define mmCOL_MAN1_INPUT_CSC_C13_C14_A_BASE_IDX 2
+#define mmCOL_MAN1_INPUT_CSC_C21_C22_A 0x1402
+#define mmCOL_MAN1_INPUT_CSC_C21_C22_A_BASE_IDX 2
+#define mmCOL_MAN1_INPUT_CSC_C23_C24_A 0x1403
+#define mmCOL_MAN1_INPUT_CSC_C23_C24_A_BASE_IDX 2
+#define mmCOL_MAN1_INPUT_CSC_C31_C32_A 0x1404
+#define mmCOL_MAN1_INPUT_CSC_C31_C32_A_BASE_IDX 2
+#define mmCOL_MAN1_INPUT_CSC_C33_C34_A 0x1405
+#define mmCOL_MAN1_INPUT_CSC_C33_C34_A_BASE_IDX 2
+#define mmCOL_MAN1_INPUT_CSC_C11_C12_B 0x1406
+#define mmCOL_MAN1_INPUT_CSC_C11_C12_B_BASE_IDX 2
+#define mmCOL_MAN1_INPUT_CSC_C13_C14_B 0x1407
+#define mmCOL_MAN1_INPUT_CSC_C13_C14_B_BASE_IDX 2
+#define mmCOL_MAN1_INPUT_CSC_C21_C22_B 0x1408
+#define mmCOL_MAN1_INPUT_CSC_C21_C22_B_BASE_IDX 2
+#define mmCOL_MAN1_INPUT_CSC_C23_C24_B 0x1409
+#define mmCOL_MAN1_INPUT_CSC_C23_C24_B_BASE_IDX 2
+#define mmCOL_MAN1_INPUT_CSC_C31_C32_B 0x140a
+#define mmCOL_MAN1_INPUT_CSC_C31_C32_B_BASE_IDX 2
+#define mmCOL_MAN1_INPUT_CSC_C33_C34_B 0x140b
+#define mmCOL_MAN1_INPUT_CSC_C33_C34_B_BASE_IDX 2
+#define mmCOL_MAN1_PRESCALE_CONTROL 0x140c
+#define mmCOL_MAN1_PRESCALE_CONTROL_BASE_IDX 2
+#define mmCOL_MAN1_PRESCALE_VALUES_R 0x140d
+#define mmCOL_MAN1_PRESCALE_VALUES_R_BASE_IDX 2
+#define mmCOL_MAN1_PRESCALE_VALUES_G 0x140e
+#define mmCOL_MAN1_PRESCALE_VALUES_G_BASE_IDX 2
+#define mmCOL_MAN1_PRESCALE_VALUES_B 0x140f
+#define mmCOL_MAN1_PRESCALE_VALUES_B_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL 0x1410
+#define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL_BASE_IDX 2
+#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A 0x1411
+#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A_BASE_IDX 2
+#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A 0x1412
+#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A_BASE_IDX 2
+#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A 0x1413
+#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A_BASE_IDX 2
+#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A 0x1414
+#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A_BASE_IDX 2
+#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A 0x1415
+#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A_BASE_IDX 2
+#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A 0x1416
+#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A_BASE_IDX 2
+#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B 0x1417
+#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B_BASE_IDX 2
+#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B 0x1418
+#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B_BASE_IDX 2
+#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B 0x1419
+#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B_BASE_IDX 2
+#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B 0x141a
+#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B_BASE_IDX 2
+#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B 0x141b
+#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B_BASE_IDX 2
+#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B 0x141c
+#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B_BASE_IDX 2
+#define mmCOL_MAN1_DENORM_CLAMP_CONTROL 0x141d
+#define mmCOL_MAN1_DENORM_CLAMP_CONTROL_BASE_IDX 2
+#define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR 0x141e
+#define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR_BASE_IDX 2
+#define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y 0x141f
+#define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y_BASE_IDX 2
+#define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB 0x1420
+#define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD 0x1421
+#define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL 0x1422
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX 0x1423
+#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA 0x1424
+#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK 0x1425
+#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL 0x1426
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL 0x1427
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1 0x1428
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2 0x1429
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1 0x142a
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3 0x142b
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5 0x142c
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7 0x142d
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9 0x142e
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11 0x142f
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13 0x1430
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15 0x1431
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL 0x1432
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL 0x1433
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1 0x1434
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2 0x1435
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1 0x1436
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3 0x1437
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5 0x1438
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7 0x1439
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9 0x143a
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11 0x143b
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13 0x143c
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15 0x143d
+#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
+#define mmCOL_MAN1_PACK_FIFO_ERROR 0x143e
+#define mmCOL_MAN1_PACK_FIFO_ERROR_BASE_IDX 2
+#define mmCOL_MAN1_OUTPUT_FIFO_ERROR 0x143f
+#define mmCOL_MAN1_OUTPUT_FIFO_ERROR_BASE_IDX 2
+#define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL 0x1440
+#define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL_BASE_IDX 2
+#define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX 0x1441
+#define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX_BASE_IDX 2
+#define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR 0x1442
+#define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR_BASE_IDX 2
+#define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA 0x1443
+#define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA_BASE_IDX 2
+#define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR 0x1444
+#define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1 0x1445
+#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2 0x1446
+#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2_BASE_IDX 2
+#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B 0x1447
+#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B_BASE_IDX 2
+#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G 0x1448
+#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G_BASE_IDX 2
+#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R 0x1449
+#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL 0x144a
+#define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL 0x144b
+#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12 0x144c
+#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14 0x144d
+#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22 0x144e
+#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24 0x144f
+#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32 0x1450
+#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32_BASE_IDX 2
+#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34 0x1451
+#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcfev1_dispdec
+// base address: 0x800
+#define mmDCFEV1_DCFEV_CLOCK_CONTROL 0x147e
+#define mmDCFEV1_DCFEV_CLOCK_CONTROL_BASE_IDX 2
+#define mmDCFEV1_DCFEV_SOFT_RESET 0x147f
+#define mmDCFEV1_DCFEV_SOFT_RESET_BASE_IDX 2
+#define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL 0x1480
+#define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL_BASE_IDX 2
+#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL 0x1482
+#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL_BASE_IDX 2
+#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS 0x1483
+#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS_BASE_IDX 2
+#define mmDCFEV1_DCFEV_MEM_PWR_CTRL 0x1484
+#define mmDCFEV1_DCFEV_MEM_PWR_CTRL_BASE_IDX 2
+#define mmDCFEV1_DCFEV_MEM_PWR_CTRL2 0x1485
+#define mmDCFEV1_DCFEV_MEM_PWR_CTRL2_BASE_IDX 2
+#define mmDCFEV1_DCFEV_MEM_PWR_STATUS 0x1486
+#define mmDCFEV1_DCFEV_MEM_PWR_STATUS_BASE_IDX 2
+#define mmDCFEV1_DCFEV_L_FLUSH 0x1487
+#define mmDCFEV1_DCFEV_L_FLUSH_BASE_IDX 2
+#define mmDCFEV1_DCFEV_C_FLUSH 0x1488
+#define mmDCFEV1_DCFEV_C_FLUSH_BASE_IDX 2
+#define mmDCFEV1_DCFEV_MISC 0x148a
+#define mmDCFEV1_DCFEV_MISC_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_perfmon12_dispdec
+// base address: 0x51c8
+#define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x1492
+#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x1493
+#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON12_PERFCOUNTER_STATE 0x1494
+#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON12_PERFMON_CNTL 0x1495
+#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON12_PERFMON_CNTL2 0x1496
+#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x1497
+#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x1498
+#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON12_PERFMON_HI 0x1499
+#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON12_PERFMON_LOW 0x149a
+#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dmifv_pg1_dispdec
+// base address: 0x800
+#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1 0x149e
+#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
+#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2 0x149f
+#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
+#define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL 0x14a0
+#define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL_BASE_IDX 2
+#define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL 0x14a1
+#define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL_BASE_IDX 2
+#define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL 0x14a2
+#define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL_BASE_IDX 2
+#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL 0x14a3
+#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_BASE_IDX 2
+#define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x14a4
+#define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2
+#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x14a5
+#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2
+#define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM 0x14a6
+#define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM_BASE_IDX 2
+#define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL 0x14aa
+#define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL_BASE_IDX 2
+#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1 0x14ab
+#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
+#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2 0x14ac
+#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
+#define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL 0x14ad
+#define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL_BASE_IDX 2
+#define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL 0x14ae
+#define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL_BASE_IDX 2
+#define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL 0x14af
+#define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL_BASE_IDX 2
+#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL 0x14b0
+#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_BASE_IDX 2
+#define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x14b1
+#define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2
+#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x14b2
+#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2
+#define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM 0x14b3
+#define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM_BASE_IDX 2
+#define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL 0x14b7
+#define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_blndv1_dispdec
+// base address: 0x800
+#define mmBLNDV1_BLNDV_CONTROL 0x14db
+#define mmBLNDV1_BLNDV_CONTROL_BASE_IDX 2
+#define mmBLNDV1_BLNDV_SM_CONTROL2 0x14dc
+#define mmBLNDV1_BLNDV_SM_CONTROL2_BASE_IDX 2
+#define mmBLNDV1_BLNDV_CONTROL2 0x14dd
+#define mmBLNDV1_BLNDV_CONTROL2_BASE_IDX 2
+#define mmBLNDV1_BLNDV_UPDATE 0x14de
+#define mmBLNDV1_BLNDV_UPDATE_BASE_IDX 2
+#define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT 0x14df
+#define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT_BASE_IDX 2
+#define mmBLNDV1_BLNDV_V_UPDATE_LOCK 0x14e0
+#define mmBLNDV1_BLNDV_V_UPDATE_LOCK_BASE_IDX 2
+#define mmBLNDV1_BLNDV_REG_UPDATE_STATUS 0x14e1
+#define mmBLNDV1_BLNDV_REG_UPDATE_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_crtcv1_dispdec
+// base address: 0x800
+#define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM 0x14e6
+#define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM_BASE_IDX 2
+#define mmCRTCV1_CRTCV_H_TOTAL 0x14e7
+#define mmCRTCV1_CRTCV_H_TOTAL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_H_BLANK_START_END 0x14e8
+#define mmCRTCV1_CRTCV_H_BLANK_START_END_BASE_IDX 2
+#define mmCRTCV1_CRTCV_H_SYNC_A 0x14e9
+#define mmCRTCV1_CRTCV_H_SYNC_A_BASE_IDX 2
+#define mmCRTCV1_CRTCV_H_SYNC_A_CNTL 0x14ea
+#define mmCRTCV1_CRTCV_H_SYNC_A_CNTL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_H_SYNC_B 0x14eb
+#define mmCRTCV1_CRTCV_H_SYNC_B_BASE_IDX 2
+#define mmCRTCV1_CRTCV_H_SYNC_B_CNTL 0x14ec
+#define mmCRTCV1_CRTCV_H_SYNC_B_CNTL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_VBI_END 0x14ed
+#define mmCRTCV1_CRTCV_VBI_END_BASE_IDX 2
+#define mmCRTCV1_CRTCV_V_TOTAL 0x14ee
+#define mmCRTCV1_CRTCV_V_TOTAL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_V_TOTAL_MIN 0x14ef
+#define mmCRTCV1_CRTCV_V_TOTAL_MIN_BASE_IDX 2
+#define mmCRTCV1_CRTCV_V_TOTAL_MAX 0x14f0
+#define mmCRTCV1_CRTCV_V_TOTAL_MAX_BASE_IDX 2
+#define mmCRTCV1_CRTCV_V_TOTAL_CONTROL 0x14f1
+#define mmCRTCV1_CRTCV_V_TOTAL_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS 0x14f2
+#define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS_BASE_IDX 2
+#define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS 0x14f3
+#define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+#define mmCRTCV1_CRTCV_V_BLANK_START_END 0x14f4
+#define mmCRTCV1_CRTCV_V_BLANK_START_END_BASE_IDX 2
+#define mmCRTCV1_CRTCV_V_SYNC_A 0x14f5
+#define mmCRTCV1_CRTCV_V_SYNC_A_BASE_IDX 2
+#define mmCRTCV1_CRTCV_V_SYNC_A_CNTL 0x14f6
+#define mmCRTCV1_CRTCV_V_SYNC_A_CNTL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_V_SYNC_B 0x14f7
+#define mmCRTCV1_CRTCV_V_SYNC_B_BASE_IDX 2
+#define mmCRTCV1_CRTCV_V_SYNC_B_CNTL 0x14f8
+#define mmCRTCV1_CRTCV_V_SYNC_B_CNTL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_DTMTEST_CNTL 0x14f9
+#define mmCRTCV1_CRTCV_DTMTEST_CNTL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION 0x14fa
+#define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION_BASE_IDX 2
+#define mmCRTCV1_CRTCV_TRIGA_CNTL 0x14fb
+#define mmCRTCV1_CRTCV_TRIGA_CNTL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG 0x14fc
+#define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG_BASE_IDX 2
+#define mmCRTCV1_CRTCV_TRIGB_CNTL 0x14fd
+#define mmCRTCV1_CRTCV_TRIGB_CNTL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG 0x14fe
+#define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG_BASE_IDX 2
+#define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL 0x14ff
+#define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_FLOW_CONTROL 0x1500
+#define mmCRTCV1_CRTCV_FLOW_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE 0x1501
+#define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+#define mmCRTCV1_CRTCV_AVSYNC_COUNTER 0x1502
+#define mmCRTCV1_CRTCV_AVSYNC_COUNTER_BASE_IDX 2
+#define mmCRTCV1_CRTCV_CONTROL 0x1503
+#define mmCRTCV1_CRTCV_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_BLANK_CONTROL 0x1504
+#define mmCRTCV1_CRTCV_BLANK_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_INTERLACE_CONTROL 0x1505
+#define mmCRTCV1_CRTCV_INTERLACE_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_INTERLACE_STATUS 0x1506
+#define mmCRTCV1_CRTCV_INTERLACE_STATUS_BASE_IDX 2
+#define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL 0x1507
+#define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0 0x1508
+#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0_BASE_IDX 2
+#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1 0x1509
+#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1_BASE_IDX 2
+#define mmCRTCV1_CRTCV_STATUS 0x150a
+#define mmCRTCV1_CRTCV_STATUS_BASE_IDX 2
+#define mmCRTCV1_CRTCV_STATUS_POSITION 0x150b
+#define mmCRTCV1_CRTCV_STATUS_POSITION_BASE_IDX 2
+#define mmCRTCV1_CRTCV_NOM_VERT_POSITION 0x150c
+#define mmCRTCV1_CRTCV_NOM_VERT_POSITION_BASE_IDX 2
+#define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT 0x150d
+#define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT_BASE_IDX 2
+#define mmCRTCV1_CRTCV_STATUS_VF_COUNT 0x150e
+#define mmCRTCV1_CRTCV_STATUS_VF_COUNT_BASE_IDX 2
+#define mmCRTCV1_CRTCV_STATUS_HV_COUNT 0x150f
+#define mmCRTCV1_CRTCV_STATUS_HV_COUNT_BASE_IDX 2
+#define mmCRTCV1_CRTCV_COUNT_CONTROL 0x1510
+#define mmCRTCV1_CRTCV_COUNT_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_COUNT_RESET 0x1511
+#define mmCRTCV1_CRTCV_COUNT_RESET_BASE_IDX 2
+#define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1512
+#define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+#define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL 0x1513
+#define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_STEREO_STATUS 0x1514
+#define mmCRTCV1_CRTCV_STEREO_STATUS_BASE_IDX 2
+#define mmCRTCV1_CRTCV_STEREO_CONTROL 0x1515
+#define mmCRTCV1_CRTCV_STEREO_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_SNAPSHOT_STATUS 0x1516
+#define mmCRTCV1_CRTCV_SNAPSHOT_STATUS_BASE_IDX 2
+#define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL 0x1517
+#define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_SNAPSHOT_POSITION 0x1518
+#define mmCRTCV1_CRTCV_SNAPSHOT_POSITION_BASE_IDX 2
+#define mmCRTCV1_CRTCV_SNAPSHOT_FRAME 0x1519
+#define mmCRTCV1_CRTCV_SNAPSHOT_FRAME_BASE_IDX 2
+#define mmCRTCV1_CRTCV_START_LINE_CONTROL 0x151a
+#define mmCRTCV1_CRTCV_START_LINE_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_INTERRUPT_CONTROL 0x151b
+#define mmCRTCV1_CRTCV_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_UPDATE_LOCK 0x151c
+#define mmCRTCV1_CRTCV_UPDATE_LOCK_BASE_IDX 2
+#define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL 0x151d
+#define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE 0x151e
+#define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
+#define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL 0x151f
+#define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS 0x1520
+#define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS_BASE_IDX 2
+#define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR 0x1521
+#define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR_BASE_IDX 2
+#define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK 0x1522
+#define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK_BASE_IDX 2
+#define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE 0x1523
+#define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE_BASE_IDX 2
+#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT 0x1524
+#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
+#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0x1525
+#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
+#define mmCRTCV1_CRTCV_MVP_STATUS 0x1526
+#define mmCRTCV1_CRTCV_MVP_STATUS_BASE_IDX 2
+#define mmCRTCV1_CRTCV_MASTER_EN 0x1527
+#define mmCRTCV1_CRTCV_MASTER_EN_BASE_IDX 2
+#define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT 0x1528
+#define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
+#define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS 0x1529
+#define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS_BASE_IDX 2
+#define mmCRTCV1_CRTCV_OVERSCAN_COLOR 0x152b
+#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_BASE_IDX 2
+#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT 0x152c
+#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT_BASE_IDX 2
+#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR 0x152d
+#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_BASE_IDX 2
+#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT 0x152e
+#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+#define mmCRTCV1_CRTCV_BLACK_COLOR 0x152f
+#define mmCRTCV1_CRTCV_BLACK_COLOR_BASE_IDX 2
+#define mmCRTCV1_CRTCV_BLACK_COLOR_EXT 0x1530
+#define mmCRTCV1_CRTCV_BLACK_COLOR_EXT_BASE_IDX 2
+#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION 0x1531
+#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL 0x1532
+#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION 0x1533
+#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL 0x1534
+#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION 0x1535
+#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL 0x1536
+#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_CRC_CNTL 0x1537
+#define mmCRTCV1_CRTCV_CRC_CNTL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL 0x1538
+#define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL 0x1539
+#define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL 0x153a
+#define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL 0x153b
+#define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_CRC0_DATA_RG 0x153c
+#define mmCRTCV1_CRTCV_CRC0_DATA_RG_BASE_IDX 2
+#define mmCRTCV1_CRTCV_CRC0_DATA_B 0x153d
+#define mmCRTCV1_CRTCV_CRC0_DATA_B_BASE_IDX 2
+#define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL 0x153e
+#define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL 0x153f
+#define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL 0x1540
+#define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL 0x1541
+#define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_CRC1_DATA_RG 0x1542
+#define mmCRTCV1_CRTCV_CRC1_DATA_RG_BASE_IDX 2
+#define mmCRTCV1_CRTCV_CRC1_DATA_B 0x1543
+#define mmCRTCV1_CRTCV_CRC1_DATA_B_BASE_IDX 2
+#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL 0x1544
+#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START 0x1545
+#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
+#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END 0x1546
+#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
+#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1547
+#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1548
+#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1549
+#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL 0x154a
+#define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL 0x154b
+#define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL_BASE_IDX 2
+#define mmCRTCV1_CRTCV_GSL_VSYNC_GAP 0x154c
+#define mmCRTCV1_CRTCV_GSL_VSYNC_GAP_BASE_IDX 2
+#define mmCRTCV1_CRTCV_GSL_WINDOW 0x154d
+#define mmCRTCV1_CRTCV_GSL_WINDOW_BASE_IDX 2
+#define mmCRTCV1_CRTCV_GSL_CONTROL 0x154e
+#define mmCRTCV1_CRTCV_GSL_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hpd0_dispdec
+// base address: 0x0
+#define mmHPD0_DC_HPD_INT_STATUS 0x1600
+#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2
+#define mmHPD0_DC_HPD_INT_CONTROL 0x1601
+#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2
+#define mmHPD0_DC_HPD_CONTROL 0x1602
+#define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2
+#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1603
+#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
+#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1604
+#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hpd1_dispdec
+// base address: 0x20
+#define mmHPD1_DC_HPD_INT_STATUS 0x1608
+#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2
+#define mmHPD1_DC_HPD_INT_CONTROL 0x1609
+#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2
+#define mmHPD1_DC_HPD_CONTROL 0x160a
+#define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2
+#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x160b
+#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
+#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x160c
+#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hpd2_dispdec
+// base address: 0x40
+#define mmHPD2_DC_HPD_INT_STATUS 0x1610
+#define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX 2
+#define mmHPD2_DC_HPD_INT_CONTROL 0x1611
+#define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2
+#define mmHPD2_DC_HPD_CONTROL 0x1612
+#define mmHPD2_DC_HPD_CONTROL_BASE_IDX 2
+#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1613
+#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
+#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1614
+#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hpd3_dispdec
+// base address: 0x60
+#define mmHPD3_DC_HPD_INT_STATUS 0x1618
+#define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX 2
+#define mmHPD3_DC_HPD_INT_CONTROL 0x1619
+#define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2
+#define mmHPD3_DC_HPD_CONTROL 0x161a
+#define mmHPD3_DC_HPD_CONTROL_BASE_IDX 2
+#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x161b
+#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
+#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x161c
+#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hpd4_dispdec
+// base address: 0x80
+#define mmHPD4_DC_HPD_INT_STATUS 0x1620
+#define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX 2
+#define mmHPD4_DC_HPD_INT_CONTROL 0x1621
+#define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2
+#define mmHPD4_DC_HPD_CONTROL 0x1622
+#define mmHPD4_DC_HPD_CONTROL_BASE_IDX 2
+#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1623
+#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
+#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1624
+#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hpd5_dispdec
+// base address: 0xa0
+#define mmHPD5_DC_HPD_INT_STATUS 0x1628
+#define mmHPD5_DC_HPD_INT_STATUS_BASE_IDX 2
+#define mmHPD5_DC_HPD_INT_CONTROL 0x1629
+#define mmHPD5_DC_HPD_INT_CONTROL_BASE_IDX 2
+#define mmHPD5_DC_HPD_CONTROL 0x162a
+#define mmHPD5_DC_HPD_CONTROL_BASE_IDX 2
+#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x162b
+#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
+#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x162c
+#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_perfmon2_dispdec
+// base address: 0x5840
+#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x1630
+#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x1631
+#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x1632
+#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON2_PERFMON_CNTL 0x1633
+#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON2_PERFMON_CNTL2 0x1634
+#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x1635
+#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x1636
+#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON2_PERFMON_HI 0x1637
+#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON2_PERFMON_LOW 0x1638
+#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dp_aux0_dispdec
+// base address: 0x0
+#define mmDP_AUX0_AUX_CONTROL 0x1766
+#define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2
+#define mmDP_AUX0_AUX_SW_CONTROL 0x1767
+#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2
+#define mmDP_AUX0_AUX_ARB_CONTROL 0x1768
+#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2
+#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1769
+#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDP_AUX0_AUX_SW_STATUS 0x176a
+#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2
+#define mmDP_AUX0_AUX_LS_STATUS 0x176b
+#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2
+#define mmDP_AUX0_AUX_SW_DATA 0x176c
+#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2
+#define mmDP_AUX0_AUX_LS_DATA 0x176d
+#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2
+#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x176e
+#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
+#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x176f
+#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1770
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1771
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
+#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1772
+#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2
+#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1773
+#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2
+#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1775
+#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1776
+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
+#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1777
+#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dp_aux1_dispdec
+// base address: 0x70
+#define mmDP_AUX1_AUX_CONTROL 0x1782
+#define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2
+#define mmDP_AUX1_AUX_SW_CONTROL 0x1783
+#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2
+#define mmDP_AUX1_AUX_ARB_CONTROL 0x1784
+#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2
+#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1785
+#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDP_AUX1_AUX_SW_STATUS 0x1786
+#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2
+#define mmDP_AUX1_AUX_LS_STATUS 0x1787
+#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2
+#define mmDP_AUX1_AUX_SW_DATA 0x1788
+#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2
+#define mmDP_AUX1_AUX_LS_DATA 0x1789
+#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2
+#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x178a
+#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
+#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x178b
+#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x178c
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x178d
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
+#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x178e
+#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2
+#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x178f
+#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2
+#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1791
+#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1792
+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
+#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1793
+#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dp_aux2_dispdec
+// base address: 0xe0
+#define mmDP_AUX2_AUX_CONTROL 0x179e
+#define mmDP_AUX2_AUX_CONTROL_BASE_IDX 2
+#define mmDP_AUX2_AUX_SW_CONTROL 0x179f
+#define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2
+#define mmDP_AUX2_AUX_ARB_CONTROL 0x17a0
+#define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2
+#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x17a1
+#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDP_AUX2_AUX_SW_STATUS 0x17a2
+#define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX 2
+#define mmDP_AUX2_AUX_LS_STATUS 0x17a3
+#define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX 2
+#define mmDP_AUX2_AUX_SW_DATA 0x17a4
+#define mmDP_AUX2_AUX_SW_DATA_BASE_IDX 2
+#define mmDP_AUX2_AUX_LS_DATA 0x17a5
+#define mmDP_AUX2_AUX_LS_DATA_BASE_IDX 2
+#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x17a6
+#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
+#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x17a7
+#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2
+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x17a8
+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x17a9
+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
+#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x17aa
+#define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2
+#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x17ab
+#define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2
+#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x17ad
+#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x17ae
+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
+#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x17af
+#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dp_aux3_dispdec
+// base address: 0x150
+#define mmDP_AUX3_AUX_CONTROL 0x17ba
+#define mmDP_AUX3_AUX_CONTROL_BASE_IDX 2
+#define mmDP_AUX3_AUX_SW_CONTROL 0x17bb
+#define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2
+#define mmDP_AUX3_AUX_ARB_CONTROL 0x17bc
+#define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2
+#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x17bd
+#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDP_AUX3_AUX_SW_STATUS 0x17be
+#define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX 2
+#define mmDP_AUX3_AUX_LS_STATUS 0x17bf
+#define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX 2
+#define mmDP_AUX3_AUX_SW_DATA 0x17c0
+#define mmDP_AUX3_AUX_SW_DATA_BASE_IDX 2
+#define mmDP_AUX3_AUX_LS_DATA 0x17c1
+#define mmDP_AUX3_AUX_LS_DATA_BASE_IDX 2
+#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x17c2
+#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
+#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x17c3
+#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2
+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x17c4
+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x17c5
+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
+#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x17c6
+#define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2
+#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x17c7
+#define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2
+#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x17c9
+#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x17ca
+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
+#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x17cb
+#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dp_aux4_dispdec
+// base address: 0x1c0
+#define mmDP_AUX4_AUX_CONTROL 0x17d6
+#define mmDP_AUX4_AUX_CONTROL_BASE_IDX 2
+#define mmDP_AUX4_AUX_SW_CONTROL 0x17d7
+#define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2
+#define mmDP_AUX4_AUX_ARB_CONTROL 0x17d8
+#define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2
+#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x17d9
+#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDP_AUX4_AUX_SW_STATUS 0x17da
+#define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX 2
+#define mmDP_AUX4_AUX_LS_STATUS 0x17db
+#define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX 2
+#define mmDP_AUX4_AUX_SW_DATA 0x17dc
+#define mmDP_AUX4_AUX_SW_DATA_BASE_IDX 2
+#define mmDP_AUX4_AUX_LS_DATA 0x17dd
+#define mmDP_AUX4_AUX_LS_DATA_BASE_IDX 2
+#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x17de
+#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
+#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x17df
+#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2
+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x17e0
+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x17e1
+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
+#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x17e2
+#define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2
+#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x17e3
+#define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2
+#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x17e5
+#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x17e6
+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
+#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x17e7
+#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dp_aux5_dispdec
+// base address: 0x230
+#define mmDP_AUX5_AUX_CONTROL 0x17f2
+#define mmDP_AUX5_AUX_CONTROL_BASE_IDX 2
+#define mmDP_AUX5_AUX_SW_CONTROL 0x17f3
+#define mmDP_AUX5_AUX_SW_CONTROL_BASE_IDX 2
+#define mmDP_AUX5_AUX_ARB_CONTROL 0x17f4
+#define mmDP_AUX5_AUX_ARB_CONTROL_BASE_IDX 2
+#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x17f5
+#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDP_AUX5_AUX_SW_STATUS 0x17f6
+#define mmDP_AUX5_AUX_SW_STATUS_BASE_IDX 2
+#define mmDP_AUX5_AUX_LS_STATUS 0x17f7
+#define mmDP_AUX5_AUX_LS_STATUS_BASE_IDX 2
+#define mmDP_AUX5_AUX_SW_DATA 0x17f8
+#define mmDP_AUX5_AUX_SW_DATA_BASE_IDX 2
+#define mmDP_AUX5_AUX_LS_DATA 0x17f9
+#define mmDP_AUX5_AUX_LS_DATA_BASE_IDX 2
+#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x17fa
+#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
+#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x17fb
+#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_BASE_IDX 2
+#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x17fc
+#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
+#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x17fd
+#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
+#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x17fe
+#define mmDP_AUX5_AUX_DPHY_TX_STATUS_BASE_IDX 2
+#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x17ff
+#define mmDP_AUX5_AUX_DPHY_RX_STATUS_BASE_IDX 2
+#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x1801
+#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
+#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1802
+#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
+#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x1803
+#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dig0_dispdec
+// base address: 0x0
+#define mmDIG0_DIG_FE_CNTL 0x187e
+#define mmDIG0_DIG_FE_CNTL_BASE_IDX 2
+#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x187f
+#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
+#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1880
+#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
+#define mmDIG0_DIG_CLOCK_PATTERN 0x1881
+#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2
+#define mmDIG0_DIG_TEST_PATTERN 0x1882
+#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2
+#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1883
+#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
+#define mmDIG0_DIG_FIFO_STATUS 0x1884
+#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2
+#define mmDIG0_HDMI_CONTROL 0x1887
+#define mmDIG0_HDMI_CONTROL_BASE_IDX 2
+#define mmDIG0_HDMI_STATUS 0x1888
+#define mmDIG0_HDMI_STATUS_BASE_IDX 2
+#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1889
+#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x188a
+#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x188b
+#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x188c
+#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x188d
+#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x188e
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
+#define mmDIG0_AFMT_INTERRUPT_STATUS 0x188f
+#define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDIG0_HDMI_GC 0x1891
+#define mmDIG0_HDMI_GC_BASE_IDX 2
+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1892
+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
+#define mmDIG0_AFMT_ISRC1_0 0x1893
+#define mmDIG0_AFMT_ISRC1_0_BASE_IDX 2
+#define mmDIG0_AFMT_ISRC1_1 0x1894
+#define mmDIG0_AFMT_ISRC1_1_BASE_IDX 2
+#define mmDIG0_AFMT_ISRC1_2 0x1895
+#define mmDIG0_AFMT_ISRC1_2_BASE_IDX 2
+#define mmDIG0_AFMT_ISRC1_3 0x1896
+#define mmDIG0_AFMT_ISRC1_3_BASE_IDX 2
+#define mmDIG0_AFMT_ISRC1_4 0x1897
+#define mmDIG0_AFMT_ISRC1_4_BASE_IDX 2
+#define mmDIG0_AFMT_ISRC2_0 0x1898
+#define mmDIG0_AFMT_ISRC2_0_BASE_IDX 2
+#define mmDIG0_AFMT_ISRC2_1 0x1899
+#define mmDIG0_AFMT_ISRC2_1_BASE_IDX 2
+#define mmDIG0_AFMT_ISRC2_2 0x189a
+#define mmDIG0_AFMT_ISRC2_2_BASE_IDX 2
+#define mmDIG0_AFMT_ISRC2_3 0x189b
+#define mmDIG0_AFMT_ISRC2_3_BASE_IDX 2
+#define mmDIG0_AFMT_AVI_INFO0 0x189c
+#define mmDIG0_AFMT_AVI_INFO0_BASE_IDX 2
+#define mmDIG0_AFMT_AVI_INFO1 0x189d
+#define mmDIG0_AFMT_AVI_INFO1_BASE_IDX 2
+#define mmDIG0_AFMT_AVI_INFO2 0x189e
+#define mmDIG0_AFMT_AVI_INFO2_BASE_IDX 2
+#define mmDIG0_AFMT_AVI_INFO3 0x189f
+#define mmDIG0_AFMT_AVI_INFO3_BASE_IDX 2
+#define mmDIG0_AFMT_MPEG_INFO0 0x18a0
+#define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX 2
+#define mmDIG0_AFMT_MPEG_INFO1 0x18a1
+#define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX 2
+#define mmDIG0_AFMT_GENERIC_HDR 0x18a2
+#define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX 2
+#define mmDIG0_AFMT_GENERIC_0 0x18a3
+#define mmDIG0_AFMT_GENERIC_0_BASE_IDX 2
+#define mmDIG0_AFMT_GENERIC_1 0x18a4
+#define mmDIG0_AFMT_GENERIC_1_BASE_IDX 2
+#define mmDIG0_AFMT_GENERIC_2 0x18a5
+#define mmDIG0_AFMT_GENERIC_2_BASE_IDX 2
+#define mmDIG0_AFMT_GENERIC_3 0x18a6
+#define mmDIG0_AFMT_GENERIC_3_BASE_IDX 2
+#define mmDIG0_AFMT_GENERIC_4 0x18a7
+#define mmDIG0_AFMT_GENERIC_4_BASE_IDX 2
+#define mmDIG0_AFMT_GENERIC_5 0x18a8
+#define mmDIG0_AFMT_GENERIC_5_BASE_IDX 2
+#define mmDIG0_AFMT_GENERIC_6 0x18a9
+#define mmDIG0_AFMT_GENERIC_6_BASE_IDX 2
+#define mmDIG0_AFMT_GENERIC_7 0x18aa
+#define mmDIG0_AFMT_GENERIC_7_BASE_IDX 2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x18ab
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
+#define mmDIG0_HDMI_ACR_32_0 0x18ac
+#define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2
+#define mmDIG0_HDMI_ACR_32_1 0x18ad
+#define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2
+#define mmDIG0_HDMI_ACR_44_0 0x18ae
+#define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2
+#define mmDIG0_HDMI_ACR_44_1 0x18af
+#define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2
+#define mmDIG0_HDMI_ACR_48_0 0x18b0
+#define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2
+#define mmDIG0_HDMI_ACR_48_1 0x18b1
+#define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2
+#define mmDIG0_HDMI_ACR_STATUS_0 0x18b2
+#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2
+#define mmDIG0_HDMI_ACR_STATUS_1 0x18b3
+#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2
+#define mmDIG0_AFMT_AUDIO_INFO0 0x18b4
+#define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX 2
+#define mmDIG0_AFMT_AUDIO_INFO1 0x18b5
+#define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX 2
+#define mmDIG0_AFMT_60958_0 0x18b6
+#define mmDIG0_AFMT_60958_0_BASE_IDX 2
+#define mmDIG0_AFMT_60958_1 0x18b7
+#define mmDIG0_AFMT_60958_1_BASE_IDX 2
+#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x18b8
+#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
+#define mmDIG0_AFMT_RAMP_CONTROL0 0x18b9
+#define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX 2
+#define mmDIG0_AFMT_RAMP_CONTROL1 0x18ba
+#define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX 2
+#define mmDIG0_AFMT_RAMP_CONTROL2 0x18bb
+#define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX 2
+#define mmDIG0_AFMT_RAMP_CONTROL3 0x18bc
+#define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX 2
+#define mmDIG0_AFMT_60958_2 0x18bd
+#define mmDIG0_AFMT_60958_2_BASE_IDX 2
+#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x18be
+#define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
+#define mmDIG0_AFMT_STATUS 0x18bf
+#define mmDIG0_AFMT_STATUS_BASE_IDX 2
+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x18c0
+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x18c1
+#define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x18c2
+#define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x18c3
+#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
+#define mmDIG0_DIG_BE_CNTL 0x18c5
+#define mmDIG0_DIG_BE_CNTL_BASE_IDX 2
+#define mmDIG0_DIG_BE_EN_CNTL 0x18c6
+#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2
+#define mmDIG0_TMDS_CNTL 0x18e9
+#define mmDIG0_TMDS_CNTL_BASE_IDX 2
+#define mmDIG0_TMDS_CONTROL_CHAR 0x18ea
+#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2
+#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x18eb
+#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
+#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x18ec
+#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x18ed
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x18ee
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
+#define mmDIG0_TMDS_CTL_BITS 0x18f0
+#define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2
+#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x18f1
+#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
+#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x18f3
+#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
+#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x18f4
+#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
+#define mmDIG0_DIG_VERSION 0x18f6
+#define mmDIG0_DIG_VERSION_BASE_IDX 2
+#define mmDIG0_DIG_LANE_ENABLE 0x18f7
+#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2
+#define mmDIG0_AFMT_CNTL 0x18fc
+#define mmDIG0_AFMT_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dp0_dispdec
+// base address: 0x0
+#define mmDP0_DP_LINK_CNTL 0x191e
+#define mmDP0_DP_LINK_CNTL_BASE_IDX 2
+#define mmDP0_DP_PIXEL_FORMAT 0x191f
+#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2
+#define mmDP0_DP_MSA_COLORIMETRY 0x1920
+#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2
+#define mmDP0_DP_CONFIG 0x1921
+#define mmDP0_DP_CONFIG_BASE_IDX 2
+#define mmDP0_DP_VID_STREAM_CNTL 0x1922
+#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2
+#define mmDP0_DP_STEER_FIFO 0x1923
+#define mmDP0_DP_STEER_FIFO_BASE_IDX 2
+#define mmDP0_DP_MSA_MISC 0x1924
+#define mmDP0_DP_MSA_MISC_BASE_IDX 2
+#define mmDP0_DP_VID_TIMING 0x1926
+#define mmDP0_DP_VID_TIMING_BASE_IDX 2
+#define mmDP0_DP_VID_N 0x1927
+#define mmDP0_DP_VID_N_BASE_IDX 2
+#define mmDP0_DP_VID_M 0x1928
+#define mmDP0_DP_VID_M_BASE_IDX 2
+#define mmDP0_DP_LINK_FRAMING_CNTL 0x1929
+#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2
+#define mmDP0_DP_HBR2_EYE_PATTERN 0x192a
+#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2
+#define mmDP0_DP_VID_MSA_VBID 0x192b
+#define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2
+#define mmDP0_DP_VID_INTERRUPT_CNTL 0x192c
+#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
+#define mmDP0_DP_DPHY_CNTL 0x192d
+#define mmDP0_DP_DPHY_CNTL_BASE_IDX 2
+#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x192e
+#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
+#define mmDP0_DP_DPHY_SYM0 0x192f
+#define mmDP0_DP_DPHY_SYM0_BASE_IDX 2
+#define mmDP0_DP_DPHY_SYM1 0x1930
+#define mmDP0_DP_DPHY_SYM1_BASE_IDX 2
+#define mmDP0_DP_DPHY_SYM2 0x1931
+#define mmDP0_DP_DPHY_SYM2_BASE_IDX 2
+#define mmDP0_DP_DPHY_8B10B_CNTL 0x1932
+#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2
+#define mmDP0_DP_DPHY_PRBS_CNTL 0x1933
+#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2
+#define mmDP0_DP_DPHY_SCRAM_CNTL 0x1934
+#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
+#define mmDP0_DP_DPHY_CRC_EN 0x1935
+#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2
+#define mmDP0_DP_DPHY_CRC_CNTL 0x1936
+#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2
+#define mmDP0_DP_DPHY_CRC_RESULT 0x1937
+#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2
+#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x1938
+#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
+#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x1939
+#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
+#define mmDP0_DP_DPHY_FAST_TRAINING 0x193a
+#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2
+#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x193b
+#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
+#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x193c
+#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
+#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x193d
+#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
+#define mmDP0_DP_SEC_CNTL 0x1941
+#define mmDP0_DP_SEC_CNTL_BASE_IDX 2
+#define mmDP0_DP_SEC_CNTL1 0x1942
+#define mmDP0_DP_SEC_CNTL1_BASE_IDX 2
+#define mmDP0_DP_SEC_FRAMING1 0x1943
+#define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2
+#define mmDP0_DP_SEC_FRAMING2 0x1944
+#define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2
+#define mmDP0_DP_SEC_FRAMING3 0x1945
+#define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2
+#define mmDP0_DP_SEC_FRAMING4 0x1946
+#define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2
+#define mmDP0_DP_SEC_AUD_N 0x1947
+#define mmDP0_DP_SEC_AUD_N_BASE_IDX 2
+#define mmDP0_DP_SEC_AUD_N_READBACK 0x1948
+#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2
+#define mmDP0_DP_SEC_AUD_M 0x1949
+#define mmDP0_DP_SEC_AUD_M_BASE_IDX 2
+#define mmDP0_DP_SEC_AUD_M_READBACK 0x194a
+#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2
+#define mmDP0_DP_SEC_TIMESTAMP 0x194b
+#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2
+#define mmDP0_DP_SEC_PACKET_CNTL 0x194c
+#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2
+#define mmDP0_DP_MSE_RATE_CNTL 0x194d
+#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2
+#define mmDP0_DP_MSE_RATE_UPDATE 0x194f
+#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2
+#define mmDP0_DP_MSE_SAT0 0x1950
+#define mmDP0_DP_MSE_SAT0_BASE_IDX 2
+#define mmDP0_DP_MSE_SAT1 0x1951
+#define mmDP0_DP_MSE_SAT1_BASE_IDX 2
+#define mmDP0_DP_MSE_SAT2 0x1952
+#define mmDP0_DP_MSE_SAT2_BASE_IDX 2
+#define mmDP0_DP_MSE_SAT_UPDATE 0x1953
+#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2
+#define mmDP0_DP_MSE_LINK_TIMING 0x1954
+#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2
+#define mmDP0_DP_MSE_MISC_CNTL 0x1955
+#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2
+#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x195a
+#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
+#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x195b
+#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
+#define mmDP0_DP_MSE_SAT0_STATUS 0x195d
+#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2
+#define mmDP0_DP_MSE_SAT1_STATUS 0x195e
+#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2
+#define mmDP0_DP_MSE_SAT2_STATUS 0x195f
+#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dig1_dispdec
+// base address: 0x400
+#define mmDIG1_DIG_FE_CNTL 0x197e
+#define mmDIG1_DIG_FE_CNTL_BASE_IDX 2
+#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x197f
+#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
+#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1980
+#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
+#define mmDIG1_DIG_CLOCK_PATTERN 0x1981
+#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2
+#define mmDIG1_DIG_TEST_PATTERN 0x1982
+#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2
+#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1983
+#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
+#define mmDIG1_DIG_FIFO_STATUS 0x1984
+#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2
+#define mmDIG1_HDMI_CONTROL 0x1987
+#define mmDIG1_HDMI_CONTROL_BASE_IDX 2
+#define mmDIG1_HDMI_STATUS 0x1988
+#define mmDIG1_HDMI_STATUS_BASE_IDX 2
+#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1989
+#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x198a
+#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x198b
+#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x198c
+#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x198d
+#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x198e
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
+#define mmDIG1_AFMT_INTERRUPT_STATUS 0x198f
+#define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDIG1_HDMI_GC 0x1991
+#define mmDIG1_HDMI_GC_BASE_IDX 2
+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1992
+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
+#define mmDIG1_AFMT_ISRC1_0 0x1993
+#define mmDIG1_AFMT_ISRC1_0_BASE_IDX 2
+#define mmDIG1_AFMT_ISRC1_1 0x1994
+#define mmDIG1_AFMT_ISRC1_1_BASE_IDX 2
+#define mmDIG1_AFMT_ISRC1_2 0x1995
+#define mmDIG1_AFMT_ISRC1_2_BASE_IDX 2
+#define mmDIG1_AFMT_ISRC1_3 0x1996
+#define mmDIG1_AFMT_ISRC1_3_BASE_IDX 2
+#define mmDIG1_AFMT_ISRC1_4 0x1997
+#define mmDIG1_AFMT_ISRC1_4_BASE_IDX 2
+#define mmDIG1_AFMT_ISRC2_0 0x1998
+#define mmDIG1_AFMT_ISRC2_0_BASE_IDX 2
+#define mmDIG1_AFMT_ISRC2_1 0x1999
+#define mmDIG1_AFMT_ISRC2_1_BASE_IDX 2
+#define mmDIG1_AFMT_ISRC2_2 0x199a
+#define mmDIG1_AFMT_ISRC2_2_BASE_IDX 2
+#define mmDIG1_AFMT_ISRC2_3 0x199b
+#define mmDIG1_AFMT_ISRC2_3_BASE_IDX 2
+#define mmDIG1_AFMT_AVI_INFO0 0x199c
+#define mmDIG1_AFMT_AVI_INFO0_BASE_IDX 2
+#define mmDIG1_AFMT_AVI_INFO1 0x199d
+#define mmDIG1_AFMT_AVI_INFO1_BASE_IDX 2
+#define mmDIG1_AFMT_AVI_INFO2 0x199e
+#define mmDIG1_AFMT_AVI_INFO2_BASE_IDX 2
+#define mmDIG1_AFMT_AVI_INFO3 0x199f
+#define mmDIG1_AFMT_AVI_INFO3_BASE_IDX 2
+#define mmDIG1_AFMT_MPEG_INFO0 0x19a0
+#define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX 2
+#define mmDIG1_AFMT_MPEG_INFO1 0x19a1
+#define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX 2
+#define mmDIG1_AFMT_GENERIC_HDR 0x19a2
+#define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX 2
+#define mmDIG1_AFMT_GENERIC_0 0x19a3
+#define mmDIG1_AFMT_GENERIC_0_BASE_IDX 2
+#define mmDIG1_AFMT_GENERIC_1 0x19a4
+#define mmDIG1_AFMT_GENERIC_1_BASE_IDX 2
+#define mmDIG1_AFMT_GENERIC_2 0x19a5
+#define mmDIG1_AFMT_GENERIC_2_BASE_IDX 2
+#define mmDIG1_AFMT_GENERIC_3 0x19a6
+#define mmDIG1_AFMT_GENERIC_3_BASE_IDX 2
+#define mmDIG1_AFMT_GENERIC_4 0x19a7
+#define mmDIG1_AFMT_GENERIC_4_BASE_IDX 2
+#define mmDIG1_AFMT_GENERIC_5 0x19a8
+#define mmDIG1_AFMT_GENERIC_5_BASE_IDX 2
+#define mmDIG1_AFMT_GENERIC_6 0x19a9
+#define mmDIG1_AFMT_GENERIC_6_BASE_IDX 2
+#define mmDIG1_AFMT_GENERIC_7 0x19aa
+#define mmDIG1_AFMT_GENERIC_7_BASE_IDX 2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x19ab
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
+#define mmDIG1_HDMI_ACR_32_0 0x19ac
+#define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2
+#define mmDIG1_HDMI_ACR_32_1 0x19ad
+#define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2
+#define mmDIG1_HDMI_ACR_44_0 0x19ae
+#define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2
+#define mmDIG1_HDMI_ACR_44_1 0x19af
+#define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2
+#define mmDIG1_HDMI_ACR_48_0 0x19b0
+#define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2
+#define mmDIG1_HDMI_ACR_48_1 0x19b1
+#define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2
+#define mmDIG1_HDMI_ACR_STATUS_0 0x19b2
+#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2
+#define mmDIG1_HDMI_ACR_STATUS_1 0x19b3
+#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2
+#define mmDIG1_AFMT_AUDIO_INFO0 0x19b4
+#define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX 2
+#define mmDIG1_AFMT_AUDIO_INFO1 0x19b5
+#define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX 2
+#define mmDIG1_AFMT_60958_0 0x19b6
+#define mmDIG1_AFMT_60958_0_BASE_IDX 2
+#define mmDIG1_AFMT_60958_1 0x19b7
+#define mmDIG1_AFMT_60958_1_BASE_IDX 2
+#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x19b8
+#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
+#define mmDIG1_AFMT_RAMP_CONTROL0 0x19b9
+#define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX 2
+#define mmDIG1_AFMT_RAMP_CONTROL1 0x19ba
+#define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX 2
+#define mmDIG1_AFMT_RAMP_CONTROL2 0x19bb
+#define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX 2
+#define mmDIG1_AFMT_RAMP_CONTROL3 0x19bc
+#define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX 2
+#define mmDIG1_AFMT_60958_2 0x19bd
+#define mmDIG1_AFMT_60958_2_BASE_IDX 2
+#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x19be
+#define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
+#define mmDIG1_AFMT_STATUS 0x19bf
+#define mmDIG1_AFMT_STATUS_BASE_IDX 2
+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x19c0
+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x19c1
+#define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x19c2
+#define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x19c3
+#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
+#define mmDIG1_DIG_BE_CNTL 0x19c5
+#define mmDIG1_DIG_BE_CNTL_BASE_IDX 2
+#define mmDIG1_DIG_BE_EN_CNTL 0x19c6
+#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2
+#define mmDIG1_TMDS_CNTL 0x19e9
+#define mmDIG1_TMDS_CNTL_BASE_IDX 2
+#define mmDIG1_TMDS_CONTROL_CHAR 0x19ea
+#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2
+#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x19eb
+#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
+#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x19ec
+#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x19ed
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x19ee
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
+#define mmDIG1_TMDS_CTL_BITS 0x19f0
+#define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2
+#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x19f1
+#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
+#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x19f3
+#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
+#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x19f4
+#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
+#define mmDIG1_DIG_VERSION 0x19f6
+#define mmDIG1_DIG_VERSION_BASE_IDX 2
+#define mmDIG1_DIG_LANE_ENABLE 0x19f7
+#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2
+#define mmDIG1_AFMT_CNTL 0x19fc
+#define mmDIG1_AFMT_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dp1_dispdec
+// base address: 0x400
+#define mmDP1_DP_LINK_CNTL 0x1a1e
+#define mmDP1_DP_LINK_CNTL_BASE_IDX 2
+#define mmDP1_DP_PIXEL_FORMAT 0x1a1f
+#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2
+#define mmDP1_DP_MSA_COLORIMETRY 0x1a20
+#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2
+#define mmDP1_DP_CONFIG 0x1a21
+#define mmDP1_DP_CONFIG_BASE_IDX 2
+#define mmDP1_DP_VID_STREAM_CNTL 0x1a22
+#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2
+#define mmDP1_DP_STEER_FIFO 0x1a23
+#define mmDP1_DP_STEER_FIFO_BASE_IDX 2
+#define mmDP1_DP_MSA_MISC 0x1a24
+#define mmDP1_DP_MSA_MISC_BASE_IDX 2
+#define mmDP1_DP_VID_TIMING 0x1a26
+#define mmDP1_DP_VID_TIMING_BASE_IDX 2
+#define mmDP1_DP_VID_N 0x1a27
+#define mmDP1_DP_VID_N_BASE_IDX 2
+#define mmDP1_DP_VID_M 0x1a28
+#define mmDP1_DP_VID_M_BASE_IDX 2
+#define mmDP1_DP_LINK_FRAMING_CNTL 0x1a29
+#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2
+#define mmDP1_DP_HBR2_EYE_PATTERN 0x1a2a
+#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2
+#define mmDP1_DP_VID_MSA_VBID 0x1a2b
+#define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2
+#define mmDP1_DP_VID_INTERRUPT_CNTL 0x1a2c
+#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
+#define mmDP1_DP_DPHY_CNTL 0x1a2d
+#define mmDP1_DP_DPHY_CNTL_BASE_IDX 2
+#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1a2e
+#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
+#define mmDP1_DP_DPHY_SYM0 0x1a2f
+#define mmDP1_DP_DPHY_SYM0_BASE_IDX 2
+#define mmDP1_DP_DPHY_SYM1 0x1a30
+#define mmDP1_DP_DPHY_SYM1_BASE_IDX 2
+#define mmDP1_DP_DPHY_SYM2 0x1a31
+#define mmDP1_DP_DPHY_SYM2_BASE_IDX 2
+#define mmDP1_DP_DPHY_8B10B_CNTL 0x1a32
+#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2
+#define mmDP1_DP_DPHY_PRBS_CNTL 0x1a33
+#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2
+#define mmDP1_DP_DPHY_SCRAM_CNTL 0x1a34
+#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
+#define mmDP1_DP_DPHY_CRC_EN 0x1a35
+#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2
+#define mmDP1_DP_DPHY_CRC_CNTL 0x1a36
+#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2
+#define mmDP1_DP_DPHY_CRC_RESULT 0x1a37
+#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2
+#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x1a38
+#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
+#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x1a39
+#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
+#define mmDP1_DP_DPHY_FAST_TRAINING 0x1a3a
+#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2
+#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1a3b
+#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
+#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1a3c
+#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
+#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1a3d
+#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
+#define mmDP1_DP_SEC_CNTL 0x1a41
+#define mmDP1_DP_SEC_CNTL_BASE_IDX 2
+#define mmDP1_DP_SEC_CNTL1 0x1a42
+#define mmDP1_DP_SEC_CNTL1_BASE_IDX 2
+#define mmDP1_DP_SEC_FRAMING1 0x1a43
+#define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2
+#define mmDP1_DP_SEC_FRAMING2 0x1a44
+#define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2
+#define mmDP1_DP_SEC_FRAMING3 0x1a45
+#define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2
+#define mmDP1_DP_SEC_FRAMING4 0x1a46
+#define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2
+#define mmDP1_DP_SEC_AUD_N 0x1a47
+#define mmDP1_DP_SEC_AUD_N_BASE_IDX 2
+#define mmDP1_DP_SEC_AUD_N_READBACK 0x1a48
+#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2
+#define mmDP1_DP_SEC_AUD_M 0x1a49
+#define mmDP1_DP_SEC_AUD_M_BASE_IDX 2
+#define mmDP1_DP_SEC_AUD_M_READBACK 0x1a4a
+#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2
+#define mmDP1_DP_SEC_TIMESTAMP 0x1a4b
+#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2
+#define mmDP1_DP_SEC_PACKET_CNTL 0x1a4c
+#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2
+#define mmDP1_DP_MSE_RATE_CNTL 0x1a4d
+#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2
+#define mmDP1_DP_MSE_RATE_UPDATE 0x1a4f
+#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2
+#define mmDP1_DP_MSE_SAT0 0x1a50
+#define mmDP1_DP_MSE_SAT0_BASE_IDX 2
+#define mmDP1_DP_MSE_SAT1 0x1a51
+#define mmDP1_DP_MSE_SAT1_BASE_IDX 2
+#define mmDP1_DP_MSE_SAT2 0x1a52
+#define mmDP1_DP_MSE_SAT2_BASE_IDX 2
+#define mmDP1_DP_MSE_SAT_UPDATE 0x1a53
+#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2
+#define mmDP1_DP_MSE_LINK_TIMING 0x1a54
+#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2
+#define mmDP1_DP_MSE_MISC_CNTL 0x1a55
+#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2
+#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x1a5a
+#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
+#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x1a5b
+#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
+#define mmDP1_DP_MSE_SAT0_STATUS 0x1a5d
+#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2
+#define mmDP1_DP_MSE_SAT1_STATUS 0x1a5e
+#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2
+#define mmDP1_DP_MSE_SAT2_STATUS 0x1a5f
+#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dig2_dispdec
+// base address: 0x800
+#define mmDIG2_DIG_FE_CNTL 0x1a7e
+#define mmDIG2_DIG_FE_CNTL_BASE_IDX 2
+#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x1a7f
+#define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
+#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x1a80
+#define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
+#define mmDIG2_DIG_CLOCK_PATTERN 0x1a81
+#define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2
+#define mmDIG2_DIG_TEST_PATTERN 0x1a82
+#define mmDIG2_DIG_TEST_PATTERN_BASE_IDX 2
+#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x1a83
+#define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
+#define mmDIG2_DIG_FIFO_STATUS 0x1a84
+#define mmDIG2_DIG_FIFO_STATUS_BASE_IDX 2
+#define mmDIG2_HDMI_CONTROL 0x1a87
+#define mmDIG2_HDMI_CONTROL_BASE_IDX 2
+#define mmDIG2_HDMI_STATUS 0x1a88
+#define mmDIG2_HDMI_STATUS_BASE_IDX 2
+#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x1a89
+#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x1a8a
+#define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x1a8b
+#define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x1a8c
+#define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x1a8d
+#define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x1a8e
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
+#define mmDIG2_AFMT_INTERRUPT_STATUS 0x1a8f
+#define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDIG2_HDMI_GC 0x1a91
+#define mmDIG2_HDMI_GC_BASE_IDX 2
+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x1a92
+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
+#define mmDIG2_AFMT_ISRC1_0 0x1a93
+#define mmDIG2_AFMT_ISRC1_0_BASE_IDX 2
+#define mmDIG2_AFMT_ISRC1_1 0x1a94
+#define mmDIG2_AFMT_ISRC1_1_BASE_IDX 2
+#define mmDIG2_AFMT_ISRC1_2 0x1a95
+#define mmDIG2_AFMT_ISRC1_2_BASE_IDX 2
+#define mmDIG2_AFMT_ISRC1_3 0x1a96
+#define mmDIG2_AFMT_ISRC1_3_BASE_IDX 2
+#define mmDIG2_AFMT_ISRC1_4 0x1a97
+#define mmDIG2_AFMT_ISRC1_4_BASE_IDX 2
+#define mmDIG2_AFMT_ISRC2_0 0x1a98
+#define mmDIG2_AFMT_ISRC2_0_BASE_IDX 2
+#define mmDIG2_AFMT_ISRC2_1 0x1a99
+#define mmDIG2_AFMT_ISRC2_1_BASE_IDX 2
+#define mmDIG2_AFMT_ISRC2_2 0x1a9a
+#define mmDIG2_AFMT_ISRC2_2_BASE_IDX 2
+#define mmDIG2_AFMT_ISRC2_3 0x1a9b
+#define mmDIG2_AFMT_ISRC2_3_BASE_IDX 2
+#define mmDIG2_AFMT_AVI_INFO0 0x1a9c
+#define mmDIG2_AFMT_AVI_INFO0_BASE_IDX 2
+#define mmDIG2_AFMT_AVI_INFO1 0x1a9d
+#define mmDIG2_AFMT_AVI_INFO1_BASE_IDX 2
+#define mmDIG2_AFMT_AVI_INFO2 0x1a9e
+#define mmDIG2_AFMT_AVI_INFO2_BASE_IDX 2
+#define mmDIG2_AFMT_AVI_INFO3 0x1a9f
+#define mmDIG2_AFMT_AVI_INFO3_BASE_IDX 2
+#define mmDIG2_AFMT_MPEG_INFO0 0x1aa0
+#define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX 2
+#define mmDIG2_AFMT_MPEG_INFO1 0x1aa1
+#define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX 2
+#define mmDIG2_AFMT_GENERIC_HDR 0x1aa2
+#define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX 2
+#define mmDIG2_AFMT_GENERIC_0 0x1aa3
+#define mmDIG2_AFMT_GENERIC_0_BASE_IDX 2
+#define mmDIG2_AFMT_GENERIC_1 0x1aa4
+#define mmDIG2_AFMT_GENERIC_1_BASE_IDX 2
+#define mmDIG2_AFMT_GENERIC_2 0x1aa5
+#define mmDIG2_AFMT_GENERIC_2_BASE_IDX 2
+#define mmDIG2_AFMT_GENERIC_3 0x1aa6
+#define mmDIG2_AFMT_GENERIC_3_BASE_IDX 2
+#define mmDIG2_AFMT_GENERIC_4 0x1aa7
+#define mmDIG2_AFMT_GENERIC_4_BASE_IDX 2
+#define mmDIG2_AFMT_GENERIC_5 0x1aa8
+#define mmDIG2_AFMT_GENERIC_5_BASE_IDX 2
+#define mmDIG2_AFMT_GENERIC_6 0x1aa9
+#define mmDIG2_AFMT_GENERIC_6_BASE_IDX 2
+#define mmDIG2_AFMT_GENERIC_7 0x1aaa
+#define mmDIG2_AFMT_GENERIC_7_BASE_IDX 2
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x1aab
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
+#define mmDIG2_HDMI_ACR_32_0 0x1aac
+#define mmDIG2_HDMI_ACR_32_0_BASE_IDX 2
+#define mmDIG2_HDMI_ACR_32_1 0x1aad
+#define mmDIG2_HDMI_ACR_32_1_BASE_IDX 2
+#define mmDIG2_HDMI_ACR_44_0 0x1aae
+#define mmDIG2_HDMI_ACR_44_0_BASE_IDX 2
+#define mmDIG2_HDMI_ACR_44_1 0x1aaf
+#define mmDIG2_HDMI_ACR_44_1_BASE_IDX 2
+#define mmDIG2_HDMI_ACR_48_0 0x1ab0
+#define mmDIG2_HDMI_ACR_48_0_BASE_IDX 2
+#define mmDIG2_HDMI_ACR_48_1 0x1ab1
+#define mmDIG2_HDMI_ACR_48_1_BASE_IDX 2
+#define mmDIG2_HDMI_ACR_STATUS_0 0x1ab2
+#define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2
+#define mmDIG2_HDMI_ACR_STATUS_1 0x1ab3
+#define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2
+#define mmDIG2_AFMT_AUDIO_INFO0 0x1ab4
+#define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX 2
+#define mmDIG2_AFMT_AUDIO_INFO1 0x1ab5
+#define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX 2
+#define mmDIG2_AFMT_60958_0 0x1ab6
+#define mmDIG2_AFMT_60958_0_BASE_IDX 2
+#define mmDIG2_AFMT_60958_1 0x1ab7
+#define mmDIG2_AFMT_60958_1_BASE_IDX 2
+#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x1ab8
+#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
+#define mmDIG2_AFMT_RAMP_CONTROL0 0x1ab9
+#define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX 2
+#define mmDIG2_AFMT_RAMP_CONTROL1 0x1aba
+#define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX 2
+#define mmDIG2_AFMT_RAMP_CONTROL2 0x1abb
+#define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX 2
+#define mmDIG2_AFMT_RAMP_CONTROL3 0x1abc
+#define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX 2
+#define mmDIG2_AFMT_60958_2 0x1abd
+#define mmDIG2_AFMT_60958_2_BASE_IDX 2
+#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x1abe
+#define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
+#define mmDIG2_AFMT_STATUS 0x1abf
+#define mmDIG2_AFMT_STATUS_BASE_IDX 2
+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x1ac0
+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x1ac1
+#define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x1ac2
+#define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x1ac3
+#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
+#define mmDIG2_DIG_BE_CNTL 0x1ac5
+#define mmDIG2_DIG_BE_CNTL_BASE_IDX 2
+#define mmDIG2_DIG_BE_EN_CNTL 0x1ac6
+#define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX 2
+#define mmDIG2_TMDS_CNTL 0x1ae9
+#define mmDIG2_TMDS_CNTL_BASE_IDX 2
+#define mmDIG2_TMDS_CONTROL_CHAR 0x1aea
+#define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2
+#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x1aeb
+#define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
+#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x1aec
+#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x1aed
+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x1aee
+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
+#define mmDIG2_TMDS_CTL_BITS 0x1af0
+#define mmDIG2_TMDS_CTL_BITS_BASE_IDX 2
+#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x1af1
+#define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
+#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x1af3
+#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
+#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x1af4
+#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
+#define mmDIG2_DIG_VERSION 0x1af6
+#define mmDIG2_DIG_VERSION_BASE_IDX 2
+#define mmDIG2_DIG_LANE_ENABLE 0x1af7
+#define mmDIG2_DIG_LANE_ENABLE_BASE_IDX 2
+#define mmDIG2_AFMT_CNTL 0x1afc
+#define mmDIG2_AFMT_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dp2_dispdec
+// base address: 0x800
+#define mmDP2_DP_LINK_CNTL 0x1b1e
+#define mmDP2_DP_LINK_CNTL_BASE_IDX 2
+#define mmDP2_DP_PIXEL_FORMAT 0x1b1f
+#define mmDP2_DP_PIXEL_FORMAT_BASE_IDX 2
+#define mmDP2_DP_MSA_COLORIMETRY 0x1b20
+#define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX 2
+#define mmDP2_DP_CONFIG 0x1b21
+#define mmDP2_DP_CONFIG_BASE_IDX 2
+#define mmDP2_DP_VID_STREAM_CNTL 0x1b22
+#define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX 2
+#define mmDP2_DP_STEER_FIFO 0x1b23
+#define mmDP2_DP_STEER_FIFO_BASE_IDX 2
+#define mmDP2_DP_MSA_MISC 0x1b24
+#define mmDP2_DP_MSA_MISC_BASE_IDX 2
+#define mmDP2_DP_VID_TIMING 0x1b26
+#define mmDP2_DP_VID_TIMING_BASE_IDX 2
+#define mmDP2_DP_VID_N 0x1b27
+#define mmDP2_DP_VID_N_BASE_IDX 2
+#define mmDP2_DP_VID_M 0x1b28
+#define mmDP2_DP_VID_M_BASE_IDX 2
+#define mmDP2_DP_LINK_FRAMING_CNTL 0x1b29
+#define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2
+#define mmDP2_DP_HBR2_EYE_PATTERN 0x1b2a
+#define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2
+#define mmDP2_DP_VID_MSA_VBID 0x1b2b
+#define mmDP2_DP_VID_MSA_VBID_BASE_IDX 2
+#define mmDP2_DP_VID_INTERRUPT_CNTL 0x1b2c
+#define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
+#define mmDP2_DP_DPHY_CNTL 0x1b2d
+#define mmDP2_DP_DPHY_CNTL_BASE_IDX 2
+#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x1b2e
+#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
+#define mmDP2_DP_DPHY_SYM0 0x1b2f
+#define mmDP2_DP_DPHY_SYM0_BASE_IDX 2
+#define mmDP2_DP_DPHY_SYM1 0x1b30
+#define mmDP2_DP_DPHY_SYM1_BASE_IDX 2
+#define mmDP2_DP_DPHY_SYM2 0x1b31
+#define mmDP2_DP_DPHY_SYM2_BASE_IDX 2
+#define mmDP2_DP_DPHY_8B10B_CNTL 0x1b32
+#define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2
+#define mmDP2_DP_DPHY_PRBS_CNTL 0x1b33
+#define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2
+#define mmDP2_DP_DPHY_SCRAM_CNTL 0x1b34
+#define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
+#define mmDP2_DP_DPHY_CRC_EN 0x1b35
+#define mmDP2_DP_DPHY_CRC_EN_BASE_IDX 2
+#define mmDP2_DP_DPHY_CRC_CNTL 0x1b36
+#define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2
+#define mmDP2_DP_DPHY_CRC_RESULT 0x1b37
+#define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2
+#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x1b38
+#define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
+#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x1b39
+#define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
+#define mmDP2_DP_DPHY_FAST_TRAINING 0x1b3a
+#define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2
+#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x1b3b
+#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
+#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x1b3c
+#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
+#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x1b3d
+#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
+#define mmDP2_DP_SEC_CNTL 0x1b41
+#define mmDP2_DP_SEC_CNTL_BASE_IDX 2
+#define mmDP2_DP_SEC_CNTL1 0x1b42
+#define mmDP2_DP_SEC_CNTL1_BASE_IDX 2
+#define mmDP2_DP_SEC_FRAMING1 0x1b43
+#define mmDP2_DP_SEC_FRAMING1_BASE_IDX 2
+#define mmDP2_DP_SEC_FRAMING2 0x1b44
+#define mmDP2_DP_SEC_FRAMING2_BASE_IDX 2
+#define mmDP2_DP_SEC_FRAMING3 0x1b45
+#define mmDP2_DP_SEC_FRAMING3_BASE_IDX 2
+#define mmDP2_DP_SEC_FRAMING4 0x1b46
+#define mmDP2_DP_SEC_FRAMING4_BASE_IDX 2
+#define mmDP2_DP_SEC_AUD_N 0x1b47
+#define mmDP2_DP_SEC_AUD_N_BASE_IDX 2
+#define mmDP2_DP_SEC_AUD_N_READBACK 0x1b48
+#define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2
+#define mmDP2_DP_SEC_AUD_M 0x1b49
+#define mmDP2_DP_SEC_AUD_M_BASE_IDX 2
+#define mmDP2_DP_SEC_AUD_M_READBACK 0x1b4a
+#define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2
+#define mmDP2_DP_SEC_TIMESTAMP 0x1b4b
+#define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX 2
+#define mmDP2_DP_SEC_PACKET_CNTL 0x1b4c
+#define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2
+#define mmDP2_DP_MSE_RATE_CNTL 0x1b4d
+#define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX 2
+#define mmDP2_DP_MSE_RATE_UPDATE 0x1b4f
+#define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2
+#define mmDP2_DP_MSE_SAT0 0x1b50
+#define mmDP2_DP_MSE_SAT0_BASE_IDX 2
+#define mmDP2_DP_MSE_SAT1 0x1b51
+#define mmDP2_DP_MSE_SAT1_BASE_IDX 2
+#define mmDP2_DP_MSE_SAT2 0x1b52
+#define mmDP2_DP_MSE_SAT2_BASE_IDX 2
+#define mmDP2_DP_MSE_SAT_UPDATE 0x1b53
+#define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2
+#define mmDP2_DP_MSE_LINK_TIMING 0x1b54
+#define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX 2
+#define mmDP2_DP_MSE_MISC_CNTL 0x1b55
+#define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX 2
+#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x1b5a
+#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
+#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x1b5b
+#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
+#define mmDP2_DP_MSE_SAT0_STATUS 0x1b5d
+#define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2
+#define mmDP2_DP_MSE_SAT1_STATUS 0x1b5e
+#define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2
+#define mmDP2_DP_MSE_SAT2_STATUS 0x1b5f
+#define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dig3_dispdec
+// base address: 0xc00
+#define mmDIG3_DIG_FE_CNTL 0x1b7e
+#define mmDIG3_DIG_FE_CNTL_BASE_IDX 2
+#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x1b7f
+#define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
+#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x1b80
+#define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
+#define mmDIG3_DIG_CLOCK_PATTERN 0x1b81
+#define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2
+#define mmDIG3_DIG_TEST_PATTERN 0x1b82
+#define mmDIG3_DIG_TEST_PATTERN_BASE_IDX 2
+#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x1b83
+#define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
+#define mmDIG3_DIG_FIFO_STATUS 0x1b84
+#define mmDIG3_DIG_FIFO_STATUS_BASE_IDX 2
+#define mmDIG3_HDMI_CONTROL 0x1b87
+#define mmDIG3_HDMI_CONTROL_BASE_IDX 2
+#define mmDIG3_HDMI_STATUS 0x1b88
+#define mmDIG3_HDMI_STATUS_BASE_IDX 2
+#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x1b89
+#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x1b8a
+#define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x1b8b
+#define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x1b8c
+#define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x1b8d
+#define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x1b8e
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
+#define mmDIG3_AFMT_INTERRUPT_STATUS 0x1b8f
+#define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDIG3_HDMI_GC 0x1b91
+#define mmDIG3_HDMI_GC_BASE_IDX 2
+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x1b92
+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
+#define mmDIG3_AFMT_ISRC1_0 0x1b93
+#define mmDIG3_AFMT_ISRC1_0_BASE_IDX 2
+#define mmDIG3_AFMT_ISRC1_1 0x1b94
+#define mmDIG3_AFMT_ISRC1_1_BASE_IDX 2
+#define mmDIG3_AFMT_ISRC1_2 0x1b95
+#define mmDIG3_AFMT_ISRC1_2_BASE_IDX 2
+#define mmDIG3_AFMT_ISRC1_3 0x1b96
+#define mmDIG3_AFMT_ISRC1_3_BASE_IDX 2
+#define mmDIG3_AFMT_ISRC1_4 0x1b97
+#define mmDIG3_AFMT_ISRC1_4_BASE_IDX 2
+#define mmDIG3_AFMT_ISRC2_0 0x1b98
+#define mmDIG3_AFMT_ISRC2_0_BASE_IDX 2
+#define mmDIG3_AFMT_ISRC2_1 0x1b99
+#define mmDIG3_AFMT_ISRC2_1_BASE_IDX 2
+#define mmDIG3_AFMT_ISRC2_2 0x1b9a
+#define mmDIG3_AFMT_ISRC2_2_BASE_IDX 2
+#define mmDIG3_AFMT_ISRC2_3 0x1b9b
+#define mmDIG3_AFMT_ISRC2_3_BASE_IDX 2
+#define mmDIG3_AFMT_AVI_INFO0 0x1b9c
+#define mmDIG3_AFMT_AVI_INFO0_BASE_IDX 2
+#define mmDIG3_AFMT_AVI_INFO1 0x1b9d
+#define mmDIG3_AFMT_AVI_INFO1_BASE_IDX 2
+#define mmDIG3_AFMT_AVI_INFO2 0x1b9e
+#define mmDIG3_AFMT_AVI_INFO2_BASE_IDX 2
+#define mmDIG3_AFMT_AVI_INFO3 0x1b9f
+#define mmDIG3_AFMT_AVI_INFO3_BASE_IDX 2
+#define mmDIG3_AFMT_MPEG_INFO0 0x1ba0
+#define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX 2
+#define mmDIG3_AFMT_MPEG_INFO1 0x1ba1
+#define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX 2
+#define mmDIG3_AFMT_GENERIC_HDR 0x1ba2
+#define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX 2
+#define mmDIG3_AFMT_GENERIC_0 0x1ba3
+#define mmDIG3_AFMT_GENERIC_0_BASE_IDX 2
+#define mmDIG3_AFMT_GENERIC_1 0x1ba4
+#define mmDIG3_AFMT_GENERIC_1_BASE_IDX 2
+#define mmDIG3_AFMT_GENERIC_2 0x1ba5
+#define mmDIG3_AFMT_GENERIC_2_BASE_IDX 2
+#define mmDIG3_AFMT_GENERIC_3 0x1ba6
+#define mmDIG3_AFMT_GENERIC_3_BASE_IDX 2
+#define mmDIG3_AFMT_GENERIC_4 0x1ba7
+#define mmDIG3_AFMT_GENERIC_4_BASE_IDX 2
+#define mmDIG3_AFMT_GENERIC_5 0x1ba8
+#define mmDIG3_AFMT_GENERIC_5_BASE_IDX 2
+#define mmDIG3_AFMT_GENERIC_6 0x1ba9
+#define mmDIG3_AFMT_GENERIC_6_BASE_IDX 2
+#define mmDIG3_AFMT_GENERIC_7 0x1baa
+#define mmDIG3_AFMT_GENERIC_7_BASE_IDX 2
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x1bab
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
+#define mmDIG3_HDMI_ACR_32_0 0x1bac
+#define mmDIG3_HDMI_ACR_32_0_BASE_IDX 2
+#define mmDIG3_HDMI_ACR_32_1 0x1bad
+#define mmDIG3_HDMI_ACR_32_1_BASE_IDX 2
+#define mmDIG3_HDMI_ACR_44_0 0x1bae
+#define mmDIG3_HDMI_ACR_44_0_BASE_IDX 2
+#define mmDIG3_HDMI_ACR_44_1 0x1baf
+#define mmDIG3_HDMI_ACR_44_1_BASE_IDX 2
+#define mmDIG3_HDMI_ACR_48_0 0x1bb0
+#define mmDIG3_HDMI_ACR_48_0_BASE_IDX 2
+#define mmDIG3_HDMI_ACR_48_1 0x1bb1
+#define mmDIG3_HDMI_ACR_48_1_BASE_IDX 2
+#define mmDIG3_HDMI_ACR_STATUS_0 0x1bb2
+#define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2
+#define mmDIG3_HDMI_ACR_STATUS_1 0x1bb3
+#define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2
+#define mmDIG3_AFMT_AUDIO_INFO0 0x1bb4
+#define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX 2
+#define mmDIG3_AFMT_AUDIO_INFO1 0x1bb5
+#define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX 2
+#define mmDIG3_AFMT_60958_0 0x1bb6
+#define mmDIG3_AFMT_60958_0_BASE_IDX 2
+#define mmDIG3_AFMT_60958_1 0x1bb7
+#define mmDIG3_AFMT_60958_1_BASE_IDX 2
+#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x1bb8
+#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
+#define mmDIG3_AFMT_RAMP_CONTROL0 0x1bb9
+#define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX 2
+#define mmDIG3_AFMT_RAMP_CONTROL1 0x1bba
+#define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX 2
+#define mmDIG3_AFMT_RAMP_CONTROL2 0x1bbb
+#define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX 2
+#define mmDIG3_AFMT_RAMP_CONTROL3 0x1bbc
+#define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX 2
+#define mmDIG3_AFMT_60958_2 0x1bbd
+#define mmDIG3_AFMT_60958_2_BASE_IDX 2
+#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x1bbe
+#define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
+#define mmDIG3_AFMT_STATUS 0x1bbf
+#define mmDIG3_AFMT_STATUS_BASE_IDX 2
+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x1bc0
+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x1bc1
+#define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x1bc2
+#define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x1bc3
+#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
+#define mmDIG3_DIG_BE_CNTL 0x1bc5
+#define mmDIG3_DIG_BE_CNTL_BASE_IDX 2
+#define mmDIG3_DIG_BE_EN_CNTL 0x1bc6
+#define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX 2
+#define mmDIG3_TMDS_CNTL 0x1be9
+#define mmDIG3_TMDS_CNTL_BASE_IDX 2
+#define mmDIG3_TMDS_CONTROL_CHAR 0x1bea
+#define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2
+#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x1beb
+#define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
+#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x1bec
+#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x1bed
+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x1bee
+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
+#define mmDIG3_TMDS_CTL_BITS 0x1bf0
+#define mmDIG3_TMDS_CTL_BITS_BASE_IDX 2
+#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x1bf1
+#define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
+#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x1bf3
+#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
+#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x1bf4
+#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
+#define mmDIG3_DIG_VERSION 0x1bf6
+#define mmDIG3_DIG_VERSION_BASE_IDX 2
+#define mmDIG3_DIG_LANE_ENABLE 0x1bf7
+#define mmDIG3_DIG_LANE_ENABLE_BASE_IDX 2
+#define mmDIG3_AFMT_CNTL 0x1bfc
+#define mmDIG3_AFMT_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dp3_dispdec
+// base address: 0xc00
+#define mmDP3_DP_LINK_CNTL 0x1c1e
+#define mmDP3_DP_LINK_CNTL_BASE_IDX 2
+#define mmDP3_DP_PIXEL_FORMAT 0x1c1f
+#define mmDP3_DP_PIXEL_FORMAT_BASE_IDX 2
+#define mmDP3_DP_MSA_COLORIMETRY 0x1c20
+#define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX 2
+#define mmDP3_DP_CONFIG 0x1c21
+#define mmDP3_DP_CONFIG_BASE_IDX 2
+#define mmDP3_DP_VID_STREAM_CNTL 0x1c22
+#define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX 2
+#define mmDP3_DP_STEER_FIFO 0x1c23
+#define mmDP3_DP_STEER_FIFO_BASE_IDX 2
+#define mmDP3_DP_MSA_MISC 0x1c24
+#define mmDP3_DP_MSA_MISC_BASE_IDX 2
+#define mmDP3_DP_VID_TIMING 0x1c26
+#define mmDP3_DP_VID_TIMING_BASE_IDX 2
+#define mmDP3_DP_VID_N 0x1c27
+#define mmDP3_DP_VID_N_BASE_IDX 2
+#define mmDP3_DP_VID_M 0x1c28
+#define mmDP3_DP_VID_M_BASE_IDX 2
+#define mmDP3_DP_LINK_FRAMING_CNTL 0x1c29
+#define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2
+#define mmDP3_DP_HBR2_EYE_PATTERN 0x1c2a
+#define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2
+#define mmDP3_DP_VID_MSA_VBID 0x1c2b
+#define mmDP3_DP_VID_MSA_VBID_BASE_IDX 2
+#define mmDP3_DP_VID_INTERRUPT_CNTL 0x1c2c
+#define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
+#define mmDP3_DP_DPHY_CNTL 0x1c2d
+#define mmDP3_DP_DPHY_CNTL_BASE_IDX 2
+#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x1c2e
+#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
+#define mmDP3_DP_DPHY_SYM0 0x1c2f
+#define mmDP3_DP_DPHY_SYM0_BASE_IDX 2
+#define mmDP3_DP_DPHY_SYM1 0x1c30
+#define mmDP3_DP_DPHY_SYM1_BASE_IDX 2
+#define mmDP3_DP_DPHY_SYM2 0x1c31
+#define mmDP3_DP_DPHY_SYM2_BASE_IDX 2
+#define mmDP3_DP_DPHY_8B10B_CNTL 0x1c32
+#define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2
+#define mmDP3_DP_DPHY_PRBS_CNTL 0x1c33
+#define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2
+#define mmDP3_DP_DPHY_SCRAM_CNTL 0x1c34
+#define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
+#define mmDP3_DP_DPHY_CRC_EN 0x1c35
+#define mmDP3_DP_DPHY_CRC_EN_BASE_IDX 2
+#define mmDP3_DP_DPHY_CRC_CNTL 0x1c36
+#define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2
+#define mmDP3_DP_DPHY_CRC_RESULT 0x1c37
+#define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2
+#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x1c38
+#define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
+#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x1c39
+#define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
+#define mmDP3_DP_DPHY_FAST_TRAINING 0x1c3a
+#define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2
+#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x1c3b
+#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
+#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x1c3c
+#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
+#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x1c3d
+#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
+#define mmDP3_DP_SEC_CNTL 0x1c41
+#define mmDP3_DP_SEC_CNTL_BASE_IDX 2
+#define mmDP3_DP_SEC_CNTL1 0x1c42
+#define mmDP3_DP_SEC_CNTL1_BASE_IDX 2
+#define mmDP3_DP_SEC_FRAMING1 0x1c43
+#define mmDP3_DP_SEC_FRAMING1_BASE_IDX 2
+#define mmDP3_DP_SEC_FRAMING2 0x1c44
+#define mmDP3_DP_SEC_FRAMING2_BASE_IDX 2
+#define mmDP3_DP_SEC_FRAMING3 0x1c45
+#define mmDP3_DP_SEC_FRAMING3_BASE_IDX 2
+#define mmDP3_DP_SEC_FRAMING4 0x1c46
+#define mmDP3_DP_SEC_FRAMING4_BASE_IDX 2
+#define mmDP3_DP_SEC_AUD_N 0x1c47
+#define mmDP3_DP_SEC_AUD_N_BASE_IDX 2
+#define mmDP3_DP_SEC_AUD_N_READBACK 0x1c48
+#define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2
+#define mmDP3_DP_SEC_AUD_M 0x1c49
+#define mmDP3_DP_SEC_AUD_M_BASE_IDX 2
+#define mmDP3_DP_SEC_AUD_M_READBACK 0x1c4a
+#define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2
+#define mmDP3_DP_SEC_TIMESTAMP 0x1c4b
+#define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX 2
+#define mmDP3_DP_SEC_PACKET_CNTL 0x1c4c
+#define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2
+#define mmDP3_DP_MSE_RATE_CNTL 0x1c4d
+#define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX 2
+#define mmDP3_DP_MSE_RATE_UPDATE 0x1c4f
+#define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2
+#define mmDP3_DP_MSE_SAT0 0x1c50
+#define mmDP3_DP_MSE_SAT0_BASE_IDX 2
+#define mmDP3_DP_MSE_SAT1 0x1c51
+#define mmDP3_DP_MSE_SAT1_BASE_IDX 2
+#define mmDP3_DP_MSE_SAT2 0x1c52
+#define mmDP3_DP_MSE_SAT2_BASE_IDX 2
+#define mmDP3_DP_MSE_SAT_UPDATE 0x1c53
+#define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2
+#define mmDP3_DP_MSE_LINK_TIMING 0x1c54
+#define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX 2
+#define mmDP3_DP_MSE_MISC_CNTL 0x1c55
+#define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX 2
+#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x1c5a
+#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
+#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x1c5b
+#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
+#define mmDP3_DP_MSE_SAT0_STATUS 0x1c5d
+#define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2
+#define mmDP3_DP_MSE_SAT1_STATUS 0x1c5e
+#define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2
+#define mmDP3_DP_MSE_SAT2_STATUS 0x1c5f
+#define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dig4_dispdec
+// base address: 0x1000
+#define mmDIG4_DIG_FE_CNTL 0x1c7e
+#define mmDIG4_DIG_FE_CNTL_BASE_IDX 2
+#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x1c7f
+#define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
+#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x1c80
+#define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
+#define mmDIG4_DIG_CLOCK_PATTERN 0x1c81
+#define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2
+#define mmDIG4_DIG_TEST_PATTERN 0x1c82
+#define mmDIG4_DIG_TEST_PATTERN_BASE_IDX 2
+#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x1c83
+#define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
+#define mmDIG4_DIG_FIFO_STATUS 0x1c84
+#define mmDIG4_DIG_FIFO_STATUS_BASE_IDX 2
+#define mmDIG4_HDMI_CONTROL 0x1c87
+#define mmDIG4_HDMI_CONTROL_BASE_IDX 2
+#define mmDIG4_HDMI_STATUS 0x1c88
+#define mmDIG4_HDMI_STATUS_BASE_IDX 2
+#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x1c89
+#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x1c8a
+#define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x1c8b
+#define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x1c8c
+#define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x1c8d
+#define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x1c8e
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
+#define mmDIG4_AFMT_INTERRUPT_STATUS 0x1c8f
+#define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDIG4_HDMI_GC 0x1c91
+#define mmDIG4_HDMI_GC_BASE_IDX 2
+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x1c92
+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
+#define mmDIG4_AFMT_ISRC1_0 0x1c93
+#define mmDIG4_AFMT_ISRC1_0_BASE_IDX 2
+#define mmDIG4_AFMT_ISRC1_1 0x1c94
+#define mmDIG4_AFMT_ISRC1_1_BASE_IDX 2
+#define mmDIG4_AFMT_ISRC1_2 0x1c95
+#define mmDIG4_AFMT_ISRC1_2_BASE_IDX 2
+#define mmDIG4_AFMT_ISRC1_3 0x1c96
+#define mmDIG4_AFMT_ISRC1_3_BASE_IDX 2
+#define mmDIG4_AFMT_ISRC1_4 0x1c97
+#define mmDIG4_AFMT_ISRC1_4_BASE_IDX 2
+#define mmDIG4_AFMT_ISRC2_0 0x1c98
+#define mmDIG4_AFMT_ISRC2_0_BASE_IDX 2
+#define mmDIG4_AFMT_ISRC2_1 0x1c99
+#define mmDIG4_AFMT_ISRC2_1_BASE_IDX 2
+#define mmDIG4_AFMT_ISRC2_2 0x1c9a
+#define mmDIG4_AFMT_ISRC2_2_BASE_IDX 2
+#define mmDIG4_AFMT_ISRC2_3 0x1c9b
+#define mmDIG4_AFMT_ISRC2_3_BASE_IDX 2
+#define mmDIG4_AFMT_AVI_INFO0 0x1c9c
+#define mmDIG4_AFMT_AVI_INFO0_BASE_IDX 2
+#define mmDIG4_AFMT_AVI_INFO1 0x1c9d
+#define mmDIG4_AFMT_AVI_INFO1_BASE_IDX 2
+#define mmDIG4_AFMT_AVI_INFO2 0x1c9e
+#define mmDIG4_AFMT_AVI_INFO2_BASE_IDX 2
+#define mmDIG4_AFMT_AVI_INFO3 0x1c9f
+#define mmDIG4_AFMT_AVI_INFO3_BASE_IDX 2
+#define mmDIG4_AFMT_MPEG_INFO0 0x1ca0
+#define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX 2
+#define mmDIG4_AFMT_MPEG_INFO1 0x1ca1
+#define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX 2
+#define mmDIG4_AFMT_GENERIC_HDR 0x1ca2
+#define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX 2
+#define mmDIG4_AFMT_GENERIC_0 0x1ca3
+#define mmDIG4_AFMT_GENERIC_0_BASE_IDX 2
+#define mmDIG4_AFMT_GENERIC_1 0x1ca4
+#define mmDIG4_AFMT_GENERIC_1_BASE_IDX 2
+#define mmDIG4_AFMT_GENERIC_2 0x1ca5
+#define mmDIG4_AFMT_GENERIC_2_BASE_IDX 2
+#define mmDIG4_AFMT_GENERIC_3 0x1ca6
+#define mmDIG4_AFMT_GENERIC_3_BASE_IDX 2
+#define mmDIG4_AFMT_GENERIC_4 0x1ca7
+#define mmDIG4_AFMT_GENERIC_4_BASE_IDX 2
+#define mmDIG4_AFMT_GENERIC_5 0x1ca8
+#define mmDIG4_AFMT_GENERIC_5_BASE_IDX 2
+#define mmDIG4_AFMT_GENERIC_6 0x1ca9
+#define mmDIG4_AFMT_GENERIC_6_BASE_IDX 2
+#define mmDIG4_AFMT_GENERIC_7 0x1caa
+#define mmDIG4_AFMT_GENERIC_7_BASE_IDX 2
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x1cab
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
+#define mmDIG4_HDMI_ACR_32_0 0x1cac
+#define mmDIG4_HDMI_ACR_32_0_BASE_IDX 2
+#define mmDIG4_HDMI_ACR_32_1 0x1cad
+#define mmDIG4_HDMI_ACR_32_1_BASE_IDX 2
+#define mmDIG4_HDMI_ACR_44_0 0x1cae
+#define mmDIG4_HDMI_ACR_44_0_BASE_IDX 2
+#define mmDIG4_HDMI_ACR_44_1 0x1caf
+#define mmDIG4_HDMI_ACR_44_1_BASE_IDX 2
+#define mmDIG4_HDMI_ACR_48_0 0x1cb0
+#define mmDIG4_HDMI_ACR_48_0_BASE_IDX 2
+#define mmDIG4_HDMI_ACR_48_1 0x1cb1
+#define mmDIG4_HDMI_ACR_48_1_BASE_IDX 2
+#define mmDIG4_HDMI_ACR_STATUS_0 0x1cb2
+#define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2
+#define mmDIG4_HDMI_ACR_STATUS_1 0x1cb3
+#define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2
+#define mmDIG4_AFMT_AUDIO_INFO0 0x1cb4
+#define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX 2
+#define mmDIG4_AFMT_AUDIO_INFO1 0x1cb5
+#define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX 2
+#define mmDIG4_AFMT_60958_0 0x1cb6
+#define mmDIG4_AFMT_60958_0_BASE_IDX 2
+#define mmDIG4_AFMT_60958_1 0x1cb7
+#define mmDIG4_AFMT_60958_1_BASE_IDX 2
+#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x1cb8
+#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
+#define mmDIG4_AFMT_RAMP_CONTROL0 0x1cb9
+#define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX 2
+#define mmDIG4_AFMT_RAMP_CONTROL1 0x1cba
+#define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX 2
+#define mmDIG4_AFMT_RAMP_CONTROL2 0x1cbb
+#define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX 2
+#define mmDIG4_AFMT_RAMP_CONTROL3 0x1cbc
+#define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX 2
+#define mmDIG4_AFMT_60958_2 0x1cbd
+#define mmDIG4_AFMT_60958_2_BASE_IDX 2
+#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x1cbe
+#define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
+#define mmDIG4_AFMT_STATUS 0x1cbf
+#define mmDIG4_AFMT_STATUS_BASE_IDX 2
+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x1cc0
+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x1cc1
+#define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x1cc2
+#define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x1cc3
+#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
+#define mmDIG4_DIG_BE_CNTL 0x1cc5
+#define mmDIG4_DIG_BE_CNTL_BASE_IDX 2
+#define mmDIG4_DIG_BE_EN_CNTL 0x1cc6
+#define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX 2
+#define mmDIG4_TMDS_CNTL 0x1ce9
+#define mmDIG4_TMDS_CNTL_BASE_IDX 2
+#define mmDIG4_TMDS_CONTROL_CHAR 0x1cea
+#define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2
+#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x1ceb
+#define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
+#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x1cec
+#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x1ced
+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x1cee
+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
+#define mmDIG4_TMDS_CTL_BITS 0x1cf0
+#define mmDIG4_TMDS_CTL_BITS_BASE_IDX 2
+#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x1cf1
+#define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
+#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x1cf3
+#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
+#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x1cf4
+#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
+#define mmDIG4_DIG_VERSION 0x1cf6
+#define mmDIG4_DIG_VERSION_BASE_IDX 2
+#define mmDIG4_DIG_LANE_ENABLE 0x1cf7
+#define mmDIG4_DIG_LANE_ENABLE_BASE_IDX 2
+#define mmDIG4_AFMT_CNTL 0x1cfc
+#define mmDIG4_AFMT_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dp4_dispdec
+// base address: 0x1000
+#define mmDP4_DP_LINK_CNTL 0x1d1e
+#define mmDP4_DP_LINK_CNTL_BASE_IDX 2
+#define mmDP4_DP_PIXEL_FORMAT 0x1d1f
+#define mmDP4_DP_PIXEL_FORMAT_BASE_IDX 2
+#define mmDP4_DP_MSA_COLORIMETRY 0x1d20
+#define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX 2
+#define mmDP4_DP_CONFIG 0x1d21
+#define mmDP4_DP_CONFIG_BASE_IDX 2
+#define mmDP4_DP_VID_STREAM_CNTL 0x1d22
+#define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX 2
+#define mmDP4_DP_STEER_FIFO 0x1d23
+#define mmDP4_DP_STEER_FIFO_BASE_IDX 2
+#define mmDP4_DP_MSA_MISC 0x1d24
+#define mmDP4_DP_MSA_MISC_BASE_IDX 2
+#define mmDP4_DP_VID_TIMING 0x1d26
+#define mmDP4_DP_VID_TIMING_BASE_IDX 2
+#define mmDP4_DP_VID_N 0x1d27
+#define mmDP4_DP_VID_N_BASE_IDX 2
+#define mmDP4_DP_VID_M 0x1d28
+#define mmDP4_DP_VID_M_BASE_IDX 2
+#define mmDP4_DP_LINK_FRAMING_CNTL 0x1d29
+#define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2
+#define mmDP4_DP_HBR2_EYE_PATTERN 0x1d2a
+#define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2
+#define mmDP4_DP_VID_MSA_VBID 0x1d2b
+#define mmDP4_DP_VID_MSA_VBID_BASE_IDX 2
+#define mmDP4_DP_VID_INTERRUPT_CNTL 0x1d2c
+#define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
+#define mmDP4_DP_DPHY_CNTL 0x1d2d
+#define mmDP4_DP_DPHY_CNTL_BASE_IDX 2
+#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x1d2e
+#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
+#define mmDP4_DP_DPHY_SYM0 0x1d2f
+#define mmDP4_DP_DPHY_SYM0_BASE_IDX 2
+#define mmDP4_DP_DPHY_SYM1 0x1d30
+#define mmDP4_DP_DPHY_SYM1_BASE_IDX 2
+#define mmDP4_DP_DPHY_SYM2 0x1d31
+#define mmDP4_DP_DPHY_SYM2_BASE_IDX 2
+#define mmDP4_DP_DPHY_8B10B_CNTL 0x1d32
+#define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2
+#define mmDP4_DP_DPHY_PRBS_CNTL 0x1d33
+#define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2
+#define mmDP4_DP_DPHY_SCRAM_CNTL 0x1d34
+#define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
+#define mmDP4_DP_DPHY_CRC_EN 0x1d35
+#define mmDP4_DP_DPHY_CRC_EN_BASE_IDX 2
+#define mmDP4_DP_DPHY_CRC_CNTL 0x1d36
+#define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2
+#define mmDP4_DP_DPHY_CRC_RESULT 0x1d37
+#define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2
+#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x1d38
+#define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
+#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x1d39
+#define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
+#define mmDP4_DP_DPHY_FAST_TRAINING 0x1d3a
+#define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2
+#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x1d3b
+#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
+#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x1d3c
+#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
+#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x1d3d
+#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
+#define mmDP4_DP_SEC_CNTL 0x1d41
+#define mmDP4_DP_SEC_CNTL_BASE_IDX 2
+#define mmDP4_DP_SEC_CNTL1 0x1d42
+#define mmDP4_DP_SEC_CNTL1_BASE_IDX 2
+#define mmDP4_DP_SEC_FRAMING1 0x1d43
+#define mmDP4_DP_SEC_FRAMING1_BASE_IDX 2
+#define mmDP4_DP_SEC_FRAMING2 0x1d44
+#define mmDP4_DP_SEC_FRAMING2_BASE_IDX 2
+#define mmDP4_DP_SEC_FRAMING3 0x1d45
+#define mmDP4_DP_SEC_FRAMING3_BASE_IDX 2
+#define mmDP4_DP_SEC_FRAMING4 0x1d46
+#define mmDP4_DP_SEC_FRAMING4_BASE_IDX 2
+#define mmDP4_DP_SEC_AUD_N 0x1d47
+#define mmDP4_DP_SEC_AUD_N_BASE_IDX 2
+#define mmDP4_DP_SEC_AUD_N_READBACK 0x1d48
+#define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2
+#define mmDP4_DP_SEC_AUD_M 0x1d49
+#define mmDP4_DP_SEC_AUD_M_BASE_IDX 2
+#define mmDP4_DP_SEC_AUD_M_READBACK 0x1d4a
+#define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2
+#define mmDP4_DP_SEC_TIMESTAMP 0x1d4b
+#define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX 2
+#define mmDP4_DP_SEC_PACKET_CNTL 0x1d4c
+#define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2
+#define mmDP4_DP_MSE_RATE_CNTL 0x1d4d
+#define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX 2
+#define mmDP4_DP_MSE_RATE_UPDATE 0x1d4f
+#define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2
+#define mmDP4_DP_MSE_SAT0 0x1d50
+#define mmDP4_DP_MSE_SAT0_BASE_IDX 2
+#define mmDP4_DP_MSE_SAT1 0x1d51
+#define mmDP4_DP_MSE_SAT1_BASE_IDX 2
+#define mmDP4_DP_MSE_SAT2 0x1d52
+#define mmDP4_DP_MSE_SAT2_BASE_IDX 2
+#define mmDP4_DP_MSE_SAT_UPDATE 0x1d53
+#define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2
+#define mmDP4_DP_MSE_LINK_TIMING 0x1d54
+#define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX 2
+#define mmDP4_DP_MSE_MISC_CNTL 0x1d55
+#define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX 2
+#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x1d5a
+#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
+#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x1d5b
+#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
+#define mmDP4_DP_MSE_SAT0_STATUS 0x1d5d
+#define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2
+#define mmDP4_DP_MSE_SAT1_STATUS 0x1d5e
+#define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2
+#define mmDP4_DP_MSE_SAT2_STATUS 0x1d5f
+#define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dig5_dispdec
+// base address: 0x1400
+#define mmDIG5_DIG_FE_CNTL 0x1d7e
+#define mmDIG5_DIG_FE_CNTL_BASE_IDX 2
+#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x1d7f
+#define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
+#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x1d80
+#define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
+#define mmDIG5_DIG_CLOCK_PATTERN 0x1d81
+#define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX 2
+#define mmDIG5_DIG_TEST_PATTERN 0x1d82
+#define mmDIG5_DIG_TEST_PATTERN_BASE_IDX 2
+#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x1d83
+#define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
+#define mmDIG5_DIG_FIFO_STATUS 0x1d84
+#define mmDIG5_DIG_FIFO_STATUS_BASE_IDX 2
+#define mmDIG5_HDMI_CONTROL 0x1d87
+#define mmDIG5_HDMI_CONTROL_BASE_IDX 2
+#define mmDIG5_HDMI_STATUS 0x1d88
+#define mmDIG5_HDMI_STATUS_BASE_IDX 2
+#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x1d89
+#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x1d8a
+#define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x1d8b
+#define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x1d8c
+#define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x1d8d
+#define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x1d8e
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
+#define mmDIG5_AFMT_INTERRUPT_STATUS 0x1d8f
+#define mmDIG5_AFMT_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDIG5_HDMI_GC 0x1d91
+#define mmDIG5_HDMI_GC_BASE_IDX 2
+#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x1d92
+#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
+#define mmDIG5_AFMT_ISRC1_0 0x1d93
+#define mmDIG5_AFMT_ISRC1_0_BASE_IDX 2
+#define mmDIG5_AFMT_ISRC1_1 0x1d94
+#define mmDIG5_AFMT_ISRC1_1_BASE_IDX 2
+#define mmDIG5_AFMT_ISRC1_2 0x1d95
+#define mmDIG5_AFMT_ISRC1_2_BASE_IDX 2
+#define mmDIG5_AFMT_ISRC1_3 0x1d96
+#define mmDIG5_AFMT_ISRC1_3_BASE_IDX 2
+#define mmDIG5_AFMT_ISRC1_4 0x1d97
+#define mmDIG5_AFMT_ISRC1_4_BASE_IDX 2
+#define mmDIG5_AFMT_ISRC2_0 0x1d98
+#define mmDIG5_AFMT_ISRC2_0_BASE_IDX 2
+#define mmDIG5_AFMT_ISRC2_1 0x1d99
+#define mmDIG5_AFMT_ISRC2_1_BASE_IDX 2
+#define mmDIG5_AFMT_ISRC2_2 0x1d9a
+#define mmDIG5_AFMT_ISRC2_2_BASE_IDX 2
+#define mmDIG5_AFMT_ISRC2_3 0x1d9b
+#define mmDIG5_AFMT_ISRC2_3_BASE_IDX 2
+#define mmDIG5_AFMT_AVI_INFO0 0x1d9c
+#define mmDIG5_AFMT_AVI_INFO0_BASE_IDX 2
+#define mmDIG5_AFMT_AVI_INFO1 0x1d9d
+#define mmDIG5_AFMT_AVI_INFO1_BASE_IDX 2
+#define mmDIG5_AFMT_AVI_INFO2 0x1d9e
+#define mmDIG5_AFMT_AVI_INFO2_BASE_IDX 2
+#define mmDIG5_AFMT_AVI_INFO3 0x1d9f
+#define mmDIG5_AFMT_AVI_INFO3_BASE_IDX 2
+#define mmDIG5_AFMT_MPEG_INFO0 0x1da0
+#define mmDIG5_AFMT_MPEG_INFO0_BASE_IDX 2
+#define mmDIG5_AFMT_MPEG_INFO1 0x1da1
+#define mmDIG5_AFMT_MPEG_INFO1_BASE_IDX 2
+#define mmDIG5_AFMT_GENERIC_HDR 0x1da2
+#define mmDIG5_AFMT_GENERIC_HDR_BASE_IDX 2
+#define mmDIG5_AFMT_GENERIC_0 0x1da3
+#define mmDIG5_AFMT_GENERIC_0_BASE_IDX 2
+#define mmDIG5_AFMT_GENERIC_1 0x1da4
+#define mmDIG5_AFMT_GENERIC_1_BASE_IDX 2
+#define mmDIG5_AFMT_GENERIC_2 0x1da5
+#define mmDIG5_AFMT_GENERIC_2_BASE_IDX 2
+#define mmDIG5_AFMT_GENERIC_3 0x1da6
+#define mmDIG5_AFMT_GENERIC_3_BASE_IDX 2
+#define mmDIG5_AFMT_GENERIC_4 0x1da7
+#define mmDIG5_AFMT_GENERIC_4_BASE_IDX 2
+#define mmDIG5_AFMT_GENERIC_5 0x1da8
+#define mmDIG5_AFMT_GENERIC_5_BASE_IDX 2
+#define mmDIG5_AFMT_GENERIC_6 0x1da9
+#define mmDIG5_AFMT_GENERIC_6_BASE_IDX 2
+#define mmDIG5_AFMT_GENERIC_7 0x1daa
+#define mmDIG5_AFMT_GENERIC_7_BASE_IDX 2
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x1dab
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
+#define mmDIG5_HDMI_ACR_32_0 0x1dac
+#define mmDIG5_HDMI_ACR_32_0_BASE_IDX 2
+#define mmDIG5_HDMI_ACR_32_1 0x1dad
+#define mmDIG5_HDMI_ACR_32_1_BASE_IDX 2
+#define mmDIG5_HDMI_ACR_44_0 0x1dae
+#define mmDIG5_HDMI_ACR_44_0_BASE_IDX 2
+#define mmDIG5_HDMI_ACR_44_1 0x1daf
+#define mmDIG5_HDMI_ACR_44_1_BASE_IDX 2
+#define mmDIG5_HDMI_ACR_48_0 0x1db0
+#define mmDIG5_HDMI_ACR_48_0_BASE_IDX 2
+#define mmDIG5_HDMI_ACR_48_1 0x1db1
+#define mmDIG5_HDMI_ACR_48_1_BASE_IDX 2
+#define mmDIG5_HDMI_ACR_STATUS_0 0x1db2
+#define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX 2
+#define mmDIG5_HDMI_ACR_STATUS_1 0x1db3
+#define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX 2
+#define mmDIG5_AFMT_AUDIO_INFO0 0x1db4
+#define mmDIG5_AFMT_AUDIO_INFO0_BASE_IDX 2
+#define mmDIG5_AFMT_AUDIO_INFO1 0x1db5
+#define mmDIG5_AFMT_AUDIO_INFO1_BASE_IDX 2
+#define mmDIG5_AFMT_60958_0 0x1db6
+#define mmDIG5_AFMT_60958_0_BASE_IDX 2
+#define mmDIG5_AFMT_60958_1 0x1db7
+#define mmDIG5_AFMT_60958_1_BASE_IDX 2
+#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x1db8
+#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
+#define mmDIG5_AFMT_RAMP_CONTROL0 0x1db9
+#define mmDIG5_AFMT_RAMP_CONTROL0_BASE_IDX 2
+#define mmDIG5_AFMT_RAMP_CONTROL1 0x1dba
+#define mmDIG5_AFMT_RAMP_CONTROL1_BASE_IDX 2
+#define mmDIG5_AFMT_RAMP_CONTROL2 0x1dbb
+#define mmDIG5_AFMT_RAMP_CONTROL2_BASE_IDX 2
+#define mmDIG5_AFMT_RAMP_CONTROL3 0x1dbc
+#define mmDIG5_AFMT_RAMP_CONTROL3_BASE_IDX 2
+#define mmDIG5_AFMT_60958_2 0x1dbd
+#define mmDIG5_AFMT_60958_2_BASE_IDX 2
+#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x1dbe
+#define mmDIG5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
+#define mmDIG5_AFMT_STATUS 0x1dbf
+#define mmDIG5_AFMT_STATUS_BASE_IDX 2
+#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x1dc0
+#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x1dc1
+#define mmDIG5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x1dc2
+#define mmDIG5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x1dc3
+#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
+#define mmDIG5_DIG_BE_CNTL 0x1dc5
+#define mmDIG5_DIG_BE_CNTL_BASE_IDX 2
+#define mmDIG5_DIG_BE_EN_CNTL 0x1dc6
+#define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX 2
+#define mmDIG5_TMDS_CNTL 0x1de9
+#define mmDIG5_TMDS_CNTL_BASE_IDX 2
+#define mmDIG5_TMDS_CONTROL_CHAR 0x1dea
+#define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX 2
+#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x1deb
+#define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
+#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x1dec
+#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
+#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x1ded
+#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
+#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x1dee
+#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
+#define mmDIG5_TMDS_CTL_BITS 0x1df0
+#define mmDIG5_TMDS_CTL_BITS_BASE_IDX 2
+#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x1df1
+#define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
+#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x1df3
+#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
+#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x1df4
+#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
+#define mmDIG5_DIG_VERSION 0x1df6
+#define mmDIG5_DIG_VERSION_BASE_IDX 2
+#define mmDIG5_DIG_LANE_ENABLE 0x1df7
+#define mmDIG5_DIG_LANE_ENABLE_BASE_IDX 2
+#define mmDIG5_AFMT_CNTL 0x1dfc
+#define mmDIG5_AFMT_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dp5_dispdec
+// base address: 0x1400
+#define mmDP5_DP_LINK_CNTL 0x1e1e
+#define mmDP5_DP_LINK_CNTL_BASE_IDX 2
+#define mmDP5_DP_PIXEL_FORMAT 0x1e1f
+#define mmDP5_DP_PIXEL_FORMAT_BASE_IDX 2
+#define mmDP5_DP_MSA_COLORIMETRY 0x1e20
+#define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX 2
+#define mmDP5_DP_CONFIG 0x1e21
+#define mmDP5_DP_CONFIG_BASE_IDX 2
+#define mmDP5_DP_VID_STREAM_CNTL 0x1e22
+#define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 2
+#define mmDP5_DP_STEER_FIFO 0x1e23
+#define mmDP5_DP_STEER_FIFO_BASE_IDX 2
+#define mmDP5_DP_MSA_MISC 0x1e24
+#define mmDP5_DP_MSA_MISC_BASE_IDX 2
+#define mmDP5_DP_VID_TIMING 0x1e26
+#define mmDP5_DP_VID_TIMING_BASE_IDX 2
+#define mmDP5_DP_VID_N 0x1e27
+#define mmDP5_DP_VID_N_BASE_IDX 2
+#define mmDP5_DP_VID_M 0x1e28
+#define mmDP5_DP_VID_M_BASE_IDX 2
+#define mmDP5_DP_LINK_FRAMING_CNTL 0x1e29
+#define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX 2
+#define mmDP5_DP_HBR2_EYE_PATTERN 0x1e2a
+#define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX 2
+#define mmDP5_DP_VID_MSA_VBID 0x1e2b
+#define mmDP5_DP_VID_MSA_VBID_BASE_IDX 2
+#define mmDP5_DP_VID_INTERRUPT_CNTL 0x1e2c
+#define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
+#define mmDP5_DP_DPHY_CNTL 0x1e2d
+#define mmDP5_DP_DPHY_CNTL_BASE_IDX 2
+#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x1e2e
+#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
+#define mmDP5_DP_DPHY_SYM0 0x1e2f
+#define mmDP5_DP_DPHY_SYM0_BASE_IDX 2
+#define mmDP5_DP_DPHY_SYM1 0x1e30
+#define mmDP5_DP_DPHY_SYM1_BASE_IDX 2
+#define mmDP5_DP_DPHY_SYM2 0x1e31
+#define mmDP5_DP_DPHY_SYM2_BASE_IDX 2
+#define mmDP5_DP_DPHY_8B10B_CNTL 0x1e32
+#define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX 2
+#define mmDP5_DP_DPHY_PRBS_CNTL 0x1e33
+#define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX 2
+#define mmDP5_DP_DPHY_SCRAM_CNTL 0x1e34
+#define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
+#define mmDP5_DP_DPHY_CRC_EN 0x1e35
+#define mmDP5_DP_DPHY_CRC_EN_BASE_IDX 2
+#define mmDP5_DP_DPHY_CRC_CNTL 0x1e36
+#define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX 2
+#define mmDP5_DP_DPHY_CRC_RESULT 0x1e37
+#define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX 2
+#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x1e38
+#define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
+#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x1e39
+#define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
+#define mmDP5_DP_DPHY_FAST_TRAINING 0x1e3a
+#define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX 2
+#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x1e3b
+#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
+#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x1e3c
+#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
+#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x1e3d
+#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
+#define mmDP5_DP_SEC_CNTL 0x1e41
+#define mmDP5_DP_SEC_CNTL_BASE_IDX 2
+#define mmDP5_DP_SEC_CNTL1 0x1e42
+#define mmDP5_DP_SEC_CNTL1_BASE_IDX 2
+#define mmDP5_DP_SEC_FRAMING1 0x1e43
+#define mmDP5_DP_SEC_FRAMING1_BASE_IDX 2
+#define mmDP5_DP_SEC_FRAMING2 0x1e44
+#define mmDP5_DP_SEC_FRAMING2_BASE_IDX 2
+#define mmDP5_DP_SEC_FRAMING3 0x1e45
+#define mmDP5_DP_SEC_FRAMING3_BASE_IDX 2
+#define mmDP5_DP_SEC_FRAMING4 0x1e46
+#define mmDP5_DP_SEC_FRAMING4_BASE_IDX 2
+#define mmDP5_DP_SEC_AUD_N 0x1e47
+#define mmDP5_DP_SEC_AUD_N_BASE_IDX 2
+#define mmDP5_DP_SEC_AUD_N_READBACK 0x1e48
+#define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX 2
+#define mmDP5_DP_SEC_AUD_M 0x1e49
+#define mmDP5_DP_SEC_AUD_M_BASE_IDX 2
+#define mmDP5_DP_SEC_AUD_M_READBACK 0x1e4a
+#define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX 2
+#define mmDP5_DP_SEC_TIMESTAMP 0x1e4b
+#define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX 2
+#define mmDP5_DP_SEC_PACKET_CNTL 0x1e4c
+#define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX 2
+#define mmDP5_DP_MSE_RATE_CNTL 0x1e4d
+#define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX 2
+#define mmDP5_DP_MSE_RATE_UPDATE 0x1e4f
+#define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX 2
+#define mmDP5_DP_MSE_SAT0 0x1e50
+#define mmDP5_DP_MSE_SAT0_BASE_IDX 2
+#define mmDP5_DP_MSE_SAT1 0x1e51
+#define mmDP5_DP_MSE_SAT1_BASE_IDX 2
+#define mmDP5_DP_MSE_SAT2 0x1e52
+#define mmDP5_DP_MSE_SAT2_BASE_IDX 2
+#define mmDP5_DP_MSE_SAT_UPDATE 0x1e53
+#define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX 2
+#define mmDP5_DP_MSE_LINK_TIMING 0x1e54
+#define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX 2
+#define mmDP5_DP_MSE_MISC_CNTL 0x1e55
+#define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX 2
+#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x1e5a
+#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
+#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x1e5b
+#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
+#define mmDP5_DP_MSE_SAT0_STATUS 0x1e5d
+#define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX 2
+#define mmDP5_DP_MSE_SAT1_STATUS 0x1e5e
+#define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX 2
+#define mmDP5_DP_MSE_SAT2_STATUS 0x1e5f
+#define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dig6_dispdec
+// base address: 0x1800
+#define mmDIG6_DIG_FE_CNTL 0x1e7e
+#define mmDIG6_DIG_FE_CNTL_BASE_IDX 2
+#define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x1e7f
+#define mmDIG6_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
+#define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x1e80
+#define mmDIG6_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
+#define mmDIG6_DIG_CLOCK_PATTERN 0x1e81
+#define mmDIG6_DIG_CLOCK_PATTERN_BASE_IDX 2
+#define mmDIG6_DIG_TEST_PATTERN 0x1e82
+#define mmDIG6_DIG_TEST_PATTERN_BASE_IDX 2
+#define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x1e83
+#define mmDIG6_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
+#define mmDIG6_DIG_FIFO_STATUS 0x1e84
+#define mmDIG6_DIG_FIFO_STATUS_BASE_IDX 2
+#define mmDIG6_HDMI_CONTROL 0x1e87
+#define mmDIG6_HDMI_CONTROL_BASE_IDX 2
+#define mmDIG6_HDMI_STATUS 0x1e88
+#define mmDIG6_HDMI_STATUS_BASE_IDX 2
+#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x1e89
+#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x1e8a
+#define mmDIG6_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x1e8b
+#define mmDIG6_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x1e8c
+#define mmDIG6_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x1e8d
+#define mmDIG6_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
+#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x1e8e
+#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
+#define mmDIG6_AFMT_INTERRUPT_STATUS 0x1e8f
+#define mmDIG6_AFMT_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDIG6_HDMI_GC 0x1e91
+#define mmDIG6_HDMI_GC_BASE_IDX 2
+#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x1e92
+#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
+#define mmDIG6_AFMT_ISRC1_0 0x1e93
+#define mmDIG6_AFMT_ISRC1_0_BASE_IDX 2
+#define mmDIG6_AFMT_ISRC1_1 0x1e94
+#define mmDIG6_AFMT_ISRC1_1_BASE_IDX 2
+#define mmDIG6_AFMT_ISRC1_2 0x1e95
+#define mmDIG6_AFMT_ISRC1_2_BASE_IDX 2
+#define mmDIG6_AFMT_ISRC1_3 0x1e96
+#define mmDIG6_AFMT_ISRC1_3_BASE_IDX 2
+#define mmDIG6_AFMT_ISRC1_4 0x1e97
+#define mmDIG6_AFMT_ISRC1_4_BASE_IDX 2
+#define mmDIG6_AFMT_ISRC2_0 0x1e98
+#define mmDIG6_AFMT_ISRC2_0_BASE_IDX 2
+#define mmDIG6_AFMT_ISRC2_1 0x1e99
+#define mmDIG6_AFMT_ISRC2_1_BASE_IDX 2
+#define mmDIG6_AFMT_ISRC2_2 0x1e9a
+#define mmDIG6_AFMT_ISRC2_2_BASE_IDX 2
+#define mmDIG6_AFMT_ISRC2_3 0x1e9b
+#define mmDIG6_AFMT_ISRC2_3_BASE_IDX 2
+#define mmDIG6_AFMT_AVI_INFO0 0x1e9c
+#define mmDIG6_AFMT_AVI_INFO0_BASE_IDX 2
+#define mmDIG6_AFMT_AVI_INFO1 0x1e9d
+#define mmDIG6_AFMT_AVI_INFO1_BASE_IDX 2
+#define mmDIG6_AFMT_AVI_INFO2 0x1e9e
+#define mmDIG6_AFMT_AVI_INFO2_BASE_IDX 2
+#define mmDIG6_AFMT_AVI_INFO3 0x1e9f
+#define mmDIG6_AFMT_AVI_INFO3_BASE_IDX 2
+#define mmDIG6_AFMT_MPEG_INFO0 0x1ea0
+#define mmDIG6_AFMT_MPEG_INFO0_BASE_IDX 2
+#define mmDIG6_AFMT_MPEG_INFO1 0x1ea1
+#define mmDIG6_AFMT_MPEG_INFO1_BASE_IDX 2
+#define mmDIG6_AFMT_GENERIC_HDR 0x1ea2
+#define mmDIG6_AFMT_GENERIC_HDR_BASE_IDX 2
+#define mmDIG6_AFMT_GENERIC_0 0x1ea3
+#define mmDIG6_AFMT_GENERIC_0_BASE_IDX 2
+#define mmDIG6_AFMT_GENERIC_1 0x1ea4
+#define mmDIG6_AFMT_GENERIC_1_BASE_IDX 2
+#define mmDIG6_AFMT_GENERIC_2 0x1ea5
+#define mmDIG6_AFMT_GENERIC_2_BASE_IDX 2
+#define mmDIG6_AFMT_GENERIC_3 0x1ea6
+#define mmDIG6_AFMT_GENERIC_3_BASE_IDX 2
+#define mmDIG6_AFMT_GENERIC_4 0x1ea7
+#define mmDIG6_AFMT_GENERIC_4_BASE_IDX 2
+#define mmDIG6_AFMT_GENERIC_5 0x1ea8
+#define mmDIG6_AFMT_GENERIC_5_BASE_IDX 2
+#define mmDIG6_AFMT_GENERIC_6 0x1ea9
+#define mmDIG6_AFMT_GENERIC_6_BASE_IDX 2
+#define mmDIG6_AFMT_GENERIC_7 0x1eaa
+#define mmDIG6_AFMT_GENERIC_7_BASE_IDX 2
+#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x1eab
+#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
+#define mmDIG6_HDMI_ACR_32_0 0x1eac
+#define mmDIG6_HDMI_ACR_32_0_BASE_IDX 2
+#define mmDIG6_HDMI_ACR_32_1 0x1ead
+#define mmDIG6_HDMI_ACR_32_1_BASE_IDX 2
+#define mmDIG6_HDMI_ACR_44_0 0x1eae
+#define mmDIG6_HDMI_ACR_44_0_BASE_IDX 2
+#define mmDIG6_HDMI_ACR_44_1 0x1eaf
+#define mmDIG6_HDMI_ACR_44_1_BASE_IDX 2
+#define mmDIG6_HDMI_ACR_48_0 0x1eb0
+#define mmDIG6_HDMI_ACR_48_0_BASE_IDX 2
+#define mmDIG6_HDMI_ACR_48_1 0x1eb1
+#define mmDIG6_HDMI_ACR_48_1_BASE_IDX 2
+#define mmDIG6_HDMI_ACR_STATUS_0 0x1eb2
+#define mmDIG6_HDMI_ACR_STATUS_0_BASE_IDX 2
+#define mmDIG6_HDMI_ACR_STATUS_1 0x1eb3
+#define mmDIG6_HDMI_ACR_STATUS_1_BASE_IDX 2
+#define mmDIG6_AFMT_AUDIO_INFO0 0x1eb4
+#define mmDIG6_AFMT_AUDIO_INFO0_BASE_IDX 2
+#define mmDIG6_AFMT_AUDIO_INFO1 0x1eb5
+#define mmDIG6_AFMT_AUDIO_INFO1_BASE_IDX 2
+#define mmDIG6_AFMT_60958_0 0x1eb6
+#define mmDIG6_AFMT_60958_0_BASE_IDX 2
+#define mmDIG6_AFMT_60958_1 0x1eb7
+#define mmDIG6_AFMT_60958_1_BASE_IDX 2
+#define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x1eb8
+#define mmDIG6_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
+#define mmDIG6_AFMT_RAMP_CONTROL0 0x1eb9
+#define mmDIG6_AFMT_RAMP_CONTROL0_BASE_IDX 2
+#define mmDIG6_AFMT_RAMP_CONTROL1 0x1eba
+#define mmDIG6_AFMT_RAMP_CONTROL1_BASE_IDX 2
+#define mmDIG6_AFMT_RAMP_CONTROL2 0x1ebb
+#define mmDIG6_AFMT_RAMP_CONTROL2_BASE_IDX 2
+#define mmDIG6_AFMT_RAMP_CONTROL3 0x1ebc
+#define mmDIG6_AFMT_RAMP_CONTROL3_BASE_IDX 2
+#define mmDIG6_AFMT_60958_2 0x1ebd
+#define mmDIG6_AFMT_60958_2_BASE_IDX 2
+#define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x1ebe
+#define mmDIG6_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
+#define mmDIG6_AFMT_STATUS 0x1ebf
+#define mmDIG6_AFMT_STATUS_BASE_IDX 2
+#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x1ec0
+#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x1ec1
+#define mmDIG6_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x1ec2
+#define mmDIG6_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x1ec3
+#define mmDIG6_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
+#define mmDIG6_DIG_BE_CNTL 0x1ec5
+#define mmDIG6_DIG_BE_CNTL_BASE_IDX 2
+#define mmDIG6_DIG_BE_EN_CNTL 0x1ec6
+#define mmDIG6_DIG_BE_EN_CNTL_BASE_IDX 2
+#define mmDIG6_TMDS_CNTL 0x1ee9
+#define mmDIG6_TMDS_CNTL_BASE_IDX 2
+#define mmDIG6_TMDS_CONTROL_CHAR 0x1eea
+#define mmDIG6_TMDS_CONTROL_CHAR_BASE_IDX 2
+#define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x1eeb
+#define mmDIG6_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
+#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x1eec
+#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
+#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x1eed
+#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
+#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x1eee
+#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
+#define mmDIG6_TMDS_CTL_BITS 0x1ef0
+#define mmDIG6_TMDS_CTL_BITS_BASE_IDX 2
+#define mmDIG6_TMDS_DCBALANCER_CONTROL 0x1ef1
+#define mmDIG6_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
+#define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x1ef3
+#define mmDIG6_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
+#define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x1ef4
+#define mmDIG6_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
+#define mmDIG6_DIG_VERSION 0x1ef6
+#define mmDIG6_DIG_VERSION_BASE_IDX 2
+#define mmDIG6_DIG_LANE_ENABLE 0x1ef7
+#define mmDIG6_DIG_LANE_ENABLE_BASE_IDX 2
+#define mmDIG6_AFMT_CNTL 0x1efc
+#define mmDIG6_AFMT_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dp6_dispdec
+// base address: 0x1800
+#define mmDP6_DP_LINK_CNTL 0x1f1e
+#define mmDP6_DP_LINK_CNTL_BASE_IDX 2
+#define mmDP6_DP_PIXEL_FORMAT 0x1f1f
+#define mmDP6_DP_PIXEL_FORMAT_BASE_IDX 2
+#define mmDP6_DP_MSA_COLORIMETRY 0x1f20
+#define mmDP6_DP_MSA_COLORIMETRY_BASE_IDX 2
+#define mmDP6_DP_CONFIG 0x1f21
+#define mmDP6_DP_CONFIG_BASE_IDX 2
+#define mmDP6_DP_VID_STREAM_CNTL 0x1f22
+#define mmDP6_DP_VID_STREAM_CNTL_BASE_IDX 2
+#define mmDP6_DP_STEER_FIFO 0x1f23
+#define mmDP6_DP_STEER_FIFO_BASE_IDX 2
+#define mmDP6_DP_MSA_MISC 0x1f24
+#define mmDP6_DP_MSA_MISC_BASE_IDX 2
+#define mmDP6_DP_VID_TIMING 0x1f26
+#define mmDP6_DP_VID_TIMING_BASE_IDX 2
+#define mmDP6_DP_VID_N 0x1f27
+#define mmDP6_DP_VID_N_BASE_IDX 2
+#define mmDP6_DP_VID_M 0x1f28
+#define mmDP6_DP_VID_M_BASE_IDX 2
+#define mmDP6_DP_LINK_FRAMING_CNTL 0x1f29
+#define mmDP6_DP_LINK_FRAMING_CNTL_BASE_IDX 2
+#define mmDP6_DP_HBR2_EYE_PATTERN 0x1f2a
+#define mmDP6_DP_HBR2_EYE_PATTERN_BASE_IDX 2
+#define mmDP6_DP_VID_MSA_VBID 0x1f2b
+#define mmDP6_DP_VID_MSA_VBID_BASE_IDX 2
+#define mmDP6_DP_VID_INTERRUPT_CNTL 0x1f2c
+#define mmDP6_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
+#define mmDP6_DP_DPHY_CNTL 0x1f2d
+#define mmDP6_DP_DPHY_CNTL_BASE_IDX 2
+#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x1f2e
+#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
+#define mmDP6_DP_DPHY_SYM0 0x1f2f
+#define mmDP6_DP_DPHY_SYM0_BASE_IDX 2
+#define mmDP6_DP_DPHY_SYM1 0x1f30
+#define mmDP6_DP_DPHY_SYM1_BASE_IDX 2
+#define mmDP6_DP_DPHY_SYM2 0x1f31
+#define mmDP6_DP_DPHY_SYM2_BASE_IDX 2
+#define mmDP6_DP_DPHY_8B10B_CNTL 0x1f32
+#define mmDP6_DP_DPHY_8B10B_CNTL_BASE_IDX 2
+#define mmDP6_DP_DPHY_PRBS_CNTL 0x1f33
+#define mmDP6_DP_DPHY_PRBS_CNTL_BASE_IDX 2
+#define mmDP6_DP_DPHY_SCRAM_CNTL 0x1f34
+#define mmDP6_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
+#define mmDP6_DP_DPHY_CRC_EN 0x1f35
+#define mmDP6_DP_DPHY_CRC_EN_BASE_IDX 2
+#define mmDP6_DP_DPHY_CRC_CNTL 0x1f36
+#define mmDP6_DP_DPHY_CRC_CNTL_BASE_IDX 2
+#define mmDP6_DP_DPHY_CRC_RESULT 0x1f37
+#define mmDP6_DP_DPHY_CRC_RESULT_BASE_IDX 2
+#define mmDP6_DP_DPHY_CRC_MST_CNTL 0x1f38
+#define mmDP6_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
+#define mmDP6_DP_DPHY_CRC_MST_STATUS 0x1f39
+#define mmDP6_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
+#define mmDP6_DP_DPHY_FAST_TRAINING 0x1f3a
+#define mmDP6_DP_DPHY_FAST_TRAINING_BASE_IDX 2
+#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x1f3b
+#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
+#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x1f3c
+#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
+#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x1f3d
+#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
+#define mmDP6_DP_SEC_CNTL 0x1f41
+#define mmDP6_DP_SEC_CNTL_BASE_IDX 2
+#define mmDP6_DP_SEC_CNTL1 0x1f42
+#define mmDP6_DP_SEC_CNTL1_BASE_IDX 2
+#define mmDP6_DP_SEC_FRAMING1 0x1f43
+#define mmDP6_DP_SEC_FRAMING1_BASE_IDX 2
+#define mmDP6_DP_SEC_FRAMING2 0x1f44
+#define mmDP6_DP_SEC_FRAMING2_BASE_IDX 2
+#define mmDP6_DP_SEC_FRAMING3 0x1f45
+#define mmDP6_DP_SEC_FRAMING3_BASE_IDX 2
+#define mmDP6_DP_SEC_FRAMING4 0x1f46
+#define mmDP6_DP_SEC_FRAMING4_BASE_IDX 2
+#define mmDP6_DP_SEC_AUD_N 0x1f47
+#define mmDP6_DP_SEC_AUD_N_BASE_IDX 2
+#define mmDP6_DP_SEC_AUD_N_READBACK 0x1f48
+#define mmDP6_DP_SEC_AUD_N_READBACK_BASE_IDX 2
+#define mmDP6_DP_SEC_AUD_M 0x1f49
+#define mmDP6_DP_SEC_AUD_M_BASE_IDX 2
+#define mmDP6_DP_SEC_AUD_M_READBACK 0x1f4a
+#define mmDP6_DP_SEC_AUD_M_READBACK_BASE_IDX 2
+#define mmDP6_DP_SEC_TIMESTAMP 0x1f4b
+#define mmDP6_DP_SEC_TIMESTAMP_BASE_IDX 2
+#define mmDP6_DP_SEC_PACKET_CNTL 0x1f4c
+#define mmDP6_DP_SEC_PACKET_CNTL_BASE_IDX 2
+#define mmDP6_DP_MSE_RATE_CNTL 0x1f4d
+#define mmDP6_DP_MSE_RATE_CNTL_BASE_IDX 2
+#define mmDP6_DP_MSE_RATE_UPDATE 0x1f4f
+#define mmDP6_DP_MSE_RATE_UPDATE_BASE_IDX 2
+#define mmDP6_DP_MSE_SAT0 0x1f50
+#define mmDP6_DP_MSE_SAT0_BASE_IDX 2
+#define mmDP6_DP_MSE_SAT1 0x1f51
+#define mmDP6_DP_MSE_SAT1_BASE_IDX 2
+#define mmDP6_DP_MSE_SAT2 0x1f52
+#define mmDP6_DP_MSE_SAT2_BASE_IDX 2
+#define mmDP6_DP_MSE_SAT_UPDATE 0x1f53
+#define mmDP6_DP_MSE_SAT_UPDATE_BASE_IDX 2
+#define mmDP6_DP_MSE_LINK_TIMING 0x1f54
+#define mmDP6_DP_MSE_LINK_TIMING_BASE_IDX 2
+#define mmDP6_DP_MSE_MISC_CNTL 0x1f55
+#define mmDP6_DP_MSE_MISC_CNTL_BASE_IDX 2
+#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x1f5a
+#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
+#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0x1f5b
+#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
+#define mmDP6_DP_MSE_SAT0_STATUS 0x1f5d
+#define mmDP6_DP_MSE_SAT0_STATUS_BASE_IDX 2
+#define mmDP6_DP_MSE_SAT1_STATUS 0x1f5e
+#define mmDP6_DP_MSE_SAT1_STATUS_BASE_IDX 2
+#define mmDP6_DP_MSE_SAT2_STATUS 0x1f5f
+#define mmDP6_DP_MSE_SAT2_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcio_uniphy0_dispdec
+// base address: 0x0
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x213e
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x213f
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x2140
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x2141
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x2142
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x2143
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x2144
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x2145
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2146
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2147
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2148
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2149
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x214a
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x214b
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x214c
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x214d
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x214e
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x214f
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x2150
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x2151
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x2152
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x2153
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x2154
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x2155
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2156
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2157
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2158
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2159
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x215a
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x215b
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x215c
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x215d
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x215e
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x215f
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x2160
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x2161
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x2162
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x2163
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x2164
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x2165
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2166
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2167
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2168
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2169
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x216a
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x216b
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x216c
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x216d
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0x216e
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0x216f
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0x2170
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0x2171
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0x2172
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0x2173
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0x2174
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0x2175
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0x2176
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0x2177
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58 0x2178
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59 0x2179
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60 0x217a
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61 0x217b
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62 0x217c
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63 0x217d
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64 0x217e
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65 0x217f
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66 0x2180
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67 0x2181
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68 0x2182
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69 0x2183
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70 0x2184
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71 0x2185
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72 0x2186
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73 0x2187
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74 0x2188
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75 0x2189
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76 0x218a
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77 0x218b
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78 0x218c
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79 0x218d
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80 0x218e
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81 0x218f
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82 0x2190
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83 0x2191
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84 0x2192
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85 0x2193
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86 0x2194
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87 0x2195
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88 0x2196
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89 0x2197
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90 0x2198
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91 0x2199
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92 0x219a
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93 0x219b
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94 0x219c
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95 0x219d
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96 0x219e
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97 0x219f
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98 0x21a0
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99 0x21a1
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100 0x21a2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101 0x21a3
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102 0x21a4
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103 0x21a5
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104 0x21a6
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105 0x21a7
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106 0x21a8
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107 0x21a9
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108 0x21aa
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109 0x21ab
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110 0x21ac
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111 0x21ad
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112 0x21ae
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113 0x21af
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114 0x21b0
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115 0x21b1
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116 0x21b2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117 0x21b3
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118 0x21b4
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119 0x21b5
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120 0x21b6
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121 0x21b7
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122 0x21b8
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123 0x21b9
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124 0x21ba
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125 0x21bb
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126 0x21bc
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127 0x21bd
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128 0x21be
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129 0x21bf
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130 0x21c0
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131 0x21c1
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132 0x21c2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133 0x21c3
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134 0x21c4
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135 0x21c5
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136 0x21c6
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137 0x21c7
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138 0x21c8
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139 0x21c9
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140 0x21ca
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141 0x21cb
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142 0x21cc
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143 0x21cd
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144 0x21ce
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145 0x21cf
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146 0x21d0
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147 0x21d1
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148 0x21d2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149 0x21d3
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150 0x21d4
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151 0x21d5
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152 0x21d6
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153 0x21d7
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154 0x21d8
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155 0x21d9
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156 0x21da
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157 0x21db
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158 0x21dc
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159 0x21dd
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophycmregs0_dispdec
+// base address: 0x0
+#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1 0x213e
+#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2 0x213f
+#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3 0x2140
+#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM 0x2141
+#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT 0x2142
+#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL 0x2143
+#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP 0x2144
+#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS 0x2145
+#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL 0x2146
+#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1 0x2147
+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2 0x2148
+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3 0x2149
+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4 0x214a
+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5 0x214b
+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6 0x214c
+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7 0x214d
+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophytxregs0_dispdec
+// base address: 0x0
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0 0x215e
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0 0x215f
+#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2160
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0 0x2161
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0 0x2162
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0 0x2163
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0 0x2164
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0 0x2165
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0 0x2166
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0 0x2167
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0 0x2168
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0 0x2169
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0 0x216a
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0 0x216b
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0 0x216c
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0 0x216d
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1 0x216e
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1 0x216f
+#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2170
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1 0x2171
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1 0x2172
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1 0x2173
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1 0x2174
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1 0x2175
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1 0x2176
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1 0x2177
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1 0x2178
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1 0x2179
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1 0x217a
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1 0x217b
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1 0x217c
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1 0x217d
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2 0x217e
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2 0x217f
+#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2180
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2 0x2181
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2 0x2182
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2 0x2183
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2 0x2184
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2 0x2185
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2 0x2186
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2 0x2187
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2 0x2188
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2 0x2189
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2 0x218a
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2 0x218b
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2 0x218c
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2 0x218d
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3 0x218e
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3 0x218f
+#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2190
+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3 0x2191
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3 0x2192
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3 0x2193
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3 0x2194
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3 0x2195
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3 0x2196
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3 0x2197
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3 0x2198
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3 0x2199
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3 0x219a
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3 0x219b
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3 0x219c
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3 0x219d
+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophypllregs0_dispdec
+// base address: 0x0
+#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0 0x219e
+#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1 0x219f
+#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2 0x21a0
+#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3 0x21a1
+#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE 0x21a2
+#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE 0x21a3
+#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL 0x21a4
+#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL 0x21a5
+#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS0_VREG_CFG 0x21a7
+#define mmDC_COMBOPHYPLLREGS0_VREG_CFG_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS0_OBSERVE0 0x21a8
+#define mmDC_COMBOPHYPLLREGS0_OBSERVE0_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS0_OBSERVE1 0x21a9
+#define mmDC_COMBOPHYPLLREGS0_OBSERVE1_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS0_DFT_OUT 0x21aa
+#define mmDC_COMBOPHYPLLREGS0_DFT_OUT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcio_uniphy1_dispdec
+// base address: 0x320
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2206
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2207
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2208
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2209
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x220a
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x220b
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x220c
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x220d
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x220e
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x220f
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2210
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2211
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2212
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2213
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2214
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2215
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2216
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2217
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2218
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2219
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x221a
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x221b
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x221c
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x221d
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x221e
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x221f
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2220
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2221
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2222
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2223
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2224
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2225
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2226
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2227
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2228
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2229
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x222a
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x222b
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x222c
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x222d
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x222e
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x222f
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2230
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2231
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2232
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2233
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2234
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2235
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2236
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2237
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2238
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2239
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x223a
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x223b
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x223c
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x223d
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x223e
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x223f
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58 0x2240
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59 0x2241
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60 0x2242
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61 0x2243
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62 0x2244
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63 0x2245
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64 0x2246
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65 0x2247
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66 0x2248
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67 0x2249
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68 0x224a
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69 0x224b
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70 0x224c
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71 0x224d
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72 0x224e
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73 0x224f
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74 0x2250
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75 0x2251
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76 0x2252
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77 0x2253
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78 0x2254
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79 0x2255
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80 0x2256
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81 0x2257
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82 0x2258
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83 0x2259
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84 0x225a
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85 0x225b
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86 0x225c
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87 0x225d
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88 0x225e
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89 0x225f
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90 0x2260
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91 0x2261
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92 0x2262
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93 0x2263
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94 0x2264
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95 0x2265
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96 0x2266
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97 0x2267
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98 0x2268
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99 0x2269
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100 0x226a
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101 0x226b
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102 0x226c
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103 0x226d
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104 0x226e
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105 0x226f
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106 0x2270
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107 0x2271
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108 0x2272
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109 0x2273
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110 0x2274
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111 0x2275
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112 0x2276
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113 0x2277
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114 0x2278
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115 0x2279
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116 0x227a
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117 0x227b
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118 0x227c
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119 0x227d
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120 0x227e
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121 0x227f
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122 0x2280
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123 0x2281
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124 0x2282
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125 0x2283
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126 0x2284
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127 0x2285
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128 0x2286
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129 0x2287
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130 0x2288
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131 0x2289
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132 0x228a
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133 0x228b
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134 0x228c
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135 0x228d
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136 0x228e
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137 0x228f
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138 0x2290
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139 0x2291
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140 0x2292
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141 0x2293
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142 0x2294
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143 0x2295
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144 0x2296
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145 0x2297
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146 0x2298
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147 0x2299
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148 0x229a
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149 0x229b
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150 0x229c
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151 0x229d
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152 0x229e
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153 0x229f
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154 0x22a0
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155 0x22a1
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156 0x22a2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157 0x22a3
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158 0x22a4
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159 0x22a5
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophycmregs1_dispdec
+// base address: 0x320
+#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1 0x2206
+#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2 0x2207
+#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3 0x2208
+#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM 0x2209
+#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT 0x220a
+#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL 0x220b
+#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP 0x220c
+#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS 0x220d
+#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL 0x220e
+#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1 0x220f
+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2 0x2210
+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3 0x2211
+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4 0x2212
+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5 0x2213
+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6 0x2214
+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7 0x2215
+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophytxregs1_dispdec
+// base address: 0x320
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0 0x2226
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0 0x2227
+#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2228
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0 0x2229
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0 0x222a
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0 0x222b
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0 0x222c
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0 0x222d
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0 0x222e
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0 0x222f
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0 0x2230
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0 0x2231
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0 0x2232
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0 0x2233
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0 0x2234
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0 0x2235
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1 0x2236
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1 0x2237
+#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2238
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1 0x2239
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1 0x223a
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1 0x223b
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1 0x223c
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1 0x223d
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1 0x223e
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1 0x223f
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1 0x2240
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1 0x2241
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1 0x2242
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1 0x2243
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1 0x2244
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1 0x2245
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2 0x2246
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2 0x2247
+#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2248
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2 0x2249
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2 0x224a
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2 0x224b
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2 0x224c
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2 0x224d
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2 0x224e
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2 0x224f
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2 0x2250
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2 0x2251
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2 0x2252
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2 0x2253
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2 0x2254
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2 0x2255
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3 0x2256
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3 0x2257
+#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2258
+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3 0x2259
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3 0x225a
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3 0x225b
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3 0x225c
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3 0x225d
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3 0x225e
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3 0x225f
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3 0x2260
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3 0x2261
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3 0x2262
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3 0x2263
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3 0x2264
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3 0x2265
+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophypllregs1_dispdec
+// base address: 0x320
+#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0 0x2266
+#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1 0x2267
+#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2 0x2268
+#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3 0x2269
+#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE 0x226a
+#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE 0x226b
+#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL 0x226c
+#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL 0x226d
+#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS1_VREG_CFG 0x226f
+#define mmDC_COMBOPHYPLLREGS1_VREG_CFG_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS1_OBSERVE0 0x2270
+#define mmDC_COMBOPHYPLLREGS1_OBSERVE0_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS1_OBSERVE1 0x2271
+#define mmDC_COMBOPHYPLLREGS1_OBSERVE1_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS1_DFT_OUT 0x2272
+#define mmDC_COMBOPHYPLLREGS1_DFT_OUT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcio_uniphy2_dispdec
+// base address: 0x640
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x22ce
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x22cf
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x22d0
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x22d1
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x22d2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x22d3
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x22d4
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x22d5
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x22d6
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x22d7
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x22d8
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x22d9
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x22da
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x22db
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x22dc
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x22dd
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x22de
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x22df
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x22e0
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x22e1
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x22e2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x22e3
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x22e4
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x22e5
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x22e6
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x22e7
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x22e8
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x22e9
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x22ea
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x22eb
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x22ec
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x22ed
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x22ee
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x22ef
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x22f0
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x22f1
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x22f2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x22f3
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x22f4
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x22f5
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x22f6
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x22f7
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x22f8
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x22f9
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x22fa
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x22fb
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x22fc
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x22fd
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x22fe
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x22ff
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2300
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2301
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2302
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2303
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2304
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2305
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2306
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2307
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58 0x2308
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59 0x2309
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60 0x230a
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61 0x230b
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62 0x230c
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63 0x230d
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64 0x230e
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65 0x230f
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66 0x2310
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67 0x2311
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68 0x2312
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69 0x2313
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70 0x2314
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71 0x2315
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72 0x2316
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73 0x2317
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74 0x2318
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75 0x2319
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76 0x231a
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77 0x231b
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78 0x231c
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79 0x231d
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80 0x231e
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81 0x231f
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82 0x2320
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83 0x2321
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84 0x2322
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85 0x2323
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86 0x2324
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87 0x2325
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88 0x2326
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89 0x2327
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90 0x2328
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91 0x2329
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92 0x232a
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93 0x232b
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94 0x232c
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95 0x232d
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96 0x232e
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97 0x232f
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98 0x2330
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99 0x2331
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100 0x2332
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101 0x2333
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102 0x2334
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103 0x2335
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104 0x2336
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105 0x2337
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106 0x2338
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107 0x2339
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108 0x233a
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109 0x233b
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110 0x233c
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111 0x233d
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112 0x233e
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113 0x233f
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114 0x2340
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115 0x2341
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116 0x2342
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117 0x2343
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118 0x2344
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119 0x2345
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120 0x2346
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121 0x2347
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122 0x2348
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123 0x2349
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124 0x234a
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125 0x234b
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126 0x234c
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127 0x234d
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128 0x234e
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129 0x234f
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130 0x2350
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131 0x2351
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132 0x2352
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133 0x2353
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134 0x2354
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135 0x2355
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136 0x2356
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137 0x2357
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138 0x2358
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139 0x2359
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140 0x235a
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141 0x235b
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142 0x235c
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143 0x235d
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144 0x235e
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145 0x235f
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146 0x2360
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147 0x2361
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148 0x2362
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149 0x2363
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150 0x2364
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151 0x2365
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152 0x2366
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153 0x2367
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154 0x2368
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155 0x2369
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156 0x236a
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157 0x236b
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158 0x236c
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159 0x236d
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophycmregs2_dispdec
+// base address: 0x640
+#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1 0x22ce
+#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2 0x22cf
+#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3 0x22d0
+#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM 0x22d1
+#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT 0x22d2
+#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL 0x22d3
+#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP 0x22d4
+#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS 0x22d5
+#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL 0x22d6
+#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1 0x22d7
+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2 0x22d8
+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3 0x22d9
+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4 0x22da
+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5 0x22db
+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6 0x22dc
+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7 0x22dd
+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophytxregs2_dispdec
+// base address: 0x640
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0 0x22ee
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0 0x22ef
+#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x22f0
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0 0x22f1
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0 0x22f2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0 0x22f3
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0 0x22f4
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0 0x22f5
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0 0x22f6
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0 0x22f7
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0 0x22f8
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0 0x22f9
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0 0x22fa
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0 0x22fb
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0 0x22fc
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0 0x22fd
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1 0x22fe
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1 0x22ff
+#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2300
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1 0x2301
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1 0x2302
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1 0x2303
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1 0x2304
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1 0x2305
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1 0x2306
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1 0x2307
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1 0x2308
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1 0x2309
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1 0x230a
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1 0x230b
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1 0x230c
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1 0x230d
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2 0x230e
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2 0x230f
+#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2310
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2 0x2311
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2 0x2312
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2 0x2313
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2 0x2314
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2 0x2315
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2 0x2316
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2 0x2317
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2 0x2318
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2 0x2319
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2 0x231a
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2 0x231b
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2 0x231c
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2 0x231d
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3 0x231e
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3 0x231f
+#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2320
+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3 0x2321
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3 0x2322
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3 0x2323
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3 0x2324
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3 0x2325
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3 0x2326
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3 0x2327
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3 0x2328
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3 0x2329
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3 0x232a
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3 0x232b
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3 0x232c
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3 0x232d
+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophypllregs2_dispdec
+// base address: 0x640
+#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0 0x232e
+#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1 0x232f
+#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2 0x2330
+#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3 0x2331
+#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE 0x2332
+#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE 0x2333
+#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL 0x2334
+#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL 0x2335
+#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS2_VREG_CFG 0x2337
+#define mmDC_COMBOPHYPLLREGS2_VREG_CFG_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS2_OBSERVE0 0x2338
+#define mmDC_COMBOPHYPLLREGS2_OBSERVE0_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS2_OBSERVE1 0x2339
+#define mmDC_COMBOPHYPLLREGS2_OBSERVE1_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS2_DFT_OUT 0x233a
+#define mmDC_COMBOPHYPLLREGS2_DFT_OUT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcio_uniphy3_dispdec
+// base address: 0x960
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2396
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2397
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2398
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2399
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x239a
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x239b
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x239c
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x239d
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x239e
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x239f
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x23a0
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x23a1
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x23a2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x23a3
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x23a4
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x23a5
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x23a6
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x23a7
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x23a8
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x23a9
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x23aa
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x23ab
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x23ac
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x23ad
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x23ae
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x23af
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x23b0
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x23b1
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x23b2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x23b3
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x23b4
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x23b5
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x23b6
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x23b7
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x23b8
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x23b9
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x23ba
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x23bb
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x23bc
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x23bd
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x23be
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x23bf
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x23c0
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x23c1
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x23c2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x23c3
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x23c4
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x23c5
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x23c6
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x23c7
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x23c8
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x23c9
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x23ca
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x23cb
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x23cc
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x23cd
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x23ce
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x23cf
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58 0x23d0
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59 0x23d1
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60 0x23d2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61 0x23d3
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62 0x23d4
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63 0x23d5
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64 0x23d6
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65 0x23d7
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66 0x23d8
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67 0x23d9
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68 0x23da
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69 0x23db
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70 0x23dc
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71 0x23dd
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72 0x23de
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73 0x23df
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74 0x23e0
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75 0x23e1
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76 0x23e2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77 0x23e3
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78 0x23e4
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79 0x23e5
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80 0x23e6
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81 0x23e7
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82 0x23e8
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83 0x23e9
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84 0x23ea
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85 0x23eb
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86 0x23ec
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87 0x23ed
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88 0x23ee
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89 0x23ef
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90 0x23f0
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91 0x23f1
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92 0x23f2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93 0x23f3
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94 0x23f4
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95 0x23f5
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96 0x23f6
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97 0x23f7
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98 0x23f8
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99 0x23f9
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100 0x23fa
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101 0x23fb
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102 0x23fc
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103 0x23fd
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104 0x23fe
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105 0x23ff
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106 0x2400
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107 0x2401
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108 0x2402
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109 0x2403
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110 0x2404
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111 0x2405
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112 0x2406
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113 0x2407
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114 0x2408
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115 0x2409
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116 0x240a
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117 0x240b
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118 0x240c
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119 0x240d
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120 0x240e
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121 0x240f
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122 0x2410
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123 0x2411
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124 0x2412
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125 0x2413
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126 0x2414
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127 0x2415
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128 0x2416
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129 0x2417
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130 0x2418
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131 0x2419
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132 0x241a
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133 0x241b
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134 0x241c
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135 0x241d
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136 0x241e
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137 0x241f
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138 0x2420
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139 0x2421
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140 0x2422
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141 0x2423
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142 0x2424
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143 0x2425
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144 0x2426
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145 0x2427
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146 0x2428
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147 0x2429
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148 0x242a
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149 0x242b
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150 0x242c
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151 0x242d
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152 0x242e
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153 0x242f
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154 0x2430
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155 0x2431
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156 0x2432
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157 0x2433
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158 0x2434
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159 0x2435
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophycmregs3_dispdec
+// base address: 0x960
+#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1 0x2396
+#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2 0x2397
+#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3 0x2398
+#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM 0x2399
+#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT 0x239a
+#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL 0x239b
+#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP 0x239c
+#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS 0x239d
+#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL 0x239e
+#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1 0x239f
+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2 0x23a0
+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3 0x23a1
+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4 0x23a2
+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5 0x23a3
+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6 0x23a4
+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7 0x23a5
+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophytxregs3_dispdec
+// base address: 0x960
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0 0x23b6
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0 0x23b7
+#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x23b8
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0 0x23b9
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0 0x23ba
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0 0x23bb
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0 0x23bc
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0 0x23bd
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0 0x23be
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0 0x23bf
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0 0x23c0
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0 0x23c1
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0 0x23c2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0 0x23c3
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0 0x23c4
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0 0x23c5
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1 0x23c6
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1 0x23c7
+#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x23c8
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1 0x23c9
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1 0x23ca
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1 0x23cb
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1 0x23cc
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1 0x23cd
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1 0x23ce
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1 0x23cf
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1 0x23d0
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1 0x23d1
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1 0x23d2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1 0x23d3
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1 0x23d4
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1 0x23d5
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2 0x23d6
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2 0x23d7
+#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x23d8
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2 0x23d9
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2 0x23da
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2 0x23db
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2 0x23dc
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2 0x23dd
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2 0x23de
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2 0x23df
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2 0x23e0
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2 0x23e1
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2 0x23e2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2 0x23e3
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2 0x23e4
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2 0x23e5
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3 0x23e6
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3 0x23e7
+#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x23e8
+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3 0x23e9
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3 0x23ea
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3 0x23eb
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3 0x23ec
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3 0x23ed
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3 0x23ee
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3 0x23ef
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3 0x23f0
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3 0x23f1
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3 0x23f2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3 0x23f3
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3 0x23f4
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3 0x23f5
+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophypllregs3_dispdec
+// base address: 0x960
+#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0 0x23f6
+#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1 0x23f7
+#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2 0x23f8
+#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3 0x23f9
+#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE 0x23fa
+#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE 0x23fb
+#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL 0x23fc
+#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL 0x23fd
+#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS3_VREG_CFG 0x23ff
+#define mmDC_COMBOPHYPLLREGS3_VREG_CFG_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS3_OBSERVE0 0x2400
+#define mmDC_COMBOPHYPLLREGS3_OBSERVE0_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS3_OBSERVE1 0x2401
+#define mmDC_COMBOPHYPLLREGS3_OBSERVE1_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS3_DFT_OUT 0x2402
+#define mmDC_COMBOPHYPLLREGS3_DFT_OUT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcio_uniphy4_dispdec
+// base address: 0xc80
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x245e
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x245f
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2460
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2461
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2462
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2463
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2464
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2465
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2466
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2467
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2468
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2469
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x246a
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x246b
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x246c
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x246d
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x246e
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x246f
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2470
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2471
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2472
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2473
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2474
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2475
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2476
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2477
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2478
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2479
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x247a
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x247b
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x247c
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x247d
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x247e
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x247f
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2480
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2481
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2482
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2483
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2484
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2485
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2486
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2487
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2488
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2489
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x248a
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x248b
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x248c
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x248d
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x248e
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x248f
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2490
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2491
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2492
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2493
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2494
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2495
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2496
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2497
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58 0x2498
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59 0x2499
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60 0x249a
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61 0x249b
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62 0x249c
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63 0x249d
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64 0x249e
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65 0x249f
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66 0x24a0
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67 0x24a1
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68 0x24a2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69 0x24a3
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70 0x24a4
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71 0x24a5
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72 0x24a6
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73 0x24a7
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74 0x24a8
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75 0x24a9
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76 0x24aa
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77 0x24ab
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78 0x24ac
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79 0x24ad
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80 0x24ae
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81 0x24af
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82 0x24b0
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83 0x24b1
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84 0x24b2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85 0x24b3
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86 0x24b4
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87 0x24b5
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88 0x24b6
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89 0x24b7
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90 0x24b8
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91 0x24b9
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92 0x24ba
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93 0x24bb
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94 0x24bc
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95 0x24bd
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96 0x24be
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97 0x24bf
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98 0x24c0
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99 0x24c1
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100 0x24c2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101 0x24c3
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102 0x24c4
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103 0x24c5
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104 0x24c6
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105 0x24c7
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106 0x24c8
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107 0x24c9
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108 0x24ca
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109 0x24cb
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110 0x24cc
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111 0x24cd
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112 0x24ce
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113 0x24cf
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114 0x24d0
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115 0x24d1
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116 0x24d2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117 0x24d3
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118 0x24d4
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119 0x24d5
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120 0x24d6
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121 0x24d7
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122 0x24d8
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123 0x24d9
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124 0x24da
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125 0x24db
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126 0x24dc
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127 0x24dd
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128 0x24de
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129 0x24df
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130 0x24e0
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131 0x24e1
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132 0x24e2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133 0x24e3
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134 0x24e4
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135 0x24e5
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136 0x24e6
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137 0x24e7
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138 0x24e8
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139 0x24e9
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140 0x24ea
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141 0x24eb
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142 0x24ec
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143 0x24ed
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144 0x24ee
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145 0x24ef
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146 0x24f0
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147 0x24f1
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148 0x24f2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149 0x24f3
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150 0x24f4
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151 0x24f5
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152 0x24f6
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153 0x24f7
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154 0x24f8
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155 0x24f9
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156 0x24fa
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157 0x24fb
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158 0x24fc
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159 0x24fd
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophycmregs4_dispdec
+// base address: 0xc80
+#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1 0x245e
+#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2 0x245f
+#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3 0x2460
+#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM 0x2461
+#define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT 0x2462
+#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL 0x2463
+#define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS4_COMMON_TMDP 0x2464
+#define mmDC_COMBOPHYCMREGS4_COMMON_TMDP_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS 0x2465
+#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL 0x2466
+#define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1 0x2467
+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2 0x2468
+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3 0x2469
+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4 0x246a
+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5 0x246b
+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6 0x246c
+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7 0x246d
+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophytxregs4_dispdec
+// base address: 0xc80
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0 0x247e
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0 0x247f
+#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2480
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0 0x2481
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0 0x2482
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0 0x2483
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0 0x2484
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0 0x2485
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0 0x2486
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0 0x2487
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0 0x2488
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0 0x2489
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0 0x248a
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0 0x248b
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0 0x248c
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0 0x248d
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1 0x248e
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1 0x248f
+#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2490
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1 0x2491
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1 0x2492
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1 0x2493
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1 0x2494
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1 0x2495
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1 0x2496
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1 0x2497
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1 0x2498
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1 0x2499
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1 0x249a
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1 0x249b
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1 0x249c
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1 0x249d
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2 0x249e
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2 0x249f
+#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x24a0
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2 0x24a1
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2 0x24a2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2 0x24a3
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2 0x24a4
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2 0x24a5
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2 0x24a6
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2 0x24a7
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2 0x24a8
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2 0x24a9
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2 0x24aa
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2 0x24ab
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2 0x24ac
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2 0x24ad
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3 0x24ae
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3 0x24af
+#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x24b0
+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3 0x24b1
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3 0x24b2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3 0x24b3
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3 0x24b4
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3 0x24b5
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3 0x24b6
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3 0x24b7
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3 0x24b8
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3 0x24b9
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3 0x24ba
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3 0x24bb
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3 0x24bc
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3 0x24bd
+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophypllregs4_dispdec
+// base address: 0xc80
+#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0 0x24be
+#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1 0x24bf
+#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2 0x24c0
+#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3 0x24c1
+#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE 0x24c2
+#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE 0x24c3
+#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS4_CAL_CTRL 0x24c4
+#define mmDC_COMBOPHYPLLREGS4_CAL_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL 0x24c5
+#define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS4_VREG_CFG 0x24c7
+#define mmDC_COMBOPHYPLLREGS4_VREG_CFG_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS4_OBSERVE0 0x24c8
+#define mmDC_COMBOPHYPLLREGS4_OBSERVE0_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS4_OBSERVE1 0x24c9
+#define mmDC_COMBOPHYPLLREGS4_OBSERVE1_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS4_DFT_OUT 0x24ca
+#define mmDC_COMBOPHYPLLREGS4_DFT_OUT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcio_uniphy5_dispdec
+// base address: 0xfa0
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x2526
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x2527
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x2528
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x2529
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x252a
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x252b
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x252c
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x252d
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x252e
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x252f
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x2530
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x2531
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x2532
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x2533
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x2534
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x2535
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x2536
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x2537
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x2538
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x2539
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x253a
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x253b
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x253c
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x253d
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x253e
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x253f
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x2540
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x2541
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x2542
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x2543
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x2544
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x2545
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32 0x2546
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33 0x2547
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34 0x2548
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35 0x2549
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36 0x254a
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37 0x254b
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38 0x254c
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39 0x254d
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40 0x254e
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41 0x254f
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42 0x2550
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43 0x2551
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44 0x2552
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45 0x2553
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46 0x2554
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47 0x2555
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48 0x2556
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49 0x2557
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50 0x2558
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51 0x2559
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52 0x255a
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53 0x255b
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54 0x255c
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55 0x255d
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56 0x255e
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57 0x255f
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58 0x2560
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59 0x2561
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60 0x2562
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61 0x2563
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62 0x2564
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63 0x2565
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64 0x2566
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65 0x2567
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66 0x2568
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67 0x2569
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68 0x256a
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69 0x256b
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70 0x256c
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71 0x256d
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72 0x256e
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73 0x256f
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74 0x2570
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75 0x2571
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76 0x2572
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77 0x2573
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78 0x2574
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79 0x2575
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80 0x2576
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81 0x2577
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82 0x2578
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83 0x2579
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84 0x257a
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85 0x257b
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86 0x257c
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87 0x257d
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88 0x257e
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89 0x257f
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90 0x2580
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91 0x2581
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92 0x2582
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93 0x2583
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94 0x2584
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95 0x2585
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96 0x2586
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97 0x2587
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98 0x2588
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99 0x2589
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100 0x258a
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101 0x258b
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102 0x258c
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103 0x258d
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104 0x258e
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105 0x258f
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106 0x2590
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107 0x2591
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108 0x2592
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109 0x2593
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110 0x2594
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111 0x2595
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112 0x2596
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113 0x2597
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114 0x2598
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115 0x2599
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116 0x259a
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117 0x259b
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118 0x259c
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119 0x259d
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120 0x259e
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121 0x259f
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122 0x25a0
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123 0x25a1
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124 0x25a2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125 0x25a3
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126 0x25a4
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127 0x25a5
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128 0x25a6
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129 0x25a7
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130 0x25a8
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131 0x25a9
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132 0x25aa
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133 0x25ab
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134 0x25ac
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135 0x25ad
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136 0x25ae
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137 0x25af
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138 0x25b0
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139 0x25b1
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140 0x25b2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141 0x25b3
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142 0x25b4
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143 0x25b5
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144 0x25b6
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145 0x25b7
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146 0x25b8
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147 0x25b9
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148 0x25ba
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149 0x25bb
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150 0x25bc
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151 0x25bd
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152 0x25be
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153 0x25bf
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154 0x25c0
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155 0x25c1
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156 0x25c2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157 0x25c3
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158 0x25c4
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159 0x25c5
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophycmregs5_dispdec
+// base address: 0xfa0
+#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1 0x2526
+#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2 0x2527
+#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3 0x2528
+#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM 0x2529
+#define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT 0x252a
+#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL 0x252b
+#define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS5_COMMON_TMDP 0x252c
+#define mmDC_COMBOPHYCMREGS5_COMMON_TMDP_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS 0x252d
+#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL 0x252e
+#define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1 0x252f
+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2 0x2530
+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3 0x2531
+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4 0x2532
+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5 0x2533
+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6 0x2534
+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7 0x2535
+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophytxregs5_dispdec
+// base address: 0xfa0
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0 0x2546
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0 0x2547
+#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2548
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0 0x2549
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0 0x254a
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0 0x254b
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0 0x254c
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0 0x254d
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0 0x254e
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0 0x254f
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0 0x2550
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0 0x2551
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0 0x2552
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0 0x2553
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0 0x2554
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0 0x2555
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1 0x2556
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1 0x2557
+#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2558
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1 0x2559
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1 0x255a
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1 0x255b
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1 0x255c
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1 0x255d
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1 0x255e
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1 0x255f
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1 0x2560
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1 0x2561
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1 0x2562
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1 0x2563
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1 0x2564
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1 0x2565
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2 0x2566
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2 0x2567
+#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2568
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2 0x2569
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2 0x256a
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2 0x256b
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2 0x256c
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2 0x256d
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2 0x256e
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2 0x256f
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2 0x2570
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2 0x2571
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2 0x2572
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2 0x2573
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2 0x2574
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2 0x2575
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3 0x2576
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3 0x2577
+#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2578
+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3 0x2579
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3 0x257a
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3 0x257b
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3 0x257c
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3 0x257d
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3 0x257e
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3 0x257f
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3 0x2580
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3 0x2581
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3 0x2582
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3 0x2583
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3 0x2584
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3 0x2585
+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophypllregs5_dispdec
+// base address: 0xfa0
+#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0 0x2586
+#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1 0x2587
+#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2 0x2588
+#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3 0x2589
+#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE 0x258a
+#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE 0x258b
+#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS5_CAL_CTRL 0x258c
+#define mmDC_COMBOPHYPLLREGS5_CAL_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL 0x258d
+#define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS5_VREG_CFG 0x258f
+#define mmDC_COMBOPHYPLLREGS5_VREG_CFG_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS5_OBSERVE0 0x2590
+#define mmDC_COMBOPHYPLLREGS5_OBSERVE0_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS5_OBSERVE1 0x2591
+#define mmDC_COMBOPHYPLLREGS5_OBSERVE1_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS5_DFT_OUT 0x2592
+#define mmDC_COMBOPHYPLLREGS5_DFT_OUT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcio_uniphy6_dispdec
+// base address: 0x12c0
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x25ee
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x25ef
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x25f0
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x25f1
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x25f2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x25f3
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x25f4
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x25f5
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x25f6
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x25f7
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x25f8
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x25f9
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x25fa
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x25fb
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x25fc
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x25fd
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x25fe
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x25ff
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x2600
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x2601
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x2602
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x2603
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x2604
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x2605
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x2606
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x2607
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x2608
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x2609
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x260a
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x260b
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x260c
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x260d
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32 0x260e
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33 0x260f
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34 0x2610
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35 0x2611
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36 0x2612
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37 0x2613
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38 0x2614
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39 0x2615
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40 0x2616
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41 0x2617
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42 0x2618
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43 0x2619
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44 0x261a
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45 0x261b
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46 0x261c
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47 0x261d
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48 0x261e
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49 0x261f
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50 0x2620
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51 0x2621
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52 0x2622
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53 0x2623
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54 0x2624
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55 0x2625
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56 0x2626
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57 0x2627
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58 0x2628
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59 0x2629
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60 0x262a
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61 0x262b
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62 0x262c
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63 0x262d
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64 0x262e
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65 0x262f
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66 0x2630
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67 0x2631
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68 0x2632
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69 0x2633
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70 0x2634
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71 0x2635
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72 0x2636
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73 0x2637
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74 0x2638
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75 0x2639
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76 0x263a
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77 0x263b
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78 0x263c
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79 0x263d
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80 0x263e
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81 0x263f
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82 0x2640
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83 0x2641
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84 0x2642
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85 0x2643
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86 0x2644
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87 0x2645
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88 0x2646
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89 0x2647
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90 0x2648
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91 0x2649
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92 0x264a
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93 0x264b
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94 0x264c
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95 0x264d
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96 0x264e
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97 0x264f
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98 0x2650
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99 0x2651
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100 0x2652
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101 0x2653
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102 0x2654
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103 0x2655
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104 0x2656
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105 0x2657
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106 0x2658
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107 0x2659
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108 0x265a
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109 0x265b
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110 0x265c
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111 0x265d
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112 0x265e
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113 0x265f
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114 0x2660
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115 0x2661
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116 0x2662
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117 0x2663
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118 0x2664
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119 0x2665
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120 0x2666
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121 0x2667
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122 0x2668
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123 0x2669
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124 0x266a
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125 0x266b
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126 0x266c
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127 0x266d
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128 0x266e
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129 0x266f
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130 0x2670
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131 0x2671
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132 0x2672
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133 0x2673
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134 0x2674
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135 0x2675
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136 0x2676
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137 0x2677
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138 0x2678
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139 0x2679
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140 0x267a
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141 0x267b
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142 0x267c
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143 0x267d
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144 0x267e
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145 0x267f
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146 0x2680
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147 0x2681
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148 0x2682
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149 0x2683
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150 0x2684
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151 0x2685
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152 0x2686
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153 0x2687
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154 0x2688
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155 0x2689
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156 0x268a
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157 0x268b
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158 0x268c
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159 0x268d
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophycmregs6_dispdec
+// base address: 0x12c0
+#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE1 0x25ee
+#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE1_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE2 0x25ef
+#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE2_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE3 0x25f0
+#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE3_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM 0x25f1
+#define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT 0x25f2
+#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL 0x25f3
+#define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS6_COMMON_TMDP 0x25f4
+#define mmDC_COMBOPHYCMREGS6_COMMON_TMDP_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS 0x25f5
+#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL 0x25f6
+#define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1 0x25f7
+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2 0x25f8
+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3 0x25f9
+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4 0x25fa
+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5 0x25fb
+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6 0x25fc
+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7 0x25fd
+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophytxregs6_dispdec
+// base address: 0x12c0
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0 0x260e
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0 0x260f
+#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2610
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0 0x2611
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0 0x2612
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0 0x2613
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0 0x2614
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0 0x2615
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0 0x2616
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0 0x2617
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0 0x2618
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0 0x2619
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0 0x261a
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0 0x261b
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0 0x261c
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0 0x261d
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1 0x261e
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1 0x261f
+#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2620
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1 0x2621
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1 0x2622
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1 0x2623
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1 0x2624
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1 0x2625
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1 0x2626
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1 0x2627
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1 0x2628
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1 0x2629
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1 0x262a
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1 0x262b
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1 0x262c
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1 0x262d
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2 0x262e
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2 0x262f
+#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2630
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2 0x2631
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2 0x2632
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2 0x2633
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2 0x2634
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2 0x2635
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2 0x2636
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2 0x2637
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2 0x2638
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2 0x2639
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2 0x263a
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2 0x263b
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2 0x263c
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2 0x263d
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3 0x263e
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3 0x263f
+#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2640
+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3 0x2641
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3 0x2642
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3 0x2643
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3 0x2644
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3 0x2645
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3 0x2646
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3 0x2647
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3 0x2648
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3 0x2649
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3 0x264a
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3 0x264b
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3 0x264c
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3 0x264d
+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophypllregs6_dispdec
+// base address: 0x12c0
+#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0 0x264e
+#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1 0x264f
+#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2 0x2650
+#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3 0x2651
+#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE 0x2652
+#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE 0x2653
+#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS6_CAL_CTRL 0x2654
+#define mmDC_COMBOPHYPLLREGS6_CAL_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL 0x2655
+#define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS6_VREG_CFG 0x2657
+#define mmDC_COMBOPHYPLLREGS6_VREG_CFG_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS6_OBSERVE0 0x2658
+#define mmDC_COMBOPHYPLLREGS6_OBSERVE0_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS6_OBSERVE1 0x2659
+#define mmDC_COMBOPHYPLLREGS6_OBSERVE1_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS6_DFT_OUT 0x265a
+#define mmDC_COMBOPHYPLLREGS6_DFT_OUT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcio_uniphy8_dispdec
+// base address: 0x15e0
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0 0x26b6
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1 0x26b7
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2 0x26b8
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3 0x26b9
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4 0x26ba
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5 0x26bb
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6 0x26bc
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7 0x26bd
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8 0x26be
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9 0x26bf
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10 0x26c0
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11 0x26c1
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12 0x26c2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13 0x26c3
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14 0x26c4
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15 0x26c5
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16 0x26c6
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17 0x26c7
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18 0x26c8
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19 0x26c9
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20 0x26ca
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21 0x26cb
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22 0x26cc
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23 0x26cd
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24 0x26ce
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25 0x26cf
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26 0x26d0
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27 0x26d1
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28 0x26d2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29 0x26d3
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30 0x26d4
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31 0x26d5
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32 0x26d6
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33 0x26d7
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34 0x26d8
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35 0x26d9
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36 0x26da
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37 0x26db
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38 0x26dc
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39 0x26dd
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40 0x26de
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41 0x26df
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42 0x26e0
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43 0x26e1
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44 0x26e2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45 0x26e3
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46 0x26e4
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47 0x26e5
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48 0x26e6
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49 0x26e7
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50 0x26e8
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51 0x26e9
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52 0x26ea
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53 0x26eb
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54 0x26ec
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55 0x26ed
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56 0x26ee
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57 0x26ef
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58 0x26f0
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59 0x26f1
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60 0x26f2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61 0x26f3
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62 0x26f4
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63 0x26f5
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64 0x26f6
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65 0x26f7
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66 0x26f8
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67 0x26f9
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68 0x26fa
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69 0x26fb
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70 0x26fc
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71 0x26fd
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72 0x26fe
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73 0x26ff
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74 0x2700
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75 0x2701
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76 0x2702
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77 0x2703
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78 0x2704
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79 0x2705
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80 0x2706
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81 0x2707
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82 0x2708
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83 0x2709
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84 0x270a
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85 0x270b
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86 0x270c
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87 0x270d
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88 0x270e
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89 0x270f
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90 0x2710
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91 0x2711
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92 0x2712
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93 0x2713
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94 0x2714
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95 0x2715
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96 0x2716
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97 0x2717
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98 0x2718
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99 0x2719
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100 0x271a
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101 0x271b
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102 0x271c
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103 0x271d
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104 0x271e
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105 0x271f
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106 0x2720
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107 0x2721
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108 0x2722
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109 0x2723
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110 0x2724
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111 0x2725
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112 0x2726
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113 0x2727
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114 0x2728
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115 0x2729
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116 0x272a
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117 0x272b
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118 0x272c
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119 0x272d
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120 0x272e
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121 0x272f
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122 0x2730
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123 0x2731
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124 0x2732
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125 0x2733
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126 0x2734
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127 0x2735
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128 0x2736
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129 0x2737
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130 0x2738
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131 0x2739
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132 0x273a
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133 0x273b
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134 0x273c
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135 0x273d
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136 0x273e
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137 0x273f
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138 0x2740
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139 0x2741
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140 0x2742
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141 0x2743
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142 0x2744
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143 0x2745
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144 0x2746
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145 0x2747
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146 0x2748
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147 0x2749
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148 0x274a
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149 0x274b
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150 0x274c
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151 0x274d
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152 0x274e
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153 0x274f
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154 0x2750
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155 0x2751
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156 0x2752
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157 0x2753
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158 0x2754
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159 0x2755
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophycmregs8_dispdec
+// base address: 0x15e0
+#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE1 0x26b6
+#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE1_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE2 0x26b7
+#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE2_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE3 0x26b8
+#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE3_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM 0x26b9
+#define mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT 0x26ba
+#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL 0x26bb
+#define mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS8_COMMON_TMDP 0x26bc
+#define mmDC_COMBOPHYCMREGS8_COMMON_TMDP_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS 0x26bd
+#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL 0x26be
+#define mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1 0x26bf
+#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2 0x26c0
+#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3 0x26c1
+#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4 0x26c2
+#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5 0x26c3
+#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6 0x26c4
+#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6_BASE_IDX 2
+#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7 0x26c5
+#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophytxregs8_dispdec
+// base address: 0x15e0
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0 0x26d6
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0 0x26d7
+#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x26d8
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0 0x26d9
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0 0x26da
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0 0x26db
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0 0x26dc
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0 0x26dd
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0 0x26de
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0 0x26df
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0 0x26e0
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0 0x26e1
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0 0x26e2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0 0x26e3
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0 0x26e4
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0 0x26e5
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1 0x26e6
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1 0x26e7
+#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x26e8
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1 0x26e9
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1 0x26ea
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1 0x26eb
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1 0x26ec
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1 0x26ed
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1 0x26ee
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1 0x26ef
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1 0x26f0
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1 0x26f1
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1 0x26f2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1 0x26f3
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1 0x26f4
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1 0x26f5
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2 0x26f6
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2 0x26f7
+#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x26f8
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2 0x26f9
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2 0x26fa
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2 0x26fb
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2 0x26fc
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2 0x26fd
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2 0x26fe
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2 0x26ff
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2 0x2700
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2 0x2701
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2 0x2702
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2 0x2703
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2 0x2704
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2 0x2705
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3 0x2706
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3 0x2707
+#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2708
+#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3 0x2709
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3 0x270a
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3 0x270b
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3 0x270c
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3 0x270d
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3 0x270e
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3 0x270f
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3 0x2710
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3 0x2711
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3 0x2712
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3 0x2713
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3 0x2714
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3_BASE_IDX 2
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3 0x2715
+#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_combophypllregs8_dispdec
+// base address: 0x15e0
+#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0 0x2716
+#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1 0x2717
+#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2 0x2718
+#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3 0x2719
+#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE 0x271a
+#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE 0x271b
+#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS8_CAL_CTRL 0x271c
+#define mmDC_COMBOPHYPLLREGS8_CAL_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS8_LOOP_CTRL 0x271d
+#define mmDC_COMBOPHYPLLREGS8_LOOP_CTRL_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS8_VREG_CFG 0x271f
+#define mmDC_COMBOPHYPLLREGS8_VREG_CFG_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS8_OBSERVE0 0x2720
+#define mmDC_COMBOPHYPLLREGS8_OBSERVE0_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS8_OBSERVE1 0x2721
+#define mmDC_COMBOPHYPLLREGS8_OBSERVE1_BASE_IDX 2
+#define mmDC_COMBOPHYPLLREGS8_DFT_OUT 0x2722
+#define mmDC_COMBOPHYPLLREGS8_DFT_OUT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsi0_dispdec
+// base address: 0x0
+#define mmDSI0_DISP_DSI_CTRL 0x27be
+#define mmDSI0_DISP_DSI_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_STATUS 0x27bf
+#define mmDSI0_DISP_DSI_STATUS_BASE_IDX 2
+#define mmDSI0_DISP_DSI_VIDEO_MODE_CTRL 0x27c0
+#define mmDSI0_DISP_DSI_VIDEO_MODE_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE 0x27c1
+#define mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_BASE_IDX 2
+#define mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD 0x27c2
+#define mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_BASE_IDX 2
+#define mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD 0x27c3
+#define mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_BASE_IDX 2
+#define mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE 0x27c4
+#define mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_BASE_IDX 2
+#define mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE 0x27c5
+#define mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_BASE_IDX 2
+#define mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL 0x27c6
+#define mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_COMMAND_MODE_CTRL 0x27c7
+#define mmDSI0_DISP_DSI_COMMAND_MODE_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL 0x27c8
+#define mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL 0x27c9
+#define mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_DMA_CMD_OFFSET 0x27ca
+#define mmDSI0_DISP_DSI_DMA_CMD_OFFSET_BASE_IDX 2
+#define mmDSI0_DISP_DSI_DMA_CMD_LENGTH 0x27cb
+#define mmDSI0_DISP_DSI_DMA_CMD_LENGTH_BASE_IDX 2
+#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0 0x27cc
+#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0_BASE_IDX 2
+#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1 0x27cd
+#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1_BASE_IDX 2
+#define mmDSI0_DISP_DSI_DMA_DATA_PITCH 0x27ce
+#define mmDSI0_DISP_DSI_DMA_DATA_PITCH_BASE_IDX 2
+#define mmDSI0_DISP_DSI_DMA_DATA_WIDTH 0x27cf
+#define mmDSI0_DISP_DSI_DMA_DATA_WIDTH_BASE_IDX 2
+#define mmDSI0_DISP_DSI_DMA_DATA_HEIGHT 0x27d0
+#define mmDSI0_DISP_DSI_DMA_DATA_HEIGHT_BASE_IDX 2
+#define mmDSI0_DISP_DSI_DMA_FIFO_CTRL 0x27d1
+#define mmDSI0_DISP_DSI_DMA_FIFO_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA 0x27d2
+#define mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA_BASE_IDX 2
+#define mmDSI0_DISP_DSI_DENG_DATA_LENGTH 0x27d3
+#define mmDSI0_DISP_DSI_DENG_DATA_LENGTH_BASE_IDX 2
+#define mmDSI0_DISP_DSI_ACK_ERROR_REPORT 0x27d4
+#define mmDSI0_DISP_DSI_ACK_ERROR_REPORT_BASE_IDX 2
+#define mmDSI0_DISP_DSI_RDBK_DATA0 0x27d5
+#define mmDSI0_DISP_DSI_RDBK_DATA0_BASE_IDX 2
+#define mmDSI0_DISP_DSI_RDBK_DATA1 0x27d6
+#define mmDSI0_DISP_DSI_RDBK_DATA1_BASE_IDX 2
+#define mmDSI0_DISP_DSI_RDBK_DATA2 0x27d7
+#define mmDSI0_DISP_DSI_RDBK_DATA2_BASE_IDX 2
+#define mmDSI0_DISP_DSI_RDBK_DATA3 0x27d8
+#define mmDSI0_DISP_DSI_RDBK_DATA3_BASE_IDX 2
+#define mmDSI0_DISP_DSI_RDBK_DATATYPE0 0x27d9
+#define mmDSI0_DISP_DSI_RDBK_DATATYPE0_BASE_IDX 2
+#define mmDSI0_DISP_DSI_RDBK_DATATYPE1 0x27da
+#define mmDSI0_DISP_DSI_RDBK_DATATYPE1_BASE_IDX 2
+#define mmDSI0_DISP_DSI_TRIG_CTRL 0x27db
+#define mmDSI0_DISP_DSI_TRIG_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_EXT_MUX 0x27dc
+#define mmDSI0_DISP_DSI_EXT_MUX_BASE_IDX 2
+#define mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL 0x27dd
+#define mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER 0x27de
+#define mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_BASE_IDX 2
+#define mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER 0x27df
+#define mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_BASE_IDX 2
+#define mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER 0x27e0
+#define mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_BASE_IDX 2
+#define mmDSI0_DISP_DSI_RESET_SW_TRIGGER 0x27e1
+#define mmDSI0_DISP_DSI_RESET_SW_TRIGGER_BASE_IDX 2
+#define mmDSI0_DISP_DSI_EXT_RESET 0x27e2
+#define mmDSI0_DISP_DSI_EXT_RESET_BASE_IDX 2
+#define mmDSI0_DISP_DSI_LANE_CRC_HS_MODE 0x27e3
+#define mmDSI0_DISP_DSI_LANE_CRC_HS_MODE_BASE_IDX 2
+#define mmDSI0_DISP_DSI_LANE_CRC_LP_MODE 0x27e4
+#define mmDSI0_DISP_DSI_LANE_CRC_LP_MODE_BASE_IDX 2
+#define mmDSI0_DISP_DSI_LANE_CRC_CTRL 0x27e5
+#define mmDSI0_DISP_DSI_LANE_CRC_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_PIXEL_CRC_CTRL 0x27e6
+#define mmDSI0_DISP_DSI_PIXEL_CRC_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_LANE_CTRL 0x27e7
+#define mmDSI0_DISP_DSI_LANE_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_DLN0_PHY_ERROR 0x27e8
+#define mmDSI0_DISP_DSI_DLN0_PHY_ERROR_BASE_IDX 2
+#define mmDSI0_DISP_DSI_LP_TIMER_CTRL 0x27e9
+#define mmDSI0_DISP_DSI_LP_TIMER_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_HS_TIMER_CTRL 0x27ea
+#define mmDSI0_DISP_DSI_HS_TIMER_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_TIMEOUT_STATUS 0x27eb
+#define mmDSI0_DISP_DSI_TIMEOUT_STATUS_BASE_IDX 2
+#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL 0x27ec
+#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2 0x27ed
+#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2_BASE_IDX 2
+#define mmDSI0_DISP_DSI_EOT_PACKET 0x27ee
+#define mmDSI0_DISP_DSI_EOT_PACKET_BASE_IDX 2
+#define mmDSI0_DISP_DSI_EOT_PACKET_CTRL 0x27ef
+#define mmDSI0_DISP_DSI_EOT_PACKET_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER 0x27f0
+#define mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER_BASE_IDX 2
+#define mmDSI0_DISP_DSI_MIPI_BIST_CTRL 0x27f1
+#define mmDSI0_DISP_DSI_MIPI_BIST_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE 0x27f2
+#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE_BASE_IDX 2
+#define mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE 0x27f3
+#define mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE_BASE_IDX 2
+#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG 0x27f4
+#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG_BASE_IDX 2
+#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL 0x27f5
+#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT 0x27f6
+#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT_BASE_IDX 2
+#define mmDSI0_DISP_DSI_MIPI_BIST_START 0x27f7
+#define mmDSI0_DISP_DSI_MIPI_BIST_START_BASE_IDX 2
+#define mmDSI0_DISP_DSI_MIPI_BIST_STATUS 0x27f8
+#define mmDSI0_DISP_DSI_MIPI_BIST_STATUS_BASE_IDX 2
+#define mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK 0x27f9
+#define mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK_BASE_IDX 2
+#define mmDSI0_DISP_DSI_INTERRUPT_CTRL 0x27fa
+#define mmDSI0_DISP_DSI_INTERRUPT_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_CLK_CTRL 0x27fb
+#define mmDSI0_DISP_DSI_CLK_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_CLK_STATUS 0x27fc
+#define mmDSI0_DISP_DSI_CLK_STATUS_BASE_IDX 2
+#define mmDSI0_DISP_DSI_DENG_FIFO_STATUS 0x27fd
+#define mmDSI0_DISP_DSI_DENG_FIFO_STATUS_BASE_IDX 2
+#define mmDSI0_DISP_DSI_DENG_FIFO_CTRL 0x27fe
+#define mmDSI0_DISP_DSI_DENG_FIFO_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_CMD_FIFO_DATA 0x27ff
+#define mmDSI0_DISP_DSI_CMD_FIFO_DATA_BASE_IDX 2
+#define mmDSI0_DISP_DSI_CMD_FIFO_CTRL 0x2800
+#define mmDSI0_DISP_DSI_CMD_FIFO_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_TE_CTRL 0x2801
+#define mmDSI0_DISP_DSI_TE_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_LANE_STATUS 0x2805
+#define mmDSI0_DISP_DSI_LANE_STATUS_BASE_IDX 2
+#define mmDSI0_DISP_DSI_PERF_CTRL 0x2806
+#define mmDSI0_DISP_DSI_PERF_CTRL_BASE_IDX 2
+#define mmDSI0_DISP_DSI_HSYNC_LENGTH 0x2807
+#define mmDSI0_DISP_DSI_HSYNC_LENGTH_BASE_IDX 2
+#define mmDSI0_DISP_DSI_RDBK_NUM 0x2808
+#define mmDSI0_DISP_DSI_RDBK_NUM_BASE_IDX 2
+#define mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL 0x2809
+#define mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsi1_dispdec
+// base address: 0x400
+#define mmDSI1_DISP_DSI_CTRL 0x28be
+#define mmDSI1_DISP_DSI_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_STATUS 0x28bf
+#define mmDSI1_DISP_DSI_STATUS_BASE_IDX 2
+#define mmDSI1_DISP_DSI_VIDEO_MODE_CTRL 0x28c0
+#define mmDSI1_DISP_DSI_VIDEO_MODE_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE 0x28c1
+#define mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_BASE_IDX 2
+#define mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD 0x28c2
+#define mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_BASE_IDX 2
+#define mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD 0x28c3
+#define mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_BASE_IDX 2
+#define mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE 0x28c4
+#define mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_BASE_IDX 2
+#define mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE 0x28c5
+#define mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_BASE_IDX 2
+#define mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL 0x28c6
+#define mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_COMMAND_MODE_CTRL 0x28c7
+#define mmDSI1_DISP_DSI_COMMAND_MODE_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL 0x28c8
+#define mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL 0x28c9
+#define mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_DMA_CMD_OFFSET 0x28ca
+#define mmDSI1_DISP_DSI_DMA_CMD_OFFSET_BASE_IDX 2
+#define mmDSI1_DISP_DSI_DMA_CMD_LENGTH 0x28cb
+#define mmDSI1_DISP_DSI_DMA_CMD_LENGTH_BASE_IDX 2
+#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0 0x28cc
+#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0_BASE_IDX 2
+#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1 0x28cd
+#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1_BASE_IDX 2
+#define mmDSI1_DISP_DSI_DMA_DATA_PITCH 0x28ce
+#define mmDSI1_DISP_DSI_DMA_DATA_PITCH_BASE_IDX 2
+#define mmDSI1_DISP_DSI_DMA_DATA_WIDTH 0x28cf
+#define mmDSI1_DISP_DSI_DMA_DATA_WIDTH_BASE_IDX 2
+#define mmDSI1_DISP_DSI_DMA_DATA_HEIGHT 0x28d0
+#define mmDSI1_DISP_DSI_DMA_DATA_HEIGHT_BASE_IDX 2
+#define mmDSI1_DISP_DSI_DMA_FIFO_CTRL 0x28d1
+#define mmDSI1_DISP_DSI_DMA_FIFO_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA 0x28d2
+#define mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA_BASE_IDX 2
+#define mmDSI1_DISP_DSI_DENG_DATA_LENGTH 0x28d3
+#define mmDSI1_DISP_DSI_DENG_DATA_LENGTH_BASE_IDX 2
+#define mmDSI1_DISP_DSI_ACK_ERROR_REPORT 0x28d4
+#define mmDSI1_DISP_DSI_ACK_ERROR_REPORT_BASE_IDX 2
+#define mmDSI1_DISP_DSI_RDBK_DATA0 0x28d5
+#define mmDSI1_DISP_DSI_RDBK_DATA0_BASE_IDX 2
+#define mmDSI1_DISP_DSI_RDBK_DATA1 0x28d6
+#define mmDSI1_DISP_DSI_RDBK_DATA1_BASE_IDX 2
+#define mmDSI1_DISP_DSI_RDBK_DATA2 0x28d7
+#define mmDSI1_DISP_DSI_RDBK_DATA2_BASE_IDX 2
+#define mmDSI1_DISP_DSI_RDBK_DATA3 0x28d8
+#define mmDSI1_DISP_DSI_RDBK_DATA3_BASE_IDX 2
+#define mmDSI1_DISP_DSI_RDBK_DATATYPE0 0x28d9
+#define mmDSI1_DISP_DSI_RDBK_DATATYPE0_BASE_IDX 2
+#define mmDSI1_DISP_DSI_RDBK_DATATYPE1 0x28da
+#define mmDSI1_DISP_DSI_RDBK_DATATYPE1_BASE_IDX 2
+#define mmDSI1_DISP_DSI_TRIG_CTRL 0x28db
+#define mmDSI1_DISP_DSI_TRIG_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_EXT_MUX 0x28dc
+#define mmDSI1_DISP_DSI_EXT_MUX_BASE_IDX 2
+#define mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL 0x28dd
+#define mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER 0x28de
+#define mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_BASE_IDX 2
+#define mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER 0x28df
+#define mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_BASE_IDX 2
+#define mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER 0x28e0
+#define mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_BASE_IDX 2
+#define mmDSI1_DISP_DSI_RESET_SW_TRIGGER 0x28e1
+#define mmDSI1_DISP_DSI_RESET_SW_TRIGGER_BASE_IDX 2
+#define mmDSI1_DISP_DSI_EXT_RESET 0x28e2
+#define mmDSI1_DISP_DSI_EXT_RESET_BASE_IDX 2
+#define mmDSI1_DISP_DSI_LANE_CRC_HS_MODE 0x28e3
+#define mmDSI1_DISP_DSI_LANE_CRC_HS_MODE_BASE_IDX 2
+#define mmDSI1_DISP_DSI_LANE_CRC_LP_MODE 0x28e4
+#define mmDSI1_DISP_DSI_LANE_CRC_LP_MODE_BASE_IDX 2
+#define mmDSI1_DISP_DSI_LANE_CRC_CTRL 0x28e5
+#define mmDSI1_DISP_DSI_LANE_CRC_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_PIXEL_CRC_CTRL 0x28e6
+#define mmDSI1_DISP_DSI_PIXEL_CRC_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_LANE_CTRL 0x28e7
+#define mmDSI1_DISP_DSI_LANE_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_DLN0_PHY_ERROR 0x28e8
+#define mmDSI1_DISP_DSI_DLN0_PHY_ERROR_BASE_IDX 2
+#define mmDSI1_DISP_DSI_LP_TIMER_CTRL 0x28e9
+#define mmDSI1_DISP_DSI_LP_TIMER_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_HS_TIMER_CTRL 0x28ea
+#define mmDSI1_DISP_DSI_HS_TIMER_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_TIMEOUT_STATUS 0x28eb
+#define mmDSI1_DISP_DSI_TIMEOUT_STATUS_BASE_IDX 2
+#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL 0x28ec
+#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2 0x28ed
+#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2_BASE_IDX 2
+#define mmDSI1_DISP_DSI_EOT_PACKET 0x28ee
+#define mmDSI1_DISP_DSI_EOT_PACKET_BASE_IDX 2
+#define mmDSI1_DISP_DSI_EOT_PACKET_CTRL 0x28ef
+#define mmDSI1_DISP_DSI_EOT_PACKET_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER 0x28f0
+#define mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER_BASE_IDX 2
+#define mmDSI1_DISP_DSI_MIPI_BIST_CTRL 0x28f1
+#define mmDSI1_DISP_DSI_MIPI_BIST_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE 0x28f2
+#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE_BASE_IDX 2
+#define mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE 0x28f3
+#define mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE_BASE_IDX 2
+#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG 0x28f4
+#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG_BASE_IDX 2
+#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL 0x28f5
+#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT 0x28f6
+#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT_BASE_IDX 2
+#define mmDSI1_DISP_DSI_MIPI_BIST_START 0x28f7
+#define mmDSI1_DISP_DSI_MIPI_BIST_START_BASE_IDX 2
+#define mmDSI1_DISP_DSI_MIPI_BIST_STATUS 0x28f8
+#define mmDSI1_DISP_DSI_MIPI_BIST_STATUS_BASE_IDX 2
+#define mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK 0x28f9
+#define mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK_BASE_IDX 2
+#define mmDSI1_DISP_DSI_INTERRUPT_CTRL 0x28fa
+#define mmDSI1_DISP_DSI_INTERRUPT_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_CLK_CTRL 0x28fb
+#define mmDSI1_DISP_DSI_CLK_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_CLK_STATUS 0x28fc
+#define mmDSI1_DISP_DSI_CLK_STATUS_BASE_IDX 2
+#define mmDSI1_DISP_DSI_DENG_FIFO_STATUS 0x28fd
+#define mmDSI1_DISP_DSI_DENG_FIFO_STATUS_BASE_IDX 2
+#define mmDSI1_DISP_DSI_DENG_FIFO_CTRL 0x28fe
+#define mmDSI1_DISP_DSI_DENG_FIFO_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_CMD_FIFO_DATA 0x28ff
+#define mmDSI1_DISP_DSI_CMD_FIFO_DATA_BASE_IDX 2
+#define mmDSI1_DISP_DSI_CMD_FIFO_CTRL 0x2900
+#define mmDSI1_DISP_DSI_CMD_FIFO_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_TE_CTRL 0x2901
+#define mmDSI1_DISP_DSI_TE_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_LANE_STATUS 0x2905
+#define mmDSI1_DISP_DSI_LANE_STATUS_BASE_IDX 2
+#define mmDSI1_DISP_DSI_PERF_CTRL 0x2906
+#define mmDSI1_DISP_DSI_PERF_CTRL_BASE_IDX 2
+#define mmDSI1_DISP_DSI_HSYNC_LENGTH 0x2907
+#define mmDSI1_DISP_DSI_HSYNC_LENGTH_BASE_IDX 2
+#define mmDSI1_DISP_DSI_RDBK_NUM 0x2908
+#define mmDSI1_DISP_DSI_RDBK_NUM_BASE_IDX 2
+#define mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL 0x2909
+#define mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dprx_sd0_dispdec
+// base address: 0x0
+#define mmDPRX_SD0_DPRX_SD_CONTROL 0x29be
+#define mmDPRX_SD0_DPRX_SD_CONTROL_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_STREAM_ENABLE 0x29bf
+#define mmDPRX_SD0_DPRX_SD_STREAM_ENABLE_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_MSA0 0x29c0
+#define mmDPRX_SD0_DPRX_SD_MSA0_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_MSA1 0x29c1
+#define mmDPRX_SD0_DPRX_SD_MSA1_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_MSA2 0x29c2
+#define mmDPRX_SD0_DPRX_SD_MSA2_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_MSA3 0x29c3
+#define mmDPRX_SD0_DPRX_SD_MSA3_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_MSA4 0x29c4
+#define mmDPRX_SD0_DPRX_SD_MSA4_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_MSA5 0x29c5
+#define mmDPRX_SD0_DPRX_SD_MSA5_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_MSA6 0x29c6
+#define mmDPRX_SD0_DPRX_SD_MSA6_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_MSA7 0x29c7
+#define mmDPRX_SD0_DPRX_SD_MSA7_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_MSA8 0x29c8
+#define mmDPRX_SD0_DPRX_SD_MSA8_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_VBID 0x29c9
+#define mmDPRX_SD0_DPRX_SD_VBID_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_CURRENT_LINE 0x29ca
+#define mmDPRX_SD0_DPRX_SD_CURRENT_LINE_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT 0x29cb
+#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE 0x29cc
+#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_MSE_SAT 0x29ce
+#define mmDPRX_SD0_DPRX_SD_MSE_SAT_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE 0x29cf
+#define mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE 0x29d0
+#define mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_V_PARAMETER 0x29d1
+#define mmDPRX_SD0_DPRX_SD_V_PARAMETER_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT 0x29d2
+#define mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS 0x29d3
+#define mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED 0x29d4
+#define mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS 0x29d5
+#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL 0x29d6
+#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS 0x29d7
+#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL 0x29d8
+#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR 0x29d9
+#define mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE 0x29da
+#define mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR 0x29db
+#define mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED 0x29dc
+#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR 0x29dd
+#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR 0x29de
+#define mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR 0x29df
+#define mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH 0x29e1
+#define mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_SDP_STEER 0x29e3
+#define mmDPRX_SD0_DPRX_SD_SDP_STEER_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS 0x29e4
+#define mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_SDP_LEVEL 0x29e5
+#define mmDPRX_SD0_DPRX_SD_SDP_LEVEL_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_SDP_DATA 0x29e6
+#define mmDPRX_SD0_DPRX_SD_SDP_DATA_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_SDP_ERROR 0x29e7
+#define mmDPRX_SD0_DPRX_SD_SDP_ERROR_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_AUDIO_HEADER 0x29e8
+#define mmDPRX_SD0_DPRX_SD_AUDIO_HEADER_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR 0x29e9
+#define mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_SDP_CONTROL 0x29ea
+#define mmDPRX_SD0_DPRX_SD_SDP_CONTROL_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED 0x29eb
+#define mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED 0x29ec
+#define mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_BS_COUNTER 0x29ed
+#define mmDPRX_SD0_DPRX_SD_BS_COUNTER_BASE_IDX 2
+#define mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED 0x29ee
+#define mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dprx_sd1_dispdec
+// base address: 0x180
+#define mmDPRX_SD1_DPRX_SD_CONTROL 0x2a1e
+#define mmDPRX_SD1_DPRX_SD_CONTROL_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_STREAM_ENABLE 0x2a1f
+#define mmDPRX_SD1_DPRX_SD_STREAM_ENABLE_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_MSA0 0x2a20
+#define mmDPRX_SD1_DPRX_SD_MSA0_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_MSA1 0x2a21
+#define mmDPRX_SD1_DPRX_SD_MSA1_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_MSA2 0x2a22
+#define mmDPRX_SD1_DPRX_SD_MSA2_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_MSA3 0x2a23
+#define mmDPRX_SD1_DPRX_SD_MSA3_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_MSA4 0x2a24
+#define mmDPRX_SD1_DPRX_SD_MSA4_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_MSA5 0x2a25
+#define mmDPRX_SD1_DPRX_SD_MSA5_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_MSA6 0x2a26
+#define mmDPRX_SD1_DPRX_SD_MSA6_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_MSA7 0x2a27
+#define mmDPRX_SD1_DPRX_SD_MSA7_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_MSA8 0x2a28
+#define mmDPRX_SD1_DPRX_SD_MSA8_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_VBID 0x2a29
+#define mmDPRX_SD1_DPRX_SD_VBID_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_CURRENT_LINE 0x2a2a
+#define mmDPRX_SD1_DPRX_SD_CURRENT_LINE_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT 0x2a2b
+#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE 0x2a2c
+#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_MSE_SAT 0x2a2e
+#define mmDPRX_SD1_DPRX_SD_MSE_SAT_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE 0x2a2f
+#define mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE 0x2a30
+#define mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_V_PARAMETER 0x2a31
+#define mmDPRX_SD1_DPRX_SD_V_PARAMETER_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT 0x2a32
+#define mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS 0x2a33
+#define mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED 0x2a34
+#define mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS 0x2a35
+#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL 0x2a36
+#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS 0x2a37
+#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL 0x2a38
+#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR 0x2a39
+#define mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE 0x2a3a
+#define mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR 0x2a3b
+#define mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED 0x2a3c
+#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR 0x2a3d
+#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR 0x2a3e
+#define mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR 0x2a3f
+#define mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH 0x2a41
+#define mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_SDP_STEER 0x2a43
+#define mmDPRX_SD1_DPRX_SD_SDP_STEER_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS 0x2a44
+#define mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_SDP_LEVEL 0x2a45
+#define mmDPRX_SD1_DPRX_SD_SDP_LEVEL_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_SDP_DATA 0x2a46
+#define mmDPRX_SD1_DPRX_SD_SDP_DATA_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_SDP_ERROR 0x2a47
+#define mmDPRX_SD1_DPRX_SD_SDP_ERROR_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_AUDIO_HEADER 0x2a48
+#define mmDPRX_SD1_DPRX_SD_AUDIO_HEADER_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR 0x2a49
+#define mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_SDP_CONTROL 0x2a4a
+#define mmDPRX_SD1_DPRX_SD_SDP_CONTROL_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED 0x2a4b
+#define mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED 0x2a4c
+#define mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_BS_COUNTER 0x2a4d
+#define mmDPRX_SD1_DPRX_SD_BS_COUNTER_BASE_IDX 2
+#define mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED 0x2a4e
+#define mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_perfmon10_dispdec
+// base address: 0xacf8
+#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x2b5e
+#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x2b5f
+#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x2b60
+#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON10_PERFMON_CNTL 0x2b61
+#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON10_PERFMON_CNTL2 0x2b62
+#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x2b63
+#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x2b64
+#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON10_PERFMON_HI 0x2b65
+#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON10_PERFMON_LOW 0x2b66
+#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dc_zcalregs_dispdec
+// base address: 0x0
+#define mmCOMP_EN_CTL 0x2d96
+#define mmCOMP_EN_CTL_BASE_IDX 2
+#define mmCOMP_EN_DFX 0x2d97
+#define mmCOMP_EN_DFX_BASE_IDX 2
+#define mmZCAL_FUSES 0x2d98
+#define mmZCAL_FUSES_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
+// base address: 0x48
+//#define mmVGA_dispdec_VGA_MEM_WRITE_PAGE_ADDR 0x0012
+
+
+// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
+// base address: 0x4c
+//#define mmVGA_dispdec_VGA_MEM_READ_PAGE_ADDR 0x0014
+
+
+// addressBlock: dce_dc_dispdec[948..986]
+// base address: 0x3b4
+//#define mmVGA_CRTC8_IDX 0x002d
+//#define mmVGA_CRTC8_DATA 0x002d
+//#define mmVGA_GENFC_WT 0x002e
+//#define mmVGA_GENS1 0x002e
+//#define mmVGA_ATTRDW 0x0030
+//#define mmVGA_ATTRX 0x0030
+//#define mmVGA_ATTRDR 0x0030
+//#define mmVGA_GENMO_WT 0x0030
+//#define mmVGA_GENS0 0x0030
+//#define mmVGA_GENENB 0x0030
+//#define mmVGA_SEQ8_IDX 0x0031
+//#define mmVGA_SEQ8_DATA 0x0031
+//#define mmVGA_DAC_MASK 0x0031
+//#define mmVGA_DAC_R_INDEX 0x0031
+//#define mmVGA_DAC_W_INDEX 0x0032
+//#define mmVGA_DAC_DATA 0x0032
+//#define mmVGA_GENFC_RD 0x0032
+//#define mmVGA_GENMO_RD 0x0033
+//#define mmVGA_GRPH8_IDX 0x0033
+//#define mmVGA_GRPH8_DATA 0x0033
+//#define mmVGA_CRTC8_IDX_1 0x0035
+//#define mmVGA_CRTC8_DATA_1 0x0035
+//#define mmVGA_GENFC_WT_1 0x0036
+//#define mmVGA_GENS1_1 0x0036
+
+
+// addressBlock: dce_dc_azdec
+// base address: 0x0
+#define mmCORB_WRITE_POINTER 0x0000
+#define mmCORB_WRITE_POINTER_BASE_IDX 0
+#define mmCORB_READ_POINTER 0x0000
+#define mmCORB_READ_POINTER_BASE_IDX 0
+#define mmCORB_CONTROL 0x0001
+#define mmCORB_CONTROL_BASE_IDX 0
+#define mmCORB_STATUS 0x0001
+#define mmCORB_STATUS_BASE_IDX 0
+#define mmCORB_SIZE 0x0001
+#define mmCORB_SIZE_BASE_IDX 0
+#define mmRIRB_LOWER_BASE_ADDRESS 0x0002
+#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0
+#define mmRIRB_UPPER_BASE_ADDRESS 0x0003
+#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0
+#define mmRIRB_WRITE_POINTER 0x0004
+#define mmRIRB_WRITE_POINTER_BASE_IDX 0
+#define mmRESPONSE_INTERRUPT_COUNT 0x0004
+#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0
+#define mmRIRB_CONTROL 0x0005
+#define mmRIRB_CONTROL_BASE_IDX 0
+#define mmRIRB_STATUS 0x0005
+#define mmRIRB_STATUS_BASE_IDX 0
+#define mmRIRB_SIZE 0x0005
+#define mmRIRB_SIZE_BASE_IDX 0
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
+#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
+#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
+#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
+#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
+#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007
+#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0
+#define mmIMMEDIATE_COMMAND_STATUS 0x0008
+#define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0
+#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a
+#define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0
+#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b
+#define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0
+#define mmWALL_CLOCK_COUNTER_ALIAS 0x074c
+#define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1
+
+
+// addressBlock: dce_dc_azstream0_azdec
+// base address: 0x0
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+
+
+// addressBlock: dce_dc_azstream1_azdec
+// base address: 0x20
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+
+
+// addressBlock: dce_dc_azstream2_azdec
+// base address: 0x40
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+
+
+// addressBlock: dce_dc_azstream3_azdec
+// base address: 0x60
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+
+
+// addressBlock: dce_dc_azstream4_azdec
+// base address: 0x80
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+
+
+// addressBlock: dce_dc_azstream5_azdec
+// base address: 0xa0
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+
+
+// addressBlock: dce_dc_azstream6_azdec
+// base address: 0xc0
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+
+
+// addressBlock: dce_dc_azstream7_azdec
+// base address: 0xe0
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+
+
+// addressBlock: azf0stream0_streamind
+// base address: 0x0
+#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream1_streamind
+// base address: 0x0
+#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream2_streamind
+// base address: 0x0
+#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream3_streamind
+// base address: 0x0
+#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream4_streamind
+// base address: 0x0
+#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream5_streamind
+// base address: 0x0
+#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream6_streamind
+// base address: 0x0
+#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream7_streamind
+// base address: 0x0
+#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream8_streamind
+// base address: 0x0
+#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream9_streamind
+// base address: 0x0
+#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream10_streamind
+// base address: 0x0
+#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream11_streamind
+// base address: 0x0
+#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream12_streamind
+// base address: 0x0
+#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream13_streamind
+// base address: 0x0
+#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream14_streamind
+// base address: 0x0
+#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream15_streamind
+// base address: 0x0
+#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0endpoint0_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+
+
+// addressBlock: azf0endpoint1_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+
+
+// addressBlock: azf0endpoint2_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+
+
+// addressBlock: azf0endpoint3_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+
+
+// addressBlock: azf0endpoint4_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+
+
+// addressBlock: azf0endpoint5_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+
+
+// addressBlock: azf0endpoint6_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+
+
+// addressBlock: azf0endpoint7_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+
+
+// addressBlock: azf0inputendpoint0_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+
+
+// addressBlock: azf0inputendpoint1_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+
+
+// addressBlock: azf0inputendpoint2_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+
+
+// addressBlock: azf0inputendpoint3_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+
+
+// addressBlock: azf0inputendpoint4_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+
+
+// addressBlock: azf0inputendpoint5_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+
+
+// addressBlock: azf0inputendpoint6_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+
+
+// addressBlock: azf0inputendpoint7_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+
+
+// addressBlock: f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e
+#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792
+#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c
+
+
+// addressBlock: descriptorind
+// base address: 0x0
+#define ixAUDIO_DESCRIPTOR0 0x0001
+#define ixAUDIO_DESCRIPTOR1 0x0002
+#define ixAUDIO_DESCRIPTOR2 0x0003
+#define ixAUDIO_DESCRIPTOR3 0x0004
+#define ixAUDIO_DESCRIPTOR4 0x0005
+#define ixAUDIO_DESCRIPTOR5 0x0006
+#define ixAUDIO_DESCRIPTOR6 0x0007
+#define ixAUDIO_DESCRIPTOR7 0x0008
+#define ixAUDIO_DESCRIPTOR8 0x0009
+#define ixAUDIO_DESCRIPTOR9 0x000a
+#define ixAUDIO_DESCRIPTOR10 0x000b
+#define ixAUDIO_DESCRIPTOR11 0x000c
+#define ixAUDIO_DESCRIPTOR12 0x000d
+#define ixAUDIO_DESCRIPTOR13 0x000e
+
+
+// addressBlock: sinkinfoind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004
+#define ixSINK_DESCRIPTION0 0x0005
+#define ixSINK_DESCRIPTION1 0x0006
+#define ixSINK_DESCRIPTION2 0x0007
+#define ixSINK_DESCRIPTION3 0x0008
+#define ixSINK_DESCRIPTION4 0x0009
+#define ixSINK_DESCRIPTION5 0x000a
+#define ixSINK_DESCRIPTION6 0x000b
+#define ixSINK_DESCRIPTION7 0x000c
+#define ixSINK_DESCRIPTION8 0x000d
+#define ixSINK_DESCRIPTION9 0x000e
+#define ixSINK_DESCRIPTION10 0x000f
+#define ixSINK_DESCRIPTION11 0x0010
+#define ixSINK_DESCRIPTION12 0x0011
+#define ixSINK_DESCRIPTION13 0x0012
+#define ixSINK_DESCRIPTION14 0x0013
+#define ixSINK_DESCRIPTION15 0x0014
+#define ixSINK_DESCRIPTION16 0x0015
+#define ixSINK_DESCRIPTION17 0x0016
+
+
+// addressBlock: azinputcrc0resultind
+// base address: 0x0
+#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000
+#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001
+#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002
+#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003
+#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004
+#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005
+#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006
+#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007
+
+
+// addressBlock: azinputcrc1resultind
+// base address: 0x0
+#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000
+#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001
+#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002
+#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003
+#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004
+#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005
+#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006
+#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007
+
+
+// addressBlock: azcrc0resultind
+// base address: 0x0
+#define ixAZALIA_CRC0_CHANNEL0 0x0000
+#define ixAZALIA_CRC0_CHANNEL1 0x0001
+#define ixAZALIA_CRC0_CHANNEL2 0x0002
+#define ixAZALIA_CRC0_CHANNEL3 0x0003
+#define ixAZALIA_CRC0_CHANNEL4 0x0004
+#define ixAZALIA_CRC0_CHANNEL5 0x0005
+#define ixAZALIA_CRC0_CHANNEL6 0x0006
+#define ixAZALIA_CRC0_CHANNEL7 0x0007
+
+
+// addressBlock: azcrc1resultind
+// base address: 0x0
+#define ixAZALIA_CRC1_CHANNEL0 0x0000
+#define ixAZALIA_CRC1_CHANNEL1 0x0001
+#define ixAZALIA_CRC1_CHANNEL2 0x0002
+#define ixAZALIA_CRC1_CHANNEL3 0x0003
+#define ixAZALIA_CRC1_CHANNEL4 0x0004
+#define ixAZALIA_CRC1_CHANNEL5 0x0005
+#define ixAZALIA_CRC1_CHANNEL6 0x0006
+#define ixAZALIA_CRC1_CHANNEL7 0x0007
+
+
+// addressBlock: vgaseqind
+// base address: 0x0
+#define ixSEQ00 0x0000
+#define ixSEQ01 0x0001
+#define ixSEQ02 0x0002
+#define ixSEQ03 0x0003
+#define ixSEQ04 0x0004
+
+
+// addressBlock: vgacrtind
+// base address: 0x0
+#define ixCRT00 0x0000
+#define ixCRT01 0x0001
+#define ixCRT02 0x0002
+#define ixCRT03 0x0003
+#define ixCRT04 0x0004
+#define ixCRT05 0x0005
+#define ixCRT06 0x0006
+#define ixCRT07 0x0007
+#define ixCRT08 0x0008
+#define ixCRT09 0x0009
+#define ixCRT0A 0x000a
+#define ixCRT0B 0x000b
+#define ixCRT0C 0x000c
+#define ixCRT0D 0x000d
+#define ixCRT0E 0x000e
+#define ixCRT0F 0x000f
+#define ixCRT10 0x0010
+#define ixCRT11 0x0011
+#define ixCRT12 0x0012
+#define ixCRT13 0x0013
+#define ixCRT14 0x0014
+#define ixCRT15 0x0015
+#define ixCRT16 0x0016
+#define ixCRT17 0x0017
+#define ixCRT18 0x0018
+#define ixCRT1E 0x001e
+#define ixCRT1F 0x001f
+#define ixCRT22 0x0022
+
+
+// addressBlock: vgagrphind
+// base address: 0x0
+#define ixGRA00 0x0000
+#define ixGRA01 0x0001
+#define ixGRA02 0x0002
+#define ixGRA03 0x0003
+#define ixGRA04 0x0004
+#define ixGRA05 0x0005
+#define ixGRA06 0x0006
+#define ixGRA07 0x0007
+#define ixGRA08 0x0008
+
+
+// addressBlock: vgaattrind
+// base address: 0x0
+#define ixATTR00 0x0000
+#define ixATTR01 0x0001
+#define ixATTR02 0x0002
+#define ixATTR03 0x0003
+#define ixATTR04 0x0004
+#define ixATTR05 0x0005
+#define ixATTR06 0x0006
+#define ixATTR07 0x0007
+#define ixATTR08 0x0008
+#define ixATTR09 0x0009
+#define ixATTR0A 0x000a
+#define ixATTR0B 0x000b
+#define ixATTR0C 0x000c
+#define ixATTR0D 0x000d
+#define ixATTR0E 0x000e
+#define ixATTR0F 0x000f
+#define ixATTR10 0x0010
+#define ixATTR11 0x0011
+#define ixATTR12 0x0012
+#define ixATTR13 0x0013
+#define ixATTR14 0x0014
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h
new file mode 100644
index 000000000000..d8ad862b3a74
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h
@@ -0,0 +1,64636 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dce_12_0_SH_MASK_HEADER
+#define _dce_12_0_SH_MASK_HEADER
+
+
+// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
+//dispdec_VGA_MEM_WRITE_PAGE_ADDR
+#define dispdec_VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
+#define dispdec_VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
+#define dispdec_VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
+#define dispdec_VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
+
+
+// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
+//dispdec_VGA_MEM_READ_PAGE_ADDR
+#define dispdec_VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
+#define dispdec_VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
+#define dispdec_VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
+#define dispdec_VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
+
+
+// addressBlock: dce_dc_dc_perfmon0_dispdec
+//DC_PERFMON0_PERFCOUNTER_CNTL
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON0_PERFCOUNTER_CNTL2
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON0_PERFCOUNTER_STATE
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON0_PERFMON_CNTL
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON0_PERFMON_CNTL2
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON0_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON0_PERFMON_CVALUE_LOW
+#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON0_PERFMON_HI
+#define DC_PERFMON0_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON0_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON0_PERFMON_LOW
+#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_perfmon13_dispdec
+//DC_PERFMON13_PERFCOUNTER_CNTL
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON13_PERFCOUNTER_CNTL2
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON13_PERFCOUNTER_STATE
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON13_PERFMON_CNTL
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON13_PERFMON_CNTL2
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON13_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON13_PERFMON_CVALUE_LOW
+#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON13_PERFMON_HI
+#define DC_PERFMON13_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON13_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON13_PERFMON_LOW
+#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_displaypllregs_dispdec
+//PPLL_VREG_CFG
+#define PPLL_VREG_CFG__pw_pc_bleeder_ac__SHIFT 0x0
+#define PPLL_VREG_CFG__pw_pc_bleeder_en__SHIFT 0x1
+#define PPLL_VREG_CFG__pw_pc_is_1p2__SHIFT 0x2
+#define PPLL_VREG_CFG__pw_pc_reg_obs_sel__SHIFT 0x3
+#define PPLL_VREG_CFG__pw_pc_reg_on_mode__SHIFT 0x5
+#define PPLL_VREG_CFG__pw_pc_rlad_tap_sel__SHIFT 0x7
+#define PPLL_VREG_CFG__pw_pc_reg_off_hi__SHIFT 0xb
+#define PPLL_VREG_CFG__pw_pc_reg_off_lo__SHIFT 0xc
+#define PPLL_VREG_CFG__pw_pc_scale_driver__SHIFT 0xd
+#define PPLL_VREG_CFG__pw_pc_sel_bump__SHIFT 0xf
+#define PPLL_VREG_CFG__pw_pc_sel_rladder_x__SHIFT 0x10
+#define PPLL_VREG_CFG__pw_pc_short_rc_filt_x__SHIFT 0x11
+#define PPLL_VREG_CFG__pw_pc_vref_pwr_on__SHIFT 0x12
+#define PPLL_VREG_CFG__pw_pc_dpll_cfg_2__SHIFT 0x14
+#define PPLL_VREG_CFG__pw_pc_bleeder_ac_MASK 0x00000001L
+#define PPLL_VREG_CFG__pw_pc_bleeder_en_MASK 0x00000002L
+#define PPLL_VREG_CFG__pw_pc_is_1p2_MASK 0x00000004L
+#define PPLL_VREG_CFG__pw_pc_reg_obs_sel_MASK 0x00000018L
+#define PPLL_VREG_CFG__pw_pc_reg_on_mode_MASK 0x00000060L
+#define PPLL_VREG_CFG__pw_pc_rlad_tap_sel_MASK 0x00000780L
+#define PPLL_VREG_CFG__pw_pc_reg_off_hi_MASK 0x00000800L
+#define PPLL_VREG_CFG__pw_pc_reg_off_lo_MASK 0x00001000L
+#define PPLL_VREG_CFG__pw_pc_scale_driver_MASK 0x00006000L
+#define PPLL_VREG_CFG__pw_pc_sel_bump_MASK 0x00008000L
+#define PPLL_VREG_CFG__pw_pc_sel_rladder_x_MASK 0x00010000L
+#define PPLL_VREG_CFG__pw_pc_short_rc_filt_x_MASK 0x00020000L
+#define PPLL_VREG_CFG__pw_pc_vref_pwr_on_MASK 0x00040000L
+#define PPLL_VREG_CFG__pw_pc_dpll_cfg_2_MASK 0x0FF00000L
+//PPLL_MODE_CNTL
+#define PPLL_MODE_CNTL__pw_pc_refclk_gate_dis__SHIFT 0x0
+#define PPLL_MODE_CNTL__pw_pc_multi_phase_en__SHIFT 0x8
+#define PPLL_MODE_CNTL__reg_tmg_pwr_state__SHIFT 0x10
+#define PPLL_MODE_CNTL__pw_pc_refclk_gate_dis_MASK 0x00000001L
+#define PPLL_MODE_CNTL__pw_pc_multi_phase_en_MASK 0x00000F00L
+#define PPLL_MODE_CNTL__reg_tmg_pwr_state_MASK 0x00030000L
+//PPLL_FREQ_CTRL0
+#define PPLL_FREQ_CTRL0__reg_tmg_fcw0_frac__SHIFT 0x0
+#define PPLL_FREQ_CTRL0__reg_tmg_fcw0_int__SHIFT 0x10
+#define PPLL_FREQ_CTRL0__reg_tmg_fcw0_frac_MASK 0x0000FFFFL
+#define PPLL_FREQ_CTRL0__reg_tmg_fcw0_int_MASK 0x01FF0000L
+//PPLL_FREQ_CTRL1
+#define PPLL_FREQ_CTRL1__reg_tmg_fcw1_frac__SHIFT 0x0
+#define PPLL_FREQ_CTRL1__reg_tmg_fcw1_int__SHIFT 0x10
+#define PPLL_FREQ_CTRL1__reg_tmg_fcw1_frac_MASK 0x0000FFFFL
+#define PPLL_FREQ_CTRL1__reg_tmg_fcw1_int_MASK 0x01FF0000L
+//PPLL_FREQ_CTRL2
+#define PPLL_FREQ_CTRL2__reg_tmg_fcw_denom__SHIFT 0x0
+#define PPLL_FREQ_CTRL2__reg_tmg_fcw_slew_frac__SHIFT 0x10
+#define PPLL_FREQ_CTRL2__reg_tmg_fcw_denom_MASK 0x0000FFFFL
+#define PPLL_FREQ_CTRL2__reg_tmg_fcw_slew_frac_MASK 0xFFFF0000L
+//PPLL_FREQ_CTRL3
+#define PPLL_FREQ_CTRL3__reg_tmg_refclk_div__SHIFT 0x0
+#define PPLL_FREQ_CTRL3__reg_tmg_vco_pre_div__SHIFT 0x3
+#define PPLL_FREQ_CTRL3__reg_tmg_fracn_en__SHIFT 0x6
+#define PPLL_FREQ_CTRL3__reg_tmg_ssc_en__SHIFT 0x8
+#define PPLL_FREQ_CTRL3__reg_tmg_fcw_sel__SHIFT 0xa
+#define PPLL_FREQ_CTRL3__reg_tmg_freq_jump_en__SHIFT 0xc
+#define PPLL_FREQ_CTRL3__reg_tmg_tdc_resol__SHIFT 0x10
+#define PPLL_FREQ_CTRL3__pw_pc_dpll_cfg_1__SHIFT 0x18
+#define PPLL_FREQ_CTRL3__reg_tmg_refclk_div_MASK 0x00000003L
+#define PPLL_FREQ_CTRL3__reg_tmg_vco_pre_div_MASK 0x00000018L
+#define PPLL_FREQ_CTRL3__reg_tmg_fracn_en_MASK 0x00000040L
+#define PPLL_FREQ_CTRL3__reg_tmg_ssc_en_MASK 0x00000100L
+#define PPLL_FREQ_CTRL3__reg_tmg_fcw_sel_MASK 0x00000400L
+#define PPLL_FREQ_CTRL3__reg_tmg_freq_jump_en_MASK 0x00001000L
+#define PPLL_FREQ_CTRL3__reg_tmg_tdc_resol_MASK 0x00FF0000L
+#define PPLL_FREQ_CTRL3__pw_pc_dpll_cfg_1_MASK 0xFF000000L
+//PPLL_BW_CTRL_COARSE
+#define PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_mant__SHIFT 0x0
+#define PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_exp__SHIFT 0x2
+#define PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_mant__SHIFT 0x7
+#define PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_exp__SHIFT 0xc
+#define PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_res__SHIFT 0x11
+#define PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_frac_res__SHIFT 0x18
+#define PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_mant_MASK 0x00000003L
+#define PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_exp_MASK 0x0000003CL
+#define PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_mant_MASK 0x00000780L
+#define PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_exp_MASK 0x0000F000L
+#define PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_res_MASK 0x007E0000L
+#define PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_frac_res_MASK 0x03000000L
+//PPLL_BW_CTRL_FINE
+#define PPLL_BW_CTRL_FINE__pw_pc_dpll_cfg_3__SHIFT 0x0
+#define PPLL_BW_CTRL_FINE__pw_pc_dpll_cfg_3_MASK 0x000003FFL
+//PPLL_CAL_CTRL
+#define PPLL_CAL_CTRL__pw_pc_bypass_freq_lock__SHIFT 0x0
+#define PPLL_CAL_CTRL__pw_pc_tdc_cal_en__SHIFT 0x1
+#define PPLL_CAL_CTRL__pw_pc_tdc_cal_ctrl__SHIFT 0x3
+#define PPLL_CAL_CTRL__pw_pc_meas_win_sel__SHIFT 0x9
+#define PPLL_CAL_CTRL__pw_pc_kdco_cal_dis__SHIFT 0xb
+#define PPLL_CAL_CTRL__pw_pc_kdco_ratio__SHIFT 0xd
+#define PPLL_CAL_CTRL__pw_pc_kdco_incr_cal_dis__SHIFT 0x16
+#define PPLL_CAL_CTRL__pw_pc_nctl_adj_dis__SHIFT 0x17
+#define PPLL_CAL_CTRL__pw_pc_refclk_rate__SHIFT 0x18
+#define PPLL_CAL_CTRL__pw_pc_bypass_freq_lock_MASK 0x00000001L
+#define PPLL_CAL_CTRL__pw_pc_tdc_cal_en_MASK 0x00000002L
+#define PPLL_CAL_CTRL__pw_pc_tdc_cal_ctrl_MASK 0x000001F8L
+#define PPLL_CAL_CTRL__pw_pc_meas_win_sel_MASK 0x00000600L
+#define PPLL_CAL_CTRL__pw_pc_kdco_cal_dis_MASK 0x00000800L
+#define PPLL_CAL_CTRL__pw_pc_kdco_ratio_MASK 0x001FE000L
+#define PPLL_CAL_CTRL__pw_pc_kdco_incr_cal_dis_MASK 0x00400000L
+#define PPLL_CAL_CTRL__pw_pc_nctl_adj_dis_MASK 0x00800000L
+#define PPLL_CAL_CTRL__pw_pc_refclk_rate_MASK 0xFF000000L
+//PPLL_LOOP_CTRL
+#define PPLL_LOOP_CTRL__pw_pc_fbdiv_mask_en__SHIFT 0x0
+#define PPLL_LOOP_CTRL__pw_pc_fb_slip_dis__SHIFT 0x2
+#define PPLL_LOOP_CTRL__pw_pc_clk_tdc_sel__SHIFT 0x4
+#define PPLL_LOOP_CTRL__pw_pc_clk_nctl_sel__SHIFT 0x7
+#define PPLL_LOOP_CTRL__pw_pc_sig_del_patt_sel__SHIFT 0xa
+#define PPLL_LOOP_CTRL__pw_pc_nctl_sig_del_dis__SHIFT 0xc
+#define PPLL_LOOP_CTRL__pw_pc_fbclk_track_refclk__SHIFT 0xe
+#define PPLL_LOOP_CTRL__pw_pc_prbs_en__SHIFT 0x10
+#define PPLL_LOOP_CTRL__pw_pc_tdc_clk_gate_en__SHIFT 0x12
+#define PPLL_LOOP_CTRL__pw_pc_phase_offset__SHIFT 0x14
+#define PPLL_LOOP_CTRL__pw_pc_fbdiv_mask_en_MASK 0x00000001L
+#define PPLL_LOOP_CTRL__pw_pc_fb_slip_dis_MASK 0x00000004L
+#define PPLL_LOOP_CTRL__pw_pc_clk_tdc_sel_MASK 0x00000030L
+#define PPLL_LOOP_CTRL__pw_pc_clk_nctl_sel_MASK 0x00000180L
+#define PPLL_LOOP_CTRL__pw_pc_sig_del_patt_sel_MASK 0x00000400L
+#define PPLL_LOOP_CTRL__pw_pc_nctl_sig_del_dis_MASK 0x00001000L
+#define PPLL_LOOP_CTRL__pw_pc_fbclk_track_refclk_MASK 0x00004000L
+#define PPLL_LOOP_CTRL__pw_pc_prbs_en_MASK 0x00010000L
+#define PPLL_LOOP_CTRL__pw_pc_tdc_clk_gate_en_MASK 0x00040000L
+#define PPLL_LOOP_CTRL__pw_pc_phase_offset_MASK 0x07F00000L
+//PPLL_REFCLK_CNTL
+#define PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_en__SHIFT 0x0
+#define PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_en__SHIFT 0x1
+#define PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_en__SHIFT 0x2
+#define PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_en__SHIFT 0x3
+#define PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_sel__SHIFT 0x8
+#define PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_sel__SHIFT 0x9
+#define PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_sel__SHIFT 0xa
+#define PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_sel__SHIFT 0xb
+#define PPLL_REFCLK_CNTL__regs_pw_refdivsrc__SHIFT 0xe
+#define PPLL_REFCLK_CNTL__regs_pw_ref2core_sel__SHIFT 0x10
+#define PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_en_MASK 0x00000001L
+#define PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_en_MASK 0x00000002L
+#define PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_en_MASK 0x00000004L
+#define PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_en_MASK 0x00000008L
+#define PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_sel_MASK 0x00000100L
+#define PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_sel_MASK 0x00000200L
+#define PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_sel_MASK 0x00000400L
+#define PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_sel_MASK 0x00000800L
+#define PPLL_REFCLK_CNTL__regs_pw_refdivsrc_MASK 0x0000C000L
+#define PPLL_REFCLK_CNTL__regs_pw_ref2core_sel_MASK 0x00010000L
+//PPLL_CLKOUT_CNTL
+#define PPLL_CLKOUT_CNTL__regs_pw_pixclk_pre_pdivsel__SHIFT 0x8
+#define PPLL_CLKOUT_CNTL__regs_pw_pixclk_pdivsel__SHIFT 0x9
+#define PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pre_pdivsel__SHIFT 0xa
+#define PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pdivsel__SHIFT 0xb
+#define PPLL_CLKOUT_CNTL__regs_pw_idclk_en__SHIFT 0xc
+#define PPLL_CLKOUT_CNTL__regs_pw_idclk_pre_pdivsel__SHIFT 0xd
+#define PPLL_CLKOUT_CNTL__regs_pw_idclk_pdivsel__SHIFT 0xe
+#define PPLL_CLKOUT_CNTL__regs_pw_idclk_obs_sel__SHIFT 0xf
+#define PPLL_CLKOUT_CNTL__regs_pw_refclk_sel__SHIFT 0x10
+#define PPLL_CLKOUT_CNTL__regs_cc_resetb__SHIFT 0x14
+#define PPLL_CLKOUT_CNTL__regs_pw_pixclk_pre_pdivsel_MASK 0x00000100L
+#define PPLL_CLKOUT_CNTL__regs_pw_pixclk_pdivsel_MASK 0x00000200L
+#define PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pre_pdivsel_MASK 0x00000400L
+#define PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pdivsel_MASK 0x00000800L
+#define PPLL_CLKOUT_CNTL__regs_pw_idclk_en_MASK 0x00001000L
+#define PPLL_CLKOUT_CNTL__regs_pw_idclk_pre_pdivsel_MASK 0x00002000L
+#define PPLL_CLKOUT_CNTL__regs_pw_idclk_pdivsel_MASK 0x00004000L
+#define PPLL_CLKOUT_CNTL__regs_pw_idclk_obs_sel_MASK 0x00008000L
+#define PPLL_CLKOUT_CNTL__regs_pw_refclk_sel_MASK 0x00030000L
+#define PPLL_CLKOUT_CNTL__regs_cc_resetb_MASK 0x00100000L
+//PPLL_DFT_CNTL
+#define PPLL_DFT_CNTL__regs_pw_obs_en__SHIFT 0x0
+#define PPLL_DFT_CNTL__regs_pw_obs_div_sel_1__SHIFT 0x1
+#define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_1__SHIFT 0x4
+#define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_2__SHIFT 0x8
+#define PPLL_DFT_CNTL__regs_pw_obs_sel__SHIFT 0xc
+#define PPLL_DFT_CNTL__regs_pw_obs_en_MASK 0x00000001L
+#define PPLL_DFT_CNTL__regs_pw_obs_div_sel_1_MASK 0x00000006L
+#define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_1_MASK 0x000000F0L
+#define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_2_MASK 0x00000F00L
+#define PPLL_DFT_CNTL__regs_pw_obs_sel_MASK 0x00003000L
+//PPLL_ANALOG_CNTL
+#define PPLL_ANALOG_CNTL__regs_pw_spare__SHIFT 0x0
+#define PPLL_ANALOG_CNTL__regs_pw_spare_MASK 0x000000FFL
+//PPLL_POSTDIV
+#define PPLL_POSTDIV__reg_tmg_postdiv__SHIFT 0x8
+#define PPLL_POSTDIV__reg_tmg_pixclk_pdiv2__SHIFT 0xc
+#define PPLL_POSTDIV__reg_tmg_postdiv_MASK 0x00000F00L
+#define PPLL_POSTDIV__reg_tmg_pixclk_pdiv2_MASK 0x00001000L
+//PPLL_OBSERVE0
+#define PPLL_OBSERVE0__pw_pc_lock_det_tdc_steps__SHIFT 0x0
+#define PPLL_OBSERVE0__pw_pc_clear_sticky_lock__SHIFT 0x6
+#define PPLL_OBSERVE0__pw_pc_lock_det_dis__SHIFT 0x8
+#define PPLL_OBSERVE0__pw_pc_dco_cfg__SHIFT 0xa
+#define PPLL_OBSERVE0__pw_pc_anaobs_sel__SHIFT 0x15
+#define PPLL_OBSERVE0__pw_pc_lock_det_tdc_steps_MASK 0x0000001FL
+#define PPLL_OBSERVE0__pw_pc_clear_sticky_lock_MASK 0x00000040L
+#define PPLL_OBSERVE0__pw_pc_lock_det_dis_MASK 0x00000100L
+#define PPLL_OBSERVE0__pw_pc_dco_cfg_MASK 0x0003FC00L
+#define PPLL_OBSERVE0__pw_pc_anaobs_sel_MASK 0x00E00000L
+//PPLL_OBSERVE1
+#define PPLL_OBSERVE1__pw_pc_digobs_sel__SHIFT 0x0
+#define PPLL_OBSERVE1__pw_pc_digobs_trig_sel__SHIFT 0x5
+#define PPLL_OBSERVE1__pw_pc_digobs_div__SHIFT 0xa
+#define PPLL_OBSERVE1__pw_pc_digobs_trig_div__SHIFT 0xc
+#define PPLL_OBSERVE1__reg_tmg_lock_timer__SHIFT 0x10
+#define PPLL_OBSERVE1__pw_pc_digobs_sel_MASK 0x0000000FL
+#define PPLL_OBSERVE1__pw_pc_digobs_trig_sel_MASK 0x000001E0L
+#define PPLL_OBSERVE1__pw_pc_digobs_div_MASK 0x00000C00L
+#define PPLL_OBSERVE1__pw_pc_digobs_trig_div_MASK 0x00003000L
+#define PPLL_OBSERVE1__reg_tmg_lock_timer_MASK 0x3FFF0000L
+//PPLL_UPDATE_CNTL
+#define PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_LOCK__SHIFT 0x2
+#define PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_POINT__SHIFT 0x3
+#define PPLL_UPDATE_CNTL__tmg_reg_UPDATE_PENDING__SHIFT 0x8
+#define PPLL_UPDATE_CNTL__pc_pw_pll_rdy__SHIFT 0x9
+#define PPLL_UPDATE_CNTL__TieLow1__SHIFT 0x10
+#define PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_LOCK_MASK 0x00000004L
+#define PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_POINT_MASK 0x00000008L
+#define PPLL_UPDATE_CNTL__tmg_reg_UPDATE_PENDING_MASK 0x00000100L
+#define PPLL_UPDATE_CNTL__pc_pw_pll_rdy_MASK 0x00000200L
+#define PPLL_UPDATE_CNTL__TieLow1_MASK 0x00010000L
+//PPLL_OBSERVE0_OUT
+#define PPLL_OBSERVE0_OUT__disppll_core_obsout__SHIFT 0x0
+#define PPLL_OBSERVE0_OUT__disppll_core_obsout_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dccg_pll0_dispdec
+//PLL_MACRO_CNTL_RESERVED0
+#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED1
+#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED2
+#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED3
+#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED4
+#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED5
+#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED6
+#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED7
+#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED8
+#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED9
+#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED10
+#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED11
+#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED12
+#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED13
+#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED14
+#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED15
+#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED16
+#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED17
+#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED18
+#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED19
+#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED20
+#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED21
+#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED22
+#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED23
+#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED24
+#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED25
+#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED26
+#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED27
+#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED28
+#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED29
+#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED30
+#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED31
+#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED32
+#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED33
+#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED34
+#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED35
+#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED36
+#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED37
+#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED38
+#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED39
+#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED40
+#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED41
+#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_perfmon1_dispdec
+//DC_PERFMON1_PERFCOUNTER_CNTL
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON1_PERFCOUNTER_CNTL2
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON1_PERFCOUNTER_STATE
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON1_PERFMON_CNTL
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON1_PERFMON_CNTL2
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON1_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON1_PERFMON_CVALUE_LOW
+#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON1_PERFMON_HI
+#define DC_PERFMON1_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON1_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON1_PERFMON_LOW
+#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_mcif_wb0_dispdec
+//MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L
+//MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R
+#define MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL
+//MCIF_WB0_MCIF_WB_BUFMGR_STATUS
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L
+//MCIF_WB0_MCIF_WB_BUF_PITCH
+#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8
+#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18
+#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L
+#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L
+//MCIF_WB0_MCIF_WB_BUF_1_STATUS
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB0_MCIF_WB_BUF_1_STATUS2
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L
+//MCIF_WB0_MCIF_WB_BUF_2_STATUS
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB0_MCIF_WB_BUF_2_STATUS2
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L
+//MCIF_WB0_MCIF_WB_BUF_3_STATUS
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB0_MCIF_WB_BUF_3_STATUS2
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L
+//MCIF_WB0_MCIF_WB_BUF_4_STATUS
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB0_MCIF_WB_BUF_4_STATUS2
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L
+//MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL
+#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16
+#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L
+#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L
+//MCIF_WB0_MCIF_WB_SCLK_CHANGE
+#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1
+#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L
+#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL
+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y
+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET
+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C
+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET
+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y
+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET
+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C
+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET
+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y
+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET
+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C
+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET
+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y
+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET
+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C
+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET
+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L
+//MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
+#define MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0001FFFFL
+//MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL
+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1
+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2
+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4
+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L
+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L
+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L
+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L
+//MCIF_WB0_MCIF_WB_WATERMARK
+#define MCIF_WB0_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL
+//MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL
+#define MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L
+//MCIF_WB0_MCIF_WB_WARM_UP_CNTL
+#define MCIF_WB0_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8
+#define MCIF_WB0_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L
+//MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL
+#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1
+#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L
+#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L
+//MCIF_WB0_MULTI_LEVEL_QOS_CTRL
+#define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0
+#define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL
+//MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE
+#define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL
+//MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE
+#define MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL
+
+
+// addressBlock: dce_dc_mcif_wb1_dispdec
+//MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L
+//MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R
+#define MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL
+//MCIF_WB1_MCIF_WB_BUFMGR_STATUS
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L
+//MCIF_WB1_MCIF_WB_BUF_PITCH
+#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8
+#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18
+#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L
+#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L
+//MCIF_WB1_MCIF_WB_BUF_1_STATUS
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB1_MCIF_WB_BUF_1_STATUS2
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L
+//MCIF_WB1_MCIF_WB_BUF_2_STATUS
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB1_MCIF_WB_BUF_2_STATUS2
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L
+//MCIF_WB1_MCIF_WB_BUF_3_STATUS
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB1_MCIF_WB_BUF_3_STATUS2
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L
+//MCIF_WB1_MCIF_WB_BUF_4_STATUS
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB1_MCIF_WB_BUF_4_STATUS2
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L
+//MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL
+#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16
+#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L
+#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L
+//MCIF_WB1_MCIF_WB_SCLK_CHANGE
+#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1
+#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L
+#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL
+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y
+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET
+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C
+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET
+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y
+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET
+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C
+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET
+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y
+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET
+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C
+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET
+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y
+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET
+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C
+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET
+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L
+//MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
+#define MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0001FFFFL
+//MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL
+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1
+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2
+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4
+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L
+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L
+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L
+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L
+//MCIF_WB1_MCIF_WB_WATERMARK
+#define MCIF_WB1_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL
+//MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL
+#define MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L
+//MCIF_WB1_MCIF_WB_WARM_UP_CNTL
+#define MCIF_WB1_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8
+#define MCIF_WB1_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L
+//MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL
+#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1
+#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L
+#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L
+//MCIF_WB1_MULTI_LEVEL_QOS_CTRL
+#define MCIF_WB1_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0
+#define MCIF_WB1_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL
+//MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE
+#define MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL
+//MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE
+#define MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL
+
+
+// addressBlock: dce_dc_mcif_wb2_dispdec
+//MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L
+//MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R
+#define MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL
+//MCIF_WB2_MCIF_WB_BUFMGR_STATUS
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L
+//MCIF_WB2_MCIF_WB_BUF_PITCH
+#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8
+#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18
+#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L
+#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L
+//MCIF_WB2_MCIF_WB_BUF_1_STATUS
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB2_MCIF_WB_BUF_1_STATUS2
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L
+//MCIF_WB2_MCIF_WB_BUF_2_STATUS
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB2_MCIF_WB_BUF_2_STATUS2
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L
+//MCIF_WB2_MCIF_WB_BUF_3_STATUS
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB2_MCIF_WB_BUF_3_STATUS2
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L
+//MCIF_WB2_MCIF_WB_BUF_4_STATUS
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB2_MCIF_WB_BUF_4_STATUS2
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L
+//MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL
+#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16
+#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L
+#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L
+//MCIF_WB2_MCIF_WB_SCLK_CHANGE
+#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1
+#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L
+#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL
+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y
+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET
+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_C
+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET
+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y
+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET
+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_C
+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET
+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y
+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET
+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_C
+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET
+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y
+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET
+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_C
+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET
+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L
+//MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
+#define MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0001FFFFL
+//MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL
+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1
+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2
+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4
+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L
+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L
+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L
+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L
+//MCIF_WB2_MCIF_WB_WATERMARK
+#define MCIF_WB2_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL
+//MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL
+#define MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L
+//MCIF_WB2_MCIF_WB_WARM_UP_CNTL
+#define MCIF_WB2_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8
+#define MCIF_WB2_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L
+//MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL
+#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1
+#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L
+#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L
+//MCIF_WB2_MULTI_LEVEL_QOS_CTRL
+#define MCIF_WB2_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0
+#define MCIF_WB2_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL
+//MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE
+#define MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL
+//MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE
+#define MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL
+
+
+// addressBlock: dce_dc_cwb0_dispdec
+//CWB0_CWB_CTRL
+#define CWB0_CWB_CTRL__CWB_EN__SHIFT 0x0
+#define CWB0_CWB_CTRL__CWB_OUTPUT_COLOR_DEPTH__SHIFT 0x2
+#define CWB0_CWB_CTRL__CWB_ZERO_PADDING_MODE__SHIFT 0x4
+#define CWB0_CWB_CTRL__CWB_CB_CR_SWAP__SHIFT 0x6
+#define CWB0_CWB_CTRL__CWB_422MODE_LUMA_CHROMA_SWAP__SHIFT 0x7
+#define CWB0_CWB_CTRL__CWB_444MODE_ROUNDING_EN__SHIFT 0x8
+#define CWB0_CWB_CTRL__CWB_PACK_FMT_SEL__SHIFT 0xa
+#define CWB0_CWB_CTRL__CWB_EN_MASK 0x00000001L
+#define CWB0_CWB_CTRL__CWB_OUTPUT_COLOR_DEPTH_MASK 0x0000000CL
+#define CWB0_CWB_CTRL__CWB_ZERO_PADDING_MODE_MASK 0x00000010L
+#define CWB0_CWB_CTRL__CWB_CB_CR_SWAP_MASK 0x00000040L
+#define CWB0_CWB_CTRL__CWB_422MODE_LUMA_CHROMA_SWAP_MASK 0x00000080L
+#define CWB0_CWB_CTRL__CWB_444MODE_ROUNDING_EN_MASK 0x00000100L
+#define CWB0_CWB_CTRL__CWB_PACK_FMT_SEL_MASK 0x00000400L
+//CWB0_CWB_FENCE_PAR0
+#define CWB0_CWB_FENCE_PAR0__CWB_OUTPUT_LINE_WIDTH__SHIFT 0x0
+#define CWB0_CWB_FENCE_PAR0__CWB_ERROR_LINE_WIDTH__SHIFT 0x10
+#define CWB0_CWB_FENCE_PAR0__CWB_OUTPUT_LINE_WIDTH_MASK 0x00001FFFL
+#define CWB0_CWB_FENCE_PAR0__CWB_ERROR_LINE_WIDTH_MASK 0x1FFF0000L
+//CWB0_CWB_FENCE_PAR1
+#define CWB0_CWB_FENCE_PAR1__CWB_OUTPUT_LINES_PER_FRAME__SHIFT 0x0
+#define CWB0_CWB_FENCE_PAR1__CWB_EOF_TO_SOF_SPACING__SHIFT 0x10
+#define CWB0_CWB_FENCE_PAR1__CWB_OUTPUT_LINES_PER_FRAME_MASK 0x00001FFFL
+#define CWB0_CWB_FENCE_PAR1__CWB_EOF_TO_SOF_SPACING_MASK 0x003F0000L
+//CWB0_CWB_CRC_CTRL
+#define CWB0_CWB_CRC_CTRL__CWB_CRC_EN__SHIFT 0x0
+#define CWB0_CWB_CRC_CTRL__CWB_CRC_CONT_EN__SHIFT 0x2
+#define CWB0_CWB_CRC_CTRL__CWB_CRC_SRC_SEL__SHIFT 0x6
+#define CWB0_CWB_CRC_CTRL__CWB_CRC_EN_MASK 0x00000001L
+#define CWB0_CWB_CRC_CTRL__CWB_CRC_CONT_EN_MASK 0x00000004L
+#define CWB0_CWB_CRC_CTRL__CWB_CRC_SRC_SEL_MASK 0x00000040L
+//CWB0_CWB_CRC_RED_GREEN_MASK
+#define CWB0_CWB_CRC_RED_GREEN_MASK__CWB_CRC_RED_MASK__SHIFT 0x0
+#define CWB0_CWB_CRC_RED_GREEN_MASK__CWB_CRC_GREEN_MASK__SHIFT 0x10
+#define CWB0_CWB_CRC_RED_GREEN_MASK__CWB_CRC_RED_MASK_MASK 0x0000FFFFL
+#define CWB0_CWB_CRC_RED_GREEN_MASK__CWB_CRC_GREEN_MASK_MASK 0xFFFF0000L
+//CWB0_CWB_CRC_BLUE_MASK
+#define CWB0_CWB_CRC_BLUE_MASK__CWB_CRC_BLUE_MASK__SHIFT 0x0
+#define CWB0_CWB_CRC_BLUE_MASK__CWB_CRC_BLUE_MASK_MASK 0x0000FFFFL
+//CWB0_CWB_CRC_RED_GREEN_RESULT
+#define CWB0_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_RED_RESULT__SHIFT 0x0
+#define CWB0_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_GREEN_RESULT__SHIFT 0x10
+#define CWB0_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_RED_RESULT_MASK 0x0000FFFFL
+#define CWB0_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_GREEN_RESULT_MASK 0xFFFF0000L
+//CWB0_CWB_CRC_BLUE_RESULT
+#define CWB0_CWB_CRC_BLUE_RESULT__CWB_CRC_BLUE_RESULT__SHIFT 0x0
+#define CWB0_CWB_CRC_BLUE_RESULT__CWB_CRC_COUNT__SHIFT 0x10
+#define CWB0_CWB_CRC_BLUE_RESULT__CWB_CRC_BLUE_RESULT_MASK 0x0000FFFFL
+#define CWB0_CWB_CRC_BLUE_RESULT__CWB_CRC_COUNT_MASK 0x000F0000L
+
+
+// addressBlock: dce_dc_cwb1_dispdec
+//CWB1_CWB_CTRL
+#define CWB1_CWB_CTRL__CWB_EN__SHIFT 0x0
+#define CWB1_CWB_CTRL__CWB_OUTPUT_COLOR_DEPTH__SHIFT 0x2
+#define CWB1_CWB_CTRL__CWB_ZERO_PADDING_MODE__SHIFT 0x4
+#define CWB1_CWB_CTRL__CWB_CB_CR_SWAP__SHIFT 0x6
+#define CWB1_CWB_CTRL__CWB_422MODE_LUMA_CHROMA_SWAP__SHIFT 0x7
+#define CWB1_CWB_CTRL__CWB_444MODE_ROUNDING_EN__SHIFT 0x8
+#define CWB1_CWB_CTRL__CWB_PACK_FMT_SEL__SHIFT 0xa
+#define CWB1_CWB_CTRL__CWB_EN_MASK 0x00000001L
+#define CWB1_CWB_CTRL__CWB_OUTPUT_COLOR_DEPTH_MASK 0x0000000CL
+#define CWB1_CWB_CTRL__CWB_ZERO_PADDING_MODE_MASK 0x00000010L
+#define CWB1_CWB_CTRL__CWB_CB_CR_SWAP_MASK 0x00000040L
+#define CWB1_CWB_CTRL__CWB_422MODE_LUMA_CHROMA_SWAP_MASK 0x00000080L
+#define CWB1_CWB_CTRL__CWB_444MODE_ROUNDING_EN_MASK 0x00000100L
+#define CWB1_CWB_CTRL__CWB_PACK_FMT_SEL_MASK 0x00000400L
+//CWB1_CWB_FENCE_PAR0
+#define CWB1_CWB_FENCE_PAR0__CWB_OUTPUT_LINE_WIDTH__SHIFT 0x0
+#define CWB1_CWB_FENCE_PAR0__CWB_ERROR_LINE_WIDTH__SHIFT 0x10
+#define CWB1_CWB_FENCE_PAR0__CWB_OUTPUT_LINE_WIDTH_MASK 0x00001FFFL
+#define CWB1_CWB_FENCE_PAR0__CWB_ERROR_LINE_WIDTH_MASK 0x1FFF0000L
+//CWB1_CWB_FENCE_PAR1
+#define CWB1_CWB_FENCE_PAR1__CWB_OUTPUT_LINES_PER_FRAME__SHIFT 0x0
+#define CWB1_CWB_FENCE_PAR1__CWB_EOF_TO_SOF_SPACING__SHIFT 0x10
+#define CWB1_CWB_FENCE_PAR1__CWB_OUTPUT_LINES_PER_FRAME_MASK 0x00001FFFL
+#define CWB1_CWB_FENCE_PAR1__CWB_EOF_TO_SOF_SPACING_MASK 0x003F0000L
+//CWB1_CWB_CRC_CTRL
+#define CWB1_CWB_CRC_CTRL__CWB_CRC_EN__SHIFT 0x0
+#define CWB1_CWB_CRC_CTRL__CWB_CRC_CONT_EN__SHIFT 0x2
+#define CWB1_CWB_CRC_CTRL__CWB_CRC_SRC_SEL__SHIFT 0x6
+#define CWB1_CWB_CRC_CTRL__CWB_CRC_EN_MASK 0x00000001L
+#define CWB1_CWB_CRC_CTRL__CWB_CRC_CONT_EN_MASK 0x00000004L
+#define CWB1_CWB_CRC_CTRL__CWB_CRC_SRC_SEL_MASK 0x00000040L
+//CWB1_CWB_CRC_RED_GREEN_MASK
+#define CWB1_CWB_CRC_RED_GREEN_MASK__CWB_CRC_RED_MASK__SHIFT 0x0
+#define CWB1_CWB_CRC_RED_GREEN_MASK__CWB_CRC_GREEN_MASK__SHIFT 0x10
+#define CWB1_CWB_CRC_RED_GREEN_MASK__CWB_CRC_RED_MASK_MASK 0x0000FFFFL
+#define CWB1_CWB_CRC_RED_GREEN_MASK__CWB_CRC_GREEN_MASK_MASK 0xFFFF0000L
+//CWB1_CWB_CRC_BLUE_MASK
+#define CWB1_CWB_CRC_BLUE_MASK__CWB_CRC_BLUE_MASK__SHIFT 0x0
+#define CWB1_CWB_CRC_BLUE_MASK__CWB_CRC_BLUE_MASK_MASK 0x0000FFFFL
+//CWB1_CWB_CRC_RED_GREEN_RESULT
+#define CWB1_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_RED_RESULT__SHIFT 0x0
+#define CWB1_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_GREEN_RESULT__SHIFT 0x10
+#define CWB1_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_RED_RESULT_MASK 0x0000FFFFL
+#define CWB1_CWB_CRC_RED_GREEN_RESULT__CWB_CRC_GREEN_RESULT_MASK 0xFFFF0000L
+//CWB1_CWB_CRC_BLUE_RESULT
+#define CWB1_CWB_CRC_BLUE_RESULT__CWB_CRC_BLUE_RESULT__SHIFT 0x0
+#define CWB1_CWB_CRC_BLUE_RESULT__CWB_CRC_COUNT__SHIFT 0x10
+#define CWB1_CWB_CRC_BLUE_RESULT__CWB_CRC_BLUE_RESULT_MASK 0x0000FFFFL
+#define CWB1_CWB_CRC_BLUE_RESULT__CWB_CRC_COUNT_MASK 0x000F0000L
+
+
+// addressBlock: dce_dc_dc_perfmon9_dispdec
+//DC_PERFMON9_PERFCOUNTER_CNTL
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON9_PERFCOUNTER_CNTL2
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON9_PERFCOUNTER_STATE
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON9_PERFMON_CNTL
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON9_PERFMON_CNTL2
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON9_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON9_PERFMON_CVALUE_LOW
+#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON9_PERFMON_HI
+#define DC_PERFMON9_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON9_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON9_PERFMON_LOW
+#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dispdec
+//VGA_MEM_WRITE_PAGE_ADDR
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
+//VGA_MEM_READ_PAGE_ADDR
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
+//VGA_RENDER_CONTROL
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18
+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x0000001FL
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x00000060L
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x00000080L
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x00000100L
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x00030000L
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x01000000L
+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x02000000L
+//VGA_SEQUENCER_RESET_CONTROL
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000001L
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000002L
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000004L
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000008L
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000010L
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000020L
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000100L
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000200L
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000400L
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000800L
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00001000L
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00002000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x00010000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x00020000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0x00FC0000L
+//VGA_MODE_CONTROL
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10
+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT 0x18
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x00000001L
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x00000030L
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x00000100L
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x00010000L
+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK 0x01000000L
+//VGA_SURFACE_PITCH_SELECT
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x00000003L
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x00000300L
+//VGA_MEMORY_BASE_ADDRESS
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//VGA_DISPBUF1_SURFACE_ADDR
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x01FFFFFFL
+//VGA_DISPBUF2_SURFACE_ADDR
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x01FFFFFFL
+//VGA_MEMORY_BASE_ADDRESS_HIGH
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0x000000FFL
+//VGA_HDP_CONTROL
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x00000001L
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x00000010L
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x00000100L
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x00010000L
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x01000000L
+//VGA_CACHE_CONTROL
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x00000001L
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x00000100L
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x00010000L
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x00100000L
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3F000000L
+//D1VGA_CONTROL
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x00000001L
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x00000100L
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
+#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x03000000L
+//D2VGA_CONTROL
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x00000001L
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
+#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x03000000L
+//VGA_STATUS
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x00000001L
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x00000002L
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x00000004L
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x00000008L
+//VGA_INTERRUPT_CONTROL
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x00000001L
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x00000100L
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x00010000L
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x01000000L
+//VGA_STATUS_CLEAR
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x00000001L
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x00000100L
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x00010000L
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x01000000L
+//VGA_INTERRUPT_STATUS
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x00000001L
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x00000002L
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x00000004L
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x00000008L
+//VGA_MAIN_CONTROL
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x00000003L
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x00000018L
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0x000000E0L
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x00000300L
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0x0000F000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x00030000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x03000000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x04000000L
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000L
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000L
+//VGA_TEST_CONTROL
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x00000001L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x00000100L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x00010000L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x01000000L
+//VGA_QOS_CTRL
+#define VGA_QOS_CTRL__VGA_READ_QOS__SHIFT 0x0
+#define VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT 0x4
+#define VGA_QOS_CTRL__VGA_READ_QOS_MASK 0x0000000FL
+#define VGA_QOS_CTRL__VGA_WRITE_QOS_MASK 0x000000F0L
+//CRTC8_IDX
+#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0
+#define CRTC8_IDX__VCRTC_IDX_MASK 0x3FL
+//CRTC8_DATA
+#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0
+#define CRTC8_DATA__VCRTC_DATA_MASK 0xFFL
+//GENFC_WT
+#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3
+#define GENFC_WT__VSYNC_SEL_W_MASK 0x08L
+//GENS1
+#define GENS1__NO_DISPLAY__SHIFT 0x0
+#define GENS1__VGA_VSTATUS__SHIFT 0x3
+#define GENS1__PIXEL_READ_BACK__SHIFT 0x4
+#define GENS1__NO_DISPLAY_MASK 0x01L
+#define GENS1__VGA_VSTATUS_MASK 0x08L
+#define GENS1__PIXEL_READ_BACK_MASK 0x30L
+//ATTRDW
+#define ATTRDW__ATTR_DATA__SHIFT 0x0
+#define ATTRDW__ATTR_DATA_MASK 0xFFL
+//ATTRX
+#define ATTRX__ATTR_IDX__SHIFT 0x0
+#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5
+#define ATTRX__ATTR_IDX_MASK 0x1FL
+#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20L
+//ATTRDR
+#define ATTRDR__ATTR_DATA__SHIFT 0x0
+#define ATTRDR__ATTR_DATA_MASK 0xFFL
+//GENMO_WT
+#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0
+#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1
+#define GENMO_WT__VGA_CKSEL__SHIFT 0x2
+#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5
+#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6
+#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7
+#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x01L
+#define GENMO_WT__VGA_RAM_EN_MASK 0x02L
+#define GENMO_WT__VGA_CKSEL_MASK 0x0CL
+#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20L
+#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40L
+#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80L
+//GENS0
+#define GENS0__SENSE_SWITCH__SHIFT 0x4
+#define GENS0__CRT_INTR__SHIFT 0x7
+#define GENS0__SENSE_SWITCH_MASK 0x10L
+#define GENS0__CRT_INTR_MASK 0x80L
+//GENENB
+#define GENENB__BLK_IO_BASE__SHIFT 0x0
+#define GENENB__BLK_IO_BASE_MASK 0xFFL
+//SEQ8_IDX
+#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0
+#define SEQ8_IDX__SEQ_IDX_MASK 0x07L
+//SEQ8_DATA
+#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0
+#define SEQ8_DATA__SEQ_DATA_MASK 0xFFL
+//DAC_MASK
+#define DAC_MASK__DAC_MASK__SHIFT 0x0
+#define DAC_MASK__DAC_MASK_MASK 0xFFL
+//DAC_R_INDEX
+#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0
+#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xFFL
+//DAC_W_INDEX
+#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0
+#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xFFL
+//DAC_DATA
+#define DAC_DATA__DAC_DATA__SHIFT 0x0
+#define DAC_DATA__DAC_DATA_MASK 0x3FL
+//GENFC_RD
+#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3
+#define GENFC_RD__VSYNC_SEL_R_MASK 0x08L
+//GENMO_RD
+#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0
+#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1
+#define GENMO_RD__VGA_CKSEL__SHIFT 0x2
+#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5
+#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6
+#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7
+#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x01L
+#define GENMO_RD__VGA_RAM_EN_MASK 0x02L
+#define GENMO_RD__VGA_CKSEL_MASK 0x0CL
+#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20L
+#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40L
+#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80L
+//GRPH8_IDX
+#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0
+#define GRPH8_IDX__GRPH_IDX_MASK 0x0FL
+//GRPH8_DATA
+#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0
+#define GRPH8_DATA__GRPH_DATA_MASK 0xFFL
+//CRTC8_IDX_1
+#define CRTC8_IDX_1__VCRTC_IDX__SHIFT 0x0
+#define CRTC8_IDX_1__VCRTC_IDX_MASK 0x3FL
+//CRTC8_DATA_1
+#define CRTC8_DATA_1__VCRTC_DATA__SHIFT 0x0
+#define CRTC8_DATA_1__VCRTC_DATA_MASK 0xFFL
+//GENFC_WT_1
+#define GENFC_WT_1__VSYNC_SEL_W__SHIFT 0x3
+#define GENFC_WT_1__VSYNC_SEL_W_MASK 0x08L
+//GENS1_1
+#define GENS1_1__NO_DISPLAY__SHIFT 0x0
+#define GENS1_1__VGA_VSTATUS__SHIFT 0x3
+#define GENS1_1__PIXEL_READ_BACK__SHIFT 0x4
+#define GENS1_1__NO_DISPLAY_MASK 0x01L
+#define GENS1_1__VGA_VSTATUS_MASK 0x08L
+#define GENS1_1__PIXEL_READ_BACK_MASK 0x30L
+//D3VGA_CONTROL
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x00000001L
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x00000100L
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
+#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x03000000L
+//D4VGA_CONTROL
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x00000001L
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x00000100L
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
+#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x03000000L
+//D5VGA_CONTROL
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x00000001L
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x00000100L
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
+#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x03000000L
+//D6VGA_CONTROL
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x00000001L
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x00000100L
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
+#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x03000000L
+//VGA_SOURCE_SELECT
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x00000007L
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x00000700L
+//PHYPLLA_PIXCLK_RESYNC_CNTL
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT 0x8
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK 0x00000100L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+//PHYPLLB_PIXCLK_RESYNC_CNTL
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT 0x8
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK 0x00000100L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+//PHYPLLC_PIXCLK_RESYNC_CNTL
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT 0x8
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK 0x00000100L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+//PHYPLLD_PIXCLK_RESYNC_CNTL
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT 0x8
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK 0x00000100L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+//DCFEV0_CRTC_PIXEL_RATE_CNTL
+#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x8
+#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_PLL_SOURCE__SHIFT 0xf
+#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_SOURCE_MASK 0x00000003L
+#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000700L
+#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_PLL_SOURCE_MASK 0x00008000L
+//DCFEV1_CRTC_PIXEL_RATE_CNTL
+#define DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x8
+#define DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PIXEL_RATE_PLL_SOURCE__SHIFT 0xf
+#define DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PIXEL_RATE_SOURCE_MASK 0x00000003L
+#define DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000700L
+#define DCFEV1_CRTC_PIXEL_RATE_CNTL__DCFEV1_CRTC_PIXEL_RATE_PLL_SOURCE_MASK 0x00008000L
+//SYMCLKLPA_CLOCK_ENABLE
+#define SYMCLKLPA_CLOCK_ENABLE__SYMCLKLPA_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKLPA_CLOCK_ENABLE__SYMCLKLPA_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKLPA_CLOCK_ENABLE__SYMCLKLPA_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKLPA_CLOCK_ENABLE__SYMCLKLPA_CLOCK_ENABLE_MASK 0x00000001L
+#define SYMCLKLPA_CLOCK_ENABLE__SYMCLKLPA_FE_FORCE_EN_MASK 0x00000010L
+#define SYMCLKLPA_CLOCK_ENABLE__SYMCLKLPA_FE_FORCE_SRC_MASK 0x00000700L
+//SYMCLKLPB_CLOCK_ENABLE
+#define SYMCLKLPB_CLOCK_ENABLE__SYMCLKLPB_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKLPB_CLOCK_ENABLE__SYMCLKLPB_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKLPB_CLOCK_ENABLE__SYMCLKLPB_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKLPB_CLOCK_ENABLE__SYMCLKLPB_CLOCK_ENABLE_MASK 0x00000001L
+#define SYMCLKLPB_CLOCK_ENABLE__SYMCLKLPB_FE_FORCE_EN_MASK 0x00000010L
+#define SYMCLKLPB_CLOCK_ENABLE__SYMCLKLPB_FE_FORCE_SRC_MASK 0x00000700L
+//DPREFCLK_CGTT_BLK_CTRL_REG
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0x0000000FL
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
+//REFCLK_CNTL
+#define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT 0x0
+#define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT 0x1
+#define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK 0x00000001L
+#define REFCLK_CNTL__REFCLK_SRC_SEL_MASK 0x00000002L
+//MIPI_CLK_CNTL
+#define MIPI_CLK_CNTL__DSICLK_CLOCK_ENABLE__SHIFT 0x0
+#define MIPI_CLK_CNTL__BYTECLK_CLOCK_ENABLE__SHIFT 0x1
+#define MIPI_CLK_CNTL__ESCCLK_CLOCK_ENABLE__SHIFT 0x2
+#define MIPI_CLK_CNTL__DSICLK_CLOCK_ENABLE_MASK 0x00000001L
+#define MIPI_CLK_CNTL__BYTECLK_CLOCK_ENABLE_MASK 0x00000002L
+#define MIPI_CLK_CNTL__ESCCLK_CLOCK_ENABLE_MASK 0x00000004L
+//REFCLK_CGTT_BLK_CTRL_REG
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0x0000000FL
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
+//PHYPLLE_PIXCLK_RESYNC_CNTL
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT 0x8
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK 0x00000100L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+//DCCG_PERFMON_CNTL2
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT 0x4
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT 0x5
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT 0x6
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT 0x7
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT 0x8
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x00000001L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x00000002L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x00000004L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x00000008L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK 0x00000010L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK 0x00000020L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK 0x00000040L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK 0x00000080L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK 0x00000100L
+//DSICLK_CGTT_BLK_CTRL_REG
+#define DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_ON_DELAY__SHIFT 0x0
+#define DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_OFF_DELAY__SHIFT 0x4
+#define DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_ON_DELAY_MASK 0x0000000FL
+#define DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_OFF_DELAY_MASK 0x00000FF0L
+//DCCG_CBUS_WRCMD_DELAY
+#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY__SHIFT 0x0
+#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY_MASK 0x0000000FL
+//DCCG_DS_DTO_INCR
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xFFFFFFFFL
+//DCCG_DS_DTO_MODULO
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xFFFFFFFFL
+//DCCG_DS_CNTL
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0
+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT 0x4
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x00000001L
+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK 0x00000030L
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x00000100L
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x00000200L
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x00030000L
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x01000000L
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x02000000L
+//DCCG_DS_HW_CAL_INTERVAL
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xFFFFFFFFL
+//SYMCLKG_CLOCK_ENABLE
+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE_MASK 0x00000001L
+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN_MASK 0x00000010L
+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC_MASK 0x00000700L
+//DPREFCLK_CNTL
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0
+#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE__SHIFT 0x8
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x00000007L
+#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE_MASK 0x00000100L
+//AOMCLK0_CNTL
+#define AOMCLK0_CNTL__AOMCLK0_CLOCK_EN__SHIFT 0x0
+#define AOMCLK0_CNTL__AOMCLK0_CLOCK_EN_MASK 0x00000001L
+//AOMCLK1_CNTL
+#define AOMCLK1_CNTL__AOMCLK1_CLOCK_EN__SHIFT 0x0
+#define AOMCLK1_CNTL__AOMCLK1_CLOCK_EN_MASK 0x00000001L
+//AOMCLK2_CNTL
+#define AOMCLK2_CNTL__AOMCLK2_CLOCK_EN__SHIFT 0x0
+#define AOMCLK2_CNTL__AOMCLK2_CLOCK_EN_MASK 0x00000001L
+//DCCG_AUDIO_DTO2_PHASE
+#define DCCG_AUDIO_DTO2_PHASE__DCCG_AUDIO_DTO2_PHASE__SHIFT 0x0
+#define DCCG_AUDIO_DTO2_PHASE__DCCG_AUDIO_DTO2_PHASE_MASK 0xFFFFFFFFL
+//DCCG_AUDIO_DTO2_MODULO
+#define DCCG_AUDIO_DTO2_MODULO__DCCG_AUDIO_DTO2_MODULO__SHIFT 0x0
+#define DCCG_AUDIO_DTO2_MODULO__DCCG_AUDIO_DTO2_MODULO_MASK 0xFFFFFFFFL
+//DCE_VERSION
+#define DCE_VERSION__MAJOR_VERSION__SHIFT 0x0
+#define DCE_VERSION__MINOR_VERSION__SHIFT 0x8
+#define DCE_VERSION__MAJOR_VERSION_MASK 0x000000FFL
+#define DCE_VERSION__MINOR_VERSION_MASK 0x0000FF00L
+//PHYPLLG_PIXCLK_RESYNC_CNTL
+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE__SHIFT 0x8
+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE_MASK 0x00000100L
+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+//DCCG_GTC_CNTL
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x00000001L
+//DCCG_GTC_DTO_INCR
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xFFFFFFFFL
+//DCCG_GTC_DTO_MODULO
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xFFFFFFFFL
+//DCCG_GTC_CURRENT
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xFFFFFFFFL
+//DENTIST_DISPCLK_CNTL
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x15
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x16
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x18
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x00018000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x00020000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x00040000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x00100000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x00200000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x00400000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7F000000L
+//MIPI_DTO_CNTL
+#define MIPI_DTO_CNTL__MIPI_DTO_ENABLE__SHIFT 0x0
+#define MIPI_DTO_CNTL__MIPI_DTO_ENABLE_MASK 0x00000001L
+//MIPI_DTO_PHASE
+#define MIPI_DTO_PHASE__MIPI_DTO_PHASE__SHIFT 0x0
+#define MIPI_DTO_PHASE__MIPI_DTO_PHASE_MASK 0xFFFFFFFFL
+//MIPI_DTO_MODULO
+#define MIPI_DTO_MODULO__MIPI_DTO_MODULO__SHIFT 0x0
+#define MIPI_DTO_MODULO__MIPI_DTO_MODULO_MASK 0xFFFFFFFFL
+//DAC_CLK_ENABLE
+#define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x0
+#define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x4
+#define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x00000001L
+#define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x00000010L
+//DVO_CLK_ENABLE
+#define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x0
+#define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x00000001L
+//AVSYNC_COUNTER_WRITE
+#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE__SHIFT 0x0
+#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE_MASK 0xFFFFFFFFL
+//AVSYNC_COUNTER_CONTROL
+#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE__SHIFT 0x0
+#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE_MASK 0x00000001L
+//DMCU_SMU_INTERRUPT_CNTL
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x00000001L
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xFFFF0000L
+//SMU_CONTROL
+#define SMU_CONTROL__DISPLAY0_FORCE_VBI__SHIFT 0x0
+#define SMU_CONTROL__DISPLAY1_FORCE_VBI__SHIFT 0x1
+#define SMU_CONTROL__DISPLAY2_FORCE_VBI__SHIFT 0x2
+#define SMU_CONTROL__DISPLAY3_FORCE_VBI__SHIFT 0x3
+#define SMU_CONTROL__DISPLAY4_FORCE_VBI__SHIFT 0x4
+#define SMU_CONTROL__DISPLAY5_FORCE_VBI__SHIFT 0x5
+#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI__SHIFT 0x6
+#define SMU_CONTROL__DISPLAY_V1_FORCE_VBI__SHIFT 0x7
+#define SMU_CONTROL__MCIF_WB_FORCE_VBI__SHIFT 0x8
+#define SMU_CONTROL__DISPLAY0_FORCE_VBI_MASK 0x00000001L
+#define SMU_CONTROL__DISPLAY1_FORCE_VBI_MASK 0x00000002L
+#define SMU_CONTROL__DISPLAY2_FORCE_VBI_MASK 0x00000004L
+#define SMU_CONTROL__DISPLAY3_FORCE_VBI_MASK 0x00000008L
+#define SMU_CONTROL__DISPLAY4_FORCE_VBI_MASK 0x00000010L
+#define SMU_CONTROL__DISPLAY5_FORCE_VBI_MASK 0x00000020L
+#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI_MASK 0x00000040L
+#define SMU_CONTROL__DISPLAY_V1_FORCE_VBI_MASK 0x00000080L
+#define SMU_CONTROL__MCIF_WB_FORCE_VBI_MASK 0x00000100L
+//SMU_INTERRUPT_CONTROL
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x00000001L
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x00000010L
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xFFFF0000L
+//AVSYNC_COUNTER_READ
+#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE__SHIFT 0x0
+#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE_MASK 0xFFFFFFFFL
+//MILLISECOND_TIME_BASE_DIV
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x0001FFFFL
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L
+//DISPCLK_FREQ_CHANGE_CNTL
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x00003FFFL
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0x000F0000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x00100000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0x0E000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000L
+//DC_MEM_GLOBAL_PWR_REQ_CNTL
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001L
+//DCCG_PERFMON_CNTL
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT 0x2
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT 0x3
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4
+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7
+#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x8
+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x00000001L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x00000002L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK 0x00000004L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK 0x00000008L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x00000010L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x00000020L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x00000040L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x00000080L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x00000700L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xFFFFF800L
+//DCCG_GATE_DISABLE_CNTL
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1
+#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x2
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4
+#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x5
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13
+#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16
+#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE__SHIFT 0x17
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x00000001L
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000002L
+#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x00000004L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x00000008L
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x00000010L
+#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x00000020L
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x00000040L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x00000100L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x00020000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x00040000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x00080000L
+#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x00200000L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x00400000L
+#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE_MASK 0x00800000L
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x04000000L
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x08000000L
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000L
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000L
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000L
+//DISPCLK_CGTT_BLK_CTRL_REG
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0x0000000FL
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
+//SCLK_CGTT_BLK_CTRL_REG
+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x0
+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE__SHIFT 0xc
+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0x0000000FL
+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
+#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE_MASK 0x00001000L
+//DCCG_CAC_STATUS
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xFFFFFFFFL
+//PIXCLK1_RESYNC_CNTL
+#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x0
+#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x4
+#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x00000001L
+#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x00000030L
+//PIXCLK2_RESYNC_CNTL
+#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x0
+#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x4
+#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x00000001L
+#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x00000030L
+//PIXCLK0_RESYNC_CNTL
+#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x0
+#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x4
+#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x00000001L
+#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x00000030L
+//MICROSECOND_TIME_BASE_DIV
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007FL
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x00007F00L
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x00010000L
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x00020000L
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L
+//DCCG_GATE_DISABLE_CNTL2
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT 0x0
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT 0x1
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT 0x2
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT 0x3
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT 0x4
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT 0x5
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT 0x6
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_FE_GATE_DISABLE__SHIFT 0x8
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE__SHIFT 0x9
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT 0x10
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT 0x11
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT 0x12
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT 0x13
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT 0x14
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT 0x15
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT 0x16
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_GATE_DISABLE__SHIFT 0x18
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_GATE_DISABLE__SHIFT 0x19
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK 0x00000001L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK 0x00000002L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK 0x00000004L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK 0x00000008L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK 0x00000010L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK 0x00000020L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK 0x00000040L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_FE_GATE_DISABLE_MASK 0x00000100L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE_MASK 0x00000200L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK 0x00010000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK 0x00020000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK 0x00040000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK 0x00080000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK 0x00100000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK 0x00200000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK 0x00400000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_GATE_DISABLE_MASK 0x01000000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_GATE_DISABLE_MASK 0x02000000L
+//SYMCLK_CGTT_BLK_CTRL_REG
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT 0x0
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK 0x0000000FL
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
+//PHYPLLF_PIXCLK_RESYNC_CNTL
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE__SHIFT 0x8
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK 0x00000100L
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+//DCCG_DISP_CNTL_REG
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x00000100L
+//CRTC0_PIXEL_RATE_CNTL
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4
+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x8
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x9
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_HALF_RATE_EN__SHIFT 0xb
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x00000003L
+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x00000010L
+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x00000020L
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x00000100L
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x00000200L
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0x0000C000L
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L
+//DP_DTO0_PHASE
+#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0
+#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xFFFFFFFFL
+//DP_DTO0_MODULO
+#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0
+#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xFFFFFFFFL
+//CRTC0_PHYPLL_PIXEL_RATE_CNTL
+#define CRTC0_PHYPLL_PIXEL_RATE_CNTL__CRTC0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC0_PHYPLL_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
+#define CRTC0_PHYPLL_PIXEL_RATE_CNTL__CRTC0_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
+#define CRTC0_PHYPLL_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
+//CRTC1_PIXEL_RATE_CNTL
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4
+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x8
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x9
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_HALF_RATE_EN__SHIFT 0xb
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x00000003L
+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x00000010L
+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x00000020L
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x00000100L
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x00000200L
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0x0000C000L
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L
+//DP_DTO1_PHASE
+#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0
+#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xFFFFFFFFL
+//DP_DTO1_MODULO
+#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0
+#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xFFFFFFFFL
+//CRTC1_PHYPLL_PIXEL_RATE_CNTL
+#define CRTC1_PHYPLL_PIXEL_RATE_CNTL__CRTC1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC1_PHYPLL_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
+#define CRTC1_PHYPLL_PIXEL_RATE_CNTL__CRTC1_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
+#define CRTC1_PHYPLL_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
+//CRTC2_PIXEL_RATE_CNTL
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4
+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x8
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x9
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_HALF_RATE_EN__SHIFT 0xb
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x00000003L
+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x00000010L
+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x00000020L
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x00000100L
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x00000200L
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0x0000C000L
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L
+//DP_DTO2_PHASE
+#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0
+#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xFFFFFFFFL
+//DP_DTO2_MODULO
+#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0
+#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xFFFFFFFFL
+//CRTC2_PHYPLL_PIXEL_RATE_CNTL
+#define CRTC2_PHYPLL_PIXEL_RATE_CNTL__CRTC2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC2_PHYPLL_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
+#define CRTC2_PHYPLL_PIXEL_RATE_CNTL__CRTC2_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
+#define CRTC2_PHYPLL_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
+//CRTC3_PIXEL_RATE_CNTL
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4
+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x8
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x9
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_HALF_RATE_EN__SHIFT 0xb
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x00000003L
+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x00000010L
+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x00000020L
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x00000100L
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x00000200L
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0x0000C000L
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L
+//DP_DTO3_PHASE
+#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0
+#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xFFFFFFFFL
+//DP_DTO3_MODULO
+#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0
+#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xFFFFFFFFL
+//CRTC3_PHYPLL_PIXEL_RATE_CNTL
+#define CRTC3_PHYPLL_PIXEL_RATE_CNTL__CRTC3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC3_PHYPLL_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
+#define CRTC3_PHYPLL_PIXEL_RATE_CNTL__CRTC3_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
+#define CRTC3_PHYPLL_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
+//CRTC4_PIXEL_RATE_CNTL
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4
+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x8
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x9
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_HALF_RATE_EN__SHIFT 0xb
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x00000003L
+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x00000010L
+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x00000020L
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x00000100L
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x00000200L
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0x0000C000L
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L
+//DP_DTO4_PHASE
+#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0
+#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xFFFFFFFFL
+//DP_DTO4_MODULO
+#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0
+#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xFFFFFFFFL
+//CRTC4_PHYPLL_PIXEL_RATE_CNTL
+#define CRTC4_PHYPLL_PIXEL_RATE_CNTL__CRTC4_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC4_PHYPLL_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
+#define CRTC4_PHYPLL_PIXEL_RATE_CNTL__CRTC4_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
+#define CRTC4_PHYPLL_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
+//CRTC5_PIXEL_RATE_CNTL
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4
+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x8
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x9
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_HALF_RATE_EN__SHIFT 0xb
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x00000003L
+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x00000010L
+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x00000020L
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x00000100L
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x00000200L
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0x0000C000L
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L
+//DP_DTO5_PHASE
+#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0
+#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xFFFFFFFFL
+//DP_DTO5_MODULO
+#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0
+#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xFFFFFFFFL
+//CRTC5_PHYPLL_PIXEL_RATE_CNTL
+#define CRTC5_PHYPLL_PIXEL_RATE_CNTL__CRTC5_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC5_PHYPLL_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
+#define CRTC5_PHYPLL_PIXEL_RATE_CNTL__CRTC5_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
+#define CRTC5_PHYPLL_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
+//DCCG_SOFT_RESET
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0
+#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT 0x1
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x00000001L
+#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK 0x00000002L
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x00000004L
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x00000008L
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x00000010L
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x00000100L
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x00001000L
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x00002000L
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x00004000L
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x00008000L
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x00010000L
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x00020000L
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x00040000L
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x00080000L
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x00100000L
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x00200000L
+//SYMCLKA_CLOCK_ENABLE
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x00000001L
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x00000010L
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x00000700L
+//SYMCLKB_CLOCK_ENABLE
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x00000001L
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x00000010L
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x00000700L
+//SYMCLKC_CLOCK_ENABLE
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x00000001L
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x00000010L
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x00000700L
+//SYMCLKD_CLOCK_ENABLE
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x00000001L
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x00000010L
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x00000700L
+//SYMCLKE_CLOCK_ENABLE
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x00000001L
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x00000010L
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x00000700L
+//SYMCLKF_CLOCK_ENABLE
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x00000001L
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x00000010L
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x00000700L
+//DVOACLKD_CNTL
+#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x0
+#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x8
+#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x10
+#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x11
+#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x12
+#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x00000007L
+#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x00001F00L
+#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x00010000L
+#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x00020000L
+#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x00040000L
+//DVOACLKC_MVP_CNTL
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x0
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x8
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x10
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x11
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x12
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x14
+#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT 0x18
+#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x1c
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x00000007L
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x00001F00L
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x00010000L
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x00020000L
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x00040000L
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x00100000L
+#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK 0x03000000L
+#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK 0x30000000L
+//DVOACLKC_CNTL
+#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x0
+#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x8
+#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x10
+#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x11
+#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x12
+#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x00000007L
+#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x00001F00L
+#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x00010000L
+#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x00020000L
+#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x00040000L
+//DCCG_AUDIO_DTO_SOURCE
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x00000007L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x00000030L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x00003000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x00010000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x00100000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x01000000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000L
+//DCCG_AUDIO_DTO0_PHASE
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xFFFFFFFFL
+//DCCG_AUDIO_DTO0_MODULE
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xFFFFFFFFL
+//DCCG_AUDIO_DTO1_PHASE
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xFFFFFFFFL
+//DCCG_AUDIO_DTO1_MODULE
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xFFFFFFFFL
+//DCCG_TEST_CLK_SEL
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x000001FFL
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x00001000L
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x01FF0000L
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000L
+//FBC_CNTL
+#define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x0
+#define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x1
+#define FBC_CNTL__FBC_COMP_CLK_GATE_EN__SHIFT 0x8
+#define FBC_CNTL__FBC_DECOMP_CLK_GATE_EN__SHIFT 0xa
+#define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x10
+#define FBC_CNTL__FBC_DS_ALLOW_DIS__SHIFT 0x18
+#define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x19
+#define FBC_CNTL__FBC_QOS_LEVEL__SHIFT 0x1a
+#define FBC_CNTL__FBC_EN__SHIFT 0x1f
+#define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x00000001L
+#define FBC_CNTL__FBC_SRC_SEL_MASK 0x0000000EL
+#define FBC_CNTL__FBC_COMP_CLK_GATE_EN_MASK 0x00000100L
+#define FBC_CNTL__FBC_DECOMP_CLK_GATE_EN_MASK 0x00000400L
+#define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x00030000L
+#define FBC_CNTL__FBC_DS_ALLOW_DIS_MASK 0x01000000L
+#define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x02000000L
+#define FBC_CNTL__FBC_QOS_LEVEL_MASK 0x3C000000L
+#define FBC_CNTL__FBC_EN_MASK 0x80000000L
+//FBC_IDLE_FORCE_CLEAR_MASK
+#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x0
+#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xFFFFFFFFL
+//FBC_START_STOP_DELAY
+#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x0
+#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x7
+#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x8
+#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x0000001FL
+#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x00000080L
+#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x00001F00L
+//FBC_COMP_CNTL
+#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x0
+#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x10
+#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x11
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x12
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x13
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x14
+#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0x0000000FL
+#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x00010000L
+#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x00020000L
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x00040000L
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x00080000L
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x00100000L
+//FBC_COMP_MODE
+#define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x0
+#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x8
+#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x9
+#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0xa
+#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0xb
+#define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x10
+#define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x00000001L
+#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x00000100L
+#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x00000200L
+#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x00000400L
+#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x00000800L
+#define FBC_COMP_MODE__FBC_IND_EN_MASK 0x00010000L
+//FBC_IND_LUT0
+#define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x0
+#define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0xFFFFFFFFL
+//FBC_IND_LUT1
+#define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x0
+#define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0xFFFFFFFFL
+//FBC_IND_LUT2
+#define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x0
+#define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0xFFFFFFFFL
+//FBC_IND_LUT3
+#define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x0
+#define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0xFFFFFFFFL
+//FBC_IND_LUT4
+#define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x0
+#define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0xFFFFFFFFL
+//FBC_IND_LUT5
+#define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x0
+#define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0xFFFFFFFFL
+//FBC_IND_LUT6
+#define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x0
+#define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0xFFFFFFFFL
+//FBC_IND_LUT7
+#define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x0
+#define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0xFFFFFFFFL
+//FBC_IND_LUT8
+#define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x0
+#define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0xFFFFFFFFL
+//FBC_IND_LUT9
+#define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x0
+#define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0xFFFFFFFFL
+//FBC_IND_LUT10
+#define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x0
+#define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0xFFFFFFFFL
+//FBC_IND_LUT11
+#define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x0
+#define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0xFFFFFFFFL
+//FBC_IND_LUT12
+#define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x0
+#define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0xFFFFFFFFL
+//FBC_IND_LUT13
+#define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x0
+#define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0xFFFFFFFFL
+//FBC_IND_LUT14
+#define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x0
+#define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0xFFFFFFFFL
+//FBC_IND_LUT15
+#define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x0
+#define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0xFFFFFFFFL
+//FBC_CSM_REGION_OFFSET_01
+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x0
+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x10
+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0x00000FFFL
+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0x0FFF0000L
+//FBC_CSM_REGION_OFFSET_23
+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x0
+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x10
+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0x00000FFFL
+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0x0FFF0000L
+//FBC_CLIENT_REGION_MASK
+#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x10
+#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0x000F0000L
+//FBC_DEBUG_COMP
+#define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x0
+#define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x3
+#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x4
+#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x8
+#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0xa
+#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0xb
+#define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x00000003L
+#define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x00000008L
+#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0x000000F0L
+#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x00000300L
+#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x00000400L
+#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x00000800L
+//FBC_MISC
+#define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x0
+#define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x2
+#define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x3
+#define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x4
+#define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x8
+#define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0xa
+#define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0xb
+#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0xc
+#define FBC_MISC__FBC_STOP_ON_HFLIP_EVENT__SHIFT 0xd
+#define FBC_MISC__FBC_STOP_COMP_ON_INVALIDATE__SHIFT 0xe
+#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x10
+#define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x14
+#define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x15
+#define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x18
+#define FBC_MISC__FBC_FORCE_DECOMPRESSOR_EN__SHIFT 0x1f
+#define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x00000003L
+#define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x00000004L
+#define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x00000008L
+#define FBC_MISC__FBC_ERROR_PIXEL_MASK 0x000000F0L
+#define FBC_MISC__FBC_DIVIDE_X_MASK 0x00000300L
+#define FBC_MISC__FBC_DIVIDE_Y_MASK 0x00000400L
+#define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x00000800L
+#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x00001000L
+#define FBC_MISC__FBC_STOP_ON_HFLIP_EVENT_MASK 0x00002000L
+#define FBC_MISC__FBC_STOP_COMP_ON_INVALIDATE_MASK 0x00004000L
+#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x00010000L
+#define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x00100000L
+#define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x00200000L
+#define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0x1F000000L
+#define FBC_MISC__FBC_FORCE_DECOMPRESSOR_EN_MASK 0x80000000L
+//FBC_STATUS
+#define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x0
+#define FBC_STATUS__FBC_ENABLE_STATUS_SW__SHIFT 0x4
+#define FBC_STATUS__FBC_COMPRESSION_ENABLE_STATUS__SHIFT 0x8
+#define FBC_STATUS__FBC_DECOMPRESSION_ENABLE_STATUS__SHIFT 0xc
+#define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x00000001L
+#define FBC_STATUS__FBC_ENABLE_STATUS_SW_MASK 0x00000010L
+#define FBC_STATUS__FBC_COMPRESSION_ENABLE_STATUS_MASK 0x00000100L
+#define FBC_STATUS__FBC_DECOMPRESSION_ENABLE_STATUS_MASK 0x00001000L
+//FBC_ALPHA_CNTL
+#define FBC_ALPHA_CNTL__FBC_ALPHA_COMP_EN__SHIFT 0x0
+#define FBC_ALPHA_CNTL__FBC_FORCE_COPY_TO_COMP_BUF__SHIFT 0x4
+#define FBC_ALPHA_CNTL__FBC_ZERO_ALPHA_CHUNK_SKIP_EN__SHIFT 0x8
+#define FBC_ALPHA_CNTL__FBC_ALPHA_COMP_EN_MASK 0x00000001L
+#define FBC_ALPHA_CNTL__FBC_FORCE_COPY_TO_COMP_BUF_MASK 0x00000010L
+#define FBC_ALPHA_CNTL__FBC_ZERO_ALPHA_CHUNK_SKIP_EN_MASK 0x00000100L
+//FBC_ALPHA_RGB_OVERRIDE
+#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_R_VAL__SHIFT 0x0
+#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_G_VAL__SHIFT 0xc
+#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_B_VAL__SHIFT 0x18
+#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_R_VAL_MASK 0x000000FFL
+#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_G_VAL_MASK 0x000FF000L
+#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_B_VAL_MASK 0xFF000000L
+//PIPE0_PG_CONFIG
+#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
+#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x00000001L
+//PIPE0_PG_ENABLE
+#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
+#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x00000001L
+//PIPE0_PG_STATUS
+#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
+#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000L
+#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//PIPE1_PG_CONFIG
+#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x0
+#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x00000001L
+//PIPE1_PG_ENABLE
+#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x0
+#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x00000001L
+//PIPE1_PG_STATUS
+#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x1c
+#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000L
+#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//PIPE2_PG_CONFIG
+#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x0
+#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x00000001L
+//PIPE2_PG_ENABLE
+#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x0
+#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x00000001L
+//PIPE2_PG_STATUS
+#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c
+#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000L
+#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//PIPE3_PG_CONFIG
+#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x0
+#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x00000001L
+//PIPE3_PG_ENABLE
+#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x0
+#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x00000001L
+//PIPE3_PG_STATUS
+#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x1c
+#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000L
+#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//PIPE4_PG_CONFIG
+#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x0
+#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x00000001L
+//PIPE4_PG_ENABLE
+#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x0
+#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x00000001L
+//PIPE4_PG_STATUS
+#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x1c
+#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000L
+#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//PIPE5_PG_CONFIG
+#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x0
+#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x00000001L
+//PIPE5_PG_ENABLE
+#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x0
+#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x00000001L
+//PIPE5_PG_STATUS
+#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x1c
+#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000L
+#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DSI_PG_CONFIG
+#define DSI_PG_CONFIG__DSI_POWER_FORCEON__SHIFT 0x0
+#define DSI_PG_CONFIG__DSI_POWER_FORCEON_MASK 0x00000001L
+//DSI_PG_ENABLE
+#define DSI_PG_ENABLE__DSI_POWER_GATE__SHIFT 0x0
+#define DSI_PG_ENABLE__DSI_POWER_GATE_MASK 0x00000001L
+//DSI_PG_STATUS
+#define DSI_PG_STATUS__DSI_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DSI_PG_STATUS__DSI_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DSI_PG_STATUS__DSI_DESIRED_PWR_STATE_MASK 0x10000000L
+#define DSI_PG_STATUS__DSI_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DCFEV0_PG_CONFIG
+#define DCFEV0_PG_CONFIG__DCFEV0_POWER_FORCEON__SHIFT 0x0
+#define DCFEV0_PG_CONFIG__DCFEV0_POWER_FORCEON_MASK 0x00000001L
+//DCFEV0_PG_ENABLE
+#define DCFEV0_PG_ENABLE__DCFEV0_POWER_GATE__SHIFT 0x0
+#define DCFEV0_PG_ENABLE__DCFEV0_POWER_GATE_MASK 0x00000001L
+//DCFEV0_PG_STATUS
+#define DCFEV0_PG_STATUS__DCFEV0_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DCFEV0_PG_STATUS__DCFEV0_DESIRED_PWR_STATE_MASK 0x10000000L
+#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DCPG_INTERRUPT_STATUS
+#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0x0
+#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x1
+#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0x2
+#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3
+#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0x4
+#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x5
+#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0x6
+#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x7
+#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x8
+#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x9
+#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0xa
+#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0xb
+#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_UP_INT_OCCURRED__SHIFT 0xc
+#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_DOWN_INT_OCCURRED__SHIFT 0xd
+#define DCPG_INTERRUPT_STATUS__DSI_POWER_UP_INT_OCCURRED__SHIFT 0xe
+#define DCPG_INTERRUPT_STATUS__DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0xf
+#define DCPG_INTERRUPT_STATUS__DCFEV1_POWER_UP_INT_OCCURRED__SHIFT 0x10
+#define DCPG_INTERRUPT_STATUS__DCFEV1_POWER_DOWN_INT_OCCURRED__SHIFT 0x11
+#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_UP_INT_OCCURRED_MASK 0x00000001L
+#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L
+#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_UP_INT_OCCURRED_MASK 0x00000004L
+#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L
+#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED_MASK 0x00000010L
+#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L
+#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_UP_INT_OCCURRED_MASK 0x00000040L
+#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L
+#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED_MASK 0x00000100L
+#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x00000200L
+#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_UP_INT_OCCURRED_MASK 0x00000400L
+#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x00000800L
+#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_UP_INT_OCCURRED_MASK 0x00001000L
+#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_DOWN_INT_OCCURRED_MASK 0x00002000L
+#define DCPG_INTERRUPT_STATUS__DSI_POWER_UP_INT_OCCURRED_MASK 0x00004000L
+#define DCPG_INTERRUPT_STATUS__DSI_POWER_DOWN_INT_OCCURRED_MASK 0x00008000L
+#define DCPG_INTERRUPT_STATUS__DCFEV1_POWER_UP_INT_OCCURRED_MASK 0x00010000L
+#define DCPG_INTERRUPT_STATUS__DCFEV1_POWER_DOWN_INT_OCCURRED_MASK 0x00020000L
+//DCPG_INTERRUPT_CONTROL
+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_MASK__SHIFT 0x0
+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_CLEAR__SHIFT 0x1
+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x2
+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x3
+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK__SHIFT 0x4
+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_CLEAR__SHIFT 0x5
+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x6
+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x7
+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK__SHIFT 0x8
+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR__SHIFT 0x9
+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_MASK__SHIFT 0xa
+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0xb
+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_MASK__SHIFT 0xc
+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xd
+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_MASK__SHIFT 0xe
+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0xf
+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK__SHIFT 0x10
+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x11
+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x12
+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x13
+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_MASK__SHIFT 0x14
+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x15
+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x16
+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17
+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_MASK__SHIFT 0x18
+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_CLEAR__SHIFT 0x19
+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_MASK__SHIFT 0x1a
+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_CLEAR__SHIFT 0x1b
+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_MASK__SHIFT 0x1c
+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_CLEAR__SHIFT 0x1d
+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_MASK__SHIFT 0x1e
+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x1f
+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_MASK_MASK 0x00000001L
+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_CLEAR_MASK 0x00000002L
+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_MASK_MASK 0x00000004L
+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x00000008L
+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK_MASK 0x00000010L
+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_CLEAR_MASK 0x00000020L
+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_MASK_MASK 0x00000040L
+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x00000080L
+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK_MASK 0x00000100L
+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR_MASK 0x00000200L
+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_MASK_MASK 0x00000400L
+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x00000800L
+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_MASK_MASK 0x00001000L
+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_CLEAR_MASK 0x00002000L
+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_MASK_MASK 0x00004000L
+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x00008000L
+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK_MASK 0x00010000L
+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_CLEAR_MASK 0x00020000L
+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_MASK_MASK 0x00040000L
+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x00080000L
+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_MASK_MASK 0x00100000L
+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_CLEAR_MASK 0x00200000L
+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_MASK_MASK 0x00400000L
+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L
+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_MASK_MASK 0x01000000L
+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_CLEAR_MASK 0x02000000L
+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_MASK_MASK 0x04000000L
+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_CLEAR_MASK 0x08000000L
+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_MASK_MASK 0x10000000L
+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_CLEAR_MASK 0x20000000L
+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_MASK_MASK 0x40000000L
+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_CLEAR_MASK 0x80000000L
+//DCPG_INTERRUPT_CONTROL2
+#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_MASK__SHIFT 0x18
+#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_CLEAR__SHIFT 0x19
+#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_MASK__SHIFT 0x1a
+#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_CLEAR__SHIFT 0x1b
+#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_MASK_MASK 0x01000000L
+#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_CLEAR_MASK 0x02000000L
+#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_MASK_MASK 0x04000000L
+#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_CLEAR_MASK 0x08000000L
+//DCFEV1_PG_CONFIG
+#define DCFEV1_PG_CONFIG__DCFEV1_POWER_FORCEON__SHIFT 0x0
+#define DCFEV1_PG_CONFIG__DCFEV1_POWER_FORCEON_MASK 0x00000001L
+//DCFEV1_PG_ENABLE
+#define DCFEV1_PG_ENABLE__DCFEV1_POWER_GATE__SHIFT 0x0
+#define DCFEV1_PG_ENABLE__DCFEV1_POWER_GATE_MASK 0x00000001L
+//DCFEV1_PG_STATUS
+#define DCFEV1_PG_STATUS__DCFEV1_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DCFEV1_PG_STATUS__DCFEV1_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DCFEV1_PG_STATUS__DCFEV1_DESIRED_PWR_STATE_MASK 0x10000000L
+#define DCFEV1_PG_STATUS__DCFEV1_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DC_IP_REQUEST_CNTL
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x00000001L
+//DC_PGCNTL_STATUS_REG
+//DMIFV_STATUS
+#define DMIFV_STATUS__DMIFV_MC_SEND_ON_IDLE__SHIFT 0x0
+#define DMIFV_STATUS__DMIFV_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8
+#define DMIFV_STATUS__DMIFV_MC_SEND_ON_IDLE_MASK 0x0000000FL
+#define DMIFV_STATUS__DMIFV_CLEAR_MC_SEND_ON_IDLE_MASK 0x00000F00L
+//DMIF_CONTROL
+#define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x0
+#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x2
+#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x4
+#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x8
+#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN__SHIFT 0xb
+#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0xc
+#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x11
+#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x18
+#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x1d
+#define DMIF_CONTROL__DMIF_PSTATE_URGENT_DISABLE__SHIFT 0x1f
+#define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x00000003L
+#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x00000004L
+#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x00000010L
+#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x00000700L
+#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN_MASK 0x00000800L
+#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0x0001F000L
+#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x007E0000L
+#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1F000000L
+#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000L
+#define DMIF_CONTROL__DMIF_PSTATE_URGENT_DISABLE_MASK 0x80000000L
+//DMIF_STATUS
+#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x0
+#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0xf
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x10
+#define DMIF_STATUS__DMIF_PIPE_EN_FBC_CHUNK_TRACKER__SHIFT 0x11
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x14
+#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x18
+#define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x1c
+#define DMIF_STATUS__DMIF_MC_LATENCY_TAP_POINT__SHIFT 0x1d
+#define DMIF_STATUS__DMIF_MC_LATENCY_REQ_TYPE__SHIFT 0x1f
+#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0x0000003FL
+#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0x00003F00L
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x00008000L
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x00010000L
+#define DMIF_STATUS__DMIF_PIPE_EN_FBC_CHUNK_TRACKER_MASK 0x000E0000L
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0x00F00000L
+#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0x0F000000L
+#define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000L
+#define DMIF_STATUS__DMIF_MC_LATENCY_TAP_POINT_MASK 0x60000000L
+#define DMIF_STATUS__DMIF_MC_LATENCY_REQ_TYPE_MASK 0x80000000L
+//DMIF_ARBITRATION_CONTROL
+#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x0
+#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x10
+#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0x0000FFFFL
+#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xFFFF0000L
+//PIPE0_ARBITRATION_CONTROL3
+#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
+//PIPE1_ARBITRATION_CONTROL3
+#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
+//PIPE2_ARBITRATION_CONTROL3
+#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
+//PIPE3_ARBITRATION_CONTROL3
+#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
+//PIPE4_ARBITRATION_CONTROL3
+#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
+//PIPE5_ARBITRATION_CONTROL3
+#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
+//DMIF_P_VMID
+#define DMIF_P_VMID__P_VMID_PIPE0__SHIFT 0x0
+#define DMIF_P_VMID__P_VMID_PIPE1__SHIFT 0x4
+#define DMIF_P_VMID__P_VMID_PIPE2__SHIFT 0x8
+#define DMIF_P_VMID__P_VMID_PIPE3__SHIFT 0xc
+#define DMIF_P_VMID__P_VMID_PIPE4__SHIFT 0x10
+#define DMIF_P_VMID__P_VMID_PIPE5__SHIFT 0x14
+#define DMIF_P_VMID__P_VMID_PIPE6__SHIFT 0x18
+#define DMIF_P_VMID__P_VMID_PIPE7__SHIFT 0x1c
+#define DMIF_P_VMID__P_VMID_PIPE0_MASK 0x0000000FL
+#define DMIF_P_VMID__P_VMID_PIPE1_MASK 0x000000F0L
+#define DMIF_P_VMID__P_VMID_PIPE2_MASK 0x00000F00L
+#define DMIF_P_VMID__P_VMID_PIPE3_MASK 0x0000F000L
+#define DMIF_P_VMID__P_VMID_PIPE4_MASK 0x000F0000L
+#define DMIF_P_VMID__P_VMID_PIPE5_MASK 0x00F00000L
+#define DMIF_P_VMID__P_VMID_PIPE6_MASK 0x0F000000L
+#define DMIF_P_VMID__P_VMID_PIPE7_MASK 0xF0000000L
+//DMIF_ADDR_CALC
+#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x1c
+#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000L
+//DMIF_STATUS2
+#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x0
+#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1
+#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x2
+#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x3
+#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x4
+#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x5
+#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x8
+#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x9
+#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x00000001L
+#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x00000002L
+#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x00000004L
+#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x00000008L
+#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x00000010L
+#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x00000020L
+#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x00000100L
+#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x00000200L
+//PIPE0_MAX_REQUESTS
+#define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
+//PIPE1_MAX_REQUESTS
+#define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
+//PIPE2_MAX_REQUESTS
+#define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
+//PIPE3_MAX_REQUESTS
+#define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
+//PIPE4_MAX_REQUESTS
+#define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
+//PIPE5_MAX_REQUESTS
+#define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
+//LOW_POWER_TILING_CONTROL
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x0
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x3
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x5
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x8
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0xb
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0xc
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x10
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x00000001L
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x00000018L
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0x000000E0L
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x00000700L
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x00000800L
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x00007000L
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0x0FFF0000L
+//MCIF_CONTROL
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L
+//MCIF_WRITE_COMBINE_CONTROL
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0x000003FFL
+//MCIF_PHASE0_OUTSTANDING_COUNTER
+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0
+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL
+//CC_DC_PIPE_DIS
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x1
+#define CC_DC_PIPE_DIS__DC_UNDERLAY_PIPE_DIS__SHIFT 0x10
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x0000007EL
+#define CC_DC_PIPE_DIS__DC_UNDERLAY_PIPE_DIS_MASK 0x003F0000L
+//SMU_WM_CONTROL
+#define SMU_WM_CONTROL__DMIF_WM_CHG_SEL__SHIFT 0x0
+#define SMU_WM_CONTROL__DMIF_WM_CHG_REQ__SHIFT 0x2
+#define SMU_WM_CONTROL__DMIF_WM_CHG_ACK_INT_DIS__SHIFT 0x10
+#define SMU_WM_CONTROL__DMIF_WM_CHG_ACK_INT_STATUS__SHIFT 0x11
+#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL__SHIFT 0x14
+#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ__SHIFT 0x16
+#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_ACK_INT_DIS__SHIFT 0x18
+#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_ACK_INT_STATUS__SHIFT 0x19
+#define SMU_WM_CONTROL__DMIF_WM_CHG_SEL_MASK 0x00000003L
+#define SMU_WM_CONTROL__DMIF_WM_CHG_REQ_MASK 0x00000004L
+#define SMU_WM_CONTROL__DMIF_WM_CHG_ACK_INT_DIS_MASK 0x00010000L
+#define SMU_WM_CONTROL__DMIF_WM_CHG_ACK_INT_STATUS_MASK 0x00020000L
+#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL_MASK 0x00300000L
+#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ_MASK 0x00400000L
+#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_ACK_INT_DIS_MASK 0x01000000L
+#define SMU_WM_CONTROL__MCIF_WB_WM_CHG_ACK_INT_STATUS_MASK 0x02000000L
+//RBBMIF_TIMEOUT
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT 0x14
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0x000FFFFFL
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK 0xFFF00000L
+//RBBMIF_STATUS
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0x0000FFFFL
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000L
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000L
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000L
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000L
+//RBBMIF_TIMEOUT_DIS
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe
+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT 0xf
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x00000001L
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x00000002L
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x00000004L
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x00000008L
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x00000010L
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x00000020L
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x00000040L
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x00000080L
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x00000100L
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x00000200L
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x00000400L
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x00000800L
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x00001000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x00002000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x00004000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK 0x00008000L
+//DCI_MEM_PWR_STATUS
+#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE__SHIFT 0x0
+#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x8
+#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE__SHIFT 0x9
+#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xb
+#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE__SHIFT 0xc
+#define DCI_MEM_PWR_STATUS__DMIF_CURSOR_MEM_PWR_STATE__SHIFT 0x10
+#define DCI_MEM_PWR_STATUS__DMIF_CURSOR_RD_REQ_MEM_PWR_STATE__SHIFT 0x12
+#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE__SHIFT 0x16
+#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0x18
+#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE__SHIFT 0x1a
+#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE__SHIFT 0x1c
+#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE_MASK 0x00000003L
+#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x00000100L
+#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE_MASK 0x00000600L
+#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000800L
+#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE_MASK 0x00003000L
+#define DCI_MEM_PWR_STATUS__DMIF_CURSOR_MEM_PWR_STATE_MASK 0x00030000L
+#define DCI_MEM_PWR_STATUS__DMIF_CURSOR_RD_REQ_MEM_PWR_STATE_MASK 0x000C0000L
+#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE_MASK 0x00400000L
+#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x03000000L
+#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE_MASK 0x0C000000L
+#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE_MASK 0x10000000L
+//DCI_MEM_PWR_STATUS2
+#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0
+#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE__SHIFT 0x2
+#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE__SHIFT 0x4
+#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x5
+#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE__SHIFT 0x7
+#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE__SHIFT 0x9
+#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0xa
+#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE__SHIFT 0xc
+#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE__SHIFT 0xe
+#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0xf
+#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT 0x11
+#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE__SHIFT 0x13
+#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x14
+#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE__SHIFT 0x16
+#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE__SHIFT 0x18
+#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0x00000003L
+#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE_MASK 0x0000000CL
+#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE_MASK 0x00000010L
+#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x00000060L
+#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE_MASK 0x00000180L
+#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE_MASK 0x00000200L
+#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0x00000C00L
+#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE_MASK 0x00003000L
+#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE_MASK 0x00004000L
+#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x00018000L
+#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK 0x00060000L
+#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE_MASK 0x00080000L
+#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0x00300000L
+#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE_MASK 0x00C00000L
+#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE_MASK 0x01000000L
+//DCI_CLK_CNTL
+#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x0
+#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x5
+#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x6
+#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x7
+#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8
+#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x9
+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV1_L_GATE_DIS__SHIFT 0xa
+#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0xb
+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV1_C_GATE_DIS__SHIFT 0xc
+#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0xd
+#define DCI_CLK_CNTL__VPCLK_POL__SHIFT 0xe
+#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0xf
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x10
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x11
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x12
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x13
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x14
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x15
+#define DCI_CLK_CNTL__DCEFCLK_G_DMIF_FBCTRK_GATE_DIS__SHIFT 0x16
+#define DCI_CLK_CNTL__DCEFCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x17
+#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x18
+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV0_L_GATE_DIS__SHIFT 0x19
+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV0_C_GATE_DIS__SHIFT 0x1a
+#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x1b
+#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x0000001FL
+#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x00000020L
+#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x00000040L
+#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x00000080L
+#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x00000100L
+#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x00000200L
+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV1_L_GATE_DIS_MASK 0x00000400L
+#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x00000800L
+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV1_C_GATE_DIS_MASK 0x00001000L
+#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x00002000L
+#define DCI_CLK_CNTL__VPCLK_POL_MASK 0x00004000L
+#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x00008000L
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x00010000L
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x00020000L
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x00040000L
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x00080000L
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x00100000L
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x00200000L
+#define DCI_CLK_CNTL__DCEFCLK_G_DMIF_FBCTRK_GATE_DIS_MASK 0x00400000L
+#define DCI_CLK_CNTL__DCEFCLK_G_DMIFTRK_GATE_DIS_MASK 0x00800000L
+#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x01000000L
+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV0_L_GATE_DIS_MASK 0x02000000L
+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV0_C_GATE_DIS_MASK 0x04000000L
+#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xF8000000L
+//DCI_CLK_CNTL2
+#define DCI_CLK_CNTL2__DISPCLK_G_MCIF_DWB_GATE_DIS__SHIFT 0x0
+#define DCI_CLK_CNTL2__SCLK_G_MCIF_DWB_GATE_DIS__SHIFT 0x1
+#define DCI_CLK_CNTL2__DISPCLK_G_MCIF_CWB0_GATE_DIS__SHIFT 0x2
+#define DCI_CLK_CNTL2__SCLK_G_MCIF_CWB0_GATE_DIS__SHIFT 0x3
+#define DCI_CLK_CNTL2__DISPCLK_G_MCIF_CWB1_GATE_DIS__SHIFT 0x4
+#define DCI_CLK_CNTL2__DCEFCLK_GATE_DIS__SHIFT 0x5
+#define DCI_CLK_CNTL2__DCEFCLK_TURN_ON_DELAY__SHIFT 0x8
+#define DCI_CLK_CNTL2__DCEFCLK_TURN_OFF_DELAY__SHIFT 0xc
+#define DCI_CLK_CNTL2__CGTT_DCEFCLK_OVERRIDE__SHIFT 0x14
+#define DCI_CLK_CNTL2__SCLK_G_MCIF_CWB1_GATE_DIS__SHIFT 0x1f
+#define DCI_CLK_CNTL2__DISPCLK_G_MCIF_DWB_GATE_DIS_MASK 0x00000001L
+#define DCI_CLK_CNTL2__SCLK_G_MCIF_DWB_GATE_DIS_MASK 0x00000002L
+#define DCI_CLK_CNTL2__DISPCLK_G_MCIF_CWB0_GATE_DIS_MASK 0x00000004L
+#define DCI_CLK_CNTL2__SCLK_G_MCIF_CWB0_GATE_DIS_MASK 0x00000008L
+#define DCI_CLK_CNTL2__DISPCLK_G_MCIF_CWB1_GATE_DIS_MASK 0x00000010L
+#define DCI_CLK_CNTL2__DCEFCLK_GATE_DIS_MASK 0x00000020L
+#define DCI_CLK_CNTL2__DCEFCLK_TURN_ON_DELAY_MASK 0x00000F00L
+#define DCI_CLK_CNTL2__DCEFCLK_TURN_OFF_DELAY_MASK 0x000FF000L
+#define DCI_CLK_CNTL2__CGTT_DCEFCLK_OVERRIDE_MASK 0x00100000L
+#define DCI_CLK_CNTL2__SCLK_G_MCIF_CWB1_GATE_DIS_MASK 0x80000000L
+//DCI_MEM_PWR_CNTL
+#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x0
+#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS__SHIFT 0x2
+#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x7
+#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x8
+#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT 0x9
+#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT 0xb
+#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT 0xc
+#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT 0xd
+#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE__SHIFT 0xe
+#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS__SHIFT 0x10
+#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE__SHIFT 0x14
+#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS__SHIFT 0x16
+#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE__SHIFT 0x17
+#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS__SHIFT 0x19
+#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE__SHIFT 0x1a
+#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS__SHIFT 0x1c
+#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE__SHIFT 0x1d
+#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS__SHIFT 0x1e
+#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE_MASK 0x00000003L
+#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS_MASK 0x00000004L
+#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x00000080L
+#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x00000100L
+#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK 0x00000600L
+#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x00000800L
+#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK 0x00001000L
+#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK 0x00002000L
+#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE_MASK 0x0000C000L
+#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS_MASK 0x00010000L
+#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE_MASK 0x00300000L
+#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS_MASK 0x00400000L
+#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE_MASK 0x01800000L
+#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS_MASK 0x02000000L
+#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE_MASK 0x0C000000L
+#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS_MASK 0x10000000L
+#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE_MASK 0x20000000L
+#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS_MASK 0x40000000L
+//DCI_MEM_PWR_CNTL2
+#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE__SHIFT 0x0
+#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS__SHIFT 0x2
+#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE__SHIFT 0x3
+#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS__SHIFT 0x5
+#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE__SHIFT 0x6
+#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS__SHIFT 0x7
+#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE__SHIFT 0x8
+#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS__SHIFT 0xa
+#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE__SHIFT 0xb
+#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS__SHIFT 0xd
+#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE__SHIFT 0xe
+#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS__SHIFT 0xf
+#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE__SHIFT 0x10
+#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS__SHIFT 0x12
+#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE__SHIFT 0x13
+#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS__SHIFT 0x15
+#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE__SHIFT 0x16
+#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS__SHIFT 0x17
+#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE__SHIFT 0x18
+#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS__SHIFT 0x1a
+#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE__SHIFT 0x1b
+#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS__SHIFT 0x1d
+#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE__SHIFT 0x1e
+#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS__SHIFT 0x1f
+#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE_MASK 0x00000003L
+#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS_MASK 0x00000004L
+#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE_MASK 0x00000018L
+#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS_MASK 0x00000020L
+#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE_MASK 0x00000040L
+#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS_MASK 0x00000080L
+#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE_MASK 0x00000300L
+#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS_MASK 0x00000400L
+#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE_MASK 0x00001800L
+#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS_MASK 0x00002000L
+#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE_MASK 0x00004000L
+#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS_MASK 0x00008000L
+#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE_MASK 0x00030000L
+#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS_MASK 0x00040000L
+#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE_MASK 0x00180000L
+#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS_MASK 0x00200000L
+#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE_MASK 0x00400000L
+#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS_MASK 0x00800000L
+#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE_MASK 0x03000000L
+#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS_MASK 0x04000000L
+#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE_MASK 0x18000000L
+#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS_MASK 0x20000000L
+#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE_MASK 0x40000000L
+#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS_MASK 0x80000000L
+//DCI_MEM_PWR_CNTL3
+#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE__SHIFT 0x0
+#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS__SHIFT 0x2
+#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE__SHIFT 0x3
+#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS__SHIFT 0x5
+#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE__SHIFT 0x6
+#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS__SHIFT 0x7
+#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE__SHIFT 0x8
+#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS__SHIFT 0xa
+#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE__SHIFT 0xb
+#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS__SHIFT 0xd
+#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE__SHIFT 0xe
+#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS__SHIFT 0xf
+#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL__SHIFT 0x10
+#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL__SHIFT 0x12
+#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL__SHIFT 0x14
+#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT 0x16
+#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL__SHIFT 0x17
+#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL__SHIFT 0x19
+#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL__SHIFT 0x1b
+#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL__SHIFT 0x1d
+#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE_MASK 0x00000003L
+#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS_MASK 0x00000004L
+#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE_MASK 0x00000018L
+#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS_MASK 0x00000020L
+#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE_MASK 0x00000040L
+#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS_MASK 0x00000080L
+#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE_MASK 0x00000300L
+#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS_MASK 0x00000400L
+#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE_MASK 0x00001800L
+#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS_MASK 0x00002000L
+#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE_MASK 0x00004000L
+#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS_MASK 0x00008000L
+#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL_MASK 0x00030000L
+#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL_MASK 0x000C0000L
+#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL_MASK 0x00300000L
+#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x00400000L
+#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL_MASK 0x01800000L
+#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL_MASK 0x06000000L
+#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL_MASK 0x18000000L
+#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL_MASK 0x60000000L
+//PIPE0_DMIF_BUFFER_CONTROL
+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
+//PIPE1_DMIF_BUFFER_CONTROL
+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
+//PIPE2_DMIF_BUFFER_CONTROL
+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
+//PIPE3_DMIF_BUFFER_CONTROL
+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
+//PIPE4_DMIF_BUFFER_CONTROL
+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
+//PIPE5_DMIF_BUFFER_CONTROL
+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
+//RBBMIF_STATUS_FLAG
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT 0x8
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT 0x9
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT 0x10
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x00000003L
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x00000010L
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x00000020L
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x00000040L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK 0x00000100L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK 0x00000E00L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK 0xFFFF0000L
+//DCI_SOFT_RESET
+#define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0
+#define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x1
+#define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x2
+#define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x3
+#define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x4
+#define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x5
+#define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x6
+#define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x7
+#define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x8
+#define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x9
+#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET__SHIFT 0xa
+#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET__SHIFT 0xb
+#define DCI_SOFT_RESET__DCFEV1_L_SOFT_RESET__SHIFT 0xc
+#define DCI_SOFT_RESET__DCFEV1_C_SOFT_RESET__SHIFT 0xd
+#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0xe
+#define DCI_SOFT_RESET__DCHUB_SOFT_RESET__SHIFT 0xf
+#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET__SHIFT 0x10
+#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET__SHIFT 0x11
+#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET__SHIFT 0x12
+#define DCI_SOFT_RESET__MCIF_WB_SOFT_RESET__SHIFT 0x13
+#define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x00000001L
+#define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x00000002L
+#define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x00000004L
+#define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x00000008L
+#define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x00000010L
+#define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x00000020L
+#define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x00000040L
+#define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x00000080L
+#define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x00000100L
+#define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x00000200L
+#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET_MASK 0x00000400L
+#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET_MASK 0x00000800L
+#define DCI_SOFT_RESET__DCFEV1_L_SOFT_RESET_MASK 0x00001000L
+#define DCI_SOFT_RESET__DCFEV1_C_SOFT_RESET_MASK 0x00002000L
+#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x00004000L
+#define DCI_SOFT_RESET__DCHUB_SOFT_RESET_MASK 0x00008000L
+#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET_MASK 0x00010000L
+#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET_MASK 0x00020000L
+#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET_MASK 0x00040000L
+#define DCI_SOFT_RESET__MCIF_WB_SOFT_RESET_MASK 0x00080000L
+//DMIF_URG_OVERRIDE
+#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN__SHIFT 0x0
+#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL__SHIFT 0x4
+#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN_MASK 0x00000001L
+#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL_MASK 0x000000F0L
+//PIPE6_ARBITRATION_CONTROL3
+#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
+//PIPE7_ARBITRATION_CONTROL3
+#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000FFFFL
+//PIPE6_MAX_REQUESTS
+#define PIPE6_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE6_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
+//PIPE7_MAX_REQUESTS
+#define PIPE7_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE7_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003FFL
+//DVMM_REG_RD_STATUS
+#define DVMM_REG_RD_STATUS__DVMM_REG_RD_STATUS__SHIFT 0x0
+#define DVMM_REG_RD_STATUS__DVMM_REG_RD_STATUS_MASK 0x00000001L
+//DVMM_REG_RD_DATA
+#define DVMM_REG_RD_DATA__DVMM_REG_RD_DATA__SHIFT 0x0
+#define DVMM_REG_RD_DATA__DVMM_REG_RD_DATA_MASK 0xFFFFFFFFL
+//DVMM_PTE_REQ
+#define DVMM_PTE_REQ__MAX_PTEREQ_TO_ISSUE__SHIFT 0x0
+#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_INT__SHIFT 0x8
+#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER__SHIFT 0x10
+#define DVMM_PTE_REQ__MAX_PTEREQ_TO_ISSUE_MASK 0x000000FFL
+#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_INT_MASK 0x0000FF00L
+#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER_MASK 0x003F0000L
+//DVMM_CNTL
+#define DVMM_CNTL__PDE_CACHE_INVALIDATE_CNTL__SHIFT 0x0
+#define DVMM_CNTL__FORCE_SYSTEM_ACCESS_MODE__SHIFT 0x7
+#define DVMM_CNTL__OVERRIDE_SNOOP__SHIFT 0x11
+#define DVMM_CNTL__ENABLE_PDE_INVALIDATE__SHIFT 0x12
+#define DVMM_CNTL__PDE_CACHE_INVALIDATE_CNTL_MASK 0x00000003L
+#define DVMM_CNTL__FORCE_SYSTEM_ACCESS_MODE_MASK 0x00000080L
+#define DVMM_CNTL__OVERRIDE_SNOOP_MASK 0x00020000L
+#define DVMM_CNTL__ENABLE_PDE_INVALIDATE_MASK 0x00040000L
+//DVMM_FAULT_STATUS
+#define DVMM_FAULT_STATUS__DVMM_FAULT_STATUS__SHIFT 0x0
+#define DVMM_FAULT_STATUS__DVMM_FAULT_STATUS_MASK 0xFFFFFFFFL
+//DVMM_FAULT_ADDR
+#define DVMM_FAULT_ADDR__DVMM_FAULT_ADDR__SHIFT 0x0
+#define DVMM_FAULT_ADDR__DVMM_FAULT_ADDR_MASK 0xFFFFFFFFL
+//FMON_CTRL
+#define FMON_CTRL__FMON_START__SHIFT 0x0
+#define FMON_CTRL__FMON_MODE__SHIFT 0x1
+#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT 0x4
+#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT 0x5
+#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT 0x6
+#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT 0x7
+#define FMON_CTRL__FMON_STATE__SHIFT 0x8
+#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT 0xc
+#define FMON_CTRL__FMON_FILTER_UID__SHIFT 0x10
+#define FMON_CTRL__FMON_SOF_SEL__SHIFT 0x18
+#define FMON_CTRL__FMON_START_MASK 0x00000001L
+#define FMON_CTRL__FMON_MODE_MASK 0x00000006L
+#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK 0x00000010L
+#define FMON_CTRL__FMON_STATUS_IGNORE_MASK 0x00000020L
+#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK 0x00000040L
+#define FMON_CTRL__FMON_FILTER_UID_EN_MASK 0x00000080L
+#define FMON_CTRL__FMON_STATE_MASK 0x00000300L
+#define FMON_CTRL__FMON_URG_THRESHOLD_MASK 0x0000F000L
+#define FMON_CTRL__FMON_FILTER_UID_MASK 0x001F0000L
+#define FMON_CTRL__FMON_SOF_SEL_MASK 0x07000000L
+//DVMM_PTE_PGMEM_CONTROL
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_FORCE__SHIFT 0x0
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_DIS__SHIFT 0x2
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_FORCE__SHIFT 0x3
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_DIS__SHIFT 0x5
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_FORCE__SHIFT 0x6
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_DIS__SHIFT 0x8
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_FORCE__SHIFT 0x9
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_DIS__SHIFT 0xb
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_FORCE__SHIFT 0xc
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_DIS__SHIFT 0xe
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_FORCE__SHIFT 0xf
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_DIS__SHIFT 0x11
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_FORCE__SHIFT 0x12
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_DIS__SHIFT 0x14
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_FORCE__SHIFT 0x15
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_DIS__SHIFT 0x17
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE_MEM_PWR_MODE_SEL__SHIFT 0x18
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_FORCE_MASK 0x00000003L
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_DIS_MASK 0x00000004L
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_FORCE_MASK 0x00000018L
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_DIS_MASK 0x00000020L
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_FORCE_MASK 0x000000C0L
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_DIS_MASK 0x00000100L
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_FORCE_MASK 0x00000600L
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_DIS_MASK 0x00000800L
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_FORCE_MASK 0x00003000L
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_DIS_MASK 0x00004000L
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_FORCE_MASK 0x00018000L
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_DIS_MASK 0x00020000L
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_FORCE_MASK 0x000C0000L
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_DIS_MASK 0x00100000L
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_FORCE_MASK 0x00600000L
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_DIS_MASK 0x00800000L
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE_MEM_PWR_MODE_SEL_MASK 0x03000000L
+//DVMM_PTE_PGMEM_STATE
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE0_PTE_PGMEM_STATE__SHIFT 0x0
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE1_PTE_PGMEM_STATE__SHIFT 0x2
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE2_PTE_PGMEM_STATE__SHIFT 0x4
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE3_PTE_PGMEM_STATE__SHIFT 0x6
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE4_PTE_PGMEM_STATE__SHIFT 0x8
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE5_PTE_PGMEM_STATE__SHIFT 0xa
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE6_PTE_PGMEM_STATE__SHIFT 0xc
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE7_PTE_PGMEM_STATE__SHIFT 0xe
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE0_PTE_PGMEM_STATE_MASK 0x00000003L
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE1_PTE_PGMEM_STATE_MASK 0x0000000CL
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE2_PTE_PGMEM_STATE_MASK 0x00000030L
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE3_PTE_PGMEM_STATE_MASK 0x000000C0L
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE4_PTE_PGMEM_STATE_MASK 0x00000300L
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE5_PTE_PGMEM_STATE_MASK 0x00000C00L
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE6_PTE_PGMEM_STATE_MASK 0x00003000L
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE7_PTE_PGMEM_STATE_MASK 0x0000C000L
+//MCIF_PHASE1_OUTSTANDING_COUNTER
+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0
+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL
+//MCIF_PHASE2_OUTSTANDING_COUNTER
+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER__SHIFT 0x0
+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL
+//MCIF_WB_PHASE0_OUTSTANDING_COUNTER
+#define MCIF_WB_PHASE0_OUTSTANDING_COUNTER__MCIF_WB_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0
+#define MCIF_WB_PHASE0_OUTSTANDING_COUNTER__MCIF_WB_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL
+//MCIF_WB_PHASE1_OUTSTANDING_COUNTER
+#define MCIF_WB_PHASE1_OUTSTANDING_COUNTER__MCIF_WB_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0
+#define MCIF_WB_PHASE1_OUTSTANDING_COUNTER__MCIF_WB_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL
+//DCI_MEM_PWR_CNTL4
+#define DCI_MEM_PWR_CNTL4__MCIF_DWB_LUMA_MEM_EN_NUM__SHIFT 0x0
+#define DCI_MEM_PWR_CNTL4__MCIF_DWB_CHROMA_MEM_EN_NUM__SHIFT 0x1
+#define DCI_MEM_PWR_CNTL4__MCIF_CWB0_LUMA_MEM_EN_NUM__SHIFT 0x2
+#define DCI_MEM_PWR_CNTL4__MCIF_CWB0_CHROMA_MEM_EN_NUM__SHIFT 0x3
+#define DCI_MEM_PWR_CNTL4__MCIF_CWB1_LUMA_MEM_EN_NUM__SHIFT 0x4
+#define DCI_MEM_PWR_CNTL4__MCIF_CWB1_CHROMA_MEM_EN_NUM__SHIFT 0x5
+#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_MEM_PWR_FORCE__SHIFT 0x6
+#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_MEM_PWR_DIS__SHIFT 0x8
+#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_FORCE__SHIFT 0x9
+#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_DIS__SHIFT 0xb
+#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_MODE_SEL__SHIFT 0xc
+#define DCI_MEM_PWR_CNTL4__MCIF_DWB_LUMA_MEM_EN_NUM_MASK 0x00000001L
+#define DCI_MEM_PWR_CNTL4__MCIF_DWB_CHROMA_MEM_EN_NUM_MASK 0x00000002L
+#define DCI_MEM_PWR_CNTL4__MCIF_CWB0_LUMA_MEM_EN_NUM_MASK 0x00000004L
+#define DCI_MEM_PWR_CNTL4__MCIF_CWB0_CHROMA_MEM_EN_NUM_MASK 0x00000008L
+#define DCI_MEM_PWR_CNTL4__MCIF_CWB1_LUMA_MEM_EN_NUM_MASK 0x00000010L
+#define DCI_MEM_PWR_CNTL4__MCIF_CWB1_CHROMA_MEM_EN_NUM_MASK 0x00000020L
+#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_MEM_PWR_FORCE_MASK 0x000000C0L
+#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_MEM_PWR_DIS_MASK 0x00000100L
+#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_FORCE_MASK 0x00000600L
+#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_DIS_MASK 0x00000800L
+#define DCI_MEM_PWR_CNTL4__DMIF_CURSOR_RD_REQ_MEM_PWR_MODE_SEL_MASK 0x00003000L
+//MCIF_WB_MISC_CTRL
+#define MCIF_WB_MISC_CTRL__MCIFWB_WR_COMBINE_TIMEOUT_THRESH__SHIFT 0x0
+#define MCIF_WB_MISC_CTRL__MCIF_WB_SOCCLK_DS_ENABLE__SHIFT 0x10
+#define MCIF_WB_MISC_CTRL__MCIFWB_WR_COMBINE_TIMEOUT_THRESH_MASK 0x000003FFL
+#define MCIF_WB_MISC_CTRL__MCIF_WB_SOCCLK_DS_ENABLE_MASK 0x00010000L
+//DCI_MEM_PWR_STATUS3
+#define DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM0_PWR_STATE__SHIFT 0x0
+#define DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM1_PWR_STATE__SHIFT 0x2
+#define DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM0_PWR_STATE__SHIFT 0x4
+#define DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM1_PWR_STATE__SHIFT 0x6
+#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM0_PWR_STATE__SHIFT 0x8
+#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM1_PWR_STATE__SHIFT 0xa
+#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM0_PWR_STATE__SHIFT 0xc
+#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM1_PWR_STATE__SHIFT 0xe
+#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM0_PWR_STATE__SHIFT 0x10
+#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM1_PWR_STATE__SHIFT 0x12
+#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM0_PWR_STATE__SHIFT 0x14
+#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM1_PWR_STATE__SHIFT 0x16
+#define DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM0_PWR_STATE_MASK 0x00000003L
+#define DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM1_PWR_STATE_MASK 0x0000000CL
+#define DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM0_PWR_STATE_MASK 0x00000030L
+#define DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM1_PWR_STATE_MASK 0x000000C0L
+#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM0_PWR_STATE_MASK 0x00000300L
+#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM1_PWR_STATE_MASK 0x00000C00L
+#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM0_PWR_STATE_MASK 0x00003000L
+#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM1_PWR_STATE_MASK 0x0000C000L
+#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM0_PWR_STATE_MASK 0x00030000L
+#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM1_PWR_STATE_MASK 0x000C0000L
+#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM0_PWR_STATE_MASK 0x00300000L
+#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM1_PWR_STATE_MASK 0x00C00000L
+//DMIF_CURSOR_CONTROL
+#define DMIF_CURSOR_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x4
+#define DMIF_CURSOR_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x8
+#define DMIF_CURSOR_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x10
+#define DMIF_CURSOR_CONTROL__DMIF_CURSOR_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e
+#define DMIF_CURSOR_CONTROL__DMIF_CURSOR_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f
+#define DMIF_CURSOR_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x00000010L
+#define DMIF_CURSOR_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x00000100L
+#define DMIF_CURSOR_CONTROL__LOW_READ_URG_LEVEL_MASK 0x00FF0000L
+#define DMIF_CURSOR_CONTROL__DMIF_CURSOR_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L
+#define DMIF_CURSOR_CONTROL__DMIF_CURSOR_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L
+//DMIF_CURSOR_MEM_CONTROL
+#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_MODE_DIS__SHIFT 0x0
+#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_MODE__SHIFT 0x4
+#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_SIZE__SHIFT 0x8
+#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_PIPE__SHIFT 0x10
+#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_TYPE__SHIFT 0x13
+#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_MODE_DIS_MASK 0x00000001L
+#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_MODE_MASK 0x00000030L
+#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_SIZE_MASK 0x0000FF00L
+#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_PIPE_MASK 0x00070000L
+#define DMIF_CURSOR_MEM_CONTROL__DMIF_CURSOR_MEM_CACHE_TYPE_MASK 0x00180000L
+//DCHUB_FB_LOCATION
+#define DCHUB_FB_LOCATION__FB_BASE__SHIFT 0x0
+#define DCHUB_FB_LOCATION__FB_TOP__SHIFT 0x10
+#define DCHUB_FB_LOCATION__FB_BASE_MASK 0x0000FFFFL
+#define DCHUB_FB_LOCATION__FB_TOP_MASK 0xFFFF0000L
+//DCHUB_FB_OFFSET
+#define DCHUB_FB_OFFSET__FB_OFFSET__SHIFT 0x0
+#define DCHUB_FB_OFFSET__FB_OFFSET_MASK 0x003FFFFFL
+//DCHUB_AGP_BASE
+#define DCHUB_AGP_BASE__AGP_BASE__SHIFT 0x0
+#define DCHUB_AGP_BASE__AGP_BASE_MASK 0x003FFFFFL
+//DCHUB_AGP_BOT
+#define DCHUB_AGP_BOT__AGP_BOT__SHIFT 0x0
+#define DCHUB_AGP_BOT__AGP_BOT_MASK 0x0003FFFFL
+//DCHUB_AGP_TOP
+#define DCHUB_AGP_TOP__AGP_TOP__SHIFT 0x0
+#define DCHUB_AGP_TOP__AGP_TOP_MASK 0x0003FFFFL
+//DCHUB_DRAM_APER_BASE
+#define DCHUB_DRAM_APER_BASE__BASE__SHIFT 0x0
+#define DCHUB_DRAM_APER_BASE__LOCK_DCHUB_DRAM_REGS__SHIFT 0x1c
+#define DCHUB_DRAM_APER_BASE__BASE_MASK 0x00FFFFFFL
+#define DCHUB_DRAM_APER_BASE__LOCK_DCHUB_DRAM_REGS_MASK 0x10000000L
+//DCHUB_DRAM_APER_DEF
+#define DCHUB_DRAM_APER_DEF__DEF__SHIFT 0x0
+#define DCHUB_DRAM_APER_DEF__DEF_MASK 0xFFFFFFFFL
+//DCHUB_DRAM_APER_TOP
+#define DCHUB_DRAM_APER_TOP__TOP__SHIFT 0x0
+#define DCHUB_DRAM_APER_TOP__TOP_MASK 0x00FFFFFFL
+//DCHUB_CONTROL_STATUS
+#define DCHUB_CONTROL_STATUS__NO_OUTSTANDING_REQ__SHIFT 0x0
+#define DCHUB_CONTROL_STATUS__SDP_PORT_STATUS__SHIFT 0x4
+#define DCHUB_CONTROL_STATUS__SDP_DATA_RESPONSE_STATUS__SHIFT 0x6
+#define DCHUB_CONTROL_STATUS__SDP_REQ_CREDIT_ERROR__SHIFT 0x9
+#define DCHUB_CONTROL_STATUS__SDP_DATA_RESPONSE_STATUS_CLEAR__SHIFT 0xc
+#define DCHUB_CONTROL_STATUS__SDP_REQ_CREDIT_ERROR_CLEAR__SHIFT 0xd
+#define DCHUB_CONTROL_STATUS__FLUSH_REQ_CREDIT_EN__SHIFT 0x10
+#define DCHUB_CONTROL_STATUS__REQ_CREDIT_EN__SHIFT 0x11
+#define DCHUB_CONTROL_STATUS__DCE_PORT_CONTROL__SHIFT 0x12
+#define DCHUB_CONTROL_STATUS__SDP_CREDIT_DISCONNECT_DELAY__SHIFT 0x14
+#define DCHUB_CONTROL_STATUS__NO_OUTSTANDING_REQ_MASK 0x00000001L
+#define DCHUB_CONTROL_STATUS__SDP_PORT_STATUS_MASK 0x00000030L
+#define DCHUB_CONTROL_STATUS__SDP_DATA_RESPONSE_STATUS_MASK 0x000001C0L
+#define DCHUB_CONTROL_STATUS__SDP_REQ_CREDIT_ERROR_MASK 0x00000200L
+#define DCHUB_CONTROL_STATUS__SDP_DATA_RESPONSE_STATUS_CLEAR_MASK 0x00001000L
+#define DCHUB_CONTROL_STATUS__SDP_REQ_CREDIT_ERROR_CLEAR_MASK 0x00002000L
+#define DCHUB_CONTROL_STATUS__FLUSH_REQ_CREDIT_EN_MASK 0x00010000L
+#define DCHUB_CONTROL_STATUS__REQ_CREDIT_EN_MASK 0x00020000L
+#define DCHUB_CONTROL_STATUS__DCE_PORT_CONTROL_MASK 0x00040000L
+#define DCHUB_CONTROL_STATUS__SDP_CREDIT_DISCONNECT_DELAY_MASK 0x03F00000L
+//WB_ENABLE
+#define WB_ENABLE__WB_ENABLE__SHIFT 0x0
+#define WB_ENABLE__WB_ENABLE_MASK 0x00000001L
+//WB_EC_CONFIG
+#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT 0x0
+#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT 0x1
+#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT 0x2
+#define WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT 0x3
+#define WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT 0x7
+#define WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT 0x8
+#define WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT 0x9
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT 0xc
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT 0xe
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT 0xf
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_SM__SHIFT 0x11
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_BG__SHIFT 0x13
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT 0x15
+#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT 0x17
+#define WB_EC_CONFIG__LB_MEM_PWR_STATE_SM__SHIFT 0x18
+#define WB_EC_CONFIG__LB_MEM_PWR_STATE_BG__SHIFT 0x1a
+#define WB_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c
+#define WB_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e
+#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK 0x00000001L
+#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK 0x00000002L
+#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK 0x00000004L
+#define WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK 0x00000078L
+#define WB_EC_CONFIG__WB_LB_LS_DIS_MASK 0x00000080L
+#define WB_EC_CONFIG__WB_LB_SD_DIS_MASK 0x00000100L
+#define WB_EC_CONFIG__WB_LUT_LS_DIS_MASK 0x00000200L
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x00003000L
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK 0x00004000L
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK 0x00018000L
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_SM_MASK 0x00060000L
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_BG_MASK 0x00180000L
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK 0x00600000L
+#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK 0x00800000L
+#define WB_EC_CONFIG__LB_MEM_PWR_STATE_SM_MASK 0x03000000L
+#define WB_EC_CONFIG__LB_MEM_PWR_STATE_BG_MASK 0x0C000000L
+#define WB_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000L
+#define WB_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xC0000000L
+//CNV_MODE
+#define CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT 0x8
+#define CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT 0xc
+#define CNV_MODE__CNV_STEREO_TYPE__SHIFT 0xd
+#define CNV_MODE__CNV_INTERLACED_MODE__SHIFT 0xf
+#define CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10
+#define CNV_MODE__CNV_STEREO_POLARITY__SHIFT 0x12
+#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT 0x13
+#define CNV_MODE__CNV_STEREO_SPLIT__SHIFT 0x14
+#define CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18
+#define CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT 0x1f
+#define CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK 0x00000300L
+#define CNV_MODE__CNV_WINDOW_CROP_EN_MASK 0x00001000L
+#define CNV_MODE__CNV_STEREO_TYPE_MASK 0x00006000L
+#define CNV_MODE__CNV_INTERLACED_MODE_MASK 0x00008000L
+#define CNV_MODE__CNV_EYE_SELECTION_MASK 0x00030000L
+#define CNV_MODE__CNV_STEREO_POLARITY_MASK 0x00040000L
+#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK 0x00080000L
+#define CNV_MODE__CNV_STEREO_SPLIT_MASK 0x00100000L
+#define CNV_MODE__CNV_NEW_CONTENT_MASK 0x01000000L
+#define CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK 0x80000000L
+//CNV_WINDOW_START
+#define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0
+#define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10
+#define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0x00000FFFL
+#define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0x0FFF0000L
+//CNV_WINDOW_SIZE
+#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0
+#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10
+#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0x00000FFFL
+#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0x0FFF0000L
+//CNV_UPDATE
+#define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0
+#define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8
+#define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10
+#define CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x00000001L
+#define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x00000100L
+#define CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x00010000L
+//CNV_SOURCE_SIZE
+#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0
+#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10
+#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x00007FFFL
+#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7FFF0000L
+//CNV_CSC_CONTROL
+#define CNV_CSC_CONTROL__CNV_CSC_BYPASS__SHIFT 0x0
+#define CNV_CSC_CONTROL__CNV_CSC_BYPASS_MASK 0x00000001L
+//CNV_CSC_C11_C12
+#define CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0
+#define CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10
+#define CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x00001FFFL
+#define CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1FFF0000L
+//CNV_CSC_C13_C14
+#define CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0
+#define CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10
+#define CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x00001FFFL
+#define CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7FFF0000L
+//CNV_CSC_C21_C22
+#define CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0
+#define CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10
+#define CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x00001FFFL
+#define CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1FFF0000L
+//CNV_CSC_C23_C24
+#define CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0
+#define CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10
+#define CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x00001FFFL
+#define CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7FFF0000L
+//CNV_CSC_C31_C32
+#define CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0
+#define CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10
+#define CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x00001FFFL
+#define CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1FFF0000L
+//CNV_CSC_C33_C34
+#define CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0
+#define CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10
+#define CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x00001FFFL
+#define CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7FFF0000L
+//CNV_CSC_ROUND_OFFSET_R
+#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0
+#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0x0000FFFFL
+//CNV_CSC_ROUND_OFFSET_G
+#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0
+#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0x0000FFFFL
+//CNV_CSC_ROUND_OFFSET_B
+#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0
+#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0x0000FFFFL
+//CNV_CSC_CLAMP_R
+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0
+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10
+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0x0000FFFFL
+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xFFFF0000L
+//CNV_CSC_CLAMP_G
+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0
+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10
+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0x0000FFFFL
+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xFFFF0000L
+//CNV_CSC_CLAMP_B
+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0
+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10
+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0x0000FFFFL
+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xFFFF0000L
+//CNV_TEST_CNTL
+#define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4
+#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8
+#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10
+#define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x00000010L
+#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x00000100L
+#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x00010000L
+//CNV_TEST_CRC_RED
+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x4
+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10
+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0x0000FFF0L
+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xFFFF0000L
+//CNV_TEST_CRC_GREEN
+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x4
+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10
+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0x0000FFF0L
+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xFFFF0000L
+//CNV_TEST_CRC_BLUE
+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x4
+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10
+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0x0000FFF0L
+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xFFFF0000L
+//CNV_INPUT_SELECT
+#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT__SHIFT 0x0
+#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT__SHIFT 0x2
+#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT_MASK 0x00000003L
+#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT_MASK 0x0000001CL
+//WB_SOFT_RESET
+#define WB_SOFT_RESET__WB_SOFT_RESET__SHIFT 0x0
+#define WB_SOFT_RESET__WB_SOFT_RESET_MASK 0x00000001L
+//WB_WARM_UP_MODE_CTL1
+#define WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP__SHIFT 0x0
+#define WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP__SHIFT 0x10
+#define WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE__SHIFT 0x1f
+#define WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP_MASK 0x00007FFFL
+#define WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP_MASK 0x7FFF0000L
+#define WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE_MASK 0x80000000L
+//WB_WARM_UP_MODE_CTL2
+#define WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP__SHIFT 0x0
+#define WB_WARM_UP_MODE_CTL2__MODE_WARMUP__SHIFT 0x8
+#define WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP_MASK 0x000000FFL
+#define WB_WARM_UP_MODE_CTL2__MODE_WARMUP_MASK 0x00000100L
+//WBSCL_COEF_RAM_SELECT
+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE__SHIFT 0x8
+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10
+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000007L
+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE_MASK 0x00000F00L
+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE_MASK 0x00030000L
+//WBSCL_COEF_RAM_TAP_DATA
+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+//WBSCL_MODE
+#define WBSCL_MODE__WBSCL_MODE__SHIFT 0x0
+#define WBSCL_MODE__WBSCL_MODE_MASK 0x00000003L
+//WBSCL_TAP_CONTROL
+#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB__SHIFT 0x0
+#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR__SHIFT 0x4
+#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB__SHIFT 0x8
+#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR__SHIFT 0xc
+#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB_MASK 0x0000000FL
+#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR_MASK 0x000000F0L
+#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB_MASK 0x00000F00L
+#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR_MASK 0x0000F000L
+//WBSCL_DEST_SIZE
+#define WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT__SHIFT 0x0
+#define WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH__SHIFT 0x10
+#define WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT_MASK 0x00007FFFL
+#define WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH_MASK 0x7FFF0000L
+//WBSCL_HORZ_FILTER_SCALE_RATIO
+#define WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO__SHIFT 0x0
+#define WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO_MASK 0x07FFFFFFL
+//WBSCL_HORZ_FILTER_INIT_Y_RGB
+#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB__SHIFT 0x0
+#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB__SHIFT 0x18
+#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB_MASK 0x00FFFFFFL
+#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB_MASK 0x1F000000L
+//WBSCL_HORZ_FILTER_INIT_CBCR
+#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR__SHIFT 0x0
+#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR__SHIFT 0x18
+#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR_MASK 0x00FFFFFFL
+#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR_MASK 0x1F000000L
+//WBSCL_VERT_FILTER_SCALE_RATIO
+#define WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO__SHIFT 0x0
+#define WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO_MASK 0x07FFFFFFL
+//WBSCL_VERT_FILTER_INIT_Y_RGB
+#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB__SHIFT 0x0
+#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB__SHIFT 0x18
+#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB_MASK 0x00FFFFFFL
+#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB_MASK 0x1F000000L
+//WBSCL_VERT_FILTER_INIT_CBCR
+#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR__SHIFT 0x0
+#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR__SHIFT 0x18
+#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR_MASK 0x00FFFFFFL
+#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR_MASK 0x1F000000L
+//WBSCL_ROUND_OFFSET
+#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB__SHIFT 0x0
+#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB_MASK 0x0000FFFFL
+#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
+//WBSCL_CLAMP
+#define WBSCL_CLAMP__WBSCL_CLAMP_UPPER_Y_RGB__SHIFT 0x0
+#define WBSCL_CLAMP__WBSCL_CLAMP_LOWER_Y_RGB__SHIFT 0x8
+#define WBSCL_CLAMP__WBSCL_CLAMP_UPPER_CBCR__SHIFT 0x10
+#define WBSCL_CLAMP__WBSCL_CLAMP_LOWER_CBCR__SHIFT 0x18
+#define WBSCL_CLAMP__WBSCL_CLAMP_UPPER_Y_RGB_MASK 0x000000FFL
+#define WBSCL_CLAMP__WBSCL_CLAMP_LOWER_Y_RGB_MASK 0x0000FF00L
+#define WBSCL_CLAMP__WBSCL_CLAMP_UPPER_CBCR_MASK 0x00FF0000L
+#define WBSCL_CLAMP__WBSCL_CLAMP_LOWER_CBCR_MASK 0xFF000000L
+//WBSCL_OVERFLOW_STATUS
+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG__SHIFT 0x0
+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK__SHIFT 0x8
+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK__SHIFT 0xc
+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS__SHIFT 0x10
+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE__SHIFT 0x14
+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG_MASK 0x00000001L
+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK_MASK 0x00000100L
+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK_MASK 0x00001000L
+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS_MASK 0x00010000L
+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE_MASK 0x00100000L
+//WBSCL_COEF_RAM_CONFLICT_STATUS
+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG__SHIFT 0x0
+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK__SHIFT 0x8
+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK__SHIFT 0xc
+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE__SHIFT 0x14
+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK_MASK 0x00000100L
+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK_MASK 0x00001000L
+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE_MASK 0x00100000L
+//WBSCL_OUTSIDE_PIX_STRATEGY
+#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY__SHIFT 0x0
+#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_B_CB__SHIFT 0x8
+#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y__SHIFT 0x10
+#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_R_CR__SHIFT 0x18
+#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY_MASK 0x00000001L
+#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_B_CB_MASK 0x0000FF00L
+#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y_MASK 0x00FF0000L
+#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_R_CR_MASK 0xFF000000L
+//WBSCL_TEST_CNTL
+#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN__SHIFT 0x4
+#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN__SHIFT 0x8
+#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_DE_ONLY__SHIFT 0x10
+#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN_MASK 0x00000010L
+#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN_MASK 0x00000100L
+#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_DE_ONLY_MASK 0x00010000L
+//WBSCL_TEST_CRC_RED
+#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK__SHIFT 0x8
+#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED__SHIFT 0x10
+#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK_MASK 0x0000FF00L
+#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED_MASK 0xFFFF0000L
+//WBSCL_TEST_CRC_GREEN
+#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK__SHIFT 0x0
+#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN__SHIFT 0x10
+#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK_MASK 0x0000FFFFL
+#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN_MASK 0xFFFF0000L
+//WBSCL_TEST_CRC_BLUE
+#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK__SHIFT 0x8
+#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE__SHIFT 0x10
+#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK_MASK 0x0000FF00L
+#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE_MASK 0xFFFF0000L
+//WBSCL_BACKPRESSURE_CNT_EN
+#define WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN__SHIFT 0x0
+#define WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN_MASK 0x00000001L
+//WB_MCIF_BACKPRESSURE_CNT
+#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE__SHIFT 0x0
+#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE__SHIFT 0x10
+#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE_MASK 0x0000FFFFL
+#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE_MASK 0xFFFF0000L
+//WBSCL_RAM_SHUTDOWN
+#define WBSCL_RAM_SHUTDOWN__WBSCL_RAM_SHUTDOWN_SEL__SHIFT 0x0
+#define WBSCL_RAM_SHUTDOWN__WBSCL_RAM_SHUTDOWN_SEL_MASK 0x00000003L
+//DMCU_CTRL
+#define DMCU_CTRL__RESET_UC__SHIFT 0x0
+#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1
+#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2
+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3
+#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4
+#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT 0x8
+#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x10
+#define DMCU_CTRL__RESET_UC_MASK 0x00000001L
+#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x00000002L
+#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x00000004L
+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x00000008L
+#define DMCU_CTRL__DMCU_ENABLE_MASK 0x00000010L
+#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK 0x00000100L
+#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xFFFF0000L
+//DMCU_STATUS
+#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0
+#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1
+#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2
+#define DMCU_STATUS__UC_IN_RESET_MASK 0x00000001L
+#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x00000002L
+#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x00000004L
+//DMCU_PC_START_ADDR
+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0
+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8
+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0x000000FFL
+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0x0000FF00L
+//DMCU_FW_START_ADDR
+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0
+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8
+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0x000000FFL
+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0x0000FF00L
+//DMCU_FW_END_ADDR
+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0
+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8
+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0x000000FFL
+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0x0000FF00L
+//DMCU_FW_ISR_START_ADDR
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0x000000FFL
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0x0000FF00L
+//DMCU_FW_CS_HI
+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0
+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xFFFFFFFFL
+//DMCU_FW_CS_LO
+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0
+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xFFFFFFFFL
+//DMCU_RAM_ACCESS_CTRL
+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0
+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1
+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2
+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3
+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4
+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5
+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x00000001L
+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x00000002L
+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x00000004L
+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x00000008L
+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x00000010L
+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x00000020L
+//DMCU_ERAM_WR_CTRL
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0x0000FFFFL
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0x000F0000L
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x00100000L
+//DMCU_ERAM_WR_DATA
+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0
+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xFFFFFFFFL
+//DMCU_ERAM_RD_CTRL
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0x0000FFFFL
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0x000F0000L
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x00100000L
+//DMCU_ERAM_RD_DATA
+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0
+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xFFFFFFFFL
+//DMCU_IRAM_WR_CTRL
+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0
+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x000003FFL
+//DMCU_IRAM_WR_DATA
+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0
+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0x000000FFL
+//DMCU_IRAM_RD_CTRL
+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0
+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x000003FFL
+//DMCU_IRAM_RD_DATA
+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0
+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0x000000FFL
+//DMCU_EVENT_TRIGGER
+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0
+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10
+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17
+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x00000001L
+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x007F0000L
+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x00800000L
+//DMCU_UC_INTERNAL_INT_STATUS
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x00000001L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x00000002L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x00000004L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x00000008L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x00000010L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x00000020L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x00000040L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x00000080L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x00000100L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x00000200L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x00000400L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x00000800L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x00001000L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x00002000L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x00004000L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x00008000L
+//DMCU_SS_INTERRUPT_CNTL_STATUS
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x00002000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x00004000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x00004000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x00008000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x00010000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x00010000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x00020000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x00040000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x00040000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x00080000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x00100000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x00100000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x00200000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x00400000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x00400000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x00800000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x01000000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x01000000L
+//DMCU_INTERRUPT_STATUS
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2
+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED__SHIFT 0x4
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR__SHIFT 0x4
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0x5
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x5
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8
+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0xc
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0xc
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0xd
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0xd
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0xe
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0xe
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0xf
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xf
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x10
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x10
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x11
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x11
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x12
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x13
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x14
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x15
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x16
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x00000001L
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x00000001L
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x00000002L
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x00000002L
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x00000004L
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x00000004L
+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x00000008L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED_MASK 0x00000010L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR_MASK 0x00000010L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR_MASK 0x00000020L
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x00000100L
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x00000100L
+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x00000200L
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x00000400L
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x00000400L
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x00000800L
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x00000800L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x00001000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x00001000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x00002000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x00002000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x00004000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x00004000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x00008000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x00008000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x00010000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x00010000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x00020000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x00020000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x00040000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x00080000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x00100000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x00100000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x00200000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x00200000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x00400000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x00400000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x00800000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x01000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x01000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x02000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x02000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x04000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x04000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x08000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x08000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000L
+//DMCU_INTERRUPT_TO_HOST_EN_MASK
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x2
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x00000001L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x00000002L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x00000004L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x00000200L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x00000400L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x00000800L
+//DMCU_INTERRUPT_TO_UC_EN_MASK
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x1e
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x00000001L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x00000002L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x00000004L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x00000008L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN_MASK 0x00000010L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000020L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x00000040L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x00000080L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x00000100L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x00000200L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x00000400L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x00000800L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x00001000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x00002000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x00004000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x00008000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x00010000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x00020000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x00100000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x00200000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x00400000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x00800000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x01000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x02000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x04000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x08000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x40000000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0x1e
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00800000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x01000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x02000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x08000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x40000000L
+//DC_DMCU_SCRATCH
+#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0
+#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xFFFFFFFFL
+//DMCU_INT_CNT
+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0
+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8
+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10
+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0x000000FFL
+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0x0000FF00L
+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0x00FF0000L
+//DMCU_FW_CHECKSUM_SMPL_BYTE_POS
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x00000003L
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0x0000000CL
+//DMCU_UC_CLK_GATING_CNTL
+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0
+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8
+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10
+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x00000007L
+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x00000700L
+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x00010000L
+//MASTER_COMM_DATA_REG1
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0x000000FFL
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0x0000FF00L
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0x00FF0000L
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xFF000000L
+//MASTER_COMM_DATA_REG2
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0x000000FFL
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0x0000FF00L
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0x00FF0000L
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xFF000000L
+//MASTER_COMM_DATA_REG3
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0x000000FFL
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0x0000FF00L
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0x00FF0000L
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xFF000000L
+//MASTER_COMM_CMD_REG
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0x000000FFL
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0x0000FF00L
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0x00FF0000L
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xFF000000L
+//MASTER_COMM_CNTL_REG
+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0
+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L
+//SLAVE_COMM_DATA_REG1
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0x000000FFL
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0x0000FF00L
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0x00FF0000L
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xFF000000L
+//SLAVE_COMM_DATA_REG2
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0x000000FFL
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0x0000FF00L
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0x00FF0000L
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xFF000000L
+//SLAVE_COMM_DATA_REG3
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0x000000FFL
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0x0000FF00L
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0x00FF0000L
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xFF000000L
+//SLAVE_COMM_CMD_REG
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0x000000FFL
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0x0000FF00L
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0x00FF0000L
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xFF000000L
+//SLAVE_COMM_CNTL_REG
+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0
+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8
+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x00000001L
+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x00000100L
+//BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0
+#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL
+//BL1_PWM_USER_LEVEL
+#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0
+#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL
+//BL1_PWM_TARGET_ABM_LEVEL
+#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0
+#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL
+//BL1_PWM_CURRENT_ABM_LEVEL
+#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0
+#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL
+//BL1_PWM_FINAL_DUTY_CYCLE
+#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0
+#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL
+//BL1_PWM_MINIMUM_DUTY_CYCLE
+#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0
+#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL
+//BL1_PWM_ABM_CNTL
+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0
+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10
+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L
+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L
+//BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
+//BL1_PWM_GRP2_REG_LOCK
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L
+//DMCU_INTERRUPT_TO_UC_EN_MASK_1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV0_VBLANK_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_UP_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV1_VBLANK_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC0_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC1_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC2_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC3_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC4_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC5_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN_MASK 0x00000001L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000002L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV0_VBLANK_INT_TO_UC_EN_MASK 0x00000004L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_UP_INT_TO_UC_EN_MASK 0x00000008L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000010L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV1_VBLANK_INT_TO_UC_EN_MASK 0x00000020L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC0_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000040L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000080L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC2_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000100L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC3_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000200L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC4_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000400L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__CRTC5_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000800L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN_MASK 0x00002000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV1_VBLANK_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV1_VBLANK_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__CRTC5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
+//DMCU_INTERRUPT_STATUS_1
+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED__SHIFT 0x0
+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR__SHIFT 0x0
+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_OCCURRED__SHIFT 0x1
+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_CLEAR__SHIFT 0x1
+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED__SHIFT 0x2
+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR__SHIFT 0x2
+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3
+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_CLEAR__SHIFT 0x3
+#define DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_OCCURRED__SHIFT 0x4
+#define DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_CLEAR__SHIFT 0x4
+#define DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_OCCURRED__SHIFT 0x5
+#define DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_CLEAR__SHIFT 0x5
+#define DMCU_INTERRUPT_STATUS_1__CRTC0_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x6
+#define DMCU_INTERRUPT_STATUS_1__CRTC0_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x6
+#define DMCU_INTERRUPT_STATUS_1__CRTC1_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x7
+#define DMCU_INTERRUPT_STATUS_1__CRTC1_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x7
+#define DMCU_INTERRUPT_STATUS_1__CRTC2_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x8
+#define DMCU_INTERRUPT_STATUS_1__CRTC2_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x8
+#define DMCU_INTERRUPT_STATUS_1__CRTC3_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x9
+#define DMCU_INTERRUPT_STATUS_1__CRTC3_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x9
+#define DMCU_INTERRUPT_STATUS_1__CRTC4_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0xa
+#define DMCU_INTERRUPT_STATUS_1__CRTC4_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0xa
+#define DMCU_INTERRUPT_STATUS_1__CRTC5_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0xb
+#define DMCU_INTERRUPT_STATUS_1__CRTC5_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0xb
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED__SHIFT 0xd
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR__SHIFT 0xd
+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED_MASK 0x00000001L
+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR_MASK 0x00000001L
+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_OCCURRED_MASK 0x00000002L
+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_CLEAR_MASK 0x00000002L
+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED_MASK 0x00000004L
+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR_MASK 0x00000004L
+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L
+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_CLEAR_MASK 0x00000008L
+#define DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_OCCURRED_MASK 0x00000010L
+#define DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_CLEAR_MASK 0x00000010L
+#define DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_OCCURRED_MASK 0x00000020L
+#define DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_CLEAR_MASK 0x00000020L
+#define DMCU_INTERRUPT_STATUS_1__CRTC0_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000040L
+#define DMCU_INTERRUPT_STATUS_1__CRTC0_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000040L
+#define DMCU_INTERRUPT_STATUS_1__CRTC1_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000080L
+#define DMCU_INTERRUPT_STATUS_1__CRTC1_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000080L
+#define DMCU_INTERRUPT_STATUS_1__CRTC2_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000100L
+#define DMCU_INTERRUPT_STATUS_1__CRTC2_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000100L
+#define DMCU_INTERRUPT_STATUS_1__CRTC3_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000200L
+#define DMCU_INTERRUPT_STATUS_1__CRTC3_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000200L
+#define DMCU_INTERRUPT_STATUS_1__CRTC4_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000400L
+#define DMCU_INTERRUPT_STATUS_1__CRTC4_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000400L
+#define DMCU_INTERRUPT_STATUS_1__CRTC5_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000800L
+#define DMCU_INTERRUPT_STATUS_1__CRTC5_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000800L
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED_MASK 0x00002000L
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR_MASK 0x00002000L
+//DMCU_DPRX_INTERRUPT_STATUS1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x0
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x0
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT 0x2
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT 0x2
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT 0x3
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT 0x3
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x4
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x4
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x5
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x5
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x6
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x6
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT 0x7
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT 0x7
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT 0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT 0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x9
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x9
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xa
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xa
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xb
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xb
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xc
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xc
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xd
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xd
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xe
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xe
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xf
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xf
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0x10
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0x10
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT 0x11
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT 0x11
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT 0x12
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT 0x12
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT 0x13
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT 0x13
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT 0x14
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT 0x14
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT 0x15
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT 0x15
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT 0x16
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT 0x16
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT 0x17
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT 0x17
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT 0x18
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT 0x18
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT 0x19
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT 0x19
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT 0x1a
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT 0x1b
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT 0x1b
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT 0x1c
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT 0x1c
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x00000001L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK 0x00000001L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x00000002L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x00000002L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK 0x00000004L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK 0x00000004L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK 0x00000008L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK 0x00000008L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x00000010L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK 0x00000010L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x00000020L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK 0x00000020L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x00000040L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x00000040L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK 0x00000080L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK 0x00000080L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK 0x00000100L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK 0x00000100L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x00000200L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK 0x00000200L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00000400L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00000400L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00000800L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00000800L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00001000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00001000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00002000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00002000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00004000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00004000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00008000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00008000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00010000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00010000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK 0x00020000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK 0x00020000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK 0x00040000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK 0x00040000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK 0x00080000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK 0x00080000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK 0x00100000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK 0x00100000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK 0x00200000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK 0x00200000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK 0x00400000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK 0x00400000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK 0x00800000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK 0x00800000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK 0x01000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK 0x01000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK 0x02000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x02000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK 0x04000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK 0x04000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK 0x08000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK 0x08000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK 0x10000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK 0x10000000L
+//DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x2
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x3
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x7
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x8
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1b
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1c
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x00000001L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x00000002L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK 0x00000004L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK 0x00000008L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x00000010L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x00000020L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x00000040L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK 0x00000080L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK 0x00000100L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x00000200L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00000400L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00000800L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00001000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00002000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00004000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00008000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00010000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK 0x00020000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK 0x00040000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK 0x00080000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK 0x00100000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK 0x00200000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK 0x00400000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK 0x00800000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK 0x01000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK 0x02000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK 0x04000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK 0x08000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK 0x10000000L
+//DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1b
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1c
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x00000004L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x00000008L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x00000080L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x00000100L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK 0x00800000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK 0x01000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x02000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x08000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x10000000L
+//DC_ABM1_CNTL
+#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0
+#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8
+#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x1f
+#define DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L
+#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x00000700L
+#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000L
+//DC_ABM1_IPCSC_COEFF_SEL
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
+//DC_ABM1_ACE_OFFSET_SLOPE_0
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L
+//DC_ABM1_ACE_OFFSET_SLOPE_1
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L
+//DC_ABM1_ACE_OFFSET_SLOPE_2
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L
+//DC_ABM1_ACE_OFFSET_SLOPE_3
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L
+//DC_ABM1_ACE_OFFSET_SLOPE_4
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L
+//DC_ABM1_ACE_THRES_12
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L
+//DC_ABM1_ACE_THRES_34
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L
+//DC_ABM1_ACE_CNTL_MISC
+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0
+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8
+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L
+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L
+//DMCU_PERFMON_INTERRUPT_STATUS5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000200L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000200L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000400L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000400L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000800L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000800L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00001000L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00001000L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00002000L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00002000L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00004000L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00004000L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00008000L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00008000L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x00010000L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x00010000L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x00020000L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x00020000L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000200L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000400L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000800L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00001000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00002000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00004000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00008000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00010000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x00020000L
+//DMCU_PERFMON_INTERRUPT_STATUS1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000200L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000200L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000400L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000400L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000800L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000800L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00001000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00001000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00002000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00002000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00004000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00004000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00008000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00008000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00010000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00010000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00020000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00020000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00040000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00040000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00080000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00080000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00100000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00100000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00200000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00200000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00400000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00400000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00800000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00800000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x01000000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x01000000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x02000000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x02000000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x04000000L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x04000000L
+//DMCU_PERFMON_INTERRUPT_STATUS2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000200L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000200L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000400L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000400L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000800L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000800L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00001000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00001000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00002000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00002000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00004000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00004000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00008000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00008000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00010000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00010000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00020000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00020000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00040000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00040000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00080000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00080000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00100000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00100000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00200000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00200000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00400000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00400000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00800000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00800000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x01000000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x01000000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x02000000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x02000000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x04000000L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x04000000L
+//DMCU_PERFMON_INTERRUPT_STATUS3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000200L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000200L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000400L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000400L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000800L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000800L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00001000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00001000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00002000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00002000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00004000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00004000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00008000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00008000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00010000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00010000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00020000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00020000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00040000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00040000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00080000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00080000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00100000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00100000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00200000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00200000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00400000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00400000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00800000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00800000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x01000000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x01000000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x02000000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x02000000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x04000000L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x04000000L
+//DMCU_PERFMON_INTERRUPT_STATUS4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_OCCURRED__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_CLEAR__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_OCCURRED__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_CLEAR__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_OCCURRED__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_CLEAR__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_OCCURRED__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_CLEAR__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_OCCURRED__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_CLEAR__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_OCCURRED__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_CLEAR__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_OCCURRED__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_CLEAR__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_OCCURRED__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_CLEAR__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x00000200L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR_MASK 0x00000200L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x00000400L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR_MASK 0x00000400L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x00000800L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR_MASK 0x00000800L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x00001000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR_MASK 0x00001000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x00002000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR_MASK 0x00002000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x00004000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR_MASK 0x00004000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x00008000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR_MASK 0x00008000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_OCCURRED_MASK 0x00010000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_CLEAR_MASK 0x00010000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_OCCURRED_MASK 0x00020000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_CLEAR_MASK 0x00020000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_OCCURRED_MASK 0x00040000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_CLEAR_MASK 0x00040000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_OCCURRED_MASK 0x00080000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_CLEAR_MASK 0x00080000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_OCCURRED_MASK 0x00100000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_CLEAR_MASK 0x00100000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_OCCURRED_MASK 0x00200000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_CLEAR_MASK 0x00200000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_OCCURRED_MASK 0x00400000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_CLEAR_MASK 0x00400000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_OCCURRED_MASK 0x00800000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_CLEAR_MASK 0x00800000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x01000000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x01000000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x02000000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x02000000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_OCCURRED_MASK 0x04000000L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_CLEAR_MASK 0x04000000L
+//DC_ABM1_HGLS_REG_READ_PROGRESS
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L
+//DC_ABM1_HG_MISC_CTRL
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10
+#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L
+#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
+//DC_ABM1_LS_SUM_OF_LUMA
+#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0
+#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL
+//DC_ABM1_LS_MIN_MAX_LUMA
+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0
+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10
+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL
+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L
+//DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0
+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10
+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL
+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L
+//DC_ABM1_LS_PIXEL_COUNT
+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0
+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL
+//DC_ABM1_LS_OVR_SCAN_BIN
+#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x0
+#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0x00FFFFFFL
+//DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
+//DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0
+#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL
+//DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0
+#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL
+//DC_ABM1_HG_SAMPLE_RATE
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
+//DC_ABM1_LS_SAMPLE_RATE
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
+//DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0
+#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0
+#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0
+#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0
+#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0
+#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_1
+#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_2
+#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_3
+#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_4
+#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_5
+#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_6
+#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_7
+#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_8
+#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_9
+#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_10
+#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_11
+#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_12
+#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_13
+#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_14
+#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_15
+#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_16
+#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_17
+#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_18
+#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_19
+#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_20
+#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_21
+#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_22
+#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_23
+#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_24
+#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000200L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000400L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000800L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00001000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00002000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00004000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00008000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00010000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00020000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00040000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00080000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00100000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00200000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00400000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00800000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x01000000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x02000000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x04000000L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000200L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000400L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000800L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00001000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00002000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00004000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00008000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00010000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00020000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00040000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00080000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00100000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00200000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00400000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00800000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x01000000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x02000000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x04000000L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000200L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000400L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000800L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00001000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00002000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00004000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00008000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00010000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00020000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00040000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00080000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00100000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00200000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00400000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00800000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x01000000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x02000000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x04000000L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x00000200L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x00000400L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x00000800L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x00001000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x00002000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x00004000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x00008000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER0_INT_TO_UC_EN_MASK 0x00010000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER1_INT_TO_UC_EN_MASK 0x00020000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER2_INT_TO_UC_EN_MASK 0x00040000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER3_INT_TO_UC_EN_MASK 0x00080000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER4_INT_TO_UC_EN_MASK 0x00100000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER5_INT_TO_UC_EN_MASK 0x00200000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER6_INT_TO_UC_EN_MASK 0x00400000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER7_INT_TO_UC_EN_MASK 0x00800000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x01000000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x02000000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_OFF_INT_TO_UC_EN_MASK 0x04000000L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00800000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x01000000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x02000000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00800000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x01000000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x02000000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00800000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x01000000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x02000000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x00800000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x01000000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x02000000L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
+//DC_ABM1_OVERSCAN_PIXEL_VALUE
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x0
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0xa
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x14
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x000003FFL
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0x000FFC00L
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3FF00000L
+//DC_ABM1_BL_MASTER_LOCK
+#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f
+#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L
+//AZALIA_CONTROLLER_CLOCK_GATING
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x00000001L
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x00000010L
+//AZALIA_AUDIO_DTO
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0x0000FFFFL
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xFFFF0000L
+//AZALIA_AUDIO_DTO_CONTROL
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x00000300L
+//AZALIA_SOCCLK_CONTROL
+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT 0x1
+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK 0x00000002L
+//AZALIA_UNDERFLOW_FILLER_SAMPLE
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xFFFFFFFFL
+//AZALIA_DATA_DMA_CONTROL
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x00000003L
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0x0000000CL
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x00000030L
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0x000000C0L
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x00010000L
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x00020000L
+//AZALIA_BDL_DMA_CONTROL
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x00000003L
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0x0000000CL
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x00000030L
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0x000000C0L
+//AZALIA_RIRB_AND_DP_CONTROL
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x00000001L
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x00000010L
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x000001E0L
+//AZALIA_CORB_DMA_CONTROL
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x00000001L
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x00000010L
+//AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xFFFFFFFFL
+//AZALIA_CYCLIC_BUFFER_SYNC
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x00000001L
+//AZALIA_GLOBAL_CAPABILITIES
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x00000006L
+//AZALIA_OUTPUT_PAYLOAD_CAPABILITY
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xFFFF0000L
+//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0x000000FFL
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x00000100L
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0x00FF0000L
+//AZALIA_INPUT_PAYLOAD_CAPABILITY
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xFFFF0000L
+//AZALIA_INPUT_CRC0_CONTROL0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L
+//AZALIA_INPUT_CRC0_CONTROL1
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CONTROL2
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL
+//AZALIA_INPUT_CRC0_CONTROL3
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L
+//AZALIA_INPUT_CRC0_RESULT
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CONTROL0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L
+//AZALIA_INPUT_CRC1_CONTROL1
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CONTROL2
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL
+//AZALIA_INPUT_CRC1_CONTROL3
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L
+//AZALIA_INPUT_CRC1_RESULT
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL
+//AZALIA_CRC0_CONTROL0
+#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
+#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x00000001L
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L
+//AZALIA_CRC0_CONTROL1
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL
+//AZALIA_CRC0_CONTROL2
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL
+//AZALIA_CRC0_CONTROL3
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x00000001L
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L
+//AZALIA_CRC0_RESULT
+#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0
+#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL
+//AZALIA_CRC1_CONTROL0
+#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
+#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x00000001L
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L
+//AZALIA_CRC1_CONTROL1
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL
+//AZALIA_CRC1_CONTROL2
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL
+//AZALIA_CRC1_CONTROL3
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x00000001L
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L
+//AZALIA_CRC1_RESULT
+#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0
+#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL
+//AZALIA_MEM_PWR_CTRL
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x00000003L
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x00000004L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x00000018L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x00000020L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0x000000C0L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x00000100L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x00000600L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x00000800L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x00003000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x00004000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x00018000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x00020000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0x000C0000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x00100000L
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000L
+//AZALIA_MEM_PWR_STATUS
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x00000003L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0x0000000CL
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x00000030L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0x000000C0L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x00000300L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0x00000C00L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x00003000L
+//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL
+//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL
+//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x00000007L
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x00000070L
+//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x0000003FL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL
+//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x00000007L
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L
+//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x00000007L
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L
+//AZALIA_F0_GTC_GROUP_OFFSET0
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET1
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET2
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET3
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET4
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET5
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET6
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xFFFFFFFFL
+//REG_DC_AUDIO_PORT_CONNECTIVITY
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT 0x0
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK 0x00000007L
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L
+//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT 0x0
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK 0x00000007L
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L
+//DAC_ENABLE
+#define DAC_ENABLE__DAC_ENABLE__SHIFT 0x0
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x1
+#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x4
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x5
+#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x8
+#define DAC_ENABLE__DAC_ENABLE_MASK 0x00000001L
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x00000002L
+#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0x0000000CL
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x00000010L
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x00000020L
+#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x00000100L
+//DAC_SOURCE_SELECT
+#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x0
+#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x3
+#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x00000007L
+#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x00000008L
+//DAC_CRC_EN
+#define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x0
+#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x10
+#define DAC_CRC_EN__DAC_CRC_EN_MASK 0x00000001L
+#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x00010000L
+//DAC_CRC_CONTROL
+#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x0
+#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB__SHIFT 0x8
+#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x00000001L
+#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB_MASK 0x00000100L
+//DAC_CRC_SIG_RGB_MASK
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x0
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0xa
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x14
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x000003FFL
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0x000FFC00L
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3FF00000L
+//DAC_CRC_SIG_CONTROL_MASK
+#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x0
+#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x0000003FL
+//DAC_CRC_SIG_RGB
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x0
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0xa
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x14
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x000003FFL
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0x000FFC00L
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3FF00000L
+//DAC_CRC_SIG_CONTROL
+#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x0
+#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x0000003FL
+//DAC_SYNC_TRISTATE_CONTROL
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x0
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x8
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x10
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x00000001L
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x00000100L
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x00010000L
+//DAC_STEREOSYNC_SELECT
+#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x0
+#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x00000007L
+//DAC_AUTODETECT_CONTROL
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x0
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x8
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x10
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x00000003L
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0x0000FF00L
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x00070000L
+//DAC_AUTODETECT_CONTROL2
+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x0
+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x8
+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0x000000FFL
+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x00000100L
+//DAC_AUTODETECT_CONTROL3
+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x0
+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x8
+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0x000000FFL
+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0x0000FF00L
+//DAC_AUTODETECT_STATUS
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x0
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x4
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x8
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x10
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x18
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x00000001L
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x00000010L
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x00000300L
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x00030000L
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x03000000L
+//DAC_AUTODETECT_INT_CONTROL
+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x0
+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x10
+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x00000001L
+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x00010000L
+//DAC_FORCE_OUTPUT_CNTL
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x0
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x8
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY__SHIFT 0x18
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x00000001L
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x00000700L
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY_MASK 0x01000000L
+//DAC_FORCE_DATA
+#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x0
+#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x000003FFL
+//DAC_POWERDOWN
+#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x0
+#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x8
+#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x10
+#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x18
+#define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x00000001L
+#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x00000100L
+#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x00010000L
+#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x01000000L
+//DAC_CONTROL
+#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x0
+#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x8
+#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x10
+#define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x00000001L
+#define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x00000100L
+#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x00010000L
+//DAC_COMPARATOR_ENABLE
+#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x0
+#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x8
+#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x10
+#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x11
+#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x12
+#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x00000001L
+#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x00000100L
+#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x00010000L
+#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x00020000L
+#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x00040000L
+//DAC_COMPARATOR_OUTPUT
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x0
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x1
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x3
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x00000001L
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x00000002L
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x00000004L
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x00000008L
+//DAC_PWR_CNTL
+#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x0
+#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x10
+#define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x00000003L
+#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x00030000L
+//DAC_DFT_CONFIG
+#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x0
+#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xFFFFFFFFL
+//DAC_FIFO_STATUS
+#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x1d
+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0x000F0000L
+#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000L
+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+//DC_I2C_CONTROL
+#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14
+#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x00000001L
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x00000002L
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x00000004L
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x00000008L
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x00000700L
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x00300000L
+//DC_I2C_ARBITRATION
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x00000003L
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0x0000000CL
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x00000010L
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x00000100L
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x00001000L
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x00100000L
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x00200000L
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x01000000L
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x02000000L
+//DC_I2C_INTERRUPT_CONTROL
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x00000001L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x00000002L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x00000004L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x00000010L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x00000020L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x00000040L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x00000100L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x00000200L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x00000400L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x00001000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x00002000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x00004000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x00010000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x00020000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x00040000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x00100000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x00200000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x00400000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x01000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x02000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x04000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x08000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000L
+//DC_I2C_SW_STATUS
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x00000003L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x00000004L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x00000010L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x00000020L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x00000040L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x00000080L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x00000100L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x00001000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x00002000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x00004000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x00008000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x00040000L
+//DC_I2C_DDC1_HW_STATUS
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x00000003L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x00000008L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x00010000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x00020000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x00100000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000L
+//DC_I2C_DDC2_HW_STATUS
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x00000003L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x00000008L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x00010000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x00020000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x00100000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000L
+//DC_I2C_DDC3_HW_STATUS
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x00000003L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x00000008L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x00010000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x00020000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x00100000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000L
+//DC_I2C_DDC4_HW_STATUS
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x00000003L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x00000008L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x00010000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x00020000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x00100000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000L
+//DC_I2C_DDC5_HW_STATUS
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x00000003L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x00000008L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x00010000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x00020000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x00100000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000L
+//DC_I2C_DDC6_HW_STATUS
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x00000003L
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x00000008L
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x00010000L
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x00020000L
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x00100000L
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000L
+//DC_I2C_DDC1_SPEED
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x00000003L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x00000300L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xFFFF0000L
+//DC_I2C_DDC1_SETUP
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x00000001L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x00000002L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x00000010L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x00000020L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x00000040L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x00000080L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xFF000000L
+//DC_I2C_DDC2_SPEED
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x00000003L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x00000300L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xFFFF0000L
+//DC_I2C_DDC2_SETUP
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x00000001L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x00000002L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x00000010L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x00000020L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x00000040L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x00000080L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xFF000000L
+//DC_I2C_DDC3_SPEED
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x00000003L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x00000300L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xFFFF0000L
+//DC_I2C_DDC3_SETUP
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x00000001L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x00000002L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x00000010L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x00000020L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x00000040L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x00000080L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xFF000000L
+//DC_I2C_DDC4_SPEED
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x00000003L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x00000300L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xFFFF0000L
+//DC_I2C_DDC4_SETUP
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x00000001L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x00000002L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x00000010L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x00000020L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x00000040L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x00000080L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xFF000000L
+//DC_I2C_DDC5_SPEED
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x00000003L
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x00000300L
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xFFFF0000L
+//DC_I2C_DDC5_SETUP
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x00000001L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x00000002L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x00000010L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x00000020L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x00000040L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x00000080L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xFF000000L
+//DC_I2C_DDC6_SPEED
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x00000003L
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL_MASK 0x00000300L
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xFFFF0000L
+//DC_I2C_DDC6_SETUP
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x00000001L
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x00000002L
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x00000010L
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x00000020L
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x00000040L
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x00000080L
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xFF000000L
+//DC_I2C_TRANSACTION0
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8
+#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x00000001L
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x00000100L
+#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x00001000L
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x00002000L
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x03FF0000L
+//DC_I2C_TRANSACTION1
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8
+#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x00000001L
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x00000100L
+#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x00001000L
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x00002000L
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x03FF0000L
+//DC_I2C_TRANSACTION2
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8
+#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x00000001L
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x00000100L
+#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x00001000L
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x00002000L
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x03FF0000L
+//DC_I2C_TRANSACTION3
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8
+#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x00000001L
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x00000100L
+#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x00001000L
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x00002000L
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x03FF0000L
+//DC_I2C_DATA
+#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0
+#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8
+#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f
+#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x00000001L
+#define DC_I2C_DATA__DC_I2C_DATA_MASK 0x0000FF00L
+#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x03FF0000L
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000L
+//DC_I2C_DDCVGA_HW_STATUS
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x11
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x00000003L
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x00000008L
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x00010000L
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x00020000L
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x00100000L
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000L
+//DC_I2C_DDCVGA_SPEED
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x00000003L
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL_MASK 0x00000300L
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xFFFF0000L
+//DC_I2C_DDCVGA_SETUP
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x6
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x00000001L
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x00000002L
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x00000010L
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x00000020L
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x00000040L
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x00000080L
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xFF000000L
+//DC_I2C_EDID_DETECT_CTRL
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0x0000FFFFL
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0x00F00000L
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000L
+//DC_I2C_READ_REQUEST_INTERRUPT
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x00000001L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x00000002L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x00000004L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x00000008L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x00000010L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x00000020L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x00000040L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x00000080L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x00000100L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x00000200L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x00000400L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x00000800L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x00001000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x00002000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x00004000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x00008000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x00010000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x00020000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x00040000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x00080000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x00100000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x00200000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x00400000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x00800000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x01000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x02000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x04000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x08000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000L
+//GENERIC_I2C_CONTROL
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x0
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x1
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x2
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x3
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x00000001L
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x00000002L
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x00000004L
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x00000008L
+//GENERIC_I2C_INTERRUPT_CONTROL
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x0
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x1
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x2
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x00000001L
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x00000002L
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x00000004L
+//GENERIC_I2C_STATUS
+#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x0
+#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x4
+#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x5
+#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x6
+#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x9
+#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0xa
+#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0x0000000FL
+#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x00000010L
+#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x00000020L
+#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x00000040L
+#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x00000200L
+#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x00000400L
+//GENERIC_I2C_SPEED
+#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x0
+#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x10
+#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x00000003L
+#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL_MASK 0x00000300L
+#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xFFFF0000L
+//GENERIC_I2C_SETUP
+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x0
+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x1
+#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x7
+#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x8
+#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x18
+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x00000001L
+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x00000002L
+#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x00000080L
+#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xFF000000L
+//GENERIC_I2C_TRANSACTION
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x0
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x8
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x9
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0xc
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0xd
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x10
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x00000001L
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x00000100L
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x00000200L
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x00001000L
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x00002000L
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0x000F0000L
+//GENERIC_I2C_DATA
+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x0
+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x8
+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x10
+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x1f
+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x00000001L
+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0x0000FF00L
+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0x000F0000L
+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000L
+//GENERIC_I2C_PIN_SELECTION
+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x0
+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x8
+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x0000007FL
+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x00007F00L
+//DCO_SCRATCH0
+#define DCO_SCRATCH0__DCO_SCRATCH0__SHIFT 0x0
+#define DCO_SCRATCH0__DCO_SCRATCH0_MASK 0xFFFFFFFFL
+//DCO_SCRATCH1
+#define DCO_SCRATCH1__DCO_SCRATCH1__SHIFT 0x0
+#define DCO_SCRATCH1__DCO_SCRATCH1_MASK 0xFFFFFFFFL
+//DCO_SCRATCH2
+#define DCO_SCRATCH2__DCO_SCRATCH2__SHIFT 0x0
+#define DCO_SCRATCH2__DCO_SCRATCH2_MASK 0xFFFFFFFFL
+//DCO_SCRATCH3
+#define DCO_SCRATCH3__DCO_SCRATCH3__SHIFT 0x0
+#define DCO_SCRATCH3__DCO_SCRATCH3_MASK 0xFFFFFFFFL
+//DCO_SCRATCH4
+#define DCO_SCRATCH4__DCO_SCRATCH4__SHIFT 0x0
+#define DCO_SCRATCH4__DCO_SCRATCH4_MASK 0xFFFFFFFFL
+//DCO_SCRATCH5
+#define DCO_SCRATCH5__DCO_SCRATCH5__SHIFT 0x0
+#define DCO_SCRATCH5__DCO_SCRATCH5_MASK 0xFFFFFFFFL
+//DCO_SCRATCH6
+#define DCO_SCRATCH6__DCO_SCRATCH6__SHIFT 0x0
+#define DCO_SCRATCH6__DCO_SCRATCH6_MASK 0xFFFFFFFFL
+//DCO_SCRATCH7
+#define DCO_SCRATCH7__DCO_SCRATCH7__SHIFT 0x0
+#define DCO_SCRATCH7__DCO_SCRATCH7_MASK 0xFFFFFFFFL
+//DCE_VCE_CONTROL
+#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x0
+#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x4
+#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x00000007L
+#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x00000070L
+//DISP_INTERRUPT_STATUS
+#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x00000004L
+#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x00000008L
+#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x01000000L
+#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000L
+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000L
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE
+#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT_MASK 0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1_MASK 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2_MASK 0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE2
+#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT_MASK 0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1_MASK 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2_MASK 0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE3
+#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT_MASK 0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1_MASK 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2_MASK 0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1_MASK 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2_MASK 0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE5
+#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1_MASK 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2_MASK 0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE6
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT_MASK 0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT_MASK 0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE7
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT_MASK 0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT_MASK 0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT_MASK 0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT_MASK 0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT_MASK 0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT_MASK 0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT_MASK 0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT_MASK 0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT_MASK 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT_MASK 0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE8
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT_MASK 0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT_MASK 0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT_MASK 0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT_MASK 0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT_MASK 0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT_MASK 0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT_MASK 0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT_MASK 0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT_MASK 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT_MASK 0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE9
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT_MASK 0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT_MASK 0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT_MASK 0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT_MASK 0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT_MASK 0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT_MASK 0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT_MASK 0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT_MASK 0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK 0x80000000L
+//DCO_MEM_PWR_STATUS
+#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0
+#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE__SHIFT 0x2
+#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3
+#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4
+#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5
+#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6
+#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7
+#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8
+#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9
+#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE__SHIFT 0xa
+#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE__SHIFT 0xc
+#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE__SHIFT 0xe
+#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE__SHIFT 0x10
+#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE__SHIFT 0x12
+#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE__SHIFT 0x14
+#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE__SHIFT 0x16
+#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x00000001L
+#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE_MASK 0x00000004L
+#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x00000008L
+#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x00000010L
+#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x00000020L
+#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x00000040L
+#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x00000080L
+#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x00000100L
+#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x00000200L
+#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE_MASK 0x00000C00L
+#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE_MASK 0x00003000L
+#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE_MASK 0x0000C000L
+#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE_MASK 0x00030000L
+#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE_MASK 0x000C0000L
+#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE_MASK 0x00300000L
+#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE_MASK 0x00C00000L
+//DCO_MEM_PWR_CTRL
+#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0
+#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1
+#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS__SHIFT 0x3
+#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4
+#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5
+#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6
+#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7
+#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8
+#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9
+#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa
+#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE__SHIFT 0xb
+#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS__SHIFT 0xd
+#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE__SHIFT 0xe
+#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS__SHIFT 0x10
+#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE__SHIFT 0x11
+#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS__SHIFT 0x13
+#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE__SHIFT 0x14
+#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS__SHIFT 0x16
+#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE__SHIFT 0x17
+#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS__SHIFT 0x19
+#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE__SHIFT 0x1a
+#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS__SHIFT 0x1c
+#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE__SHIFT 0x1d
+#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS__SHIFT 0x1f
+#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x00000001L
+#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x00000002L
+#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS_MASK 0x00000008L
+#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x00000010L
+#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x00000020L
+#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x00000040L
+#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x00000080L
+#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x00000100L
+#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x00000200L
+#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x00000400L
+#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE_MASK 0x00001800L
+#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS_MASK 0x00002000L
+#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE_MASK 0x0000C000L
+#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS_MASK 0x00010000L
+#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE_MASK 0x00060000L
+#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS_MASK 0x00080000L
+#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE_MASK 0x00300000L
+#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS_MASK 0x00400000L
+#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE_MASK 0x01800000L
+#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS_MASK 0x02000000L
+#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE_MASK 0x0C000000L
+#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS_MASK 0x10000000L
+#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE_MASK 0x60000000L
+#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS_MASK 0x80000000L
+//DCO_MEM_PWR_CTRL2
+#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL__SHIFT 0x0
+#define DCO_MEM_PWR_CTRL2__DPLPA_LIGHT_SLEEP_DIS__SHIFT 0x2
+#define DCO_MEM_PWR_CTRL2__DPLPB_LIGHT_SLEEP_DIS__SHIFT 0x3
+#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_FORCE__SHIFT 0x10
+#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_DIS__SHIFT 0x12
+#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_FORCE__SHIFT 0x13
+#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_DIS__SHIFT 0x15
+#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL_MASK 0x00000003L
+#define DCO_MEM_PWR_CTRL2__DPLPA_LIGHT_SLEEP_DIS_MASK 0x00000004L
+#define DCO_MEM_PWR_CTRL2__DPLPB_LIGHT_SLEEP_DIS_MASK 0x00000008L
+#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_FORCE_MASK 0x00030000L
+#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_DIS_MASK 0x00040000L
+#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_FORCE_MASK 0x00180000L
+#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_DIS_MASK 0x00200000L
+//DCO_CLK_CNTL
+#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x5
+#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x6
+#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x7
+#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x8
+#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x9
+#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS__SHIFT 0xa
+#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x10
+#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x11
+#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x12
+#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x13
+#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x14
+#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x15
+#define DCO_CLK_CNTL__DISPCLK_G_DIGLPA_GATE_DIS__SHIFT 0x16
+#define DCO_CLK_CNTL__DISPCLK_G_DIGLPB_GATE_DIS__SHIFT 0x17
+#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18
+#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19
+#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a
+#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b
+#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c
+#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d
+#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e
+#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x00000020L
+#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x00000040L
+#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x00000080L
+#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x00000100L
+#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x00000200L
+#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS_MASK 0x00000400L
+#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x00010000L
+#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x00020000L
+#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x00040000L
+#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x00080000L
+#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x00100000L
+#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x00200000L
+#define DCO_CLK_CNTL__DISPCLK_G_DIGLPA_GATE_DIS_MASK 0x00400000L
+#define DCO_CLK_CNTL__DISPCLK_G_DIGLPB_GATE_DIS_MASK 0x00800000L
+#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x01000000L
+#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x02000000L
+#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x04000000L
+#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x08000000L
+#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000L
+#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000L
+#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000L
+//DCO_POWER_MANAGEMENT_CNTL
+#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0
+#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8
+#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x00000001L
+#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x00000100L
+//DIG_SOFT_RESET_2
+#define DIG_SOFT_RESET_2__DIGLPA_FE_SOFT_RESET__SHIFT 0x0
+#define DIG_SOFT_RESET_2__DIGLPA_BE_SOFT_RESET__SHIFT 0x1
+#define DIG_SOFT_RESET_2__DIGLPB_FE_SOFT_RESET__SHIFT 0x4
+#define DIG_SOFT_RESET_2__DIGLPB_BE_SOFT_RESET__SHIFT 0x5
+#define DIG_SOFT_RESET_2__DIGLPA_FE_SOFT_RESET_MASK 0x00000001L
+#define DIG_SOFT_RESET_2__DIGLPA_BE_SOFT_RESET_MASK 0x00000002L
+#define DIG_SOFT_RESET_2__DIGLPB_FE_SOFT_RESET_MASK 0x00000010L
+#define DIG_SOFT_RESET_2__DIGLPB_BE_SOFT_RESET_MASK 0x00000020L
+//DCO_STEREOSYNC_SEL
+#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x0
+#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x10
+#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x00000007L
+#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x00070000L
+//DCO_SOFT_RESET
+#define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x0
+#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT 0x4
+#define DCO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT 0x5
+#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT 0x6
+#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET__SHIFT 0xc
+#define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x10
+#define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x11
+#define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x12
+#define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x13
+#define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x14
+#define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x15
+#define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x18
+#define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x19
+#define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x1b
+#define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x00000001L
+#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK 0x00000010L
+#define DCO_SOFT_RESET__I2S1_SOFT_RESET_MASK 0x00000020L
+#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK 0x00000040L
+#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET_MASK 0x00001000L
+#define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x00010000L
+#define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x00020000L
+#define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x00040000L
+#define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x00080000L
+#define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x00100000L
+#define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x00200000L
+#define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x01000000L
+#define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x02000000L
+#define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x08000000L
+//DIG_SOFT_RESET
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x00000001L
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x00000002L
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x00000010L
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x00000020L
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x00000100L
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x00000200L
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x00001000L
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x00002000L
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x00010000L
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x00020000L
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x00100000L
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x00200000L
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x01000000L
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x02000000L
+//DCO_MEM_PWR_STATUS1
+#define DCO_MEM_PWR_STATUS1__DPLPA_MEM_PWR_STATE__SHIFT 0x0
+#define DCO_MEM_PWR_STATUS1__DPLPB_MEM_PWR_STATE__SHIFT 0x1
+#define DCO_MEM_PWR_STATUS1__HDMILP0_MEM_PWR_STATE__SHIFT 0xa
+#define DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE__SHIFT 0xc
+#define DCO_MEM_PWR_STATUS1__DPLPA_MEM_PWR_STATE_MASK 0x00000001L
+#define DCO_MEM_PWR_STATUS1__DPLPB_MEM_PWR_STATE_MASK 0x00000002L
+#define DCO_MEM_PWR_STATUS1__HDMILP0_MEM_PWR_STATE_MASK 0x00000C00L
+#define DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE_MASK 0x00003000L
+//DISP_INTERRUPT_STATUS_CONTINUE10
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER2_INTERRUPT__SHIFT 0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER3_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER4_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER5_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER6_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER7_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER_OFF_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC1_RANGE_TIMING_UPDATE__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC2_RANGE_TIMING_UPDATE__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC3_RANGE_TIMING_UPDATE__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC4_RANGE_TIMING_UPDATE__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC5_RANGE_TIMING_UPDATE__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC6_RANGE_TIMING_UPDATE__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK 0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK 0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER2_INTERRUPT_MASK 0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER3_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER4_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER5_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER6_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER7_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER_OFF_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC1_RANGE_TIMING_UPDATE_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC2_RANGE_TIMING_UPDATE_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC3_RANGE_TIMING_UPDATE_MASK 0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC4_RANGE_TIMING_UPDATE_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC5_RANGE_TIMING_UPDATE_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__CRTC6_RANGE_TIMING_UPDATE_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK 0x80000000L
+//DCO_CLK_CNTL2
+#define DCO_CLK_CNTL2__DCO_TEST_CLK_SEL__SHIFT 0x0
+#define DCO_CLK_CNTL2__SCLK_G_AFMTA_GATE_DIS__SHIFT 0x7
+#define DCO_CLK_CNTL2__SCLK_G_AFMTB_GATE_DIS__SHIFT 0x8
+#define DCO_CLK_CNTL2__SCLK_G_AFMTC_GATE_DIS__SHIFT 0x9
+#define DCO_CLK_CNTL2__SCLK_G_AFMTD_GATE_DIS__SHIFT 0xa
+#define DCO_CLK_CNTL2__SCLK_G_AFMTE_GATE_DIS__SHIFT 0xb
+#define DCO_CLK_CNTL2__SCLK_G_AFMTF_GATE_DIS__SHIFT 0xc
+#define DCO_CLK_CNTL2__SCLK_G_AFMTG_GATE_DIS__SHIFT 0xd
+#define DCO_CLK_CNTL2__SCLK_G_AFMTLPA_GATE_DIS__SHIFT 0xf
+#define DCO_CLK_CNTL2__SCLK_G_AFMTLPB_GATE_DIS__SHIFT 0x10
+#define DCO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT 0x11
+#define DCO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT 0x12
+#define DCO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT 0x13
+#define DCO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT 0x14
+#define DCO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT 0x15
+#define DCO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT 0x16
+#define DCO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT 0x17
+#define DCO_CLK_CNTL2__SYMCLKLPA_FE_G_AFMT_GATE_DIS__SHIFT 0x19
+#define DCO_CLK_CNTL2__SYMCLKLPB_FE_G_AFMT_GATE_DIS__SHIFT 0x1a
+#define DCO_CLK_CNTL2__DCO_TEST_CLK_SEL_MASK 0x0000007FL
+#define DCO_CLK_CNTL2__SCLK_G_AFMTA_GATE_DIS_MASK 0x00000080L
+#define DCO_CLK_CNTL2__SCLK_G_AFMTB_GATE_DIS_MASK 0x00000100L
+#define DCO_CLK_CNTL2__SCLK_G_AFMTC_GATE_DIS_MASK 0x00000200L
+#define DCO_CLK_CNTL2__SCLK_G_AFMTD_GATE_DIS_MASK 0x00000400L
+#define DCO_CLK_CNTL2__SCLK_G_AFMTE_GATE_DIS_MASK 0x00000800L
+#define DCO_CLK_CNTL2__SCLK_G_AFMTF_GATE_DIS_MASK 0x00001000L
+#define DCO_CLK_CNTL2__SCLK_G_AFMTG_GATE_DIS_MASK 0x00002000L
+#define DCO_CLK_CNTL2__SCLK_G_AFMTLPA_GATE_DIS_MASK 0x00008000L
+#define DCO_CLK_CNTL2__SCLK_G_AFMTLPB_GATE_DIS_MASK 0x00010000L
+#define DCO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK 0x00020000L
+#define DCO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK 0x00040000L
+#define DCO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK 0x00080000L
+#define DCO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK 0x00100000L
+#define DCO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK 0x00200000L
+#define DCO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK 0x00400000L
+#define DCO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK 0x00800000L
+#define DCO_CLK_CNTL2__SYMCLKLPA_FE_G_AFMT_GATE_DIS_MASK 0x02000000L
+#define DCO_CLK_CNTL2__SYMCLKLPB_FE_G_AFMT_GATE_DIS_MASK 0x04000000L
+//DCO_CLK_CNTL3
+#define DCO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT 0x0
+#define DCO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT 0x1
+#define DCO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT 0x2
+#define DCO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT 0x3
+#define DCO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT 0x4
+#define DCO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT 0x5
+#define DCO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT 0x6
+#define DCO_CLK_CNTL3__SYMCLKLPA_FE_G_TMDS_GATE_DIS__SHIFT 0x8
+#define DCO_CLK_CNTL3__SYMCLKLPB_FE_G_TMDS_GATE_DIS__SHIFT 0x9
+#define DCO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT 0xa
+#define DCO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT 0xb
+#define DCO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT 0xc
+#define DCO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT 0xd
+#define DCO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT 0xe
+#define DCO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT 0xf
+#define DCO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT 0x10
+#define DCO_CLK_CNTL3__SYMCLKLPA_G_TMDS_GATE_DIS__SHIFT 0x12
+#define DCO_CLK_CNTL3__SYMCLKLPB_G_TMDS_GATE_DIS__SHIFT 0x13
+#define DCO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK 0x00000001L
+#define DCO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK 0x00000002L
+#define DCO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK 0x00000004L
+#define DCO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK 0x00000008L
+#define DCO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK 0x00000010L
+#define DCO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK 0x00000020L
+#define DCO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK 0x00000040L
+#define DCO_CLK_CNTL3__SYMCLKLPA_FE_G_TMDS_GATE_DIS_MASK 0x00000100L
+#define DCO_CLK_CNTL3__SYMCLKLPB_FE_G_TMDS_GATE_DIS_MASK 0x00000200L
+#define DCO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK 0x00000400L
+#define DCO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK 0x00000800L
+#define DCO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK 0x00001000L
+#define DCO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK 0x00002000L
+#define DCO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK 0x00004000L
+#define DCO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK 0x00008000L
+#define DCO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK 0x00010000L
+#define DCO_CLK_CNTL3__SYMCLKLPA_G_TMDS_GATE_DIS_MASK 0x00040000L
+#define DCO_CLK_CNTL3__SYMCLKLPB_G_TMDS_GATE_DIS_MASK 0x00080000L
+//DCO_HDMI_RXSTATUS_TIMER_CONTROL
+#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT 0x0
+#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT 0x4
+#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT 0x8
+#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_MASK__SHIFT 0xc
+#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT 0x10
+#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_ENABLE_MASK 0x00000001L
+#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_TYPE_MASK 0x00000010L
+#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_STATUS_MASK 0x00000100L
+#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_MASK_MASK 0x00001000L
+#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK 0x0FFF0000L
+//DCO_PSP_INTERRUPT_STATUS
+#define DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_STATUS__SHIFT 0x0
+#define DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_MESSAGE__SHIFT 0x1
+#define DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_STATUS_MASK 0x00000001L
+#define DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_MESSAGE_MASK 0xFFFFFFFEL
+//DCO_PSP_INTERRUPT_CLEAR
+#define DCO_PSP_INTERRUPT_CLEAR__DCO_PSP_INTERRUPT_CLEAR__SHIFT 0x0
+#define DCO_PSP_INTERRUPT_CLEAR__DCO_PSP_INTERRUPT_CLEAR_MASK 0x00000001L
+//DCO_GENERIC_INTERRUPT_MESSAGE
+#define DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_STATUS__SHIFT 0x0
+#define DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_MESSAGE__SHIFT 0x1
+#define DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_STATUS_MASK 0x00000001L
+#define DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_MESSAGE_MASK 0xFFFFFFFEL
+//DCO_GENERIC_INTERRUPT_CLEAR
+#define DCO_GENERIC_INTERRUPT_CLEAR__DCO_GENERIC_INTERRUPT_CLEAR__SHIFT 0x0
+#define DCO_GENERIC_INTERRUPT_CLEAR__DCO_GENERIC_INTERRUPT_CLEAR_MASK 0x00000001L
+//FMT_MEMORY0_CONTROL
+#define FMT_MEMORY0_CONTROL__FMT420_MEM0_SOURCE_SEL__SHIFT 0x0
+#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_FORCE__SHIFT 0x4
+#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_DIS__SHIFT 0x8
+#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_STATE__SHIFT 0xc
+#define FMT_MEMORY0_CONTROL__FMT420_MEM0_SOURCE_SEL_MASK 0x00000007L
+#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_FORCE_MASK 0x00000030L
+#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_DIS_MASK 0x00000100L
+#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_STATE_MASK 0x00003000L
+//FMT_MEMORY1_CONTROL
+#define FMT_MEMORY1_CONTROL__FMT420_MEM1_SOURCE_SEL__SHIFT 0x0
+#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_FORCE__SHIFT 0x4
+#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_DIS__SHIFT 0x8
+#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_STATE__SHIFT 0xc
+#define FMT_MEMORY1_CONTROL__FMT420_MEM1_SOURCE_SEL_MASK 0x00000007L
+#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_FORCE_MASK 0x00000030L
+#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_DIS_MASK 0x00000100L
+#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_STATE_MASK 0x00003000L
+//FMT_MEMORY2_CONTROL
+#define FMT_MEMORY2_CONTROL__FMT420_MEM2_SOURCE_SEL__SHIFT 0x0
+#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_FORCE__SHIFT 0x4
+#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_DIS__SHIFT 0x8
+#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_STATE__SHIFT 0xc
+#define FMT_MEMORY2_CONTROL__FMT420_MEM2_SOURCE_SEL_MASK 0x00000007L
+#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_FORCE_MASK 0x00000030L
+#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_DIS_MASK 0x00000100L
+#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_STATE_MASK 0x00003000L
+//FMT_MEMORY3_CONTROL
+#define FMT_MEMORY3_CONTROL__FMT420_MEM3_SOURCE_SEL__SHIFT 0x0
+#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_FORCE__SHIFT 0x4
+#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_DIS__SHIFT 0x8
+#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_STATE__SHIFT 0xc
+#define FMT_MEMORY3_CONTROL__FMT420_MEM3_SOURCE_SEL_MASK 0x00000007L
+#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_FORCE_MASK 0x00000030L
+#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_DIS_MASK 0x00000100L
+#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_STATE_MASK 0x00003000L
+//FMT_MEMORY4_CONTROL
+#define FMT_MEMORY4_CONTROL__FMT420_MEM4_SOURCE_SEL__SHIFT 0x0
+#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_FORCE__SHIFT 0x4
+#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_DIS__SHIFT 0x8
+#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_STATE__SHIFT 0xc
+#define FMT_MEMORY4_CONTROL__FMT420_MEM4_SOURCE_SEL_MASK 0x00000007L
+#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_FORCE_MASK 0x00000030L
+#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_DIS_MASK 0x00000100L
+#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_STATE_MASK 0x00003000L
+//FMT_MEMORY5_CONTROL
+#define FMT_MEMORY5_CONTROL__FMT420_MEM5_SOURCE_SEL__SHIFT 0x0
+#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_FORCE__SHIFT 0x4
+#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_DIS__SHIFT 0x8
+#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_STATE__SHIFT 0xc
+#define FMT_MEMORY5_CONTROL__FMT420_MEM5_SOURCE_SEL_MASK 0x00000007L
+#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_FORCE_MASK 0x00000030L
+#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_DIS_MASK 0x00000100L
+#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_STATE_MASK 0x00003000L
+//DISP_INTERRUPT_STATUS_CONTINUE11
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP0_xdma_vsync_flip_timeout_interrupt__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP1_xdma_vsync_flip_timeout_interrupt__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP2_xdma_vsync_flip_timeout_interrupt__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP3_xdma_vsync_flip_timeout_interrupt__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP4_xdma_vsync_flip_timeout_interrupt__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP5_xdma_vsync_flip_timeout_interrupt__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP0_xdma_vsync_flip_timeout_interrupt_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP1_xdma_vsync_flip_timeout_interrupt_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP2_xdma_vsync_flip_timeout_interrupt_MASK 0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP3_xdma_vsync_flip_timeout_interrupt_MASK 0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP4_xdma_vsync_flip_timeout_interrupt_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DCP5_xdma_vsync_flip_timeout_interrupt_MASK 0x00000020L
+//DC_GENERICA
+#define DC_GENERICA__GENERICA_EN__SHIFT 0x0
+#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
+#define DC_GENERICA__GENERICA_EN_MASK 0x00000001L
+#define DC_GENERICA__GENERICA_SEL_MASK 0x00000F80L
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L
+//DC_GENERICB
+#define DC_GENERICB__GENERICB_EN__SHIFT 0x0
+#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
+#define DC_GENERICB__GENERICB_EN_MASK 0x00000001L
+#define DC_GENERICB__GENERICB_SEL_MASK 0x00000F00L
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L
+//DC_PAD_EXTERN_SIG
+#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x0
+#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x4
+#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0x0000000FL
+#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x00000030L
+//DC_REF_CLK_CNTL
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x00000003L
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L
+//DC_GPIO_DEBUG
+#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x0
+#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x8
+#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x10
+#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT 0x11
+#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE__SHIFT 0x1f
+#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x00000001L
+#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x00000300L
+#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x00010000L
+#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK 0x00020000L
+#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE_MASK 0x80000000L
+//UNIPHYA_LINK_CNTL
+#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
+#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
+#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+//UNIPHYA_CHANNEL_XBAR_CNTL
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
+//UNIPHYB_LINK_CNTL
+#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
+#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
+#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+//UNIPHYB_CHANNEL_XBAR_CNTL
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
+//UNIPHYC_LINK_CNTL
+#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
+#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
+#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+//UNIPHYC_CHANNEL_XBAR_CNTL
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
+//UNIPHYD_LINK_CNTL
+#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
+#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
+#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+//UNIPHYD_CHANNEL_XBAR_CNTL
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
+//UNIPHYE_LINK_CNTL
+#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
+#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
+#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+//UNIPHYE_CHANNEL_XBAR_CNTL
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
+//UNIPHYF_LINK_CNTL
+#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
+#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
+#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
+#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
+#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+//UNIPHYF_CHANNEL_XBAR_CNTL
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
+//UNIPHYG_LINK_CNTL
+#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
+#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
+#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
+#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
+#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+//UNIPHYG_CHANNEL_XBAR_CNTL
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
+//DCIO_WRCMD_DELAY
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x0
+#define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT 0x4
+#define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT 0x8
+#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT 0xc
+#define DCIO_WRCMD_DELAY__ZCAL_DELAY__SHIFT 0x10
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0x0000000FL
+#define DCIO_WRCMD_DELAY__DAC_DELAY_MASK 0x000000F0L
+#define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK 0x00000F00L
+#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK 0x0000F000L
+#define DCIO_WRCMD_DELAY__ZCAL_DELAY_MASK 0x000F0000L
+//DC_DVODATA_CONFIG
+#define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13
+#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14
+#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x15
+#define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x00080000L
+#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x00100000L
+#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x00200000L
+//LVTMA_PWRSEQ_CNTL
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x00000001L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x00000002L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x00000010L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x00000100L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x00000200L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x00000400L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x00010000L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x00020000L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x00040000L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x01000000L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x02000000L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x04000000L
+//LVTMA_PWRSEQ_STATE
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x00000002L
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x00000004L
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x00000008L
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x00000010L
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0x00000F00L
+//LVTMA_PWRSEQ_REF_DIV
+#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0
+#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10
+#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0x00000FFFL
+#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xFFFF0000L
+//LVTMA_PWRSEQ_DELAY1
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0x000000FFL
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0x0000FF00L
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0x00FF0000L
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xFF000000L
+//LVTMA_PWRSEQ_DELAY2
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0x000000FFL
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0x0000FF00L
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0x00FF0000L
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x01000000L
+//BL_PWM_CNTL
+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0
+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e
+#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f
+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000FFFFL
+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L
+#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L
+//BL_PWM_CNTL2
+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f
+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000FFFFL
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000L
+//BL_PWM_PERIOD_CNTL
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000FFFFL
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000F0000L
+//BL_PWM_GRP1_REG_LOCK
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0x000E0000L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L
+//DCIO_GSL_GENLK_PAD_CNTL
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x0
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x4
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x10
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x14
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x00000003L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x00000030L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x00030000L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x00300000L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L
+//DCIO_GSL_SWAPLOCK_PAD_CNTL
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x0
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x4
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x10
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x14
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x00000003L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x00000030L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x00030000L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x00300000L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L
+//DCIO_GSL0_CNTL
+#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x0
+#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x8
+#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x10
+#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x00000007L
+#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x00000700L
+#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x00070000L
+//DCIO_GSL1_CNTL
+#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x0
+#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8
+#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x10
+#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x00000007L
+#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x00000700L
+#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x00070000L
+//DCIO_GSL2_CNTL
+#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x0
+#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x8
+#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x10
+#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x00000007L
+#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x00000700L
+#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x00070000L
+//DC_GPU_TIMER_START_POSITION_V_UPDATE
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x00000007L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x00000070L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x00000700L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x00007000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x00070000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x00700000L
+//DC_GPU_TIMER_START_POSITION_P_FLIP
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x0
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x4
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x8
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0xc
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x10
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x14
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV0_P_FLIP__SHIFT 0x17
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV1_P_FLIP__SHIFT 0x1a
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x00000007L
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x00000070L
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x00000700L
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x00007000L
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x00070000L
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x00700000L
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV0_P_FLIP_MASK 0x03800000L
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV1_P_FLIP_MASK 0x1C000000L
+//DC_GPU_TIMER_READ
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xFFFFFFFFL
+//DC_GPU_TIMER_READ_CNTL
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x0000003FL
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x00000700L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x00003800L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x0001C000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0x000E0000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x00700000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x03800000L
+//DCIO_CLOCK_CNTL
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x0000001FL
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x00000020L
+//DCO_DCFE_EXT_VSYNC_CNTL
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX__SHIFT 0x0
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX__SHIFT 0x4
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX__SHIFT 0x8
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX__SHIFT 0xc
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX__SHIFT 0x10
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX__SHIFT 0x14
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT 0x18
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK__SHIFT 0x1c
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL__SHIFT 0x1f
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX_MASK 0x00000007L
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX_MASK 0x00000070L
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX_MASK 0x00000700L
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX_MASK 0x00007000L
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX_MASK 0x00070000L
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX_MASK 0x00700000L
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK_MASK 0x07000000L
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK_MASK 0x70000000L
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL_MASK 0x80000000L
+//DCIO_SOFT_RESET
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd
+#define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x10
+#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT 0x14
+#define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT 0x18
+#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET__SHIFT 0x1a
+#define DCIO_SOFT_RESET__UNIPHYLPA_SOFT_RESET__SHIFT 0x1c
+#define DCIO_SOFT_RESET__DSYNCLPA_SOFT_RESET__SHIFT 0x1d
+#define DCIO_SOFT_RESET__UNIPHYLPB_SOFT_RESET__SHIFT 0x1e
+#define DCIO_SOFT_RESET__DSYNCLPB_SOFT_RESET__SHIFT 0x1f
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x00000001L
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x00000002L
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x00000004L
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x00000008L
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x00000010L
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x00000020L
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x00000040L
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x00000080L
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x00000100L
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x00000200L
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x00000400L
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x00000800L
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x00001000L
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x00002000L
+#define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x00010000L
+#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK 0x00100000L
+#define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK 0x01000000L
+#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET_MASK 0x04000000L
+#define DCIO_SOFT_RESET__UNIPHYLPA_SOFT_RESET_MASK 0x10000000L
+#define DCIO_SOFT_RESET__DSYNCLPA_SOFT_RESET_MASK 0x20000000L
+#define DCIO_SOFT_RESET__UNIPHYLPB_SOFT_RESET_MASK 0x40000000L
+#define DCIO_SOFT_RESET__DSYNCLPB_SOFT_RESET_MASK 0x80000000L
+//DCIO_DPHY_SEL
+#define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT 0x0
+#define DCIO_DPHY_SEL__DPHY_LANE1_SEL__SHIFT 0x2
+#define DCIO_DPHY_SEL__DPHY_LANE2_SEL__SHIFT 0x4
+#define DCIO_DPHY_SEL__DPHY_LANE3_SEL__SHIFT 0x6
+#define DCIO_DPHY_SEL__DPHY_LANE0_SEL_MASK 0x00000003L
+#define DCIO_DPHY_SEL__DPHY_LANE1_SEL_MASK 0x0000000CL
+#define DCIO_DPHY_SEL__DPHY_LANE2_SEL_MASK 0x00000030L
+#define DCIO_DPHY_SEL__DPHY_LANE3_SEL_MASK 0x000000C0L
+//UNIPHY_IMPCAL_LINKA
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x1e
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x00000001L
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x00000100L
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x00000200L
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x00000400L
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0x000F0000L
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0x00F00000L
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0x0F000000L
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000L
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000L
+//UNIPHY_IMPCAL_LINKB
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x1e
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x00000001L
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x00000100L
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x00000200L
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x00000400L
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0x000F0000L
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0x00F00000L
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0x0F000000L
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000L
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000L
+//UNIPHY_IMPCAL_PERIOD
+#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x0
+#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xFFFFFFFFL
+//AUXP_IMPCAL
+#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x0
+#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x8
+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x9
+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0xa
+#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x10
+#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x14
+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x18
+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c
+#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x00000001L
+#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x00000100L
+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x00000200L
+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x00000400L
+#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0x000F0000L
+#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0x00F00000L
+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0x0F000000L
+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L
+//AUXN_IMPCAL
+#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x0
+#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x8
+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x9
+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0xa
+#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x10
+#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x14
+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x18
+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c
+#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x00000001L
+#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x00000100L
+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x00000200L
+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x00000400L
+#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0x000F0000L
+#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0x00F00000L
+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0x0F000000L
+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L
+//DCIO_IMPCAL_CNTL
+#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE__SHIFT 0x0
+#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET__SHIFT 0x5
+#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS__SHIFT 0x8
+#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE__SHIFT 0xc
+#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL__SHIFT 0xf
+#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE_MASK 0x0000000FL
+#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET_MASK 0x00000020L
+#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS_MASK 0x00000300L
+#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE_MASK 0x00007000L
+#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL_MASK 0x00078000L
+//UNIPHY_IMPCAL_PSW_AB
+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x0
+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x10
+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x00007FFFL
+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7FFF0000L
+//UNIPHY_IMPCAL_LINKC
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x1e
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x00000001L
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x00000100L
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x00000200L
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x00000400L
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0x000F0000L
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0x00F00000L
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0x0F000000L
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000L
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000L
+//UNIPHY_IMPCAL_LINKD
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x1e
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x00000001L
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x00000100L
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x00000200L
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x00000400L
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0x000F0000L
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0x00F00000L
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0x0F000000L
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000L
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000L
+//DCIO_IMPCAL_CNTL_CD
+#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x0
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x5
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x8
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0xc
+#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0x0000000FL
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x00000020L
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x00000300L
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x00007000L
+//UNIPHY_IMPCAL_PSW_CD
+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x0
+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x10
+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x00007FFFL
+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7FFF0000L
+//UNIPHY_IMPCAL_LINKE
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x1e
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x00000001L
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x00000100L
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x00000200L
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x00000400L
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0x000F0000L
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0x00F00000L
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0x0F000000L
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000L
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000L
+//UNIPHY_IMPCAL_LINKF
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x1e
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x00000001L
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x00000100L
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x00000200L
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x00000400L
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0x000F0000L
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0x00F00000L
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0x0F000000L
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000L
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000L
+//DCIO_IMPCAL_CNTL_EF
+#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x0
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x5
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x8
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0xc
+#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0x0000000FL
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x00000020L
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x00000300L
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x00007000L
+//UNIPHY_IMPCAL_PSW_EF
+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x0
+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x10
+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x00007FFFL
+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7FFF0000L
+//UNIPHYLPA_LINK_CNTL
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PFREQCHG__SHIFT 0x0
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PFREQCHG_MASK 0x00000001L
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PIXVLD_RESET_MASK 0x00000010L
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT_MASK 0x00001000L
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT_MASK 0x00002000L
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT_MASK 0x00004000L
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT_MASK 0x00008000L
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY_MASK 0x00700000L
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+//UNIPHYLPB_LINK_CNTL
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PFREQCHG__SHIFT 0x0
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PFREQCHG_MASK 0x00000001L
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PIXVLD_RESET_MASK 0x00000010L
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT_MASK 0x00001000L
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT_MASK 0x00002000L
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT_MASK 0x00004000L
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT_MASK 0x00008000L
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY_MASK 0x00700000L
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+//UNIPHYLPA_CHANNEL_XBAR_CNTL
+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE_MASK 0x10000000L
+//UNIPHYLPB_CHANNEL_XBAR_CNTL
+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE_MASK 0x10000000L
+//DCIO_DPCS_TX_INTERRUPT
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_TYPE__SHIFT 0x0
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_MASK__SHIFT 0x1
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_OCCUR__SHIFT 0x2
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_TYPE__SHIFT 0x3
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_MASK__SHIFT 0x4
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_OCCUR__SHIFT 0x5
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_TYPE__SHIFT 0x6
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_MASK__SHIFT 0x7
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_OCCUR__SHIFT 0x8
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_TYPE__SHIFT 0x9
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_MASK__SHIFT 0xa
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_OCCUR__SHIFT 0xb
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_TYPE__SHIFT 0xc
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_MASK__SHIFT 0xd
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_OCCUR__SHIFT 0xe
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_TYPE__SHIFT 0xf
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_MASK__SHIFT 0x10
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_OCCUR__SHIFT 0x11
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_TYPE__SHIFT 0x12
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_MASK__SHIFT 0x13
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_OCCUR__SHIFT 0x14
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_TYPE__SHIFT 0x18
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_MASK__SHIFT 0x19
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_OCCUR__SHIFT 0x1a
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_TYPE__SHIFT 0x1b
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_MASK__SHIFT 0x1c
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_OCCUR__SHIFT 0x1d
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_TYPE_MASK 0x00000001L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_MASK_MASK 0x00000002L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_OCCUR_MASK 0x00000004L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_TYPE_MASK 0x00000008L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_MASK_MASK 0x00000010L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_OCCUR_MASK 0x00000020L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_TYPE_MASK 0x00000040L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_MASK_MASK 0x00000080L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_OCCUR_MASK 0x00000100L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_TYPE_MASK 0x00000200L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_MASK_MASK 0x00000400L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_OCCUR_MASK 0x00000800L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_TYPE_MASK 0x00001000L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_MASK_MASK 0x00002000L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_OCCUR_MASK 0x00004000L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_TYPE_MASK 0x00008000L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_MASK_MASK 0x00010000L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_OCCUR_MASK 0x00020000L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_TYPE_MASK 0x00040000L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_MASK_MASK 0x00080000L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_OCCUR_MASK 0x00100000L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_TYPE_MASK 0x01000000L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_MASK_MASK 0x02000000L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_OCCUR_MASK 0x04000000L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_TYPE_MASK 0x08000000L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_MASK_MASK 0x10000000L
+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_OCCUR_MASK 0x20000000L
+//DCIO_DPCS_RX_INTERRUPT
+#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_TYPE__SHIFT 0x0
+#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_MASK__SHIFT 0x1
+#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_OCCUR__SHIFT 0x2
+#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_TYPE_MASK 0x00000001L
+#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_MASK_MASK 0x00000002L
+#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_OCCUR_MASK 0x00000004L
+//DCIO_SEMAPHORE0
+#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_REQ__SHIFT 0x0
+#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_GNT__SHIFT 0x10
+#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_REQ_MASK 0x0000FFFFL
+#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_GNT_MASK 0xFFFF0000L
+//DCIO_SEMAPHORE1
+#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_REQ__SHIFT 0x0
+#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_GNT__SHIFT 0x10
+#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_REQ_MASK 0x0000FFFFL
+#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_GNT_MASK 0xFFFF0000L
+//DCIO_SEMAPHORE2
+#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_REQ__SHIFT 0x0
+#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_GNT__SHIFT 0x10
+#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_REQ_MASK 0x0000FFFFL
+#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_GNT_MASK 0xFFFF0000L
+//DCIO_SEMAPHORE3
+#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_REQ__SHIFT 0x0
+#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_GNT__SHIFT 0x10
+#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_REQ_MASK 0x0000FFFFL
+#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_GNT_MASK 0xFFFF0000L
+//DCIO_SEMAPHORE4
+#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_REQ__SHIFT 0x0
+#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_GNT__SHIFT 0x10
+#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_REQ_MASK 0x0000FFFFL
+#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_GNT_MASK 0xFFFF0000L
+//DCIO_SEMAPHORE5
+#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_REQ__SHIFT 0x0
+#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_GNT__SHIFT 0x10
+#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_REQ_MASK 0x0000FFFFL
+#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_GNT_MASK 0xFFFF0000L
+//DCIO_SEMAPHORE6
+#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_REQ__SHIFT 0x0
+#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_GNT__SHIFT 0x10
+#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_REQ_MASK 0x0000FFFFL
+#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_GNT_MASK 0xFFFF0000L
+//DCIO_SEMAPHORE7
+#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_REQ__SHIFT 0x0
+#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_GNT__SHIFT 0x10
+#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_REQ_MASK 0x0000FFFFL
+#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_GNT_MASK 0xFFFF0000L
+//DC_GPIO_GENERIC_MASK
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x00000001L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x00000002L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x0000000CL
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x00000010L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x00000020L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x000000C0L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x00000100L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x00000200L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x00000C00L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x00001000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x00002000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x0000C000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x00010000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x00020000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x000C0000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x00100000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x00200000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x00C00000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x01000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x02000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x0C000000L
+//DC_GPIO_GENERIC_A
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x00000001L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x00000100L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x00010000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x00100000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x00200000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x00400000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x00800000L
+//DC_GPIO_GENERIC_EN
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x00000001L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x00000100L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x00010000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x00100000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x00200000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x00400000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x00800000L
+//DC_GPIO_GENERIC_Y
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x00000001L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x00000100L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x00010000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x00100000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x00200000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x00400000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x00800000L
+//DC_GPIO_DVODATA_MASK
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x0
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x18
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x1d
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x1e
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0x00FFFFFFL
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x1F000000L
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x20000000L
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xC0000000L
+//DC_GPIO_DVODATA_A
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x0
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x18
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x1d
+#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x1e
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0x00FFFFFFL
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x1F000000L
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x20000000L
+#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xC0000000L
+//DC_GPIO_DVODATA_EN
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x0
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x18
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x1d
+#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x1e
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0x00FFFFFFL
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x1F000000L
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x20000000L
+#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xC0000000L
+//DC_GPIO_DVODATA_Y
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x0
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x18
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x1d
+#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x1e
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0x00FFFFFFL
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x1F000000L
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x20000000L
+#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xC0000000L
+//DC_GPIO_DDC1_MASK
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10
+#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L
+#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0x0F000000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xF0000000L
+//DC_GPIO_DDC1_A
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L
+//DC_GPIO_DDC1_EN
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L
+//DC_GPIO_DDC1_Y
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L
+//DC_GPIO_DDC2_MASK
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10
+#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L
+#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0x0F000000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xF0000000L
+//DC_GPIO_DDC2_A
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L
+//DC_GPIO_DDC2_EN
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L
+//DC_GPIO_DDC2_Y
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L
+//DC_GPIO_DDC3_MASK
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10
+#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L
+#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0x0F000000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xF0000000L
+//DC_GPIO_DDC3_A
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L
+//DC_GPIO_DDC3_EN
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L
+//DC_GPIO_DDC3_Y
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L
+//DC_GPIO_DDC4_MASK
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10
+#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L
+#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0x0F000000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xF0000000L
+//DC_GPIO_DDC4_A
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L
+//DC_GPIO_DDC4_EN
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L
+//DC_GPIO_DDC4_Y
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L
+//DC_GPIO_DDC5_MASK
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10
+#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L
+#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0x0F000000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xF0000000L
+//DC_GPIO_DDC5_A
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L
+//DC_GPIO_DDC5_EN
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L
+//DC_GPIO_DDC5_Y
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L
+//DC_GPIO_DDC6_MASK
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10
+#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14
+#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x00000001L
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x00000010L
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x00000040L
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x00000100L
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x00001000L
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x00004000L
+#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x00010000L
+#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x00100000L
+#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x00400000L
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0x0F000000L
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xF0000000L
+//DC_GPIO_DDC6_A
+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x00000001L
+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x00000100L
+//DC_GPIO_DDC6_EN
+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x00000001L
+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x00000100L
+//DC_GPIO_DDC6_Y
+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x00000001L
+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x00000100L
+//DC_GPIO_DDCVGA_MASK
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x00010000L
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x00100000L
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0x0F000000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xF0000000L
+//DC_GPIO_DDCVGA_A
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L
+//DC_GPIO_DDCVGA_EN
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L
+//DC_GPIO_DDCVGA_Y
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L
+//DC_GPIO_SYNCA_MASK
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x0
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x4
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x6
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x8
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0xc
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0xe
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x18
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x1c
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x00000001L
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x00000010L
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x000000C0L
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x00000100L
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x00001000L
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x0000C000L
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x07000000L
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000L
+//DC_GPIO_SYNCA_A
+#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x0
+#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x8
+#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x00000001L
+#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x00000100L
+//DC_GPIO_SYNCA_EN
+#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x0
+#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x8
+#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x00000001L
+#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x00000100L
+//DC_GPIO_SYNCA_Y
+#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x0
+#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x8
+#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x00000001L
+#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x00000100L
+//DC_GPIO_GENLK_MASK
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x4
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xc
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x14
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1c
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x00000001L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x00000002L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x00000008L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x00000030L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x00000100L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x00000200L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x00000800L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x00003000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x00010000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x00020000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x00080000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x00300000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x01000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x02000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x08000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x30000000L
+//DC_GPIO_GENLK_A
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x00000001L
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x00000100L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x00010000L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x01000000L
+//DC_GPIO_GENLK_EN
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x00000001L
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x00000100L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x00010000L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x01000000L
+//DC_GPIO_GENLK_Y
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x00000001L
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x00000100L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x00010000L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x01000000L
+//DC_GPIO_HPD_MASK
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT 0x1
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT 0x2
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT 0x3
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x00000001L
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK 0x00000002L
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK 0x00000004L
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK 0x00000008L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x00000010L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x000000C0L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x00000100L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x00000200L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x00000C00L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x00010000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x00020000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x000C0000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x00100000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x00200000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x00C00000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x01000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x02000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x0C000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0xC0000000L
+//DC_GPIO_HPD_A
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x00000001L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x00000100L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x00010000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x01000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x04000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000L
+//DC_GPIO_HPD_EN
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2
+#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT 0x3
+#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT 0x4
+#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT 0x5
+#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6
+#define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT 0x7
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT 0x9
+#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT 0xa
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT 0x11
+#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT 0x12
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x14
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT 0x15
+#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT 0x16
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x18
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT 0x19
+#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT 0x1a
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT 0x1d
+#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT 0x1e
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x00000001L
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x00000002L
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x00000004L
+#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK 0x00000008L
+#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK 0x00000010L
+#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK 0x00000020L
+#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x00000040L
+#define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK 0x00000080L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x00000100L
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK 0x00000200L
+#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK 0x00000400L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x00010000L
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK 0x00020000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK 0x00040000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x00100000L
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK 0x00200000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK 0x00400000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x01000000L
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK 0x02000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK 0x04000000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000L
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK 0x20000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK 0x40000000L
+//DC_GPIO_HPD_Y
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x00000001L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x00000100L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x00010000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x01000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x04000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000L
+//DC_GPIO_PWRSEQ_MASK
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00000001L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00000010L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x000000C0L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x0000C000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x00010000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x00100000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x00C00000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x01000000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x02000000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x04000000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000L
+//DC_GPIO_PWRSEQ_A
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x00000001L
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x00000100L
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x00010000L
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x01000000L
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000L
+//DC_GPIO_PWRSEQ_EN
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00000001L
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x00000002L
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x00010000L
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x01000000L
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000L
+//DC_GPIO_PWRSEQ_Y
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x00000001L
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x00000100L
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x00010000L
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x01000000L
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000L
+//DC_GPIO_PAD_STRENGTH_1
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT 0x8
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT 0xc
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT 0x10
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT 0x14
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK 0x00000F00L
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK 0x0000F000L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK 0x000F0000L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK 0x00F00000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0F000000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xF0000000L
+//DC_GPIO_PAD_STRENGTH_2
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x00000700L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x00007000L
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0x000F0000L
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0x00F00000L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xC0000000L
+//PHY_AUX_CNTL
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT 0x0
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT 0x1
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT 0x3
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT 0x4
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT 0x5
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT 0x6
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT 0x7
+#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0xc
+#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT 0xd
+#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe
+#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10
+#define PHY_AUX_CNTL__AUX_CAL_BIASENTST__SHIFT 0x14
+#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN__SHIFT 0x17
+#define PHY_AUX_CNTL__AUX_CAL_SPARE__SHIFT 0x18
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK 0x00000001L
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK 0x00000002L
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK 0x00000004L
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK 0x00000008L
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK 0x00000010L
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK 0x00000020L
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK 0x00000040L
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK 0x00000080L
+#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x00001000L
+#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK 0x00002000L
+#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00004000L
+#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x00030000L
+#define PHY_AUX_CNTL__AUX_CAL_BIASENTST_MASK 0x00700000L
+#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN_MASK 0x00800000L
+#define PHY_AUX_CNTL__AUX_CAL_SPARE_MASK 0x03000000L
+//DC_GPIO_I2CPAD_MASK
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK__SHIFT 0x0
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS__SHIFT 0x1
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV__SHIFT 0x2
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK__SHIFT 0x4
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS__SHIFT 0x5
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV__SHIFT 0x6
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK 0x00000001L
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK 0x00000002L
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK 0x00000004L
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK 0x00000010L
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK 0x00000020L
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK 0x00000040L
+//DC_GPIO_I2CPAD_A
+#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0
+#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x1
+#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x00000001L
+#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x00000002L
+//DC_GPIO_I2CPAD_EN
+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x0
+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x1
+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x00000001L
+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x00000002L
+//DC_GPIO_I2CPAD_Y
+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x0
+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x1
+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x00000001L
+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x00000002L
+//DC_GPIO_I2CPAD_STRENGTH
+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x0
+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x4
+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0x0000000FL
+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0x000000F0L
+//DVO_STRENGTH_CONTROL
+#define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT 0x0
+#define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT 0x4
+#define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT 0x8
+#define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT 0xc
+#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH__SHIFT 0x10
+#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH__SHIFT 0x14
+#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH__SHIFT 0x18
+#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT 0x1c
+#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT 0x1d
+#define DVO_STRENGTH_CONTROL__DVO_SP_MASK 0x0000000FL
+#define DVO_STRENGTH_CONTROL__DVO_SN_MASK 0x000000F0L
+#define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK 0x00000F00L
+#define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK 0x0000F000L
+#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH_MASK 0x00070000L
+#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH_MASK 0x00700000L
+#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH_MASK 0x07000000L
+#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK 0x10000000L
+#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK 0x20000000L
+//DVO_VREF_CONTROL
+#define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x0
+#define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1
+#define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x4
+#define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x00000001L
+#define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x00000002L
+#define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0x000000F0L
+//DVO_SKEW_ADJUST
+#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x0
+#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xFFFFFFFFL
+//DC_GPIO_I2S_SPDIF_MASK
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK__SHIFT 0x0
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK__SHIFT 0x4
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK__SHIFT 0x5
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK__SHIFT 0x6
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK__SHIFT 0x7
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK__SHIFT 0x8
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK__SHIFT 0x9
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK__SHIFT 0xa
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK__SHIFT 0xb
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK__SHIFT 0xc
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK_MASK 0x0000000FL
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK_MASK 0x00000010L
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK_MASK 0x00000020L
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK_MASK 0x00000040L
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK_MASK 0x00000080L
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK_MASK 0x00000100L
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK_MASK 0x00000200L
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK_MASK 0x00000400L
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK_MASK 0x00000800L
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK_MASK 0x00001000L
+//DC_GPIO_I2S_SPDIF_A
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A__SHIFT 0x0
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A__SHIFT 0x4
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A__SHIFT 0x5
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A__SHIFT 0x6
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A__SHIFT 0x7
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A__SHIFT 0x8
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A__SHIFT 0x9
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A__SHIFT 0xa
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A__SHIFT 0xb
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A__SHIFT 0xc
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A_MASK 0x0000000FL
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A_MASK 0x00000010L
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A_MASK 0x00000020L
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A_MASK 0x00000040L
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A_MASK 0x00000080L
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A_MASK 0x00000100L
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A_MASK 0x00000200L
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A_MASK 0x00000400L
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A_MASK 0x00000800L
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A_MASK 0x00001000L
+//DC_GPIO_I2S_SPDIF_EN
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN__SHIFT 0x0
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN__SHIFT 0x4
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN__SHIFT 0x5
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN__SHIFT 0x6
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN__SHIFT 0x7
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN__SHIFT 0x8
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN__SHIFT 0x9
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN__SHIFT 0xa
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN__SHIFT 0xb
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN__SHIFT 0xc
+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_APORT__SHIFT 0xd
+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_PU__SHIFT 0xe
+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_RXSEL__SHIFT 0xf
+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SCHMEN__SHIFT 0x10
+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SMODE_EN__SHIFT 0x11
+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_IMODE__SHIFT 0x12
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN_MASK 0x0000000FL
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN_MASK 0x00000010L
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN_MASK 0x00000020L
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN_MASK 0x00000040L
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN_MASK 0x00000080L
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN_MASK 0x00000100L
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN_MASK 0x00000200L
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN_MASK 0x00000400L
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN_MASK 0x00000800L
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN_MASK 0x00001000L
+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_APORT_MASK 0x00002000L
+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_PU_MASK 0x00004000L
+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_RXSEL_MASK 0x00008000L
+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SCHMEN_MASK 0x00010000L
+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SMODE_EN_MASK 0x00020000L
+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_IMODE_MASK 0x00040000L
+//DC_GPIO_I2S_SPDIF_Y
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y__SHIFT 0x0
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y__SHIFT 0x4
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y__SHIFT 0x5
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y__SHIFT 0x6
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y__SHIFT 0x7
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y__SHIFT 0x8
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y__SHIFT 0x9
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y__SHIFT 0xa
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y__SHIFT 0xb
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y__SHIFT 0xc
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y_MASK 0x0000000FL
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y_MASK 0x00000010L
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y_MASK 0x00000020L
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y_MASK 0x00000040L
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y_MASK 0x00000080L
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y_MASK 0x00000100L
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y_MASK 0x00000200L
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y_MASK 0x00000400L
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y_MASK 0x00000800L
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y_MASK 0x00001000L
+//DC_GPIO_I2S_SPDIF_STRENGTH
+#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH__SHIFT 0x0
+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SN__SHIFT 0x8
+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SP__SHIFT 0xb
+#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH__SHIFT 0x10
+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SN__SHIFT 0x18
+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SP__SHIFT 0x1b
+#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH_MASK 0x00000007L
+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SN_MASK 0x00000700L
+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SP_MASK 0x00003800L
+#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH_MASK 0x00070000L
+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SN_MASK 0x07000000L
+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SP_MASK 0x38000000L
+//DC_GPIO_TX12_EN
+#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN__SHIFT 0x0
+#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN__SHIFT 0x1
+#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN__SHIFT 0x2
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT 0x3
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT 0x4
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT 0x5
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT 0x6
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT 0x7
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT 0x8
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT 0x9
+#define DC_GPIO_TX12_EN__DC_GPIO_HSYNC_TX12_EN__SHIFT 0xa
+#define DC_GPIO_TX12_EN__DC_GPIO_VSYNC_TX12_EN__SHIFT 0xb
+#define DC_GPIO_TX12_EN__DC_GPIO_GENLK_CLK_TX12_EN__SHIFT 0xc
+#define DC_GPIO_TX12_EN__DC_GPIO_GENLK_VSYNC_TX12_EN__SHIFT 0xd
+#define DC_GPIO_TX12_EN__DC_GPIO_SWAPLOCKA_TX12_EN__SHIFT 0xe
+#define DC_GPIO_TX12_EN__DC_GPIO_SWAPLOCKB_TX12_EN__SHIFT 0xf
+#define DC_GPIO_TX12_EN__DC_GPIO_SCL_TX12_EN__SHIFT 0x10
+#define DC_GPIO_TX12_EN__DC_GPIO_SDA_TX12_EN__SHIFT 0x11
+#define DC_GPIO_TX12_EN__DC_GPIO_HPD1_TX12_EN__SHIFT 0x12
+#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN_MASK 0x00000001L
+#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN_MASK 0x00000002L
+#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN_MASK 0x00000004L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK 0x00000008L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK 0x00000010L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK 0x00000020L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK 0x00000040L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK 0x00000080L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK 0x00000100L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK 0x00000200L
+#define DC_GPIO_TX12_EN__DC_GPIO_HSYNC_TX12_EN_MASK 0x00000400L
+#define DC_GPIO_TX12_EN__DC_GPIO_VSYNC_TX12_EN_MASK 0x00000800L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENLK_CLK_TX12_EN_MASK 0x00001000L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENLK_VSYNC_TX12_EN_MASK 0x00002000L
+#define DC_GPIO_TX12_EN__DC_GPIO_SWAPLOCKA_TX12_EN_MASK 0x00004000L
+#define DC_GPIO_TX12_EN__DC_GPIO_SWAPLOCKB_TX12_EN_MASK 0x00008000L
+#define DC_GPIO_TX12_EN__DC_GPIO_SCL_TX12_EN_MASK 0x00010000L
+#define DC_GPIO_TX12_EN__DC_GPIO_SDA_TX12_EN_MASK 0x00020000L
+#define DC_GPIO_TX12_EN__DC_GPIO_HPD1_TX12_EN_MASK 0x00040000L
+//DC_GPIO_AUX_CTRL_0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT 0x0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT 0x2
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT 0x4
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT 0x6
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT 0x8
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT 0xa
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT 0xc
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_FALLSLEWSEL__SHIFT 0xe
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT 0x10
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT 0x11
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT 0x12
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT 0x13
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT 0x14
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT 0x15
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT 0x16
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCEN__SHIFT 0x17
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT 0x18
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT 0x19
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT 0x1a
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT 0x1b
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT 0x1c
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT 0x1d
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT 0x1e
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCSEL__SHIFT 0x1f
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK 0x00000003L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK 0x0000000CL
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK 0x00000030L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK 0x000000C0L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK 0x00000300L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK 0x00000C00L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK 0x00003000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_FALLSLEWSEL_MASK 0x0000C000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK 0x00010000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK 0x00020000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK 0x00040000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK 0x00080000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK 0x00100000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK 0x00200000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK 0x00400000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCEN_MASK 0x00800000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK 0x01000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK 0x02000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK 0x04000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK 0x08000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK 0x10000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK 0x20000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK 0x40000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCSEL_MASK 0x80000000L
+//DC_GPIO_AUX_CTRL_1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT 0x0
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT 0x1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT 0x2
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT 0x3
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT 0x4
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT 0x5
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT 0x6
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT 0x7
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT 0x8
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT 0x9
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT 0xa
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT 0xb
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_COMPSEL__SHIFT 0xc
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_COMPSEL__SHIFT 0xd
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT 0xe
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SPARE__SHIFT 0x10
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT 0x12
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SLEWN__SHIFT 0x13
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT 0x14
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_RXSEL__SHIFT 0x16
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_PDEN__SHIFT 0x18
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK 0x00000001L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK 0x00000002L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK 0x00000004L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK 0x00000008L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK 0x00000010L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK 0x00000020L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK 0x00000040L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK 0x00000080L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK 0x00000100L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK 0x00000200L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK 0x00000400L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK 0x00000800L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_COMPSEL_MASK 0x00001000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_COMPSEL_MASK 0x00002000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK 0x0000C000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SPARE_MASK 0x00030000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK 0x00040000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SLEWN_MASK 0x00080000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK 0x00300000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_RXSEL_MASK 0x00C00000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_PDEN_MASK 0x01000000L
+//DC_GPIO_AUX_CTRL_2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT 0x0
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT 0x2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT 0x4
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT 0x8
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT 0x9
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT 0xa
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT 0xc
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT 0xd
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT 0xe
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT 0x10
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT 0x11
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT 0x12
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT 0x13
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT 0x14
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT 0x18
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT 0x19
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT 0x1a
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK 0x00000003L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK 0x0000000CL
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK 0x00000030L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK 0x00000100L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK 0x00000200L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK 0x00000400L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK 0x00001000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK 0x00002000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK 0x00004000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK 0x00010000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK 0x00020000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK 0x00040000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK 0x00080000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK 0x00100000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK 0x01000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK 0x02000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK 0x04000000L
+//DC_GPIO_RXEN
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT 0x0
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT 0x1
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT 0x2
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT 0x3
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT 0x4
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT 0x5
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT 0x6
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT 0x8
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT 0x9
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT 0xa
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT 0xb
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT 0xc
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT 0xd
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT 0xe
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT 0xf
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT 0x10
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT 0x11
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT 0x12
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT 0x13
+#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN__SHIFT 0x14
+#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN__SHIFT 0x15
+#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN__SHIFT 0x16
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK 0x00000001L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK 0x00000002L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK 0x00000004L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK 0x00000008L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK 0x00000010L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK 0x00000020L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK 0x00000040L
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK 0x00000100L
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK 0x00000200L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK 0x00000400L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK 0x00000800L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK 0x00001000L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK 0x00002000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK 0x00004000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK 0x00008000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK 0x00010000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK 0x00020000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK 0x00040000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK 0x00080000L
+#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN_MASK 0x00100000L
+#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN_MASK 0x00200000L
+#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN_MASK 0x00400000L
+//BPHYC_DAC_MACRO_CNTL
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x0
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x8
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x10
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x18
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x1c
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x00000003L
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x00003F00L
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x003F0000L
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0x0F000000L
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000L
+//DAC_MACRO_CNTL_RESERVED0
+#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//BPHYC_DAC_AUTO_CALIB_CONTROL
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x0
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x1
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x2
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x4
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x14
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x1c
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x00000001L
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x00000002L
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x00000004L
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x00003FF0L
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x00700000L
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000L
+//DAC_MACRO_CNTL_RESERVED1
+#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DAC_MACRO_CNTL_RESERVED2
+#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DAC_MACRO_CNTL_RESERVED3
+#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DISP_DSI_DUAL_CTRL
+#define DISP_DSI_DUAL_CTRL__DUAL_PIPE_MODE__SHIFT 0x0
+#define DISP_DSI_DUAL_CTRL__DUAL_PIPE_MODE_MASK 0x00000001L
+//DPHY_MACRO_CNTL_RESERVED0
+#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED1
+#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED2
+#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED3
+#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED4
+#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED5
+#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED6
+#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED7
+#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED8
+#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED9
+#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED10
+#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED11
+#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED12
+#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED13
+#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED14
+#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED15
+#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED16
+#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED17
+#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED18
+#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED19
+#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED20
+#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED21
+#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED22
+#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED23
+#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED24
+#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED25
+#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED26
+#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED27
+#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED28
+#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED29
+#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED30
+#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED31
+#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED32
+#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED33
+#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED34
+#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED35
+#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED36
+#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED37
+#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED38
+#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED39
+#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED40
+#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED41
+#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED42
+#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED43
+#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED44
+#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED45
+#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED46
+#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED47
+#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED48
+#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED49
+#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED50
+#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED51
+#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED52
+#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED53
+#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED54
+#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED55
+#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED56
+#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED57
+#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED58
+#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED59
+#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED60
+#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED61
+#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED62
+#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPHY_MACRO_CNTL_RESERVED63
+#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DPRX_AUX_REFERENCE_PULSE_DIV
+#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MICROSECOND_DIV__SHIFT 0x0
+#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MICROSECOND_SOURCE_SEL__SHIFT 0xf
+#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_100_MICROSECOND_DIV__SHIFT 0x10
+#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MILLISECOND_DIV__SHIFT 0x18
+#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MICROSECOND_DIV_MASK 0x000003FFL
+#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MICROSECOND_SOURCE_SEL_MASK 0x00008000L
+#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_100_MICROSECOND_DIV_MASK 0x00FF0000L
+#define DPRX_AUX_REFERENCE_PULSE_DIV__DPRX_AUX_1_MILLISECOND_DIV_MASK 0x3F000000L
+//DPRX_AUX_CONTROL
+#define DPRX_AUX_CONTROL__DPRX_AUX_EN__SHIFT 0x0
+#define DPRX_AUX_CONTROL__DPRX_AUX_REQUEST_TIMEOUT_LEN__SHIFT 0x8
+#define DPRX_AUX_CONTROL__DPRX_AUX_IMPCAL_REQ_EN__SHIFT 0x18
+#define DPRX_AUX_CONTROL__DPRX_AUX_TEST_MODE__SHIFT 0x1c
+#define DPRX_AUX_CONTROL__DPRX_AUX_DEGLITCH_EN__SHIFT 0x1d
+#define DPRX_AUX_CONTROL__DPRX_AUX_SPARE_0__SHIFT 0x1e
+#define DPRX_AUX_CONTROL__DPRX_AUX_SPARE_1__SHIFT 0x1f
+#define DPRX_AUX_CONTROL__DPRX_AUX_EN_MASK 0x00000001L
+#define DPRX_AUX_CONTROL__DPRX_AUX_REQUEST_TIMEOUT_LEN_MASK 0x0001FF00L
+#define DPRX_AUX_CONTROL__DPRX_AUX_IMPCAL_REQ_EN_MASK 0x01000000L
+#define DPRX_AUX_CONTROL__DPRX_AUX_TEST_MODE_MASK 0x10000000L
+#define DPRX_AUX_CONTROL__DPRX_AUX_DEGLITCH_EN_MASK 0x20000000L
+#define DPRX_AUX_CONTROL__DPRX_AUX_SPARE_0_MASK 0x40000000L
+#define DPRX_AUX_CONTROL__DPRX_AUX_SPARE_1_MASK 0x80000000L
+//DPRX_AUX_HPD_CONTROL1
+#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_IRQ_PULSE_WIDTH__SHIFT 0x0
+#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_IRQ_GAP__SHIFT 0x8
+#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_A__SHIFT 0x10
+#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_EN__SHIFT 0x11
+#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_IRQ_PULSE_WIDTH_MASK 0x0000000FL
+#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_IRQ_GAP_MASK 0x00003F00L
+#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_A_MASK 0x00010000L
+#define DPRX_AUX_HPD_CONTROL1__DPRX_AUX_HPD_EN_MASK 0x00020000L
+//DPRX_AUX_HPD_CONTROL2
+#define DPRX_AUX_HPD_CONTROL2__DPRX_AUX_HPD_IRQ_TRIGGER__SHIFT 0x0
+#define DPRX_AUX_HPD_CONTROL2__DPRX_AUX_NEW_HPD_IRQ_READY__SHIFT 0x1
+#define DPRX_AUX_HPD_CONTROL2__DPRX_AUX_HPD_IRQ_TRIGGER_MASK 0x00000001L
+#define DPRX_AUX_HPD_CONTROL2__DPRX_AUX_NEW_HPD_IRQ_READY_MASK 0x00000002L
+//DPRX_AUX_RX_STATUS
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_STATUS_CLEAR__SHIFT 0x0
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_DONE__SHIFT 0x7
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_OVERFLOW__SHIFT 0x8
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_TIMEOUT__SHIFT 0x9
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_INVALID_STOP__SHIFT 0xe
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_INVALID_START__SHIFT 0x13
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_NO_DET__SHIFT 0x14
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_INVALID_H__SHIFT 0x16
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_INVALID_L__SHIFT 0x17
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_BYTE_COUNT__SHIFT 0x18
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_STATUS_CLEAR_MASK 0x00000001L
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_DONE_MASK 0x00000080L
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_OVERFLOW_MASK 0x00000100L
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_TIMEOUT_MASK 0x00000200L
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_INVALID_STOP_MASK 0x00004000L
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_INVALID_START_MASK 0x00080000L
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_NO_DET_MASK 0x00100000L
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DPRX_AUX_RX_STATUS__DPRX_AUX_RX_BYTE_COUNT_MASK 0x1F000000L
+//DPRX_AUX_RX_ERROR_MASK
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_OVERFLOW_MASK__SHIFT 0x8
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_TIMEOUT_MASK__SHIFT 0x9
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_PARTIAL_BYTE_MASK__SHIFT 0xa
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_MIN_COUNT_VIOL_MASK__SHIFT 0xc
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_INVALID_STOP_MASK__SHIFT 0xe
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_SYNC_INVALID_L_MASK__SHIFT 0x11
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_SYNC_INVALID_H_MASK__SHIFT 0x12
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_INVALID_START_MASK__SHIFT 0x13
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_NO_DET_MASK__SHIFT 0x14
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_INVALID_H_MASK__SHIFT 0x16
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_INVALID_L_MASK__SHIFT 0x17
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_OVERFLOW_MASK_MASK 0x00000100L
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_TIMEOUT_MASK_MASK 0x00000200L
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_PARTIAL_BYTE_MASK_MASK 0x00000400L
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_MIN_COUNT_VIOL_MASK_MASK 0x00001000L
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_INVALID_STOP_MASK_MASK 0x00004000L
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_SYNC_INVALID_L_MASK_MASK 0x00020000L
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_SYNC_INVALID_H_MASK_MASK 0x00040000L
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_INVALID_START_MASK_MASK 0x00080000L
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_NO_DET_MASK_MASK 0x00100000L
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_INVALID_H_MASK_MASK 0x00400000L
+#define DPRX_AUX_RX_ERROR_MASK__DPRX_AUX_RX_RECV_INVALID_L_MASK_MASK 0x00800000L
+//DPRX_AUX_DPHY_TX_REF_CONTROL
+#define DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_REF_SEL__SHIFT 0x0
+#define DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_RATE__SHIFT 0x4
+#define DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_REF_DIV__SHIFT 0x10
+#define DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_REF_SEL_MASK 0x00000001L
+#define DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_RATE_MASK 0x00000030L
+#define DPRX_AUX_DPHY_TX_REF_CONTROL__DPRX_AUX_TX_REF_DIV_MASK 0x01FF0000L
+//DPRX_AUX_DPHY_TX_CONTROL
+#define DPRX_AUX_DPHY_TX_CONTROL__DPRX_AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+#define DPRX_AUX_DPHY_TX_CONTROL__DPRX_AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+#define DPRX_AUX_DPHY_TX_CONTROL__DPRX_AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
+#define DPRX_AUX_DPHY_TX_CONTROL__DPRX_AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
+//DPRX_AUX_DPHY_RX_CONTROL0
+#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_START_WINDOW__SHIFT 0x4
+#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_START_WINDOW_MASK 0x00000070L
+#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
+#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
+#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
+#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
+#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
+#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
+#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
+#define DPRX_AUX_DPHY_RX_CONTROL0__DPRX_AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
+//DPRX_AUX_DPHY_RX_CONTROL1
+#define DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+#define DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_TIMEOUT_LEN__SHIFT 0x8
+#define DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_TIMEOUT_COUNTER_START__SHIFT 0x18
+#define DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
+#define DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_TIMEOUT_LEN_MASK 0x0001FF00L
+#define DPRX_AUX_DPHY_RX_CONTROL1__DPRX_AUX_RX_TIMEOUT_COUNTER_START_MASK 0x1F000000L
+//DPRX_AUX_DPHY_TX_STATUS
+#define DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_ACTIVE__SHIFT 0x0
+#define DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_STATE__SHIFT 0x4
+#define DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+#define DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_ACTIVE_MASK 0x00000001L
+#define DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_STATE_MASK 0x000000F0L
+#define DPRX_AUX_DPHY_TX_STATUS__DPRX_AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
+//DPRX_AUX_DPHY_RX_STATUS
+#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_STATE__SHIFT 0x0
+#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_STATE_MASK 0x00000007L
+#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
+#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
+#define DPRX_AUX_DPHY_RX_STATUS__DPRX_AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
+//DPRX_AUX_DMCU_HW_INT_STATUS
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_INT_STATUS__SHIFT 0x0
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_INT_STATUS__SHIFT 0x1
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_STATUS__SHIFT 0x2
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_STATUS__SHIFT 0x3
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_STATUS__SHIFT 0x4
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_STATUS__SHIFT 0x5
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_INT_MASK__SHIFT 0x8
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_INT_MASK__SHIFT 0x9
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_MASK__SHIFT 0xa
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_MASK__SHIFT 0xb
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_MASK__SHIFT 0xc
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_MASK__SHIFT 0xd
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_EVENT_OCCURRED__SHIFT 0x10
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_EVENT_OCCURRED__SHIFT 0x11
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_EVENT_OCCURRED__SHIFT 0x12
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_EVENT_OCCURRED__SHIFT 0x13
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_EVENT_OCCURRED__SHIFT 0x14
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_EVENT_OCCURRED__SHIFT 0x15
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_INT_STATUS_MASK 0x00000001L
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_INT_STATUS_MASK 0x00000002L
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_STATUS_MASK 0x00000004L
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_STATUS_MASK 0x00000008L
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_STATUS_MASK 0x00000010L
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_STATUS_MASK 0x00000020L
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_INT_MASK_MASK 0x00000100L
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_INT_MASK_MASK 0x00000200L
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_MASK_MASK 0x00000400L
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_MASK_MASK 0x00000800L
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_MASK_MASK 0x00001000L
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_MASK_MASK 0x00002000L
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_AUX_EVENT_OCCURRED_MASK 0x00010000L
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_I2C_EVENT_OCCURRED_MASK 0x00020000L
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG1_TIMEOUT_EVENT_OCCURRED_MASK 0x00040000L
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG2_TIMEOUT_EVENT_OCCURRED_MASK 0x00080000L
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG3_TIMEOUT_EVENT_OCCURRED_MASK 0x00100000L
+#define DPRX_AUX_DMCU_HW_INT_STATUS__DPRX_AUX_DMCU_MSG4_TIMEOUT_EVENT_OCCURRED_MASK 0x00200000L
+//DPRX_AUX_DMCU_HW_INT_ACK
+#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_AUX_INT_ACK__SHIFT 0x0
+#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_I2C_INT_ACK__SHIFT 0x1
+#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_ACK__SHIFT 0x2
+#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_ACK__SHIFT 0x3
+#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_ACK__SHIFT 0x4
+#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_ACK__SHIFT 0x5
+#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_AUX_INT_ACK_MASK 0x00000001L
+#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_I2C_INT_ACK_MASK 0x00000002L
+#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_ACK_MASK 0x00000004L
+#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_ACK_MASK 0x00000008L
+#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_ACK_MASK 0x00000010L
+#define DPRX_AUX_DMCU_HW_INT_ACK__DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_ACK_MASK 0x00000020L
+//DPRX_AUX_CPU_TO_DMCU_INTERRUPT1
+#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT1__DPRX_AUX_CPU_TO_DMCU_INT_TRIGGER__SHIFT 0x0
+#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT1__DPRX_AUX_CPU_TO_DMCU_INT_TRIGGER_MASK 0x00000001L
+//DPRX_AUX_CPU_TO_DMCU_INTERRUPT2
+#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_MASK__SHIFT 0x0
+#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_ACK__SHIFT 0x8
+#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_STATUS__SHIFT 0x10
+#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_MASK_MASK 0x00000001L
+#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_ACK_MASK 0x00000100L
+#define DPRX_AUX_CPU_TO_DMCU_INTERRUPT2__DPRX_AUX_CPU_TO_DMCU_INT_STATUS_MASK 0x00010000L
+//DPRX_AUX_DMCU_TO_CPU_INTERRUPT1
+#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT1__DPRX_AUX_DMCU_TO_CPU_INT_TRIGGER__SHIFT 0x0
+#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT1__DPRX_AUX_DMCU_TO_CPU_INT_TRIGGER_MASK 0x00000001L
+//DPRX_AUX_DMCU_TO_CPU_INTERRUPT2
+#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_MASK__SHIFT 0x0
+#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_TYPE__SHIFT 0x1
+#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_ACK__SHIFT 0x8
+#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_OCCURRED__SHIFT 0x10
+#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_MASK_MASK 0x00000001L
+#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_TYPE_MASK 0x00000002L
+#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_ACK_MASK 0x00000100L
+#define DPRX_AUX_DMCU_TO_CPU_INTERRUPT2__DPRX_AUX_DMCU_TO_CPU_INT_OCCURRED_MASK 0x00010000L
+//DPRX_AUX_AUX_BUF_INDEX
+#define DPRX_AUX_AUX_BUF_INDEX__DPRX_AUX_AUX_BUF_INDEX__SHIFT 0x0
+#define DPRX_AUX_AUX_BUF_INDEX__DPRX_AUX_AUX_BUF_INDEX_MASK 0x0000007FL
+//DPRX_AUX_AUX_BUF_DATA
+#define DPRX_AUX_AUX_BUF_DATA__DPRX_AUX_AUX_BUF_DATA__SHIFT 0x0
+#define DPRX_AUX_AUX_BUF_DATA__DPRX_AUX_AUX_BUF_DATA_MASK 0xFFFFFFFFL
+//DPRX_AUX_EDID_INDEX
+#define DPRX_AUX_EDID_INDEX__DPRX_AUX_EDID_INDEX__SHIFT 0x0
+#define DPRX_AUX_EDID_INDEX__DPRX_AUX_EDID_MODE__SHIFT 0x10
+#define DPRX_AUX_EDID_INDEX__DPRX_AUX_EDID_INDEX_MASK 0x000003FFL
+#define DPRX_AUX_EDID_INDEX__DPRX_AUX_EDID_MODE_MASK 0x00010000L
+//DPRX_AUX_EDID_DATA
+#define DPRX_AUX_EDID_DATA__DPRX_AUX_EDID_DATA__SHIFT 0x0
+#define DPRX_AUX_EDID_DATA__DPRX_AUX_EDID_DATA_MASK 0xFFFFFFFFL
+//DPRX_AUX_DPCD_INDEX1
+#define DPRX_AUX_DPCD_INDEX1__DPRX_AUX_DPCD_INDEX1__SHIFT 0x0
+#define DPRX_AUX_DPCD_INDEX1__DPRX_AUX_DPCD_MODE1__SHIFT 0x10
+#define DPRX_AUX_DPCD_INDEX1__DPRX_AUX_DPCD_INDEX1_MASK 0x000007FFL
+#define DPRX_AUX_DPCD_INDEX1__DPRX_AUX_DPCD_MODE1_MASK 0x00010000L
+//DPRX_AUX_DPCD_DATA1
+#define DPRX_AUX_DPCD_DATA1__DPRX_AUX_DPCD_DATA1__SHIFT 0x0
+#define DPRX_AUX_DPCD_DATA1__DPRX_AUX_DPCD_DATA1_MASK 0xFFFFFFFFL
+//DPRX_AUX_DPCD_INDEX2
+#define DPRX_AUX_DPCD_INDEX2__DPRX_AUX_DPCD_INDEX2__SHIFT 0x0
+#define DPRX_AUX_DPCD_INDEX2__DPRX_AUX_DPCD_MODE2__SHIFT 0x10
+#define DPRX_AUX_DPCD_INDEX2__DPRX_AUX_DPCD_INDEX2_MASK 0x000007FFL
+#define DPRX_AUX_DPCD_INDEX2__DPRX_AUX_DPCD_MODE2_MASK 0x00010000L
+//DPRX_AUX_DPCD_DATA2
+#define DPRX_AUX_DPCD_DATA2__DPRX_AUX_DPCD_DATA2__SHIFT 0x0
+#define DPRX_AUX_DPCD_DATA2__DPRX_AUX_DPCD_DATA2_MASK 0xFFFFFFFFL
+//DPRX_AUX_MSG_INDEX1
+#define DPRX_AUX_MSG_INDEX1__DPRX_AUX_MSG_INDEX1__SHIFT 0x0
+#define DPRX_AUX_MSG_INDEX1__DPRX_AUX_MSG_MODE1__SHIFT 0x10
+#define DPRX_AUX_MSG_INDEX1__DPRX_AUX_MSG_INDEX1_MASK 0x000003FFL
+#define DPRX_AUX_MSG_INDEX1__DPRX_AUX_MSG_MODE1_MASK 0x00010000L
+//DPRX_AUX_MSG_DATA1
+#define DPRX_AUX_MSG_DATA1__DPRX_AUX_MSG_DATA1__SHIFT 0x0
+#define DPRX_AUX_MSG_DATA1__DPRX_AUX_MSG_DATA1_MASK 0xFFFFFFFFL
+//DPRX_AUX_MSG_INDEX2
+#define DPRX_AUX_MSG_INDEX2__DPRX_AUX_MSG_INDEX2__SHIFT 0x0
+#define DPRX_AUX_MSG_INDEX2__DPRX_AUX_MSG_MODE2__SHIFT 0x10
+#define DPRX_AUX_MSG_INDEX2__DPRX_AUX_MSG_INDEX2_MASK 0x000003FFL
+#define DPRX_AUX_MSG_INDEX2__DPRX_AUX_MSG_MODE2_MASK 0x00010000L
+//DPRX_AUX_MSG_DATA2
+#define DPRX_AUX_MSG_DATA2__DPRX_AUX_MSG_DATA2__SHIFT 0x0
+#define DPRX_AUX_MSG_DATA2__DPRX_AUX_MSG_DATA2_MASK 0xFFFFFFFFL
+//DPRX_AUX_KSV_INDEX1
+#define DPRX_AUX_KSV_INDEX1__DPRX_AUX_KSV_INDEX1__SHIFT 0x0
+#define DPRX_AUX_KSV_INDEX1__DPRX_AUX_KSV_MODE1__SHIFT 0x10
+#define DPRX_AUX_KSV_INDEX1__DPRX_AUX_KSV_INDEX1_MASK 0x000003FFL
+#define DPRX_AUX_KSV_INDEX1__DPRX_AUX_KSV_MODE1_MASK 0x00010000L
+//DPRX_AUX_KSV_DATA1
+#define DPRX_AUX_KSV_DATA1__DPRX_AUX_KSV_DATA1__SHIFT 0x0
+#define DPRX_AUX_KSV_DATA1__DPRX_AUX_KSV_DATA1_MASK 0xFFFFFFFFL
+//DPRX_AUX_KSV_INDEX2
+#define DPRX_AUX_KSV_INDEX2__DPRX_AUX_KSV_INDEX2__SHIFT 0x0
+#define DPRX_AUX_KSV_INDEX2__DPRX_AUX_KSV_MODE2__SHIFT 0x10
+#define DPRX_AUX_KSV_INDEX2__DPRX_AUX_KSV_INDEX2_MASK 0x000003FFL
+#define DPRX_AUX_KSV_INDEX2__DPRX_AUX_KSV_MODE2_MASK 0x00010000L
+//DPRX_AUX_KSV_DATA2
+#define DPRX_AUX_KSV_DATA2__DPRX_AUX_KSV_DATA2__SHIFT 0x0
+#define DPRX_AUX_KSV_DATA2__DPRX_AUX_KSV_DATA2_MASK 0xFFFFFFFFL
+//DPRX_AUX_MSG_TIMEOUT_CONTROL
+#define DPRX_AUX_MSG_TIMEOUT_CONTROL__DPRX_AUX_MSG_TIMEOUT_LEN__SHIFT 0x0
+#define DPRX_AUX_MSG_TIMEOUT_CONTROL__DPRX_AUX_MSG_TIMEOUT_LEN_MASK 0x000000FFL
+//DPRX_AUX_MSG_BUF_CONTROL1
+#define DPRX_AUX_MSG_BUF_CONTROL1__DPRX_AUX_MSG_REP_WRITE_REQ1__SHIFT 0x0
+#define DPRX_AUX_MSG_BUF_CONTROL1__DPRX_AUX_MSG_REP_WRITE_GNT1__SHIFT 0x1
+#define DPRX_AUX_MSG_BUF_CONTROL1__DPRX_AUX_MSG_REP_WRITE_REQ1_MASK 0x00000001L
+#define DPRX_AUX_MSG_BUF_CONTROL1__DPRX_AUX_MSG_REP_WRITE_GNT1_MASK 0x00000002L
+//DPRX_AUX_MSG_BUF_CONTROL2
+#define DPRX_AUX_MSG_BUF_CONTROL2__DPRX_AUX_MSG_REP_WRITE_REQ2__SHIFT 0x0
+#define DPRX_AUX_MSG_BUF_CONTROL2__DPRX_AUX_MSG_REP_WRITE_GNT2__SHIFT 0x1
+#define DPRX_AUX_MSG_BUF_CONTROL2__DPRX_AUX_MSG_REP_WRITE_REQ2_MASK 0x00000001L
+#define DPRX_AUX_MSG_BUF_CONTROL2__DPRX_AUX_MSG_REP_WRITE_GNT2_MASK 0x00000002L
+//DPRX_AUX_SCRATCH1
+#define DPRX_AUX_SCRATCH1__DPRX_AUX_SCRATCH1__SHIFT 0x0
+#define DPRX_AUX_SCRATCH1__DPRX_AUX_SCRATCH1_MASK 0xFFFFFFFFL
+//DPRX_AUX_SCRATCH2
+#define DPRX_AUX_SCRATCH2__DPRX_AUX_SCRATCH2__SHIFT 0x0
+#define DPRX_AUX_SCRATCH2__DPRX_AUX_SCRATCH2_MASK 0xFFFFFFFFL
+//DPRX_AUX_MSG1_PENDING
+#define DPRX_AUX_MSG1_PENDING__DPRX_AUX_MSG1_PENDING__SHIFT 0x0
+#define DPRX_AUX_MSG1_PENDING__DPRX_AUX_MSG1_PENDING_MASK 0x00000001L
+//DPRX_AUX_MSG2_PENDING
+#define DPRX_AUX_MSG2_PENDING__DPRX_AUX_MSG2_PENDING__SHIFT 0x0
+#define DPRX_AUX_MSG2_PENDING__DPRX_AUX_MSG2_PENDING_MASK 0x00000001L
+//DPRX_AUX_MSG3_PENDING
+#define DPRX_AUX_MSG3_PENDING__DPRX_AUX_MSG3_PENDING__SHIFT 0x0
+#define DPRX_AUX_MSG3_PENDING__DPRX_AUX_MSG3_PENDING_MASK 0x00000001L
+//DPRX_AUX_MSG4_PENDING
+#define DPRX_AUX_MSG4_PENDING__DPRX_AUX_MSG4_PENDING__SHIFT 0x0
+#define DPRX_AUX_MSG4_PENDING__DPRX_AUX_MSG4_PENDING_MASK 0x00000001L
+//DPRX_DPHY_DPCD_LANE_COUNT_SET
+#define DPRX_DPHY_DPCD_LANE_COUNT_SET__LANE_COUNT_SET__SHIFT 0x0
+#define DPRX_DPHY_DPCD_LANE_COUNT_SET__LANE_COUNT_SET_MASK 0x0000001FL
+//DPRX_DPHY_DPCD_TRAINING_PATTERN_SET
+#define DPRX_DPHY_DPCD_TRAINING_PATTERN_SET__TRAINING_PATTERN_SET__SHIFT 0x0
+#define DPRX_DPHY_DPCD_TRAINING_PATTERN_SET__TRAINING_PATTERN_SET_MASK 0x00000003L
+//DPRX_DPHY_DPCD_MSTM_CTRL
+#define DPRX_DPHY_DPCD_MSTM_CTRL__MST_EN__SHIFT 0x0
+#define DPRX_DPHY_DPCD_MSTM_CTRL__MST_EN_MASK 0x00000001L
+//DPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET__LANE0_LINK_QUAL_PATTERN_SET__SHIFT 0x0
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET__LANE0_LINK_QUAL_PATTERN_SET_MASK 0x00000007L
+//DPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS__LANE0_LINK_QUAL_PATTERN_DETECT__SHIFT 0x0
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS__LANE0_HBR2_COMPL_EYE_PATTERN_DETECT__SHIFT 0x3
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS__LANE0_LINK_QUAL_PATTERN_DETECT_MASK 0x00000007L
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS__LANE0_HBR2_COMPL_EYE_PATTERN_DETECT_MASK 0x00000018L
+//DPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET__LANE1_LINK_QUAL_PATTERN_SET__SHIFT 0x0
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET__LANE1_LINK_QUAL_PATTERN_SET_MASK 0x00000007L
+//DPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS__LANE1_LINK_QUAL_PATTERN_DETECT__SHIFT 0x0
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS__LANE1_HBR2_COMPL_EYE_PATTERN_DETECT__SHIFT 0x3
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS__LANE1_LINK_QUAL_PATTERN_DETECT_MASK 0x00000007L
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS__LANE1_HBR2_COMPL_EYE_PATTERN_DETECT_MASK 0x00000018L
+//DPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET__LANE2_LINK_QUAL_PATTERN_SET__SHIFT 0x0
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET__LANE2_LINK_QUAL_PATTERN_SET_MASK 0x00000007L
+//DPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS__LANE2_LINK_QUAL_PATTERN_DETECT__SHIFT 0x0
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS__LANE2_HBR2_COMPL_EYE_PATTERN_DETECT__SHIFT 0x3
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS__LANE2_LINK_QUAL_PATTERN_DETECT_MASK 0x00000007L
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS__LANE2_HBR2_COMPL_EYE_PATTERN_DETECT_MASK 0x00000018L
+//DPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET__LANE3_LINK_QUAL_PATTERN_SET__SHIFT 0x0
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET__LANE3_LINK_QUAL_PATTERN_SET_MASK 0x00000007L
+//DPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS__LANE3_LINK_QUAL_PATTERN_DETECT__SHIFT 0x0
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS__LANE3_HBR2_COMPL_EYE_PATTERN_DETECT__SHIFT 0x3
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS__LANE3_LINK_QUAL_PATTERN_DETECT_MASK 0x00000007L
+#define DPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS__LANE3_HBR2_COMPL_EYE_PATTERN_DETECT_MASK 0x00000018L
+//DPRX_DPHY_READY
+#define DPRX_DPHY_READY__CP_READY__SHIFT 0x0
+#define DPRX_DPHY_READY__ACT_READY__SHIFT 0x1
+#define DPRX_DPHY_READY__SDOUT_READY__SHIFT 0x2
+#define DPRX_DPHY_READY__ACT_READY_CLR__SHIFT 0x3
+#define DPRX_DPHY_READY__MVOTE_DATA_ERROR__SHIFT 0x4
+#define DPRX_DPHY_READY__MVOTE_DATA_ERROR_CLR__SHIFT 0x5
+#define DPRX_DPHY_READY__MVOTE_KCODE_ERROR__SHIFT 0x6
+#define DPRX_DPHY_READY__MVOTE_KCODE_ERROR_CLR__SHIFT 0x7
+#define DPRX_DPHY_READY__CP_READY_MASK 0x00000001L
+#define DPRX_DPHY_READY__ACT_READY_MASK 0x00000002L
+#define DPRX_DPHY_READY__SDOUT_READY_MASK 0x00000004L
+#define DPRX_DPHY_READY__ACT_READY_CLR_MASK 0x00000008L
+#define DPRX_DPHY_READY__MVOTE_DATA_ERROR_MASK 0x00000010L
+#define DPRX_DPHY_READY__MVOTE_DATA_ERROR_CLR_MASK 0x00000020L
+#define DPRX_DPHY_READY__MVOTE_KCODE_ERROR_MASK 0x00000040L
+#define DPRX_DPHY_READY__MVOTE_KCODE_ERROR_CLR_MASK 0x00000080L
+//DPRX_DPHY_COMMA_STATUS
+#define DPRX_DPHY_COMMA_STATUS__LANE0_COMMA_LOCKED__SHIFT 0x0
+#define DPRX_DPHY_COMMA_STATUS__LANE1_COMMA_LOCKED__SHIFT 0x1
+#define DPRX_DPHY_COMMA_STATUS__LANE2_COMMA_LOCKED__SHIFT 0x2
+#define DPRX_DPHY_COMMA_STATUS__LANE3_COMMA_LOCKED__SHIFT 0x3
+#define DPRX_DPHY_COMMA_STATUS__LANE0_SR_LOCKED__SHIFT 0x4
+#define DPRX_DPHY_COMMA_STATUS__LANE1_SR_LOCKED__SHIFT 0x5
+#define DPRX_DPHY_COMMA_STATUS__LANE2_SR_LOCKED__SHIFT 0x6
+#define DPRX_DPHY_COMMA_STATUS__LANE3_SR_LOCKED__SHIFT 0x7
+#define DPRX_DPHY_COMMA_STATUS__LANE0_COMMA_LOCKED_MASK 0x00000001L
+#define DPRX_DPHY_COMMA_STATUS__LANE1_COMMA_LOCKED_MASK 0x00000002L
+#define DPRX_DPHY_COMMA_STATUS__LANE2_COMMA_LOCKED_MASK 0x00000004L
+#define DPRX_DPHY_COMMA_STATUS__LANE3_COMMA_LOCKED_MASK 0x00000008L
+#define DPRX_DPHY_COMMA_STATUS__LANE0_SR_LOCKED_MASK 0x00000010L
+#define DPRX_DPHY_COMMA_STATUS__LANE1_SR_LOCKED_MASK 0x00000020L
+#define DPRX_DPHY_COMMA_STATUS__LANE2_SR_LOCKED_MASK 0x00000040L
+#define DPRX_DPHY_COMMA_STATUS__LANE3_SR_LOCKED_MASK 0x00000080L
+//DPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED
+#define DPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED__LANE0_INTERLANE_ALIGN_ERROR_COUNT__SHIFT 0x0
+#define DPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED__LANE0_INTERLANE_ALIGN_ERROR_COUNT_MASK 0x0000000FL
+//DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED
+#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_DONE__SHIFT 0x0
+#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_CHECK_DONE__SHIFT 0x1
+#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_FIFO_LEVEL__SHIFT 0x2
+#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_STATE__SHIFT 0x19
+#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_WAIT_COUNT__SHIFT 0x1b
+#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_DONE_MASK 0x00000001L
+#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_CHECK_DONE_MASK 0x00000002L
+#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_FIFO_LEVEL_MASK 0x0003FFFCL
+#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_STATE_MASK 0x06000000L
+#define DPRX_DPHY_LANE_ALIGN_STATUS_UPDATED__INTERLANE_ALIGN_WAIT_COUNT_MASK 0xF8000000L
+//DPRX_DPHY_ERROR_THRESH_A_LANE0
+#define DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_SYMBOL_ERROR_COUNT_THRESH__SHIFT 0x0
+#define DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_DISPARITY_ERROR_COUNT_THRESH__SHIFT 0x8
+#define DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_TEST_PATTERN_ERROR_THRESH__SHIFT 0x18
+#define DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_SYMBOL_ERROR_COUNT_THRESH_MASK 0x000000FFL
+#define DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_DISPARITY_ERROR_COUNT_THRESH_MASK 0x0000FF00L
+#define DPRX_DPHY_ERROR_THRESH_A_LANE0__LANE0_TEST_PATTERN_ERROR_THRESH_MASK 0xFF000000L
+//DPRX_DPHY_ERROR_COUNT_A_LANE0
+#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_SYMBOL_ERROR_COUNT__SHIFT 0x0
+#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_SYMBOL_ERROR_COUNT_VALID__SHIFT 0xf
+#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_DISPARITY_ERROR_COUNT__SHIFT 0x10
+#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_DISPARITY_ERROR_COUNT_VALID__SHIFT 0x1f
+#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_SYMBOL_ERROR_COUNT_MASK 0x00007FFFL
+#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_SYMBOL_ERROR_COUNT_VALID_MASK 0x00008000L
+#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_DISPARITY_ERROR_COUNT_MASK 0x7FFF0000L
+#define DPRX_DPHY_ERROR_COUNT_A_LANE0__LANE0_DISPARITY_ERROR_COUNT_VALID_MASK 0x80000000L
+//DPRX_DPHY_ERROR_COUNT_B_LANE0
+#define DPRX_DPHY_ERROR_COUNT_B_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT__SHIFT 0x10
+#define DPRX_DPHY_ERROR_COUNT_B_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT_VALID__SHIFT 0x1f
+#define DPRX_DPHY_ERROR_COUNT_B_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT_MASK 0x7FFF0000L
+#define DPRX_DPHY_ERROR_COUNT_B_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT_VALID_MASK 0x80000000L
+//DPRX_DPHY_ERROR_COUNT_C_LANE0
+#define DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_SYMBOL_ERROR_COUNT_CLR__SHIFT 0x1b
+#define DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_DISPARITY_ERROR_COUNT_CLR__SHIFT 0x1c
+#define DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT_CLR__SHIFT 0x1e
+#define DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_SYMBOL_ERROR_COUNT_CLR_MASK 0x08000000L
+#define DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_DISPARITY_ERROR_COUNT_CLR_MASK 0x10000000L
+#define DPRX_DPHY_ERROR_COUNT_C_LANE0__LANE0_TEST_PATTERN_ERROR_COUNT_CLR_MASK 0x40000000L
+//DPRX_DPHY_ERROR_THRESH_A_LANE1
+#define DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_SYMBOL_ERROR_COUNT_THRESH__SHIFT 0x0
+#define DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_DISPARITY_ERROR_COUNT_THRESH__SHIFT 0x8
+#define DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_TEST_PATTERN_ERROR_THRESH__SHIFT 0x18
+#define DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_SYMBOL_ERROR_COUNT_THRESH_MASK 0x000000FFL
+#define DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_DISPARITY_ERROR_COUNT_THRESH_MASK 0x0000FF00L
+#define DPRX_DPHY_ERROR_THRESH_A_LANE1__LANE1_TEST_PATTERN_ERROR_THRESH_MASK 0xFF000000L
+//DPRX_DPHY_ERROR_COUNT_A_LANE1
+#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_SYMBOL_ERROR_COUNT__SHIFT 0x0
+#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_SYMBOL_ERROR_COUNT_VALID__SHIFT 0xf
+#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_DISPARITY_ERROR_COUNT__SHIFT 0x10
+#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_DISPARITY_ERROR_COUNT_VALID__SHIFT 0x1f
+#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_SYMBOL_ERROR_COUNT_MASK 0x00007FFFL
+#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_SYMBOL_ERROR_COUNT_VALID_MASK 0x00008000L
+#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_DISPARITY_ERROR_COUNT_MASK 0x7FFF0000L
+#define DPRX_DPHY_ERROR_COUNT_A_LANE1__LANE1_DISPARITY_ERROR_COUNT_VALID_MASK 0x80000000L
+//DPRX_DPHY_ERROR_COUNT_B_LANE1
+#define DPRX_DPHY_ERROR_COUNT_B_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT__SHIFT 0x10
+#define DPRX_DPHY_ERROR_COUNT_B_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT_VALID__SHIFT 0x1f
+#define DPRX_DPHY_ERROR_COUNT_B_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT_MASK 0x7FFF0000L
+#define DPRX_DPHY_ERROR_COUNT_B_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT_VALID_MASK 0x80000000L
+//DPRX_DPHY_ERROR_COUNT_C_LANE1
+#define DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_SYMBOL_ERROR_COUNT_CLR__SHIFT 0x1b
+#define DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_DISPARITY_ERROR_COUNT_CLR__SHIFT 0x1c
+#define DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT_CLR__SHIFT 0x1e
+#define DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_SYMBOL_ERROR_COUNT_CLR_MASK 0x08000000L
+#define DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_DISPARITY_ERROR_COUNT_CLR_MASK 0x10000000L
+#define DPRX_DPHY_ERROR_COUNT_C_LANE1__LANE1_TEST_PATTERN_ERROR_COUNT_CLR_MASK 0x40000000L
+//DPRX_DPHY_ERROR_THRESH_A_LANE2
+#define DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_SYMBOL_ERROR_COUNT_THRESH__SHIFT 0x0
+#define DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_DISPARITY_ERROR_COUNT_THRESH__SHIFT 0x8
+#define DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_TEST_PATTERN_ERROR_THRESH__SHIFT 0x18
+#define DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_SYMBOL_ERROR_COUNT_THRESH_MASK 0x000000FFL
+#define DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_DISPARITY_ERROR_COUNT_THRESH_MASK 0x0000FF00L
+#define DPRX_DPHY_ERROR_THRESH_A_LANE2__LANE2_TEST_PATTERN_ERROR_THRESH_MASK 0xFF000000L
+//DPRX_DPHY_ERROR_COUNT_A_LANE2
+#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_SYMBOL_ERROR_COUNT__SHIFT 0x0
+#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_SYMBOL_ERROR_COUNT_VALID__SHIFT 0xf
+#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_DISPARITY_ERROR_COUNT__SHIFT 0x10
+#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_DISPARITY_ERROR_COUNT_VALID__SHIFT 0x1f
+#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_SYMBOL_ERROR_COUNT_MASK 0x00007FFFL
+#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_SYMBOL_ERROR_COUNT_VALID_MASK 0x00008000L
+#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_DISPARITY_ERROR_COUNT_MASK 0x7FFF0000L
+#define DPRX_DPHY_ERROR_COUNT_A_LANE2__LANE2_DISPARITY_ERROR_COUNT_VALID_MASK 0x80000000L
+//DPRX_DPHY_ERROR_COUNT_B_LANE2
+#define DPRX_DPHY_ERROR_COUNT_B_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT__SHIFT 0x10
+#define DPRX_DPHY_ERROR_COUNT_B_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT_VALID__SHIFT 0x1f
+#define DPRX_DPHY_ERROR_COUNT_B_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT_MASK 0x7FFF0000L
+#define DPRX_DPHY_ERROR_COUNT_B_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT_VALID_MASK 0x80000000L
+//DPRX_DPHY_ERROR_COUNT_C_LANE2
+#define DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_SYMBOL_ERROR_COUNT_CLR__SHIFT 0x1b
+#define DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_DISPARITY_ERROR_COUNT_CLR__SHIFT 0x1c
+#define DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT_CLR__SHIFT 0x1e
+#define DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_SYMBOL_ERROR_COUNT_CLR_MASK 0x08000000L
+#define DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_DISPARITY_ERROR_COUNT_CLR_MASK 0x10000000L
+#define DPRX_DPHY_ERROR_COUNT_C_LANE2__LANE2_TEST_PATTERN_ERROR_COUNT_CLR_MASK 0x40000000L
+//DPRX_DPHY_ERROR_THRESH_A_LANE3
+#define DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_SYMBOL_ERROR_COUNT_THRESH__SHIFT 0x0
+#define DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_DISPARITY_ERROR_COUNT_THRESH__SHIFT 0x8
+#define DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_TEST_PATTERN_ERROR_THRESH__SHIFT 0x18
+#define DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_SYMBOL_ERROR_COUNT_THRESH_MASK 0x000000FFL
+#define DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_DISPARITY_ERROR_COUNT_THRESH_MASK 0x0000FF00L
+#define DPRX_DPHY_ERROR_THRESH_A_LANE3__LANE3_TEST_PATTERN_ERROR_THRESH_MASK 0xFF000000L
+//DPRX_DPHY_ERROR_COUNT_A_LANE3
+#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_SYMBOL_ERROR_COUNT__SHIFT 0x0
+#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_SYMBOL_ERROR_COUNT_VALID__SHIFT 0xf
+#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_DISPARITY_ERROR_COUNT__SHIFT 0x10
+#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_DISPARITY_ERROR_COUNT_VALID__SHIFT 0x1f
+#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_SYMBOL_ERROR_COUNT_MASK 0x00007FFFL
+#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_SYMBOL_ERROR_COUNT_VALID_MASK 0x00008000L
+#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_DISPARITY_ERROR_COUNT_MASK 0x7FFF0000L
+#define DPRX_DPHY_ERROR_COUNT_A_LANE3__LANE3_DISPARITY_ERROR_COUNT_VALID_MASK 0x80000000L
+//DPRX_DPHY_ERROR_COUNT_B_LANE3
+#define DPRX_DPHY_ERROR_COUNT_B_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT__SHIFT 0x10
+#define DPRX_DPHY_ERROR_COUNT_B_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT_VALID__SHIFT 0x1f
+#define DPRX_DPHY_ERROR_COUNT_B_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT_MASK 0x7FFF0000L
+#define DPRX_DPHY_ERROR_COUNT_B_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT_VALID_MASK 0x80000000L
+//DPRX_DPHY_ERROR_COUNT_C_LANE3
+#define DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_SYMBOL_ERROR_COUNT_CLR__SHIFT 0x1b
+#define DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_DISPARITY_ERROR_COUNT_CLR__SHIFT 0x1c
+#define DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT_CLR__SHIFT 0x1e
+#define DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_SYMBOL_ERROR_COUNT_CLR_MASK 0x08000000L
+#define DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_DISPARITY_ERROR_COUNT_CLR_MASK 0x10000000L
+#define DPRX_DPHY_ERROR_COUNT_C_LANE3__LANE3_TEST_PATTERN_ERROR_COUNT_CLR_MASK 0x40000000L
+//DPRX_DPHY_BS_ERROR_THRESH_GLOBAL
+#define DPRX_DPHY_BS_ERROR_THRESH_GLOBAL__BS_INTERVAL_ERROR_THRESH__SHIFT 0x0
+#define DPRX_DPHY_BS_ERROR_THRESH_GLOBAL__BS_INTERVAL_UNCERTAINTY_THRESH__SHIFT 0x8
+#define DPRX_DPHY_BS_ERROR_THRESH_GLOBAL__BS_INTERVAL_ERROR_THRESH_MASK 0x0000001FL
+#define DPRX_DPHY_BS_ERROR_THRESH_GLOBAL__BS_INTERVAL_UNCERTAINTY_THRESH_MASK 0x0000FF00L
+//DPRX_DPHY_SR_ERROR_COUNT_A
+#define DPRX_DPHY_SR_ERROR_COUNT_A__SR_ERROR_COUNT__SHIFT 0x0
+#define DPRX_DPHY_SR_ERROR_COUNT_A__SR_INTERVAL_COUNT__SHIFT 0x8
+#define DPRX_DPHY_SR_ERROR_COUNT_A__SR_ERROR_COUNT_CLR__SHIFT 0x19
+#define DPRX_DPHY_SR_ERROR_COUNT_A__SR_ERROR_COUNT_MASK 0x000000FFL
+#define DPRX_DPHY_SR_ERROR_COUNT_A__SR_INTERVAL_COUNT_MASK 0x01FFFF00L
+#define DPRX_DPHY_SR_ERROR_COUNT_A__SR_ERROR_COUNT_CLR_MASK 0x02000000L
+//DPRX_DPHY_BS_ERROR_COUNT_A
+#define DPRX_DPHY_BS_ERROR_COUNT_A__BS_ERROR_COUNT__SHIFT 0x0
+#define DPRX_DPHY_BS_ERROR_COUNT_A__BS_INTERVAL_COUNT__SHIFT 0x8
+#define DPRX_DPHY_BS_ERROR_COUNT_A__BS_ERROR_COUNT_CLR__SHIFT 0x19
+#define DPRX_DPHY_BS_ERROR_COUNT_A__BS_ERROR_COUNT_MASK 0x000000FFL
+#define DPRX_DPHY_BS_ERROR_COUNT_A__BS_INTERVAL_COUNT_MASK 0x01FFFF00L
+#define DPRX_DPHY_BS_ERROR_COUNT_A__BS_ERROR_COUNT_CLR_MASK 0x02000000L
+//DPRX_DPHY_BS_ERROR_COUNT_B
+#define DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_UNCERTAINTY_COUNT__SHIFT 0x0
+#define DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_ERROR_COUNT__SHIFT 0x8
+#define DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_ERROR_COUNT_CLR__SHIFT 0x11
+#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE0_CPBS_ERROR_CLR__SHIFT 0x14
+#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE1_CPBS_ERROR_CLR__SHIFT 0x15
+#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE2_CPBS_ERROR_CLR__SHIFT 0x16
+#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE3_CPBS_ERROR_CLR__SHIFT 0x17
+#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE0_CPBS_ERROR__SHIFT 0x18
+#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE1_CPBS_ERROR__SHIFT 0x1a
+#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE2_CPBS_ERROR__SHIFT 0x1c
+#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE3_CPBS_ERROR__SHIFT 0x1e
+#define DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_UNCERTAINTY_COUNT_MASK 0x000000FFL
+#define DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_ERROR_COUNT_MASK 0x00001F00L
+#define DPRX_DPHY_BS_ERROR_COUNT_B__BS_INTERVAL_ERROR_COUNT_CLR_MASK 0x00020000L
+#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE0_CPBS_ERROR_CLR_MASK 0x00100000L
+#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE1_CPBS_ERROR_CLR_MASK 0x00200000L
+#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE2_CPBS_ERROR_CLR_MASK 0x00400000L
+#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE3_CPBS_ERROR_CLR_MASK 0x00800000L
+#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE0_CPBS_ERROR_MASK 0x03000000L
+#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE1_CPBS_ERROR_MASK 0x0C000000L
+#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE2_CPBS_ERROR_MASK 0x30000000L
+#define DPRX_DPHY_BS_ERROR_COUNT_B__LANE3_CPBS_ERROR_MASK 0xC0000000L
+//DPRX_DPHY_LANESETUP0
+#define DPRX_DPHY_LANESETUP0__LANE_MAP__SHIFT 0x0
+#define DPRX_DPHY_LANESETUP0__LANE_MAP_MASK 0x000000FFL
+//DPRX_DPHY_LANESETUP1
+#define DPRX_DPHY_LANESETUP1__LANEINV__SHIFT 0x0
+#define DPRX_DPHY_LANESETUP1__LANEINV_MASK 0x0000000FL
+//DPRX_DPHY_LFSRADV
+#define DPRX_DPHY_LFSRADV__TWOSYMCORRECTMIDDLE_ENABLE__SHIFT 0x1
+#define DPRX_DPHY_LFSRADV__TWOSYMCORRECTLR_ENABLE__SHIFT 0x2
+#define DPRX_DPHY_LFSRADV__SEVENSYMBOLWINDOW_ENABLE__SHIFT 0x3
+#define DPRX_DPHY_LFSRADV__SUPPRESS_SINGLE_BS_BF_CP_SR_EN__SHIFT 0x4
+#define DPRX_DPHY_LFSRADV__IGNORE_ERROR_FLAG_FOR_BS_INTERVAL__SHIFT 0x5
+#define DPRX_DPHY_LFSRADV__TWOSYMCORRECTMIDDLE_ENABLE_MASK 0x00000002L
+#define DPRX_DPHY_LFSRADV__TWOSYMCORRECTLR_ENABLE_MASK 0x00000004L
+#define DPRX_DPHY_LFSRADV__SEVENSYMBOLWINDOW_ENABLE_MASK 0x00000008L
+#define DPRX_DPHY_LFSRADV__SUPPRESS_SINGLE_BS_BF_CP_SR_EN_MASK 0x00000010L
+#define DPRX_DPHY_LFSRADV__IGNORE_ERROR_FLAG_FOR_BS_INTERVAL_MASK 0x00000020L
+//DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT
+#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE0__SHIFT 0x0
+#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE1__SHIFT 0x8
+#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE2__SHIFT 0x10
+#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE3__SHIFT 0x18
+#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_CLEAR__SHIFT 0x1f
+#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE0_MASK 0x0000007FL
+#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE1_MASK 0x00007F00L
+#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE2_MASK 0x007F0000L
+#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_LANE3_MASK 0x7F000000L
+#define DPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT__SEVENSYMBOLWINDOW_ERROR_DETECT_CLEAR_MASK 0x80000000L
+//DPRX_DPHY_SET_ENABLE
+#define DPRX_DPHY_SET_ENABLE__SET_ENABLE__SHIFT 0x0
+#define DPRX_DPHY_SET_ENABLE__CLOCK_ENABLE__SHIFT 0x8
+#define DPRX_DPHY_SET_ENABLE__CLOCK_ON__SHIFT 0xc
+#define DPRX_DPHY_SET_ENABLE__SET_ENABLE_MASK 0x00000003L
+#define DPRX_DPHY_SET_ENABLE__CLOCK_ENABLE_MASK 0x00000100L
+#define DPRX_DPHY_SET_ENABLE__CLOCK_ON_MASK 0x00001000L
+//DPRX_DPHY_ECF_LSB
+#define DPRX_DPHY_ECF_LSB__ECF_LSB__SHIFT 0x0
+#define DPRX_DPHY_ECF_LSB__ECF_LSB_MASK 0xFFFFFFFFL
+//DPRX_DPHY_ECF_MSB
+#define DPRX_DPHY_ECF_MSB__ECF_MSB__SHIFT 0x0
+#define DPRX_DPHY_ECF_MSB__ECF_MSB_MASK 0xFFFFFFFFL
+//DPRX_DPHY_ENHANCED_FRAME_EN
+#define DPRX_DPHY_ENHANCED_FRAME_EN__ENHANCED_FRAME_EN__SHIFT 0x0
+#define DPRX_DPHY_ENHANCED_FRAME_EN__ENHANCED_FRAME_EN_MASK 0x00000001L
+//DPRX_DPHY_MTP_HEADER_COUNT_FORCE
+#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__MTP_HEADER_COUNT_FORCE__SHIFT 0x0
+#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__USE_TRAILING_BF__SHIFT 0x11
+#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__LINK_LINE_COUNT_FORCE__SHIFT 0x12
+#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__BS_COUNT_FORCE__SHIFT 0x14
+#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__MTP_HEADER_COUNT_FORCE_MASK 0x000003FFL
+#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__USE_TRAILING_BF_MASK 0x00020000L
+#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__LINK_LINE_COUNT_FORCE_MASK 0x000C0000L
+#define DPRX_DPHY_MTP_HEADER_COUNT_FORCE__BS_COUNT_FORCE_MASK 0x3FF00000L
+//DPRX_DPHY_DYNAMIC_DESKEW_DATA
+#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH0_DATA__SHIFT 0x0
+#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH1_DATA__SHIFT 0x8
+#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH2_DATA__SHIFT 0x10
+#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH3_DATA__SHIFT 0x18
+#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH0_DATA_MASK 0x000000FFL
+#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH1_DATA_MASK 0x0000FF00L
+#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH2_DATA_MASK 0x00FF0000L
+#define DPRX_DPHY_DYNAMIC_DESKEW_DATA__MATCH3_DATA_MASK 0xFF000000L
+//DPRX_DPHY_DYNAMIC_DESKEW_CONTROL
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__DESKEW_WAIT_COUNT__SHIFT 0x0
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_KCODE__SHIFT 0x5
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_DATA_DONTCARE__SHIFT 0x6
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_KCODE_DONTCARE__SHIFT 0x7
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_KCODE__SHIFT 0x8
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_DATA_DONTCARE__SHIFT 0x9
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_KCODE_DONTCARE__SHIFT 0xa
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_KCODE__SHIFT 0xb
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_DATA_DONTCARE__SHIFT 0xc
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_KCODE_DONTCARE__SHIFT 0xd
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_KCODE__SHIFT 0xe
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_DATA_DONTCARE__SHIFT 0xf
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_KCODE_DONTCARE__SHIFT 0x10
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__INTERLANE_ALIGN_CHECK_COUNT__SHIFT 0x11
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__FIFO_LEN_IGNORE_DURING_DS_RST__SHIFT 0x1f
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__DESKEW_WAIT_COUNT_MASK 0x0000001FL
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_KCODE_MASK 0x00000020L
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_DATA_DONTCARE_MASK 0x00000040L
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH0_KCODE_DONTCARE_MASK 0x00000080L
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_KCODE_MASK 0x00000100L
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_DATA_DONTCARE_MASK 0x00000200L
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH1_KCODE_DONTCARE_MASK 0x00000400L
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_KCODE_MASK 0x00000800L
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_DATA_DONTCARE_MASK 0x00001000L
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH2_KCODE_DONTCARE_MASK 0x00002000L
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_KCODE_MASK 0x00004000L
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_DATA_DONTCARE_MASK 0x00008000L
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__MATCH3_KCODE_DONTCARE_MASK 0x00010000L
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__INTERLANE_ALIGN_CHECK_COUNT_MASK 0x007E0000L
+#define DPRX_DPHY_DYNAMIC_DESKEW_CONTROL__FIFO_LEN_IGNORE_DURING_DS_RST_MASK 0x80000000L
+//DPRX_DPHY_BYPASS
+#define DPRX_DPHY_BYPASS__LANE0_SDESKEW_BYPASS__SHIFT 0x4
+#define DPRX_DPHY_BYPASS__LANE1_SDESKEW_BYPASS__SHIFT 0x5
+#define DPRX_DPHY_BYPASS__LANE2_SDESKEW_BYPASS__SHIFT 0x6
+#define DPRX_DPHY_BYPASS__LANE3_SDESKEW_BYPASS__SHIFT 0x7
+#define DPRX_DPHY_BYPASS__LANE0_SDESKEW_BYPASS_MASK 0x00000010L
+#define DPRX_DPHY_BYPASS__LANE1_SDESKEW_BYPASS_MASK 0x00000020L
+#define DPRX_DPHY_BYPASS__LANE2_SDESKEW_BYPASS_MASK 0x00000040L
+#define DPRX_DPHY_BYPASS__LANE3_SDESKEW_BYPASS_MASK 0x00000080L
+//DPRX_DPHY_INT_RESET
+#define DPRX_DPHY_INT_RESET__LANE0_ALIGN_RESET__SHIFT 0x0
+#define DPRX_DPHY_INT_RESET__LANE1_ALIGN_RESET__SHIFT 0x1
+#define DPRX_DPHY_INT_RESET__LANE2_ALIGN_RESET__SHIFT 0x2
+#define DPRX_DPHY_INT_RESET__LANE3_ALIGN_RESET__SHIFT 0x3
+#define DPRX_DPHY_INT_RESET__LANE0_SDESKEW_RESET__SHIFT 0x4
+#define DPRX_DPHY_INT_RESET__LANE1_SDESKEW_RESET__SHIFT 0x5
+#define DPRX_DPHY_INT_RESET__LANE2_SDESKEW_RESET__SHIFT 0x6
+#define DPRX_DPHY_INT_RESET__LANE3_SDESKEW_RESET__SHIFT 0x7
+#define DPRX_DPHY_INT_RESET__LANE0_8B10BDEC_RESET__SHIFT 0x8
+#define DPRX_DPHY_INT_RESET__LANE1_8B10BDEC_RESET__SHIFT 0x9
+#define DPRX_DPHY_INT_RESET__LANE2_8B10BDEC_RESET__SHIFT 0xa
+#define DPRX_DPHY_INT_RESET__LANE3_8B10BDEC_RESET__SHIFT 0xb
+#define DPRX_DPHY_INT_RESET__LANE0_LCOUNT_RESET__SHIFT 0x10
+#define DPRX_DPHY_INT_RESET__LANE1_LCOUNT_RESET__SHIFT 0x11
+#define DPRX_DPHY_INT_RESET__LANE2_LCOUNT_RESET__SHIFT 0x12
+#define DPRX_DPHY_INT_RESET__LANE3_LCOUNT_RESET__SHIFT 0x13
+#define DPRX_DPHY_INT_RESET__LANE0_DDESKEW_RESET__SHIFT 0x14
+#define DPRX_DPHY_INT_RESET__LANE1_DDESKEW_RESET__SHIFT 0x15
+#define DPRX_DPHY_INT_RESET__LANE2_DDESKEW_RESET__SHIFT 0x16
+#define DPRX_DPHY_INT_RESET__LANE3_DDESKEW_RESET__SHIFT 0x17
+#define DPRX_DPHY_INT_RESET__INV_RESET__SHIFT 0x18
+#define DPRX_DPHY_INT_RESET__LANEREV_RESET__SHIFT 0x19
+#define DPRX_DPHY_INT_RESET__ENABLE_RESET__SHIFT 0x1a
+#define DPRX_DPHY_INT_RESET__CTL_RESET__SHIFT 0x1b
+#define DPRX_DPHY_INT_RESET__CTL_DS_RESET__SHIFT 0x1c
+#define DPRX_DPHY_INT_RESET__CTL_TRN_RESET__SHIFT 0x1d
+#define DPRX_DPHY_INT_RESET__HEADERPARSE_RESET__SHIFT 0x1e
+#define DPRX_DPHY_INT_RESET__SDOUT_RESET__SHIFT 0x1f
+#define DPRX_DPHY_INT_RESET__LANE0_ALIGN_RESET_MASK 0x00000001L
+#define DPRX_DPHY_INT_RESET__LANE1_ALIGN_RESET_MASK 0x00000002L
+#define DPRX_DPHY_INT_RESET__LANE2_ALIGN_RESET_MASK 0x00000004L
+#define DPRX_DPHY_INT_RESET__LANE3_ALIGN_RESET_MASK 0x00000008L
+#define DPRX_DPHY_INT_RESET__LANE0_SDESKEW_RESET_MASK 0x00000010L
+#define DPRX_DPHY_INT_RESET__LANE1_SDESKEW_RESET_MASK 0x00000020L
+#define DPRX_DPHY_INT_RESET__LANE2_SDESKEW_RESET_MASK 0x00000040L
+#define DPRX_DPHY_INT_RESET__LANE3_SDESKEW_RESET_MASK 0x00000080L
+#define DPRX_DPHY_INT_RESET__LANE0_8B10BDEC_RESET_MASK 0x00000100L
+#define DPRX_DPHY_INT_RESET__LANE1_8B10BDEC_RESET_MASK 0x00000200L
+#define DPRX_DPHY_INT_RESET__LANE2_8B10BDEC_RESET_MASK 0x00000400L
+#define DPRX_DPHY_INT_RESET__LANE3_8B10BDEC_RESET_MASK 0x00000800L
+#define DPRX_DPHY_INT_RESET__LANE0_LCOUNT_RESET_MASK 0x00010000L
+#define DPRX_DPHY_INT_RESET__LANE1_LCOUNT_RESET_MASK 0x00020000L
+#define DPRX_DPHY_INT_RESET__LANE2_LCOUNT_RESET_MASK 0x00040000L
+#define DPRX_DPHY_INT_RESET__LANE3_LCOUNT_RESET_MASK 0x00080000L
+#define DPRX_DPHY_INT_RESET__LANE0_DDESKEW_RESET_MASK 0x00100000L
+#define DPRX_DPHY_INT_RESET__LANE1_DDESKEW_RESET_MASK 0x00200000L
+#define DPRX_DPHY_INT_RESET__LANE2_DDESKEW_RESET_MASK 0x00400000L
+#define DPRX_DPHY_INT_RESET__LANE3_DDESKEW_RESET_MASK 0x00800000L
+#define DPRX_DPHY_INT_RESET__INV_RESET_MASK 0x01000000L
+#define DPRX_DPHY_INT_RESET__LANEREV_RESET_MASK 0x02000000L
+#define DPRX_DPHY_INT_RESET__ENABLE_RESET_MASK 0x04000000L
+#define DPRX_DPHY_INT_RESET__CTL_RESET_MASK 0x08000000L
+#define DPRX_DPHY_INT_RESET__CTL_DS_RESET_MASK 0x10000000L
+#define DPRX_DPHY_INT_RESET__CTL_TRN_RESET_MASK 0x20000000L
+#define DPRX_DPHY_INT_RESET__HEADERPARSE_RESET_MASK 0x40000000L
+#define DPRX_DPHY_INT_RESET__SDOUT_RESET_MASK 0x80000000L
+//DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS
+#define DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_FLAG__SHIFT 0x0
+#define DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_ACK__SHIFT 0x4
+#define DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_MASK__SHIFT 0x8
+#define DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_FLAG_MASK 0x00000001L
+#define DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_ACK_MASK 0x00000010L
+#define DPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS__BS_INTERVAL_ERROR_THRESH_EXCEEDED_MASK_MASK 0x00000100L
+//DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS
+#define DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_FLAG__SHIFT 0x0
+#define DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_ACK__SHIFT 0x4
+#define DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_MASK__SHIFT 0x8
+#define DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_FLAG_MASK 0x00000001L
+#define DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_ACK_MASK 0x00000010L
+#define DPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS__SYMBOL_ERROR_THRESH_EXCEEDED_MASK_MASK 0x00000100L
+//DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS
+#define DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_FLAG__SHIFT 0x0
+#define DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_ACK__SHIFT 0x4
+#define DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_MASK__SHIFT 0x8
+#define DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_FLAG_MASK 0x00000001L
+#define DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_ACK_MASK 0x00000010L
+#define DPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS__DISPARITY_ERROR_THRESH_EXCEEDED_MASK_MASK 0x00000100L
+//DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS
+#define DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_FLAG__SHIFT 0x0
+#define DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_ACK__SHIFT 0x4
+#define DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_MASK__SHIFT 0x8
+#define DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_FLAG_MASK 0x00000001L
+#define DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_ACK_MASK 0x00000010L
+#define DPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS__TEST_PATTERN_ERROR_THRESH_EXCEEDED_MASK_MASK 0x00000100L
+//DPRX_DPHY_DETECT_SR_LOCK_STATUS
+#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_FLAG__SHIFT 0x0
+#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_ACK__SHIFT 0x4
+#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_MASK__SHIFT 0x8
+#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_TYPE__SHIFT 0xc
+#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_FLAG_MASK 0x00000001L
+#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_ACK_MASK 0x00000010L
+#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_MASK_MASK 0x00000100L
+#define DPRX_DPHY_DETECT_SR_LOCK_STATUS__DETECT_SR_LOCK_STATUS_TYPE_MASK 0x00001000L
+//DPRX_DPHY_LOSS_OF_ALIGN_STATUS
+#define DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_FLAG__SHIFT 0x0
+#define DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_ACK__SHIFT 0x4
+#define DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_MASK__SHIFT 0x8
+#define DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_FLAG_MASK 0x00000001L
+#define DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_ACK_MASK 0x00000010L
+#define DPRX_DPHY_LOSS_OF_ALIGN_STATUS__LOSS_OF_ALIGN_MASK_MASK 0x00000100L
+//DPRX_DPHY_LOSS_OF_DESKEW_STATUS
+#define DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_FLAG__SHIFT 0x0
+#define DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_ACK__SHIFT 0x4
+#define DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_MASK__SHIFT 0x8
+#define DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_FLAG_MASK 0x00000001L
+#define DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_ACK_MASK 0x00000010L
+#define DPRX_DPHY_LOSS_OF_DESKEW_STATUS__LOSS_OF_DESKEW_MASK_MASK 0x00000100L
+//DPRX_DPHY_EXCESSIVE_ERROR_STATUS
+#define DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_FLAG__SHIFT 0x0
+#define DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_ACK__SHIFT 0x4
+#define DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_MASK__SHIFT 0x8
+#define DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_FLAG_MASK 0x00000001L
+#define DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_ACK_MASK 0x00000010L
+#define DPRX_DPHY_EXCESSIVE_ERROR_STATUS__EXCESSIVE_ERROR_MASK_MASK 0x00000100L
+//DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS
+#define DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_FLAG__SHIFT 0x0
+#define DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_ACK__SHIFT 0x4
+#define DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_MASK__SHIFT 0x8
+#define DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_FLAG_MASK 0x00000001L
+#define DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_ACK_MASK 0x00000010L
+#define DPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS__DESKEW_FIFO_OVERFLOW_MASK_MASK 0x00000100L
+//DPRX_DPHY_SPARE
+#define DPRX_DPHY_SPARE__DPHY_SPARE__SHIFT 0x0
+#define DPRX_DPHY_SPARE__DPHY_SPARE_MASK 0xFFFFFFFFL
+//DCRX_GATE_DISABLE_CNTL
+#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_CWB0_SD0_GATE_DISABLE__SHIFT 0x0
+#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_CWB1_SD1_GATE_DISABLE__SHIFT 0x1
+#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_AUX_GATE_DISABLE__SHIFT 0x2
+#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_R_GATE_DISABLE__SHIFT 0x3
+#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_SD0_GATE_DISABLE__SHIFT 0x8
+#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_SD1_GATE_DISABLE__SHIFT 0x9
+#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_DPHY_GATE_DISABLE__SHIFT 0xa
+#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_P_GATE_DISABLE__SHIFT 0xc
+#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_CWB0_SD0_GATE_DISABLE_MASK 0x00000001L
+#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_CWB1_SD1_GATE_DISABLE_MASK 0x00000002L
+#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_AUX_GATE_DISABLE_MASK 0x00000004L
+#define DCRX_GATE_DISABLE_CNTL__DCRX_DISPCLK_R_GATE_DISABLE_MASK 0x00000008L
+#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_SD0_GATE_DISABLE_MASK 0x00000100L
+#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_SD1_GATE_DISABLE_MASK 0x00000200L
+#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_DPHY_GATE_DISABLE_MASK 0x00000400L
+#define DCRX_GATE_DISABLE_CNTL__DCRX_SYMCLK_RX_P_GATE_DISABLE_MASK 0x00001000L
+//DCRX_SOFT_RESET
+#define DCRX_SOFT_RESET__DCRX_DISPCLK_CWB0_SD0_SOFT_RESET__SHIFT 0x0
+#define DCRX_SOFT_RESET__DCRX_DISPCLK_CWB1_SD1_SOFT_RESET__SHIFT 0x1
+#define DCRX_SOFT_RESET__DCRX_DISPCLK_AUX_SOFT_RESET__SHIFT 0x2
+#define DCRX_SOFT_RESET__DCRX_DISPCLK_P_SOFT_RESET__SHIFT 0x4
+#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_SD0_SOFT_RESET__SHIFT 0x8
+#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_SD1_SOFT_RESET__SHIFT 0x9
+#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_DPHY_SOFT_RESET__SHIFT 0xa
+#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_P_SOFT_RESET__SHIFT 0xc
+#define DCRX_SOFT_RESET__DCRX_REFCLK_SOFT_RESET__SHIFT 0x10
+#define DCRX_SOFT_RESET__DCRX_SCLK_SOFT_RESET__SHIFT 0x11
+#define DCRX_SOFT_RESET__DCRX_DISPCLK_CWB0_SD0_SOFT_RESET_MASK 0x00000001L
+#define DCRX_SOFT_RESET__DCRX_DISPCLK_CWB1_SD1_SOFT_RESET_MASK 0x00000002L
+#define DCRX_SOFT_RESET__DCRX_DISPCLK_AUX_SOFT_RESET_MASK 0x00000004L
+#define DCRX_SOFT_RESET__DCRX_DISPCLK_P_SOFT_RESET_MASK 0x00000010L
+#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_SD0_SOFT_RESET_MASK 0x00000100L
+#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_SD1_SOFT_RESET_MASK 0x00000200L
+#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_DPHY_SOFT_RESET_MASK 0x00000400L
+#define DCRX_SOFT_RESET__DCRX_SYMCLK_RX_P_SOFT_RESET_MASK 0x00001000L
+#define DCRX_SOFT_RESET__DCRX_REFCLK_SOFT_RESET_MASK 0x00010000L
+#define DCRX_SOFT_RESET__DCRX_SCLK_SOFT_RESET_MASK 0x00020000L
+//DCRX_LIGHT_SLEEP_CNTL
+#define DCRX_LIGHT_SLEEP_CNTL__DCRX_AUX_LIGHT_SLEEP_DIS__SHIFT 0x0
+#define DCRX_LIGHT_SLEEP_CNTL__DCRX_DPRX_LIGHT_SLEEP_DIS__SHIFT 0x8
+#define DCRX_LIGHT_SLEEP_CNTL__DCRX_AUX_LIGHT_SLEEP_DIS_MASK 0x00000001L
+#define DCRX_LIGHT_SLEEP_CNTL__DCRX_DPRX_LIGHT_SLEEP_DIS_MASK 0x00000100L
+//DCRX_DISPCLK_GATE_CNTL
+#define DCRX_DISPCLK_GATE_CNTL__DCRX_DISPCLK_TURN_ON_DELAY__SHIFT 0x0
+#define DCRX_DISPCLK_GATE_CNTL__DCRX_DISPCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define DCRX_DISPCLK_GATE_CNTL__DCRX_DISPCLK_TURN_ON_DELAY_MASK 0x0000000FL
+#define DCRX_DISPCLK_GATE_CNTL__DCRX_DISPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
+//DCRX_CLK_CNTL
+#define DCRX_CLK_CNTL__DCRX_SYMCLK_RX_P_ENABLE__SHIFT 0x2
+#define DCRX_CLK_CNTL__DCRX_SYMCLK_RX_P_ENABLE_MASK 0x00000004L
+//DCRX_TEST_CLK_CNTL
+#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICA_SEL__SHIFT 0x0
+#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICA_INV__SHIFT 0x7
+#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICB_SEL__SHIFT 0x8
+#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICB_INV__SHIFT 0xf
+#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICA_SEL_MASK 0x0000001FL
+#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICA_INV_MASK 0x00000080L
+#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICB_SEL_MASK 0x00001F00L
+#define DCRX_TEST_CLK_CNTL__DCRX_TEST_CLK_GENERICB_INV_MASK 0x00008000L
+//DCRX_PHY_MACRO_CNTL_RESERVED0
+#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED1
+#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED2
+#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED3
+#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED4
+#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED5
+#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED6
+#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED7
+#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED8
+#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED9
+#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED10
+#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED11
+#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED12
+#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED13
+#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED14
+#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED15
+#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED16
+#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED17
+#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED18
+#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED19
+#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED20
+#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED21
+#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED22
+#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED23
+#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED24
+#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED25
+#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED26
+#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED27
+#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED28
+#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED29
+#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED30
+#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED31
+#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED32
+#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED33
+#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED34
+#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED35
+#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED36
+#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED37
+#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED38
+#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED39
+#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED40
+#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED41
+#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED42
+#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED43
+#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED44
+#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED45
+#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED46
+#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED47
+#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED48
+#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED49
+#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED50
+#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED51
+#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED52
+#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED53
+#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED54
+#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED55
+#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED56
+#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED57
+#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED58
+#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED59
+#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED60
+#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED61
+#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED62
+#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED63
+#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED64
+#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED65
+#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED66
+#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED67
+#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED68
+#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED69
+#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED70
+#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED71
+#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED72
+#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED73
+#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED74
+#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED75
+#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED76
+#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED77
+#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED78
+#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED79
+#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED80
+#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED81
+#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED82
+#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED83
+#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED84
+#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED85
+#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED86
+#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED87
+#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED88
+#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED89
+#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED90
+#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED91
+#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED92
+#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED93
+#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED94
+#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED95
+#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED96
+#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED97
+#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED98
+#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED99
+#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED100
+#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED101
+#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED102
+#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED103
+#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED104
+#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED105
+#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED106
+#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED107
+#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED108
+#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED109
+#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED110
+#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED111
+#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED112
+#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED113
+#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED114
+#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED115
+#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED116
+#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED117
+#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED118
+#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED119
+#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED120
+#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED121
+#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED122
+#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED123
+#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED124
+#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED125
+#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED126
+#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED127
+#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED128
+#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED129
+#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED130
+#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED131
+#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED132
+#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED133
+#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED134
+#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED135
+#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED136
+#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED137
+#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED138
+#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED139
+#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED140
+#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED141
+#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED142
+#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED143
+#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED144
+#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED145
+#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED146
+#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED147
+#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED148
+#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED149
+#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED150
+#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED151
+#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED152
+#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED153
+#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED154
+#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED155
+#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED156
+#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED157
+#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED158
+#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED159
+#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED160
+#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED161
+#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED162
+#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED163
+#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED164
+#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED165
+#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED166
+#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED167
+#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED168
+#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED169
+#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED170
+#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED171
+#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED172
+#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED173
+#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED174
+#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED175
+#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED176
+#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED177
+#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED178
+#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED179
+#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED180
+#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED181
+#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED182
+#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED183
+#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED184
+#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED185
+#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED186
+#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED187
+#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED188
+#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED189
+#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED190
+#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED191
+#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED192
+#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED193
+#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED194
+#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED195
+#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED196
+#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED197
+#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED198
+#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED199
+#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED200
+#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED201
+#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED202
+#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED203
+#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED204
+#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED205
+#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED206
+#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED207
+#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED208
+#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED209
+#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED210
+#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED211
+#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED212
+#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED213
+#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED214
+#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED215
+#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED216
+#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED217
+#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED218
+#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED219
+#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED220
+#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED221
+#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED222
+#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED223
+#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED224
+#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED225
+#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED226
+#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED227
+#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED228
+#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED229
+#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED230
+#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED231
+#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED232
+#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED233
+#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED234
+#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED235
+#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED236
+#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED237
+#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED238
+#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED239
+#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED240
+#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED241
+#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED242
+#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED243
+#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED244
+#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED245
+#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED246
+#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED247
+#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED248
+#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED249
+#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED250
+#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED251
+#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED252
+#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED253
+#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED254
+#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED255
+#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED256
+#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED257
+#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED258
+#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED259
+#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED260
+#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED261
+#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED262
+#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED263
+#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED264
+#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED265
+#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED266
+#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED267
+#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED268
+#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED269
+#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED270
+#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED271
+#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED272
+#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED273
+#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED274
+#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED275
+#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED276
+#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED277
+#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED278
+#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED279
+#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED280
+#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED281
+#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED282
+#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED283
+#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED284
+#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED285
+#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED286
+#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED287
+#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED288
+#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED289
+#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED290
+#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED291
+#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED292
+#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED293
+#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED294
+#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED295
+#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED296
+#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED297
+#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED298
+#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED299
+#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED300
+#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED301
+#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED302
+#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED303
+#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED304
+#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED305
+#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED306
+#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED307
+#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED308
+#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED309
+#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED310
+#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED311
+#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED312
+#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED313
+#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED314
+#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED315
+#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED316
+#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED317
+#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED318
+#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED319
+#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED320
+#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED321
+#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED322
+#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED323
+#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED324
+#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED325
+#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED326
+#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED327
+#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED328
+#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED329
+#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED330
+#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED331
+#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED332
+#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED333
+#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED334
+#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED335
+#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED336
+#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED337
+#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED338
+#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED339
+#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED340
+#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED341
+#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED342
+#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED343
+#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED344
+#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED345
+#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED346
+#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED347
+#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED348
+#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED349
+#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED350
+#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED351
+#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED352
+#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED353
+#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED354
+#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED355
+#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED356
+#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED357
+#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED358
+#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED359
+#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED360
+#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED361
+#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED362
+#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED363
+#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED364
+#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED365
+#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED366
+#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED367
+#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED368
+#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED369
+#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED370
+#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED371
+#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED372
+#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED373
+#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED374
+#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED375
+#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED376
+#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED377
+#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED378
+#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCRX_PHY_MACRO_CNTL_RESERVED379
+#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//I2S0_CNTL
+#define I2S0_CNTL__I2S0_WORD_SIZE__SHIFT 0x0
+#define I2S0_CNTL__I2S0_SAMPLE_ALIGNMENT__SHIFT 0x4
+#define I2S0_CNTL__I2S0_SAMPLE_BIT_ORDER__SHIFT 0x8
+#define I2S0_CNTL__I2S0_LRCLK_POLARITY__SHIFT 0xc
+#define I2S0_CNTL__I2S0_WORD_ALIGNMENT__SHIFT 0x10
+#define I2S0_CNTL__I2S0_ENABLE__SHIFT 0x1a
+#define I2S0_CNTL__I2S0_FIFO_START_ADDR__SHIFT 0x1e
+#define I2S0_CNTL__I2S0_WORD_SIZE_MASK 0x00000001L
+#define I2S0_CNTL__I2S0_SAMPLE_ALIGNMENT_MASK 0x00000010L
+#define I2S0_CNTL__I2S0_SAMPLE_BIT_ORDER_MASK 0x00000100L
+#define I2S0_CNTL__I2S0_LRCLK_POLARITY_MASK 0x00001000L
+#define I2S0_CNTL__I2S0_WORD_ALIGNMENT_MASK 0x00010000L
+#define I2S0_CNTL__I2S0_ENABLE_MASK 0x04000000L
+#define I2S0_CNTL__I2S0_FIFO_START_ADDR_MASK 0x40000000L
+//SPDIF0_CNTL
+#define SPDIF0_CNTL__SPDIF0_EN__SHIFT 0x0
+#define SPDIF0_CNTL__SPDIF0_FIFO_START_ADDR__SHIFT 0x4
+#define SPDIF0_CNTL__SPDIF0_EN_MASK 0x00000001L
+#define SPDIF0_CNTL__SPDIF0_FIFO_START_ADDR_MASK 0x00000010L
+//I2S1_CNTL
+#define I2S1_CNTL__I2S1_WORD_SIZE__SHIFT 0x0
+#define I2S1_CNTL__I2S1_SAMPLE_ALIGNMENT__SHIFT 0x4
+#define I2S1_CNTL__I2S1_SAMPLE_BIT_ORDER__SHIFT 0x8
+#define I2S1_CNTL__I2S1_LRCLK_POLARITY__SHIFT 0xc
+#define I2S1_CNTL__I2S1_WORD_ALIGNMENT__SHIFT 0x10
+#define I2S1_CNTL__I2S1_ENABLE__SHIFT 0x1a
+#define I2S1_CNTL__I2S1_FIFO_START_ADDR__SHIFT 0x1e
+#define I2S1_CNTL__I2S1_WORD_SIZE_MASK 0x00000001L
+#define I2S1_CNTL__I2S1_SAMPLE_ALIGNMENT_MASK 0x00000010L
+#define I2S1_CNTL__I2S1_SAMPLE_BIT_ORDER_MASK 0x00000100L
+#define I2S1_CNTL__I2S1_LRCLK_POLARITY_MASK 0x00001000L
+#define I2S1_CNTL__I2S1_WORD_ALIGNMENT_MASK 0x00010000L
+#define I2S1_CNTL__I2S1_ENABLE_MASK 0x04000000L
+#define I2S1_CNTL__I2S1_FIFO_START_ADDR_MASK 0x40000000L
+//SPDIF1_CNTL
+#define SPDIF1_CNTL__SPDIF1_EN__SHIFT 0x0
+#define SPDIF1_CNTL__SPDIF1_FIFO_START_ADDR__SHIFT 0x4
+#define SPDIF1_CNTL__SPDIF1_INVERT_EN__SHIFT 0x8
+#define SPDIF1_CNTL__SPDIF1_EN_MASK 0x00000001L
+#define SPDIF1_CNTL__SPDIF1_FIFO_START_ADDR_MASK 0x00000010L
+#define SPDIF1_CNTL__SPDIF1_INVERT_EN_MASK 0x00000100L
+//I2S0_STATUS
+#define I2S0_STATUS__STREAM0_AUDIO_ENABLE__SHIFT 0x0
+#define I2S0_STATUS__STREAM0_IDLE__SHIFT 0x1
+#define I2S0_STATUS__I2S0_DATA_RDY__SHIFT 0x2
+#define I2S0_STATUS__I2S0_SAMPLE_RATE__SHIFT 0x3
+#define I2S0_STATUS__STREAM0_AUDIO_ENABLE_MASK 0x00000001L
+#define I2S0_STATUS__STREAM0_IDLE_MASK 0x00000002L
+#define I2S0_STATUS__I2S0_DATA_RDY_MASK 0x00000004L
+#define I2S0_STATUS__I2S0_SAMPLE_RATE_MASK 0x00000038L
+//I2S1_STATUS
+#define I2S1_STATUS__STREAM1_AUDIO_ENABLE__SHIFT 0x0
+#define I2S1_STATUS__STREAM1_IDLE__SHIFT 0x1
+#define I2S1_STATUS__I2S1_DATA_RDY__SHIFT 0x2
+#define I2S1_STATUS__I2S1_SAMPLE_RATE__SHIFT 0x3
+#define I2S1_STATUS__STREAM1_AUDIO_ENABLE_MASK 0x00000001L
+#define I2S1_STATUS__STREAM1_IDLE_MASK 0x00000002L
+#define I2S1_STATUS__I2S1_DATA_RDY_MASK 0x00000004L
+#define I2S1_STATUS__I2S1_SAMPLE_RATE_MASK 0x00000038L
+//I2S0_CRC_TEST_CNTL
+#define I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_EN__SHIFT 0x0
+#define I2S0_CRC_TEST_CNTL__I2S0_CRC_SOFT_RESET__SHIFT 0x1
+#define I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_CONT_EN__SHIFT 0x4
+#define I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_NUMBER_OF_SAMPLES__SHIFT 0x8
+#define I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_EN_MASK 0x00000001L
+#define I2S0_CRC_TEST_CNTL__I2S0_CRC_SOFT_RESET_MASK 0x00000002L
+#define I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_CONT_EN_MASK 0x00000010L
+#define I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_NUMBER_OF_SAMPLES_MASK 0xFFFFFF00L
+//I2S0_CRC_TEST_DATA_01
+#define I2S0_CRC_TEST_DATA_01__I2S0_CRC_TEST_DATA0__SHIFT 0x0
+#define I2S0_CRC_TEST_DATA_01__I2S0_CRC_TEST_DATA1__SHIFT 0x10
+#define I2S0_CRC_TEST_DATA_01__I2S0_CRC_TEST_DATA0_MASK 0x0000FFFFL
+#define I2S0_CRC_TEST_DATA_01__I2S0_CRC_TEST_DATA1_MASK 0xFFFF0000L
+//I2S0_CRC_TEST_DATA_23
+#define I2S0_CRC_TEST_DATA_23__I2S0_CRC_TEST_DATA2__SHIFT 0x0
+#define I2S0_CRC_TEST_DATA_23__I2S0_CRC_TEST_DATA3__SHIFT 0x10
+#define I2S0_CRC_TEST_DATA_23__I2S0_CRC_TEST_DATA2_MASK 0x0000FFFFL
+#define I2S0_CRC_TEST_DATA_23__I2S0_CRC_TEST_DATA3_MASK 0xFFFF0000L
+//I2S1_CRC_TEST_CNTL
+#define I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_EN__SHIFT 0x0
+#define I2S1_CRC_TEST_CNTL__I2S1_CRC_SOFT_RESET__SHIFT 0x1
+#define I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_CONT_EN__SHIFT 0x4
+#define I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_NUMBER_OF_SAMPLES__SHIFT 0x8
+#define I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_EN_MASK 0x00000001L
+#define I2S1_CRC_TEST_CNTL__I2S1_CRC_SOFT_RESET_MASK 0x00000002L
+#define I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_CONT_EN_MASK 0x00000010L
+#define I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_NUMBER_OF_SAMPLES_MASK 0xFFFFFF00L
+//I2S1_CRC_TEST_DATA_0
+#define I2S1_CRC_TEST_DATA_0__I2S1_CRC_TEST_DATA0__SHIFT 0x0
+#define I2S1_CRC_TEST_DATA_0__I2S1_CRC_TEST_DATA0_MASK 0x0000FFFFL
+//SPDIF0_CRC_TEST_CNTL
+#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_TEST_EN__SHIFT 0x0
+#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_SOFT_RESET__SHIFT 0x1
+#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_TEST_CONT_EN__SHIFT 0x4
+#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_TEST_NUMBER_OF_SAMPLES__SHIFT 0x8
+#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_TEST_EN_MASK 0x00000001L
+#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_SOFT_RESET_MASK 0x00000002L
+#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_TEST_CONT_EN_MASK 0x00000010L
+#define SPDIF0_CRC_TEST_CNTL__SPDIF0_CRC_TEST_NUMBER_OF_SAMPLES_MASK 0xFFFFFF00L
+//SPDIF0_CRC_TEST_DATA_0
+#define SPDIF0_CRC_TEST_DATA_0__SPDIF0_CRC_TEST_DATA0__SHIFT 0x0
+#define SPDIF0_CRC_TEST_DATA_0__SPDIF0_CRC_TEST_DATA0_MASK 0x0000FFFFL
+//SPDIF1_CRC_TEST_CNTL
+#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_TEST_EN__SHIFT 0x0
+#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_SOFT_RESET__SHIFT 0x1
+#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_TEST_CONT_EN__SHIFT 0x4
+#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_TEST_NUMBER_OF_SAMPLES__SHIFT 0x8
+#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_TEST_EN_MASK 0x00000001L
+#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_SOFT_RESET_MASK 0x00000002L
+#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_TEST_CONT_EN_MASK 0x00000010L
+#define SPDIF1_CRC_TEST_CNTL__SPDIF1_CRC_TEST_NUMBER_OF_SAMPLES_MASK 0xFFFFFF00L
+//SPDIF1_CRC_TEST_DATA
+#define SPDIF1_CRC_TEST_DATA__SPDIF1_CRC_TEST_DATA__SHIFT 0x0
+#define SPDIF1_CRC_TEST_DATA__SPDIF1_CRC_TEST_DATA_MASK 0x0000FFFFL
+//CRC_I2S_CONT_REPEAT_NUM
+#define CRC_I2S_CONT_REPEAT_NUM__I2S0_CRC_CONT_REPEAT_NUM__SHIFT 0x0
+#define CRC_I2S_CONT_REPEAT_NUM__I2S1_CRC_CONT_REPEAT_NUM__SHIFT 0x10
+#define CRC_I2S_CONT_REPEAT_NUM__I2S0_CRC_CONT_REPEAT_NUM_MASK 0x0000FFFFL
+#define CRC_I2S_CONT_REPEAT_NUM__I2S1_CRC_CONT_REPEAT_NUM_MASK 0xFFFF0000L
+//CRC_SPDIF_CONT_REPEAT_NUM
+#define CRC_SPDIF_CONT_REPEAT_NUM__SPDIF0_CRC_CONT_REPEAT_NUM__SHIFT 0x0
+#define CRC_SPDIF_CONT_REPEAT_NUM__SPDIF1_CRC_CONT_REPEAT_NUM__SHIFT 0x10
+#define CRC_SPDIF_CONT_REPEAT_NUM__SPDIF0_CRC_CONT_REPEAT_NUM_MASK 0x0000FFFFL
+#define CRC_SPDIF_CONT_REPEAT_NUM__SPDIF1_CRC_CONT_REPEAT_NUM_MASK 0xFFFF0000L
+//ZCAL_MACRO_CNTL_RESERVED0
+#define ZCAL_MACRO_CNTL_RESERVED0__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define ZCAL_MACRO_CNTL_RESERVED0__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//ZCAL_MACRO_CNTL_RESERVED1
+#define ZCAL_MACRO_CNTL_RESERVED1__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define ZCAL_MACRO_CNTL_RESERVED1__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//ZCAL_MACRO_CNTL_RESERVED2
+#define ZCAL_MACRO_CNTL_RESERVED2__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define ZCAL_MACRO_CNTL_RESERVED2__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//ZCAL_MACRO_CNTL_RESERVED3
+#define ZCAL_MACRO_CNTL_RESERVED3__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define ZCAL_MACRO_CNTL_RESERVED3__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//ZCAL_MACRO_CNTL_RESERVED4
+#define ZCAL_MACRO_CNTL_RESERVED4__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define ZCAL_MACRO_CNTL_RESERVED4__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0stream0_dispdec
+//AZF0STREAM0_AZALIA_STREAM_INDEX
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM0_AZALIA_STREAM_DATA
+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0stream1_dispdec
+//AZF0STREAM1_AZALIA_STREAM_INDEX
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM1_AZALIA_STREAM_DATA
+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0stream2_dispdec
+//AZF0STREAM2_AZALIA_STREAM_INDEX
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM2_AZALIA_STREAM_DATA
+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0stream3_dispdec
+//AZF0STREAM3_AZALIA_STREAM_INDEX
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM3_AZALIA_STREAM_DATA
+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0stream4_dispdec
+//AZF0STREAM4_AZALIA_STREAM_INDEX
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM4_AZALIA_STREAM_DATA
+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0stream5_dispdec
+//AZF0STREAM5_AZALIA_STREAM_INDEX
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM5_AZALIA_STREAM_DATA
+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0stream6_dispdec
+//AZF0STREAM6_AZALIA_STREAM_INDEX
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM6_AZALIA_STREAM_DATA
+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0stream7_dispdec
+//AZF0STREAM7_AZALIA_STREAM_INDEX
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM7_AZALIA_STREAM_DATA
+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0endpoint0_dispdec
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0endpoint1_dispdec
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0endpoint2_dispdec
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0endpoint3_dispdec
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0endpoint4_dispdec
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0endpoint5_dispdec
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0endpoint6_dispdec
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0endpoint7_dispdec
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0stream8_dispdec
+//AZF0STREAM8_AZALIA_STREAM_INDEX
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM8_AZALIA_STREAM_DATA
+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0stream9_dispdec
+//AZF0STREAM9_AZALIA_STREAM_INDEX
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM9_AZALIA_STREAM_DATA
+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0stream10_dispdec
+//AZF0STREAM10_AZALIA_STREAM_INDEX
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM10_AZALIA_STREAM_DATA
+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0stream11_dispdec
+//AZF0STREAM11_AZALIA_STREAM_INDEX
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM11_AZALIA_STREAM_DATA
+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0stream12_dispdec
+//AZF0STREAM12_AZALIA_STREAM_INDEX
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM12_AZALIA_STREAM_DATA
+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0stream13_dispdec
+//AZF0STREAM13_AZALIA_STREAM_INDEX
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM13_AZALIA_STREAM_DATA
+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0stream14_dispdec
+//AZF0STREAM14_AZALIA_STREAM_INDEX
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM14_AZALIA_STREAM_DATA
+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0stream15_dispdec
+//AZF0STREAM15_AZALIA_STREAM_INDEX
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM15_AZALIA_STREAM_DATA
+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0inputendpoint0_dispdec
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0inputendpoint1_dispdec
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0inputendpoint2_dispdec
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0inputendpoint3_dispdec
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0inputendpoint4_dispdec
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0inputendpoint5_dispdec
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0inputendpoint6_dispdec
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azf0inputendpoint7_dispdec
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcp0_dispdec
+//DCP0_GRPH_ENABLE
+#define DCP0_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
+#define DCP0_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1
+#define DCP0_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
+#define DCP0_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x00000002L
+//DCP0_GRPH_CONTROL
+#define DCP0_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
+#define DCP0_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT 0x2
+#define DCP0_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
+#define DCP0_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT 0x6
+#define DCP0_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
+#define DCP0_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0xc
+#define DCP0_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+#define DCP0_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+#define DCP0_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT 0x12
+#define DCP0_GRPH_CONTROL__GRPH_SW_MODE__SHIFT 0x14
+#define DCP0_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT 0x1c
+#define DCP0_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
+#define DCP0_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
+#define DCP0_GRPH_CONTROL__GRPH_SE_ENABLE_MASK 0x00000004L
+#define DCP0_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
+#define DCP0_GRPH_CONTROL__GRPH_DIM_TYPE_MASK 0x000000C0L
+#define DCP0_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
+#define DCP0_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x00007000L
+#define DCP0_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
+#define DCP0_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
+#define DCP0_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK 0x000C0000L
+#define DCP0_GRPH_CONTROL__GRPH_SW_MODE_MASK 0x01F00000L
+#define DCP0_GRPH_CONTROL__GRPH_NUM_PIPES_MASK 0x70000000L
+#define DCP0_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
+//DCP0_GRPH_LUT_10BIT_BYPASS
+#define DCP0_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
+#define DCP0_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
+#define DCP0_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L
+#define DCP0_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L
+//DCP0_GRPH_SWAP_CNTL
+#define DCP0_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
+#define DCP0_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
+#define DCP0_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
+#define DCP0_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
+#define DCP0_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
+#define DCP0_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
+#define DCP0_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
+#define DCP0_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
+#define DCP0_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
+#define DCP0_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000C00L
+//DCP0_GRPH_PRIMARY_SURFACE_ADDRESS
+#define DCP0_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
+#define DCP0_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP0_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L
+#define DCP0_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP0_GRPH_SECONDARY_SURFACE_ADDRESS
+#define DCP0_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
+#define DCP0_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP0_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L
+#define DCP0_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP0_GRPH_PITCH
+#define DCP0_GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
+#define DCP0_GRPH_PITCH__GRPH_PITCH_MASK 0x00007FFFL
+//DCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+#define DCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+#define DCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP0_GRPH_SURFACE_OFFSET_X
+#define DCP0_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
+#define DCP0_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003FFFL
+//DCP0_GRPH_SURFACE_OFFSET_Y
+#define DCP0_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
+#define DCP0_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003FFFL
+//DCP0_GRPH_X_START
+#define DCP0_GRPH_X_START__GRPH_X_START__SHIFT 0x0
+#define DCP0_GRPH_X_START__GRPH_X_START_MASK 0x00003FFFL
+//DCP0_GRPH_Y_START
+#define DCP0_GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
+#define DCP0_GRPH_Y_START__GRPH_Y_START_MASK 0x00003FFFL
+//DCP0_GRPH_X_END
+#define DCP0_GRPH_X_END__GRPH_X_END__SHIFT 0x0
+#define DCP0_GRPH_X_END__GRPH_X_END_MASK 0x00007FFFL
+//DCP0_GRPH_Y_END
+#define DCP0_GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
+#define DCP0_GRPH_Y_END__GRPH_Y_END_MASK 0x00007FFFL
+//DCP0_INPUT_GAMMA_CONTROL
+#define DCP0_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
+#define DCP0_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000001L
+//DCP0_GRPH_UPDATE
+#define DCP0_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
+#define DCP0_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
+#define DCP0_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
+#define DCP0_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
+#define DCP0_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT 0x8
+#define DCP0_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT 0x9
+#define DCP0_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT 0xa
+#define DCP0_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
+#define DCP0_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
+#define DCP0_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define DCP0_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
+#define DCP0_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
+#define DCP0_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
+#define DCP0_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
+#define DCP0_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
+#define DCP0_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK 0x00000100L
+#define DCP0_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK 0x00000200L
+#define DCP0_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK 0x00000400L
+#define DCP0_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
+#define DCP0_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
+#define DCP0_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+#define DCP0_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
+//DCP0_GRPH_FLIP_CONTROL
+#define DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
+#define DCP0_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
+#define DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4
+#define DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5
+#define DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L
+#define DCP0_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x00000002L
+#define DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x00000010L
+#define DCP0_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000020L
+//DCP0_GRPH_SURFACE_ADDRESS_INUSE
+#define DCP0_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
+#define DCP0_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xFFFFFF00L
+//DCP0_GRPH_DFQ_CONTROL
+#define DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
+#define DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
+#define DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
+#define DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L
+#define DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L
+#define DCP0_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L
+//DCP0_GRPH_DFQ_STATUS
+#define DCP0_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
+#define DCP0_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
+#define DCP0_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
+#define DCP0_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
+#define DCP0_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000FL
+#define DCP0_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000F0L
+#define DCP0_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L
+#define DCP0_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L
+//DCP0_GRPH_INTERRUPT_STATUS
+#define DCP0_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
+#define DCP0_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
+#define DCP0_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
+#define DCP0_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
+//DCP0_GRPH_INTERRUPT_CONTROL
+#define DCP0_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
+#define DCP0_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
+#define DCP0_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
+#define DCP0_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
+//DCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE
+#define DCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
+#define DCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000FFL
+//DCP0_GRPH_COMPRESS_SURFACE_ADDRESS
+#define DCP0_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP0_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP0_GRPH_COMPRESS_PITCH
+#define DCP0_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
+#define DCP0_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001FFC0L
+//DCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH
+#define DCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
+#define DCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0
+#define DCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0x000000FFL
+//DCP0_PRESCALE_GRPH_CONTROL
+#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
+#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
+#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
+#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
+#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
+#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L
+#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L
+#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L
+#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L
+#define DCP0_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L
+//DCP0_PRESCALE_VALUES_GRPH_R
+#define DCP0_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
+#define DCP0_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
+#define DCP0_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000FFFFL
+#define DCP0_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xFFFF0000L
+//DCP0_PRESCALE_VALUES_GRPH_G
+#define DCP0_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
+#define DCP0_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
+#define DCP0_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000FFFFL
+#define DCP0_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xFFFF0000L
+//DCP0_PRESCALE_VALUES_GRPH_B
+#define DCP0_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
+#define DCP0_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
+#define DCP0_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000FFFFL
+#define DCP0_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xFFFF0000L
+//DCP0_INPUT_CSC_CONTROL
+#define DCP0_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
+#define DCP0_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L
+//DCP0_INPUT_CSC_C11_C12
+#define DCP0_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
+#define DCP0_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
+#define DCP0_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000FFFFL
+#define DCP0_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xFFFF0000L
+//DCP0_INPUT_CSC_C13_C14
+#define DCP0_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
+#define DCP0_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
+#define DCP0_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000FFFFL
+#define DCP0_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xFFFF0000L
+//DCP0_INPUT_CSC_C21_C22
+#define DCP0_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
+#define DCP0_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
+#define DCP0_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000FFFFL
+#define DCP0_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xFFFF0000L
+//DCP0_INPUT_CSC_C23_C24
+#define DCP0_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
+#define DCP0_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
+#define DCP0_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000FFFFL
+#define DCP0_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xFFFF0000L
+//DCP0_INPUT_CSC_C31_C32
+#define DCP0_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
+#define DCP0_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
+#define DCP0_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000FFFFL
+#define DCP0_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xFFFF0000L
+//DCP0_INPUT_CSC_C33_C34
+#define DCP0_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
+#define DCP0_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
+#define DCP0_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000FFFFL
+#define DCP0_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xFFFF0000L
+//DCP0_OUTPUT_CSC_CONTROL
+#define DCP0_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
+#define DCP0_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L
+//DCP0_OUTPUT_CSC_C11_C12
+#define DCP0_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
+#define DCP0_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
+#define DCP0_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000FFFFL
+#define DCP0_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xFFFF0000L
+//DCP0_OUTPUT_CSC_C13_C14
+#define DCP0_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
+#define DCP0_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
+#define DCP0_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000FFFFL
+#define DCP0_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xFFFF0000L
+//DCP0_OUTPUT_CSC_C21_C22
+#define DCP0_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
+#define DCP0_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
+#define DCP0_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000FFFFL
+#define DCP0_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xFFFF0000L
+//DCP0_OUTPUT_CSC_C23_C24
+#define DCP0_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
+#define DCP0_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
+#define DCP0_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000FFFFL
+#define DCP0_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xFFFF0000L
+//DCP0_OUTPUT_CSC_C31_C32
+#define DCP0_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
+#define DCP0_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
+#define DCP0_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000FFFFL
+#define DCP0_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xFFFF0000L
+//DCP0_OUTPUT_CSC_C33_C34
+#define DCP0_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
+#define DCP0_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
+#define DCP0_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000FFFFL
+#define DCP0_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xFFFF0000L
+//DCP0_COMM_MATRIXA_TRANS_C11_C12
+#define DCP0_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
+#define DCP0_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
+#define DCP0_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000FFFFL
+#define DCP0_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xFFFF0000L
+//DCP0_COMM_MATRIXA_TRANS_C13_C14
+#define DCP0_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
+#define DCP0_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
+#define DCP0_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000FFFFL
+#define DCP0_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xFFFF0000L
+//DCP0_COMM_MATRIXA_TRANS_C21_C22
+#define DCP0_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
+#define DCP0_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
+#define DCP0_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000FFFFL
+#define DCP0_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xFFFF0000L
+//DCP0_COMM_MATRIXA_TRANS_C23_C24
+#define DCP0_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
+#define DCP0_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
+#define DCP0_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000FFFFL
+#define DCP0_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xFFFF0000L
+//DCP0_COMM_MATRIXA_TRANS_C31_C32
+#define DCP0_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
+#define DCP0_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
+#define DCP0_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000FFFFL
+#define DCP0_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xFFFF0000L
+//DCP0_COMM_MATRIXA_TRANS_C33_C34
+#define DCP0_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
+#define DCP0_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
+#define DCP0_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000FFFFL
+#define DCP0_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xFFFF0000L
+//DCP0_COMM_MATRIXB_TRANS_C11_C12
+#define DCP0_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
+#define DCP0_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
+#define DCP0_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000FFFFL
+#define DCP0_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xFFFF0000L
+//DCP0_COMM_MATRIXB_TRANS_C13_C14
+#define DCP0_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
+#define DCP0_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
+#define DCP0_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000FFFFL
+#define DCP0_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xFFFF0000L
+//DCP0_COMM_MATRIXB_TRANS_C21_C22
+#define DCP0_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
+#define DCP0_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
+#define DCP0_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000FFFFL
+#define DCP0_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xFFFF0000L
+//DCP0_COMM_MATRIXB_TRANS_C23_C24
+#define DCP0_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
+#define DCP0_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
+#define DCP0_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000FFFFL
+#define DCP0_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xFFFF0000L
+//DCP0_COMM_MATRIXB_TRANS_C31_C32
+#define DCP0_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
+#define DCP0_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
+#define DCP0_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000FFFFL
+#define DCP0_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xFFFF0000L
+//DCP0_COMM_MATRIXB_TRANS_C33_C34
+#define DCP0_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
+#define DCP0_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
+#define DCP0_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000FFFFL
+#define DCP0_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xFFFF0000L
+//DCP0_DENORM_CONTROL
+#define DCP0_DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
+#define DCP0_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
+#define DCP0_DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L
+#define DCP0_DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x00000010L
+//DCP0_OUT_ROUND_CONTROL
+#define DCP0_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
+#define DCP0_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000FL
+//DCP0_OUT_CLAMP_CONTROL_R_CR
+#define DCP0_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
+#define DCP0_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
+#define DCP0_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x00003FFFL
+#define DCP0_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3FFF0000L
+//DCP0_OUT_CLAMP_CONTROL_G_Y
+#define DCP0_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
+#define DCP0_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
+#define DCP0_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x00003FFFL
+#define DCP0_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3FFF0000L
+//DCP0_OUT_CLAMP_CONTROL_B_CB
+#define DCP0_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
+#define DCP0_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
+#define DCP0_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x00003FFFL
+#define DCP0_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3FFF0000L
+//DCP0_KEY_CONTROL
+#define DCP0_KEY_CONTROL__KEY_MODE__SHIFT 0x1
+#define DCP0_KEY_CONTROL__KEY_MODE_MASK 0x00000006L
+//DCP0_KEY_RANGE_ALPHA
+#define DCP0_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
+#define DCP0_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
+#define DCP0_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000FFFFL
+#define DCP0_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xFFFF0000L
+//DCP0_KEY_RANGE_RED
+#define DCP0_KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
+#define DCP0_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
+#define DCP0_KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000FFFFL
+#define DCP0_KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xFFFF0000L
+//DCP0_KEY_RANGE_GREEN
+#define DCP0_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
+#define DCP0_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
+#define DCP0_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000FFFFL
+#define DCP0_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xFFFF0000L
+//DCP0_KEY_RANGE_BLUE
+#define DCP0_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
+#define DCP0_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
+#define DCP0_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000FFFFL
+#define DCP0_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xFFFF0000L
+//DCP0_DEGAMMA_CONTROL
+#define DCP0_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
+#define DCP0_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
+#define DCP0_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
+#define DCP0_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L
+#define DCP0_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x00000300L
+#define DCP0_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L
+//DCP0_GAMUT_REMAP_CONTROL
+#define DCP0_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
+#define DCP0_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L
+//DCP0_GAMUT_REMAP_C11_C12
+#define DCP0_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
+#define DCP0_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
+#define DCP0_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000FFFFL
+#define DCP0_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xFFFF0000L
+//DCP0_GAMUT_REMAP_C13_C14
+#define DCP0_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
+#define DCP0_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
+#define DCP0_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000FFFFL
+#define DCP0_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xFFFF0000L
+//DCP0_GAMUT_REMAP_C21_C22
+#define DCP0_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
+#define DCP0_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
+#define DCP0_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000FFFFL
+#define DCP0_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xFFFF0000L
+//DCP0_GAMUT_REMAP_C23_C24
+#define DCP0_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
+#define DCP0_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
+#define DCP0_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000FFFFL
+#define DCP0_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xFFFF0000L
+//DCP0_GAMUT_REMAP_C31_C32
+#define DCP0_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
+#define DCP0_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
+#define DCP0_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000FFFFL
+#define DCP0_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xFFFF0000L
+//DCP0_GAMUT_REMAP_C33_C34
+#define DCP0_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
+#define DCP0_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
+#define DCP0_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000FFFFL
+#define DCP0_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xFFFF0000L
+//DCP0_DCP_SPATIAL_DITHER_CNTL
+#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
+#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
+#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
+#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
+#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
+#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
+#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L
+#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L
+#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x000000C0L
+#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L
+#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L
+#define DCP0_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L
+//DCP0_DCP_RANDOM_SEEDS
+#define DCP0_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
+#define DCP0_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
+#define DCP0_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
+#define DCP0_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000FFL
+#define DCP0_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000FF00L
+#define DCP0_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00FF0000L
+//DCP0_DCP_FP_CONVERTED_FIELD
+#define DCP0_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
+#define DCP0_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
+#define DCP0_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
+#define DCP0_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
+//DCP0_CUR_CONTROL
+#define DCP0_CUR_CONTROL__CURSOR_EN__SHIFT 0x0
+#define DCP0_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
+#define DCP0_CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
+#define DCP0_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT 0xb
+#define DCP0_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT 0xc
+#define DCP0_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
+#define DCP0_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
+#define DCP0_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
+#define DCP0_CUR_CONTROL__CURSOR_EN_MASK 0x00000001L
+#define DCP0_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L
+#define DCP0_CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L
+#define DCP0_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK 0x00000800L
+#define DCP0_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK 0x0000F000L
+#define DCP0_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L
+#define DCP0_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L
+#define DCP0_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L
+//DCP0_CUR_SURFACE_ADDRESS
+#define DCP0_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
+#define DCP0_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//DCP0_CUR_SIZE
+#define DCP0_CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
+#define DCP0_CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
+#define DCP0_CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000007FL
+#define DCP0_CUR_SIZE__CURSOR_WIDTH_MASK 0x007F0000L
+//DCP0_CUR_SURFACE_ADDRESS_HIGH
+#define DCP0_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP0_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP0_CUR_POSITION
+#define DCP0_CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
+#define DCP0_CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
+#define DCP0_CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
+#define DCP0_CUR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
+//DCP0_CUR_HOT_SPOT
+#define DCP0_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
+#define DCP0_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
+#define DCP0_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000007FL
+#define DCP0_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x007F0000L
+//DCP0_CUR_COLOR1
+#define DCP0_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
+#define DCP0_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
+#define DCP0_CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
+#define DCP0_CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000FFL
+#define DCP0_CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000FF00L
+#define DCP0_CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00FF0000L
+//DCP0_CUR_COLOR2
+#define DCP0_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
+#define DCP0_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
+#define DCP0_CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
+#define DCP0_CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000FFL
+#define DCP0_CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000FF00L
+#define DCP0_CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00FF0000L
+//DCP0_CUR_UPDATE
+#define DCP0_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
+#define DCP0_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
+#define DCP0_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
+#define DCP0_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define DCP0_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
+#define DCP0_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L
+#define DCP0_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L
+#define DCP0_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L
+#define DCP0_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+#define DCP0_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x06000000L
+//DCP0_CUR_REQUEST_FILTER_CNTL
+#define DCP0_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
+#define DCP0_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L
+//DCP0_CUR_STEREO_CONTROL
+#define DCP0_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
+#define DCP0_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
+#define DCP0_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
+#define DCP0_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
+#define DCP0_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x00003FF0L
+#define DCP0_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x03FF0000L
+//DCP0_DC_LUT_RW_MODE
+#define DCP0_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
+#define DCP0_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
+#define DCP0_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
+#define DCP0_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L
+#define DCP0_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x00010000L
+#define DCP0_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x00020000L
+//DCP0_DC_LUT_RW_INDEX
+#define DCP0_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
+#define DCP0_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000FFL
+//DCP0_DC_LUT_SEQ_COLOR
+#define DCP0_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
+#define DCP0_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000FFFFL
+//DCP0_DC_LUT_PWL_DATA
+#define DCP0_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
+#define DCP0_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
+#define DCP0_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000FFFFL
+#define DCP0_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xFFFF0000L
+//DCP0_DC_LUT_30_COLOR
+#define DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
+#define DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
+#define DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
+#define DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003FFL
+#define DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
+#define DCP0_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3FF00000L
+//DCP0_DC_LUT_VGA_ACCESS_ENABLE
+#define DCP0_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
+#define DCP0_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L
+//DCP0_DC_LUT_WRITE_EN_MASK
+#define DCP0_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define DCP0_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L
+//DCP0_DC_LUT_AUTOFILL
+#define DCP0_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
+#define DCP0_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
+#define DCP0_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L
+#define DCP0_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L
+//DCP0_DC_LUT_CONTROL
+#define DCP0_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
+#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
+#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
+#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
+#define DCP0_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
+#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
+#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
+#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
+#define DCP0_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
+#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
+#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
+#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
+#define DCP0_DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000FL
+#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L
+#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L
+#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000C0L
+#define DCP0_DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000F00L
+#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L
+#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L
+#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000C000L
+#define DCP0_DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000F0000L
+#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L
+#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L
+#define DCP0_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00C00000L
+//DCP0_DC_LUT_BLACK_OFFSET_BLUE
+#define DCP0_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
+#define DCP0_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL
+//DCP0_DC_LUT_BLACK_OFFSET_GREEN
+#define DCP0_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
+#define DCP0_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL
+//DCP0_DC_LUT_BLACK_OFFSET_RED
+#define DCP0_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
+#define DCP0_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL
+//DCP0_DC_LUT_WHITE_OFFSET_BLUE
+#define DCP0_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
+#define DCP0_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000FFFFL
+//DCP0_DC_LUT_WHITE_OFFSET_GREEN
+#define DCP0_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
+#define DCP0_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000FFFFL
+//DCP0_DC_LUT_WHITE_OFFSET_RED
+#define DCP0_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
+#define DCP0_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000FFFFL
+//DCP0_DCP_CRC_CONTROL
+#define DCP0_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
+#define DCP0_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
+#define DCP0_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
+#define DCP0_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L
+#define DCP0_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001CL
+#define DCP0_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L
+//DCP0_DCP_CRC_MASK
+#define DCP0_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
+#define DCP0_DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xFFFFFFFFL
+//DCP0_DCP_CRC_CURRENT
+#define DCP0_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
+#define DCP0_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xFFFFFFFFL
+//DCP0_DVMM_PTE_CONTROL
+#define DCP0_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
+#define DCP0_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
+#define DCP0_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
+#define DCP0_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
+#define DCP0_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
+#define DCP0_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
+#define DCP0_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
+#define DCP0_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
+#define DCP0_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
+#define DCP0_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
+#define DCP0_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
+#define DCP0_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
+//DCP0_DCP_CRC_LAST
+#define DCP0_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
+#define DCP0_DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xFFFFFFFFL
+//DCP0_DVMM_PTE_ARB_CONTROL
+#define DCP0_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
+#define DCP0_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
+#define DCP0_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
+#define DCP0_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
+//DCP0_GRPH_FLIP_RATE_CNTL
+#define DCP0_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
+#define DCP0_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
+#define DCP0_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x00000007L
+#define DCP0_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x00000008L
+//DCP0_DCP_GSL_CONTROL
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x4
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x14
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x15
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x17
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT 0x1a
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x000FFFF0L
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00100000L
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x00600000L
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x00800000L
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK 0x04000000L
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L
+#define DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xF0000000L
+//DCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK
+#define DCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
+#define DCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
+#define DCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000FL
+#define DCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000001F0L
+//DCP0_GRPH_STEREOSYNC_FLIP
+#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
+#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
+#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
+#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L
+#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
+#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
+#define DCP0_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
+//DCP0_HW_ROTATION
+#define DCP0_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
+#define DCP0_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x00000007L
+//DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL
+#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
+#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
+#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
+#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x00000001L
+#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x00000002L
+#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x0001FFF0L
+//DCP0_REGAMMA_CONTROL
+#define DCP0_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
+#define DCP0_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L
+//DCP0_REGAMMA_LUT_INDEX
+#define DCP0_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
+#define DCP0_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001FFL
+//DCP0_REGAMMA_LUT_DATA
+#define DCP0_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
+#define DCP0_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007FFFFL
+//DCP0_REGAMMA_LUT_WRITE_EN_MASK
+#define DCP0_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define DCP0_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
+//DCP0_REGAMMA_CNTLA_START_CNTL
+#define DCP0_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define DCP0_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
+#define DCP0_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+//DCP0_REGAMMA_CNTLA_SLOPE_CNTL
+#define DCP0_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+//DCP0_REGAMMA_CNTLA_END_CNTL1
+#define DCP0_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
+//DCP0_REGAMMA_CNTLA_END_CNTL2
+#define DCP0_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
+#define DCP0_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+#define DCP0_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+//DCP0_REGAMMA_CNTLA_REGION_0_1
+#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP0_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//DCP0_REGAMMA_CNTLA_REGION_2_3
+#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP0_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//DCP0_REGAMMA_CNTLA_REGION_4_5
+#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP0_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//DCP0_REGAMMA_CNTLA_REGION_6_7
+#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP0_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//DCP0_REGAMMA_CNTLA_REGION_8_9
+#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP0_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//DCP0_REGAMMA_CNTLA_REGION_10_11
+#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP0_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//DCP0_REGAMMA_CNTLA_REGION_12_13
+#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP0_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//DCP0_REGAMMA_CNTLA_REGION_14_15
+#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP0_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//DCP0_REGAMMA_CNTLB_START_CNTL
+#define DCP0_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define DCP0_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
+#define DCP0_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+//DCP0_REGAMMA_CNTLB_SLOPE_CNTL
+#define DCP0_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+//DCP0_REGAMMA_CNTLB_END_CNTL1
+#define DCP0_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
+//DCP0_REGAMMA_CNTLB_END_CNTL2
+#define DCP0_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
+#define DCP0_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+#define DCP0_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+//DCP0_REGAMMA_CNTLB_REGION_0_1
+#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP0_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//DCP0_REGAMMA_CNTLB_REGION_2_3
+#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP0_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//DCP0_REGAMMA_CNTLB_REGION_4_5
+#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP0_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//DCP0_REGAMMA_CNTLB_REGION_6_7
+#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP0_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//DCP0_REGAMMA_CNTLB_REGION_8_9
+#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP0_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//DCP0_REGAMMA_CNTLB_REGION_10_11
+#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP0_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//DCP0_REGAMMA_CNTLB_REGION_12_13
+#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP0_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//DCP0_REGAMMA_CNTLB_REGION_14_15
+#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP0_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//DCP0_ALPHA_CONTROL
+#define DCP0_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
+#define DCP0_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
+#define DCP0_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x00000001L
+#define DCP0_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x00000002L
+//DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS
+#define DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH
+#define DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS
+#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
+#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
+#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
+#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
+#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
+#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
+#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
+#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0x000FFFFFL
+#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x01000000L
+#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x02000000L
+#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x04000000L
+#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000L
+#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000L
+#define DCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000L
+//DCP0_GRPH_XDMA_FLIP_TIMEOUT
+#define DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT 0x0
+#define DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT 0x1
+#define DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT 0x2
+#define DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK 0x00000001L
+#define DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK 0x00000002L
+#define DCP0_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK 0x00000004L
+//DCP0_GRPH_XDMA_FLIP_AVG_DELAY
+#define DCP0_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT 0x0
+#define DCP0_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT 0x10
+#define DCP0_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK 0x0000FFFFL
+#define DCP0_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK 0x00FF0000L
+//DCP0_GRPH_SURFACE_COUNTER_CONTROL
+#define DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0
+#define DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1
+#define DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9
+#define DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x00000001L
+#define DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x0000001EL
+#define DCP0_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x00000200L
+//DCP0_GRPH_SURFACE_COUNTER_OUTPUT
+#define DCP0_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0
+#define DCP0_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10
+#define DCP0_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0x0000FFFFL
+#define DCP0_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_lb0_dispdec
+//LB0_LB_DATA_FORMAT
+#define LB0_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
+#define LB0_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
+#define LB0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
+#define LB0_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
+#define LB0_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
+#define LB0_LB_DATA_FORMAT__PREFILL_EN__SHIFT 0x8
+#define LB0_LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
+#define LB0_LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
+#define LB0_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
+#define LB0_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
+#define LB0_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
+#define LB0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
+#define LB0_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
+#define LB0_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
+#define LB0_LB_DATA_FORMAT__PREFILL_EN_MASK 0x00000100L
+#define LB0_LB_DATA_FORMAT__PREFETCH_MASK 0x00001000L
+#define LB0_LB_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
+#define LB0_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
+//LB0_LB_MEMORY_CTRL
+#define LB0_LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
+#define LB0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+#define LB0_LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
+#define LB0_LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00001FFFL
+#define LB0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
+#define LB0_LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
+//LB0_LB_MEMORY_SIZE_STATUS
+#define LB0_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
+#define LB0_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00001FFFL
+//LB0_LB_DESKTOP_HEIGHT
+#define LB0_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
+#define LB0_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
+//LB0_LB_VLINE_START_END
+#define LB0_LB_VLINE_START_END__VLINE_START__SHIFT 0x0
+#define LB0_LB_VLINE_START_END__VLINE_END__SHIFT 0x10
+#define LB0_LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
+#define LB0_LB_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
+#define LB0_LB_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
+#define LB0_LB_VLINE_START_END__VLINE_INV_MASK 0x80000000L
+//LB0_LB_VLINE2_START_END
+#define LB0_LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
+#define LB0_LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
+#define LB0_LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
+#define LB0_LB_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
+#define LB0_LB_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
+#define LB0_LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
+//LB0_LB_V_COUNTER
+#define LB0_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
+#define LB0_LB_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
+//LB0_LB_SNAPSHOT_V_COUNTER
+#define LB0_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
+#define LB0_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
+//LB0_LB_INTERRUPT_MASK
+#define LB0_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
+#define LB0_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
+#define LB0_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
+#define LB0_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
+#define LB0_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
+#define LB0_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
+//LB0_LB_VLINE_STATUS
+#define LB0_LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
+#define LB0_LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
+#define LB0_LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
+#define LB0_LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
+#define LB0_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
+#define LB0_LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
+#define LB0_LB_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
+#define LB0_LB_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
+#define LB0_LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
+#define LB0_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
+//LB0_LB_VLINE2_STATUS
+#define LB0_LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
+#define LB0_LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
+#define LB0_LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
+#define LB0_LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
+#define LB0_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
+#define LB0_LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
+#define LB0_LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
+#define LB0_LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
+#define LB0_LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
+#define LB0_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
+//LB0_LB_VBLANK_STATUS
+#define LB0_LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
+#define LB0_LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
+#define LB0_LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
+#define LB0_LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
+#define LB0_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
+#define LB0_LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
+#define LB0_LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
+#define LB0_LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
+#define LB0_LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
+#define LB0_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
+//LB0_LB_SYNC_RESET_SEL
+#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
+#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
+#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
+#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
+#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
+#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
+#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
+#define LB0_LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
+//LB0_LB_BLACK_KEYER_R_CR
+#define LB0_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
+#define LB0_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
+//LB0_LB_BLACK_KEYER_G_Y
+#define LB0_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
+#define LB0_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
+//LB0_LB_BLACK_KEYER_B_CB
+#define LB0_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
+#define LB0_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
+//LB0_LB_KEYER_COLOR_CTRL
+#define LB0_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
+#define LB0_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
+#define LB0_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
+#define LB0_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
+//LB0_LB_KEYER_COLOR_R_CR
+#define LB0_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
+#define LB0_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
+//LB0_LB_KEYER_COLOR_G_Y
+#define LB0_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
+#define LB0_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
+//LB0_LB_KEYER_COLOR_B_CB
+#define LB0_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
+#define LB0_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
+//LB0_LB_KEYER_COLOR_REP_R_CR
+#define LB0_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
+#define LB0_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
+//LB0_LB_KEYER_COLOR_REP_G_Y
+#define LB0_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
+#define LB0_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
+//LB0_LB_KEYER_COLOR_REP_B_CB
+#define LB0_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
+#define LB0_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
+//LB0_LB_BUFFER_LEVEL_STATUS
+#define LB0_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
+#define LB0_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
+#define LB0_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
+#define LB0_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
+#define LB0_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
+#define LB0_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
+#define LB0_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
+#define LB0_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
+//LB0_LB_BUFFER_URGENCY_CTRL
+#define LB0_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
+#define LB0_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
+#define LB0_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
+#define LB0_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
+//LB0_LB_BUFFER_URGENCY_STATUS
+#define LB0_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
+#define LB0_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
+#define LB0_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
+#define LB0_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
+//LB0_LB_BUFFER_STATUS
+#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
+#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
+#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
+#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
+#define LB0_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
+#define LB0_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
+#define LB0_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
+#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
+#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
+#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
+#define LB0_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
+#define LB0_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
+#define LB0_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
+#define LB0_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
+//LB0_LB_NO_OUTSTANDING_REQ_STATUS
+#define LB0_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
+#define LB0_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
+//LB0_MVP_AFR_FLIP_MODE
+#define LB0_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
+#define LB0_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L
+//LB0_MVP_AFR_FLIP_FIFO_CNTL
+#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
+#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
+#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
+#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
+#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000FL
+#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L
+#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L
+#define LB0_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L
+//LB0_MVP_FLIP_LINE_NUM_INSERT
+#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
+#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
+#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
+#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
+#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L
+#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007FFF00L
+#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3F000000L
+#define LB0_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L
+//LB0_DC_MVP_LB_CONTROL
+#define LB0_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
+#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
+#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
+#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
+#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
+#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
+#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
+#define LB0_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L
+#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L
+#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L
+#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L
+#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L
+#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L
+#define LB0_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L
+
+
+// addressBlock: dce_dc_dcfe0_dispdec
+//DCFE0_DCFE_CLOCK_CONTROL
+#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
+#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
+#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
+#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf
+#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT 0x11
+#define DCFE0_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
+#define DCFE0_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
+#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L
+#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L
+#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L
+#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x00008000L
+#define DCFE0_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK 0x00020000L
+#define DCFE0_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1F000000L
+#define DCFE0_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000L
+//DCFE0_DCFE_SOFT_RESET
+#define DCFE0_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
+#define DCFE0_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
+#define DCFE0_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
+#define DCFE0_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
+#define DCFE0_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
+#define DCFE0_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5
+#define DCFE0_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
+#define DCFE0_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x00000002L
+#define DCFE0_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x00000004L
+#define DCFE0_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x00000008L
+#define DCFE0_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
+#define DCFE0_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x00000020L
+//DCFE0_DCFE_MEM_PWR_CTRL
+#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
+#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
+#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
+#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
+#define DCFE0_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
+#define DCFE0_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
+#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
+#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
+#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x00000003L
+#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x00000004L
+#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x00000018L
+#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x00000020L
+#define DCFE0_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
+#define DCFE0_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x00000100L
+#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x00000600L
+#define DCFE0_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x00000800L
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x00003000L
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x00004000L
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x00018000L
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x00020000L
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0x000C0000L
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x00100000L
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x00600000L
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x00800000L
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x03000000L
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x04000000L
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000L
+#define DCFE0_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000L
+//DCFE0_DCFE_MEM_PWR_CTRL2
+#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
+#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
+#define DCFE0_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
+#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
+#define DCFE0_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
+#define DCFE0_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
+#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
+#define DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
+#define DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
+#define DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
+#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
+#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
+#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x00000003L
+#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
+#define DCFE0_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
+#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0x000000C0L
+#define DCFE0_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x00000300L
+#define DCFE0_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0x00000C00L
+#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x00003000L
+#define DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0x0000C000L
+#define DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x00030000L
+#define DCFE0_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x00040000L
+#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x00600000L
+#define DCFE0_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x00800000L
+//DCFE0_DCFE_MEM_PWR_STATUS
+#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
+#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
+#define DCFE0_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
+#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
+#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
+#define DCFE0_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
+#define DCFE0_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
+#define DCFE0_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
+#define DCFE0_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
+#define DCFE0_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
+#define DCFE0_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
+#define DCFE0_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
+#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x00000003L
+#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0x0000000CL
+#define DCFE0_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x00000030L
+#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0x000000C0L
+#define DCFE0_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x00000300L
+#define DCFE0_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0x00000C00L
+#define DCFE0_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x00003000L
+#define DCFE0_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0x0000C000L
+#define DCFE0_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x00030000L
+#define DCFE0_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0x000C0000L
+#define DCFE0_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x00300000L
+#define DCFE0_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0x00C00000L
+//DCFE0_DCFE_MISC
+#define DCFE0_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
+#define DCFE0_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
+//DCFE0_DCFE_FLUSH
+#define DCFE0_DCFE_FLUSH__FLUSH_OCCURED__SHIFT 0x0
+#define DCFE0_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
+#define DCFE0_DCFE_FLUSH__FLUSH_DEEP__SHIFT 0x2
+#define DCFE0_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
+#define DCFE0_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
+#define DCFE0_DCFE_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
+#define DCFE0_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
+#define DCFE0_DCFE_FLUSH__FLUSH_DEEP_MASK 0x00000004L
+#define DCFE0_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
+#define DCFE0_DCFE_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
+
+
+// addressBlock: dce_dc_dc_perfmon3_dispdec
+//DC_PERFMON3_PERFCOUNTER_CNTL
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON3_PERFCOUNTER_CNTL2
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON3_PERFCOUNTER_STATE
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON3_PERFMON_CNTL
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON3_PERFMON_CNTL2
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON3_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON3_PERFMON_CVALUE_LOW
+#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON3_PERFMON_HI
+#define DC_PERFMON3_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON3_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON3_PERFMON_LOW
+#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dmif_pg0_dispdec
+//DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
+#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
+#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
+//DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2
+#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
+#define DMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
+//DMIF_PG0_DPG_WATERMARK_MASK_CONTROL
+#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x4
+#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT 0xc
+#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0xf
+#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x12
+#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT 0x13
+#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT 0x14
+#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000007L
+#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000070L
+#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000700L
+#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK 0x00007000L
+#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00038000L
+#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x00040000L
+#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK 0x00080000L
+#define DMIF_PG0_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK 0x3FF00000L
+//DMIF_PG0_DPG_PIPE_URGENCY_CONTROL
+#define DMIF_PG0_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+#define DMIF_PG0_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+#define DMIF_PG0_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
+#define DMIF_PG0_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
+//DMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL
+#define DMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT 0x0
+#define DMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT 0x10
+#define DMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK 0x0000FFFFL
+#define DMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK 0xFFFF0000L
+//DMIF_PG0_DPG_PIPE_STUTTER_CONTROL
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT 0x10
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x14
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x15
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x16
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x17
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x1a
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x1b
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK 0x00010000L
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00100000L
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00200000L
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00400000L
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00800000L
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x04000000L
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x08000000L
+//DMIF_PG0_DPG_PIPE_STUTTER_CONTROL2
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x0
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT 0x10
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0x0000FFFFL
+#define DMIF_PG0_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
+//DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL
+#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT 0x0
+#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT 0x1
+#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT 0xf
+#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK 0x00000001L
+#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK 0x00000002L
+#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
+#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
+#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
+#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
+#define DMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK 0xFFFF8000L
+//DMIF_PG0_DPG_REPEATER_PROGRAM
+#define DMIF_PG0_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+#define DMIF_PG0_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+#define DMIF_PG0_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
+#define DMIF_PG0_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
+//DMIF_PG0_DPG_CHK_PRE_PROC_CNTL
+#define DMIF_PG0_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+#define DMIF_PG0_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
+//DMIF_PG0_DPG_DVMM_STATUS
+#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT 0x0
+#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT 0x1
+#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT 0x4
+#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT 0x5
+#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK 0x00000001L
+#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK 0x00000002L
+#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK 0x00000010L
+#define DMIF_PG0_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK 0x00000020L
+
+
+// addressBlock: dce_dc_scl0_dispdec
+//SCL0_SCL_COEF_RAM_SELECT
+#define SCL0_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define SCL0_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
+#define SCL0_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
+#define SCL0_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000FL
+#define SCL0_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000F00L
+#define SCL0_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00070000L
+//SCL0_SCL_COEF_RAM_TAP_DATA
+#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+#define SCL0_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+//SCL0_SCL_MODE
+#define SCL0_SCL_MODE__SCL_MODE__SHIFT 0x0
+#define SCL0_SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
+#define SCL0_SCL_MODE__SCL_MODE_MASK 0x00000003L
+#define SCL0_SCL_MODE__SCL_PSCL_EN_MASK 0x00000010L
+//SCL0_SCL_TAP_CONTROL
+#define SCL0_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
+#define SCL0_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
+#define SCL0_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
+#define SCL0_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000F00L
+//SCL0_SCL_CONTROL
+#define SCL0_SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+#define SCL0_SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
+#define SCL0_SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+#define SCL0_SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
+//SCL0_SCL_BYPASS_CONTROL
+#define SCL0_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
+#define SCL0_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L
+//SCL0_SCL_MANUAL_REPLICATE_CONTROL
+#define SCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+#define SCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+#define SCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+#define SCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+//SCL0_SCL_AUTOMATIC_MODE_CONTROL
+#define SCL0_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
+#define SCL0_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
+#define SCL0_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
+#define SCL0_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
+//SCL0_SCL_HORZ_FILTER_CONTROL
+#define SCL0_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
+#define SCL0_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCL0_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L
+#define SCL0_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+//SCL0_SCL_HORZ_FILTER_SCALE_RATIO
+#define SCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+#define SCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+//SCL0_SCL_HORZ_FILTER_INIT
+#define SCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+#define SCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+#define SCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+#define SCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+//SCL0_SCL_VERT_FILTER_CONTROL
+#define SCL0_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
+#define SCL0_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCL0_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L
+#define SCL0_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+//SCL0_SCL_VERT_FILTER_SCALE_RATIO
+#define SCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+#define SCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+//SCL0_SCL_VERT_FILTER_INIT
+#define SCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+#define SCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+#define SCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+#define SCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
+//SCL0_SCL_VERT_FILTER_INIT_BOT
+#define SCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+#define SCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+#define SCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+#define SCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
+//SCL0_SCL_ROUND_OFFSET
+#define SCL0_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
+#define SCL0_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+#define SCL0_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
+#define SCL0_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
+//SCL0_SCL_UPDATE
+#define SCL0_SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+#define SCL0_SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
+#define SCL0_SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
+#define SCL0_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
+#define SCL0_SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+#define SCL0_SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
+#define SCL0_SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
+#define SCL0_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
+//SCL0_SCL_F_SHARP_CONTROL
+#define SCL0_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
+#define SCL0_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
+#define SCL0_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
+#define SCL0_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
+#define SCL0_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L
+#define SCL0_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L
+#define SCL0_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L
+#define SCL0_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L
+//SCL0_SCL_ALU_CONTROL
+#define SCL0_SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
+#define SCL0_SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
+//SCL0_SCL_COEF_RAM_CONFLICT_STATUS
+#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
+#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
+#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
+#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
+#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
+#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L
+#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L
+#define SCL0_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
+//SCL0_VIEWPORT_START_SECONDARY
+#define SCL0_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
+#define SCL0_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
+#define SCL0_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
+#define SCL0_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
+//SCL0_VIEWPORT_START
+#define SCL0_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
+#define SCL0_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
+#define SCL0_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
+#define SCL0_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
+//SCL0_VIEWPORT_SIZE
+#define SCL0_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
+#define SCL0_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
+#define SCL0_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003FFFL
+#define SCL0_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3FFF0000L
+//SCL0_EXT_OVERSCAN_LEFT_RIGHT
+#define SCL0_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+#define SCL0_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+#define SCL0_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+#define SCL0_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+//SCL0_EXT_OVERSCAN_TOP_BOTTOM
+#define SCL0_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+#define SCL0_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+#define SCL0_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+#define SCL0_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+//SCL0_SCL_MODE_CHANGE_DET1
+#define SCL0_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
+#define SCL0_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
+#define SCL0_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
+#define SCL0_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
+#define SCL0_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
+#define SCL0_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
+//SCL0_SCL_MODE_CHANGE_DET2
+#define SCL0_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
+#define SCL0_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
+//SCL0_SCL_MODE_CHANGE_DET3
+#define SCL0_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
+#define SCL0_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
+#define SCL0_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
+#define SCL0_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
+//SCL0_SCL_MODE_CHANGE_MASK
+#define SCL0_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
+#define SCL0_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_blnd0_dispdec
+//BLND0_BLND_CONTROL
+#define BLND0_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
+#define BLND0_BLND_CONTROL__BLND_MODE__SHIFT 0x8
+#define BLND0_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
+#define BLND0_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
+#define BLND0_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
+#define BLND0_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
+#define BLND0_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
+#define BLND0_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
+#define BLND0_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
+#define BLND0_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
+#define BLND0_BLND_CONTROL__BLND_MODE_MASK 0x00000300L
+#define BLND0_BLND_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
+#define BLND0_BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
+#define BLND0_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
+#define BLND0_BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
+#define BLND0_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
+#define BLND0_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
+#define BLND0_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
+//BLND0_BLND_SM_CONTROL2
+#define BLND0_BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0
+#define BLND0_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
+#define BLND0_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
+#define BLND0_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+#define BLND0_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+#define BLND0_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
+#define BLND0_BLND_SM_CONTROL2__SM_MODE_MASK 0x00000007L
+#define BLND0_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
+#define BLND0_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
+#define BLND0_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+#define BLND0_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+#define BLND0_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
+//BLND0_BLND_CONTROL2
+#define BLND0_BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
+#define BLND0_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
+#define BLND0_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
+#define BLND0_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
+#define BLND0_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
+#define BLND0_BLND_CONTROL2__PTI_ENABLE_MASK 0x00000001L
+#define BLND0_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
+#define BLND0_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
+#define BLND0_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
+#define BLND0_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
+//BLND0_BLND_UPDATE
+#define BLND0_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
+#define BLND0_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
+#define BLND0_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
+#define BLND0_BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
+#define BLND0_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
+#define BLND0_BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
+//BLND0_BLND_UNDERFLOW_INTERRUPT
+#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
+#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
+#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
+#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
+#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
+#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
+#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
+#define BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
+//BLND0_BLND_V_UPDATE_LOCK
+#define BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
+#define BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
+#define BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
+#define BLND0_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
+#define BLND0_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
+#define BLND0_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
+#define BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
+#define BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
+#define BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
+#define BLND0_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
+#define BLND0_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
+#define BLND0_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
+//BLND0_BLND_REG_UPDATE_STATUS
+#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
+#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
+#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
+#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
+#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
+#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
+#define BLND0_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
+#define BLND0_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
+#define BLND0_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
+#define BLND0_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
+#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
+#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
+#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
+#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
+#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
+#define BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
+#define BLND0_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
+#define BLND0_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
+#define BLND0_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
+#define BLND0_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
+
+
+// addressBlock: dce_dc_crtc0_dispdec
+//CRTC0_CRTC_H_BLANK_EARLY_NUM
+#define CRTC0_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
+#define CRTC0_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
+#define CRTC0_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
+#define CRTC0_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
+//CRTC0_CRTC_H_TOTAL
+#define CRTC0_CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
+#define CRTC0_CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
+//CRTC0_CRTC_H_BLANK_START_END
+#define CRTC0_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
+#define CRTC0_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
+#define CRTC0_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
+#define CRTC0_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
+//CRTC0_CRTC_H_SYNC_A
+#define CRTC0_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
+#define CRTC0_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
+#define CRTC0_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
+#define CRTC0_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
+//CRTC0_CRTC_H_SYNC_A_CNTL
+#define CRTC0_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
+#define CRTC0_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
+#define CRTC0_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
+#define CRTC0_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
+#define CRTC0_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
+#define CRTC0_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
+//CRTC0_CRTC_H_SYNC_B
+#define CRTC0_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
+#define CRTC0_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
+#define CRTC0_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
+#define CRTC0_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
+//CRTC0_CRTC_H_SYNC_B_CNTL
+#define CRTC0_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
+#define CRTC0_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
+#define CRTC0_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
+#define CRTC0_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
+#define CRTC0_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
+#define CRTC0_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
+//CRTC0_CRTC_VBI_END
+#define CRTC0_CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
+#define CRTC0_CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
+#define CRTC0_CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
+#define CRTC0_CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
+//CRTC0_CRTC_V_TOTAL
+#define CRTC0_CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
+#define CRTC0_CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
+//CRTC0_CRTC_V_TOTAL_MIN
+#define CRTC0_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
+#define CRTC0_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
+//CRTC0_CRTC_V_TOTAL_MAX
+#define CRTC0_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
+#define CRTC0_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
+#define CRTC0_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
+#define CRTC0_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
+//CRTC0_CRTC_V_TOTAL_CONTROL
+#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
+#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
+#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
+#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
+#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
+#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
+#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
+#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
+#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
+#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
+#define CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+//CRTC0_CRTC_V_TOTAL_INT_STATUS
+#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+#define CRTC0_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+//CRTC0_CRTC_VSYNC_NOM_INT_STATUS
+#define CRTC0_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
+#define CRTC0_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+#define CRTC0_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
+#define CRTC0_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+//CRTC0_CRTC_V_BLANK_START_END
+#define CRTC0_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
+#define CRTC0_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
+#define CRTC0_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
+#define CRTC0_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
+//CRTC0_CRTC_V_SYNC_A
+#define CRTC0_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
+#define CRTC0_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
+#define CRTC0_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
+#define CRTC0_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
+//CRTC0_CRTC_V_SYNC_A_CNTL
+#define CRTC0_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
+#define CRTC0_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
+//CRTC0_CRTC_V_SYNC_B
+#define CRTC0_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
+#define CRTC0_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
+#define CRTC0_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
+#define CRTC0_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
+//CRTC0_CRTC_V_SYNC_B_CNTL
+#define CRTC0_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
+#define CRTC0_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
+//CRTC0_CRTC_DTMTEST_CNTL
+#define CRTC0_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
+#define CRTC0_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
+#define CRTC0_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
+#define CRTC0_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
+//CRTC0_CRTC_DTMTEST_STATUS_POSITION
+#define CRTC0_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
+#define CRTC0_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
+#define CRTC0_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
+#define CRTC0_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTC0_CRTC_TRIGA_CNTL
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
+#define CRTC0_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
+//CRTC0_CRTC_TRIGA_MANUAL_TRIG
+#define CRTC0_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
+#define CRTC0_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+//CRTC0_CRTC_TRIGB_CNTL
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
+#define CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
+//CRTC0_CRTC_TRIGB_MANUAL_TRIG
+#define CRTC0_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
+#define CRTC0_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+//CRTC0_CRTC_FORCE_COUNT_NOW_CNTL
+#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+#define CRTC0_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+//CRTC0_CRTC_FLOW_CONTROL
+#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
+#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+#define CRTC0_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+//CRTC0_CRTC_STEREO_FORCE_NEXT_EYE
+#define CRTC0_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+#define CRTC0_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+#define CRTC0_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
+#define CRTC0_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+#define CRTC0_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+#define CRTC0_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+//CRTC0_CRTC_AVSYNC_COUNTER
+#define CRTC0_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
+#define CRTC0_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
+//CRTC0_CRTC_CONTROL
+#define CRTC0_CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTC0_CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
+#define CRTC0_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
+#define CRTC0_CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
+#define CRTC0_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
+#define CRTC0_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
+#define CRTC0_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+#define CRTC0_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
+#define CRTC0_CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
+#define CRTC0_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+#define CRTC0_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+#define CRTC0_CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
+#define CRTC0_CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
+#define CRTC0_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
+#define CRTC0_CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
+#define CRTC0_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
+#define CRTC0_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+#define CRTC0_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+#define CRTC0_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
+#define CRTC0_CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
+#define CRTC0_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+#define CRTC0_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+//CRTC0_CRTC_BLANK_CONTROL
+#define CRTC0_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
+#define CRTC0_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
+#define CRTC0_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
+#define CRTC0_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
+#define CRTC0_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
+#define CRTC0_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
+//CRTC0_CRTC_INTERLACE_CONTROL
+#define CRTC0_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
+#define CRTC0_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+#define CRTC0_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
+#define CRTC0_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+//CRTC0_CRTC_INTERLACE_STATUS
+#define CRTC0_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+#define CRTC0_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
+#define CRTC0_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+#define CRTC0_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+//CRTC0_CRTC_FIELD_INDICATION_CONTROL
+#define CRTC0_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
+#define CRTC0_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
+#define CRTC0_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
+#define CRTC0_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
+//CRTC0_CRTC_PIXEL_DATA_READBACK0
+#define CRTC0_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+#define CRTC0_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+#define CRTC0_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
+#define CRTC0_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
+//CRTC0_CRTC_PIXEL_DATA_READBACK1
+#define CRTC0_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
+#define CRTC0_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
+//CRTC0_CRTC_STATUS
+#define CRTC0_CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
+#define CRTC0_CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
+#define CRTC0_CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
+#define CRTC0_CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
+#define CRTC0_CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
+#define CRTC0_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+#define CRTC0_CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
+#define CRTC0_CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
+#define CRTC0_CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
+#define CRTC0_CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L
+#define CRTC0_CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
+#define CRTC0_CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
+#define CRTC0_CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
+#define CRTC0_CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
+#define CRTC0_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+#define CRTC0_CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L
+#define CRTC0_CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
+#define CRTC0_CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
+//CRTC0_CRTC_STATUS_POSITION
+#define CRTC0_CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
+#define CRTC0_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
+#define CRTC0_CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
+#define CRTC0_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTC0_CRTC_NOM_VERT_POSITION
+#define CRTC0_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
+#define CRTC0_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
+//CRTC0_CRTC_STATUS_FRAME_COUNT
+#define CRTC0_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
+#define CRTC0_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
+//CRTC0_CRTC_STATUS_VF_COUNT
+#define CRTC0_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
+#define CRTC0_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
+//CRTC0_CRTC_STATUS_HV_COUNT
+#define CRTC0_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
+#define CRTC0_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
+//CRTC0_CRTC_COUNT_CONTROL
+#define CRTC0_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
+#define CRTC0_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
+#define CRTC0_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+#define CRTC0_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+//CRTC0_CRTC_COUNT_RESET
+#define CRTC0_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
+#define CRTC0_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
+//CRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define CRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+#define CRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+//CRTC0_CRTC_VERT_SYNC_CONTROL
+#define CRTC0_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+#define CRTC0_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+#define CRTC0_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+#define CRTC0_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+#define CRTC0_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+#define CRTC0_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+//CRTC0_CRTC_STEREO_STATUS
+#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
+#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
+#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
+#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
+#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
+#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
+#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
+#define CRTC0_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+//CRTC0_CRTC_STEREO_CONTROL
+#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
+#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+#define CRTC0_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+#define CRTC0_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
+#define CRTC0_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
+#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
+#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
+#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+#define CRTC0_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+#define CRTC0_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
+#define CRTC0_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+#define CRTC0_CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
+//CRTC0_CRTC_SNAPSHOT_STATUS
+#define CRTC0_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
+#define CRTC0_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
+#define CRTC0_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+#define CRTC0_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
+#define CRTC0_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
+#define CRTC0_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+//CRTC0_CRTC_SNAPSHOT_CONTROL
+#define CRTC0_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+#define CRTC0_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+//CRTC0_CRTC_SNAPSHOT_POSITION
+#define CRTC0_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+#define CRTC0_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+#define CRTC0_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
+#define CRTC0_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTC0_CRTC_SNAPSHOT_FRAME
+#define CRTC0_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+#define CRTC0_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+//CRTC0_CRTC_START_LINE_CONTROL
+#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
+#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
+#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
+#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
+#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
+#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
+#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
+#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
+#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
+#define CRTC0_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
+//CRTC0_CRTC_INTERRUPT_CONTROL
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+#define CRTC0_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+//CRTC0_CRTC_UPDATE_LOCK
+#define CRTC0_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
+#define CRTC0_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
+//CRTC0_CRTC_DOUBLE_BUFFER_CONTROL
+#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
+#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
+#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
+#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
+#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
+#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
+#define CRTC0_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
+//CRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE
+#define CRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
+#define CRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
+//CRTC0_CRTC_TEST_PATTERN_CONTROL
+#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
+#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
+#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
+#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
+#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
+#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
+#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
+#define CRTC0_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
+//CRTC0_CRTC_TEST_PATTERN_PARAMETERS
+#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
+#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
+#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
+#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
+#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
+#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
+#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
+#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
+#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
+#define CRTC0_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
+//CRTC0_CRTC_TEST_PATTERN_COLOR
+#define CRTC0_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
+#define CRTC0_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
+#define CRTC0_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
+#define CRTC0_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
+//CRTC0_CRTC_MASTER_UPDATE_LOCK
+#define CRTC0_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
+#define CRTC0_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
+#define CRTC0_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
+#define CRTC0_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
+#define CRTC0_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
+#define CRTC0_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
+//CRTC0_CRTC_MASTER_UPDATE_MODE
+#define CRTC0_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
+#define CRTC0_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
+#define CRTC0_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
+#define CRTC0_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
+//CRTC0_CRTC_MVP_INBAND_CNTL_INSERT
+#define CRTC0_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
+#define CRTC0_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
+#define CRTC0_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
+#define CRTC0_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
+//CRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER
+#define CRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
+#define CRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
+//CRTC0_CRTC_MVP_STATUS
+#define CRTC0_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
+#define CRTC0_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
+#define CRTC0_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
+#define CRTC0_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
+#define CRTC0_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
+#define CRTC0_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
+#define CRTC0_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
+#define CRTC0_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
+//CRTC0_CRTC_MASTER_EN
+#define CRTC0_CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTC0_CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
+//CRTC0_CRTC_ALLOW_STOP_OFF_V_CNT
+#define CRTC0_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
+#define CRTC0_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
+#define CRTC0_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
+#define CRTC0_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
+//CRTC0_CRTC_V_UPDATE_INT_STATUS
+#define CRTC0_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
+#define CRTC0_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
+#define CRTC0_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
+#define CRTC0_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
+//CRTC0_CRTC_OVERSCAN_COLOR
+#define CRTC0_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
+#define CRTC0_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
+#define CRTC0_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
+#define CRTC0_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
+#define CRTC0_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
+#define CRTC0_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
+//CRTC0_CRTC_OVERSCAN_COLOR_EXT
+#define CRTC0_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
+#define CRTC0_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
+#define CRTC0_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
+#define CRTC0_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
+#define CRTC0_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
+#define CRTC0_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
+//CRTC0_CRTC_BLANK_DATA_COLOR
+#define CRTC0_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+#define CRTC0_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+#define CRTC0_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+#define CRTC0_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+#define CRTC0_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+#define CRTC0_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+//CRTC0_CRTC_BLANK_DATA_COLOR_EXT
+#define CRTC0_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+#define CRTC0_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+#define CRTC0_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+#define CRTC0_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
+#define CRTC0_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
+#define CRTC0_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
+//CRTC0_CRTC_BLACK_COLOR
+#define CRTC0_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
+#define CRTC0_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
+#define CRTC0_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
+#define CRTC0_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
+#define CRTC0_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+#define CRTC0_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+//CRTC0_CRTC_BLACK_COLOR_EXT
+#define CRTC0_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+#define CRTC0_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+#define CRTC0_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+#define CRTC0_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
+#define CRTC0_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
+#define CRTC0_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
+//CRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION
+#define CRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+#define CRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+#define CRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
+#define CRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
+//CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL
+#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+#define CRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+//CRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION
+#define CRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+#define CRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
+//CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL
+#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+#define CRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+//CRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION
+#define CRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+#define CRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
+//CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL
+#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+#define CRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+//CRTC0_CRTC_CRC_CNTL
+#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
+#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
+#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
+#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
+#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
+#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
+#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
+#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
+#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
+#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
+#define CRTC0_CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
+//CRTC0_CRTC_CRC0_WINDOWA_X_CONTROL
+#define CRTC0_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
+#define CRTC0_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
+#define CRTC0_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
+#define CRTC0_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
+//CRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL
+#define CRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
+#define CRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
+#define CRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
+#define CRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
+//CRTC0_CRTC_CRC0_WINDOWB_X_CONTROL
+#define CRTC0_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
+#define CRTC0_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
+#define CRTC0_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
+#define CRTC0_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
+//CRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL
+#define CRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
+#define CRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
+#define CRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
+#define CRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
+//CRTC0_CRTC_CRC0_DATA_RG
+#define CRTC0_CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+#define CRTC0_CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+#define CRTC0_CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+#define CRTC0_CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+//CRTC0_CRTC_CRC0_DATA_B
+#define CRTC0_CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+#define CRTC0_CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+//CRTC0_CRTC_CRC1_WINDOWA_X_CONTROL
+#define CRTC0_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
+#define CRTC0_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
+#define CRTC0_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
+#define CRTC0_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
+//CRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL
+#define CRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
+#define CRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
+#define CRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
+#define CRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
+//CRTC0_CRTC_CRC1_WINDOWB_X_CONTROL
+#define CRTC0_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
+#define CRTC0_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
+#define CRTC0_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
+#define CRTC0_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
+//CRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL
+#define CRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
+#define CRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
+#define CRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
+#define CRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
+//CRTC0_CRTC_CRC1_DATA_RG
+#define CRTC0_CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+#define CRTC0_CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+#define CRTC0_CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+#define CRTC0_CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+//CRTC0_CRTC_CRC1_DATA_B
+#define CRTC0_CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+#define CRTC0_CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+//CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
+//CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START
+#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
+#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
+#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
+#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
+//CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END
+#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
+#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
+#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
+#define CRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
+//CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
+#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
+#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
+#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
+#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
+#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
+#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
+#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
+//CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL
+#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
+#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
+#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
+#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
+#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
+#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
+//CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
+#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
+#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
+#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
+#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
+#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
+#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
+#define CRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
+//CRTC0_CRTC_STATIC_SCREEN_CONTROL
+#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
+#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
+#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
+#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
+#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
+#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
+#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
+#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
+#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
+#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
+#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
+#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
+#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
+#define CRTC0_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
+//CRTC0_CRTC_3D_STRUCTURE_CONTROL
+#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
+#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
+#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
+#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
+#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+#define CRTC0_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+//CRTC0_CRTC_GSL_VSYNC_GAP
+#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
+#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+#define CRTC0_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
+//CRTC0_CRTC_GSL_WINDOW
+#define CRTC0_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
+#define CRTC0_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
+#define CRTC0_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
+#define CRTC0_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
+//CRTC0_CRTC_GSL_CONTROL
+#define CRTC0_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
+#define CRTC0_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
+#define CRTC0_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+#define CRTC0_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
+#define CRTC0_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
+#define CRTC0_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+//CRTC0_CRTC_RANGE_TIMING_INT_STATUS
+#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
+#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
+#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
+#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
+#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
+#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
+#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
+#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
+#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
+#define CRTC0_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
+//CRTC0_CRTC_DRR_CONTROL
+#define CRTC0_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY__SHIFT 0x0
+#define CRTC0_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0xe
+#define CRTC0_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS__SHIFT 0x1c
+#define CRTC0_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE__SHIFT 0x1d
+#define CRTC0_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY_MASK 0x00003FFFL
+#define CRTC0_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR_MASK 0x0FFFC000L
+#define CRTC0_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS_MASK 0x10000000L
+#define CRTC0_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE_MASK 0x60000000L
+
+
+// addressBlock: dce_dc_fmt0_dispdec
+//FMT0_FMT_CLAMP_COMPONENT_R
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
+//FMT0_FMT_CLAMP_COMPONENT_G
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
+//FMT0_FMT_CLAMP_COMPONENT_B
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
+//FMT0_FMT_DYNAMIC_EXP_CNTL
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
+//FMT0_FMT_CONTROL
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
+#define FMT0_FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
+#define FMT0_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED__SHIFT 0x1e
+#define FMT0_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR__SHIFT 0x1f
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
+#define FMT0_FMT_CONTROL__FMT_SRC_SELECT_MASK 0x07000000L
+#define FMT0_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_MASK 0x40000000L
+#define FMT0_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR_MASK 0x80000000L
+//FMT0_FMT_BIT_DEPTH_CONTROL
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
+//FMT0_FMT_DITHER_RAND_R_SEED
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
+//FMT0_FMT_DITHER_RAND_G_SEED
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
+//FMT0_FMT_DITHER_RAND_B_SEED
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
+//FMT0_FMT_CLAMP_CNTL
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
+//FMT0_FMT_CRC_CNTL
+#define FMT0_FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
+#define FMT0_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
+#define FMT0_FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
+#define FMT0_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5
+#define FMT0_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6
+#define FMT0_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
+#define FMT0_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9
+#define FMT0_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
+#define FMT0_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+#define FMT0_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
+#define FMT0_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
+#define FMT0_FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L
+#define FMT0_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x00000002L
+#define FMT0_FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L
+#define FMT0_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x00000020L
+#define FMT0_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x00000040L
+#define FMT0_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x00000100L
+#define FMT0_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x00000200L
+#define FMT0_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define FMT0_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+#define FMT0_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L
+#define FMT0_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L
+//FMT0_FMT_CRC_SIG_RED_GREEN_MASK
+#define FMT0_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
+#define FMT0_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
+#define FMT0_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
+#define FMT0_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
+//FMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK
+#define FMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
+#define FMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
+#define FMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
+#define FMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
+//FMT0_FMT_CRC_SIG_RED_GREEN
+#define FMT0_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
+#define FMT0_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
+#define FMT0_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000FFFFL
+#define FMT0_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xFFFF0000L
+//FMT0_FMT_CRC_SIG_BLUE_CONTROL
+#define FMT0_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
+#define FMT0_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
+#define FMT0_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000FFFFL
+#define FMT0_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xFFFF0000L
+//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
+//FMT0_FMT_420_HBLANK_EARLY_START
+#define FMT0_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START__SHIFT 0x0
+#define FMT0_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START_MASK 0x00000FFFL
+
+
+// addressBlock: dce_dc_dcp1_dispdec
+//DCP1_GRPH_ENABLE
+#define DCP1_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
+#define DCP1_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1
+#define DCP1_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
+#define DCP1_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x00000002L
+//DCP1_GRPH_CONTROL
+#define DCP1_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
+#define DCP1_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT 0x2
+#define DCP1_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
+#define DCP1_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT 0x6
+#define DCP1_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
+#define DCP1_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0xc
+#define DCP1_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+#define DCP1_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+#define DCP1_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT 0x12
+#define DCP1_GRPH_CONTROL__GRPH_SW_MODE__SHIFT 0x14
+#define DCP1_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT 0x1c
+#define DCP1_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
+#define DCP1_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
+#define DCP1_GRPH_CONTROL__GRPH_SE_ENABLE_MASK 0x00000004L
+#define DCP1_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
+#define DCP1_GRPH_CONTROL__GRPH_DIM_TYPE_MASK 0x000000C0L
+#define DCP1_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
+#define DCP1_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x00007000L
+#define DCP1_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
+#define DCP1_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
+#define DCP1_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK 0x000C0000L
+#define DCP1_GRPH_CONTROL__GRPH_SW_MODE_MASK 0x01F00000L
+#define DCP1_GRPH_CONTROL__GRPH_NUM_PIPES_MASK 0x70000000L
+#define DCP1_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
+//DCP1_GRPH_LUT_10BIT_BYPASS
+#define DCP1_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
+#define DCP1_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
+#define DCP1_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L
+#define DCP1_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L
+//DCP1_GRPH_SWAP_CNTL
+#define DCP1_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
+#define DCP1_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
+#define DCP1_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
+#define DCP1_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
+#define DCP1_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
+#define DCP1_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
+#define DCP1_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
+#define DCP1_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
+#define DCP1_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
+#define DCP1_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000C00L
+//DCP1_GRPH_PRIMARY_SURFACE_ADDRESS
+#define DCP1_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
+#define DCP1_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP1_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L
+#define DCP1_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP1_GRPH_SECONDARY_SURFACE_ADDRESS
+#define DCP1_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
+#define DCP1_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP1_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L
+#define DCP1_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP1_GRPH_PITCH
+#define DCP1_GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
+#define DCP1_GRPH_PITCH__GRPH_PITCH_MASK 0x00007FFFL
+//DCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+#define DCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+#define DCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP1_GRPH_SURFACE_OFFSET_X
+#define DCP1_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
+#define DCP1_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003FFFL
+//DCP1_GRPH_SURFACE_OFFSET_Y
+#define DCP1_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
+#define DCP1_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003FFFL
+//DCP1_GRPH_X_START
+#define DCP1_GRPH_X_START__GRPH_X_START__SHIFT 0x0
+#define DCP1_GRPH_X_START__GRPH_X_START_MASK 0x00003FFFL
+//DCP1_GRPH_Y_START
+#define DCP1_GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
+#define DCP1_GRPH_Y_START__GRPH_Y_START_MASK 0x00003FFFL
+//DCP1_GRPH_X_END
+#define DCP1_GRPH_X_END__GRPH_X_END__SHIFT 0x0
+#define DCP1_GRPH_X_END__GRPH_X_END_MASK 0x00007FFFL
+//DCP1_GRPH_Y_END
+#define DCP1_GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
+#define DCP1_GRPH_Y_END__GRPH_Y_END_MASK 0x00007FFFL
+//DCP1_INPUT_GAMMA_CONTROL
+#define DCP1_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
+#define DCP1_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000001L
+//DCP1_GRPH_UPDATE
+#define DCP1_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
+#define DCP1_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
+#define DCP1_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
+#define DCP1_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
+#define DCP1_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT 0x8
+#define DCP1_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT 0x9
+#define DCP1_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT 0xa
+#define DCP1_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
+#define DCP1_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
+#define DCP1_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define DCP1_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
+#define DCP1_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
+#define DCP1_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
+#define DCP1_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
+#define DCP1_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
+#define DCP1_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK 0x00000100L
+#define DCP1_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK 0x00000200L
+#define DCP1_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK 0x00000400L
+#define DCP1_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
+#define DCP1_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
+#define DCP1_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+#define DCP1_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
+//DCP1_GRPH_FLIP_CONTROL
+#define DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
+#define DCP1_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
+#define DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4
+#define DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5
+#define DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L
+#define DCP1_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x00000002L
+#define DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x00000010L
+#define DCP1_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000020L
+//DCP1_GRPH_SURFACE_ADDRESS_INUSE
+#define DCP1_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
+#define DCP1_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xFFFFFF00L
+//DCP1_GRPH_DFQ_CONTROL
+#define DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
+#define DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
+#define DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
+#define DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L
+#define DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L
+#define DCP1_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L
+//DCP1_GRPH_DFQ_STATUS
+#define DCP1_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
+#define DCP1_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
+#define DCP1_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
+#define DCP1_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
+#define DCP1_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000FL
+#define DCP1_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000F0L
+#define DCP1_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L
+#define DCP1_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L
+//DCP1_GRPH_INTERRUPT_STATUS
+#define DCP1_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
+#define DCP1_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
+#define DCP1_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
+#define DCP1_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
+//DCP1_GRPH_INTERRUPT_CONTROL
+#define DCP1_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
+#define DCP1_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
+#define DCP1_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
+#define DCP1_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
+//DCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE
+#define DCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
+#define DCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000FFL
+//DCP1_GRPH_COMPRESS_SURFACE_ADDRESS
+#define DCP1_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP1_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP1_GRPH_COMPRESS_PITCH
+#define DCP1_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
+#define DCP1_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001FFC0L
+//DCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH
+#define DCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
+#define DCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0
+#define DCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0x000000FFL
+//DCP1_PRESCALE_GRPH_CONTROL
+#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
+#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
+#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
+#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
+#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
+#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L
+#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L
+#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L
+#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L
+#define DCP1_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L
+//DCP1_PRESCALE_VALUES_GRPH_R
+#define DCP1_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
+#define DCP1_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
+#define DCP1_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000FFFFL
+#define DCP1_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xFFFF0000L
+//DCP1_PRESCALE_VALUES_GRPH_G
+#define DCP1_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
+#define DCP1_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
+#define DCP1_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000FFFFL
+#define DCP1_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xFFFF0000L
+//DCP1_PRESCALE_VALUES_GRPH_B
+#define DCP1_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
+#define DCP1_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
+#define DCP1_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000FFFFL
+#define DCP1_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xFFFF0000L
+//DCP1_INPUT_CSC_CONTROL
+#define DCP1_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
+#define DCP1_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L
+//DCP1_INPUT_CSC_C11_C12
+#define DCP1_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
+#define DCP1_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
+#define DCP1_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000FFFFL
+#define DCP1_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xFFFF0000L
+//DCP1_INPUT_CSC_C13_C14
+#define DCP1_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
+#define DCP1_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
+#define DCP1_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000FFFFL
+#define DCP1_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xFFFF0000L
+//DCP1_INPUT_CSC_C21_C22
+#define DCP1_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
+#define DCP1_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
+#define DCP1_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000FFFFL
+#define DCP1_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xFFFF0000L
+//DCP1_INPUT_CSC_C23_C24
+#define DCP1_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
+#define DCP1_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
+#define DCP1_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000FFFFL
+#define DCP1_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xFFFF0000L
+//DCP1_INPUT_CSC_C31_C32
+#define DCP1_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
+#define DCP1_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
+#define DCP1_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000FFFFL
+#define DCP1_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xFFFF0000L
+//DCP1_INPUT_CSC_C33_C34
+#define DCP1_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
+#define DCP1_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
+#define DCP1_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000FFFFL
+#define DCP1_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xFFFF0000L
+//DCP1_OUTPUT_CSC_CONTROL
+#define DCP1_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
+#define DCP1_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L
+//DCP1_OUTPUT_CSC_C11_C12
+#define DCP1_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
+#define DCP1_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
+#define DCP1_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000FFFFL
+#define DCP1_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xFFFF0000L
+//DCP1_OUTPUT_CSC_C13_C14
+#define DCP1_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
+#define DCP1_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
+#define DCP1_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000FFFFL
+#define DCP1_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xFFFF0000L
+//DCP1_OUTPUT_CSC_C21_C22
+#define DCP1_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
+#define DCP1_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
+#define DCP1_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000FFFFL
+#define DCP1_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xFFFF0000L
+//DCP1_OUTPUT_CSC_C23_C24
+#define DCP1_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
+#define DCP1_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
+#define DCP1_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000FFFFL
+#define DCP1_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xFFFF0000L
+//DCP1_OUTPUT_CSC_C31_C32
+#define DCP1_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
+#define DCP1_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
+#define DCP1_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000FFFFL
+#define DCP1_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xFFFF0000L
+//DCP1_OUTPUT_CSC_C33_C34
+#define DCP1_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
+#define DCP1_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
+#define DCP1_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000FFFFL
+#define DCP1_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xFFFF0000L
+//DCP1_COMM_MATRIXA_TRANS_C11_C12
+#define DCP1_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
+#define DCP1_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
+#define DCP1_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000FFFFL
+#define DCP1_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xFFFF0000L
+//DCP1_COMM_MATRIXA_TRANS_C13_C14
+#define DCP1_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
+#define DCP1_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
+#define DCP1_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000FFFFL
+#define DCP1_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xFFFF0000L
+//DCP1_COMM_MATRIXA_TRANS_C21_C22
+#define DCP1_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
+#define DCP1_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
+#define DCP1_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000FFFFL
+#define DCP1_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xFFFF0000L
+//DCP1_COMM_MATRIXA_TRANS_C23_C24
+#define DCP1_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
+#define DCP1_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
+#define DCP1_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000FFFFL
+#define DCP1_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xFFFF0000L
+//DCP1_COMM_MATRIXA_TRANS_C31_C32
+#define DCP1_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
+#define DCP1_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
+#define DCP1_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000FFFFL
+#define DCP1_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xFFFF0000L
+//DCP1_COMM_MATRIXA_TRANS_C33_C34
+#define DCP1_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
+#define DCP1_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
+#define DCP1_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000FFFFL
+#define DCP1_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xFFFF0000L
+//DCP1_COMM_MATRIXB_TRANS_C11_C12
+#define DCP1_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
+#define DCP1_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
+#define DCP1_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000FFFFL
+#define DCP1_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xFFFF0000L
+//DCP1_COMM_MATRIXB_TRANS_C13_C14
+#define DCP1_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
+#define DCP1_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
+#define DCP1_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000FFFFL
+#define DCP1_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xFFFF0000L
+//DCP1_COMM_MATRIXB_TRANS_C21_C22
+#define DCP1_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
+#define DCP1_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
+#define DCP1_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000FFFFL
+#define DCP1_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xFFFF0000L
+//DCP1_COMM_MATRIXB_TRANS_C23_C24
+#define DCP1_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
+#define DCP1_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
+#define DCP1_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000FFFFL
+#define DCP1_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xFFFF0000L
+//DCP1_COMM_MATRIXB_TRANS_C31_C32
+#define DCP1_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
+#define DCP1_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
+#define DCP1_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000FFFFL
+#define DCP1_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xFFFF0000L
+//DCP1_COMM_MATRIXB_TRANS_C33_C34
+#define DCP1_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
+#define DCP1_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
+#define DCP1_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000FFFFL
+#define DCP1_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xFFFF0000L
+//DCP1_DENORM_CONTROL
+#define DCP1_DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
+#define DCP1_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
+#define DCP1_DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L
+#define DCP1_DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x00000010L
+//DCP1_OUT_ROUND_CONTROL
+#define DCP1_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
+#define DCP1_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000FL
+//DCP1_OUT_CLAMP_CONTROL_R_CR
+#define DCP1_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
+#define DCP1_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
+#define DCP1_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x00003FFFL
+#define DCP1_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3FFF0000L
+//DCP1_OUT_CLAMP_CONTROL_G_Y
+#define DCP1_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
+#define DCP1_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
+#define DCP1_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x00003FFFL
+#define DCP1_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3FFF0000L
+//DCP1_OUT_CLAMP_CONTROL_B_CB
+#define DCP1_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
+#define DCP1_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
+#define DCP1_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x00003FFFL
+#define DCP1_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3FFF0000L
+//DCP1_KEY_CONTROL
+#define DCP1_KEY_CONTROL__KEY_MODE__SHIFT 0x1
+#define DCP1_KEY_CONTROL__KEY_MODE_MASK 0x00000006L
+//DCP1_KEY_RANGE_ALPHA
+#define DCP1_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
+#define DCP1_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
+#define DCP1_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000FFFFL
+#define DCP1_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xFFFF0000L
+//DCP1_KEY_RANGE_RED
+#define DCP1_KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
+#define DCP1_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
+#define DCP1_KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000FFFFL
+#define DCP1_KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xFFFF0000L
+//DCP1_KEY_RANGE_GREEN
+#define DCP1_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
+#define DCP1_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
+#define DCP1_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000FFFFL
+#define DCP1_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xFFFF0000L
+//DCP1_KEY_RANGE_BLUE
+#define DCP1_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
+#define DCP1_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
+#define DCP1_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000FFFFL
+#define DCP1_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xFFFF0000L
+//DCP1_DEGAMMA_CONTROL
+#define DCP1_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
+#define DCP1_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
+#define DCP1_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
+#define DCP1_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L
+#define DCP1_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x00000300L
+#define DCP1_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L
+//DCP1_GAMUT_REMAP_CONTROL
+#define DCP1_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
+#define DCP1_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L
+//DCP1_GAMUT_REMAP_C11_C12
+#define DCP1_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
+#define DCP1_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
+#define DCP1_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000FFFFL
+#define DCP1_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xFFFF0000L
+//DCP1_GAMUT_REMAP_C13_C14
+#define DCP1_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
+#define DCP1_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
+#define DCP1_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000FFFFL
+#define DCP1_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xFFFF0000L
+//DCP1_GAMUT_REMAP_C21_C22
+#define DCP1_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
+#define DCP1_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
+#define DCP1_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000FFFFL
+#define DCP1_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xFFFF0000L
+//DCP1_GAMUT_REMAP_C23_C24
+#define DCP1_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
+#define DCP1_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
+#define DCP1_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000FFFFL
+#define DCP1_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xFFFF0000L
+//DCP1_GAMUT_REMAP_C31_C32
+#define DCP1_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
+#define DCP1_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
+#define DCP1_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000FFFFL
+#define DCP1_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xFFFF0000L
+//DCP1_GAMUT_REMAP_C33_C34
+#define DCP1_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
+#define DCP1_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
+#define DCP1_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000FFFFL
+#define DCP1_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xFFFF0000L
+//DCP1_DCP_SPATIAL_DITHER_CNTL
+#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
+#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
+#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
+#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
+#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
+#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
+#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L
+#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L
+#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x000000C0L
+#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L
+#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L
+#define DCP1_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L
+//DCP1_DCP_RANDOM_SEEDS
+#define DCP1_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
+#define DCP1_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
+#define DCP1_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
+#define DCP1_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000FFL
+#define DCP1_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000FF00L
+#define DCP1_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00FF0000L
+//DCP1_DCP_FP_CONVERTED_FIELD
+#define DCP1_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
+#define DCP1_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
+#define DCP1_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
+#define DCP1_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
+//DCP1_CUR_CONTROL
+#define DCP1_CUR_CONTROL__CURSOR_EN__SHIFT 0x0
+#define DCP1_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
+#define DCP1_CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
+#define DCP1_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT 0xb
+#define DCP1_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT 0xc
+#define DCP1_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
+#define DCP1_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
+#define DCP1_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
+#define DCP1_CUR_CONTROL__CURSOR_EN_MASK 0x00000001L
+#define DCP1_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L
+#define DCP1_CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L
+#define DCP1_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK 0x00000800L
+#define DCP1_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK 0x0000F000L
+#define DCP1_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L
+#define DCP1_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L
+#define DCP1_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L
+//DCP1_CUR_SURFACE_ADDRESS
+#define DCP1_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
+#define DCP1_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//DCP1_CUR_SIZE
+#define DCP1_CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
+#define DCP1_CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
+#define DCP1_CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000007FL
+#define DCP1_CUR_SIZE__CURSOR_WIDTH_MASK 0x007F0000L
+//DCP1_CUR_SURFACE_ADDRESS_HIGH
+#define DCP1_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP1_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP1_CUR_POSITION
+#define DCP1_CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
+#define DCP1_CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
+#define DCP1_CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
+#define DCP1_CUR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
+//DCP1_CUR_HOT_SPOT
+#define DCP1_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
+#define DCP1_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
+#define DCP1_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000007FL
+#define DCP1_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x007F0000L
+//DCP1_CUR_COLOR1
+#define DCP1_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
+#define DCP1_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
+#define DCP1_CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
+#define DCP1_CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000FFL
+#define DCP1_CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000FF00L
+#define DCP1_CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00FF0000L
+//DCP1_CUR_COLOR2
+#define DCP1_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
+#define DCP1_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
+#define DCP1_CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
+#define DCP1_CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000FFL
+#define DCP1_CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000FF00L
+#define DCP1_CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00FF0000L
+//DCP1_CUR_UPDATE
+#define DCP1_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
+#define DCP1_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
+#define DCP1_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
+#define DCP1_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define DCP1_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
+#define DCP1_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L
+#define DCP1_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L
+#define DCP1_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L
+#define DCP1_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+#define DCP1_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x06000000L
+//DCP1_CUR_REQUEST_FILTER_CNTL
+#define DCP1_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
+#define DCP1_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L
+//DCP1_CUR_STEREO_CONTROL
+#define DCP1_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
+#define DCP1_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
+#define DCP1_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
+#define DCP1_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
+#define DCP1_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x00003FF0L
+#define DCP1_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x03FF0000L
+//DCP1_DC_LUT_RW_MODE
+#define DCP1_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
+#define DCP1_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
+#define DCP1_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
+#define DCP1_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L
+#define DCP1_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x00010000L
+#define DCP1_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x00020000L
+//DCP1_DC_LUT_RW_INDEX
+#define DCP1_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
+#define DCP1_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000FFL
+//DCP1_DC_LUT_SEQ_COLOR
+#define DCP1_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
+#define DCP1_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000FFFFL
+//DCP1_DC_LUT_PWL_DATA
+#define DCP1_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
+#define DCP1_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
+#define DCP1_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000FFFFL
+#define DCP1_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xFFFF0000L
+//DCP1_DC_LUT_30_COLOR
+#define DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
+#define DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
+#define DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
+#define DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003FFL
+#define DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
+#define DCP1_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3FF00000L
+//DCP1_DC_LUT_VGA_ACCESS_ENABLE
+#define DCP1_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
+#define DCP1_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L
+//DCP1_DC_LUT_WRITE_EN_MASK
+#define DCP1_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define DCP1_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L
+//DCP1_DC_LUT_AUTOFILL
+#define DCP1_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
+#define DCP1_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
+#define DCP1_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L
+#define DCP1_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L
+//DCP1_DC_LUT_CONTROL
+#define DCP1_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
+#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
+#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
+#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
+#define DCP1_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
+#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
+#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
+#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
+#define DCP1_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
+#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
+#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
+#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
+#define DCP1_DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000FL
+#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L
+#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L
+#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000C0L
+#define DCP1_DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000F00L
+#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L
+#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L
+#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000C000L
+#define DCP1_DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000F0000L
+#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L
+#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L
+#define DCP1_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00C00000L
+//DCP1_DC_LUT_BLACK_OFFSET_BLUE
+#define DCP1_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
+#define DCP1_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL
+//DCP1_DC_LUT_BLACK_OFFSET_GREEN
+#define DCP1_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
+#define DCP1_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL
+//DCP1_DC_LUT_BLACK_OFFSET_RED
+#define DCP1_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
+#define DCP1_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL
+//DCP1_DC_LUT_WHITE_OFFSET_BLUE
+#define DCP1_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
+#define DCP1_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000FFFFL
+//DCP1_DC_LUT_WHITE_OFFSET_GREEN
+#define DCP1_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
+#define DCP1_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000FFFFL
+//DCP1_DC_LUT_WHITE_OFFSET_RED
+#define DCP1_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
+#define DCP1_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000FFFFL
+//DCP1_DCP_CRC_CONTROL
+#define DCP1_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
+#define DCP1_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
+#define DCP1_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
+#define DCP1_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L
+#define DCP1_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001CL
+#define DCP1_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L
+//DCP1_DCP_CRC_MASK
+#define DCP1_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
+#define DCP1_DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xFFFFFFFFL
+//DCP1_DCP_CRC_CURRENT
+#define DCP1_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
+#define DCP1_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xFFFFFFFFL
+//DCP1_DVMM_PTE_CONTROL
+#define DCP1_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
+#define DCP1_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
+#define DCP1_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
+#define DCP1_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
+#define DCP1_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
+#define DCP1_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
+#define DCP1_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
+#define DCP1_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
+#define DCP1_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
+#define DCP1_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
+#define DCP1_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
+#define DCP1_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
+//DCP1_DCP_CRC_LAST
+#define DCP1_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
+#define DCP1_DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xFFFFFFFFL
+//DCP1_DVMM_PTE_ARB_CONTROL
+#define DCP1_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
+#define DCP1_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
+#define DCP1_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
+#define DCP1_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
+//DCP1_GRPH_FLIP_RATE_CNTL
+#define DCP1_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
+#define DCP1_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
+#define DCP1_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x00000007L
+#define DCP1_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x00000008L
+//DCP1_DCP_GSL_CONTROL
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x4
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x14
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x15
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x17
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT 0x1a
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x000FFFF0L
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00100000L
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x00600000L
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x00800000L
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK 0x04000000L
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L
+#define DCP1_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xF0000000L
+//DCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK
+#define DCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
+#define DCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
+#define DCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000FL
+#define DCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000001F0L
+//DCP1_GRPH_STEREOSYNC_FLIP
+#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
+#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
+#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
+#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L
+#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
+#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
+#define DCP1_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
+//DCP1_HW_ROTATION
+#define DCP1_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
+#define DCP1_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x00000007L
+//DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL
+#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
+#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
+#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
+#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x00000001L
+#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x00000002L
+#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x0001FFF0L
+//DCP1_REGAMMA_CONTROL
+#define DCP1_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
+#define DCP1_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L
+//DCP1_REGAMMA_LUT_INDEX
+#define DCP1_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
+#define DCP1_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001FFL
+//DCP1_REGAMMA_LUT_DATA
+#define DCP1_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
+#define DCP1_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007FFFFL
+//DCP1_REGAMMA_LUT_WRITE_EN_MASK
+#define DCP1_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define DCP1_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
+//DCP1_REGAMMA_CNTLA_START_CNTL
+#define DCP1_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define DCP1_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
+#define DCP1_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+//DCP1_REGAMMA_CNTLA_SLOPE_CNTL
+#define DCP1_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+//DCP1_REGAMMA_CNTLA_END_CNTL1
+#define DCP1_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
+//DCP1_REGAMMA_CNTLA_END_CNTL2
+#define DCP1_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
+#define DCP1_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+#define DCP1_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+//DCP1_REGAMMA_CNTLA_REGION_0_1
+#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP1_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//DCP1_REGAMMA_CNTLA_REGION_2_3
+#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP1_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//DCP1_REGAMMA_CNTLA_REGION_4_5
+#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP1_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//DCP1_REGAMMA_CNTLA_REGION_6_7
+#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP1_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//DCP1_REGAMMA_CNTLA_REGION_8_9
+#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP1_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//DCP1_REGAMMA_CNTLA_REGION_10_11
+#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP1_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//DCP1_REGAMMA_CNTLA_REGION_12_13
+#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP1_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//DCP1_REGAMMA_CNTLA_REGION_14_15
+#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP1_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//DCP1_REGAMMA_CNTLB_START_CNTL
+#define DCP1_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define DCP1_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
+#define DCP1_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+//DCP1_REGAMMA_CNTLB_SLOPE_CNTL
+#define DCP1_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+//DCP1_REGAMMA_CNTLB_END_CNTL1
+#define DCP1_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
+//DCP1_REGAMMA_CNTLB_END_CNTL2
+#define DCP1_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
+#define DCP1_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+#define DCP1_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+//DCP1_REGAMMA_CNTLB_REGION_0_1
+#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP1_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//DCP1_REGAMMA_CNTLB_REGION_2_3
+#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP1_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//DCP1_REGAMMA_CNTLB_REGION_4_5
+#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP1_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//DCP1_REGAMMA_CNTLB_REGION_6_7
+#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP1_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//DCP1_REGAMMA_CNTLB_REGION_8_9
+#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP1_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//DCP1_REGAMMA_CNTLB_REGION_10_11
+#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP1_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//DCP1_REGAMMA_CNTLB_REGION_12_13
+#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP1_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//DCP1_REGAMMA_CNTLB_REGION_14_15
+#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP1_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//DCP1_ALPHA_CONTROL
+#define DCP1_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
+#define DCP1_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
+#define DCP1_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x00000001L
+#define DCP1_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x00000002L
+//DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS
+#define DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH
+#define DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS
+#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
+#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
+#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
+#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
+#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
+#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
+#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
+#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0x000FFFFFL
+#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x01000000L
+#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x02000000L
+#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x04000000L
+#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000L
+#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000L
+#define DCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000L
+//DCP1_GRPH_XDMA_FLIP_TIMEOUT
+#define DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT 0x0
+#define DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT 0x1
+#define DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT 0x2
+#define DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK 0x00000001L
+#define DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK 0x00000002L
+#define DCP1_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK 0x00000004L
+//DCP1_GRPH_XDMA_FLIP_AVG_DELAY
+#define DCP1_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT 0x0
+#define DCP1_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT 0x10
+#define DCP1_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK 0x0000FFFFL
+#define DCP1_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK 0x00FF0000L
+//DCP1_GRPH_SURFACE_COUNTER_CONTROL
+#define DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0
+#define DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1
+#define DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9
+#define DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x00000001L
+#define DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x0000001EL
+#define DCP1_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x00000200L
+//DCP1_GRPH_SURFACE_COUNTER_OUTPUT
+#define DCP1_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0
+#define DCP1_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10
+#define DCP1_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0x0000FFFFL
+#define DCP1_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_lb1_dispdec
+//LB1_LB_DATA_FORMAT
+#define LB1_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
+#define LB1_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
+#define LB1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
+#define LB1_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
+#define LB1_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
+#define LB1_LB_DATA_FORMAT__PREFILL_EN__SHIFT 0x8
+#define LB1_LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
+#define LB1_LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
+#define LB1_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
+#define LB1_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
+#define LB1_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
+#define LB1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
+#define LB1_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
+#define LB1_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
+#define LB1_LB_DATA_FORMAT__PREFILL_EN_MASK 0x00000100L
+#define LB1_LB_DATA_FORMAT__PREFETCH_MASK 0x00001000L
+#define LB1_LB_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
+#define LB1_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
+//LB1_LB_MEMORY_CTRL
+#define LB1_LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
+#define LB1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+#define LB1_LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
+#define LB1_LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00001FFFL
+#define LB1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
+#define LB1_LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
+//LB1_LB_MEMORY_SIZE_STATUS
+#define LB1_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
+#define LB1_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00001FFFL
+//LB1_LB_DESKTOP_HEIGHT
+#define LB1_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
+#define LB1_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
+//LB1_LB_VLINE_START_END
+#define LB1_LB_VLINE_START_END__VLINE_START__SHIFT 0x0
+#define LB1_LB_VLINE_START_END__VLINE_END__SHIFT 0x10
+#define LB1_LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
+#define LB1_LB_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
+#define LB1_LB_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
+#define LB1_LB_VLINE_START_END__VLINE_INV_MASK 0x80000000L
+//LB1_LB_VLINE2_START_END
+#define LB1_LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
+#define LB1_LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
+#define LB1_LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
+#define LB1_LB_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
+#define LB1_LB_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
+#define LB1_LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
+//LB1_LB_V_COUNTER
+#define LB1_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
+#define LB1_LB_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
+//LB1_LB_SNAPSHOT_V_COUNTER
+#define LB1_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
+#define LB1_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
+//LB1_LB_INTERRUPT_MASK
+#define LB1_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
+#define LB1_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
+#define LB1_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
+#define LB1_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
+#define LB1_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
+#define LB1_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
+//LB1_LB_VLINE_STATUS
+#define LB1_LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
+#define LB1_LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
+#define LB1_LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
+#define LB1_LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
+#define LB1_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
+#define LB1_LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
+#define LB1_LB_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
+#define LB1_LB_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
+#define LB1_LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
+#define LB1_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
+//LB1_LB_VLINE2_STATUS
+#define LB1_LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
+#define LB1_LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
+#define LB1_LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
+#define LB1_LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
+#define LB1_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
+#define LB1_LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
+#define LB1_LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
+#define LB1_LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
+#define LB1_LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
+#define LB1_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
+//LB1_LB_VBLANK_STATUS
+#define LB1_LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
+#define LB1_LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
+#define LB1_LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
+#define LB1_LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
+#define LB1_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
+#define LB1_LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
+#define LB1_LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
+#define LB1_LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
+#define LB1_LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
+#define LB1_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
+//LB1_LB_SYNC_RESET_SEL
+#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
+#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
+#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
+#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
+#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
+#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
+#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
+#define LB1_LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
+//LB1_LB_BLACK_KEYER_R_CR
+#define LB1_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
+#define LB1_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
+//LB1_LB_BLACK_KEYER_G_Y
+#define LB1_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
+#define LB1_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
+//LB1_LB_BLACK_KEYER_B_CB
+#define LB1_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
+#define LB1_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
+//LB1_LB_KEYER_COLOR_CTRL
+#define LB1_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
+#define LB1_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
+#define LB1_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
+#define LB1_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
+//LB1_LB_KEYER_COLOR_R_CR
+#define LB1_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
+#define LB1_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
+//LB1_LB_KEYER_COLOR_G_Y
+#define LB1_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
+#define LB1_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
+//LB1_LB_KEYER_COLOR_B_CB
+#define LB1_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
+#define LB1_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
+//LB1_LB_KEYER_COLOR_REP_R_CR
+#define LB1_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
+#define LB1_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
+//LB1_LB_KEYER_COLOR_REP_G_Y
+#define LB1_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
+#define LB1_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
+//LB1_LB_KEYER_COLOR_REP_B_CB
+#define LB1_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
+#define LB1_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
+//LB1_LB_BUFFER_LEVEL_STATUS
+#define LB1_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
+#define LB1_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
+#define LB1_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
+#define LB1_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
+#define LB1_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
+#define LB1_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
+#define LB1_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
+#define LB1_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
+//LB1_LB_BUFFER_URGENCY_CTRL
+#define LB1_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
+#define LB1_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
+#define LB1_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
+#define LB1_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
+//LB1_LB_BUFFER_URGENCY_STATUS
+#define LB1_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
+#define LB1_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
+#define LB1_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
+#define LB1_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
+//LB1_LB_BUFFER_STATUS
+#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
+#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
+#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
+#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
+#define LB1_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
+#define LB1_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
+#define LB1_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
+#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
+#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
+#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
+#define LB1_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
+#define LB1_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
+#define LB1_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
+#define LB1_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
+//LB1_LB_NO_OUTSTANDING_REQ_STATUS
+#define LB1_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
+#define LB1_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
+//LB1_MVP_AFR_FLIP_MODE
+#define LB1_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
+#define LB1_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L
+//LB1_MVP_AFR_FLIP_FIFO_CNTL
+#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
+#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
+#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
+#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
+#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000FL
+#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L
+#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L
+#define LB1_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L
+//LB1_MVP_FLIP_LINE_NUM_INSERT
+#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
+#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
+#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
+#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
+#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L
+#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007FFF00L
+#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3F000000L
+#define LB1_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L
+//LB1_DC_MVP_LB_CONTROL
+#define LB1_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
+#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
+#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
+#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
+#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
+#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
+#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
+#define LB1_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L
+#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L
+#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L
+#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L
+#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L
+#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L
+#define LB1_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L
+
+
+// addressBlock: dce_dc_dcfe1_dispdec
+//DCFE1_DCFE_CLOCK_CONTROL
+#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
+#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
+#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
+#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf
+#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT 0x11
+#define DCFE1_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
+#define DCFE1_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
+#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L
+#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L
+#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L
+#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x00008000L
+#define DCFE1_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK 0x00020000L
+#define DCFE1_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1F000000L
+#define DCFE1_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000L
+//DCFE1_DCFE_SOFT_RESET
+#define DCFE1_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
+#define DCFE1_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
+#define DCFE1_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
+#define DCFE1_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
+#define DCFE1_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
+#define DCFE1_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5
+#define DCFE1_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
+#define DCFE1_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x00000002L
+#define DCFE1_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x00000004L
+#define DCFE1_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x00000008L
+#define DCFE1_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
+#define DCFE1_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x00000020L
+//DCFE1_DCFE_MEM_PWR_CTRL
+#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
+#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
+#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
+#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
+#define DCFE1_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
+#define DCFE1_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
+#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
+#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
+#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x00000003L
+#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x00000004L
+#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x00000018L
+#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x00000020L
+#define DCFE1_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
+#define DCFE1_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x00000100L
+#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x00000600L
+#define DCFE1_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x00000800L
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x00003000L
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x00004000L
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x00018000L
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x00020000L
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0x000C0000L
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x00100000L
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x00600000L
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x00800000L
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x03000000L
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x04000000L
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000L
+#define DCFE1_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000L
+//DCFE1_DCFE_MEM_PWR_CTRL2
+#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
+#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
+#define DCFE1_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
+#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
+#define DCFE1_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
+#define DCFE1_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
+#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
+#define DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
+#define DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
+#define DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
+#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
+#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
+#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x00000003L
+#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
+#define DCFE1_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
+#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0x000000C0L
+#define DCFE1_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x00000300L
+#define DCFE1_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0x00000C00L
+#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x00003000L
+#define DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0x0000C000L
+#define DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x00030000L
+#define DCFE1_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x00040000L
+#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x00600000L
+#define DCFE1_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x00800000L
+//DCFE1_DCFE_MEM_PWR_STATUS
+#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
+#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
+#define DCFE1_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
+#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
+#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
+#define DCFE1_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
+#define DCFE1_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
+#define DCFE1_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
+#define DCFE1_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
+#define DCFE1_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
+#define DCFE1_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
+#define DCFE1_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
+#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x00000003L
+#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0x0000000CL
+#define DCFE1_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x00000030L
+#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0x000000C0L
+#define DCFE1_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x00000300L
+#define DCFE1_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0x00000C00L
+#define DCFE1_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x00003000L
+#define DCFE1_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0x0000C000L
+#define DCFE1_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x00030000L
+#define DCFE1_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0x000C0000L
+#define DCFE1_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x00300000L
+#define DCFE1_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0x00C00000L
+//DCFE1_DCFE_MISC
+#define DCFE1_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
+#define DCFE1_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
+//DCFE1_DCFE_FLUSH
+#define DCFE1_DCFE_FLUSH__FLUSH_OCCURED__SHIFT 0x0
+#define DCFE1_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
+#define DCFE1_DCFE_FLUSH__FLUSH_DEEP__SHIFT 0x2
+#define DCFE1_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
+#define DCFE1_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
+#define DCFE1_DCFE_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
+#define DCFE1_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
+#define DCFE1_DCFE_FLUSH__FLUSH_DEEP_MASK 0x00000004L
+#define DCFE1_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
+#define DCFE1_DCFE_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
+
+
+// addressBlock: dce_dc_dc_perfmon4_dispdec
+//DC_PERFMON4_PERFCOUNTER_CNTL
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON4_PERFCOUNTER_CNTL2
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON4_PERFCOUNTER_STATE
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON4_PERFMON_CNTL
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON4_PERFMON_CNTL2
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON4_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON4_PERFMON_CVALUE_LOW
+#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON4_PERFMON_HI
+#define DC_PERFMON4_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON4_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON4_PERFMON_LOW
+#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dmif_pg1_dispdec
+//DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1
+#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
+#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
+//DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2
+#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
+#define DMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
+//DMIF_PG1_DPG_WATERMARK_MASK_CONTROL
+#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x4
+#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT 0xc
+#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0xf
+#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x12
+#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT 0x13
+#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT 0x14
+#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000007L
+#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000070L
+#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000700L
+#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK 0x00007000L
+#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00038000L
+#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x00040000L
+#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK 0x00080000L
+#define DMIF_PG1_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK 0x3FF00000L
+//DMIF_PG1_DPG_PIPE_URGENCY_CONTROL
+#define DMIF_PG1_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+#define DMIF_PG1_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+#define DMIF_PG1_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
+#define DMIF_PG1_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
+//DMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL
+#define DMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT 0x0
+#define DMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT 0x10
+#define DMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK 0x0000FFFFL
+#define DMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK 0xFFFF0000L
+//DMIF_PG1_DPG_PIPE_STUTTER_CONTROL
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT 0x10
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x14
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x15
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x16
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x17
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x1a
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x1b
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK 0x00010000L
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00100000L
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00200000L
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00400000L
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00800000L
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x04000000L
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x08000000L
+//DMIF_PG1_DPG_PIPE_STUTTER_CONTROL2
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x0
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT 0x10
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0x0000FFFFL
+#define DMIF_PG1_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
+//DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL
+#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT 0x0
+#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT 0x1
+#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT 0xf
+#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK 0x00000001L
+#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK 0x00000002L
+#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
+#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
+#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
+#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
+#define DMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK 0xFFFF8000L
+//DMIF_PG1_DPG_REPEATER_PROGRAM
+#define DMIF_PG1_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+#define DMIF_PG1_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+#define DMIF_PG1_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
+#define DMIF_PG1_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
+//DMIF_PG1_DPG_CHK_PRE_PROC_CNTL
+#define DMIF_PG1_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+#define DMIF_PG1_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
+//DMIF_PG1_DPG_DVMM_STATUS
+#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT 0x0
+#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT 0x1
+#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT 0x4
+#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT 0x5
+#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK 0x00000001L
+#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK 0x00000002L
+#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK 0x00000010L
+#define DMIF_PG1_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK 0x00000020L
+
+
+// addressBlock: dce_dc_scl1_dispdec
+//SCL1_SCL_COEF_RAM_SELECT
+#define SCL1_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define SCL1_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
+#define SCL1_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
+#define SCL1_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000FL
+#define SCL1_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000F00L
+#define SCL1_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00070000L
+//SCL1_SCL_COEF_RAM_TAP_DATA
+#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+#define SCL1_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+//SCL1_SCL_MODE
+#define SCL1_SCL_MODE__SCL_MODE__SHIFT 0x0
+#define SCL1_SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
+#define SCL1_SCL_MODE__SCL_MODE_MASK 0x00000003L
+#define SCL1_SCL_MODE__SCL_PSCL_EN_MASK 0x00000010L
+//SCL1_SCL_TAP_CONTROL
+#define SCL1_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
+#define SCL1_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
+#define SCL1_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
+#define SCL1_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000F00L
+//SCL1_SCL_CONTROL
+#define SCL1_SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+#define SCL1_SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
+#define SCL1_SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+#define SCL1_SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
+//SCL1_SCL_BYPASS_CONTROL
+#define SCL1_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
+#define SCL1_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L
+//SCL1_SCL_MANUAL_REPLICATE_CONTROL
+#define SCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+#define SCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+#define SCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+#define SCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+//SCL1_SCL_AUTOMATIC_MODE_CONTROL
+#define SCL1_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
+#define SCL1_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
+#define SCL1_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
+#define SCL1_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
+//SCL1_SCL_HORZ_FILTER_CONTROL
+#define SCL1_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
+#define SCL1_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCL1_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L
+#define SCL1_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+//SCL1_SCL_HORZ_FILTER_SCALE_RATIO
+#define SCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+#define SCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+//SCL1_SCL_HORZ_FILTER_INIT
+#define SCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+#define SCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+#define SCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+#define SCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+//SCL1_SCL_VERT_FILTER_CONTROL
+#define SCL1_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
+#define SCL1_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCL1_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L
+#define SCL1_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+//SCL1_SCL_VERT_FILTER_SCALE_RATIO
+#define SCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+#define SCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+//SCL1_SCL_VERT_FILTER_INIT
+#define SCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+#define SCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+#define SCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+#define SCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
+//SCL1_SCL_VERT_FILTER_INIT_BOT
+#define SCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+#define SCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+#define SCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+#define SCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
+//SCL1_SCL_ROUND_OFFSET
+#define SCL1_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
+#define SCL1_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+#define SCL1_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
+#define SCL1_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
+//SCL1_SCL_UPDATE
+#define SCL1_SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+#define SCL1_SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
+#define SCL1_SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
+#define SCL1_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
+#define SCL1_SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+#define SCL1_SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
+#define SCL1_SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
+#define SCL1_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
+//SCL1_SCL_F_SHARP_CONTROL
+#define SCL1_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
+#define SCL1_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
+#define SCL1_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
+#define SCL1_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
+#define SCL1_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L
+#define SCL1_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L
+#define SCL1_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L
+#define SCL1_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L
+//SCL1_SCL_ALU_CONTROL
+#define SCL1_SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
+#define SCL1_SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
+//SCL1_SCL_COEF_RAM_CONFLICT_STATUS
+#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
+#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
+#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
+#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
+#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
+#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L
+#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L
+#define SCL1_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
+//SCL1_VIEWPORT_START_SECONDARY
+#define SCL1_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
+#define SCL1_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
+#define SCL1_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
+#define SCL1_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
+//SCL1_VIEWPORT_START
+#define SCL1_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
+#define SCL1_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
+#define SCL1_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
+#define SCL1_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
+//SCL1_VIEWPORT_SIZE
+#define SCL1_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
+#define SCL1_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
+#define SCL1_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003FFFL
+#define SCL1_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3FFF0000L
+//SCL1_EXT_OVERSCAN_LEFT_RIGHT
+#define SCL1_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+#define SCL1_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+#define SCL1_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+#define SCL1_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+//SCL1_EXT_OVERSCAN_TOP_BOTTOM
+#define SCL1_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+#define SCL1_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+#define SCL1_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+#define SCL1_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+//SCL1_SCL_MODE_CHANGE_DET1
+#define SCL1_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
+#define SCL1_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
+#define SCL1_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
+#define SCL1_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
+#define SCL1_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
+#define SCL1_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
+//SCL1_SCL_MODE_CHANGE_DET2
+#define SCL1_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
+#define SCL1_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
+//SCL1_SCL_MODE_CHANGE_DET3
+#define SCL1_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
+#define SCL1_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
+#define SCL1_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
+#define SCL1_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
+//SCL1_SCL_MODE_CHANGE_MASK
+#define SCL1_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
+#define SCL1_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_blnd1_dispdec
+//BLND1_BLND_CONTROL
+#define BLND1_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
+#define BLND1_BLND_CONTROL__BLND_MODE__SHIFT 0x8
+#define BLND1_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
+#define BLND1_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
+#define BLND1_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
+#define BLND1_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
+#define BLND1_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
+#define BLND1_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
+#define BLND1_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
+#define BLND1_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
+#define BLND1_BLND_CONTROL__BLND_MODE_MASK 0x00000300L
+#define BLND1_BLND_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
+#define BLND1_BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
+#define BLND1_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
+#define BLND1_BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
+#define BLND1_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
+#define BLND1_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
+#define BLND1_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
+//BLND1_BLND_SM_CONTROL2
+#define BLND1_BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0
+#define BLND1_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
+#define BLND1_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
+#define BLND1_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+#define BLND1_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+#define BLND1_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
+#define BLND1_BLND_SM_CONTROL2__SM_MODE_MASK 0x00000007L
+#define BLND1_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
+#define BLND1_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
+#define BLND1_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+#define BLND1_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+#define BLND1_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
+//BLND1_BLND_CONTROL2
+#define BLND1_BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
+#define BLND1_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
+#define BLND1_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
+#define BLND1_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
+#define BLND1_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
+#define BLND1_BLND_CONTROL2__PTI_ENABLE_MASK 0x00000001L
+#define BLND1_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
+#define BLND1_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
+#define BLND1_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
+#define BLND1_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
+//BLND1_BLND_UPDATE
+#define BLND1_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
+#define BLND1_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
+#define BLND1_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
+#define BLND1_BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
+#define BLND1_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
+#define BLND1_BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
+//BLND1_BLND_UNDERFLOW_INTERRUPT
+#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
+#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
+#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
+#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
+#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
+#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
+#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
+#define BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
+//BLND1_BLND_V_UPDATE_LOCK
+#define BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
+#define BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
+#define BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
+#define BLND1_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
+#define BLND1_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
+#define BLND1_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
+#define BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
+#define BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
+#define BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
+#define BLND1_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
+#define BLND1_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
+#define BLND1_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
+//BLND1_BLND_REG_UPDATE_STATUS
+#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
+#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
+#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
+#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
+#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
+#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
+#define BLND1_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
+#define BLND1_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
+#define BLND1_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
+#define BLND1_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
+#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
+#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
+#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
+#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
+#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
+#define BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
+#define BLND1_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
+#define BLND1_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
+#define BLND1_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
+#define BLND1_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
+
+
+// addressBlock: dce_dc_crtc1_dispdec
+//CRTC1_CRTC_H_BLANK_EARLY_NUM
+#define CRTC1_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
+#define CRTC1_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
+#define CRTC1_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
+#define CRTC1_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
+//CRTC1_CRTC_H_TOTAL
+#define CRTC1_CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
+#define CRTC1_CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
+//CRTC1_CRTC_H_BLANK_START_END
+#define CRTC1_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
+#define CRTC1_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
+#define CRTC1_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
+#define CRTC1_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
+//CRTC1_CRTC_H_SYNC_A
+#define CRTC1_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
+#define CRTC1_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
+#define CRTC1_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
+#define CRTC1_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
+//CRTC1_CRTC_H_SYNC_A_CNTL
+#define CRTC1_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
+#define CRTC1_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
+#define CRTC1_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
+#define CRTC1_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
+#define CRTC1_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
+#define CRTC1_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
+//CRTC1_CRTC_H_SYNC_B
+#define CRTC1_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
+#define CRTC1_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
+#define CRTC1_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
+#define CRTC1_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
+//CRTC1_CRTC_H_SYNC_B_CNTL
+#define CRTC1_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
+#define CRTC1_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
+#define CRTC1_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
+#define CRTC1_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
+#define CRTC1_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
+#define CRTC1_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
+//CRTC1_CRTC_VBI_END
+#define CRTC1_CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
+#define CRTC1_CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
+#define CRTC1_CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
+#define CRTC1_CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
+//CRTC1_CRTC_V_TOTAL
+#define CRTC1_CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
+#define CRTC1_CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
+//CRTC1_CRTC_V_TOTAL_MIN
+#define CRTC1_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
+#define CRTC1_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
+//CRTC1_CRTC_V_TOTAL_MAX
+#define CRTC1_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
+#define CRTC1_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
+#define CRTC1_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
+#define CRTC1_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
+//CRTC1_CRTC_V_TOTAL_CONTROL
+#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
+#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
+#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
+#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
+#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
+#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
+#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
+#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
+#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
+#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
+#define CRTC1_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+//CRTC1_CRTC_V_TOTAL_INT_STATUS
+#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+#define CRTC1_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+//CRTC1_CRTC_VSYNC_NOM_INT_STATUS
+#define CRTC1_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
+#define CRTC1_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+#define CRTC1_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
+#define CRTC1_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+//CRTC1_CRTC_V_BLANK_START_END
+#define CRTC1_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
+#define CRTC1_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
+#define CRTC1_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
+#define CRTC1_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
+//CRTC1_CRTC_V_SYNC_A
+#define CRTC1_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
+#define CRTC1_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
+#define CRTC1_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
+#define CRTC1_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
+//CRTC1_CRTC_V_SYNC_A_CNTL
+#define CRTC1_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
+#define CRTC1_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
+//CRTC1_CRTC_V_SYNC_B
+#define CRTC1_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
+#define CRTC1_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
+#define CRTC1_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
+#define CRTC1_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
+//CRTC1_CRTC_V_SYNC_B_CNTL
+#define CRTC1_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
+#define CRTC1_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
+//CRTC1_CRTC_DTMTEST_CNTL
+#define CRTC1_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
+#define CRTC1_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
+#define CRTC1_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
+#define CRTC1_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
+//CRTC1_CRTC_DTMTEST_STATUS_POSITION
+#define CRTC1_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
+#define CRTC1_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
+#define CRTC1_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
+#define CRTC1_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTC1_CRTC_TRIGA_CNTL
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
+#define CRTC1_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
+//CRTC1_CRTC_TRIGA_MANUAL_TRIG
+#define CRTC1_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
+#define CRTC1_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+//CRTC1_CRTC_TRIGB_CNTL
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
+#define CRTC1_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
+//CRTC1_CRTC_TRIGB_MANUAL_TRIG
+#define CRTC1_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
+#define CRTC1_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+//CRTC1_CRTC_FORCE_COUNT_NOW_CNTL
+#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+#define CRTC1_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+//CRTC1_CRTC_FLOW_CONTROL
+#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
+#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+#define CRTC1_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+//CRTC1_CRTC_STEREO_FORCE_NEXT_EYE
+#define CRTC1_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+#define CRTC1_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+#define CRTC1_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
+#define CRTC1_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+#define CRTC1_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+#define CRTC1_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+//CRTC1_CRTC_AVSYNC_COUNTER
+#define CRTC1_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
+#define CRTC1_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
+//CRTC1_CRTC_CONTROL
+#define CRTC1_CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTC1_CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
+#define CRTC1_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
+#define CRTC1_CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
+#define CRTC1_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
+#define CRTC1_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
+#define CRTC1_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+#define CRTC1_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
+#define CRTC1_CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
+#define CRTC1_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+#define CRTC1_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+#define CRTC1_CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
+#define CRTC1_CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
+#define CRTC1_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
+#define CRTC1_CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
+#define CRTC1_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
+#define CRTC1_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+#define CRTC1_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+#define CRTC1_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
+#define CRTC1_CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
+#define CRTC1_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+#define CRTC1_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+//CRTC1_CRTC_BLANK_CONTROL
+#define CRTC1_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
+#define CRTC1_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
+#define CRTC1_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
+#define CRTC1_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
+#define CRTC1_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
+#define CRTC1_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
+//CRTC1_CRTC_INTERLACE_CONTROL
+#define CRTC1_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
+#define CRTC1_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+#define CRTC1_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
+#define CRTC1_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+//CRTC1_CRTC_INTERLACE_STATUS
+#define CRTC1_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+#define CRTC1_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
+#define CRTC1_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+#define CRTC1_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+//CRTC1_CRTC_FIELD_INDICATION_CONTROL
+#define CRTC1_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
+#define CRTC1_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
+#define CRTC1_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
+#define CRTC1_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
+//CRTC1_CRTC_PIXEL_DATA_READBACK0
+#define CRTC1_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+#define CRTC1_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+#define CRTC1_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
+#define CRTC1_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
+//CRTC1_CRTC_PIXEL_DATA_READBACK1
+#define CRTC1_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
+#define CRTC1_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
+//CRTC1_CRTC_STATUS
+#define CRTC1_CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
+#define CRTC1_CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
+#define CRTC1_CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
+#define CRTC1_CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
+#define CRTC1_CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
+#define CRTC1_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+#define CRTC1_CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
+#define CRTC1_CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
+#define CRTC1_CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
+#define CRTC1_CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L
+#define CRTC1_CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
+#define CRTC1_CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
+#define CRTC1_CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
+#define CRTC1_CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
+#define CRTC1_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+#define CRTC1_CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L
+#define CRTC1_CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
+#define CRTC1_CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
+//CRTC1_CRTC_STATUS_POSITION
+#define CRTC1_CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
+#define CRTC1_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
+#define CRTC1_CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
+#define CRTC1_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTC1_CRTC_NOM_VERT_POSITION
+#define CRTC1_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
+#define CRTC1_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
+//CRTC1_CRTC_STATUS_FRAME_COUNT
+#define CRTC1_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
+#define CRTC1_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
+//CRTC1_CRTC_STATUS_VF_COUNT
+#define CRTC1_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
+#define CRTC1_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
+//CRTC1_CRTC_STATUS_HV_COUNT
+#define CRTC1_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
+#define CRTC1_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
+//CRTC1_CRTC_COUNT_CONTROL
+#define CRTC1_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
+#define CRTC1_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
+#define CRTC1_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+#define CRTC1_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+//CRTC1_CRTC_COUNT_RESET
+#define CRTC1_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
+#define CRTC1_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
+//CRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define CRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+#define CRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+//CRTC1_CRTC_VERT_SYNC_CONTROL
+#define CRTC1_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+#define CRTC1_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+#define CRTC1_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+#define CRTC1_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+#define CRTC1_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+#define CRTC1_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+//CRTC1_CRTC_STEREO_STATUS
+#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
+#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
+#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
+#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
+#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
+#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
+#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
+#define CRTC1_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+//CRTC1_CRTC_STEREO_CONTROL
+#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
+#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+#define CRTC1_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+#define CRTC1_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
+#define CRTC1_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
+#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
+#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
+#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+#define CRTC1_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+#define CRTC1_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
+#define CRTC1_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+#define CRTC1_CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
+//CRTC1_CRTC_SNAPSHOT_STATUS
+#define CRTC1_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
+#define CRTC1_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
+#define CRTC1_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+#define CRTC1_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
+#define CRTC1_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
+#define CRTC1_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+//CRTC1_CRTC_SNAPSHOT_CONTROL
+#define CRTC1_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+#define CRTC1_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+//CRTC1_CRTC_SNAPSHOT_POSITION
+#define CRTC1_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+#define CRTC1_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+#define CRTC1_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
+#define CRTC1_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTC1_CRTC_SNAPSHOT_FRAME
+#define CRTC1_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+#define CRTC1_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+//CRTC1_CRTC_START_LINE_CONTROL
+#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
+#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
+#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
+#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
+#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
+#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
+#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
+#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
+#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
+#define CRTC1_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
+//CRTC1_CRTC_INTERRUPT_CONTROL
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+#define CRTC1_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+//CRTC1_CRTC_UPDATE_LOCK
+#define CRTC1_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
+#define CRTC1_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
+//CRTC1_CRTC_DOUBLE_BUFFER_CONTROL
+#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
+#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
+#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
+#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
+#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
+#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
+#define CRTC1_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
+//CRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE
+#define CRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
+#define CRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
+//CRTC1_CRTC_TEST_PATTERN_CONTROL
+#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
+#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
+#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
+#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
+#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
+#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
+#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
+#define CRTC1_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
+//CRTC1_CRTC_TEST_PATTERN_PARAMETERS
+#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
+#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
+#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
+#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
+#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
+#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
+#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
+#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
+#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
+#define CRTC1_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
+//CRTC1_CRTC_TEST_PATTERN_COLOR
+#define CRTC1_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
+#define CRTC1_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
+#define CRTC1_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
+#define CRTC1_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
+//CRTC1_CRTC_MASTER_UPDATE_LOCK
+#define CRTC1_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
+#define CRTC1_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
+#define CRTC1_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
+#define CRTC1_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
+#define CRTC1_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
+#define CRTC1_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
+//CRTC1_CRTC_MASTER_UPDATE_MODE
+#define CRTC1_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
+#define CRTC1_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
+#define CRTC1_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
+#define CRTC1_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
+//CRTC1_CRTC_MVP_INBAND_CNTL_INSERT
+#define CRTC1_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
+#define CRTC1_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
+#define CRTC1_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
+#define CRTC1_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
+//CRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER
+#define CRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
+#define CRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
+//CRTC1_CRTC_MVP_STATUS
+#define CRTC1_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
+#define CRTC1_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
+#define CRTC1_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
+#define CRTC1_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
+#define CRTC1_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
+#define CRTC1_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
+#define CRTC1_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
+#define CRTC1_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
+//CRTC1_CRTC_MASTER_EN
+#define CRTC1_CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTC1_CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
+//CRTC1_CRTC_ALLOW_STOP_OFF_V_CNT
+#define CRTC1_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
+#define CRTC1_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
+#define CRTC1_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
+#define CRTC1_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
+//CRTC1_CRTC_V_UPDATE_INT_STATUS
+#define CRTC1_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
+#define CRTC1_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
+#define CRTC1_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
+#define CRTC1_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
+//CRTC1_CRTC_OVERSCAN_COLOR
+#define CRTC1_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
+#define CRTC1_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
+#define CRTC1_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
+#define CRTC1_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
+#define CRTC1_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
+#define CRTC1_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
+//CRTC1_CRTC_OVERSCAN_COLOR_EXT
+#define CRTC1_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
+#define CRTC1_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
+#define CRTC1_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
+#define CRTC1_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
+#define CRTC1_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
+#define CRTC1_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
+//CRTC1_CRTC_BLANK_DATA_COLOR
+#define CRTC1_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+#define CRTC1_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+#define CRTC1_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+#define CRTC1_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+#define CRTC1_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+#define CRTC1_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+//CRTC1_CRTC_BLANK_DATA_COLOR_EXT
+#define CRTC1_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+#define CRTC1_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+#define CRTC1_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+#define CRTC1_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
+#define CRTC1_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
+#define CRTC1_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
+//CRTC1_CRTC_BLACK_COLOR
+#define CRTC1_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
+#define CRTC1_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
+#define CRTC1_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
+#define CRTC1_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
+#define CRTC1_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+#define CRTC1_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+//CRTC1_CRTC_BLACK_COLOR_EXT
+#define CRTC1_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+#define CRTC1_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+#define CRTC1_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+#define CRTC1_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
+#define CRTC1_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
+#define CRTC1_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
+//CRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION
+#define CRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+#define CRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+#define CRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
+#define CRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
+//CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL
+#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+#define CRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+//CRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION
+#define CRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+#define CRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
+//CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL
+#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+#define CRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+//CRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION
+#define CRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+#define CRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
+//CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL
+#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+#define CRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+//CRTC1_CRTC_CRC_CNTL
+#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
+#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
+#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
+#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
+#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
+#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
+#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
+#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
+#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
+#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
+#define CRTC1_CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
+//CRTC1_CRTC_CRC0_WINDOWA_X_CONTROL
+#define CRTC1_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
+#define CRTC1_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
+#define CRTC1_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
+#define CRTC1_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
+//CRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL
+#define CRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
+#define CRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
+#define CRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
+#define CRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
+//CRTC1_CRTC_CRC0_WINDOWB_X_CONTROL
+#define CRTC1_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
+#define CRTC1_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
+#define CRTC1_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
+#define CRTC1_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
+//CRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL
+#define CRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
+#define CRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
+#define CRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
+#define CRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
+//CRTC1_CRTC_CRC0_DATA_RG
+#define CRTC1_CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+#define CRTC1_CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+#define CRTC1_CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+#define CRTC1_CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+//CRTC1_CRTC_CRC0_DATA_B
+#define CRTC1_CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+#define CRTC1_CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+//CRTC1_CRTC_CRC1_WINDOWA_X_CONTROL
+#define CRTC1_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
+#define CRTC1_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
+#define CRTC1_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
+#define CRTC1_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
+//CRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL
+#define CRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
+#define CRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
+#define CRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
+#define CRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
+//CRTC1_CRTC_CRC1_WINDOWB_X_CONTROL
+#define CRTC1_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
+#define CRTC1_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
+#define CRTC1_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
+#define CRTC1_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
+//CRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL
+#define CRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
+#define CRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
+#define CRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
+#define CRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
+//CRTC1_CRTC_CRC1_DATA_RG
+#define CRTC1_CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+#define CRTC1_CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+#define CRTC1_CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+#define CRTC1_CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+//CRTC1_CRTC_CRC1_DATA_B
+#define CRTC1_CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+#define CRTC1_CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+//CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
+//CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START
+#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
+#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
+#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
+#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
+//CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END
+#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
+#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
+#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
+#define CRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
+//CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
+#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
+#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
+#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
+#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
+#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
+#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
+#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
+//CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL
+#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
+#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
+#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
+#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
+#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
+#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
+//CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
+#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
+#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
+#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
+#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
+#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
+#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
+#define CRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
+//CRTC1_CRTC_STATIC_SCREEN_CONTROL
+#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
+#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
+#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
+#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
+#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
+#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
+#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
+#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
+#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
+#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
+#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
+#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
+#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
+#define CRTC1_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
+//CRTC1_CRTC_3D_STRUCTURE_CONTROL
+#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
+#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
+#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
+#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
+#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+#define CRTC1_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+//CRTC1_CRTC_GSL_VSYNC_GAP
+#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
+#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+#define CRTC1_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
+//CRTC1_CRTC_GSL_WINDOW
+#define CRTC1_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
+#define CRTC1_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
+#define CRTC1_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
+#define CRTC1_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
+//CRTC1_CRTC_GSL_CONTROL
+#define CRTC1_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
+#define CRTC1_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
+#define CRTC1_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+#define CRTC1_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
+#define CRTC1_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
+#define CRTC1_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+//CRTC1_CRTC_RANGE_TIMING_INT_STATUS
+#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
+#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
+#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
+#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
+#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
+#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
+#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
+#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
+#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
+#define CRTC1_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
+//CRTC1_CRTC_DRR_CONTROL
+#define CRTC1_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY__SHIFT 0x0
+#define CRTC1_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0xe
+#define CRTC1_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS__SHIFT 0x1c
+#define CRTC1_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE__SHIFT 0x1d
+#define CRTC1_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY_MASK 0x00003FFFL
+#define CRTC1_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR_MASK 0x0FFFC000L
+#define CRTC1_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS_MASK 0x10000000L
+#define CRTC1_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE_MASK 0x60000000L
+
+
+// addressBlock: dce_dc_fmt1_dispdec
+//FMT1_FMT_CLAMP_COMPONENT_R
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
+//FMT1_FMT_CLAMP_COMPONENT_G
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
+//FMT1_FMT_CLAMP_COMPONENT_B
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
+//FMT1_FMT_DYNAMIC_EXP_CNTL
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
+//FMT1_FMT_CONTROL
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
+#define FMT1_FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
+#define FMT1_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED__SHIFT 0x1e
+#define FMT1_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR__SHIFT 0x1f
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
+#define FMT1_FMT_CONTROL__FMT_SRC_SELECT_MASK 0x07000000L
+#define FMT1_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_MASK 0x40000000L
+#define FMT1_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR_MASK 0x80000000L
+//FMT1_FMT_BIT_DEPTH_CONTROL
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
+//FMT1_FMT_DITHER_RAND_R_SEED
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
+//FMT1_FMT_DITHER_RAND_G_SEED
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
+//FMT1_FMT_DITHER_RAND_B_SEED
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
+//FMT1_FMT_CLAMP_CNTL
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
+//FMT1_FMT_CRC_CNTL
+#define FMT1_FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
+#define FMT1_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
+#define FMT1_FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
+#define FMT1_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5
+#define FMT1_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6
+#define FMT1_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
+#define FMT1_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9
+#define FMT1_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
+#define FMT1_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+#define FMT1_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
+#define FMT1_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
+#define FMT1_FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L
+#define FMT1_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x00000002L
+#define FMT1_FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L
+#define FMT1_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x00000020L
+#define FMT1_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x00000040L
+#define FMT1_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x00000100L
+#define FMT1_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x00000200L
+#define FMT1_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define FMT1_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+#define FMT1_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L
+#define FMT1_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L
+//FMT1_FMT_CRC_SIG_RED_GREEN_MASK
+#define FMT1_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
+#define FMT1_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
+#define FMT1_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
+#define FMT1_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
+//FMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK
+#define FMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
+#define FMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
+#define FMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
+#define FMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
+//FMT1_FMT_CRC_SIG_RED_GREEN
+#define FMT1_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
+#define FMT1_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
+#define FMT1_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000FFFFL
+#define FMT1_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xFFFF0000L
+//FMT1_FMT_CRC_SIG_BLUE_CONTROL
+#define FMT1_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
+#define FMT1_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
+#define FMT1_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000FFFFL
+#define FMT1_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xFFFF0000L
+//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
+//FMT1_FMT_420_HBLANK_EARLY_START
+#define FMT1_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START__SHIFT 0x0
+#define FMT1_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START_MASK 0x00000FFFL
+
+
+// addressBlock: dce_dc_dcp2_dispdec
+//DCP2_GRPH_ENABLE
+#define DCP2_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
+#define DCP2_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1
+#define DCP2_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
+#define DCP2_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x00000002L
+//DCP2_GRPH_CONTROL
+#define DCP2_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
+#define DCP2_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT 0x2
+#define DCP2_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
+#define DCP2_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT 0x6
+#define DCP2_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
+#define DCP2_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0xc
+#define DCP2_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+#define DCP2_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+#define DCP2_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT 0x12
+#define DCP2_GRPH_CONTROL__GRPH_SW_MODE__SHIFT 0x14
+#define DCP2_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT 0x1c
+#define DCP2_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
+#define DCP2_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
+#define DCP2_GRPH_CONTROL__GRPH_SE_ENABLE_MASK 0x00000004L
+#define DCP2_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
+#define DCP2_GRPH_CONTROL__GRPH_DIM_TYPE_MASK 0x000000C0L
+#define DCP2_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
+#define DCP2_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x00007000L
+#define DCP2_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
+#define DCP2_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
+#define DCP2_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK 0x000C0000L
+#define DCP2_GRPH_CONTROL__GRPH_SW_MODE_MASK 0x01F00000L
+#define DCP2_GRPH_CONTROL__GRPH_NUM_PIPES_MASK 0x70000000L
+#define DCP2_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
+//DCP2_GRPH_LUT_10BIT_BYPASS
+#define DCP2_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
+#define DCP2_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
+#define DCP2_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L
+#define DCP2_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L
+//DCP2_GRPH_SWAP_CNTL
+#define DCP2_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
+#define DCP2_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
+#define DCP2_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
+#define DCP2_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
+#define DCP2_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
+#define DCP2_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
+#define DCP2_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
+#define DCP2_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
+#define DCP2_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
+#define DCP2_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000C00L
+//DCP2_GRPH_PRIMARY_SURFACE_ADDRESS
+#define DCP2_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
+#define DCP2_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP2_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L
+#define DCP2_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP2_GRPH_SECONDARY_SURFACE_ADDRESS
+#define DCP2_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
+#define DCP2_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP2_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L
+#define DCP2_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP2_GRPH_PITCH
+#define DCP2_GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
+#define DCP2_GRPH_PITCH__GRPH_PITCH_MASK 0x00007FFFL
+//DCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+#define DCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+#define DCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP2_GRPH_SURFACE_OFFSET_X
+#define DCP2_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
+#define DCP2_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003FFFL
+//DCP2_GRPH_SURFACE_OFFSET_Y
+#define DCP2_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
+#define DCP2_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003FFFL
+//DCP2_GRPH_X_START
+#define DCP2_GRPH_X_START__GRPH_X_START__SHIFT 0x0
+#define DCP2_GRPH_X_START__GRPH_X_START_MASK 0x00003FFFL
+//DCP2_GRPH_Y_START
+#define DCP2_GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
+#define DCP2_GRPH_Y_START__GRPH_Y_START_MASK 0x00003FFFL
+//DCP2_GRPH_X_END
+#define DCP2_GRPH_X_END__GRPH_X_END__SHIFT 0x0
+#define DCP2_GRPH_X_END__GRPH_X_END_MASK 0x00007FFFL
+//DCP2_GRPH_Y_END
+#define DCP2_GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
+#define DCP2_GRPH_Y_END__GRPH_Y_END_MASK 0x00007FFFL
+//DCP2_INPUT_GAMMA_CONTROL
+#define DCP2_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
+#define DCP2_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000001L
+//DCP2_GRPH_UPDATE
+#define DCP2_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
+#define DCP2_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
+#define DCP2_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
+#define DCP2_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
+#define DCP2_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT 0x8
+#define DCP2_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT 0x9
+#define DCP2_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT 0xa
+#define DCP2_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
+#define DCP2_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
+#define DCP2_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define DCP2_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
+#define DCP2_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
+#define DCP2_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
+#define DCP2_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
+#define DCP2_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
+#define DCP2_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK 0x00000100L
+#define DCP2_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK 0x00000200L
+#define DCP2_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK 0x00000400L
+#define DCP2_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
+#define DCP2_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
+#define DCP2_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+#define DCP2_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
+//DCP2_GRPH_FLIP_CONTROL
+#define DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
+#define DCP2_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
+#define DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4
+#define DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5
+#define DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L
+#define DCP2_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x00000002L
+#define DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x00000010L
+#define DCP2_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000020L
+//DCP2_GRPH_SURFACE_ADDRESS_INUSE
+#define DCP2_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
+#define DCP2_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xFFFFFF00L
+//DCP2_GRPH_DFQ_CONTROL
+#define DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
+#define DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
+#define DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
+#define DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L
+#define DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L
+#define DCP2_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L
+//DCP2_GRPH_DFQ_STATUS
+#define DCP2_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
+#define DCP2_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
+#define DCP2_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
+#define DCP2_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
+#define DCP2_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000FL
+#define DCP2_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000F0L
+#define DCP2_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L
+#define DCP2_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L
+//DCP2_GRPH_INTERRUPT_STATUS
+#define DCP2_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
+#define DCP2_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
+#define DCP2_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
+#define DCP2_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
+//DCP2_GRPH_INTERRUPT_CONTROL
+#define DCP2_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
+#define DCP2_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
+#define DCP2_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
+#define DCP2_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
+//DCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE
+#define DCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
+#define DCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000FFL
+//DCP2_GRPH_COMPRESS_SURFACE_ADDRESS
+#define DCP2_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP2_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP2_GRPH_COMPRESS_PITCH
+#define DCP2_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
+#define DCP2_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001FFC0L
+//DCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH
+#define DCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
+#define DCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0
+#define DCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0x000000FFL
+//DCP2_PRESCALE_GRPH_CONTROL
+#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
+#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
+#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
+#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
+#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
+#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L
+#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L
+#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L
+#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L
+#define DCP2_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L
+//DCP2_PRESCALE_VALUES_GRPH_R
+#define DCP2_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
+#define DCP2_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
+#define DCP2_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000FFFFL
+#define DCP2_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xFFFF0000L
+//DCP2_PRESCALE_VALUES_GRPH_G
+#define DCP2_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
+#define DCP2_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
+#define DCP2_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000FFFFL
+#define DCP2_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xFFFF0000L
+//DCP2_PRESCALE_VALUES_GRPH_B
+#define DCP2_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
+#define DCP2_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
+#define DCP2_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000FFFFL
+#define DCP2_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xFFFF0000L
+//DCP2_INPUT_CSC_CONTROL
+#define DCP2_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
+#define DCP2_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L
+//DCP2_INPUT_CSC_C11_C12
+#define DCP2_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
+#define DCP2_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
+#define DCP2_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000FFFFL
+#define DCP2_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xFFFF0000L
+//DCP2_INPUT_CSC_C13_C14
+#define DCP2_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
+#define DCP2_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
+#define DCP2_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000FFFFL
+#define DCP2_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xFFFF0000L
+//DCP2_INPUT_CSC_C21_C22
+#define DCP2_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
+#define DCP2_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
+#define DCP2_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000FFFFL
+#define DCP2_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xFFFF0000L
+//DCP2_INPUT_CSC_C23_C24
+#define DCP2_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
+#define DCP2_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
+#define DCP2_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000FFFFL
+#define DCP2_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xFFFF0000L
+//DCP2_INPUT_CSC_C31_C32
+#define DCP2_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
+#define DCP2_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
+#define DCP2_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000FFFFL
+#define DCP2_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xFFFF0000L
+//DCP2_INPUT_CSC_C33_C34
+#define DCP2_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
+#define DCP2_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
+#define DCP2_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000FFFFL
+#define DCP2_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xFFFF0000L
+//DCP2_OUTPUT_CSC_CONTROL
+#define DCP2_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
+#define DCP2_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L
+//DCP2_OUTPUT_CSC_C11_C12
+#define DCP2_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
+#define DCP2_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
+#define DCP2_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000FFFFL
+#define DCP2_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xFFFF0000L
+//DCP2_OUTPUT_CSC_C13_C14
+#define DCP2_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
+#define DCP2_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
+#define DCP2_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000FFFFL
+#define DCP2_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xFFFF0000L
+//DCP2_OUTPUT_CSC_C21_C22
+#define DCP2_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
+#define DCP2_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
+#define DCP2_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000FFFFL
+#define DCP2_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xFFFF0000L
+//DCP2_OUTPUT_CSC_C23_C24
+#define DCP2_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
+#define DCP2_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
+#define DCP2_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000FFFFL
+#define DCP2_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xFFFF0000L
+//DCP2_OUTPUT_CSC_C31_C32
+#define DCP2_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
+#define DCP2_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
+#define DCP2_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000FFFFL
+#define DCP2_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xFFFF0000L
+//DCP2_OUTPUT_CSC_C33_C34
+#define DCP2_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
+#define DCP2_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
+#define DCP2_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000FFFFL
+#define DCP2_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xFFFF0000L
+//DCP2_COMM_MATRIXA_TRANS_C11_C12
+#define DCP2_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
+#define DCP2_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
+#define DCP2_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000FFFFL
+#define DCP2_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xFFFF0000L
+//DCP2_COMM_MATRIXA_TRANS_C13_C14
+#define DCP2_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
+#define DCP2_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
+#define DCP2_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000FFFFL
+#define DCP2_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xFFFF0000L
+//DCP2_COMM_MATRIXA_TRANS_C21_C22
+#define DCP2_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
+#define DCP2_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
+#define DCP2_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000FFFFL
+#define DCP2_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xFFFF0000L
+//DCP2_COMM_MATRIXA_TRANS_C23_C24
+#define DCP2_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
+#define DCP2_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
+#define DCP2_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000FFFFL
+#define DCP2_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xFFFF0000L
+//DCP2_COMM_MATRIXA_TRANS_C31_C32
+#define DCP2_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
+#define DCP2_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
+#define DCP2_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000FFFFL
+#define DCP2_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xFFFF0000L
+//DCP2_COMM_MATRIXA_TRANS_C33_C34
+#define DCP2_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
+#define DCP2_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
+#define DCP2_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000FFFFL
+#define DCP2_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xFFFF0000L
+//DCP2_COMM_MATRIXB_TRANS_C11_C12
+#define DCP2_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
+#define DCP2_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
+#define DCP2_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000FFFFL
+#define DCP2_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xFFFF0000L
+//DCP2_COMM_MATRIXB_TRANS_C13_C14
+#define DCP2_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
+#define DCP2_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
+#define DCP2_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000FFFFL
+#define DCP2_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xFFFF0000L
+//DCP2_COMM_MATRIXB_TRANS_C21_C22
+#define DCP2_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
+#define DCP2_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
+#define DCP2_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000FFFFL
+#define DCP2_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xFFFF0000L
+//DCP2_COMM_MATRIXB_TRANS_C23_C24
+#define DCP2_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
+#define DCP2_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
+#define DCP2_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000FFFFL
+#define DCP2_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xFFFF0000L
+//DCP2_COMM_MATRIXB_TRANS_C31_C32
+#define DCP2_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
+#define DCP2_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
+#define DCP2_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000FFFFL
+#define DCP2_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xFFFF0000L
+//DCP2_COMM_MATRIXB_TRANS_C33_C34
+#define DCP2_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
+#define DCP2_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
+#define DCP2_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000FFFFL
+#define DCP2_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xFFFF0000L
+//DCP2_DENORM_CONTROL
+#define DCP2_DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
+#define DCP2_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
+#define DCP2_DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L
+#define DCP2_DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x00000010L
+//DCP2_OUT_ROUND_CONTROL
+#define DCP2_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
+#define DCP2_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000FL
+//DCP2_OUT_CLAMP_CONTROL_R_CR
+#define DCP2_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
+#define DCP2_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
+#define DCP2_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x00003FFFL
+#define DCP2_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3FFF0000L
+//DCP2_OUT_CLAMP_CONTROL_G_Y
+#define DCP2_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
+#define DCP2_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
+#define DCP2_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x00003FFFL
+#define DCP2_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3FFF0000L
+//DCP2_OUT_CLAMP_CONTROL_B_CB
+#define DCP2_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
+#define DCP2_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
+#define DCP2_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x00003FFFL
+#define DCP2_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3FFF0000L
+//DCP2_KEY_CONTROL
+#define DCP2_KEY_CONTROL__KEY_MODE__SHIFT 0x1
+#define DCP2_KEY_CONTROL__KEY_MODE_MASK 0x00000006L
+//DCP2_KEY_RANGE_ALPHA
+#define DCP2_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
+#define DCP2_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
+#define DCP2_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000FFFFL
+#define DCP2_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xFFFF0000L
+//DCP2_KEY_RANGE_RED
+#define DCP2_KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
+#define DCP2_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
+#define DCP2_KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000FFFFL
+#define DCP2_KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xFFFF0000L
+//DCP2_KEY_RANGE_GREEN
+#define DCP2_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
+#define DCP2_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
+#define DCP2_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000FFFFL
+#define DCP2_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xFFFF0000L
+//DCP2_KEY_RANGE_BLUE
+#define DCP2_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
+#define DCP2_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
+#define DCP2_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000FFFFL
+#define DCP2_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xFFFF0000L
+//DCP2_DEGAMMA_CONTROL
+#define DCP2_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
+#define DCP2_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
+#define DCP2_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
+#define DCP2_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L
+#define DCP2_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x00000300L
+#define DCP2_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L
+//DCP2_GAMUT_REMAP_CONTROL
+#define DCP2_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
+#define DCP2_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L
+//DCP2_GAMUT_REMAP_C11_C12
+#define DCP2_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
+#define DCP2_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
+#define DCP2_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000FFFFL
+#define DCP2_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xFFFF0000L
+//DCP2_GAMUT_REMAP_C13_C14
+#define DCP2_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
+#define DCP2_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
+#define DCP2_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000FFFFL
+#define DCP2_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xFFFF0000L
+//DCP2_GAMUT_REMAP_C21_C22
+#define DCP2_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
+#define DCP2_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
+#define DCP2_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000FFFFL
+#define DCP2_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xFFFF0000L
+//DCP2_GAMUT_REMAP_C23_C24
+#define DCP2_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
+#define DCP2_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
+#define DCP2_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000FFFFL
+#define DCP2_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xFFFF0000L
+//DCP2_GAMUT_REMAP_C31_C32
+#define DCP2_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
+#define DCP2_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
+#define DCP2_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000FFFFL
+#define DCP2_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xFFFF0000L
+//DCP2_GAMUT_REMAP_C33_C34
+#define DCP2_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
+#define DCP2_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
+#define DCP2_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000FFFFL
+#define DCP2_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xFFFF0000L
+//DCP2_DCP_SPATIAL_DITHER_CNTL
+#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
+#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
+#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
+#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
+#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
+#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
+#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L
+#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L
+#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x000000C0L
+#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L
+#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L
+#define DCP2_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L
+//DCP2_DCP_RANDOM_SEEDS
+#define DCP2_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
+#define DCP2_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
+#define DCP2_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
+#define DCP2_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000FFL
+#define DCP2_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000FF00L
+#define DCP2_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00FF0000L
+//DCP2_DCP_FP_CONVERTED_FIELD
+#define DCP2_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
+#define DCP2_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
+#define DCP2_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
+#define DCP2_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
+//DCP2_CUR_CONTROL
+#define DCP2_CUR_CONTROL__CURSOR_EN__SHIFT 0x0
+#define DCP2_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
+#define DCP2_CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
+#define DCP2_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT 0xb
+#define DCP2_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT 0xc
+#define DCP2_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
+#define DCP2_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
+#define DCP2_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
+#define DCP2_CUR_CONTROL__CURSOR_EN_MASK 0x00000001L
+#define DCP2_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L
+#define DCP2_CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L
+#define DCP2_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK 0x00000800L
+#define DCP2_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK 0x0000F000L
+#define DCP2_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L
+#define DCP2_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L
+#define DCP2_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L
+//DCP2_CUR_SURFACE_ADDRESS
+#define DCP2_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
+#define DCP2_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//DCP2_CUR_SIZE
+#define DCP2_CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
+#define DCP2_CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
+#define DCP2_CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000007FL
+#define DCP2_CUR_SIZE__CURSOR_WIDTH_MASK 0x007F0000L
+//DCP2_CUR_SURFACE_ADDRESS_HIGH
+#define DCP2_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP2_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP2_CUR_POSITION
+#define DCP2_CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
+#define DCP2_CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
+#define DCP2_CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
+#define DCP2_CUR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
+//DCP2_CUR_HOT_SPOT
+#define DCP2_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
+#define DCP2_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
+#define DCP2_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000007FL
+#define DCP2_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x007F0000L
+//DCP2_CUR_COLOR1
+#define DCP2_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
+#define DCP2_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
+#define DCP2_CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
+#define DCP2_CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000FFL
+#define DCP2_CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000FF00L
+#define DCP2_CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00FF0000L
+//DCP2_CUR_COLOR2
+#define DCP2_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
+#define DCP2_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
+#define DCP2_CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
+#define DCP2_CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000FFL
+#define DCP2_CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000FF00L
+#define DCP2_CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00FF0000L
+//DCP2_CUR_UPDATE
+#define DCP2_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
+#define DCP2_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
+#define DCP2_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
+#define DCP2_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define DCP2_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
+#define DCP2_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L
+#define DCP2_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L
+#define DCP2_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L
+#define DCP2_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+#define DCP2_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x06000000L
+//DCP2_CUR_REQUEST_FILTER_CNTL
+#define DCP2_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
+#define DCP2_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L
+//DCP2_CUR_STEREO_CONTROL
+#define DCP2_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
+#define DCP2_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
+#define DCP2_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
+#define DCP2_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
+#define DCP2_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x00003FF0L
+#define DCP2_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x03FF0000L
+//DCP2_DC_LUT_RW_MODE
+#define DCP2_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
+#define DCP2_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
+#define DCP2_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
+#define DCP2_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L
+#define DCP2_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x00010000L
+#define DCP2_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x00020000L
+//DCP2_DC_LUT_RW_INDEX
+#define DCP2_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
+#define DCP2_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000FFL
+//DCP2_DC_LUT_SEQ_COLOR
+#define DCP2_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
+#define DCP2_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000FFFFL
+//DCP2_DC_LUT_PWL_DATA
+#define DCP2_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
+#define DCP2_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
+#define DCP2_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000FFFFL
+#define DCP2_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xFFFF0000L
+//DCP2_DC_LUT_30_COLOR
+#define DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
+#define DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
+#define DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
+#define DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003FFL
+#define DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
+#define DCP2_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3FF00000L
+//DCP2_DC_LUT_VGA_ACCESS_ENABLE
+#define DCP2_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
+#define DCP2_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L
+//DCP2_DC_LUT_WRITE_EN_MASK
+#define DCP2_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define DCP2_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L
+//DCP2_DC_LUT_AUTOFILL
+#define DCP2_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
+#define DCP2_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
+#define DCP2_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L
+#define DCP2_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L
+//DCP2_DC_LUT_CONTROL
+#define DCP2_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
+#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
+#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
+#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
+#define DCP2_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
+#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
+#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
+#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
+#define DCP2_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
+#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
+#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
+#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
+#define DCP2_DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000FL
+#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L
+#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L
+#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000C0L
+#define DCP2_DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000F00L
+#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L
+#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L
+#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000C000L
+#define DCP2_DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000F0000L
+#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L
+#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L
+#define DCP2_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00C00000L
+//DCP2_DC_LUT_BLACK_OFFSET_BLUE
+#define DCP2_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
+#define DCP2_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL
+//DCP2_DC_LUT_BLACK_OFFSET_GREEN
+#define DCP2_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
+#define DCP2_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL
+//DCP2_DC_LUT_BLACK_OFFSET_RED
+#define DCP2_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
+#define DCP2_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL
+//DCP2_DC_LUT_WHITE_OFFSET_BLUE
+#define DCP2_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
+#define DCP2_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000FFFFL
+//DCP2_DC_LUT_WHITE_OFFSET_GREEN
+#define DCP2_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
+#define DCP2_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000FFFFL
+//DCP2_DC_LUT_WHITE_OFFSET_RED
+#define DCP2_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
+#define DCP2_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000FFFFL
+//DCP2_DCP_CRC_CONTROL
+#define DCP2_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
+#define DCP2_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
+#define DCP2_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
+#define DCP2_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L
+#define DCP2_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001CL
+#define DCP2_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L
+//DCP2_DCP_CRC_MASK
+#define DCP2_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
+#define DCP2_DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xFFFFFFFFL
+//DCP2_DCP_CRC_CURRENT
+#define DCP2_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
+#define DCP2_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xFFFFFFFFL
+//DCP2_DVMM_PTE_CONTROL
+#define DCP2_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
+#define DCP2_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
+#define DCP2_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
+#define DCP2_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
+#define DCP2_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
+#define DCP2_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
+#define DCP2_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
+#define DCP2_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
+#define DCP2_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
+#define DCP2_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
+#define DCP2_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
+#define DCP2_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
+//DCP2_DCP_CRC_LAST
+#define DCP2_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
+#define DCP2_DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xFFFFFFFFL
+//DCP2_DVMM_PTE_ARB_CONTROL
+#define DCP2_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
+#define DCP2_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
+#define DCP2_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
+#define DCP2_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
+//DCP2_GRPH_FLIP_RATE_CNTL
+#define DCP2_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
+#define DCP2_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
+#define DCP2_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x00000007L
+#define DCP2_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x00000008L
+//DCP2_DCP_GSL_CONTROL
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x4
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x14
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x15
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x17
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT 0x1a
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x000FFFF0L
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00100000L
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x00600000L
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x00800000L
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK 0x04000000L
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L
+#define DCP2_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xF0000000L
+//DCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK
+#define DCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
+#define DCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
+#define DCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000FL
+#define DCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000001F0L
+//DCP2_GRPH_STEREOSYNC_FLIP
+#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
+#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
+#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
+#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L
+#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
+#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
+#define DCP2_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
+//DCP2_HW_ROTATION
+#define DCP2_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
+#define DCP2_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x00000007L
+//DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL
+#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
+#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
+#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
+#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x00000001L
+#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x00000002L
+#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x0001FFF0L
+//DCP2_REGAMMA_CONTROL
+#define DCP2_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
+#define DCP2_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L
+//DCP2_REGAMMA_LUT_INDEX
+#define DCP2_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
+#define DCP2_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001FFL
+//DCP2_REGAMMA_LUT_DATA
+#define DCP2_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
+#define DCP2_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007FFFFL
+//DCP2_REGAMMA_LUT_WRITE_EN_MASK
+#define DCP2_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define DCP2_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
+//DCP2_REGAMMA_CNTLA_START_CNTL
+#define DCP2_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define DCP2_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
+#define DCP2_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+//DCP2_REGAMMA_CNTLA_SLOPE_CNTL
+#define DCP2_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+//DCP2_REGAMMA_CNTLA_END_CNTL1
+#define DCP2_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
+//DCP2_REGAMMA_CNTLA_END_CNTL2
+#define DCP2_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
+#define DCP2_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+#define DCP2_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+//DCP2_REGAMMA_CNTLA_REGION_0_1
+#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP2_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//DCP2_REGAMMA_CNTLA_REGION_2_3
+#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP2_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//DCP2_REGAMMA_CNTLA_REGION_4_5
+#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP2_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//DCP2_REGAMMA_CNTLA_REGION_6_7
+#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP2_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//DCP2_REGAMMA_CNTLA_REGION_8_9
+#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP2_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//DCP2_REGAMMA_CNTLA_REGION_10_11
+#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP2_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//DCP2_REGAMMA_CNTLA_REGION_12_13
+#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP2_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//DCP2_REGAMMA_CNTLA_REGION_14_15
+#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP2_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//DCP2_REGAMMA_CNTLB_START_CNTL
+#define DCP2_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define DCP2_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
+#define DCP2_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+//DCP2_REGAMMA_CNTLB_SLOPE_CNTL
+#define DCP2_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+//DCP2_REGAMMA_CNTLB_END_CNTL1
+#define DCP2_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
+//DCP2_REGAMMA_CNTLB_END_CNTL2
+#define DCP2_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
+#define DCP2_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+#define DCP2_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+//DCP2_REGAMMA_CNTLB_REGION_0_1
+#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP2_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//DCP2_REGAMMA_CNTLB_REGION_2_3
+#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP2_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//DCP2_REGAMMA_CNTLB_REGION_4_5
+#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP2_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//DCP2_REGAMMA_CNTLB_REGION_6_7
+#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP2_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//DCP2_REGAMMA_CNTLB_REGION_8_9
+#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP2_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//DCP2_REGAMMA_CNTLB_REGION_10_11
+#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP2_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//DCP2_REGAMMA_CNTLB_REGION_12_13
+#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP2_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//DCP2_REGAMMA_CNTLB_REGION_14_15
+#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP2_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//DCP2_ALPHA_CONTROL
+#define DCP2_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
+#define DCP2_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
+#define DCP2_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x00000001L
+#define DCP2_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x00000002L
+//DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS
+#define DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH
+#define DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS
+#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
+#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
+#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
+#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
+#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
+#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
+#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
+#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0x000FFFFFL
+#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x01000000L
+#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x02000000L
+#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x04000000L
+#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000L
+#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000L
+#define DCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000L
+//DCP2_GRPH_XDMA_FLIP_TIMEOUT
+#define DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT 0x0
+#define DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT 0x1
+#define DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT 0x2
+#define DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK 0x00000001L
+#define DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK 0x00000002L
+#define DCP2_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK 0x00000004L
+//DCP2_GRPH_XDMA_FLIP_AVG_DELAY
+#define DCP2_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT 0x0
+#define DCP2_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT 0x10
+#define DCP2_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK 0x0000FFFFL
+#define DCP2_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK 0x00FF0000L
+//DCP2_GRPH_SURFACE_COUNTER_CONTROL
+#define DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0
+#define DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1
+#define DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9
+#define DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x00000001L
+#define DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x0000001EL
+#define DCP2_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x00000200L
+//DCP2_GRPH_SURFACE_COUNTER_OUTPUT
+#define DCP2_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0
+#define DCP2_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10
+#define DCP2_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0x0000FFFFL
+#define DCP2_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_lb2_dispdec
+//LB2_LB_DATA_FORMAT
+#define LB2_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
+#define LB2_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
+#define LB2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
+#define LB2_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
+#define LB2_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
+#define LB2_LB_DATA_FORMAT__PREFILL_EN__SHIFT 0x8
+#define LB2_LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
+#define LB2_LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
+#define LB2_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
+#define LB2_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
+#define LB2_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
+#define LB2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
+#define LB2_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
+#define LB2_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
+#define LB2_LB_DATA_FORMAT__PREFILL_EN_MASK 0x00000100L
+#define LB2_LB_DATA_FORMAT__PREFETCH_MASK 0x00001000L
+#define LB2_LB_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
+#define LB2_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
+//LB2_LB_MEMORY_CTRL
+#define LB2_LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
+#define LB2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+#define LB2_LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
+#define LB2_LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00001FFFL
+#define LB2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
+#define LB2_LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
+//LB2_LB_MEMORY_SIZE_STATUS
+#define LB2_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
+#define LB2_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00001FFFL
+//LB2_LB_DESKTOP_HEIGHT
+#define LB2_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
+#define LB2_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
+//LB2_LB_VLINE_START_END
+#define LB2_LB_VLINE_START_END__VLINE_START__SHIFT 0x0
+#define LB2_LB_VLINE_START_END__VLINE_END__SHIFT 0x10
+#define LB2_LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
+#define LB2_LB_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
+#define LB2_LB_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
+#define LB2_LB_VLINE_START_END__VLINE_INV_MASK 0x80000000L
+//LB2_LB_VLINE2_START_END
+#define LB2_LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
+#define LB2_LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
+#define LB2_LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
+#define LB2_LB_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
+#define LB2_LB_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
+#define LB2_LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
+//LB2_LB_V_COUNTER
+#define LB2_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
+#define LB2_LB_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
+//LB2_LB_SNAPSHOT_V_COUNTER
+#define LB2_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
+#define LB2_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
+//LB2_LB_INTERRUPT_MASK
+#define LB2_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
+#define LB2_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
+#define LB2_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
+#define LB2_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
+#define LB2_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
+#define LB2_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
+//LB2_LB_VLINE_STATUS
+#define LB2_LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
+#define LB2_LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
+#define LB2_LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
+#define LB2_LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
+#define LB2_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
+#define LB2_LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
+#define LB2_LB_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
+#define LB2_LB_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
+#define LB2_LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
+#define LB2_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
+//LB2_LB_VLINE2_STATUS
+#define LB2_LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
+#define LB2_LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
+#define LB2_LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
+#define LB2_LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
+#define LB2_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
+#define LB2_LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
+#define LB2_LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
+#define LB2_LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
+#define LB2_LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
+#define LB2_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
+//LB2_LB_VBLANK_STATUS
+#define LB2_LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
+#define LB2_LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
+#define LB2_LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
+#define LB2_LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
+#define LB2_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
+#define LB2_LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
+#define LB2_LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
+#define LB2_LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
+#define LB2_LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
+#define LB2_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
+//LB2_LB_SYNC_RESET_SEL
+#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
+#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
+#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
+#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
+#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
+#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
+#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
+#define LB2_LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
+//LB2_LB_BLACK_KEYER_R_CR
+#define LB2_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
+#define LB2_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
+//LB2_LB_BLACK_KEYER_G_Y
+#define LB2_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
+#define LB2_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
+//LB2_LB_BLACK_KEYER_B_CB
+#define LB2_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
+#define LB2_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
+//LB2_LB_KEYER_COLOR_CTRL
+#define LB2_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
+#define LB2_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
+#define LB2_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
+#define LB2_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
+//LB2_LB_KEYER_COLOR_R_CR
+#define LB2_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
+#define LB2_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
+//LB2_LB_KEYER_COLOR_G_Y
+#define LB2_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
+#define LB2_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
+//LB2_LB_KEYER_COLOR_B_CB
+#define LB2_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
+#define LB2_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
+//LB2_LB_KEYER_COLOR_REP_R_CR
+#define LB2_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
+#define LB2_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
+//LB2_LB_KEYER_COLOR_REP_G_Y
+#define LB2_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
+#define LB2_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
+//LB2_LB_KEYER_COLOR_REP_B_CB
+#define LB2_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
+#define LB2_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
+//LB2_LB_BUFFER_LEVEL_STATUS
+#define LB2_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
+#define LB2_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
+#define LB2_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
+#define LB2_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
+#define LB2_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
+#define LB2_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
+#define LB2_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
+#define LB2_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
+//LB2_LB_BUFFER_URGENCY_CTRL
+#define LB2_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
+#define LB2_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
+#define LB2_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
+#define LB2_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
+//LB2_LB_BUFFER_URGENCY_STATUS
+#define LB2_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
+#define LB2_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
+#define LB2_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
+#define LB2_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
+//LB2_LB_BUFFER_STATUS
+#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
+#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
+#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
+#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
+#define LB2_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
+#define LB2_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
+#define LB2_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
+#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
+#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
+#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
+#define LB2_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
+#define LB2_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
+#define LB2_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
+#define LB2_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
+//LB2_LB_NO_OUTSTANDING_REQ_STATUS
+#define LB2_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
+#define LB2_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
+//LB2_MVP_AFR_FLIP_MODE
+#define LB2_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
+#define LB2_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L
+//LB2_MVP_AFR_FLIP_FIFO_CNTL
+#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
+#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
+#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
+#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
+#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000FL
+#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L
+#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L
+#define LB2_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L
+//LB2_MVP_FLIP_LINE_NUM_INSERT
+#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
+#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
+#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
+#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
+#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L
+#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007FFF00L
+#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3F000000L
+#define LB2_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L
+//LB2_DC_MVP_LB_CONTROL
+#define LB2_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
+#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
+#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
+#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
+#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
+#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
+#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
+#define LB2_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L
+#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L
+#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L
+#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L
+#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L
+#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L
+#define LB2_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L
+
+
+// addressBlock: dce_dc_dcfe2_dispdec
+//DCFE2_DCFE_CLOCK_CONTROL
+#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
+#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
+#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
+#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf
+#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT 0x11
+#define DCFE2_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
+#define DCFE2_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
+#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L
+#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L
+#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L
+#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x00008000L
+#define DCFE2_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK 0x00020000L
+#define DCFE2_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1F000000L
+#define DCFE2_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000L
+//DCFE2_DCFE_SOFT_RESET
+#define DCFE2_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
+#define DCFE2_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
+#define DCFE2_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
+#define DCFE2_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
+#define DCFE2_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
+#define DCFE2_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5
+#define DCFE2_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
+#define DCFE2_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x00000002L
+#define DCFE2_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x00000004L
+#define DCFE2_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x00000008L
+#define DCFE2_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
+#define DCFE2_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x00000020L
+//DCFE2_DCFE_MEM_PWR_CTRL
+#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
+#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
+#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
+#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
+#define DCFE2_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
+#define DCFE2_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
+#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
+#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
+#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x00000003L
+#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x00000004L
+#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x00000018L
+#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x00000020L
+#define DCFE2_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
+#define DCFE2_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x00000100L
+#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x00000600L
+#define DCFE2_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x00000800L
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x00003000L
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x00004000L
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x00018000L
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x00020000L
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0x000C0000L
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x00100000L
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x00600000L
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x00800000L
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x03000000L
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x04000000L
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000L
+#define DCFE2_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000L
+//DCFE2_DCFE_MEM_PWR_CTRL2
+#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
+#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
+#define DCFE2_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
+#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
+#define DCFE2_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
+#define DCFE2_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
+#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
+#define DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
+#define DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
+#define DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
+#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
+#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
+#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x00000003L
+#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
+#define DCFE2_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
+#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0x000000C0L
+#define DCFE2_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x00000300L
+#define DCFE2_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0x00000C00L
+#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x00003000L
+#define DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0x0000C000L
+#define DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x00030000L
+#define DCFE2_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x00040000L
+#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x00600000L
+#define DCFE2_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x00800000L
+//DCFE2_DCFE_MEM_PWR_STATUS
+#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
+#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
+#define DCFE2_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
+#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
+#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
+#define DCFE2_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
+#define DCFE2_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
+#define DCFE2_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
+#define DCFE2_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
+#define DCFE2_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
+#define DCFE2_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
+#define DCFE2_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
+#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x00000003L
+#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0x0000000CL
+#define DCFE2_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x00000030L
+#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0x000000C0L
+#define DCFE2_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x00000300L
+#define DCFE2_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0x00000C00L
+#define DCFE2_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x00003000L
+#define DCFE2_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0x0000C000L
+#define DCFE2_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x00030000L
+#define DCFE2_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0x000C0000L
+#define DCFE2_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x00300000L
+#define DCFE2_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0x00C00000L
+//DCFE2_DCFE_MISC
+#define DCFE2_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
+#define DCFE2_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
+//DCFE2_DCFE_FLUSH
+#define DCFE2_DCFE_FLUSH__FLUSH_OCCURED__SHIFT 0x0
+#define DCFE2_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
+#define DCFE2_DCFE_FLUSH__FLUSH_DEEP__SHIFT 0x2
+#define DCFE2_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
+#define DCFE2_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
+#define DCFE2_DCFE_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
+#define DCFE2_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
+#define DCFE2_DCFE_FLUSH__FLUSH_DEEP_MASK 0x00000004L
+#define DCFE2_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
+#define DCFE2_DCFE_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
+
+
+// addressBlock: dce_dc_dc_perfmon5_dispdec
+//DC_PERFMON5_PERFCOUNTER_CNTL
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON5_PERFCOUNTER_CNTL2
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON5_PERFCOUNTER_STATE
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON5_PERFMON_CNTL
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON5_PERFMON_CNTL2
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON5_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON5_PERFMON_CVALUE_LOW
+#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON5_PERFMON_HI
+#define DC_PERFMON5_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON5_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON5_PERFMON_LOW
+#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dmif_pg2_dispdec
+//DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1
+#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
+#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
+//DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2
+#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
+#define DMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
+//DMIF_PG2_DPG_WATERMARK_MASK_CONTROL
+#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x4
+#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT 0xc
+#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0xf
+#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x12
+#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT 0x13
+#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT 0x14
+#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000007L
+#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000070L
+#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000700L
+#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK 0x00007000L
+#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00038000L
+#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x00040000L
+#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK 0x00080000L
+#define DMIF_PG2_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK 0x3FF00000L
+//DMIF_PG2_DPG_PIPE_URGENCY_CONTROL
+#define DMIF_PG2_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+#define DMIF_PG2_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+#define DMIF_PG2_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
+#define DMIF_PG2_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
+//DMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL
+#define DMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT 0x0
+#define DMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT 0x10
+#define DMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK 0x0000FFFFL
+#define DMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK 0xFFFF0000L
+//DMIF_PG2_DPG_PIPE_STUTTER_CONTROL
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT 0x10
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x14
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x15
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x16
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x17
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x1a
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x1b
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK 0x00010000L
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00100000L
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00200000L
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00400000L
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00800000L
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x04000000L
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x08000000L
+//DMIF_PG2_DPG_PIPE_STUTTER_CONTROL2
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x0
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT 0x10
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0x0000FFFFL
+#define DMIF_PG2_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
+//DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL
+#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT 0x0
+#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT 0x1
+#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT 0xf
+#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK 0x00000001L
+#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK 0x00000002L
+#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
+#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
+#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
+#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
+#define DMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK 0xFFFF8000L
+//DMIF_PG2_DPG_REPEATER_PROGRAM
+#define DMIF_PG2_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+#define DMIF_PG2_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+#define DMIF_PG2_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
+#define DMIF_PG2_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
+//DMIF_PG2_DPG_CHK_PRE_PROC_CNTL
+#define DMIF_PG2_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+#define DMIF_PG2_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
+//DMIF_PG2_DPG_DVMM_STATUS
+#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT 0x0
+#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT 0x1
+#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT 0x4
+#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT 0x5
+#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK 0x00000001L
+#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK 0x00000002L
+#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK 0x00000010L
+#define DMIF_PG2_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK 0x00000020L
+
+
+// addressBlock: dce_dc_scl2_dispdec
+//SCL2_SCL_COEF_RAM_SELECT
+#define SCL2_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define SCL2_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
+#define SCL2_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
+#define SCL2_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000FL
+#define SCL2_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000F00L
+#define SCL2_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00070000L
+//SCL2_SCL_COEF_RAM_TAP_DATA
+#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+#define SCL2_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+//SCL2_SCL_MODE
+#define SCL2_SCL_MODE__SCL_MODE__SHIFT 0x0
+#define SCL2_SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
+#define SCL2_SCL_MODE__SCL_MODE_MASK 0x00000003L
+#define SCL2_SCL_MODE__SCL_PSCL_EN_MASK 0x00000010L
+//SCL2_SCL_TAP_CONTROL
+#define SCL2_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
+#define SCL2_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
+#define SCL2_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
+#define SCL2_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000F00L
+//SCL2_SCL_CONTROL
+#define SCL2_SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+#define SCL2_SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
+#define SCL2_SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+#define SCL2_SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
+//SCL2_SCL_BYPASS_CONTROL
+#define SCL2_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
+#define SCL2_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L
+//SCL2_SCL_MANUAL_REPLICATE_CONTROL
+#define SCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+#define SCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+#define SCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+#define SCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+//SCL2_SCL_AUTOMATIC_MODE_CONTROL
+#define SCL2_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
+#define SCL2_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
+#define SCL2_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
+#define SCL2_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
+//SCL2_SCL_HORZ_FILTER_CONTROL
+#define SCL2_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
+#define SCL2_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCL2_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L
+#define SCL2_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+//SCL2_SCL_HORZ_FILTER_SCALE_RATIO
+#define SCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+#define SCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+//SCL2_SCL_HORZ_FILTER_INIT
+#define SCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+#define SCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+#define SCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+#define SCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+//SCL2_SCL_VERT_FILTER_CONTROL
+#define SCL2_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
+#define SCL2_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCL2_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L
+#define SCL2_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+//SCL2_SCL_VERT_FILTER_SCALE_RATIO
+#define SCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+#define SCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+//SCL2_SCL_VERT_FILTER_INIT
+#define SCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+#define SCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+#define SCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+#define SCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
+//SCL2_SCL_VERT_FILTER_INIT_BOT
+#define SCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+#define SCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+#define SCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+#define SCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
+//SCL2_SCL_ROUND_OFFSET
+#define SCL2_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
+#define SCL2_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+#define SCL2_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
+#define SCL2_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
+//SCL2_SCL_UPDATE
+#define SCL2_SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+#define SCL2_SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
+#define SCL2_SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
+#define SCL2_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
+#define SCL2_SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+#define SCL2_SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
+#define SCL2_SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
+#define SCL2_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
+//SCL2_SCL_F_SHARP_CONTROL
+#define SCL2_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
+#define SCL2_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
+#define SCL2_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
+#define SCL2_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
+#define SCL2_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L
+#define SCL2_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L
+#define SCL2_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L
+#define SCL2_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L
+//SCL2_SCL_ALU_CONTROL
+#define SCL2_SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
+#define SCL2_SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
+//SCL2_SCL_COEF_RAM_CONFLICT_STATUS
+#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
+#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
+#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
+#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
+#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
+#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L
+#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L
+#define SCL2_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
+//SCL2_VIEWPORT_START_SECONDARY
+#define SCL2_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
+#define SCL2_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
+#define SCL2_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
+#define SCL2_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
+//SCL2_VIEWPORT_START
+#define SCL2_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
+#define SCL2_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
+#define SCL2_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
+#define SCL2_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
+//SCL2_VIEWPORT_SIZE
+#define SCL2_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
+#define SCL2_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
+#define SCL2_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003FFFL
+#define SCL2_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3FFF0000L
+//SCL2_EXT_OVERSCAN_LEFT_RIGHT
+#define SCL2_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+#define SCL2_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+#define SCL2_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+#define SCL2_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+//SCL2_EXT_OVERSCAN_TOP_BOTTOM
+#define SCL2_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+#define SCL2_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+#define SCL2_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+#define SCL2_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+//SCL2_SCL_MODE_CHANGE_DET1
+#define SCL2_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
+#define SCL2_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
+#define SCL2_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
+#define SCL2_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
+#define SCL2_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
+#define SCL2_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
+//SCL2_SCL_MODE_CHANGE_DET2
+#define SCL2_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
+#define SCL2_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
+//SCL2_SCL_MODE_CHANGE_DET3
+#define SCL2_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
+#define SCL2_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
+#define SCL2_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
+#define SCL2_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
+//SCL2_SCL_MODE_CHANGE_MASK
+#define SCL2_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
+#define SCL2_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_blnd2_dispdec
+//BLND2_BLND_CONTROL
+#define BLND2_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
+#define BLND2_BLND_CONTROL__BLND_MODE__SHIFT 0x8
+#define BLND2_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
+#define BLND2_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
+#define BLND2_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
+#define BLND2_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
+#define BLND2_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
+#define BLND2_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
+#define BLND2_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
+#define BLND2_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
+#define BLND2_BLND_CONTROL__BLND_MODE_MASK 0x00000300L
+#define BLND2_BLND_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
+#define BLND2_BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
+#define BLND2_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
+#define BLND2_BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
+#define BLND2_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
+#define BLND2_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
+#define BLND2_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
+//BLND2_BLND_SM_CONTROL2
+#define BLND2_BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0
+#define BLND2_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
+#define BLND2_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
+#define BLND2_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+#define BLND2_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+#define BLND2_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
+#define BLND2_BLND_SM_CONTROL2__SM_MODE_MASK 0x00000007L
+#define BLND2_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
+#define BLND2_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
+#define BLND2_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+#define BLND2_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+#define BLND2_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
+//BLND2_BLND_CONTROL2
+#define BLND2_BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
+#define BLND2_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
+#define BLND2_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
+#define BLND2_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
+#define BLND2_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
+#define BLND2_BLND_CONTROL2__PTI_ENABLE_MASK 0x00000001L
+#define BLND2_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
+#define BLND2_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
+#define BLND2_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
+#define BLND2_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
+//BLND2_BLND_UPDATE
+#define BLND2_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
+#define BLND2_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
+#define BLND2_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
+#define BLND2_BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
+#define BLND2_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
+#define BLND2_BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
+//BLND2_BLND_UNDERFLOW_INTERRUPT
+#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
+#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
+#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
+#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
+#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
+#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
+#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
+#define BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
+//BLND2_BLND_V_UPDATE_LOCK
+#define BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
+#define BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
+#define BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
+#define BLND2_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
+#define BLND2_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
+#define BLND2_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
+#define BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
+#define BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
+#define BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
+#define BLND2_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
+#define BLND2_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
+#define BLND2_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
+//BLND2_BLND_REG_UPDATE_STATUS
+#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
+#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
+#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
+#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
+#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
+#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
+#define BLND2_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
+#define BLND2_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
+#define BLND2_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
+#define BLND2_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
+#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
+#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
+#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
+#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
+#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
+#define BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
+#define BLND2_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
+#define BLND2_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
+#define BLND2_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
+#define BLND2_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
+
+
+// addressBlock: dce_dc_crtc2_dispdec
+//CRTC2_CRTC_H_BLANK_EARLY_NUM
+#define CRTC2_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
+#define CRTC2_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
+#define CRTC2_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
+#define CRTC2_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
+//CRTC2_CRTC_H_TOTAL
+#define CRTC2_CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
+#define CRTC2_CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
+//CRTC2_CRTC_H_BLANK_START_END
+#define CRTC2_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
+#define CRTC2_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
+#define CRTC2_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
+#define CRTC2_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
+//CRTC2_CRTC_H_SYNC_A
+#define CRTC2_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
+#define CRTC2_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
+#define CRTC2_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
+#define CRTC2_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
+//CRTC2_CRTC_H_SYNC_A_CNTL
+#define CRTC2_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
+#define CRTC2_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
+#define CRTC2_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
+#define CRTC2_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
+#define CRTC2_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
+#define CRTC2_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
+//CRTC2_CRTC_H_SYNC_B
+#define CRTC2_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
+#define CRTC2_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
+#define CRTC2_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
+#define CRTC2_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
+//CRTC2_CRTC_H_SYNC_B_CNTL
+#define CRTC2_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
+#define CRTC2_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
+#define CRTC2_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
+#define CRTC2_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
+#define CRTC2_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
+#define CRTC2_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
+//CRTC2_CRTC_VBI_END
+#define CRTC2_CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
+#define CRTC2_CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
+#define CRTC2_CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
+#define CRTC2_CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
+//CRTC2_CRTC_V_TOTAL
+#define CRTC2_CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
+#define CRTC2_CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
+//CRTC2_CRTC_V_TOTAL_MIN
+#define CRTC2_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
+#define CRTC2_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
+//CRTC2_CRTC_V_TOTAL_MAX
+#define CRTC2_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
+#define CRTC2_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
+#define CRTC2_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
+#define CRTC2_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
+//CRTC2_CRTC_V_TOTAL_CONTROL
+#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
+#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
+#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
+#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
+#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
+#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
+#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
+#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
+#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
+#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
+#define CRTC2_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+//CRTC2_CRTC_V_TOTAL_INT_STATUS
+#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+#define CRTC2_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+//CRTC2_CRTC_VSYNC_NOM_INT_STATUS
+#define CRTC2_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
+#define CRTC2_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+#define CRTC2_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
+#define CRTC2_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+//CRTC2_CRTC_V_BLANK_START_END
+#define CRTC2_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
+#define CRTC2_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
+#define CRTC2_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
+#define CRTC2_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
+//CRTC2_CRTC_V_SYNC_A
+#define CRTC2_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
+#define CRTC2_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
+#define CRTC2_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
+#define CRTC2_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
+//CRTC2_CRTC_V_SYNC_A_CNTL
+#define CRTC2_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
+#define CRTC2_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
+//CRTC2_CRTC_V_SYNC_B
+#define CRTC2_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
+#define CRTC2_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
+#define CRTC2_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
+#define CRTC2_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
+//CRTC2_CRTC_V_SYNC_B_CNTL
+#define CRTC2_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
+#define CRTC2_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
+//CRTC2_CRTC_DTMTEST_CNTL
+#define CRTC2_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
+#define CRTC2_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
+#define CRTC2_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
+#define CRTC2_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
+//CRTC2_CRTC_DTMTEST_STATUS_POSITION
+#define CRTC2_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
+#define CRTC2_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
+#define CRTC2_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
+#define CRTC2_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTC2_CRTC_TRIGA_CNTL
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
+#define CRTC2_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
+//CRTC2_CRTC_TRIGA_MANUAL_TRIG
+#define CRTC2_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
+#define CRTC2_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+//CRTC2_CRTC_TRIGB_CNTL
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
+#define CRTC2_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
+//CRTC2_CRTC_TRIGB_MANUAL_TRIG
+#define CRTC2_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
+#define CRTC2_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+//CRTC2_CRTC_FORCE_COUNT_NOW_CNTL
+#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+#define CRTC2_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+//CRTC2_CRTC_FLOW_CONTROL
+#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
+#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+#define CRTC2_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+//CRTC2_CRTC_STEREO_FORCE_NEXT_EYE
+#define CRTC2_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+#define CRTC2_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+#define CRTC2_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
+#define CRTC2_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+#define CRTC2_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+#define CRTC2_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+//CRTC2_CRTC_AVSYNC_COUNTER
+#define CRTC2_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
+#define CRTC2_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
+//CRTC2_CRTC_CONTROL
+#define CRTC2_CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTC2_CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
+#define CRTC2_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
+#define CRTC2_CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
+#define CRTC2_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
+#define CRTC2_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
+#define CRTC2_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+#define CRTC2_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
+#define CRTC2_CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
+#define CRTC2_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+#define CRTC2_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+#define CRTC2_CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
+#define CRTC2_CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
+#define CRTC2_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
+#define CRTC2_CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
+#define CRTC2_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
+#define CRTC2_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+#define CRTC2_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+#define CRTC2_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
+#define CRTC2_CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
+#define CRTC2_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+#define CRTC2_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+//CRTC2_CRTC_BLANK_CONTROL
+#define CRTC2_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
+#define CRTC2_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
+#define CRTC2_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
+#define CRTC2_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
+#define CRTC2_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
+#define CRTC2_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
+//CRTC2_CRTC_INTERLACE_CONTROL
+#define CRTC2_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
+#define CRTC2_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+#define CRTC2_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
+#define CRTC2_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+//CRTC2_CRTC_INTERLACE_STATUS
+#define CRTC2_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+#define CRTC2_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
+#define CRTC2_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+#define CRTC2_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+//CRTC2_CRTC_FIELD_INDICATION_CONTROL
+#define CRTC2_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
+#define CRTC2_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
+#define CRTC2_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
+#define CRTC2_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
+//CRTC2_CRTC_PIXEL_DATA_READBACK0
+#define CRTC2_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+#define CRTC2_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+#define CRTC2_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
+#define CRTC2_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
+//CRTC2_CRTC_PIXEL_DATA_READBACK1
+#define CRTC2_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
+#define CRTC2_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
+//CRTC2_CRTC_STATUS
+#define CRTC2_CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
+#define CRTC2_CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
+#define CRTC2_CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
+#define CRTC2_CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
+#define CRTC2_CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
+#define CRTC2_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+#define CRTC2_CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
+#define CRTC2_CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
+#define CRTC2_CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
+#define CRTC2_CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L
+#define CRTC2_CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
+#define CRTC2_CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
+#define CRTC2_CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
+#define CRTC2_CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
+#define CRTC2_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+#define CRTC2_CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L
+#define CRTC2_CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
+#define CRTC2_CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
+//CRTC2_CRTC_STATUS_POSITION
+#define CRTC2_CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
+#define CRTC2_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
+#define CRTC2_CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
+#define CRTC2_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTC2_CRTC_NOM_VERT_POSITION
+#define CRTC2_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
+#define CRTC2_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
+//CRTC2_CRTC_STATUS_FRAME_COUNT
+#define CRTC2_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
+#define CRTC2_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
+//CRTC2_CRTC_STATUS_VF_COUNT
+#define CRTC2_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
+#define CRTC2_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
+//CRTC2_CRTC_STATUS_HV_COUNT
+#define CRTC2_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
+#define CRTC2_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
+//CRTC2_CRTC_COUNT_CONTROL
+#define CRTC2_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
+#define CRTC2_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
+#define CRTC2_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+#define CRTC2_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+//CRTC2_CRTC_COUNT_RESET
+#define CRTC2_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
+#define CRTC2_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
+//CRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define CRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+#define CRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+//CRTC2_CRTC_VERT_SYNC_CONTROL
+#define CRTC2_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+#define CRTC2_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+#define CRTC2_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+#define CRTC2_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+#define CRTC2_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+#define CRTC2_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+//CRTC2_CRTC_STEREO_STATUS
+#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
+#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
+#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
+#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
+#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
+#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
+#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
+#define CRTC2_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+//CRTC2_CRTC_STEREO_CONTROL
+#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
+#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+#define CRTC2_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+#define CRTC2_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
+#define CRTC2_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
+#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
+#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
+#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+#define CRTC2_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+#define CRTC2_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
+#define CRTC2_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+#define CRTC2_CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
+//CRTC2_CRTC_SNAPSHOT_STATUS
+#define CRTC2_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
+#define CRTC2_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
+#define CRTC2_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+#define CRTC2_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
+#define CRTC2_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
+#define CRTC2_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+//CRTC2_CRTC_SNAPSHOT_CONTROL
+#define CRTC2_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+#define CRTC2_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+//CRTC2_CRTC_SNAPSHOT_POSITION
+#define CRTC2_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+#define CRTC2_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+#define CRTC2_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
+#define CRTC2_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTC2_CRTC_SNAPSHOT_FRAME
+#define CRTC2_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+#define CRTC2_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+//CRTC2_CRTC_START_LINE_CONTROL
+#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
+#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
+#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
+#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
+#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
+#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
+#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
+#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
+#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
+#define CRTC2_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
+//CRTC2_CRTC_INTERRUPT_CONTROL
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+#define CRTC2_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+//CRTC2_CRTC_UPDATE_LOCK
+#define CRTC2_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
+#define CRTC2_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
+//CRTC2_CRTC_DOUBLE_BUFFER_CONTROL
+#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
+#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
+#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
+#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
+#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
+#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
+#define CRTC2_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
+//CRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE
+#define CRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
+#define CRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
+//CRTC2_CRTC_TEST_PATTERN_CONTROL
+#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
+#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
+#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
+#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
+#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
+#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
+#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
+#define CRTC2_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
+//CRTC2_CRTC_TEST_PATTERN_PARAMETERS
+#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
+#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
+#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
+#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
+#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
+#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
+#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
+#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
+#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
+#define CRTC2_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
+//CRTC2_CRTC_TEST_PATTERN_COLOR
+#define CRTC2_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
+#define CRTC2_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
+#define CRTC2_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
+#define CRTC2_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
+//CRTC2_CRTC_MASTER_UPDATE_LOCK
+#define CRTC2_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
+#define CRTC2_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
+#define CRTC2_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
+#define CRTC2_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
+#define CRTC2_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
+#define CRTC2_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
+//CRTC2_CRTC_MASTER_UPDATE_MODE
+#define CRTC2_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
+#define CRTC2_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
+#define CRTC2_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
+#define CRTC2_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
+//CRTC2_CRTC_MVP_INBAND_CNTL_INSERT
+#define CRTC2_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
+#define CRTC2_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
+#define CRTC2_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
+#define CRTC2_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
+//CRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER
+#define CRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
+#define CRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
+//CRTC2_CRTC_MVP_STATUS
+#define CRTC2_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
+#define CRTC2_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
+#define CRTC2_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
+#define CRTC2_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
+#define CRTC2_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
+#define CRTC2_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
+#define CRTC2_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
+#define CRTC2_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
+//CRTC2_CRTC_MASTER_EN
+#define CRTC2_CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTC2_CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
+//CRTC2_CRTC_ALLOW_STOP_OFF_V_CNT
+#define CRTC2_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
+#define CRTC2_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
+#define CRTC2_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
+#define CRTC2_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
+//CRTC2_CRTC_V_UPDATE_INT_STATUS
+#define CRTC2_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
+#define CRTC2_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
+#define CRTC2_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
+#define CRTC2_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
+//CRTC2_CRTC_OVERSCAN_COLOR
+#define CRTC2_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
+#define CRTC2_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
+#define CRTC2_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
+#define CRTC2_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
+#define CRTC2_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
+#define CRTC2_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
+//CRTC2_CRTC_OVERSCAN_COLOR_EXT
+#define CRTC2_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
+#define CRTC2_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
+#define CRTC2_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
+#define CRTC2_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
+#define CRTC2_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
+#define CRTC2_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
+//CRTC2_CRTC_BLANK_DATA_COLOR
+#define CRTC2_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+#define CRTC2_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+#define CRTC2_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+#define CRTC2_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+#define CRTC2_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+#define CRTC2_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+//CRTC2_CRTC_BLANK_DATA_COLOR_EXT
+#define CRTC2_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+#define CRTC2_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+#define CRTC2_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+#define CRTC2_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
+#define CRTC2_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
+#define CRTC2_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
+//CRTC2_CRTC_BLACK_COLOR
+#define CRTC2_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
+#define CRTC2_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
+#define CRTC2_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
+#define CRTC2_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
+#define CRTC2_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+#define CRTC2_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+//CRTC2_CRTC_BLACK_COLOR_EXT
+#define CRTC2_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+#define CRTC2_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+#define CRTC2_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+#define CRTC2_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
+#define CRTC2_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
+#define CRTC2_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
+//CRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION
+#define CRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+#define CRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+#define CRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
+#define CRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
+//CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL
+#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+#define CRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+//CRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION
+#define CRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+#define CRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
+//CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL
+#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+#define CRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+//CRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION
+#define CRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+#define CRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
+//CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL
+#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+#define CRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+//CRTC2_CRTC_CRC_CNTL
+#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
+#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
+#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
+#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
+#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
+#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
+#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
+#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
+#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
+#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
+#define CRTC2_CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
+//CRTC2_CRTC_CRC0_WINDOWA_X_CONTROL
+#define CRTC2_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
+#define CRTC2_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
+#define CRTC2_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
+#define CRTC2_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
+//CRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL
+#define CRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
+#define CRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
+#define CRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
+#define CRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
+//CRTC2_CRTC_CRC0_WINDOWB_X_CONTROL
+#define CRTC2_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
+#define CRTC2_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
+#define CRTC2_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
+#define CRTC2_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
+//CRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL
+#define CRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
+#define CRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
+#define CRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
+#define CRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
+//CRTC2_CRTC_CRC0_DATA_RG
+#define CRTC2_CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+#define CRTC2_CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+#define CRTC2_CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+#define CRTC2_CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+//CRTC2_CRTC_CRC0_DATA_B
+#define CRTC2_CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+#define CRTC2_CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+//CRTC2_CRTC_CRC1_WINDOWA_X_CONTROL
+#define CRTC2_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
+#define CRTC2_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
+#define CRTC2_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
+#define CRTC2_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
+//CRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL
+#define CRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
+#define CRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
+#define CRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
+#define CRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
+//CRTC2_CRTC_CRC1_WINDOWB_X_CONTROL
+#define CRTC2_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
+#define CRTC2_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
+#define CRTC2_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
+#define CRTC2_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
+//CRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL
+#define CRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
+#define CRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
+#define CRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
+#define CRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
+//CRTC2_CRTC_CRC1_DATA_RG
+#define CRTC2_CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+#define CRTC2_CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+#define CRTC2_CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+#define CRTC2_CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+//CRTC2_CRTC_CRC1_DATA_B
+#define CRTC2_CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+#define CRTC2_CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+//CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
+//CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START
+#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
+#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
+#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
+#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
+//CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END
+#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
+#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
+#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
+#define CRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
+//CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
+#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
+#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
+#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
+#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
+#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
+#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
+#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
+//CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL
+#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
+#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
+#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
+#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
+#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
+#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
+//CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
+#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
+#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
+#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
+#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
+#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
+#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
+#define CRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
+//CRTC2_CRTC_STATIC_SCREEN_CONTROL
+#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
+#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
+#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
+#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
+#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
+#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
+#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
+#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
+#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
+#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
+#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
+#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
+#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
+#define CRTC2_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
+//CRTC2_CRTC_3D_STRUCTURE_CONTROL
+#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
+#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
+#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
+#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
+#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+#define CRTC2_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+//CRTC2_CRTC_GSL_VSYNC_GAP
+#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
+#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+#define CRTC2_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
+//CRTC2_CRTC_GSL_WINDOW
+#define CRTC2_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
+#define CRTC2_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
+#define CRTC2_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
+#define CRTC2_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
+//CRTC2_CRTC_GSL_CONTROL
+#define CRTC2_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
+#define CRTC2_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
+#define CRTC2_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+#define CRTC2_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
+#define CRTC2_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
+#define CRTC2_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+//CRTC2_CRTC_RANGE_TIMING_INT_STATUS
+#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
+#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
+#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
+#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
+#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
+#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
+#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
+#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
+#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
+#define CRTC2_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
+//CRTC2_CRTC_DRR_CONTROL
+#define CRTC2_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY__SHIFT 0x0
+#define CRTC2_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0xe
+#define CRTC2_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS__SHIFT 0x1c
+#define CRTC2_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE__SHIFT 0x1d
+#define CRTC2_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY_MASK 0x00003FFFL
+#define CRTC2_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR_MASK 0x0FFFC000L
+#define CRTC2_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS_MASK 0x10000000L
+#define CRTC2_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE_MASK 0x60000000L
+
+
+// addressBlock: dce_dc_fmt2_dispdec
+//FMT2_FMT_CLAMP_COMPONENT_R
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
+//FMT2_FMT_CLAMP_COMPONENT_G
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
+//FMT2_FMT_CLAMP_COMPONENT_B
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
+//FMT2_FMT_DYNAMIC_EXP_CNTL
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
+//FMT2_FMT_CONTROL
+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
+#define FMT2_FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
+#define FMT2_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED__SHIFT 0x1e
+#define FMT2_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR__SHIFT 0x1f
+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
+#define FMT2_FMT_CONTROL__FMT_SRC_SELECT_MASK 0x07000000L
+#define FMT2_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_MASK 0x40000000L
+#define FMT2_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR_MASK 0x80000000L
+//FMT2_FMT_BIT_DEPTH_CONTROL
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
+//FMT2_FMT_DITHER_RAND_R_SEED
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
+//FMT2_FMT_DITHER_RAND_G_SEED
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
+//FMT2_FMT_DITHER_RAND_B_SEED
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
+//FMT2_FMT_CLAMP_CNTL
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
+//FMT2_FMT_CRC_CNTL
+#define FMT2_FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
+#define FMT2_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
+#define FMT2_FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
+#define FMT2_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5
+#define FMT2_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6
+#define FMT2_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
+#define FMT2_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9
+#define FMT2_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
+#define FMT2_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+#define FMT2_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
+#define FMT2_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
+#define FMT2_FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L
+#define FMT2_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x00000002L
+#define FMT2_FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L
+#define FMT2_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x00000020L
+#define FMT2_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x00000040L
+#define FMT2_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x00000100L
+#define FMT2_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x00000200L
+#define FMT2_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define FMT2_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+#define FMT2_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L
+#define FMT2_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L
+//FMT2_FMT_CRC_SIG_RED_GREEN_MASK
+#define FMT2_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
+#define FMT2_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
+#define FMT2_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
+#define FMT2_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
+//FMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK
+#define FMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
+#define FMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
+#define FMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
+#define FMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
+//FMT2_FMT_CRC_SIG_RED_GREEN
+#define FMT2_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
+#define FMT2_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
+#define FMT2_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000FFFFL
+#define FMT2_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xFFFF0000L
+//FMT2_FMT_CRC_SIG_BLUE_CONTROL
+#define FMT2_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
+#define FMT2_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
+#define FMT2_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000FFFFL
+#define FMT2_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xFFFF0000L
+//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
+//FMT2_FMT_420_HBLANK_EARLY_START
+#define FMT2_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START__SHIFT 0x0
+#define FMT2_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START_MASK 0x00000FFFL
+
+
+// addressBlock: dce_dc_dcp3_dispdec
+//DCP3_GRPH_ENABLE
+#define DCP3_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
+#define DCP3_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1
+#define DCP3_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
+#define DCP3_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x00000002L
+//DCP3_GRPH_CONTROL
+#define DCP3_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
+#define DCP3_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT 0x2
+#define DCP3_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
+#define DCP3_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT 0x6
+#define DCP3_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
+#define DCP3_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0xc
+#define DCP3_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+#define DCP3_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+#define DCP3_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT 0x12
+#define DCP3_GRPH_CONTROL__GRPH_SW_MODE__SHIFT 0x14
+#define DCP3_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT 0x1c
+#define DCP3_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
+#define DCP3_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
+#define DCP3_GRPH_CONTROL__GRPH_SE_ENABLE_MASK 0x00000004L
+#define DCP3_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
+#define DCP3_GRPH_CONTROL__GRPH_DIM_TYPE_MASK 0x000000C0L
+#define DCP3_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
+#define DCP3_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x00007000L
+#define DCP3_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
+#define DCP3_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
+#define DCP3_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK 0x000C0000L
+#define DCP3_GRPH_CONTROL__GRPH_SW_MODE_MASK 0x01F00000L
+#define DCP3_GRPH_CONTROL__GRPH_NUM_PIPES_MASK 0x70000000L
+#define DCP3_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
+//DCP3_GRPH_LUT_10BIT_BYPASS
+#define DCP3_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
+#define DCP3_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
+#define DCP3_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L
+#define DCP3_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L
+//DCP3_GRPH_SWAP_CNTL
+#define DCP3_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
+#define DCP3_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
+#define DCP3_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
+#define DCP3_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
+#define DCP3_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
+#define DCP3_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
+#define DCP3_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
+#define DCP3_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
+#define DCP3_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
+#define DCP3_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000C00L
+//DCP3_GRPH_PRIMARY_SURFACE_ADDRESS
+#define DCP3_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
+#define DCP3_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP3_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L
+#define DCP3_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP3_GRPH_SECONDARY_SURFACE_ADDRESS
+#define DCP3_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
+#define DCP3_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP3_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L
+#define DCP3_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP3_GRPH_PITCH
+#define DCP3_GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
+#define DCP3_GRPH_PITCH__GRPH_PITCH_MASK 0x00007FFFL
+//DCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+#define DCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+#define DCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP3_GRPH_SURFACE_OFFSET_X
+#define DCP3_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
+#define DCP3_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003FFFL
+//DCP3_GRPH_SURFACE_OFFSET_Y
+#define DCP3_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
+#define DCP3_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003FFFL
+//DCP3_GRPH_X_START
+#define DCP3_GRPH_X_START__GRPH_X_START__SHIFT 0x0
+#define DCP3_GRPH_X_START__GRPH_X_START_MASK 0x00003FFFL
+//DCP3_GRPH_Y_START
+#define DCP3_GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
+#define DCP3_GRPH_Y_START__GRPH_Y_START_MASK 0x00003FFFL
+//DCP3_GRPH_X_END
+#define DCP3_GRPH_X_END__GRPH_X_END__SHIFT 0x0
+#define DCP3_GRPH_X_END__GRPH_X_END_MASK 0x00007FFFL
+//DCP3_GRPH_Y_END
+#define DCP3_GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
+#define DCP3_GRPH_Y_END__GRPH_Y_END_MASK 0x00007FFFL
+//DCP3_INPUT_GAMMA_CONTROL
+#define DCP3_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
+#define DCP3_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000001L
+//DCP3_GRPH_UPDATE
+#define DCP3_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
+#define DCP3_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
+#define DCP3_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
+#define DCP3_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
+#define DCP3_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT 0x8
+#define DCP3_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT 0x9
+#define DCP3_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT 0xa
+#define DCP3_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
+#define DCP3_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
+#define DCP3_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define DCP3_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
+#define DCP3_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
+#define DCP3_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
+#define DCP3_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
+#define DCP3_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
+#define DCP3_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK 0x00000100L
+#define DCP3_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK 0x00000200L
+#define DCP3_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK 0x00000400L
+#define DCP3_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
+#define DCP3_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
+#define DCP3_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+#define DCP3_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
+//DCP3_GRPH_FLIP_CONTROL
+#define DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
+#define DCP3_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
+#define DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4
+#define DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5
+#define DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L
+#define DCP3_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x00000002L
+#define DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x00000010L
+#define DCP3_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000020L
+//DCP3_GRPH_SURFACE_ADDRESS_INUSE
+#define DCP3_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
+#define DCP3_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xFFFFFF00L
+//DCP3_GRPH_DFQ_CONTROL
+#define DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
+#define DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
+#define DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
+#define DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L
+#define DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L
+#define DCP3_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L
+//DCP3_GRPH_DFQ_STATUS
+#define DCP3_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
+#define DCP3_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
+#define DCP3_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
+#define DCP3_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
+#define DCP3_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000FL
+#define DCP3_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000F0L
+#define DCP3_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L
+#define DCP3_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L
+//DCP3_GRPH_INTERRUPT_STATUS
+#define DCP3_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
+#define DCP3_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
+#define DCP3_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
+#define DCP3_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
+//DCP3_GRPH_INTERRUPT_CONTROL
+#define DCP3_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
+#define DCP3_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
+#define DCP3_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
+#define DCP3_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
+//DCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE
+#define DCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
+#define DCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000FFL
+//DCP3_GRPH_COMPRESS_SURFACE_ADDRESS
+#define DCP3_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP3_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP3_GRPH_COMPRESS_PITCH
+#define DCP3_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
+#define DCP3_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001FFC0L
+//DCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH
+#define DCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
+#define DCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0
+#define DCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0x000000FFL
+//DCP3_PRESCALE_GRPH_CONTROL
+#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
+#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
+#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
+#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
+#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
+#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L
+#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L
+#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L
+#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L
+#define DCP3_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L
+//DCP3_PRESCALE_VALUES_GRPH_R
+#define DCP3_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
+#define DCP3_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
+#define DCP3_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000FFFFL
+#define DCP3_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xFFFF0000L
+//DCP3_PRESCALE_VALUES_GRPH_G
+#define DCP3_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
+#define DCP3_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
+#define DCP3_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000FFFFL
+#define DCP3_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xFFFF0000L
+//DCP3_PRESCALE_VALUES_GRPH_B
+#define DCP3_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
+#define DCP3_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
+#define DCP3_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000FFFFL
+#define DCP3_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xFFFF0000L
+//DCP3_INPUT_CSC_CONTROL
+#define DCP3_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
+#define DCP3_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L
+//DCP3_INPUT_CSC_C11_C12
+#define DCP3_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
+#define DCP3_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
+#define DCP3_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000FFFFL
+#define DCP3_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xFFFF0000L
+//DCP3_INPUT_CSC_C13_C14
+#define DCP3_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
+#define DCP3_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
+#define DCP3_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000FFFFL
+#define DCP3_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xFFFF0000L
+//DCP3_INPUT_CSC_C21_C22
+#define DCP3_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
+#define DCP3_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
+#define DCP3_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000FFFFL
+#define DCP3_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xFFFF0000L
+//DCP3_INPUT_CSC_C23_C24
+#define DCP3_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
+#define DCP3_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
+#define DCP3_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000FFFFL
+#define DCP3_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xFFFF0000L
+//DCP3_INPUT_CSC_C31_C32
+#define DCP3_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
+#define DCP3_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
+#define DCP3_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000FFFFL
+#define DCP3_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xFFFF0000L
+//DCP3_INPUT_CSC_C33_C34
+#define DCP3_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
+#define DCP3_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
+#define DCP3_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000FFFFL
+#define DCP3_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xFFFF0000L
+//DCP3_OUTPUT_CSC_CONTROL
+#define DCP3_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
+#define DCP3_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L
+//DCP3_OUTPUT_CSC_C11_C12
+#define DCP3_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
+#define DCP3_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
+#define DCP3_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000FFFFL
+#define DCP3_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xFFFF0000L
+//DCP3_OUTPUT_CSC_C13_C14
+#define DCP3_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
+#define DCP3_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
+#define DCP3_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000FFFFL
+#define DCP3_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xFFFF0000L
+//DCP3_OUTPUT_CSC_C21_C22
+#define DCP3_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
+#define DCP3_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
+#define DCP3_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000FFFFL
+#define DCP3_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xFFFF0000L
+//DCP3_OUTPUT_CSC_C23_C24
+#define DCP3_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
+#define DCP3_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
+#define DCP3_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000FFFFL
+#define DCP3_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xFFFF0000L
+//DCP3_OUTPUT_CSC_C31_C32
+#define DCP3_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
+#define DCP3_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
+#define DCP3_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000FFFFL
+#define DCP3_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xFFFF0000L
+//DCP3_OUTPUT_CSC_C33_C34
+#define DCP3_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
+#define DCP3_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
+#define DCP3_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000FFFFL
+#define DCP3_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xFFFF0000L
+//DCP3_COMM_MATRIXA_TRANS_C11_C12
+#define DCP3_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
+#define DCP3_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
+#define DCP3_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000FFFFL
+#define DCP3_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xFFFF0000L
+//DCP3_COMM_MATRIXA_TRANS_C13_C14
+#define DCP3_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
+#define DCP3_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
+#define DCP3_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000FFFFL
+#define DCP3_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xFFFF0000L
+//DCP3_COMM_MATRIXA_TRANS_C21_C22
+#define DCP3_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
+#define DCP3_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
+#define DCP3_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000FFFFL
+#define DCP3_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xFFFF0000L
+//DCP3_COMM_MATRIXA_TRANS_C23_C24
+#define DCP3_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
+#define DCP3_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
+#define DCP3_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000FFFFL
+#define DCP3_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xFFFF0000L
+//DCP3_COMM_MATRIXA_TRANS_C31_C32
+#define DCP3_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
+#define DCP3_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
+#define DCP3_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000FFFFL
+#define DCP3_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xFFFF0000L
+//DCP3_COMM_MATRIXA_TRANS_C33_C34
+#define DCP3_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
+#define DCP3_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
+#define DCP3_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000FFFFL
+#define DCP3_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xFFFF0000L
+//DCP3_COMM_MATRIXB_TRANS_C11_C12
+#define DCP3_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
+#define DCP3_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
+#define DCP3_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000FFFFL
+#define DCP3_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xFFFF0000L
+//DCP3_COMM_MATRIXB_TRANS_C13_C14
+#define DCP3_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
+#define DCP3_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
+#define DCP3_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000FFFFL
+#define DCP3_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xFFFF0000L
+//DCP3_COMM_MATRIXB_TRANS_C21_C22
+#define DCP3_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
+#define DCP3_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
+#define DCP3_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000FFFFL
+#define DCP3_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xFFFF0000L
+//DCP3_COMM_MATRIXB_TRANS_C23_C24
+#define DCP3_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
+#define DCP3_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
+#define DCP3_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000FFFFL
+#define DCP3_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xFFFF0000L
+//DCP3_COMM_MATRIXB_TRANS_C31_C32
+#define DCP3_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
+#define DCP3_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
+#define DCP3_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000FFFFL
+#define DCP3_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xFFFF0000L
+//DCP3_COMM_MATRIXB_TRANS_C33_C34
+#define DCP3_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
+#define DCP3_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
+#define DCP3_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000FFFFL
+#define DCP3_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xFFFF0000L
+//DCP3_DENORM_CONTROL
+#define DCP3_DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
+#define DCP3_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
+#define DCP3_DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L
+#define DCP3_DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x00000010L
+//DCP3_OUT_ROUND_CONTROL
+#define DCP3_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
+#define DCP3_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000FL
+//DCP3_OUT_CLAMP_CONTROL_R_CR
+#define DCP3_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
+#define DCP3_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
+#define DCP3_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x00003FFFL
+#define DCP3_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3FFF0000L
+//DCP3_OUT_CLAMP_CONTROL_G_Y
+#define DCP3_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
+#define DCP3_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
+#define DCP3_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x00003FFFL
+#define DCP3_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3FFF0000L
+//DCP3_OUT_CLAMP_CONTROL_B_CB
+#define DCP3_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
+#define DCP3_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
+#define DCP3_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x00003FFFL
+#define DCP3_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3FFF0000L
+//DCP3_KEY_CONTROL
+#define DCP3_KEY_CONTROL__KEY_MODE__SHIFT 0x1
+#define DCP3_KEY_CONTROL__KEY_MODE_MASK 0x00000006L
+//DCP3_KEY_RANGE_ALPHA
+#define DCP3_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
+#define DCP3_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
+#define DCP3_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000FFFFL
+#define DCP3_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xFFFF0000L
+//DCP3_KEY_RANGE_RED
+#define DCP3_KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
+#define DCP3_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
+#define DCP3_KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000FFFFL
+#define DCP3_KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xFFFF0000L
+//DCP3_KEY_RANGE_GREEN
+#define DCP3_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
+#define DCP3_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
+#define DCP3_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000FFFFL
+#define DCP3_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xFFFF0000L
+//DCP3_KEY_RANGE_BLUE
+#define DCP3_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
+#define DCP3_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
+#define DCP3_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000FFFFL
+#define DCP3_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xFFFF0000L
+//DCP3_DEGAMMA_CONTROL
+#define DCP3_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
+#define DCP3_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
+#define DCP3_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
+#define DCP3_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L
+#define DCP3_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x00000300L
+#define DCP3_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L
+//DCP3_GAMUT_REMAP_CONTROL
+#define DCP3_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
+#define DCP3_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L
+//DCP3_GAMUT_REMAP_C11_C12
+#define DCP3_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
+#define DCP3_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
+#define DCP3_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000FFFFL
+#define DCP3_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xFFFF0000L
+//DCP3_GAMUT_REMAP_C13_C14
+#define DCP3_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
+#define DCP3_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
+#define DCP3_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000FFFFL
+#define DCP3_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xFFFF0000L
+//DCP3_GAMUT_REMAP_C21_C22
+#define DCP3_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
+#define DCP3_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
+#define DCP3_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000FFFFL
+#define DCP3_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xFFFF0000L
+//DCP3_GAMUT_REMAP_C23_C24
+#define DCP3_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
+#define DCP3_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
+#define DCP3_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000FFFFL
+#define DCP3_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xFFFF0000L
+//DCP3_GAMUT_REMAP_C31_C32
+#define DCP3_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
+#define DCP3_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
+#define DCP3_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000FFFFL
+#define DCP3_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xFFFF0000L
+//DCP3_GAMUT_REMAP_C33_C34
+#define DCP3_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
+#define DCP3_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
+#define DCP3_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000FFFFL
+#define DCP3_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xFFFF0000L
+//DCP3_DCP_SPATIAL_DITHER_CNTL
+#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
+#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
+#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
+#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
+#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
+#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
+#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L
+#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L
+#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x000000C0L
+#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L
+#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L
+#define DCP3_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L
+//DCP3_DCP_RANDOM_SEEDS
+#define DCP3_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
+#define DCP3_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
+#define DCP3_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
+#define DCP3_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000FFL
+#define DCP3_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000FF00L
+#define DCP3_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00FF0000L
+//DCP3_DCP_FP_CONVERTED_FIELD
+#define DCP3_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
+#define DCP3_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
+#define DCP3_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
+#define DCP3_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
+//DCP3_CUR_CONTROL
+#define DCP3_CUR_CONTROL__CURSOR_EN__SHIFT 0x0
+#define DCP3_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
+#define DCP3_CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
+#define DCP3_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT 0xb
+#define DCP3_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT 0xc
+#define DCP3_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
+#define DCP3_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
+#define DCP3_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
+#define DCP3_CUR_CONTROL__CURSOR_EN_MASK 0x00000001L
+#define DCP3_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L
+#define DCP3_CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L
+#define DCP3_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK 0x00000800L
+#define DCP3_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK 0x0000F000L
+#define DCP3_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L
+#define DCP3_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L
+#define DCP3_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L
+//DCP3_CUR_SURFACE_ADDRESS
+#define DCP3_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
+#define DCP3_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//DCP3_CUR_SIZE
+#define DCP3_CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
+#define DCP3_CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
+#define DCP3_CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000007FL
+#define DCP3_CUR_SIZE__CURSOR_WIDTH_MASK 0x007F0000L
+//DCP3_CUR_SURFACE_ADDRESS_HIGH
+#define DCP3_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP3_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP3_CUR_POSITION
+#define DCP3_CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
+#define DCP3_CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
+#define DCP3_CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
+#define DCP3_CUR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
+//DCP3_CUR_HOT_SPOT
+#define DCP3_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
+#define DCP3_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
+#define DCP3_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000007FL
+#define DCP3_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x007F0000L
+//DCP3_CUR_COLOR1
+#define DCP3_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
+#define DCP3_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
+#define DCP3_CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
+#define DCP3_CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000FFL
+#define DCP3_CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000FF00L
+#define DCP3_CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00FF0000L
+//DCP3_CUR_COLOR2
+#define DCP3_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
+#define DCP3_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
+#define DCP3_CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
+#define DCP3_CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000FFL
+#define DCP3_CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000FF00L
+#define DCP3_CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00FF0000L
+//DCP3_CUR_UPDATE
+#define DCP3_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
+#define DCP3_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
+#define DCP3_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
+#define DCP3_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define DCP3_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
+#define DCP3_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L
+#define DCP3_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L
+#define DCP3_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L
+#define DCP3_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+#define DCP3_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x06000000L
+//DCP3_CUR_REQUEST_FILTER_CNTL
+#define DCP3_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
+#define DCP3_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L
+//DCP3_CUR_STEREO_CONTROL
+#define DCP3_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
+#define DCP3_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
+#define DCP3_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
+#define DCP3_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
+#define DCP3_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x00003FF0L
+#define DCP3_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x03FF0000L
+//DCP3_DC_LUT_RW_MODE
+#define DCP3_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
+#define DCP3_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
+#define DCP3_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
+#define DCP3_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L
+#define DCP3_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x00010000L
+#define DCP3_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x00020000L
+//DCP3_DC_LUT_RW_INDEX
+#define DCP3_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
+#define DCP3_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000FFL
+//DCP3_DC_LUT_SEQ_COLOR
+#define DCP3_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
+#define DCP3_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000FFFFL
+//DCP3_DC_LUT_PWL_DATA
+#define DCP3_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
+#define DCP3_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
+#define DCP3_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000FFFFL
+#define DCP3_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xFFFF0000L
+//DCP3_DC_LUT_30_COLOR
+#define DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
+#define DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
+#define DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
+#define DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003FFL
+#define DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
+#define DCP3_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3FF00000L
+//DCP3_DC_LUT_VGA_ACCESS_ENABLE
+#define DCP3_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
+#define DCP3_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L
+//DCP3_DC_LUT_WRITE_EN_MASK
+#define DCP3_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define DCP3_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L
+//DCP3_DC_LUT_AUTOFILL
+#define DCP3_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
+#define DCP3_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
+#define DCP3_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L
+#define DCP3_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L
+//DCP3_DC_LUT_CONTROL
+#define DCP3_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
+#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
+#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
+#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
+#define DCP3_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
+#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
+#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
+#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
+#define DCP3_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
+#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
+#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
+#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
+#define DCP3_DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000FL
+#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L
+#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L
+#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000C0L
+#define DCP3_DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000F00L
+#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L
+#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L
+#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000C000L
+#define DCP3_DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000F0000L
+#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L
+#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L
+#define DCP3_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00C00000L
+//DCP3_DC_LUT_BLACK_OFFSET_BLUE
+#define DCP3_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
+#define DCP3_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL
+//DCP3_DC_LUT_BLACK_OFFSET_GREEN
+#define DCP3_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
+#define DCP3_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL
+//DCP3_DC_LUT_BLACK_OFFSET_RED
+#define DCP3_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
+#define DCP3_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL
+//DCP3_DC_LUT_WHITE_OFFSET_BLUE
+#define DCP3_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
+#define DCP3_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000FFFFL
+//DCP3_DC_LUT_WHITE_OFFSET_GREEN
+#define DCP3_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
+#define DCP3_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000FFFFL
+//DCP3_DC_LUT_WHITE_OFFSET_RED
+#define DCP3_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
+#define DCP3_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000FFFFL
+//DCP3_DCP_CRC_CONTROL
+#define DCP3_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
+#define DCP3_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
+#define DCP3_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
+#define DCP3_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L
+#define DCP3_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001CL
+#define DCP3_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L
+//DCP3_DCP_CRC_MASK
+#define DCP3_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
+#define DCP3_DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xFFFFFFFFL
+//DCP3_DCP_CRC_CURRENT
+#define DCP3_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
+#define DCP3_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xFFFFFFFFL
+//DCP3_DVMM_PTE_CONTROL
+#define DCP3_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
+#define DCP3_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
+#define DCP3_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
+#define DCP3_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
+#define DCP3_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
+#define DCP3_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
+#define DCP3_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
+#define DCP3_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
+#define DCP3_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
+#define DCP3_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
+#define DCP3_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
+#define DCP3_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
+//DCP3_DCP_CRC_LAST
+#define DCP3_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
+#define DCP3_DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xFFFFFFFFL
+//DCP3_DVMM_PTE_ARB_CONTROL
+#define DCP3_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
+#define DCP3_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
+#define DCP3_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
+#define DCP3_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
+//DCP3_GRPH_FLIP_RATE_CNTL
+#define DCP3_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
+#define DCP3_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
+#define DCP3_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x00000007L
+#define DCP3_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x00000008L
+//DCP3_DCP_GSL_CONTROL
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x4
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x14
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x15
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x17
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT 0x1a
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x000FFFF0L
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00100000L
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x00600000L
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x00800000L
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK 0x04000000L
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L
+#define DCP3_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xF0000000L
+//DCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK
+#define DCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
+#define DCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
+#define DCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000FL
+#define DCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000001F0L
+//DCP3_GRPH_STEREOSYNC_FLIP
+#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
+#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
+#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
+#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L
+#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
+#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
+#define DCP3_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
+//DCP3_HW_ROTATION
+#define DCP3_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
+#define DCP3_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x00000007L
+//DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL
+#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
+#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
+#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
+#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x00000001L
+#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x00000002L
+#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x0001FFF0L
+//DCP3_REGAMMA_CONTROL
+#define DCP3_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
+#define DCP3_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L
+//DCP3_REGAMMA_LUT_INDEX
+#define DCP3_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
+#define DCP3_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001FFL
+//DCP3_REGAMMA_LUT_DATA
+#define DCP3_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
+#define DCP3_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007FFFFL
+//DCP3_REGAMMA_LUT_WRITE_EN_MASK
+#define DCP3_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define DCP3_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
+//DCP3_REGAMMA_CNTLA_START_CNTL
+#define DCP3_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define DCP3_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
+#define DCP3_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+//DCP3_REGAMMA_CNTLA_SLOPE_CNTL
+#define DCP3_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+//DCP3_REGAMMA_CNTLA_END_CNTL1
+#define DCP3_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
+//DCP3_REGAMMA_CNTLA_END_CNTL2
+#define DCP3_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
+#define DCP3_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+#define DCP3_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+//DCP3_REGAMMA_CNTLA_REGION_0_1
+#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP3_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//DCP3_REGAMMA_CNTLA_REGION_2_3
+#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP3_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//DCP3_REGAMMA_CNTLA_REGION_4_5
+#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP3_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//DCP3_REGAMMA_CNTLA_REGION_6_7
+#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP3_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//DCP3_REGAMMA_CNTLA_REGION_8_9
+#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP3_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//DCP3_REGAMMA_CNTLA_REGION_10_11
+#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP3_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//DCP3_REGAMMA_CNTLA_REGION_12_13
+#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP3_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//DCP3_REGAMMA_CNTLA_REGION_14_15
+#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP3_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//DCP3_REGAMMA_CNTLB_START_CNTL
+#define DCP3_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define DCP3_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
+#define DCP3_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+//DCP3_REGAMMA_CNTLB_SLOPE_CNTL
+#define DCP3_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+//DCP3_REGAMMA_CNTLB_END_CNTL1
+#define DCP3_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
+//DCP3_REGAMMA_CNTLB_END_CNTL2
+#define DCP3_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
+#define DCP3_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+#define DCP3_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+//DCP3_REGAMMA_CNTLB_REGION_0_1
+#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP3_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//DCP3_REGAMMA_CNTLB_REGION_2_3
+#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP3_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//DCP3_REGAMMA_CNTLB_REGION_4_5
+#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP3_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//DCP3_REGAMMA_CNTLB_REGION_6_7
+#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP3_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//DCP3_REGAMMA_CNTLB_REGION_8_9
+#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP3_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//DCP3_REGAMMA_CNTLB_REGION_10_11
+#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP3_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//DCP3_REGAMMA_CNTLB_REGION_12_13
+#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP3_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//DCP3_REGAMMA_CNTLB_REGION_14_15
+#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP3_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//DCP3_ALPHA_CONTROL
+#define DCP3_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
+#define DCP3_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
+#define DCP3_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x00000001L
+#define DCP3_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x00000002L
+//DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS
+#define DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH
+#define DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS
+#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
+#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
+#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
+#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
+#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
+#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
+#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
+#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0x000FFFFFL
+#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x01000000L
+#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x02000000L
+#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x04000000L
+#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000L
+#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000L
+#define DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000L
+//DCP3_GRPH_XDMA_FLIP_TIMEOUT
+#define DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT 0x0
+#define DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT 0x1
+#define DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT 0x2
+#define DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK 0x00000001L
+#define DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK 0x00000002L
+#define DCP3_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK 0x00000004L
+//DCP3_GRPH_XDMA_FLIP_AVG_DELAY
+#define DCP3_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT 0x0
+#define DCP3_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT 0x10
+#define DCP3_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK 0x0000FFFFL
+#define DCP3_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK 0x00FF0000L
+//DCP3_GRPH_SURFACE_COUNTER_CONTROL
+#define DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0
+#define DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1
+#define DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9
+#define DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x00000001L
+#define DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x0000001EL
+#define DCP3_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x00000200L
+//DCP3_GRPH_SURFACE_COUNTER_OUTPUT
+#define DCP3_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0
+#define DCP3_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10
+#define DCP3_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0x0000FFFFL
+#define DCP3_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_lb3_dispdec
+//LB3_LB_DATA_FORMAT
+#define LB3_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
+#define LB3_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
+#define LB3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
+#define LB3_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
+#define LB3_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
+#define LB3_LB_DATA_FORMAT__PREFILL_EN__SHIFT 0x8
+#define LB3_LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
+#define LB3_LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
+#define LB3_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
+#define LB3_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
+#define LB3_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
+#define LB3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
+#define LB3_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
+#define LB3_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
+#define LB3_LB_DATA_FORMAT__PREFILL_EN_MASK 0x00000100L
+#define LB3_LB_DATA_FORMAT__PREFETCH_MASK 0x00001000L
+#define LB3_LB_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
+#define LB3_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
+//LB3_LB_MEMORY_CTRL
+#define LB3_LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
+#define LB3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+#define LB3_LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
+#define LB3_LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00001FFFL
+#define LB3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
+#define LB3_LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
+//LB3_LB_MEMORY_SIZE_STATUS
+#define LB3_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
+#define LB3_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00001FFFL
+//LB3_LB_DESKTOP_HEIGHT
+#define LB3_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
+#define LB3_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
+//LB3_LB_VLINE_START_END
+#define LB3_LB_VLINE_START_END__VLINE_START__SHIFT 0x0
+#define LB3_LB_VLINE_START_END__VLINE_END__SHIFT 0x10
+#define LB3_LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
+#define LB3_LB_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
+#define LB3_LB_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
+#define LB3_LB_VLINE_START_END__VLINE_INV_MASK 0x80000000L
+//LB3_LB_VLINE2_START_END
+#define LB3_LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
+#define LB3_LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
+#define LB3_LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
+#define LB3_LB_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
+#define LB3_LB_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
+#define LB3_LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
+//LB3_LB_V_COUNTER
+#define LB3_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
+#define LB3_LB_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
+//LB3_LB_SNAPSHOT_V_COUNTER
+#define LB3_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
+#define LB3_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
+//LB3_LB_INTERRUPT_MASK
+#define LB3_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
+#define LB3_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
+#define LB3_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
+#define LB3_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
+#define LB3_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
+#define LB3_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
+//LB3_LB_VLINE_STATUS
+#define LB3_LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
+#define LB3_LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
+#define LB3_LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
+#define LB3_LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
+#define LB3_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
+#define LB3_LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
+#define LB3_LB_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
+#define LB3_LB_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
+#define LB3_LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
+#define LB3_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
+//LB3_LB_VLINE2_STATUS
+#define LB3_LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
+#define LB3_LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
+#define LB3_LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
+#define LB3_LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
+#define LB3_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
+#define LB3_LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
+#define LB3_LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
+#define LB3_LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
+#define LB3_LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
+#define LB3_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
+//LB3_LB_VBLANK_STATUS
+#define LB3_LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
+#define LB3_LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
+#define LB3_LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
+#define LB3_LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
+#define LB3_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
+#define LB3_LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
+#define LB3_LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
+#define LB3_LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
+#define LB3_LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
+#define LB3_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
+//LB3_LB_SYNC_RESET_SEL
+#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
+#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
+#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
+#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
+#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
+#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
+#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
+#define LB3_LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
+//LB3_LB_BLACK_KEYER_R_CR
+#define LB3_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
+#define LB3_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
+//LB3_LB_BLACK_KEYER_G_Y
+#define LB3_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
+#define LB3_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
+//LB3_LB_BLACK_KEYER_B_CB
+#define LB3_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
+#define LB3_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
+//LB3_LB_KEYER_COLOR_CTRL
+#define LB3_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
+#define LB3_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
+#define LB3_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
+#define LB3_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
+//LB3_LB_KEYER_COLOR_R_CR
+#define LB3_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
+#define LB3_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
+//LB3_LB_KEYER_COLOR_G_Y
+#define LB3_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
+#define LB3_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
+//LB3_LB_KEYER_COLOR_B_CB
+#define LB3_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
+#define LB3_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
+//LB3_LB_KEYER_COLOR_REP_R_CR
+#define LB3_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
+#define LB3_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
+//LB3_LB_KEYER_COLOR_REP_G_Y
+#define LB3_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
+#define LB3_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
+//LB3_LB_KEYER_COLOR_REP_B_CB
+#define LB3_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
+#define LB3_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
+//LB3_LB_BUFFER_LEVEL_STATUS
+#define LB3_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
+#define LB3_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
+#define LB3_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
+#define LB3_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
+#define LB3_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
+#define LB3_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
+#define LB3_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
+#define LB3_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
+//LB3_LB_BUFFER_URGENCY_CTRL
+#define LB3_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
+#define LB3_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
+#define LB3_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
+#define LB3_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
+//LB3_LB_BUFFER_URGENCY_STATUS
+#define LB3_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
+#define LB3_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
+#define LB3_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
+#define LB3_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
+//LB3_LB_BUFFER_STATUS
+#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
+#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
+#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
+#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
+#define LB3_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
+#define LB3_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
+#define LB3_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
+#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
+#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
+#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
+#define LB3_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
+#define LB3_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
+#define LB3_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
+#define LB3_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
+//LB3_LB_NO_OUTSTANDING_REQ_STATUS
+#define LB3_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
+#define LB3_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
+//LB3_MVP_AFR_FLIP_MODE
+#define LB3_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
+#define LB3_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L
+//LB3_MVP_AFR_FLIP_FIFO_CNTL
+#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
+#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
+#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
+#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
+#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000FL
+#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L
+#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L
+#define LB3_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L
+//LB3_MVP_FLIP_LINE_NUM_INSERT
+#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
+#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
+#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
+#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
+#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L
+#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007FFF00L
+#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3F000000L
+#define LB3_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L
+//LB3_DC_MVP_LB_CONTROL
+#define LB3_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
+#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
+#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
+#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
+#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
+#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
+#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
+#define LB3_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L
+#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L
+#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L
+#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L
+#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L
+#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L
+#define LB3_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L
+
+
+// addressBlock: dce_dc_dcfe3_dispdec
+//DCFE3_DCFE_CLOCK_CONTROL
+#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
+#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
+#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
+#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf
+#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT 0x11
+#define DCFE3_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
+#define DCFE3_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
+#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L
+#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L
+#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L
+#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x00008000L
+#define DCFE3_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK 0x00020000L
+#define DCFE3_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1F000000L
+#define DCFE3_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000L
+//DCFE3_DCFE_SOFT_RESET
+#define DCFE3_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
+#define DCFE3_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
+#define DCFE3_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
+#define DCFE3_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
+#define DCFE3_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
+#define DCFE3_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5
+#define DCFE3_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
+#define DCFE3_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x00000002L
+#define DCFE3_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x00000004L
+#define DCFE3_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x00000008L
+#define DCFE3_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
+#define DCFE3_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x00000020L
+//DCFE3_DCFE_MEM_PWR_CTRL
+#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
+#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
+#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
+#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
+#define DCFE3_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
+#define DCFE3_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
+#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
+#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
+#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x00000003L
+#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x00000004L
+#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x00000018L
+#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x00000020L
+#define DCFE3_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
+#define DCFE3_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x00000100L
+#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x00000600L
+#define DCFE3_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x00000800L
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x00003000L
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x00004000L
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x00018000L
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x00020000L
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0x000C0000L
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x00100000L
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x00600000L
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x00800000L
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x03000000L
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x04000000L
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000L
+#define DCFE3_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000L
+//DCFE3_DCFE_MEM_PWR_CTRL2
+#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
+#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
+#define DCFE3_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
+#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
+#define DCFE3_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
+#define DCFE3_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
+#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
+#define DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
+#define DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
+#define DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
+#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
+#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
+#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x00000003L
+#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
+#define DCFE3_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
+#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0x000000C0L
+#define DCFE3_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x00000300L
+#define DCFE3_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0x00000C00L
+#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x00003000L
+#define DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0x0000C000L
+#define DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x00030000L
+#define DCFE3_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x00040000L
+#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x00600000L
+#define DCFE3_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x00800000L
+//DCFE3_DCFE_MEM_PWR_STATUS
+#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
+#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
+#define DCFE3_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
+#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
+#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
+#define DCFE3_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
+#define DCFE3_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
+#define DCFE3_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
+#define DCFE3_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
+#define DCFE3_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
+#define DCFE3_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
+#define DCFE3_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
+#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x00000003L
+#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0x0000000CL
+#define DCFE3_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x00000030L
+#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0x000000C0L
+#define DCFE3_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x00000300L
+#define DCFE3_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0x00000C00L
+#define DCFE3_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x00003000L
+#define DCFE3_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0x0000C000L
+#define DCFE3_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x00030000L
+#define DCFE3_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0x000C0000L
+#define DCFE3_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x00300000L
+#define DCFE3_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0x00C00000L
+//DCFE3_DCFE_MISC
+#define DCFE3_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
+#define DCFE3_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
+//DCFE3_DCFE_FLUSH
+#define DCFE3_DCFE_FLUSH__FLUSH_OCCURED__SHIFT 0x0
+#define DCFE3_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
+#define DCFE3_DCFE_FLUSH__FLUSH_DEEP__SHIFT 0x2
+#define DCFE3_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
+#define DCFE3_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
+#define DCFE3_DCFE_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
+#define DCFE3_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
+#define DCFE3_DCFE_FLUSH__FLUSH_DEEP_MASK 0x00000004L
+#define DCFE3_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
+#define DCFE3_DCFE_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
+
+
+// addressBlock: dce_dc_dc_perfmon6_dispdec
+//DC_PERFMON6_PERFCOUNTER_CNTL
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON6_PERFCOUNTER_CNTL2
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON6_PERFCOUNTER_STATE
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON6_PERFMON_CNTL
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON6_PERFMON_CNTL2
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON6_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON6_PERFMON_CVALUE_LOW
+#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON6_PERFMON_HI
+#define DC_PERFMON6_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON6_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON6_PERFMON_LOW
+#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dmif_pg3_dispdec
+//DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1
+#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
+#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
+//DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2
+#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
+#define DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
+//DMIF_PG3_DPG_WATERMARK_MASK_CONTROL
+#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x4
+#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT 0xc
+#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0xf
+#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x12
+#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT 0x13
+#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT 0x14
+#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000007L
+#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000070L
+#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000700L
+#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK 0x00007000L
+#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00038000L
+#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x00040000L
+#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK 0x00080000L
+#define DMIF_PG3_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK 0x3FF00000L
+//DMIF_PG3_DPG_PIPE_URGENCY_CONTROL
+#define DMIF_PG3_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+#define DMIF_PG3_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+#define DMIF_PG3_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
+#define DMIF_PG3_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
+//DMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL
+#define DMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT 0x0
+#define DMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT 0x10
+#define DMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK 0x0000FFFFL
+#define DMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK 0xFFFF0000L
+//DMIF_PG3_DPG_PIPE_STUTTER_CONTROL
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT 0x10
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x14
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x15
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x16
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x17
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x1a
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x1b
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK 0x00010000L
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00100000L
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00200000L
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00400000L
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00800000L
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x04000000L
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x08000000L
+//DMIF_PG3_DPG_PIPE_STUTTER_CONTROL2
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x0
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT 0x10
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0x0000FFFFL
+#define DMIF_PG3_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
+//DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL
+#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT 0x0
+#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT 0x1
+#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT 0xf
+#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK 0x00000001L
+#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK 0x00000002L
+#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
+#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
+#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
+#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
+#define DMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK 0xFFFF8000L
+//DMIF_PG3_DPG_REPEATER_PROGRAM
+#define DMIF_PG3_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+#define DMIF_PG3_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+#define DMIF_PG3_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
+#define DMIF_PG3_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
+//DMIF_PG3_DPG_CHK_PRE_PROC_CNTL
+#define DMIF_PG3_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+#define DMIF_PG3_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
+//DMIF_PG3_DPG_DVMM_STATUS
+#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT 0x0
+#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT 0x1
+#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT 0x4
+#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT 0x5
+#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK 0x00000001L
+#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK 0x00000002L
+#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK 0x00000010L
+#define DMIF_PG3_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK 0x00000020L
+
+
+// addressBlock: dce_dc_scl3_dispdec
+//SCL3_SCL_COEF_RAM_SELECT
+#define SCL3_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define SCL3_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
+#define SCL3_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
+#define SCL3_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000FL
+#define SCL3_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000F00L
+#define SCL3_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00070000L
+//SCL3_SCL_COEF_RAM_TAP_DATA
+#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+#define SCL3_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+//SCL3_SCL_MODE
+#define SCL3_SCL_MODE__SCL_MODE__SHIFT 0x0
+#define SCL3_SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
+#define SCL3_SCL_MODE__SCL_MODE_MASK 0x00000003L
+#define SCL3_SCL_MODE__SCL_PSCL_EN_MASK 0x00000010L
+//SCL3_SCL_TAP_CONTROL
+#define SCL3_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
+#define SCL3_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
+#define SCL3_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
+#define SCL3_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000F00L
+//SCL3_SCL_CONTROL
+#define SCL3_SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+#define SCL3_SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
+#define SCL3_SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+#define SCL3_SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
+//SCL3_SCL_BYPASS_CONTROL
+#define SCL3_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
+#define SCL3_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L
+//SCL3_SCL_MANUAL_REPLICATE_CONTROL
+#define SCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+#define SCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+#define SCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+#define SCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+//SCL3_SCL_AUTOMATIC_MODE_CONTROL
+#define SCL3_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
+#define SCL3_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
+#define SCL3_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
+#define SCL3_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
+//SCL3_SCL_HORZ_FILTER_CONTROL
+#define SCL3_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
+#define SCL3_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCL3_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L
+#define SCL3_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+//SCL3_SCL_HORZ_FILTER_SCALE_RATIO
+#define SCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+#define SCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+//SCL3_SCL_HORZ_FILTER_INIT
+#define SCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+#define SCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+#define SCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+#define SCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+//SCL3_SCL_VERT_FILTER_CONTROL
+#define SCL3_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
+#define SCL3_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCL3_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L
+#define SCL3_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+//SCL3_SCL_VERT_FILTER_SCALE_RATIO
+#define SCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+#define SCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+//SCL3_SCL_VERT_FILTER_INIT
+#define SCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+#define SCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+#define SCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+#define SCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
+//SCL3_SCL_VERT_FILTER_INIT_BOT
+#define SCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+#define SCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+#define SCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+#define SCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
+//SCL3_SCL_ROUND_OFFSET
+#define SCL3_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
+#define SCL3_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+#define SCL3_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
+#define SCL3_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
+//SCL3_SCL_UPDATE
+#define SCL3_SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+#define SCL3_SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
+#define SCL3_SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
+#define SCL3_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
+#define SCL3_SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+#define SCL3_SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
+#define SCL3_SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
+#define SCL3_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
+//SCL3_SCL_F_SHARP_CONTROL
+#define SCL3_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
+#define SCL3_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
+#define SCL3_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
+#define SCL3_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
+#define SCL3_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L
+#define SCL3_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L
+#define SCL3_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L
+#define SCL3_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L
+//SCL3_SCL_ALU_CONTROL
+#define SCL3_SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
+#define SCL3_SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
+//SCL3_SCL_COEF_RAM_CONFLICT_STATUS
+#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
+#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
+#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
+#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
+#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
+#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L
+#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L
+#define SCL3_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
+//SCL3_VIEWPORT_START_SECONDARY
+#define SCL3_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
+#define SCL3_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
+#define SCL3_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
+#define SCL3_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
+//SCL3_VIEWPORT_START
+#define SCL3_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
+#define SCL3_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
+#define SCL3_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
+#define SCL3_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
+//SCL3_VIEWPORT_SIZE
+#define SCL3_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
+#define SCL3_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
+#define SCL3_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003FFFL
+#define SCL3_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3FFF0000L
+//SCL3_EXT_OVERSCAN_LEFT_RIGHT
+#define SCL3_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+#define SCL3_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+#define SCL3_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+#define SCL3_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+//SCL3_EXT_OVERSCAN_TOP_BOTTOM
+#define SCL3_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+#define SCL3_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+#define SCL3_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+#define SCL3_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+//SCL3_SCL_MODE_CHANGE_DET1
+#define SCL3_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
+#define SCL3_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
+#define SCL3_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
+#define SCL3_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
+#define SCL3_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
+#define SCL3_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
+//SCL3_SCL_MODE_CHANGE_DET2
+#define SCL3_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
+#define SCL3_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
+//SCL3_SCL_MODE_CHANGE_DET3
+#define SCL3_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
+#define SCL3_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
+#define SCL3_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
+#define SCL3_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
+//SCL3_SCL_MODE_CHANGE_MASK
+#define SCL3_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
+#define SCL3_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_blnd3_dispdec
+//BLND3_BLND_CONTROL
+#define BLND3_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
+#define BLND3_BLND_CONTROL__BLND_MODE__SHIFT 0x8
+#define BLND3_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
+#define BLND3_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
+#define BLND3_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
+#define BLND3_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
+#define BLND3_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
+#define BLND3_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
+#define BLND3_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
+#define BLND3_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
+#define BLND3_BLND_CONTROL__BLND_MODE_MASK 0x00000300L
+#define BLND3_BLND_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
+#define BLND3_BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
+#define BLND3_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
+#define BLND3_BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
+#define BLND3_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
+#define BLND3_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
+#define BLND3_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
+//BLND3_BLND_SM_CONTROL2
+#define BLND3_BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0
+#define BLND3_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
+#define BLND3_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
+#define BLND3_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+#define BLND3_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+#define BLND3_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
+#define BLND3_BLND_SM_CONTROL2__SM_MODE_MASK 0x00000007L
+#define BLND3_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
+#define BLND3_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
+#define BLND3_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+#define BLND3_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+#define BLND3_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
+//BLND3_BLND_CONTROL2
+#define BLND3_BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
+#define BLND3_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
+#define BLND3_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
+#define BLND3_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
+#define BLND3_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
+#define BLND3_BLND_CONTROL2__PTI_ENABLE_MASK 0x00000001L
+#define BLND3_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
+#define BLND3_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
+#define BLND3_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
+#define BLND3_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
+//BLND3_BLND_UPDATE
+#define BLND3_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
+#define BLND3_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
+#define BLND3_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
+#define BLND3_BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
+#define BLND3_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
+#define BLND3_BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
+//BLND3_BLND_UNDERFLOW_INTERRUPT
+#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
+#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
+#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
+#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
+#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
+#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
+#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
+#define BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
+//BLND3_BLND_V_UPDATE_LOCK
+#define BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
+#define BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
+#define BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
+#define BLND3_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
+#define BLND3_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
+#define BLND3_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
+#define BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
+#define BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
+#define BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
+#define BLND3_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
+#define BLND3_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
+#define BLND3_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
+//BLND3_BLND_REG_UPDATE_STATUS
+#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
+#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
+#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
+#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
+#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
+#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
+#define BLND3_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
+#define BLND3_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
+#define BLND3_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
+#define BLND3_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
+#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
+#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
+#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
+#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
+#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
+#define BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
+#define BLND3_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
+#define BLND3_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
+#define BLND3_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
+#define BLND3_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
+
+
+// addressBlock: dce_dc_crtc3_dispdec
+//CRTC3_CRTC_H_BLANK_EARLY_NUM
+#define CRTC3_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
+#define CRTC3_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
+#define CRTC3_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
+#define CRTC3_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
+//CRTC3_CRTC_H_TOTAL
+#define CRTC3_CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
+#define CRTC3_CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
+//CRTC3_CRTC_H_BLANK_START_END
+#define CRTC3_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
+#define CRTC3_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
+#define CRTC3_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
+#define CRTC3_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
+//CRTC3_CRTC_H_SYNC_A
+#define CRTC3_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
+#define CRTC3_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
+#define CRTC3_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
+#define CRTC3_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
+//CRTC3_CRTC_H_SYNC_A_CNTL
+#define CRTC3_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
+#define CRTC3_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
+#define CRTC3_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
+#define CRTC3_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
+#define CRTC3_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
+#define CRTC3_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
+//CRTC3_CRTC_H_SYNC_B
+#define CRTC3_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
+#define CRTC3_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
+#define CRTC3_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
+#define CRTC3_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
+//CRTC3_CRTC_H_SYNC_B_CNTL
+#define CRTC3_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
+#define CRTC3_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
+#define CRTC3_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
+#define CRTC3_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
+#define CRTC3_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
+#define CRTC3_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
+//CRTC3_CRTC_VBI_END
+#define CRTC3_CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
+#define CRTC3_CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
+#define CRTC3_CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
+#define CRTC3_CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
+//CRTC3_CRTC_V_TOTAL
+#define CRTC3_CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
+#define CRTC3_CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
+//CRTC3_CRTC_V_TOTAL_MIN
+#define CRTC3_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
+#define CRTC3_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
+//CRTC3_CRTC_V_TOTAL_MAX
+#define CRTC3_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
+#define CRTC3_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
+#define CRTC3_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
+#define CRTC3_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
+//CRTC3_CRTC_V_TOTAL_CONTROL
+#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
+#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
+#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
+#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
+#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
+#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
+#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
+#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
+#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
+#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
+#define CRTC3_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+//CRTC3_CRTC_V_TOTAL_INT_STATUS
+#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+#define CRTC3_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+//CRTC3_CRTC_VSYNC_NOM_INT_STATUS
+#define CRTC3_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
+#define CRTC3_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+#define CRTC3_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
+#define CRTC3_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+//CRTC3_CRTC_V_BLANK_START_END
+#define CRTC3_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
+#define CRTC3_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
+#define CRTC3_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
+#define CRTC3_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
+//CRTC3_CRTC_V_SYNC_A
+#define CRTC3_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
+#define CRTC3_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
+#define CRTC3_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
+#define CRTC3_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
+//CRTC3_CRTC_V_SYNC_A_CNTL
+#define CRTC3_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
+#define CRTC3_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
+//CRTC3_CRTC_V_SYNC_B
+#define CRTC3_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
+#define CRTC3_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
+#define CRTC3_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
+#define CRTC3_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
+//CRTC3_CRTC_V_SYNC_B_CNTL
+#define CRTC3_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
+#define CRTC3_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
+//CRTC3_CRTC_DTMTEST_CNTL
+#define CRTC3_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
+#define CRTC3_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
+#define CRTC3_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
+#define CRTC3_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
+//CRTC3_CRTC_DTMTEST_STATUS_POSITION
+#define CRTC3_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
+#define CRTC3_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
+#define CRTC3_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
+#define CRTC3_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTC3_CRTC_TRIGA_CNTL
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
+#define CRTC3_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
+//CRTC3_CRTC_TRIGA_MANUAL_TRIG
+#define CRTC3_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
+#define CRTC3_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+//CRTC3_CRTC_TRIGB_CNTL
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
+#define CRTC3_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
+//CRTC3_CRTC_TRIGB_MANUAL_TRIG
+#define CRTC3_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
+#define CRTC3_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+//CRTC3_CRTC_FORCE_COUNT_NOW_CNTL
+#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+#define CRTC3_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+//CRTC3_CRTC_FLOW_CONTROL
+#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
+#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+#define CRTC3_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+//CRTC3_CRTC_STEREO_FORCE_NEXT_EYE
+#define CRTC3_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+#define CRTC3_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+#define CRTC3_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
+#define CRTC3_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+#define CRTC3_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+#define CRTC3_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+//CRTC3_CRTC_AVSYNC_COUNTER
+#define CRTC3_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
+#define CRTC3_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
+//CRTC3_CRTC_CONTROL
+#define CRTC3_CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTC3_CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
+#define CRTC3_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
+#define CRTC3_CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
+#define CRTC3_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
+#define CRTC3_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
+#define CRTC3_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+#define CRTC3_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
+#define CRTC3_CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
+#define CRTC3_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+#define CRTC3_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+#define CRTC3_CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
+#define CRTC3_CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
+#define CRTC3_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
+#define CRTC3_CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
+#define CRTC3_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
+#define CRTC3_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+#define CRTC3_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+#define CRTC3_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
+#define CRTC3_CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
+#define CRTC3_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+#define CRTC3_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+//CRTC3_CRTC_BLANK_CONTROL
+#define CRTC3_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
+#define CRTC3_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
+#define CRTC3_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
+#define CRTC3_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
+#define CRTC3_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
+#define CRTC3_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
+//CRTC3_CRTC_INTERLACE_CONTROL
+#define CRTC3_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
+#define CRTC3_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+#define CRTC3_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
+#define CRTC3_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+//CRTC3_CRTC_INTERLACE_STATUS
+#define CRTC3_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+#define CRTC3_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
+#define CRTC3_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+#define CRTC3_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+//CRTC3_CRTC_FIELD_INDICATION_CONTROL
+#define CRTC3_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
+#define CRTC3_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
+#define CRTC3_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
+#define CRTC3_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
+//CRTC3_CRTC_PIXEL_DATA_READBACK0
+#define CRTC3_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+#define CRTC3_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+#define CRTC3_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
+#define CRTC3_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
+//CRTC3_CRTC_PIXEL_DATA_READBACK1
+#define CRTC3_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
+#define CRTC3_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
+//CRTC3_CRTC_STATUS
+#define CRTC3_CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
+#define CRTC3_CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
+#define CRTC3_CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
+#define CRTC3_CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
+#define CRTC3_CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
+#define CRTC3_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+#define CRTC3_CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
+#define CRTC3_CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
+#define CRTC3_CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
+#define CRTC3_CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L
+#define CRTC3_CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
+#define CRTC3_CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
+#define CRTC3_CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
+#define CRTC3_CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
+#define CRTC3_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+#define CRTC3_CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L
+#define CRTC3_CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
+#define CRTC3_CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
+//CRTC3_CRTC_STATUS_POSITION
+#define CRTC3_CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
+#define CRTC3_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
+#define CRTC3_CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
+#define CRTC3_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTC3_CRTC_NOM_VERT_POSITION
+#define CRTC3_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
+#define CRTC3_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
+//CRTC3_CRTC_STATUS_FRAME_COUNT
+#define CRTC3_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
+#define CRTC3_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
+//CRTC3_CRTC_STATUS_VF_COUNT
+#define CRTC3_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
+#define CRTC3_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
+//CRTC3_CRTC_STATUS_HV_COUNT
+#define CRTC3_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
+#define CRTC3_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
+//CRTC3_CRTC_COUNT_CONTROL
+#define CRTC3_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
+#define CRTC3_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
+#define CRTC3_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+#define CRTC3_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+//CRTC3_CRTC_COUNT_RESET
+#define CRTC3_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
+#define CRTC3_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
+//CRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define CRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+#define CRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+//CRTC3_CRTC_VERT_SYNC_CONTROL
+#define CRTC3_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+#define CRTC3_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+#define CRTC3_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+#define CRTC3_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+#define CRTC3_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+#define CRTC3_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+//CRTC3_CRTC_STEREO_STATUS
+#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
+#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
+#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
+#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
+#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
+#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
+#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
+#define CRTC3_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+//CRTC3_CRTC_STEREO_CONTROL
+#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
+#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+#define CRTC3_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+#define CRTC3_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
+#define CRTC3_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
+#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
+#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
+#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+#define CRTC3_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+#define CRTC3_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
+#define CRTC3_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+#define CRTC3_CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
+//CRTC3_CRTC_SNAPSHOT_STATUS
+#define CRTC3_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
+#define CRTC3_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
+#define CRTC3_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+#define CRTC3_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
+#define CRTC3_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
+#define CRTC3_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+//CRTC3_CRTC_SNAPSHOT_CONTROL
+#define CRTC3_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+#define CRTC3_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+//CRTC3_CRTC_SNAPSHOT_POSITION
+#define CRTC3_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+#define CRTC3_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+#define CRTC3_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
+#define CRTC3_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTC3_CRTC_SNAPSHOT_FRAME
+#define CRTC3_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+#define CRTC3_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+//CRTC3_CRTC_START_LINE_CONTROL
+#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
+#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
+#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
+#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
+#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
+#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
+#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
+#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
+#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
+#define CRTC3_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
+//CRTC3_CRTC_INTERRUPT_CONTROL
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+#define CRTC3_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+//CRTC3_CRTC_UPDATE_LOCK
+#define CRTC3_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
+#define CRTC3_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
+//CRTC3_CRTC_DOUBLE_BUFFER_CONTROL
+#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
+#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
+#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
+#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
+#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
+#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
+#define CRTC3_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
+//CRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE
+#define CRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
+#define CRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
+//CRTC3_CRTC_TEST_PATTERN_CONTROL
+#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
+#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
+#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
+#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
+#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
+#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
+#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
+#define CRTC3_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
+//CRTC3_CRTC_TEST_PATTERN_PARAMETERS
+#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
+#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
+#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
+#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
+#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
+#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
+#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
+#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
+#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
+#define CRTC3_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
+//CRTC3_CRTC_TEST_PATTERN_COLOR
+#define CRTC3_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
+#define CRTC3_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
+#define CRTC3_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
+#define CRTC3_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
+//CRTC3_CRTC_MASTER_UPDATE_LOCK
+#define CRTC3_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
+#define CRTC3_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
+#define CRTC3_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
+#define CRTC3_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
+#define CRTC3_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
+#define CRTC3_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
+//CRTC3_CRTC_MASTER_UPDATE_MODE
+#define CRTC3_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
+#define CRTC3_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
+#define CRTC3_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
+#define CRTC3_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
+//CRTC3_CRTC_MVP_INBAND_CNTL_INSERT
+#define CRTC3_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
+#define CRTC3_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
+#define CRTC3_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
+#define CRTC3_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
+//CRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER
+#define CRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
+#define CRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
+//CRTC3_CRTC_MVP_STATUS
+#define CRTC3_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
+#define CRTC3_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
+#define CRTC3_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
+#define CRTC3_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
+#define CRTC3_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
+#define CRTC3_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
+#define CRTC3_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
+#define CRTC3_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
+//CRTC3_CRTC_MASTER_EN
+#define CRTC3_CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTC3_CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
+//CRTC3_CRTC_ALLOW_STOP_OFF_V_CNT
+#define CRTC3_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
+#define CRTC3_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
+#define CRTC3_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
+#define CRTC3_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
+//CRTC3_CRTC_V_UPDATE_INT_STATUS
+#define CRTC3_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
+#define CRTC3_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
+#define CRTC3_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
+#define CRTC3_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
+//CRTC3_CRTC_OVERSCAN_COLOR
+#define CRTC3_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
+#define CRTC3_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
+#define CRTC3_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
+#define CRTC3_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
+#define CRTC3_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
+#define CRTC3_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
+//CRTC3_CRTC_OVERSCAN_COLOR_EXT
+#define CRTC3_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
+#define CRTC3_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
+#define CRTC3_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
+#define CRTC3_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
+#define CRTC3_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
+#define CRTC3_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
+//CRTC3_CRTC_BLANK_DATA_COLOR
+#define CRTC3_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+#define CRTC3_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+#define CRTC3_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+#define CRTC3_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+#define CRTC3_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+#define CRTC3_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+//CRTC3_CRTC_BLANK_DATA_COLOR_EXT
+#define CRTC3_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+#define CRTC3_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+#define CRTC3_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+#define CRTC3_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
+#define CRTC3_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
+#define CRTC3_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
+//CRTC3_CRTC_BLACK_COLOR
+#define CRTC3_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
+#define CRTC3_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
+#define CRTC3_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
+#define CRTC3_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
+#define CRTC3_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+#define CRTC3_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+//CRTC3_CRTC_BLACK_COLOR_EXT
+#define CRTC3_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+#define CRTC3_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+#define CRTC3_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+#define CRTC3_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
+#define CRTC3_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
+#define CRTC3_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
+//CRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION
+#define CRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+#define CRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+#define CRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
+#define CRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
+//CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL
+#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+#define CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+//CRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION
+#define CRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+#define CRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
+//CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL
+#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+#define CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+//CRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION
+#define CRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+#define CRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
+//CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL
+#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+#define CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+//CRTC3_CRTC_CRC_CNTL
+#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
+#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
+#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
+#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
+#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
+#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
+#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
+#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
+#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
+#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
+#define CRTC3_CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
+//CRTC3_CRTC_CRC0_WINDOWA_X_CONTROL
+#define CRTC3_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
+#define CRTC3_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
+#define CRTC3_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
+#define CRTC3_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
+//CRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL
+#define CRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
+#define CRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
+#define CRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
+#define CRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
+//CRTC3_CRTC_CRC0_WINDOWB_X_CONTROL
+#define CRTC3_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
+#define CRTC3_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
+#define CRTC3_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
+#define CRTC3_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
+//CRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL
+#define CRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
+#define CRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
+#define CRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
+#define CRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
+//CRTC3_CRTC_CRC0_DATA_RG
+#define CRTC3_CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+#define CRTC3_CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+#define CRTC3_CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+#define CRTC3_CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+//CRTC3_CRTC_CRC0_DATA_B
+#define CRTC3_CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+#define CRTC3_CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+//CRTC3_CRTC_CRC1_WINDOWA_X_CONTROL
+#define CRTC3_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
+#define CRTC3_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
+#define CRTC3_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
+#define CRTC3_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
+//CRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL
+#define CRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
+#define CRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
+#define CRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
+#define CRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
+//CRTC3_CRTC_CRC1_WINDOWB_X_CONTROL
+#define CRTC3_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
+#define CRTC3_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
+#define CRTC3_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
+#define CRTC3_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
+//CRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL
+#define CRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
+#define CRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
+#define CRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
+#define CRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
+//CRTC3_CRTC_CRC1_DATA_RG
+#define CRTC3_CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+#define CRTC3_CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+#define CRTC3_CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+#define CRTC3_CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+//CRTC3_CRTC_CRC1_DATA_B
+#define CRTC3_CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+#define CRTC3_CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+//CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
+//CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START
+#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
+#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
+#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
+#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
+//CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END
+#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
+#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
+#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
+#define CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
+//CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
+#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
+#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
+#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
+#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
+#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
+#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
+#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
+//CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL
+#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
+#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
+#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
+#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
+#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
+#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
+//CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
+#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
+#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
+#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
+#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
+#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
+#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
+#define CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
+//CRTC3_CRTC_STATIC_SCREEN_CONTROL
+#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
+#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
+#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
+#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
+#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
+#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
+#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
+#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
+#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
+#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
+#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
+#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
+#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
+#define CRTC3_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
+//CRTC3_CRTC_3D_STRUCTURE_CONTROL
+#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
+#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
+#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
+#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
+#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+#define CRTC3_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+//CRTC3_CRTC_GSL_VSYNC_GAP
+#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
+#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+#define CRTC3_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
+//CRTC3_CRTC_GSL_WINDOW
+#define CRTC3_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
+#define CRTC3_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
+#define CRTC3_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
+#define CRTC3_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
+//CRTC3_CRTC_GSL_CONTROL
+#define CRTC3_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
+#define CRTC3_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
+#define CRTC3_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+#define CRTC3_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
+#define CRTC3_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
+#define CRTC3_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+//CRTC3_CRTC_RANGE_TIMING_INT_STATUS
+#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
+#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
+#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
+#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
+#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
+#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
+#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
+#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
+#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
+#define CRTC3_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
+//CRTC3_CRTC_DRR_CONTROL
+#define CRTC3_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY__SHIFT 0x0
+#define CRTC3_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0xe
+#define CRTC3_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS__SHIFT 0x1c
+#define CRTC3_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE__SHIFT 0x1d
+#define CRTC3_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY_MASK 0x00003FFFL
+#define CRTC3_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR_MASK 0x0FFFC000L
+#define CRTC3_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS_MASK 0x10000000L
+#define CRTC3_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE_MASK 0x60000000L
+
+
+// addressBlock: dce_dc_fmt3_dispdec
+//FMT3_FMT_CLAMP_COMPONENT_R
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
+//FMT3_FMT_CLAMP_COMPONENT_G
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
+//FMT3_FMT_CLAMP_COMPONENT_B
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
+//FMT3_FMT_DYNAMIC_EXP_CNTL
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
+//FMT3_FMT_CONTROL
+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
+#define FMT3_FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
+#define FMT3_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED__SHIFT 0x1e
+#define FMT3_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR__SHIFT 0x1f
+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
+#define FMT3_FMT_CONTROL__FMT_SRC_SELECT_MASK 0x07000000L
+#define FMT3_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_MASK 0x40000000L
+#define FMT3_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR_MASK 0x80000000L
+//FMT3_FMT_BIT_DEPTH_CONTROL
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
+//FMT3_FMT_DITHER_RAND_R_SEED
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
+//FMT3_FMT_DITHER_RAND_G_SEED
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
+//FMT3_FMT_DITHER_RAND_B_SEED
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
+//FMT3_FMT_CLAMP_CNTL
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
+//FMT3_FMT_CRC_CNTL
+#define FMT3_FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
+#define FMT3_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
+#define FMT3_FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
+#define FMT3_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5
+#define FMT3_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6
+#define FMT3_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
+#define FMT3_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9
+#define FMT3_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
+#define FMT3_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+#define FMT3_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
+#define FMT3_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
+#define FMT3_FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L
+#define FMT3_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x00000002L
+#define FMT3_FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L
+#define FMT3_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x00000020L
+#define FMT3_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x00000040L
+#define FMT3_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x00000100L
+#define FMT3_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x00000200L
+#define FMT3_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define FMT3_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+#define FMT3_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L
+#define FMT3_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L
+//FMT3_FMT_CRC_SIG_RED_GREEN_MASK
+#define FMT3_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
+#define FMT3_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
+#define FMT3_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
+#define FMT3_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
+//FMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK
+#define FMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
+#define FMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
+#define FMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
+#define FMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
+//FMT3_FMT_CRC_SIG_RED_GREEN
+#define FMT3_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
+#define FMT3_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
+#define FMT3_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000FFFFL
+#define FMT3_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xFFFF0000L
+//FMT3_FMT_CRC_SIG_BLUE_CONTROL
+#define FMT3_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
+#define FMT3_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
+#define FMT3_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000FFFFL
+#define FMT3_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xFFFF0000L
+//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
+//FMT3_FMT_420_HBLANK_EARLY_START
+#define FMT3_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START__SHIFT 0x0
+#define FMT3_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START_MASK 0x00000FFFL
+
+
+// addressBlock: dce_dc_dcp4_dispdec
+//DCP4_GRPH_ENABLE
+#define DCP4_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
+#define DCP4_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1
+#define DCP4_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
+#define DCP4_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x00000002L
+//DCP4_GRPH_CONTROL
+#define DCP4_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
+#define DCP4_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT 0x2
+#define DCP4_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
+#define DCP4_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT 0x6
+#define DCP4_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
+#define DCP4_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0xc
+#define DCP4_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+#define DCP4_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+#define DCP4_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT 0x12
+#define DCP4_GRPH_CONTROL__GRPH_SW_MODE__SHIFT 0x14
+#define DCP4_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT 0x1c
+#define DCP4_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
+#define DCP4_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
+#define DCP4_GRPH_CONTROL__GRPH_SE_ENABLE_MASK 0x00000004L
+#define DCP4_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
+#define DCP4_GRPH_CONTROL__GRPH_DIM_TYPE_MASK 0x000000C0L
+#define DCP4_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
+#define DCP4_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x00007000L
+#define DCP4_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
+#define DCP4_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
+#define DCP4_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK 0x000C0000L
+#define DCP4_GRPH_CONTROL__GRPH_SW_MODE_MASK 0x01F00000L
+#define DCP4_GRPH_CONTROL__GRPH_NUM_PIPES_MASK 0x70000000L
+#define DCP4_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
+//DCP4_GRPH_LUT_10BIT_BYPASS
+#define DCP4_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
+#define DCP4_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
+#define DCP4_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L
+#define DCP4_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L
+//DCP4_GRPH_SWAP_CNTL
+#define DCP4_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
+#define DCP4_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
+#define DCP4_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
+#define DCP4_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
+#define DCP4_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
+#define DCP4_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
+#define DCP4_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
+#define DCP4_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
+#define DCP4_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
+#define DCP4_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000C00L
+//DCP4_GRPH_PRIMARY_SURFACE_ADDRESS
+#define DCP4_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
+#define DCP4_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP4_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L
+#define DCP4_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP4_GRPH_SECONDARY_SURFACE_ADDRESS
+#define DCP4_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
+#define DCP4_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP4_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L
+#define DCP4_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP4_GRPH_PITCH
+#define DCP4_GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
+#define DCP4_GRPH_PITCH__GRPH_PITCH_MASK 0x00007FFFL
+//DCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+#define DCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+#define DCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP4_GRPH_SURFACE_OFFSET_X
+#define DCP4_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
+#define DCP4_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003FFFL
+//DCP4_GRPH_SURFACE_OFFSET_Y
+#define DCP4_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
+#define DCP4_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003FFFL
+//DCP4_GRPH_X_START
+#define DCP4_GRPH_X_START__GRPH_X_START__SHIFT 0x0
+#define DCP4_GRPH_X_START__GRPH_X_START_MASK 0x00003FFFL
+//DCP4_GRPH_Y_START
+#define DCP4_GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
+#define DCP4_GRPH_Y_START__GRPH_Y_START_MASK 0x00003FFFL
+//DCP4_GRPH_X_END
+#define DCP4_GRPH_X_END__GRPH_X_END__SHIFT 0x0
+#define DCP4_GRPH_X_END__GRPH_X_END_MASK 0x00007FFFL
+//DCP4_GRPH_Y_END
+#define DCP4_GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
+#define DCP4_GRPH_Y_END__GRPH_Y_END_MASK 0x00007FFFL
+//DCP4_INPUT_GAMMA_CONTROL
+#define DCP4_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
+#define DCP4_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000001L
+//DCP4_GRPH_UPDATE
+#define DCP4_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
+#define DCP4_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
+#define DCP4_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
+#define DCP4_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
+#define DCP4_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT 0x8
+#define DCP4_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT 0x9
+#define DCP4_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT 0xa
+#define DCP4_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
+#define DCP4_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
+#define DCP4_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define DCP4_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
+#define DCP4_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
+#define DCP4_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
+#define DCP4_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
+#define DCP4_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
+#define DCP4_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK 0x00000100L
+#define DCP4_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK 0x00000200L
+#define DCP4_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK 0x00000400L
+#define DCP4_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
+#define DCP4_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
+#define DCP4_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+#define DCP4_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
+//DCP4_GRPH_FLIP_CONTROL
+#define DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
+#define DCP4_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
+#define DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4
+#define DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5
+#define DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L
+#define DCP4_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x00000002L
+#define DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x00000010L
+#define DCP4_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000020L
+//DCP4_GRPH_SURFACE_ADDRESS_INUSE
+#define DCP4_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
+#define DCP4_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xFFFFFF00L
+//DCP4_GRPH_DFQ_CONTROL
+#define DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
+#define DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
+#define DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
+#define DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L
+#define DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L
+#define DCP4_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L
+//DCP4_GRPH_DFQ_STATUS
+#define DCP4_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
+#define DCP4_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
+#define DCP4_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
+#define DCP4_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
+#define DCP4_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000FL
+#define DCP4_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000F0L
+#define DCP4_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L
+#define DCP4_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L
+//DCP4_GRPH_INTERRUPT_STATUS
+#define DCP4_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
+#define DCP4_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
+#define DCP4_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
+#define DCP4_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
+//DCP4_GRPH_INTERRUPT_CONTROL
+#define DCP4_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
+#define DCP4_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
+#define DCP4_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
+#define DCP4_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
+//DCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE
+#define DCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
+#define DCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000FFL
+//DCP4_GRPH_COMPRESS_SURFACE_ADDRESS
+#define DCP4_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP4_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP4_GRPH_COMPRESS_PITCH
+#define DCP4_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
+#define DCP4_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001FFC0L
+//DCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH
+#define DCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
+#define DCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0
+#define DCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0x000000FFL
+//DCP4_PRESCALE_GRPH_CONTROL
+#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
+#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
+#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
+#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
+#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
+#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L
+#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L
+#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L
+#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L
+#define DCP4_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L
+//DCP4_PRESCALE_VALUES_GRPH_R
+#define DCP4_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
+#define DCP4_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
+#define DCP4_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000FFFFL
+#define DCP4_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xFFFF0000L
+//DCP4_PRESCALE_VALUES_GRPH_G
+#define DCP4_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
+#define DCP4_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
+#define DCP4_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000FFFFL
+#define DCP4_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xFFFF0000L
+//DCP4_PRESCALE_VALUES_GRPH_B
+#define DCP4_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
+#define DCP4_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
+#define DCP4_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000FFFFL
+#define DCP4_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xFFFF0000L
+//DCP4_INPUT_CSC_CONTROL
+#define DCP4_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
+#define DCP4_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L
+//DCP4_INPUT_CSC_C11_C12
+#define DCP4_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
+#define DCP4_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
+#define DCP4_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000FFFFL
+#define DCP4_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xFFFF0000L
+//DCP4_INPUT_CSC_C13_C14
+#define DCP4_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
+#define DCP4_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
+#define DCP4_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000FFFFL
+#define DCP4_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xFFFF0000L
+//DCP4_INPUT_CSC_C21_C22
+#define DCP4_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
+#define DCP4_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
+#define DCP4_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000FFFFL
+#define DCP4_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xFFFF0000L
+//DCP4_INPUT_CSC_C23_C24
+#define DCP4_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
+#define DCP4_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
+#define DCP4_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000FFFFL
+#define DCP4_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xFFFF0000L
+//DCP4_INPUT_CSC_C31_C32
+#define DCP4_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
+#define DCP4_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
+#define DCP4_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000FFFFL
+#define DCP4_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xFFFF0000L
+//DCP4_INPUT_CSC_C33_C34
+#define DCP4_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
+#define DCP4_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
+#define DCP4_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000FFFFL
+#define DCP4_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xFFFF0000L
+//DCP4_OUTPUT_CSC_CONTROL
+#define DCP4_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
+#define DCP4_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L
+//DCP4_OUTPUT_CSC_C11_C12
+#define DCP4_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
+#define DCP4_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
+#define DCP4_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000FFFFL
+#define DCP4_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xFFFF0000L
+//DCP4_OUTPUT_CSC_C13_C14
+#define DCP4_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
+#define DCP4_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
+#define DCP4_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000FFFFL
+#define DCP4_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xFFFF0000L
+//DCP4_OUTPUT_CSC_C21_C22
+#define DCP4_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
+#define DCP4_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
+#define DCP4_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000FFFFL
+#define DCP4_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xFFFF0000L
+//DCP4_OUTPUT_CSC_C23_C24
+#define DCP4_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
+#define DCP4_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
+#define DCP4_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000FFFFL
+#define DCP4_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xFFFF0000L
+//DCP4_OUTPUT_CSC_C31_C32
+#define DCP4_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
+#define DCP4_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
+#define DCP4_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000FFFFL
+#define DCP4_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xFFFF0000L
+//DCP4_OUTPUT_CSC_C33_C34
+#define DCP4_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
+#define DCP4_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
+#define DCP4_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000FFFFL
+#define DCP4_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xFFFF0000L
+//DCP4_COMM_MATRIXA_TRANS_C11_C12
+#define DCP4_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
+#define DCP4_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
+#define DCP4_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000FFFFL
+#define DCP4_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xFFFF0000L
+//DCP4_COMM_MATRIXA_TRANS_C13_C14
+#define DCP4_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
+#define DCP4_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
+#define DCP4_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000FFFFL
+#define DCP4_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xFFFF0000L
+//DCP4_COMM_MATRIXA_TRANS_C21_C22
+#define DCP4_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
+#define DCP4_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
+#define DCP4_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000FFFFL
+#define DCP4_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xFFFF0000L
+//DCP4_COMM_MATRIXA_TRANS_C23_C24
+#define DCP4_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
+#define DCP4_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
+#define DCP4_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000FFFFL
+#define DCP4_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xFFFF0000L
+//DCP4_COMM_MATRIXA_TRANS_C31_C32
+#define DCP4_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
+#define DCP4_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
+#define DCP4_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000FFFFL
+#define DCP4_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xFFFF0000L
+//DCP4_COMM_MATRIXA_TRANS_C33_C34
+#define DCP4_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
+#define DCP4_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
+#define DCP4_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000FFFFL
+#define DCP4_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xFFFF0000L
+//DCP4_COMM_MATRIXB_TRANS_C11_C12
+#define DCP4_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
+#define DCP4_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
+#define DCP4_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000FFFFL
+#define DCP4_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xFFFF0000L
+//DCP4_COMM_MATRIXB_TRANS_C13_C14
+#define DCP4_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
+#define DCP4_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
+#define DCP4_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000FFFFL
+#define DCP4_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xFFFF0000L
+//DCP4_COMM_MATRIXB_TRANS_C21_C22
+#define DCP4_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
+#define DCP4_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
+#define DCP4_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000FFFFL
+#define DCP4_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xFFFF0000L
+//DCP4_COMM_MATRIXB_TRANS_C23_C24
+#define DCP4_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
+#define DCP4_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
+#define DCP4_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000FFFFL
+#define DCP4_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xFFFF0000L
+//DCP4_COMM_MATRIXB_TRANS_C31_C32
+#define DCP4_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
+#define DCP4_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
+#define DCP4_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000FFFFL
+#define DCP4_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xFFFF0000L
+//DCP4_COMM_MATRIXB_TRANS_C33_C34
+#define DCP4_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
+#define DCP4_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
+#define DCP4_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000FFFFL
+#define DCP4_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xFFFF0000L
+//DCP4_DENORM_CONTROL
+#define DCP4_DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
+#define DCP4_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
+#define DCP4_DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L
+#define DCP4_DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x00000010L
+//DCP4_OUT_ROUND_CONTROL
+#define DCP4_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
+#define DCP4_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000FL
+//DCP4_OUT_CLAMP_CONTROL_R_CR
+#define DCP4_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
+#define DCP4_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
+#define DCP4_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x00003FFFL
+#define DCP4_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3FFF0000L
+//DCP4_OUT_CLAMP_CONTROL_G_Y
+#define DCP4_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
+#define DCP4_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
+#define DCP4_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x00003FFFL
+#define DCP4_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3FFF0000L
+//DCP4_OUT_CLAMP_CONTROL_B_CB
+#define DCP4_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
+#define DCP4_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
+#define DCP4_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x00003FFFL
+#define DCP4_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3FFF0000L
+//DCP4_KEY_CONTROL
+#define DCP4_KEY_CONTROL__KEY_MODE__SHIFT 0x1
+#define DCP4_KEY_CONTROL__KEY_MODE_MASK 0x00000006L
+//DCP4_KEY_RANGE_ALPHA
+#define DCP4_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
+#define DCP4_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
+#define DCP4_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000FFFFL
+#define DCP4_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xFFFF0000L
+//DCP4_KEY_RANGE_RED
+#define DCP4_KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
+#define DCP4_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
+#define DCP4_KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000FFFFL
+#define DCP4_KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xFFFF0000L
+//DCP4_KEY_RANGE_GREEN
+#define DCP4_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
+#define DCP4_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
+#define DCP4_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000FFFFL
+#define DCP4_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xFFFF0000L
+//DCP4_KEY_RANGE_BLUE
+#define DCP4_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
+#define DCP4_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
+#define DCP4_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000FFFFL
+#define DCP4_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xFFFF0000L
+//DCP4_DEGAMMA_CONTROL
+#define DCP4_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
+#define DCP4_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
+#define DCP4_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
+#define DCP4_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L
+#define DCP4_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x00000300L
+#define DCP4_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L
+//DCP4_GAMUT_REMAP_CONTROL
+#define DCP4_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
+#define DCP4_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L
+//DCP4_GAMUT_REMAP_C11_C12
+#define DCP4_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
+#define DCP4_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
+#define DCP4_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000FFFFL
+#define DCP4_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xFFFF0000L
+//DCP4_GAMUT_REMAP_C13_C14
+#define DCP4_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
+#define DCP4_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
+#define DCP4_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000FFFFL
+#define DCP4_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xFFFF0000L
+//DCP4_GAMUT_REMAP_C21_C22
+#define DCP4_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
+#define DCP4_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
+#define DCP4_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000FFFFL
+#define DCP4_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xFFFF0000L
+//DCP4_GAMUT_REMAP_C23_C24
+#define DCP4_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
+#define DCP4_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
+#define DCP4_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000FFFFL
+#define DCP4_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xFFFF0000L
+//DCP4_GAMUT_REMAP_C31_C32
+#define DCP4_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
+#define DCP4_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
+#define DCP4_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000FFFFL
+#define DCP4_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xFFFF0000L
+//DCP4_GAMUT_REMAP_C33_C34
+#define DCP4_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
+#define DCP4_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
+#define DCP4_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000FFFFL
+#define DCP4_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xFFFF0000L
+//DCP4_DCP_SPATIAL_DITHER_CNTL
+#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
+#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
+#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
+#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
+#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
+#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
+#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L
+#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L
+#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x000000C0L
+#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L
+#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L
+#define DCP4_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L
+//DCP4_DCP_RANDOM_SEEDS
+#define DCP4_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
+#define DCP4_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
+#define DCP4_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
+#define DCP4_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000FFL
+#define DCP4_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000FF00L
+#define DCP4_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00FF0000L
+//DCP4_DCP_FP_CONVERTED_FIELD
+#define DCP4_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
+#define DCP4_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
+#define DCP4_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
+#define DCP4_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
+//DCP4_CUR_CONTROL
+#define DCP4_CUR_CONTROL__CURSOR_EN__SHIFT 0x0
+#define DCP4_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
+#define DCP4_CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
+#define DCP4_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT 0xb
+#define DCP4_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT 0xc
+#define DCP4_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
+#define DCP4_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
+#define DCP4_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
+#define DCP4_CUR_CONTROL__CURSOR_EN_MASK 0x00000001L
+#define DCP4_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L
+#define DCP4_CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L
+#define DCP4_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK 0x00000800L
+#define DCP4_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK 0x0000F000L
+#define DCP4_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L
+#define DCP4_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L
+#define DCP4_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L
+//DCP4_CUR_SURFACE_ADDRESS
+#define DCP4_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
+#define DCP4_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//DCP4_CUR_SIZE
+#define DCP4_CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
+#define DCP4_CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
+#define DCP4_CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000007FL
+#define DCP4_CUR_SIZE__CURSOR_WIDTH_MASK 0x007F0000L
+//DCP4_CUR_SURFACE_ADDRESS_HIGH
+#define DCP4_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP4_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP4_CUR_POSITION
+#define DCP4_CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
+#define DCP4_CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
+#define DCP4_CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
+#define DCP4_CUR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
+//DCP4_CUR_HOT_SPOT
+#define DCP4_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
+#define DCP4_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
+#define DCP4_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000007FL
+#define DCP4_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x007F0000L
+//DCP4_CUR_COLOR1
+#define DCP4_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
+#define DCP4_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
+#define DCP4_CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
+#define DCP4_CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000FFL
+#define DCP4_CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000FF00L
+#define DCP4_CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00FF0000L
+//DCP4_CUR_COLOR2
+#define DCP4_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
+#define DCP4_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
+#define DCP4_CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
+#define DCP4_CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000FFL
+#define DCP4_CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000FF00L
+#define DCP4_CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00FF0000L
+//DCP4_CUR_UPDATE
+#define DCP4_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
+#define DCP4_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
+#define DCP4_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
+#define DCP4_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define DCP4_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
+#define DCP4_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L
+#define DCP4_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L
+#define DCP4_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L
+#define DCP4_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+#define DCP4_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x06000000L
+//DCP4_CUR_REQUEST_FILTER_CNTL
+#define DCP4_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
+#define DCP4_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L
+//DCP4_CUR_STEREO_CONTROL
+#define DCP4_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
+#define DCP4_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
+#define DCP4_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
+#define DCP4_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
+#define DCP4_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x00003FF0L
+#define DCP4_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x03FF0000L
+//DCP4_DC_LUT_RW_MODE
+#define DCP4_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
+#define DCP4_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
+#define DCP4_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
+#define DCP4_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L
+#define DCP4_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x00010000L
+#define DCP4_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x00020000L
+//DCP4_DC_LUT_RW_INDEX
+#define DCP4_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
+#define DCP4_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000FFL
+//DCP4_DC_LUT_SEQ_COLOR
+#define DCP4_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
+#define DCP4_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000FFFFL
+//DCP4_DC_LUT_PWL_DATA
+#define DCP4_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
+#define DCP4_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
+#define DCP4_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000FFFFL
+#define DCP4_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xFFFF0000L
+//DCP4_DC_LUT_30_COLOR
+#define DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
+#define DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
+#define DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
+#define DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003FFL
+#define DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
+#define DCP4_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3FF00000L
+//DCP4_DC_LUT_VGA_ACCESS_ENABLE
+#define DCP4_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
+#define DCP4_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L
+//DCP4_DC_LUT_WRITE_EN_MASK
+#define DCP4_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define DCP4_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L
+//DCP4_DC_LUT_AUTOFILL
+#define DCP4_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
+#define DCP4_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
+#define DCP4_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L
+#define DCP4_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L
+//DCP4_DC_LUT_CONTROL
+#define DCP4_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
+#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
+#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
+#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
+#define DCP4_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
+#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
+#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
+#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
+#define DCP4_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
+#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
+#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
+#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
+#define DCP4_DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000FL
+#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L
+#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L
+#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000C0L
+#define DCP4_DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000F00L
+#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L
+#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L
+#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000C000L
+#define DCP4_DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000F0000L
+#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L
+#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L
+#define DCP4_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00C00000L
+//DCP4_DC_LUT_BLACK_OFFSET_BLUE
+#define DCP4_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
+#define DCP4_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL
+//DCP4_DC_LUT_BLACK_OFFSET_GREEN
+#define DCP4_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
+#define DCP4_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL
+//DCP4_DC_LUT_BLACK_OFFSET_RED
+#define DCP4_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
+#define DCP4_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL
+//DCP4_DC_LUT_WHITE_OFFSET_BLUE
+#define DCP4_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
+#define DCP4_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000FFFFL
+//DCP4_DC_LUT_WHITE_OFFSET_GREEN
+#define DCP4_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
+#define DCP4_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000FFFFL
+//DCP4_DC_LUT_WHITE_OFFSET_RED
+#define DCP4_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
+#define DCP4_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000FFFFL
+//DCP4_DCP_CRC_CONTROL
+#define DCP4_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
+#define DCP4_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
+#define DCP4_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
+#define DCP4_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L
+#define DCP4_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001CL
+#define DCP4_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L
+//DCP4_DCP_CRC_MASK
+#define DCP4_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
+#define DCP4_DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xFFFFFFFFL
+//DCP4_DCP_CRC_CURRENT
+#define DCP4_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
+#define DCP4_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xFFFFFFFFL
+//DCP4_DVMM_PTE_CONTROL
+#define DCP4_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
+#define DCP4_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
+#define DCP4_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
+#define DCP4_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
+#define DCP4_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
+#define DCP4_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
+#define DCP4_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
+#define DCP4_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
+#define DCP4_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
+#define DCP4_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
+#define DCP4_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
+#define DCP4_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
+//DCP4_DCP_CRC_LAST
+#define DCP4_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
+#define DCP4_DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xFFFFFFFFL
+//DCP4_DVMM_PTE_ARB_CONTROL
+#define DCP4_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
+#define DCP4_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
+#define DCP4_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
+#define DCP4_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
+//DCP4_GRPH_FLIP_RATE_CNTL
+#define DCP4_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
+#define DCP4_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
+#define DCP4_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x00000007L
+#define DCP4_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x00000008L
+//DCP4_DCP_GSL_CONTROL
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x4
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x14
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x15
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x17
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT 0x1a
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x000FFFF0L
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00100000L
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x00600000L
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x00800000L
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK 0x04000000L
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L
+#define DCP4_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xF0000000L
+//DCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK
+#define DCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
+#define DCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
+#define DCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000FL
+#define DCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000001F0L
+//DCP4_GRPH_STEREOSYNC_FLIP
+#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
+#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
+#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
+#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L
+#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
+#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
+#define DCP4_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
+//DCP4_HW_ROTATION
+#define DCP4_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
+#define DCP4_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x00000007L
+//DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL
+#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
+#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
+#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
+#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x00000001L
+#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x00000002L
+#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x0001FFF0L
+//DCP4_REGAMMA_CONTROL
+#define DCP4_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
+#define DCP4_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L
+//DCP4_REGAMMA_LUT_INDEX
+#define DCP4_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
+#define DCP4_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001FFL
+//DCP4_REGAMMA_LUT_DATA
+#define DCP4_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
+#define DCP4_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007FFFFL
+//DCP4_REGAMMA_LUT_WRITE_EN_MASK
+#define DCP4_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define DCP4_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
+//DCP4_REGAMMA_CNTLA_START_CNTL
+#define DCP4_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define DCP4_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
+#define DCP4_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+//DCP4_REGAMMA_CNTLA_SLOPE_CNTL
+#define DCP4_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+//DCP4_REGAMMA_CNTLA_END_CNTL1
+#define DCP4_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
+//DCP4_REGAMMA_CNTLA_END_CNTL2
+#define DCP4_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
+#define DCP4_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+#define DCP4_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+//DCP4_REGAMMA_CNTLA_REGION_0_1
+#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP4_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//DCP4_REGAMMA_CNTLA_REGION_2_3
+#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP4_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//DCP4_REGAMMA_CNTLA_REGION_4_5
+#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP4_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//DCP4_REGAMMA_CNTLA_REGION_6_7
+#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP4_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//DCP4_REGAMMA_CNTLA_REGION_8_9
+#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP4_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//DCP4_REGAMMA_CNTLA_REGION_10_11
+#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP4_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//DCP4_REGAMMA_CNTLA_REGION_12_13
+#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP4_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//DCP4_REGAMMA_CNTLA_REGION_14_15
+#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP4_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//DCP4_REGAMMA_CNTLB_START_CNTL
+#define DCP4_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define DCP4_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
+#define DCP4_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+//DCP4_REGAMMA_CNTLB_SLOPE_CNTL
+#define DCP4_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+//DCP4_REGAMMA_CNTLB_END_CNTL1
+#define DCP4_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
+//DCP4_REGAMMA_CNTLB_END_CNTL2
+#define DCP4_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
+#define DCP4_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+#define DCP4_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+//DCP4_REGAMMA_CNTLB_REGION_0_1
+#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP4_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//DCP4_REGAMMA_CNTLB_REGION_2_3
+#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP4_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//DCP4_REGAMMA_CNTLB_REGION_4_5
+#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP4_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//DCP4_REGAMMA_CNTLB_REGION_6_7
+#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP4_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//DCP4_REGAMMA_CNTLB_REGION_8_9
+#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP4_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//DCP4_REGAMMA_CNTLB_REGION_10_11
+#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP4_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//DCP4_REGAMMA_CNTLB_REGION_12_13
+#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP4_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//DCP4_REGAMMA_CNTLB_REGION_14_15
+#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP4_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//DCP4_ALPHA_CONTROL
+#define DCP4_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
+#define DCP4_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
+#define DCP4_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x00000001L
+#define DCP4_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x00000002L
+//DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS
+#define DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH
+#define DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS
+#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
+#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
+#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
+#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
+#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
+#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
+#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
+#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0x000FFFFFL
+#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x01000000L
+#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x02000000L
+#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x04000000L
+#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000L
+#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000L
+#define DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000L
+//DCP4_GRPH_XDMA_FLIP_TIMEOUT
+#define DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT 0x0
+#define DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT 0x1
+#define DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT 0x2
+#define DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK 0x00000001L
+#define DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK 0x00000002L
+#define DCP4_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK 0x00000004L
+//DCP4_GRPH_XDMA_FLIP_AVG_DELAY
+#define DCP4_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT 0x0
+#define DCP4_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT 0x10
+#define DCP4_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK 0x0000FFFFL
+#define DCP4_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK 0x00FF0000L
+//DCP4_GRPH_SURFACE_COUNTER_CONTROL
+#define DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0
+#define DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1
+#define DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9
+#define DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x00000001L
+#define DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x0000001EL
+#define DCP4_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x00000200L
+//DCP4_GRPH_SURFACE_COUNTER_OUTPUT
+#define DCP4_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0
+#define DCP4_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10
+#define DCP4_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0x0000FFFFL
+#define DCP4_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_lb4_dispdec
+//LB4_LB_DATA_FORMAT
+#define LB4_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
+#define LB4_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
+#define LB4_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
+#define LB4_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
+#define LB4_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
+#define LB4_LB_DATA_FORMAT__PREFILL_EN__SHIFT 0x8
+#define LB4_LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
+#define LB4_LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
+#define LB4_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
+#define LB4_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
+#define LB4_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
+#define LB4_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
+#define LB4_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
+#define LB4_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
+#define LB4_LB_DATA_FORMAT__PREFILL_EN_MASK 0x00000100L
+#define LB4_LB_DATA_FORMAT__PREFETCH_MASK 0x00001000L
+#define LB4_LB_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
+#define LB4_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
+//LB4_LB_MEMORY_CTRL
+#define LB4_LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
+#define LB4_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+#define LB4_LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
+#define LB4_LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00001FFFL
+#define LB4_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
+#define LB4_LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
+//LB4_LB_MEMORY_SIZE_STATUS
+#define LB4_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
+#define LB4_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00001FFFL
+//LB4_LB_DESKTOP_HEIGHT
+#define LB4_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
+#define LB4_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
+//LB4_LB_VLINE_START_END
+#define LB4_LB_VLINE_START_END__VLINE_START__SHIFT 0x0
+#define LB4_LB_VLINE_START_END__VLINE_END__SHIFT 0x10
+#define LB4_LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
+#define LB4_LB_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
+#define LB4_LB_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
+#define LB4_LB_VLINE_START_END__VLINE_INV_MASK 0x80000000L
+//LB4_LB_VLINE2_START_END
+#define LB4_LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
+#define LB4_LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
+#define LB4_LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
+#define LB4_LB_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
+#define LB4_LB_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
+#define LB4_LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
+//LB4_LB_V_COUNTER
+#define LB4_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
+#define LB4_LB_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
+//LB4_LB_SNAPSHOT_V_COUNTER
+#define LB4_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
+#define LB4_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
+//LB4_LB_INTERRUPT_MASK
+#define LB4_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
+#define LB4_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
+#define LB4_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
+#define LB4_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
+#define LB4_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
+#define LB4_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
+//LB4_LB_VLINE_STATUS
+#define LB4_LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
+#define LB4_LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
+#define LB4_LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
+#define LB4_LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
+#define LB4_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
+#define LB4_LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
+#define LB4_LB_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
+#define LB4_LB_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
+#define LB4_LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
+#define LB4_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
+//LB4_LB_VLINE2_STATUS
+#define LB4_LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
+#define LB4_LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
+#define LB4_LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
+#define LB4_LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
+#define LB4_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
+#define LB4_LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
+#define LB4_LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
+#define LB4_LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
+#define LB4_LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
+#define LB4_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
+//LB4_LB_VBLANK_STATUS
+#define LB4_LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
+#define LB4_LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
+#define LB4_LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
+#define LB4_LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
+#define LB4_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
+#define LB4_LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
+#define LB4_LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
+#define LB4_LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
+#define LB4_LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
+#define LB4_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
+//LB4_LB_SYNC_RESET_SEL
+#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
+#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
+#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
+#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
+#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
+#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
+#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
+#define LB4_LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
+//LB4_LB_BLACK_KEYER_R_CR
+#define LB4_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
+#define LB4_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
+//LB4_LB_BLACK_KEYER_G_Y
+#define LB4_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
+#define LB4_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
+//LB4_LB_BLACK_KEYER_B_CB
+#define LB4_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
+#define LB4_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
+//LB4_LB_KEYER_COLOR_CTRL
+#define LB4_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
+#define LB4_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
+#define LB4_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
+#define LB4_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
+//LB4_LB_KEYER_COLOR_R_CR
+#define LB4_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
+#define LB4_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
+//LB4_LB_KEYER_COLOR_G_Y
+#define LB4_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
+#define LB4_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
+//LB4_LB_KEYER_COLOR_B_CB
+#define LB4_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
+#define LB4_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
+//LB4_LB_KEYER_COLOR_REP_R_CR
+#define LB4_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
+#define LB4_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
+//LB4_LB_KEYER_COLOR_REP_G_Y
+#define LB4_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
+#define LB4_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
+//LB4_LB_KEYER_COLOR_REP_B_CB
+#define LB4_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
+#define LB4_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
+//LB4_LB_BUFFER_LEVEL_STATUS
+#define LB4_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
+#define LB4_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
+#define LB4_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
+#define LB4_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
+#define LB4_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
+#define LB4_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
+#define LB4_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
+#define LB4_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
+//LB4_LB_BUFFER_URGENCY_CTRL
+#define LB4_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
+#define LB4_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
+#define LB4_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
+#define LB4_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
+//LB4_LB_BUFFER_URGENCY_STATUS
+#define LB4_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
+#define LB4_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
+#define LB4_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
+#define LB4_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
+//LB4_LB_BUFFER_STATUS
+#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
+#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
+#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
+#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
+#define LB4_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
+#define LB4_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
+#define LB4_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
+#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
+#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
+#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
+#define LB4_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
+#define LB4_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
+#define LB4_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
+#define LB4_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
+//LB4_LB_NO_OUTSTANDING_REQ_STATUS
+#define LB4_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
+#define LB4_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
+//LB4_MVP_AFR_FLIP_MODE
+#define LB4_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
+#define LB4_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L
+//LB4_MVP_AFR_FLIP_FIFO_CNTL
+#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
+#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
+#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
+#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
+#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000FL
+#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L
+#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L
+#define LB4_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L
+//LB4_MVP_FLIP_LINE_NUM_INSERT
+#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
+#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
+#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
+#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
+#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L
+#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007FFF00L
+#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3F000000L
+#define LB4_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L
+//LB4_DC_MVP_LB_CONTROL
+#define LB4_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
+#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
+#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
+#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
+#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
+#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
+#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
+#define LB4_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L
+#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L
+#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L
+#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L
+#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L
+#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L
+#define LB4_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L
+
+
+// addressBlock: dce_dc_dcfe4_dispdec
+//DCFE4_DCFE_CLOCK_CONTROL
+#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
+#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
+#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
+#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf
+#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT 0x11
+#define DCFE4_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
+#define DCFE4_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
+#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L
+#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L
+#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L
+#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x00008000L
+#define DCFE4_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK 0x00020000L
+#define DCFE4_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1F000000L
+#define DCFE4_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000L
+//DCFE4_DCFE_SOFT_RESET
+#define DCFE4_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
+#define DCFE4_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
+#define DCFE4_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
+#define DCFE4_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
+#define DCFE4_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
+#define DCFE4_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5
+#define DCFE4_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
+#define DCFE4_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x00000002L
+#define DCFE4_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x00000004L
+#define DCFE4_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x00000008L
+#define DCFE4_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
+#define DCFE4_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x00000020L
+//DCFE4_DCFE_MEM_PWR_CTRL
+#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
+#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
+#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
+#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
+#define DCFE4_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
+#define DCFE4_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
+#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
+#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
+#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x00000003L
+#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x00000004L
+#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x00000018L
+#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x00000020L
+#define DCFE4_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
+#define DCFE4_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x00000100L
+#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x00000600L
+#define DCFE4_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x00000800L
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x00003000L
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x00004000L
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x00018000L
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x00020000L
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0x000C0000L
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x00100000L
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x00600000L
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x00800000L
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x03000000L
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x04000000L
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000L
+#define DCFE4_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000L
+//DCFE4_DCFE_MEM_PWR_CTRL2
+#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
+#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
+#define DCFE4_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
+#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
+#define DCFE4_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
+#define DCFE4_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
+#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
+#define DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
+#define DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
+#define DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
+#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
+#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
+#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x00000003L
+#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
+#define DCFE4_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
+#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0x000000C0L
+#define DCFE4_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x00000300L
+#define DCFE4_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0x00000C00L
+#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x00003000L
+#define DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0x0000C000L
+#define DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x00030000L
+#define DCFE4_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x00040000L
+#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x00600000L
+#define DCFE4_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x00800000L
+//DCFE4_DCFE_MEM_PWR_STATUS
+#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
+#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
+#define DCFE4_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
+#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
+#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
+#define DCFE4_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
+#define DCFE4_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
+#define DCFE4_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
+#define DCFE4_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
+#define DCFE4_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
+#define DCFE4_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
+#define DCFE4_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
+#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x00000003L
+#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0x0000000CL
+#define DCFE4_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x00000030L
+#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0x000000C0L
+#define DCFE4_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x00000300L
+#define DCFE4_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0x00000C00L
+#define DCFE4_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x00003000L
+#define DCFE4_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0x0000C000L
+#define DCFE4_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x00030000L
+#define DCFE4_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0x000C0000L
+#define DCFE4_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x00300000L
+#define DCFE4_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0x00C00000L
+//DCFE4_DCFE_MISC
+#define DCFE4_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
+#define DCFE4_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
+//DCFE4_DCFE_FLUSH
+#define DCFE4_DCFE_FLUSH__FLUSH_OCCURED__SHIFT 0x0
+#define DCFE4_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
+#define DCFE4_DCFE_FLUSH__FLUSH_DEEP__SHIFT 0x2
+#define DCFE4_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
+#define DCFE4_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
+#define DCFE4_DCFE_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
+#define DCFE4_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
+#define DCFE4_DCFE_FLUSH__FLUSH_DEEP_MASK 0x00000004L
+#define DCFE4_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
+#define DCFE4_DCFE_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
+
+
+// addressBlock: dce_dc_dc_perfmon7_dispdec
+//DC_PERFMON7_PERFCOUNTER_CNTL
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON7_PERFCOUNTER_CNTL2
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON7_PERFCOUNTER_STATE
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON7_PERFMON_CNTL
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON7_PERFMON_CNTL2
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON7_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON7_PERFMON_CVALUE_LOW
+#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON7_PERFMON_HI
+#define DC_PERFMON7_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON7_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON7_PERFMON_LOW
+#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dmif_pg4_dispdec
+//DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1
+#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
+#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
+//DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2
+#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
+#define DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
+//DMIF_PG4_DPG_WATERMARK_MASK_CONTROL
+#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x4
+#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT 0xc
+#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0xf
+#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x12
+#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT 0x13
+#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT 0x14
+#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000007L
+#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000070L
+#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000700L
+#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK 0x00007000L
+#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00038000L
+#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x00040000L
+#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK 0x00080000L
+#define DMIF_PG4_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK 0x3FF00000L
+//DMIF_PG4_DPG_PIPE_URGENCY_CONTROL
+#define DMIF_PG4_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+#define DMIF_PG4_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+#define DMIF_PG4_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
+#define DMIF_PG4_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
+//DMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL
+#define DMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT 0x0
+#define DMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT 0x10
+#define DMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK 0x0000FFFFL
+#define DMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK 0xFFFF0000L
+//DMIF_PG4_DPG_PIPE_STUTTER_CONTROL
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT 0x10
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x14
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x15
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x16
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x17
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x1a
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x1b
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK 0x00010000L
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00100000L
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00200000L
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00400000L
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00800000L
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x04000000L
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x08000000L
+//DMIF_PG4_DPG_PIPE_STUTTER_CONTROL2
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x0
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT 0x10
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0x0000FFFFL
+#define DMIF_PG4_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
+//DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL
+#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT 0x0
+#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT 0x1
+#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT 0xf
+#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK 0x00000001L
+#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK 0x00000002L
+#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
+#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
+#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
+#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
+#define DMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK 0xFFFF8000L
+//DMIF_PG4_DPG_REPEATER_PROGRAM
+#define DMIF_PG4_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+#define DMIF_PG4_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+#define DMIF_PG4_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
+#define DMIF_PG4_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
+//DMIF_PG4_DPG_CHK_PRE_PROC_CNTL
+#define DMIF_PG4_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+#define DMIF_PG4_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
+//DMIF_PG4_DPG_DVMM_STATUS
+#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT 0x0
+#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT 0x1
+#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT 0x4
+#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT 0x5
+#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK 0x00000001L
+#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK 0x00000002L
+#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK 0x00000010L
+#define DMIF_PG4_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK 0x00000020L
+
+
+// addressBlock: dce_dc_scl4_dispdec
+//SCL4_SCL_COEF_RAM_SELECT
+#define SCL4_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define SCL4_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
+#define SCL4_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
+#define SCL4_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000FL
+#define SCL4_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000F00L
+#define SCL4_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00070000L
+//SCL4_SCL_COEF_RAM_TAP_DATA
+#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+#define SCL4_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+//SCL4_SCL_MODE
+#define SCL4_SCL_MODE__SCL_MODE__SHIFT 0x0
+#define SCL4_SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
+#define SCL4_SCL_MODE__SCL_MODE_MASK 0x00000003L
+#define SCL4_SCL_MODE__SCL_PSCL_EN_MASK 0x00000010L
+//SCL4_SCL_TAP_CONTROL
+#define SCL4_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
+#define SCL4_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
+#define SCL4_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
+#define SCL4_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000F00L
+//SCL4_SCL_CONTROL
+#define SCL4_SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+#define SCL4_SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
+#define SCL4_SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+#define SCL4_SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
+//SCL4_SCL_BYPASS_CONTROL
+#define SCL4_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
+#define SCL4_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L
+//SCL4_SCL_MANUAL_REPLICATE_CONTROL
+#define SCL4_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+#define SCL4_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+#define SCL4_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+#define SCL4_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+//SCL4_SCL_AUTOMATIC_MODE_CONTROL
+#define SCL4_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
+#define SCL4_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
+#define SCL4_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
+#define SCL4_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
+//SCL4_SCL_HORZ_FILTER_CONTROL
+#define SCL4_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
+#define SCL4_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCL4_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L
+#define SCL4_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+//SCL4_SCL_HORZ_FILTER_SCALE_RATIO
+#define SCL4_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+#define SCL4_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+//SCL4_SCL_HORZ_FILTER_INIT
+#define SCL4_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+#define SCL4_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+#define SCL4_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+#define SCL4_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+//SCL4_SCL_VERT_FILTER_CONTROL
+#define SCL4_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
+#define SCL4_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCL4_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L
+#define SCL4_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+//SCL4_SCL_VERT_FILTER_SCALE_RATIO
+#define SCL4_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+#define SCL4_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+//SCL4_SCL_VERT_FILTER_INIT
+#define SCL4_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+#define SCL4_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+#define SCL4_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+#define SCL4_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
+//SCL4_SCL_VERT_FILTER_INIT_BOT
+#define SCL4_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+#define SCL4_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+#define SCL4_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+#define SCL4_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
+//SCL4_SCL_ROUND_OFFSET
+#define SCL4_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
+#define SCL4_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+#define SCL4_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
+#define SCL4_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
+//SCL4_SCL_UPDATE
+#define SCL4_SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+#define SCL4_SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
+#define SCL4_SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
+#define SCL4_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
+#define SCL4_SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+#define SCL4_SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
+#define SCL4_SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
+#define SCL4_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
+//SCL4_SCL_F_SHARP_CONTROL
+#define SCL4_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
+#define SCL4_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
+#define SCL4_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
+#define SCL4_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
+#define SCL4_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L
+#define SCL4_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L
+#define SCL4_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L
+#define SCL4_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L
+//SCL4_SCL_ALU_CONTROL
+#define SCL4_SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
+#define SCL4_SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
+//SCL4_SCL_COEF_RAM_CONFLICT_STATUS
+#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
+#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
+#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
+#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
+#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
+#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L
+#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L
+#define SCL4_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
+//SCL4_VIEWPORT_START_SECONDARY
+#define SCL4_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
+#define SCL4_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
+#define SCL4_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
+#define SCL4_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
+//SCL4_VIEWPORT_START
+#define SCL4_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
+#define SCL4_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
+#define SCL4_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
+#define SCL4_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
+//SCL4_VIEWPORT_SIZE
+#define SCL4_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
+#define SCL4_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
+#define SCL4_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003FFFL
+#define SCL4_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3FFF0000L
+//SCL4_EXT_OVERSCAN_LEFT_RIGHT
+#define SCL4_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+#define SCL4_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+#define SCL4_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+#define SCL4_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+//SCL4_EXT_OVERSCAN_TOP_BOTTOM
+#define SCL4_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+#define SCL4_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+#define SCL4_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+#define SCL4_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+//SCL4_SCL_MODE_CHANGE_DET1
+#define SCL4_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
+#define SCL4_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
+#define SCL4_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
+#define SCL4_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
+#define SCL4_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
+#define SCL4_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
+//SCL4_SCL_MODE_CHANGE_DET2
+#define SCL4_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
+#define SCL4_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
+//SCL4_SCL_MODE_CHANGE_DET3
+#define SCL4_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
+#define SCL4_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
+#define SCL4_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
+#define SCL4_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
+//SCL4_SCL_MODE_CHANGE_MASK
+#define SCL4_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
+#define SCL4_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_blnd4_dispdec
+//BLND4_BLND_CONTROL
+#define BLND4_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
+#define BLND4_BLND_CONTROL__BLND_MODE__SHIFT 0x8
+#define BLND4_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
+#define BLND4_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
+#define BLND4_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
+#define BLND4_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
+#define BLND4_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
+#define BLND4_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
+#define BLND4_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
+#define BLND4_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
+#define BLND4_BLND_CONTROL__BLND_MODE_MASK 0x00000300L
+#define BLND4_BLND_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
+#define BLND4_BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
+#define BLND4_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
+#define BLND4_BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
+#define BLND4_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
+#define BLND4_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
+#define BLND4_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
+//BLND4_BLND_SM_CONTROL2
+#define BLND4_BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0
+#define BLND4_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
+#define BLND4_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
+#define BLND4_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+#define BLND4_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+#define BLND4_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
+#define BLND4_BLND_SM_CONTROL2__SM_MODE_MASK 0x00000007L
+#define BLND4_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
+#define BLND4_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
+#define BLND4_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+#define BLND4_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+#define BLND4_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
+//BLND4_BLND_CONTROL2
+#define BLND4_BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
+#define BLND4_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
+#define BLND4_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
+#define BLND4_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
+#define BLND4_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
+#define BLND4_BLND_CONTROL2__PTI_ENABLE_MASK 0x00000001L
+#define BLND4_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
+#define BLND4_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
+#define BLND4_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
+#define BLND4_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
+//BLND4_BLND_UPDATE
+#define BLND4_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
+#define BLND4_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
+#define BLND4_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
+#define BLND4_BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
+#define BLND4_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
+#define BLND4_BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
+//BLND4_BLND_UNDERFLOW_INTERRUPT
+#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
+#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
+#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
+#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
+#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
+#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
+#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
+#define BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
+//BLND4_BLND_V_UPDATE_LOCK
+#define BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
+#define BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
+#define BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
+#define BLND4_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
+#define BLND4_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
+#define BLND4_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
+#define BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
+#define BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
+#define BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
+#define BLND4_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
+#define BLND4_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
+#define BLND4_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
+//BLND4_BLND_REG_UPDATE_STATUS
+#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
+#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
+#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
+#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
+#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
+#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
+#define BLND4_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
+#define BLND4_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
+#define BLND4_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
+#define BLND4_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
+#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
+#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
+#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
+#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
+#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
+#define BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
+#define BLND4_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
+#define BLND4_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
+#define BLND4_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
+#define BLND4_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
+
+
+// addressBlock: dce_dc_crtc4_dispdec
+//CRTC4_CRTC_H_BLANK_EARLY_NUM
+#define CRTC4_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
+#define CRTC4_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
+#define CRTC4_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
+#define CRTC4_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
+//CRTC4_CRTC_H_TOTAL
+#define CRTC4_CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
+#define CRTC4_CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
+//CRTC4_CRTC_H_BLANK_START_END
+#define CRTC4_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
+#define CRTC4_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
+#define CRTC4_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
+#define CRTC4_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
+//CRTC4_CRTC_H_SYNC_A
+#define CRTC4_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
+#define CRTC4_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
+#define CRTC4_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
+#define CRTC4_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
+//CRTC4_CRTC_H_SYNC_A_CNTL
+#define CRTC4_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
+#define CRTC4_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
+#define CRTC4_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
+#define CRTC4_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
+#define CRTC4_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
+#define CRTC4_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
+//CRTC4_CRTC_H_SYNC_B
+#define CRTC4_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
+#define CRTC4_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
+#define CRTC4_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
+#define CRTC4_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
+//CRTC4_CRTC_H_SYNC_B_CNTL
+#define CRTC4_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
+#define CRTC4_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
+#define CRTC4_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
+#define CRTC4_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
+#define CRTC4_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
+#define CRTC4_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
+//CRTC4_CRTC_VBI_END
+#define CRTC4_CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
+#define CRTC4_CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
+#define CRTC4_CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
+#define CRTC4_CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
+//CRTC4_CRTC_V_TOTAL
+#define CRTC4_CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
+#define CRTC4_CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
+//CRTC4_CRTC_V_TOTAL_MIN
+#define CRTC4_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
+#define CRTC4_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
+//CRTC4_CRTC_V_TOTAL_MAX
+#define CRTC4_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
+#define CRTC4_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
+#define CRTC4_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
+#define CRTC4_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
+//CRTC4_CRTC_V_TOTAL_CONTROL
+#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
+#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
+#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
+#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
+#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
+#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
+#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
+#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
+#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
+#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
+#define CRTC4_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+//CRTC4_CRTC_V_TOTAL_INT_STATUS
+#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+#define CRTC4_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+//CRTC4_CRTC_VSYNC_NOM_INT_STATUS
+#define CRTC4_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
+#define CRTC4_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+#define CRTC4_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
+#define CRTC4_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+//CRTC4_CRTC_V_BLANK_START_END
+#define CRTC4_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
+#define CRTC4_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
+#define CRTC4_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
+#define CRTC4_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
+//CRTC4_CRTC_V_SYNC_A
+#define CRTC4_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
+#define CRTC4_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
+#define CRTC4_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
+#define CRTC4_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
+//CRTC4_CRTC_V_SYNC_A_CNTL
+#define CRTC4_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
+#define CRTC4_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
+//CRTC4_CRTC_V_SYNC_B
+#define CRTC4_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
+#define CRTC4_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
+#define CRTC4_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
+#define CRTC4_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
+//CRTC4_CRTC_V_SYNC_B_CNTL
+#define CRTC4_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
+#define CRTC4_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
+//CRTC4_CRTC_DTMTEST_CNTL
+#define CRTC4_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
+#define CRTC4_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
+#define CRTC4_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
+#define CRTC4_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
+//CRTC4_CRTC_DTMTEST_STATUS_POSITION
+#define CRTC4_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
+#define CRTC4_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
+#define CRTC4_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
+#define CRTC4_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTC4_CRTC_TRIGA_CNTL
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
+#define CRTC4_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
+//CRTC4_CRTC_TRIGA_MANUAL_TRIG
+#define CRTC4_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
+#define CRTC4_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+//CRTC4_CRTC_TRIGB_CNTL
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
+#define CRTC4_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
+//CRTC4_CRTC_TRIGB_MANUAL_TRIG
+#define CRTC4_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
+#define CRTC4_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+//CRTC4_CRTC_FORCE_COUNT_NOW_CNTL
+#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+#define CRTC4_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+//CRTC4_CRTC_FLOW_CONTROL
+#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
+#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+#define CRTC4_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+//CRTC4_CRTC_STEREO_FORCE_NEXT_EYE
+#define CRTC4_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+#define CRTC4_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+#define CRTC4_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
+#define CRTC4_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+#define CRTC4_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+#define CRTC4_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+//CRTC4_CRTC_AVSYNC_COUNTER
+#define CRTC4_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
+#define CRTC4_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
+//CRTC4_CRTC_CONTROL
+#define CRTC4_CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTC4_CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
+#define CRTC4_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
+#define CRTC4_CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
+#define CRTC4_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
+#define CRTC4_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
+#define CRTC4_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+#define CRTC4_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
+#define CRTC4_CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
+#define CRTC4_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+#define CRTC4_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+#define CRTC4_CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
+#define CRTC4_CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
+#define CRTC4_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
+#define CRTC4_CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
+#define CRTC4_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
+#define CRTC4_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+#define CRTC4_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+#define CRTC4_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
+#define CRTC4_CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
+#define CRTC4_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+#define CRTC4_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+//CRTC4_CRTC_BLANK_CONTROL
+#define CRTC4_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
+#define CRTC4_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
+#define CRTC4_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
+#define CRTC4_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
+#define CRTC4_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
+#define CRTC4_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
+//CRTC4_CRTC_INTERLACE_CONTROL
+#define CRTC4_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
+#define CRTC4_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+#define CRTC4_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
+#define CRTC4_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+//CRTC4_CRTC_INTERLACE_STATUS
+#define CRTC4_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+#define CRTC4_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
+#define CRTC4_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+#define CRTC4_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+//CRTC4_CRTC_FIELD_INDICATION_CONTROL
+#define CRTC4_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
+#define CRTC4_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
+#define CRTC4_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
+#define CRTC4_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
+//CRTC4_CRTC_PIXEL_DATA_READBACK0
+#define CRTC4_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+#define CRTC4_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+#define CRTC4_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
+#define CRTC4_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
+//CRTC4_CRTC_PIXEL_DATA_READBACK1
+#define CRTC4_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
+#define CRTC4_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
+//CRTC4_CRTC_STATUS
+#define CRTC4_CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
+#define CRTC4_CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
+#define CRTC4_CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
+#define CRTC4_CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
+#define CRTC4_CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
+#define CRTC4_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+#define CRTC4_CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
+#define CRTC4_CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
+#define CRTC4_CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
+#define CRTC4_CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L
+#define CRTC4_CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
+#define CRTC4_CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
+#define CRTC4_CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
+#define CRTC4_CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
+#define CRTC4_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+#define CRTC4_CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L
+#define CRTC4_CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
+#define CRTC4_CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
+//CRTC4_CRTC_STATUS_POSITION
+#define CRTC4_CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
+#define CRTC4_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
+#define CRTC4_CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
+#define CRTC4_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTC4_CRTC_NOM_VERT_POSITION
+#define CRTC4_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
+#define CRTC4_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
+//CRTC4_CRTC_STATUS_FRAME_COUNT
+#define CRTC4_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
+#define CRTC4_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
+//CRTC4_CRTC_STATUS_VF_COUNT
+#define CRTC4_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
+#define CRTC4_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
+//CRTC4_CRTC_STATUS_HV_COUNT
+#define CRTC4_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
+#define CRTC4_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
+//CRTC4_CRTC_COUNT_CONTROL
+#define CRTC4_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
+#define CRTC4_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
+#define CRTC4_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+#define CRTC4_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+//CRTC4_CRTC_COUNT_RESET
+#define CRTC4_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
+#define CRTC4_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
+//CRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define CRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+#define CRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+//CRTC4_CRTC_VERT_SYNC_CONTROL
+#define CRTC4_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+#define CRTC4_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+#define CRTC4_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+#define CRTC4_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+#define CRTC4_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+#define CRTC4_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+//CRTC4_CRTC_STEREO_STATUS
+#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
+#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
+#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
+#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
+#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
+#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
+#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
+#define CRTC4_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+//CRTC4_CRTC_STEREO_CONTROL
+#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
+#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+#define CRTC4_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+#define CRTC4_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
+#define CRTC4_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
+#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
+#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
+#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+#define CRTC4_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+#define CRTC4_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
+#define CRTC4_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+#define CRTC4_CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
+//CRTC4_CRTC_SNAPSHOT_STATUS
+#define CRTC4_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
+#define CRTC4_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
+#define CRTC4_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+#define CRTC4_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
+#define CRTC4_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
+#define CRTC4_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+//CRTC4_CRTC_SNAPSHOT_CONTROL
+#define CRTC4_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+#define CRTC4_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+//CRTC4_CRTC_SNAPSHOT_POSITION
+#define CRTC4_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+#define CRTC4_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+#define CRTC4_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
+#define CRTC4_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTC4_CRTC_SNAPSHOT_FRAME
+#define CRTC4_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+#define CRTC4_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+//CRTC4_CRTC_START_LINE_CONTROL
+#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
+#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
+#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
+#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
+#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
+#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
+#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
+#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
+#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
+#define CRTC4_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
+//CRTC4_CRTC_INTERRUPT_CONTROL
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+#define CRTC4_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+//CRTC4_CRTC_UPDATE_LOCK
+#define CRTC4_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
+#define CRTC4_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
+//CRTC4_CRTC_DOUBLE_BUFFER_CONTROL
+#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
+#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
+#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
+#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
+#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
+#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
+#define CRTC4_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
+//CRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE
+#define CRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
+#define CRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
+//CRTC4_CRTC_TEST_PATTERN_CONTROL
+#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
+#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
+#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
+#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
+#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
+#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
+#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
+#define CRTC4_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
+//CRTC4_CRTC_TEST_PATTERN_PARAMETERS
+#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
+#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
+#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
+#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
+#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
+#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
+#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
+#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
+#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
+#define CRTC4_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
+//CRTC4_CRTC_TEST_PATTERN_COLOR
+#define CRTC4_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
+#define CRTC4_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
+#define CRTC4_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
+#define CRTC4_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
+//CRTC4_CRTC_MASTER_UPDATE_LOCK
+#define CRTC4_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
+#define CRTC4_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
+#define CRTC4_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
+#define CRTC4_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
+#define CRTC4_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
+#define CRTC4_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
+//CRTC4_CRTC_MASTER_UPDATE_MODE
+#define CRTC4_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
+#define CRTC4_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
+#define CRTC4_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
+#define CRTC4_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
+//CRTC4_CRTC_MVP_INBAND_CNTL_INSERT
+#define CRTC4_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
+#define CRTC4_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
+#define CRTC4_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
+#define CRTC4_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
+//CRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER
+#define CRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
+#define CRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
+//CRTC4_CRTC_MVP_STATUS
+#define CRTC4_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
+#define CRTC4_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
+#define CRTC4_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
+#define CRTC4_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
+#define CRTC4_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
+#define CRTC4_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
+#define CRTC4_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
+#define CRTC4_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
+//CRTC4_CRTC_MASTER_EN
+#define CRTC4_CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTC4_CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
+//CRTC4_CRTC_ALLOW_STOP_OFF_V_CNT
+#define CRTC4_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
+#define CRTC4_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
+#define CRTC4_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
+#define CRTC4_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
+//CRTC4_CRTC_V_UPDATE_INT_STATUS
+#define CRTC4_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
+#define CRTC4_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
+#define CRTC4_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
+#define CRTC4_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
+//CRTC4_CRTC_OVERSCAN_COLOR
+#define CRTC4_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
+#define CRTC4_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
+#define CRTC4_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
+#define CRTC4_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
+#define CRTC4_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
+#define CRTC4_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
+//CRTC4_CRTC_OVERSCAN_COLOR_EXT
+#define CRTC4_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
+#define CRTC4_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
+#define CRTC4_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
+#define CRTC4_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
+#define CRTC4_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
+#define CRTC4_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
+//CRTC4_CRTC_BLANK_DATA_COLOR
+#define CRTC4_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+#define CRTC4_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+#define CRTC4_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+#define CRTC4_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+#define CRTC4_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+#define CRTC4_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+//CRTC4_CRTC_BLANK_DATA_COLOR_EXT
+#define CRTC4_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+#define CRTC4_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+#define CRTC4_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+#define CRTC4_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
+#define CRTC4_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
+#define CRTC4_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
+//CRTC4_CRTC_BLACK_COLOR
+#define CRTC4_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
+#define CRTC4_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
+#define CRTC4_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
+#define CRTC4_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
+#define CRTC4_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+#define CRTC4_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+//CRTC4_CRTC_BLACK_COLOR_EXT
+#define CRTC4_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+#define CRTC4_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+#define CRTC4_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+#define CRTC4_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
+#define CRTC4_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
+#define CRTC4_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
+//CRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION
+#define CRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+#define CRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+#define CRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
+#define CRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
+//CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL
+#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+#define CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+//CRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION
+#define CRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+#define CRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
+//CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL
+#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+#define CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+//CRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION
+#define CRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+#define CRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
+//CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL
+#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+#define CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+//CRTC4_CRTC_CRC_CNTL
+#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
+#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
+#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
+#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
+#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
+#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
+#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
+#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
+#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
+#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
+#define CRTC4_CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
+//CRTC4_CRTC_CRC0_WINDOWA_X_CONTROL
+#define CRTC4_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
+#define CRTC4_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
+#define CRTC4_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
+#define CRTC4_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
+//CRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL
+#define CRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
+#define CRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
+#define CRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
+#define CRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
+//CRTC4_CRTC_CRC0_WINDOWB_X_CONTROL
+#define CRTC4_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
+#define CRTC4_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
+#define CRTC4_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
+#define CRTC4_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
+//CRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL
+#define CRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
+#define CRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
+#define CRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
+#define CRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
+//CRTC4_CRTC_CRC0_DATA_RG
+#define CRTC4_CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+#define CRTC4_CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+#define CRTC4_CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+#define CRTC4_CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+//CRTC4_CRTC_CRC0_DATA_B
+#define CRTC4_CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+#define CRTC4_CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+//CRTC4_CRTC_CRC1_WINDOWA_X_CONTROL
+#define CRTC4_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
+#define CRTC4_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
+#define CRTC4_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
+#define CRTC4_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
+//CRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL
+#define CRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
+#define CRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
+#define CRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
+#define CRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
+//CRTC4_CRTC_CRC1_WINDOWB_X_CONTROL
+#define CRTC4_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
+#define CRTC4_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
+#define CRTC4_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
+#define CRTC4_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
+//CRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL
+#define CRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
+#define CRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
+#define CRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
+#define CRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
+//CRTC4_CRTC_CRC1_DATA_RG
+#define CRTC4_CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+#define CRTC4_CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+#define CRTC4_CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+#define CRTC4_CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+//CRTC4_CRTC_CRC1_DATA_B
+#define CRTC4_CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+#define CRTC4_CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+//CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
+//CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START
+#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
+#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
+#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
+#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
+//CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END
+#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
+#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
+#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
+#define CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
+//CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
+#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
+#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
+#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
+#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
+#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
+#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
+#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
+//CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL
+#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
+#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
+#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
+#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
+#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
+#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
+//CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
+#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
+#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
+#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
+#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
+#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
+#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
+#define CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
+//CRTC4_CRTC_STATIC_SCREEN_CONTROL
+#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
+#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
+#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
+#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
+#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
+#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
+#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
+#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
+#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
+#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
+#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
+#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
+#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
+#define CRTC4_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
+//CRTC4_CRTC_3D_STRUCTURE_CONTROL
+#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
+#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
+#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
+#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
+#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+#define CRTC4_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+//CRTC4_CRTC_GSL_VSYNC_GAP
+#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
+#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+#define CRTC4_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
+//CRTC4_CRTC_GSL_WINDOW
+#define CRTC4_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
+#define CRTC4_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
+#define CRTC4_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
+#define CRTC4_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
+//CRTC4_CRTC_GSL_CONTROL
+#define CRTC4_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
+#define CRTC4_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
+#define CRTC4_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+#define CRTC4_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
+#define CRTC4_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
+#define CRTC4_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+//CRTC4_CRTC_RANGE_TIMING_INT_STATUS
+#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
+#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
+#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
+#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
+#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
+#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
+#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
+#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
+#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
+#define CRTC4_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
+//CRTC4_CRTC_DRR_CONTROL
+#define CRTC4_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY__SHIFT 0x0
+#define CRTC4_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0xe
+#define CRTC4_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS__SHIFT 0x1c
+#define CRTC4_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE__SHIFT 0x1d
+#define CRTC4_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY_MASK 0x00003FFFL
+#define CRTC4_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR_MASK 0x0FFFC000L
+#define CRTC4_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS_MASK 0x10000000L
+#define CRTC4_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE_MASK 0x60000000L
+
+
+// addressBlock: dce_dc_fmt4_dispdec
+//FMT4_FMT_CLAMP_COMPONENT_R
+#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
+#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
+#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
+#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
+//FMT4_FMT_CLAMP_COMPONENT_G
+#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
+#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
+#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
+#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
+//FMT4_FMT_CLAMP_COMPONENT_B
+#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
+#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
+#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
+#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
+//FMT4_FMT_DYNAMIC_EXP_CNTL
+#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
+#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
+#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
+#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
+//FMT4_FMT_CONTROL
+#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
+#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
+#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
+#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
+#define FMT4_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
+#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
+#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
+#define FMT4_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
+#define FMT4_FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
+#define FMT4_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED__SHIFT 0x1e
+#define FMT4_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR__SHIFT 0x1f
+#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
+#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L
+#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
+#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
+#define FMT4_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
+#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
+#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
+#define FMT4_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
+#define FMT4_FMT_CONTROL__FMT_SRC_SELECT_MASK 0x07000000L
+#define FMT4_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_MASK 0x40000000L
+#define FMT4_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR_MASK 0x80000000L
+//FMT4_FMT_BIT_DEPTH_CONTROL
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
+//FMT4_FMT_DITHER_RAND_R_SEED
+#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
+#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
+#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
+#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
+//FMT4_FMT_DITHER_RAND_G_SEED
+#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
+#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
+#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
+#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
+//FMT4_FMT_DITHER_RAND_B_SEED
+#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
+#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
+#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
+#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
+//FMT4_FMT_CLAMP_CNTL
+#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
+#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
+#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
+#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
+//FMT4_FMT_CRC_CNTL
+#define FMT4_FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
+#define FMT4_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
+#define FMT4_FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
+#define FMT4_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5
+#define FMT4_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6
+#define FMT4_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
+#define FMT4_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9
+#define FMT4_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
+#define FMT4_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+#define FMT4_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
+#define FMT4_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
+#define FMT4_FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L
+#define FMT4_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x00000002L
+#define FMT4_FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L
+#define FMT4_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x00000020L
+#define FMT4_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x00000040L
+#define FMT4_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x00000100L
+#define FMT4_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x00000200L
+#define FMT4_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define FMT4_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+#define FMT4_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L
+#define FMT4_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L
+//FMT4_FMT_CRC_SIG_RED_GREEN_MASK
+#define FMT4_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
+#define FMT4_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
+#define FMT4_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
+#define FMT4_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
+//FMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK
+#define FMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
+#define FMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
+#define FMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
+#define FMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
+//FMT4_FMT_CRC_SIG_RED_GREEN
+#define FMT4_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
+#define FMT4_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
+#define FMT4_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000FFFFL
+#define FMT4_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xFFFF0000L
+//FMT4_FMT_CRC_SIG_BLUE_CONTROL
+#define FMT4_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
+#define FMT4_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
+#define FMT4_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000FFFFL
+#define FMT4_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xFFFF0000L
+//FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
+#define FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
+//FMT4_FMT_420_HBLANK_EARLY_START
+#define FMT4_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START__SHIFT 0x0
+#define FMT4_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START_MASK 0x00000FFFL
+
+
+// addressBlock: dce_dc_dcp5_dispdec
+//DCP5_GRPH_ENABLE
+#define DCP5_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
+#define DCP5_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1
+#define DCP5_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
+#define DCP5_GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x00000002L
+//DCP5_GRPH_CONTROL
+#define DCP5_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
+#define DCP5_GRPH_CONTROL__GRPH_SE_ENABLE__SHIFT 0x2
+#define DCP5_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
+#define DCP5_GRPH_CONTROL__GRPH_DIM_TYPE__SHIFT 0x6
+#define DCP5_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
+#define DCP5_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0xc
+#define DCP5_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+#define DCP5_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+#define DCP5_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES__SHIFT 0x12
+#define DCP5_GRPH_CONTROL__GRPH_SW_MODE__SHIFT 0x14
+#define DCP5_GRPH_CONTROL__GRPH_NUM_PIPES__SHIFT 0x1c
+#define DCP5_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
+#define DCP5_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
+#define DCP5_GRPH_CONTROL__GRPH_SE_ENABLE_MASK 0x00000004L
+#define DCP5_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
+#define DCP5_GRPH_CONTROL__GRPH_DIM_TYPE_MASK 0x000000C0L
+#define DCP5_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
+#define DCP5_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x00007000L
+#define DCP5_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
+#define DCP5_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
+#define DCP5_GRPH_CONTROL__GRPH_NUM_SHADER_ENGINES_MASK 0x000C0000L
+#define DCP5_GRPH_CONTROL__GRPH_SW_MODE_MASK 0x01F00000L
+#define DCP5_GRPH_CONTROL__GRPH_NUM_PIPES_MASK 0x70000000L
+#define DCP5_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
+//DCP5_GRPH_LUT_10BIT_BYPASS
+#define DCP5_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
+#define DCP5_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
+#define DCP5_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L
+#define DCP5_GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L
+//DCP5_GRPH_SWAP_CNTL
+#define DCP5_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
+#define DCP5_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
+#define DCP5_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
+#define DCP5_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
+#define DCP5_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
+#define DCP5_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
+#define DCP5_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
+#define DCP5_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
+#define DCP5_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
+#define DCP5_GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000C00L
+//DCP5_GRPH_PRIMARY_SURFACE_ADDRESS
+#define DCP5_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
+#define DCP5_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP5_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L
+#define DCP5_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP5_GRPH_SECONDARY_SURFACE_ADDRESS
+#define DCP5_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
+#define DCP5_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP5_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L
+#define DCP5_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP5_GRPH_PITCH
+#define DCP5_GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
+#define DCP5_GRPH_PITCH__GRPH_PITCH_MASK 0x00007FFFL
+//DCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+#define DCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+#define DCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP5_GRPH_SURFACE_OFFSET_X
+#define DCP5_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
+#define DCP5_GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003FFFL
+//DCP5_GRPH_SURFACE_OFFSET_Y
+#define DCP5_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
+#define DCP5_GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003FFFL
+//DCP5_GRPH_X_START
+#define DCP5_GRPH_X_START__GRPH_X_START__SHIFT 0x0
+#define DCP5_GRPH_X_START__GRPH_X_START_MASK 0x00003FFFL
+//DCP5_GRPH_Y_START
+#define DCP5_GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
+#define DCP5_GRPH_Y_START__GRPH_Y_START_MASK 0x00003FFFL
+//DCP5_GRPH_X_END
+#define DCP5_GRPH_X_END__GRPH_X_END__SHIFT 0x0
+#define DCP5_GRPH_X_END__GRPH_X_END_MASK 0x00007FFFL
+//DCP5_GRPH_Y_END
+#define DCP5_GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
+#define DCP5_GRPH_Y_END__GRPH_Y_END_MASK 0x00007FFFL
+//DCP5_INPUT_GAMMA_CONTROL
+#define DCP5_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
+#define DCP5_INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000001L
+//DCP5_GRPH_UPDATE
+#define DCP5_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
+#define DCP5_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
+#define DCP5_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
+#define DCP5_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
+#define DCP5_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR__SHIFT 0x8
+#define DCP5_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE__SHIFT 0x9
+#define DCP5_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE__SHIFT 0xa
+#define DCP5_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
+#define DCP5_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
+#define DCP5_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define DCP5_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
+#define DCP5_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
+#define DCP5_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
+#define DCP5_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
+#define DCP5_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
+#define DCP5_GRPH_UPDATE__GRPH_XDMA_FLIP_TYPE_CLEAR_MASK 0x00000100L
+#define DCP5_GRPH_UPDATE__GRPH_XDMA_DRR_MODE_ENABLE_MASK 0x00000200L
+#define DCP5_GRPH_UPDATE__GRPH_XDMA_MULTIFLIP_ENABLE_MASK 0x00000400L
+#define DCP5_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
+#define DCP5_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
+#define DCP5_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+#define DCP5_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
+//DCP5_GRPH_FLIP_CONTROL
+#define DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
+#define DCP5_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
+#define DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4
+#define DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5
+#define DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L
+#define DCP5_GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x00000002L
+#define DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x00000010L
+#define DCP5_GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000020L
+//DCP5_GRPH_SURFACE_ADDRESS_INUSE
+#define DCP5_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
+#define DCP5_GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xFFFFFF00L
+//DCP5_GRPH_DFQ_CONTROL
+#define DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
+#define DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
+#define DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
+#define DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L
+#define DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L
+#define DCP5_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L
+//DCP5_GRPH_DFQ_STATUS
+#define DCP5_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
+#define DCP5_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
+#define DCP5_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
+#define DCP5_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
+#define DCP5_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000FL
+#define DCP5_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000F0L
+#define DCP5_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L
+#define DCP5_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L
+//DCP5_GRPH_INTERRUPT_STATUS
+#define DCP5_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
+#define DCP5_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
+#define DCP5_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
+#define DCP5_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
+//DCP5_GRPH_INTERRUPT_CONTROL
+#define DCP5_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
+#define DCP5_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
+#define DCP5_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
+#define DCP5_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
+//DCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE
+#define DCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
+#define DCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000FFL
+//DCP5_GRPH_COMPRESS_SURFACE_ADDRESS
+#define DCP5_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP5_GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP5_GRPH_COMPRESS_PITCH
+#define DCP5_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
+#define DCP5_GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001FFC0L
+//DCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH
+#define DCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
+#define DCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0
+#define DCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0x000000FFL
+//DCP5_PRESCALE_GRPH_CONTROL
+#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
+#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
+#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
+#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
+#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
+#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L
+#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L
+#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L
+#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L
+#define DCP5_PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L
+//DCP5_PRESCALE_VALUES_GRPH_R
+#define DCP5_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
+#define DCP5_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
+#define DCP5_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000FFFFL
+#define DCP5_PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xFFFF0000L
+//DCP5_PRESCALE_VALUES_GRPH_G
+#define DCP5_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
+#define DCP5_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
+#define DCP5_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000FFFFL
+#define DCP5_PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xFFFF0000L
+//DCP5_PRESCALE_VALUES_GRPH_B
+#define DCP5_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
+#define DCP5_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
+#define DCP5_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000FFFFL
+#define DCP5_PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xFFFF0000L
+//DCP5_INPUT_CSC_CONTROL
+#define DCP5_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
+#define DCP5_INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L
+//DCP5_INPUT_CSC_C11_C12
+#define DCP5_INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
+#define DCP5_INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
+#define DCP5_INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000FFFFL
+#define DCP5_INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xFFFF0000L
+//DCP5_INPUT_CSC_C13_C14
+#define DCP5_INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
+#define DCP5_INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
+#define DCP5_INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000FFFFL
+#define DCP5_INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xFFFF0000L
+//DCP5_INPUT_CSC_C21_C22
+#define DCP5_INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
+#define DCP5_INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
+#define DCP5_INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000FFFFL
+#define DCP5_INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xFFFF0000L
+//DCP5_INPUT_CSC_C23_C24
+#define DCP5_INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
+#define DCP5_INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
+#define DCP5_INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000FFFFL
+#define DCP5_INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xFFFF0000L
+//DCP5_INPUT_CSC_C31_C32
+#define DCP5_INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
+#define DCP5_INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
+#define DCP5_INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000FFFFL
+#define DCP5_INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xFFFF0000L
+//DCP5_INPUT_CSC_C33_C34
+#define DCP5_INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
+#define DCP5_INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
+#define DCP5_INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000FFFFL
+#define DCP5_INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xFFFF0000L
+//DCP5_OUTPUT_CSC_CONTROL
+#define DCP5_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
+#define DCP5_OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L
+//DCP5_OUTPUT_CSC_C11_C12
+#define DCP5_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
+#define DCP5_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
+#define DCP5_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000FFFFL
+#define DCP5_OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xFFFF0000L
+//DCP5_OUTPUT_CSC_C13_C14
+#define DCP5_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
+#define DCP5_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
+#define DCP5_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000FFFFL
+#define DCP5_OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xFFFF0000L
+//DCP5_OUTPUT_CSC_C21_C22
+#define DCP5_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
+#define DCP5_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
+#define DCP5_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000FFFFL
+#define DCP5_OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xFFFF0000L
+//DCP5_OUTPUT_CSC_C23_C24
+#define DCP5_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
+#define DCP5_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
+#define DCP5_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000FFFFL
+#define DCP5_OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xFFFF0000L
+//DCP5_OUTPUT_CSC_C31_C32
+#define DCP5_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
+#define DCP5_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
+#define DCP5_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000FFFFL
+#define DCP5_OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xFFFF0000L
+//DCP5_OUTPUT_CSC_C33_C34
+#define DCP5_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
+#define DCP5_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
+#define DCP5_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000FFFFL
+#define DCP5_OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xFFFF0000L
+//DCP5_COMM_MATRIXA_TRANS_C11_C12
+#define DCP5_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
+#define DCP5_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
+#define DCP5_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000FFFFL
+#define DCP5_COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xFFFF0000L
+//DCP5_COMM_MATRIXA_TRANS_C13_C14
+#define DCP5_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
+#define DCP5_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
+#define DCP5_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000FFFFL
+#define DCP5_COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xFFFF0000L
+//DCP5_COMM_MATRIXA_TRANS_C21_C22
+#define DCP5_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
+#define DCP5_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
+#define DCP5_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000FFFFL
+#define DCP5_COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xFFFF0000L
+//DCP5_COMM_MATRIXA_TRANS_C23_C24
+#define DCP5_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
+#define DCP5_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
+#define DCP5_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000FFFFL
+#define DCP5_COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xFFFF0000L
+//DCP5_COMM_MATRIXA_TRANS_C31_C32
+#define DCP5_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
+#define DCP5_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
+#define DCP5_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000FFFFL
+#define DCP5_COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xFFFF0000L
+//DCP5_COMM_MATRIXA_TRANS_C33_C34
+#define DCP5_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
+#define DCP5_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
+#define DCP5_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000FFFFL
+#define DCP5_COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xFFFF0000L
+//DCP5_COMM_MATRIXB_TRANS_C11_C12
+#define DCP5_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
+#define DCP5_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
+#define DCP5_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000FFFFL
+#define DCP5_COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xFFFF0000L
+//DCP5_COMM_MATRIXB_TRANS_C13_C14
+#define DCP5_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
+#define DCP5_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
+#define DCP5_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000FFFFL
+#define DCP5_COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xFFFF0000L
+//DCP5_COMM_MATRIXB_TRANS_C21_C22
+#define DCP5_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
+#define DCP5_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
+#define DCP5_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000FFFFL
+#define DCP5_COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xFFFF0000L
+//DCP5_COMM_MATRIXB_TRANS_C23_C24
+#define DCP5_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
+#define DCP5_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
+#define DCP5_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000FFFFL
+#define DCP5_COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xFFFF0000L
+//DCP5_COMM_MATRIXB_TRANS_C31_C32
+#define DCP5_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
+#define DCP5_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
+#define DCP5_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000FFFFL
+#define DCP5_COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xFFFF0000L
+//DCP5_COMM_MATRIXB_TRANS_C33_C34
+#define DCP5_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
+#define DCP5_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
+#define DCP5_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000FFFFL
+#define DCP5_COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xFFFF0000L
+//DCP5_DENORM_CONTROL
+#define DCP5_DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
+#define DCP5_DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
+#define DCP5_DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L
+#define DCP5_DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x00000010L
+//DCP5_OUT_ROUND_CONTROL
+#define DCP5_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
+#define DCP5_OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000FL
+//DCP5_OUT_CLAMP_CONTROL_R_CR
+#define DCP5_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
+#define DCP5_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
+#define DCP5_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x00003FFFL
+#define DCP5_OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3FFF0000L
+//DCP5_OUT_CLAMP_CONTROL_G_Y
+#define DCP5_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
+#define DCP5_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
+#define DCP5_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x00003FFFL
+#define DCP5_OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3FFF0000L
+//DCP5_OUT_CLAMP_CONTROL_B_CB
+#define DCP5_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
+#define DCP5_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
+#define DCP5_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x00003FFFL
+#define DCP5_OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3FFF0000L
+//DCP5_KEY_CONTROL
+#define DCP5_KEY_CONTROL__KEY_MODE__SHIFT 0x1
+#define DCP5_KEY_CONTROL__KEY_MODE_MASK 0x00000006L
+//DCP5_KEY_RANGE_ALPHA
+#define DCP5_KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
+#define DCP5_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
+#define DCP5_KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000FFFFL
+#define DCP5_KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xFFFF0000L
+//DCP5_KEY_RANGE_RED
+#define DCP5_KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
+#define DCP5_KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
+#define DCP5_KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000FFFFL
+#define DCP5_KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xFFFF0000L
+//DCP5_KEY_RANGE_GREEN
+#define DCP5_KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
+#define DCP5_KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
+#define DCP5_KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000FFFFL
+#define DCP5_KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xFFFF0000L
+//DCP5_KEY_RANGE_BLUE
+#define DCP5_KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
+#define DCP5_KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
+#define DCP5_KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000FFFFL
+#define DCP5_KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xFFFF0000L
+//DCP5_DEGAMMA_CONTROL
+#define DCP5_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
+#define DCP5_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
+#define DCP5_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
+#define DCP5_DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L
+#define DCP5_DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x00000300L
+#define DCP5_DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L
+//DCP5_GAMUT_REMAP_CONTROL
+#define DCP5_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
+#define DCP5_GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L
+//DCP5_GAMUT_REMAP_C11_C12
+#define DCP5_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
+#define DCP5_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
+#define DCP5_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000FFFFL
+#define DCP5_GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xFFFF0000L
+//DCP5_GAMUT_REMAP_C13_C14
+#define DCP5_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
+#define DCP5_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
+#define DCP5_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000FFFFL
+#define DCP5_GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xFFFF0000L
+//DCP5_GAMUT_REMAP_C21_C22
+#define DCP5_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
+#define DCP5_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
+#define DCP5_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000FFFFL
+#define DCP5_GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xFFFF0000L
+//DCP5_GAMUT_REMAP_C23_C24
+#define DCP5_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
+#define DCP5_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
+#define DCP5_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000FFFFL
+#define DCP5_GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xFFFF0000L
+//DCP5_GAMUT_REMAP_C31_C32
+#define DCP5_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
+#define DCP5_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
+#define DCP5_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000FFFFL
+#define DCP5_GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xFFFF0000L
+//DCP5_GAMUT_REMAP_C33_C34
+#define DCP5_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
+#define DCP5_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
+#define DCP5_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000FFFFL
+#define DCP5_GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xFFFF0000L
+//DCP5_DCP_SPATIAL_DITHER_CNTL
+#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
+#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
+#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
+#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
+#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
+#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
+#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L
+#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L
+#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x000000C0L
+#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L
+#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L
+#define DCP5_DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L
+//DCP5_DCP_RANDOM_SEEDS
+#define DCP5_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
+#define DCP5_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
+#define DCP5_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
+#define DCP5_DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000FFL
+#define DCP5_DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000FF00L
+#define DCP5_DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00FF0000L
+//DCP5_DCP_FP_CONVERTED_FIELD
+#define DCP5_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
+#define DCP5_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
+#define DCP5_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
+#define DCP5_DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
+//DCP5_CUR_CONTROL
+#define DCP5_CUR_CONTROL__CURSOR_EN__SHIFT 0x0
+#define DCP5_CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
+#define DCP5_CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
+#define DCP5_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM__SHIFT 0xb
+#define DCP5_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT 0xc
+#define DCP5_CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
+#define DCP5_CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
+#define DCP5_CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
+#define DCP5_CUR_CONTROL__CURSOR_EN_MASK 0x00000001L
+#define DCP5_CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L
+#define DCP5_CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L
+#define DCP5_CUR_CONTROL__CURSOR_MAX_OUTSTANDING_GROUP_NUM_MASK 0x00000800L
+#define DCP5_CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK 0x0000F000L
+#define DCP5_CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L
+#define DCP5_CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L
+#define DCP5_CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L
+//DCP5_CUR_SURFACE_ADDRESS
+#define DCP5_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
+#define DCP5_CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//DCP5_CUR_SIZE
+#define DCP5_CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
+#define DCP5_CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
+#define DCP5_CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000007FL
+#define DCP5_CUR_SIZE__CURSOR_WIDTH_MASK 0x007F0000L
+//DCP5_CUR_SURFACE_ADDRESS_HIGH
+#define DCP5_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP5_CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP5_CUR_POSITION
+#define DCP5_CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
+#define DCP5_CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
+#define DCP5_CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
+#define DCP5_CUR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
+//DCP5_CUR_HOT_SPOT
+#define DCP5_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
+#define DCP5_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
+#define DCP5_CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000007FL
+#define DCP5_CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x007F0000L
+//DCP5_CUR_COLOR1
+#define DCP5_CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
+#define DCP5_CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
+#define DCP5_CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
+#define DCP5_CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000FFL
+#define DCP5_CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000FF00L
+#define DCP5_CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00FF0000L
+//DCP5_CUR_COLOR2
+#define DCP5_CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
+#define DCP5_CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
+#define DCP5_CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
+#define DCP5_CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000FFL
+#define DCP5_CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000FF00L
+#define DCP5_CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00FF0000L
+//DCP5_CUR_UPDATE
+#define DCP5_CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
+#define DCP5_CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
+#define DCP5_CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
+#define DCP5_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define DCP5_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
+#define DCP5_CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L
+#define DCP5_CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L
+#define DCP5_CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L
+#define DCP5_CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+#define DCP5_CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x06000000L
+//DCP5_CUR_REQUEST_FILTER_CNTL
+#define DCP5_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
+#define DCP5_CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L
+//DCP5_CUR_STEREO_CONTROL
+#define DCP5_CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
+#define DCP5_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
+#define DCP5_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
+#define DCP5_CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
+#define DCP5_CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x00003FF0L
+#define DCP5_CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x03FF0000L
+//DCP5_DC_LUT_RW_MODE
+#define DCP5_DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
+#define DCP5_DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
+#define DCP5_DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
+#define DCP5_DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L
+#define DCP5_DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x00010000L
+#define DCP5_DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x00020000L
+//DCP5_DC_LUT_RW_INDEX
+#define DCP5_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
+#define DCP5_DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000FFL
+//DCP5_DC_LUT_SEQ_COLOR
+#define DCP5_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
+#define DCP5_DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000FFFFL
+//DCP5_DC_LUT_PWL_DATA
+#define DCP5_DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
+#define DCP5_DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
+#define DCP5_DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000FFFFL
+#define DCP5_DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xFFFF0000L
+//DCP5_DC_LUT_30_COLOR
+#define DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
+#define DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
+#define DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
+#define DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003FFL
+#define DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
+#define DCP5_DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3FF00000L
+//DCP5_DC_LUT_VGA_ACCESS_ENABLE
+#define DCP5_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
+#define DCP5_DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L
+//DCP5_DC_LUT_WRITE_EN_MASK
+#define DCP5_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define DCP5_DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L
+//DCP5_DC_LUT_AUTOFILL
+#define DCP5_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
+#define DCP5_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
+#define DCP5_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L
+#define DCP5_DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L
+//DCP5_DC_LUT_CONTROL
+#define DCP5_DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
+#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
+#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
+#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
+#define DCP5_DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
+#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
+#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
+#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
+#define DCP5_DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
+#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
+#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
+#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
+#define DCP5_DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000FL
+#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L
+#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L
+#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000C0L
+#define DCP5_DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000F00L
+#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L
+#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L
+#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000C000L
+#define DCP5_DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000F0000L
+#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L
+#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L
+#define DCP5_DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00C00000L
+//DCP5_DC_LUT_BLACK_OFFSET_BLUE
+#define DCP5_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
+#define DCP5_DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL
+//DCP5_DC_LUT_BLACK_OFFSET_GREEN
+#define DCP5_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
+#define DCP5_DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL
+//DCP5_DC_LUT_BLACK_OFFSET_RED
+#define DCP5_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
+#define DCP5_DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL
+//DCP5_DC_LUT_WHITE_OFFSET_BLUE
+#define DCP5_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
+#define DCP5_DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000FFFFL
+//DCP5_DC_LUT_WHITE_OFFSET_GREEN
+#define DCP5_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
+#define DCP5_DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000FFFFL
+//DCP5_DC_LUT_WHITE_OFFSET_RED
+#define DCP5_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
+#define DCP5_DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000FFFFL
+//DCP5_DCP_CRC_CONTROL
+#define DCP5_DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
+#define DCP5_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
+#define DCP5_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
+#define DCP5_DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L
+#define DCP5_DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001CL
+#define DCP5_DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L
+//DCP5_DCP_CRC_MASK
+#define DCP5_DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
+#define DCP5_DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xFFFFFFFFL
+//DCP5_DCP_CRC_CURRENT
+#define DCP5_DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
+#define DCP5_DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xFFFFFFFFL
+//DCP5_DVMM_PTE_CONTROL
+#define DCP5_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
+#define DCP5_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
+#define DCP5_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
+#define DCP5_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
+#define DCP5_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
+#define DCP5_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
+#define DCP5_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
+#define DCP5_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
+#define DCP5_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
+#define DCP5_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
+#define DCP5_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
+#define DCP5_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
+//DCP5_DCP_CRC_LAST
+#define DCP5_DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
+#define DCP5_DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xFFFFFFFFL
+//DCP5_DVMM_PTE_ARB_CONTROL
+#define DCP5_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
+#define DCP5_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
+#define DCP5_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
+#define DCP5_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
+//DCP5_GRPH_FLIP_RATE_CNTL
+#define DCP5_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
+#define DCP5_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
+#define DCP5_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x00000007L
+#define DCP5_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x00000008L
+//DCP5_DCP_GSL_CONTROL
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x4
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x14
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x15
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x17
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__SHIFT 0x1a
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x000FFFF0L
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00100000L
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x00600000L
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x00800000L
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_MASK 0x04000000L
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L
+#define DCP5_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xF0000000L
+//DCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK
+#define DCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
+#define DCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
+#define DCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000FL
+#define DCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000001F0L
+//DCP5_GRPH_STEREOSYNC_FLIP
+#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
+#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
+#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
+#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L
+#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
+#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
+#define DCP5_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
+//DCP5_HW_ROTATION
+#define DCP5_HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
+#define DCP5_HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x00000007L
+//DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL
+#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
+#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
+#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
+#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x00000001L
+#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x00000002L
+#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x0001FFF0L
+//DCP5_REGAMMA_CONTROL
+#define DCP5_REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
+#define DCP5_REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L
+//DCP5_REGAMMA_LUT_INDEX
+#define DCP5_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
+#define DCP5_REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001FFL
+//DCP5_REGAMMA_LUT_DATA
+#define DCP5_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
+#define DCP5_REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007FFFFL
+//DCP5_REGAMMA_LUT_WRITE_EN_MASK
+#define DCP5_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define DCP5_REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
+//DCP5_REGAMMA_CNTLA_START_CNTL
+#define DCP5_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define DCP5_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
+#define DCP5_REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+//DCP5_REGAMMA_CNTLA_SLOPE_CNTL
+#define DCP5_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+//DCP5_REGAMMA_CNTLA_END_CNTL1
+#define DCP5_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
+//DCP5_REGAMMA_CNTLA_END_CNTL2
+#define DCP5_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
+#define DCP5_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+#define DCP5_REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+//DCP5_REGAMMA_CNTLA_REGION_0_1
+#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP5_REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//DCP5_REGAMMA_CNTLA_REGION_2_3
+#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP5_REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//DCP5_REGAMMA_CNTLA_REGION_4_5
+#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP5_REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//DCP5_REGAMMA_CNTLA_REGION_6_7
+#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP5_REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//DCP5_REGAMMA_CNTLA_REGION_8_9
+#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP5_REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//DCP5_REGAMMA_CNTLA_REGION_10_11
+#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP5_REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//DCP5_REGAMMA_CNTLA_REGION_12_13
+#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP5_REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//DCP5_REGAMMA_CNTLA_REGION_14_15
+#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP5_REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//DCP5_REGAMMA_CNTLB_START_CNTL
+#define DCP5_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define DCP5_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
+#define DCP5_REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+//DCP5_REGAMMA_CNTLB_SLOPE_CNTL
+#define DCP5_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+//DCP5_REGAMMA_CNTLB_END_CNTL1
+#define DCP5_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
+//DCP5_REGAMMA_CNTLB_END_CNTL2
+#define DCP5_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
+#define DCP5_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+#define DCP5_REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+//DCP5_REGAMMA_CNTLB_REGION_0_1
+#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP5_REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//DCP5_REGAMMA_CNTLB_REGION_2_3
+#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP5_REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//DCP5_REGAMMA_CNTLB_REGION_4_5
+#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP5_REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//DCP5_REGAMMA_CNTLB_REGION_6_7
+#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP5_REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//DCP5_REGAMMA_CNTLB_REGION_8_9
+#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP5_REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//DCP5_REGAMMA_CNTLB_REGION_10_11
+#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP5_REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//DCP5_REGAMMA_CNTLB_REGION_12_13
+#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP5_REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//DCP5_REGAMMA_CNTLB_REGION_14_15
+#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define DCP5_REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//DCP5_ALPHA_CONTROL
+#define DCP5_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
+#define DCP5_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
+#define DCP5_ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x00000001L
+#define DCP5_ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x00000002L
+//DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS
+#define DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
+#define DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xFFFFFF00L
+//DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH
+#define DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0x000000FFL
+//DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS
+#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
+#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
+#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
+#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
+#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
+#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
+#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
+#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0x000FFFFFL
+#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x01000000L
+#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x02000000L
+#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x04000000L
+#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000L
+#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000L
+#define DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000L
+//DCP5_GRPH_XDMA_FLIP_TIMEOUT
+#define DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS__SHIFT 0x0
+#define DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK__SHIFT 0x1
+#define DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK__SHIFT 0x2
+#define DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_STATUS_MASK 0x00000001L
+#define DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_MASK_MASK 0x00000002L
+#define DCP5_GRPH_XDMA_FLIP_TIMEOUT__GRPH_XDMA_FLIP_TIMEOUT_ACK_MASK 0x00000004L
+//DCP5_GRPH_XDMA_FLIP_AVG_DELAY
+#define DCP5_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY__SHIFT 0x0
+#define DCP5_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD__SHIFT 0x10
+#define DCP5_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_DELAY_MASK 0x0000FFFFL
+#define DCP5_GRPH_XDMA_FLIP_AVG_DELAY__GRPH_XDMA_FLIP_AVG_PERIOD_MASK 0x00FF0000L
+//DCP5_GRPH_SURFACE_COUNTER_CONTROL
+#define DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0
+#define DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1
+#define DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9
+#define DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x00000001L
+#define DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x0000001EL
+#define DCP5_GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x00000200L
+//DCP5_GRPH_SURFACE_COUNTER_OUTPUT
+#define DCP5_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0
+#define DCP5_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10
+#define DCP5_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0x0000FFFFL
+#define DCP5_GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_lb5_dispdec
+//LB5_LB_DATA_FORMAT
+#define LB5_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
+#define LB5_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
+#define LB5_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
+#define LB5_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
+#define LB5_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
+#define LB5_LB_DATA_FORMAT__PREFILL_EN__SHIFT 0x8
+#define LB5_LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
+#define LB5_LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
+#define LB5_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
+#define LB5_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
+#define LB5_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
+#define LB5_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
+#define LB5_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
+#define LB5_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
+#define LB5_LB_DATA_FORMAT__PREFILL_EN_MASK 0x00000100L
+#define LB5_LB_DATA_FORMAT__PREFETCH_MASK 0x00001000L
+#define LB5_LB_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
+#define LB5_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
+//LB5_LB_MEMORY_CTRL
+#define LB5_LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
+#define LB5_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+#define LB5_LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
+#define LB5_LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00001FFFL
+#define LB5_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
+#define LB5_LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
+//LB5_LB_MEMORY_SIZE_STATUS
+#define LB5_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
+#define LB5_LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00001FFFL
+//LB5_LB_DESKTOP_HEIGHT
+#define LB5_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
+#define LB5_LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
+//LB5_LB_VLINE_START_END
+#define LB5_LB_VLINE_START_END__VLINE_START__SHIFT 0x0
+#define LB5_LB_VLINE_START_END__VLINE_END__SHIFT 0x10
+#define LB5_LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
+#define LB5_LB_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
+#define LB5_LB_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
+#define LB5_LB_VLINE_START_END__VLINE_INV_MASK 0x80000000L
+//LB5_LB_VLINE2_START_END
+#define LB5_LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
+#define LB5_LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
+#define LB5_LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
+#define LB5_LB_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
+#define LB5_LB_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
+#define LB5_LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
+//LB5_LB_V_COUNTER
+#define LB5_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
+#define LB5_LB_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
+//LB5_LB_SNAPSHOT_V_COUNTER
+#define LB5_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
+#define LB5_LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
+//LB5_LB_INTERRUPT_MASK
+#define LB5_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
+#define LB5_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
+#define LB5_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
+#define LB5_LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
+#define LB5_LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
+#define LB5_LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
+//LB5_LB_VLINE_STATUS
+#define LB5_LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
+#define LB5_LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
+#define LB5_LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
+#define LB5_LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
+#define LB5_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
+#define LB5_LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
+#define LB5_LB_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
+#define LB5_LB_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
+#define LB5_LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
+#define LB5_LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
+//LB5_LB_VLINE2_STATUS
+#define LB5_LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
+#define LB5_LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
+#define LB5_LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
+#define LB5_LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
+#define LB5_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
+#define LB5_LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
+#define LB5_LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
+#define LB5_LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
+#define LB5_LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
+#define LB5_LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
+//LB5_LB_VBLANK_STATUS
+#define LB5_LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
+#define LB5_LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
+#define LB5_LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
+#define LB5_LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
+#define LB5_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
+#define LB5_LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
+#define LB5_LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
+#define LB5_LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
+#define LB5_LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
+#define LB5_LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
+//LB5_LB_SYNC_RESET_SEL
+#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
+#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
+#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
+#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
+#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
+#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
+#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
+#define LB5_LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
+//LB5_LB_BLACK_KEYER_R_CR
+#define LB5_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
+#define LB5_LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
+//LB5_LB_BLACK_KEYER_G_Y
+#define LB5_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
+#define LB5_LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
+//LB5_LB_BLACK_KEYER_B_CB
+#define LB5_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
+#define LB5_LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
+//LB5_LB_KEYER_COLOR_CTRL
+#define LB5_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
+#define LB5_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
+#define LB5_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
+#define LB5_LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
+//LB5_LB_KEYER_COLOR_R_CR
+#define LB5_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
+#define LB5_LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
+//LB5_LB_KEYER_COLOR_G_Y
+#define LB5_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
+#define LB5_LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
+//LB5_LB_KEYER_COLOR_B_CB
+#define LB5_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
+#define LB5_LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
+//LB5_LB_KEYER_COLOR_REP_R_CR
+#define LB5_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
+#define LB5_LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
+//LB5_LB_KEYER_COLOR_REP_G_Y
+#define LB5_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
+#define LB5_LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
+//LB5_LB_KEYER_COLOR_REP_B_CB
+#define LB5_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
+#define LB5_LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
+//LB5_LB_BUFFER_LEVEL_STATUS
+#define LB5_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
+#define LB5_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
+#define LB5_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
+#define LB5_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
+#define LB5_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
+#define LB5_LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
+#define LB5_LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
+#define LB5_LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
+//LB5_LB_BUFFER_URGENCY_CTRL
+#define LB5_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
+#define LB5_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
+#define LB5_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
+#define LB5_LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
+//LB5_LB_BUFFER_URGENCY_STATUS
+#define LB5_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
+#define LB5_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
+#define LB5_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
+#define LB5_LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
+//LB5_LB_BUFFER_STATUS
+#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
+#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
+#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
+#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
+#define LB5_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
+#define LB5_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
+#define LB5_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
+#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
+#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
+#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
+#define LB5_LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
+#define LB5_LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
+#define LB5_LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
+#define LB5_LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
+//LB5_LB_NO_OUTSTANDING_REQ_STATUS
+#define LB5_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
+#define LB5_LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
+//LB5_MVP_AFR_FLIP_MODE
+#define LB5_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
+#define LB5_MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L
+//LB5_MVP_AFR_FLIP_FIFO_CNTL
+#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
+#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
+#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
+#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
+#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000FL
+#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L
+#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L
+#define LB5_MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L
+//LB5_MVP_FLIP_LINE_NUM_INSERT
+#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
+#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
+#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
+#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
+#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L
+#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007FFF00L
+#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3F000000L
+#define LB5_MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L
+//LB5_DC_MVP_LB_CONTROL
+#define LB5_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
+#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
+#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
+#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
+#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
+#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
+#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
+#define LB5_DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L
+#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L
+#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L
+#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L
+#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L
+#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L
+#define LB5_DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L
+
+
+// addressBlock: dce_dc_dcfe5_dispdec
+//DCFE5_DCFE_CLOCK_CONTROL
+#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
+#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
+#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
+#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf
+#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT 0x11
+#define DCFE5_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
+#define DCFE5_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
+#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L
+#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L
+#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L
+#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x00008000L
+#define DCFE5_DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK 0x00020000L
+#define DCFE5_DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1F000000L
+#define DCFE5_DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000L
+//DCFE5_DCFE_SOFT_RESET
+#define DCFE5_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
+#define DCFE5_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
+#define DCFE5_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
+#define DCFE5_DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
+#define DCFE5_DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
+#define DCFE5_DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5
+#define DCFE5_DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
+#define DCFE5_DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x00000002L
+#define DCFE5_DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x00000004L
+#define DCFE5_DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x00000008L
+#define DCFE5_DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
+#define DCFE5_DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x00000020L
+//DCFE5_DCFE_MEM_PWR_CTRL
+#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
+#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
+#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
+#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
+#define DCFE5_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
+#define DCFE5_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
+#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
+#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
+#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x00000003L
+#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x00000004L
+#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x00000018L
+#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x00000020L
+#define DCFE5_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
+#define DCFE5_DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x00000100L
+#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x00000600L
+#define DCFE5_DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x00000800L
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x00003000L
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x00004000L
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x00018000L
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x00020000L
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0x000C0000L
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x00100000L
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x00600000L
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x00800000L
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x03000000L
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x04000000L
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000L
+#define DCFE5_DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000L
+//DCFE5_DCFE_MEM_PWR_CTRL2
+#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
+#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
+#define DCFE5_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
+#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
+#define DCFE5_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
+#define DCFE5_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
+#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
+#define DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
+#define DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
+#define DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
+#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
+#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
+#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x00000003L
+#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
+#define DCFE5_DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
+#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0x000000C0L
+#define DCFE5_DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x00000300L
+#define DCFE5_DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0x00000C00L
+#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x00003000L
+#define DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0x0000C000L
+#define DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x00030000L
+#define DCFE5_DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x00040000L
+#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x00600000L
+#define DCFE5_DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x00800000L
+//DCFE5_DCFE_MEM_PWR_STATUS
+#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
+#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
+#define DCFE5_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
+#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
+#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
+#define DCFE5_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
+#define DCFE5_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
+#define DCFE5_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
+#define DCFE5_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
+#define DCFE5_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
+#define DCFE5_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
+#define DCFE5_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
+#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x00000003L
+#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0x0000000CL
+#define DCFE5_DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x00000030L
+#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0x000000C0L
+#define DCFE5_DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x00000300L
+#define DCFE5_DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0x00000C00L
+#define DCFE5_DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x00003000L
+#define DCFE5_DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0x0000C000L
+#define DCFE5_DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x00030000L
+#define DCFE5_DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0x000C0000L
+#define DCFE5_DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x00300000L
+#define DCFE5_DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0x00C00000L
+//DCFE5_DCFE_MISC
+#define DCFE5_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
+#define DCFE5_DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
+//DCFE5_DCFE_FLUSH
+#define DCFE5_DCFE_FLUSH__FLUSH_OCCURED__SHIFT 0x0
+#define DCFE5_DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
+#define DCFE5_DCFE_FLUSH__FLUSH_DEEP__SHIFT 0x2
+#define DCFE5_DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
+#define DCFE5_DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
+#define DCFE5_DCFE_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
+#define DCFE5_DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
+#define DCFE5_DCFE_FLUSH__FLUSH_DEEP_MASK 0x00000004L
+#define DCFE5_DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
+#define DCFE5_DCFE_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
+
+
+// addressBlock: dce_dc_dc_perfmon8_dispdec
+//DC_PERFMON8_PERFCOUNTER_CNTL
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON8_PERFCOUNTER_CNTL2
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON8_PERFCOUNTER_STATE
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON8_PERFMON_CNTL
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON8_PERFMON_CNTL2
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON8_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON8_PERFMON_CVALUE_LOW
+#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON8_PERFMON_HI
+#define DC_PERFMON8_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON8_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON8_PERFMON_LOW
+#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dmif_pg5_dispdec
+//DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1
+#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
+#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
+//DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2
+#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
+#define DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
+//DMIF_PG5_DPG_WATERMARK_MASK_CONTROL
+#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x4
+#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK__SHIFT 0xc
+#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0xf
+#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x12
+#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL__SHIFT 0x13
+#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL__SHIFT 0x14
+#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000007L
+#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000070L
+#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000700L
+#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_WATERMARK_MASK_MASK 0x00007000L
+#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00038000L
+#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x00040000L
+#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__URGENT_LEVEL_RAMP_CONTROL_MASK 0x00080000L
+#define DMIF_PG5_DPG_WATERMARK_MASK_CONTROL__STATIC_URGENT_LEVEL_MASK 0x3FF00000L
+//DMIF_PG5_DPG_PIPE_URGENCY_CONTROL
+#define DMIF_PG5_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+#define DMIF_PG5_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+#define DMIF_PG5_DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
+#define DMIF_PG5_DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
+//DMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL
+#define DMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK__SHIFT 0x0
+#define DMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK__SHIFT 0x10
+#define DMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_LOW_WATERMARK_MASK 0x0000FFFFL
+#define DMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL__URGENT_LEVEL_HIGH_WATERMARK_MASK 0xFFFF0000L
+//DMIF_PG5_DPG_PIPE_STUTTER_CONTROL
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH__SHIFT 0x10
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x14
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x15
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x16
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x17
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x1a
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x1b
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_NONLPTCH_MASK 0x00010000L
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00100000L
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00200000L
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00400000L
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00800000L
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x04000000L
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x08000000L
+//DMIF_PG5_DPG_PIPE_STUTTER_CONTROL2
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x0
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK__SHIFT 0x10
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL2__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0x0000FFFFL
+#define DMIF_PG5_DPG_PIPE_STUTTER_CONTROL2__STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
+//DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL
+#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE__SHIFT 0x0
+#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE__SHIFT 0x1
+#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK__SHIFT 0xf
+#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_ENABLE_MASK 0x00000001L
+#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__DPM_ENABLE_MASK 0x00000002L
+#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
+#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
+#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
+#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
+#define DMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL__PSTATE_CHANGE_WATERMARK_MASK 0xFFFF8000L
+//DMIF_PG5_DPG_REPEATER_PROGRAM
+#define DMIF_PG5_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+#define DMIF_PG5_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+#define DMIF_PG5_DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
+#define DMIF_PG5_DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
+//DMIF_PG5_DPG_CHK_PRE_PROC_CNTL
+#define DMIF_PG5_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+#define DMIF_PG5_DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
+//DMIF_PG5_DPG_DVMM_STATUS
+#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT 0x0
+#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT 0x1
+#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT 0x4
+#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT 0x5
+#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK 0x00000001L
+#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK 0x00000002L
+#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK 0x00000010L
+#define DMIF_PG5_DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK 0x00000020L
+
+
+// addressBlock: dce_dc_scl5_dispdec
+//SCL5_SCL_COEF_RAM_SELECT
+#define SCL5_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define SCL5_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
+#define SCL5_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
+#define SCL5_SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000FL
+#define SCL5_SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000F00L
+#define SCL5_SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00070000L
+//SCL5_SCL_COEF_RAM_TAP_DATA
+#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+#define SCL5_SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+//SCL5_SCL_MODE
+#define SCL5_SCL_MODE__SCL_MODE__SHIFT 0x0
+#define SCL5_SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
+#define SCL5_SCL_MODE__SCL_MODE_MASK 0x00000003L
+#define SCL5_SCL_MODE__SCL_PSCL_EN_MASK 0x00000010L
+//SCL5_SCL_TAP_CONTROL
+#define SCL5_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
+#define SCL5_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
+#define SCL5_SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
+#define SCL5_SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000F00L
+//SCL5_SCL_CONTROL
+#define SCL5_SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+#define SCL5_SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
+#define SCL5_SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+#define SCL5_SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
+//SCL5_SCL_BYPASS_CONTROL
+#define SCL5_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
+#define SCL5_SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L
+//SCL5_SCL_MANUAL_REPLICATE_CONTROL
+#define SCL5_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+#define SCL5_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+#define SCL5_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+#define SCL5_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+//SCL5_SCL_AUTOMATIC_MODE_CONTROL
+#define SCL5_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
+#define SCL5_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
+#define SCL5_SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
+#define SCL5_SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
+//SCL5_SCL_HORZ_FILTER_CONTROL
+#define SCL5_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
+#define SCL5_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCL5_SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L
+#define SCL5_SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+//SCL5_SCL_HORZ_FILTER_SCALE_RATIO
+#define SCL5_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+#define SCL5_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+//SCL5_SCL_HORZ_FILTER_INIT
+#define SCL5_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+#define SCL5_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+#define SCL5_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+#define SCL5_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+//SCL5_SCL_VERT_FILTER_CONTROL
+#define SCL5_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
+#define SCL5_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCL5_SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L
+#define SCL5_SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+//SCL5_SCL_VERT_FILTER_SCALE_RATIO
+#define SCL5_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+#define SCL5_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+//SCL5_SCL_VERT_FILTER_INIT
+#define SCL5_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+#define SCL5_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+#define SCL5_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+#define SCL5_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
+//SCL5_SCL_VERT_FILTER_INIT_BOT
+#define SCL5_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+#define SCL5_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+#define SCL5_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+#define SCL5_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
+//SCL5_SCL_ROUND_OFFSET
+#define SCL5_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
+#define SCL5_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+#define SCL5_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
+#define SCL5_SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
+//SCL5_SCL_UPDATE
+#define SCL5_SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+#define SCL5_SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
+#define SCL5_SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
+#define SCL5_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
+#define SCL5_SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+#define SCL5_SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
+#define SCL5_SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
+#define SCL5_SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
+//SCL5_SCL_F_SHARP_CONTROL
+#define SCL5_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
+#define SCL5_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
+#define SCL5_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
+#define SCL5_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
+#define SCL5_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L
+#define SCL5_SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L
+#define SCL5_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L
+#define SCL5_SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L
+//SCL5_SCL_ALU_CONTROL
+#define SCL5_SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
+#define SCL5_SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
+//SCL5_SCL_COEF_RAM_CONFLICT_STATUS
+#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
+#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
+#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
+#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
+#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
+#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L
+#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L
+#define SCL5_SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
+//SCL5_VIEWPORT_START_SECONDARY
+#define SCL5_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
+#define SCL5_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
+#define SCL5_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
+#define SCL5_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
+//SCL5_VIEWPORT_START
+#define SCL5_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
+#define SCL5_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
+#define SCL5_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
+#define SCL5_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
+//SCL5_VIEWPORT_SIZE
+#define SCL5_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
+#define SCL5_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
+#define SCL5_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003FFFL
+#define SCL5_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3FFF0000L
+//SCL5_EXT_OVERSCAN_LEFT_RIGHT
+#define SCL5_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+#define SCL5_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+#define SCL5_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+#define SCL5_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+//SCL5_EXT_OVERSCAN_TOP_BOTTOM
+#define SCL5_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+#define SCL5_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+#define SCL5_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+#define SCL5_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+//SCL5_SCL_MODE_CHANGE_DET1
+#define SCL5_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
+#define SCL5_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
+#define SCL5_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
+#define SCL5_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
+#define SCL5_SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
+#define SCL5_SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
+//SCL5_SCL_MODE_CHANGE_DET2
+#define SCL5_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
+#define SCL5_SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
+//SCL5_SCL_MODE_CHANGE_DET3
+#define SCL5_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
+#define SCL5_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
+#define SCL5_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
+#define SCL5_SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
+//SCL5_SCL_MODE_CHANGE_MASK
+#define SCL5_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
+#define SCL5_SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_blnd5_dispdec
+//BLND5_BLND_CONTROL
+#define BLND5_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
+#define BLND5_BLND_CONTROL__BLND_MODE__SHIFT 0x8
+#define BLND5_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
+#define BLND5_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
+#define BLND5_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
+#define BLND5_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
+#define BLND5_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
+#define BLND5_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
+#define BLND5_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
+#define BLND5_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
+#define BLND5_BLND_CONTROL__BLND_MODE_MASK 0x00000300L
+#define BLND5_BLND_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
+#define BLND5_BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
+#define BLND5_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
+#define BLND5_BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
+#define BLND5_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
+#define BLND5_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
+#define BLND5_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
+//BLND5_BLND_SM_CONTROL2
+#define BLND5_BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0
+#define BLND5_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
+#define BLND5_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
+#define BLND5_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+#define BLND5_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+#define BLND5_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
+#define BLND5_BLND_SM_CONTROL2__SM_MODE_MASK 0x00000007L
+#define BLND5_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
+#define BLND5_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
+#define BLND5_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+#define BLND5_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+#define BLND5_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
+//BLND5_BLND_CONTROL2
+#define BLND5_BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
+#define BLND5_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
+#define BLND5_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
+#define BLND5_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
+#define BLND5_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
+#define BLND5_BLND_CONTROL2__PTI_ENABLE_MASK 0x00000001L
+#define BLND5_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
+#define BLND5_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
+#define BLND5_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
+#define BLND5_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
+//BLND5_BLND_UPDATE
+#define BLND5_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
+#define BLND5_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
+#define BLND5_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
+#define BLND5_BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
+#define BLND5_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
+#define BLND5_BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
+//BLND5_BLND_UNDERFLOW_INTERRUPT
+#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
+#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
+#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
+#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
+#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
+#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
+#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
+#define BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
+//BLND5_BLND_V_UPDATE_LOCK
+#define BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
+#define BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
+#define BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
+#define BLND5_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
+#define BLND5_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
+#define BLND5_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
+#define BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
+#define BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
+#define BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
+#define BLND5_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
+#define BLND5_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
+#define BLND5_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
+//BLND5_BLND_REG_UPDATE_STATUS
+#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
+#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
+#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
+#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
+#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
+#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
+#define BLND5_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
+#define BLND5_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
+#define BLND5_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
+#define BLND5_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
+#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
+#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
+#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
+#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
+#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
+#define BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
+#define BLND5_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
+#define BLND5_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
+#define BLND5_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
+#define BLND5_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
+
+
+// addressBlock: dce_dc_crtc5_dispdec
+//CRTC5_CRTC_H_BLANK_EARLY_NUM
+#define CRTC5_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
+#define CRTC5_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
+#define CRTC5_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
+#define CRTC5_CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
+//CRTC5_CRTC_H_TOTAL
+#define CRTC5_CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
+#define CRTC5_CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
+//CRTC5_CRTC_H_BLANK_START_END
+#define CRTC5_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
+#define CRTC5_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
+#define CRTC5_CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
+#define CRTC5_CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
+//CRTC5_CRTC_H_SYNC_A
+#define CRTC5_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
+#define CRTC5_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
+#define CRTC5_CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
+#define CRTC5_CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
+//CRTC5_CRTC_H_SYNC_A_CNTL
+#define CRTC5_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
+#define CRTC5_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
+#define CRTC5_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
+#define CRTC5_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
+#define CRTC5_CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
+#define CRTC5_CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
+//CRTC5_CRTC_H_SYNC_B
+#define CRTC5_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
+#define CRTC5_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
+#define CRTC5_CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
+#define CRTC5_CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
+//CRTC5_CRTC_H_SYNC_B_CNTL
+#define CRTC5_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
+#define CRTC5_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
+#define CRTC5_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
+#define CRTC5_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
+#define CRTC5_CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
+#define CRTC5_CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
+//CRTC5_CRTC_VBI_END
+#define CRTC5_CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
+#define CRTC5_CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
+#define CRTC5_CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
+#define CRTC5_CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
+//CRTC5_CRTC_V_TOTAL
+#define CRTC5_CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
+#define CRTC5_CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
+//CRTC5_CRTC_V_TOTAL_MIN
+#define CRTC5_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
+#define CRTC5_CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
+//CRTC5_CRTC_V_TOTAL_MAX
+#define CRTC5_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
+#define CRTC5_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
+#define CRTC5_CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
+#define CRTC5_CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
+//CRTC5_CRTC_V_TOTAL_CONTROL
+#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
+#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
+#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
+#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
+#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
+#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
+#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
+#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
+#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
+#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
+#define CRTC5_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+//CRTC5_CRTC_V_TOTAL_INT_STATUS
+#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+#define CRTC5_CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+//CRTC5_CRTC_VSYNC_NOM_INT_STATUS
+#define CRTC5_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
+#define CRTC5_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+#define CRTC5_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
+#define CRTC5_CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+//CRTC5_CRTC_V_BLANK_START_END
+#define CRTC5_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
+#define CRTC5_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
+#define CRTC5_CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
+#define CRTC5_CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
+//CRTC5_CRTC_V_SYNC_A
+#define CRTC5_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
+#define CRTC5_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
+#define CRTC5_CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
+#define CRTC5_CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
+//CRTC5_CRTC_V_SYNC_A_CNTL
+#define CRTC5_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
+#define CRTC5_CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
+//CRTC5_CRTC_V_SYNC_B
+#define CRTC5_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
+#define CRTC5_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
+#define CRTC5_CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
+#define CRTC5_CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
+//CRTC5_CRTC_V_SYNC_B_CNTL
+#define CRTC5_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
+#define CRTC5_CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
+//CRTC5_CRTC_DTMTEST_CNTL
+#define CRTC5_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
+#define CRTC5_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
+#define CRTC5_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
+#define CRTC5_CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
+//CRTC5_CRTC_DTMTEST_STATUS_POSITION
+#define CRTC5_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
+#define CRTC5_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
+#define CRTC5_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
+#define CRTC5_CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTC5_CRTC_TRIGA_CNTL
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
+#define CRTC5_CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
+//CRTC5_CRTC_TRIGA_MANUAL_TRIG
+#define CRTC5_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
+#define CRTC5_CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+//CRTC5_CRTC_TRIGB_CNTL
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
+#define CRTC5_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
+//CRTC5_CRTC_TRIGB_MANUAL_TRIG
+#define CRTC5_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
+#define CRTC5_CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+//CRTC5_CRTC_FORCE_COUNT_NOW_CNTL
+#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+#define CRTC5_CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+//CRTC5_CRTC_FLOW_CONTROL
+#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
+#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+#define CRTC5_CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+//CRTC5_CRTC_STEREO_FORCE_NEXT_EYE
+#define CRTC5_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+#define CRTC5_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+#define CRTC5_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
+#define CRTC5_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+#define CRTC5_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+#define CRTC5_CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+//CRTC5_CRTC_AVSYNC_COUNTER
+#define CRTC5_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
+#define CRTC5_CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
+//CRTC5_CRTC_CONTROL
+#define CRTC5_CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTC5_CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
+#define CRTC5_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
+#define CRTC5_CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
+#define CRTC5_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
+#define CRTC5_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
+#define CRTC5_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+#define CRTC5_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
+#define CRTC5_CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
+#define CRTC5_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+#define CRTC5_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+#define CRTC5_CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
+#define CRTC5_CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
+#define CRTC5_CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
+#define CRTC5_CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
+#define CRTC5_CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
+#define CRTC5_CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+#define CRTC5_CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+#define CRTC5_CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
+#define CRTC5_CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
+#define CRTC5_CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+#define CRTC5_CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+//CRTC5_CRTC_BLANK_CONTROL
+#define CRTC5_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
+#define CRTC5_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
+#define CRTC5_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
+#define CRTC5_CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
+#define CRTC5_CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
+#define CRTC5_CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
+//CRTC5_CRTC_INTERLACE_CONTROL
+#define CRTC5_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
+#define CRTC5_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+#define CRTC5_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
+#define CRTC5_CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+//CRTC5_CRTC_INTERLACE_STATUS
+#define CRTC5_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+#define CRTC5_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
+#define CRTC5_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+#define CRTC5_CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+//CRTC5_CRTC_FIELD_INDICATION_CONTROL
+#define CRTC5_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
+#define CRTC5_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
+#define CRTC5_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
+#define CRTC5_CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
+//CRTC5_CRTC_PIXEL_DATA_READBACK0
+#define CRTC5_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+#define CRTC5_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+#define CRTC5_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
+#define CRTC5_CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
+//CRTC5_CRTC_PIXEL_DATA_READBACK1
+#define CRTC5_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
+#define CRTC5_CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
+//CRTC5_CRTC_STATUS
+#define CRTC5_CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
+#define CRTC5_CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
+#define CRTC5_CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
+#define CRTC5_CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
+#define CRTC5_CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
+#define CRTC5_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+#define CRTC5_CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
+#define CRTC5_CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
+#define CRTC5_CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
+#define CRTC5_CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L
+#define CRTC5_CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
+#define CRTC5_CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
+#define CRTC5_CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
+#define CRTC5_CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
+#define CRTC5_CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+#define CRTC5_CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L
+#define CRTC5_CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
+#define CRTC5_CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
+//CRTC5_CRTC_STATUS_POSITION
+#define CRTC5_CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
+#define CRTC5_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
+#define CRTC5_CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
+#define CRTC5_CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTC5_CRTC_NOM_VERT_POSITION
+#define CRTC5_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
+#define CRTC5_CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
+//CRTC5_CRTC_STATUS_FRAME_COUNT
+#define CRTC5_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
+#define CRTC5_CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
+//CRTC5_CRTC_STATUS_VF_COUNT
+#define CRTC5_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
+#define CRTC5_CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
+//CRTC5_CRTC_STATUS_HV_COUNT
+#define CRTC5_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
+#define CRTC5_CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
+//CRTC5_CRTC_COUNT_CONTROL
+#define CRTC5_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
+#define CRTC5_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
+#define CRTC5_CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+#define CRTC5_CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+//CRTC5_CRTC_COUNT_RESET
+#define CRTC5_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
+#define CRTC5_CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
+//CRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define CRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+#define CRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+//CRTC5_CRTC_VERT_SYNC_CONTROL
+#define CRTC5_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+#define CRTC5_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+#define CRTC5_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+#define CRTC5_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+#define CRTC5_CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+#define CRTC5_CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+//CRTC5_CRTC_STEREO_STATUS
+#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
+#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
+#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
+#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
+#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
+#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
+#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
+#define CRTC5_CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+//CRTC5_CRTC_STEREO_CONTROL
+#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
+#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+#define CRTC5_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+#define CRTC5_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
+#define CRTC5_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
+#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
+#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
+#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+#define CRTC5_CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+#define CRTC5_CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
+#define CRTC5_CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+#define CRTC5_CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
+//CRTC5_CRTC_SNAPSHOT_STATUS
+#define CRTC5_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
+#define CRTC5_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
+#define CRTC5_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+#define CRTC5_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
+#define CRTC5_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
+#define CRTC5_CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+//CRTC5_CRTC_SNAPSHOT_CONTROL
+#define CRTC5_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+#define CRTC5_CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+//CRTC5_CRTC_SNAPSHOT_POSITION
+#define CRTC5_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+#define CRTC5_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+#define CRTC5_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
+#define CRTC5_CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTC5_CRTC_SNAPSHOT_FRAME
+#define CRTC5_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+#define CRTC5_CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+//CRTC5_CRTC_START_LINE_CONTROL
+#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
+#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
+#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
+#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
+#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
+#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
+#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
+#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
+#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
+#define CRTC5_CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
+//CRTC5_CRTC_INTERRUPT_CONTROL
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+#define CRTC5_CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+//CRTC5_CRTC_UPDATE_LOCK
+#define CRTC5_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
+#define CRTC5_CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
+//CRTC5_CRTC_DOUBLE_BUFFER_CONTROL
+#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
+#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
+#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
+#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
+#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
+#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
+#define CRTC5_CRTC_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
+//CRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE
+#define CRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
+#define CRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
+//CRTC5_CRTC_TEST_PATTERN_CONTROL
+#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
+#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
+#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
+#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
+#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
+#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
+#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
+#define CRTC5_CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
+//CRTC5_CRTC_TEST_PATTERN_PARAMETERS
+#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
+#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
+#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
+#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
+#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
+#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
+#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
+#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
+#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
+#define CRTC5_CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
+//CRTC5_CRTC_TEST_PATTERN_COLOR
+#define CRTC5_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
+#define CRTC5_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
+#define CRTC5_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
+#define CRTC5_CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
+//CRTC5_CRTC_MASTER_UPDATE_LOCK
+#define CRTC5_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
+#define CRTC5_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
+#define CRTC5_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
+#define CRTC5_CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
+#define CRTC5_CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
+#define CRTC5_CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
+//CRTC5_CRTC_MASTER_UPDATE_MODE
+#define CRTC5_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
+#define CRTC5_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
+#define CRTC5_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
+#define CRTC5_CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
+//CRTC5_CRTC_MVP_INBAND_CNTL_INSERT
+#define CRTC5_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
+#define CRTC5_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
+#define CRTC5_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
+#define CRTC5_CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
+//CRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER
+#define CRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
+#define CRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
+//CRTC5_CRTC_MVP_STATUS
+#define CRTC5_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
+#define CRTC5_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
+#define CRTC5_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
+#define CRTC5_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
+#define CRTC5_CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
+#define CRTC5_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
+#define CRTC5_CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
+#define CRTC5_CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
+//CRTC5_CRTC_MASTER_EN
+#define CRTC5_CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTC5_CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
+//CRTC5_CRTC_ALLOW_STOP_OFF_V_CNT
+#define CRTC5_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
+#define CRTC5_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
+#define CRTC5_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
+#define CRTC5_CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
+//CRTC5_CRTC_V_UPDATE_INT_STATUS
+#define CRTC5_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
+#define CRTC5_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
+#define CRTC5_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
+#define CRTC5_CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
+//CRTC5_CRTC_OVERSCAN_COLOR
+#define CRTC5_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
+#define CRTC5_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
+#define CRTC5_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
+#define CRTC5_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
+#define CRTC5_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
+#define CRTC5_CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
+//CRTC5_CRTC_OVERSCAN_COLOR_EXT
+#define CRTC5_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
+#define CRTC5_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
+#define CRTC5_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
+#define CRTC5_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
+#define CRTC5_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
+#define CRTC5_CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
+//CRTC5_CRTC_BLANK_DATA_COLOR
+#define CRTC5_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+#define CRTC5_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+#define CRTC5_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+#define CRTC5_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+#define CRTC5_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+#define CRTC5_CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+//CRTC5_CRTC_BLANK_DATA_COLOR_EXT
+#define CRTC5_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+#define CRTC5_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+#define CRTC5_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+#define CRTC5_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
+#define CRTC5_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
+#define CRTC5_CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
+//CRTC5_CRTC_BLACK_COLOR
+#define CRTC5_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
+#define CRTC5_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
+#define CRTC5_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
+#define CRTC5_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
+#define CRTC5_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+#define CRTC5_CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+//CRTC5_CRTC_BLACK_COLOR_EXT
+#define CRTC5_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+#define CRTC5_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+#define CRTC5_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+#define CRTC5_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
+#define CRTC5_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
+#define CRTC5_CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
+//CRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION
+#define CRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+#define CRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+#define CRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
+#define CRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
+//CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL
+#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+#define CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+//CRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION
+#define CRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+#define CRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
+//CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL
+#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+#define CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+//CRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION
+#define CRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+#define CRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
+//CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL
+#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+#define CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+//CRTC5_CRTC_CRC_CNTL
+#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
+#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
+#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
+#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
+#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
+#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
+#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
+#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
+#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
+#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
+#define CRTC5_CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
+//CRTC5_CRTC_CRC0_WINDOWA_X_CONTROL
+#define CRTC5_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
+#define CRTC5_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
+#define CRTC5_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
+#define CRTC5_CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
+//CRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL
+#define CRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
+#define CRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
+#define CRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
+#define CRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
+//CRTC5_CRTC_CRC0_WINDOWB_X_CONTROL
+#define CRTC5_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
+#define CRTC5_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
+#define CRTC5_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
+#define CRTC5_CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
+//CRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL
+#define CRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
+#define CRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
+#define CRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
+#define CRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
+//CRTC5_CRTC_CRC0_DATA_RG
+#define CRTC5_CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+#define CRTC5_CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+#define CRTC5_CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+#define CRTC5_CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+//CRTC5_CRTC_CRC0_DATA_B
+#define CRTC5_CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+#define CRTC5_CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+//CRTC5_CRTC_CRC1_WINDOWA_X_CONTROL
+#define CRTC5_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
+#define CRTC5_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
+#define CRTC5_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
+#define CRTC5_CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
+//CRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL
+#define CRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
+#define CRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
+#define CRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
+#define CRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
+//CRTC5_CRTC_CRC1_WINDOWB_X_CONTROL
+#define CRTC5_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
+#define CRTC5_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
+#define CRTC5_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
+#define CRTC5_CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
+//CRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL
+#define CRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
+#define CRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
+#define CRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
+#define CRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
+//CRTC5_CRTC_CRC1_DATA_RG
+#define CRTC5_CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+#define CRTC5_CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+#define CRTC5_CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+#define CRTC5_CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+//CRTC5_CRTC_CRC1_DATA_B
+#define CRTC5_CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+#define CRTC5_CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+//CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
+//CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START
+#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
+#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
+#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
+#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
+//CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END
+#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
+#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
+#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
+#define CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
+//CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
+#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
+#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
+#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
+#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
+#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
+#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
+#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
+//CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL
+#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
+#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
+#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
+#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
+#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
+#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
+//CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
+#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
+#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
+#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
+#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
+#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
+#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
+#define CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
+//CRTC5_CRTC_STATIC_SCREEN_CONTROL
+#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
+#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
+#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
+#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
+#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
+#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
+#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
+#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
+#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
+#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
+#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
+#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
+#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
+#define CRTC5_CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
+//CRTC5_CRTC_3D_STRUCTURE_CONTROL
+#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
+#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
+#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
+#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
+#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+#define CRTC5_CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+//CRTC5_CRTC_GSL_VSYNC_GAP
+#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
+#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+#define CRTC5_CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
+//CRTC5_CRTC_GSL_WINDOW
+#define CRTC5_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
+#define CRTC5_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
+#define CRTC5_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
+#define CRTC5_CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
+//CRTC5_CRTC_GSL_CONTROL
+#define CRTC5_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
+#define CRTC5_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
+#define CRTC5_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+#define CRTC5_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
+#define CRTC5_CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
+#define CRTC5_CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+//CRTC5_CRTC_RANGE_TIMING_INT_STATUS
+#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
+#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
+#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
+#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
+#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
+#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
+#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
+#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
+#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
+#define CRTC5_CRTC_RANGE_TIMING_INT_STATUS__CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
+//CRTC5_CRTC_DRR_CONTROL
+#define CRTC5_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY__SHIFT 0x0
+#define CRTC5_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0xe
+#define CRTC5_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS__SHIFT 0x1c
+#define CRTC5_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE__SHIFT 0x1d
+#define CRTC5_CRTC_DRR_CONTROL__CRTC_XDMA_PREFETCH_DELAY_MASK 0x00003FFFL
+#define CRTC5_CRTC_DRR_CONTROL__CRTC_V_TOTAL_LAST_USED_BY_DRR_MASK 0x0FFFC000L
+#define CRTC5_CRTC_DRR_CONTROL__CRTC_SET_V_TOTAL_MIN_AUTO_DIS_MASK 0x10000000L
+#define CRTC5_CRTC_DRR_CONTROL__CRTC_DRR_MODE_DBUF_UPDATE_MODE_MASK 0x60000000L
+
+
+// addressBlock: dce_dc_fmt5_dispdec
+//FMT5_FMT_CLAMP_COMPONENT_R
+#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
+#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
+#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
+#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
+//FMT5_FMT_CLAMP_COMPONENT_G
+#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
+#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
+#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
+#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
+//FMT5_FMT_CLAMP_COMPONENT_B
+#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
+#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
+#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
+#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
+//FMT5_FMT_DYNAMIC_EXP_CNTL
+#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
+#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
+#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
+#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
+//FMT5_FMT_CONTROL
+#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
+#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
+#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
+#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
+#define FMT5_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
+#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
+#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
+#define FMT5_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
+#define FMT5_FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
+#define FMT5_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED__SHIFT 0x1e
+#define FMT5_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR__SHIFT 0x1f
+#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
+#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L
+#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
+#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
+#define FMT5_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
+#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
+#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
+#define FMT5_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
+#define FMT5_FMT_CONTROL__FMT_SRC_SELECT_MASK 0x07000000L
+#define FMT5_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_MASK 0x40000000L
+#define FMT5_FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR_MASK 0x80000000L
+//FMT5_FMT_BIT_DEPTH_CONTROL
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
+//FMT5_FMT_DITHER_RAND_R_SEED
+#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
+#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
+#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
+#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
+//FMT5_FMT_DITHER_RAND_G_SEED
+#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
+#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
+#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
+#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
+//FMT5_FMT_DITHER_RAND_B_SEED
+#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
+#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
+#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
+#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
+//FMT5_FMT_CLAMP_CNTL
+#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
+#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
+#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
+#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
+//FMT5_FMT_CRC_CNTL
+#define FMT5_FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
+#define FMT5_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
+#define FMT5_FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
+#define FMT5_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5
+#define FMT5_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6
+#define FMT5_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
+#define FMT5_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9
+#define FMT5_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
+#define FMT5_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+#define FMT5_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
+#define FMT5_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
+#define FMT5_FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L
+#define FMT5_FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x00000002L
+#define FMT5_FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L
+#define FMT5_FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x00000020L
+#define FMT5_FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x00000040L
+#define FMT5_FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x00000100L
+#define FMT5_FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x00000200L
+#define FMT5_FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define FMT5_FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+#define FMT5_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L
+#define FMT5_FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L
+//FMT5_FMT_CRC_SIG_RED_GREEN_MASK
+#define FMT5_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
+#define FMT5_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
+#define FMT5_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
+#define FMT5_FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
+//FMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK
+#define FMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
+#define FMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
+#define FMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
+#define FMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
+//FMT5_FMT_CRC_SIG_RED_GREEN
+#define FMT5_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
+#define FMT5_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
+#define FMT5_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000FFFFL
+#define FMT5_FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xFFFF0000L
+//FMT5_FMT_CRC_SIG_BLUE_CONTROL
+#define FMT5_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
+#define FMT5_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
+#define FMT5_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000FFFFL
+#define FMT5_FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xFFFF0000L
+//FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
+#define FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
+//FMT5_FMT_420_HBLANK_EARLY_START
+#define FMT5_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START__SHIFT 0x0
+#define FMT5_FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START_MASK 0x00000FFFL
+
+
+// addressBlock: dce_dc_unp0_dispdec
+//UNP0_UNP_GRPH_ENABLE
+#define UNP0_UNP_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
+#define UNP0_UNP_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
+//UNP0_UNP_GRPH_CONTROL
+#define UNP0_UNP_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
+#define UNP0_UNP_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2
+#define UNP0_UNP_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
+#define UNP0_UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L__SHIFT 0x6
+#define UNP0_UNP_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
+#define UNP0_UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L__SHIFT 0xb
+#define UNP0_UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L__SHIFT 0xd
+#define UNP0_UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+#define UNP0_UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+#define UNP0_UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L__SHIFT 0x12
+#define UNP0_UNP_GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14
+#define UNP0_UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18
+#define UNP0_UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L__SHIFT 0x1d
+#define UNP0_UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
+#define UNP0_UNP_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
+#define UNP0_UNP_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x0000000CL
+#define UNP0_UNP_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
+#define UNP0_UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L_MASK 0x000000C0L
+#define UNP0_UNP_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
+#define UNP0_UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L_MASK 0x00001800L
+#define UNP0_UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L_MASK 0x0000E000L
+#define UNP0_UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
+#define UNP0_UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
+#define UNP0_UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L_MASK 0x000C0000L
+#define UNP0_UNP_GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0x00F00000L
+#define UNP0_UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1F000000L
+#define UNP0_UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L_MASK 0x60000000L
+#define UNP0_UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
+//UNP0_UNP_GRPH_CONTROL_C
+#define UNP0_UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C__SHIFT 0x6
+#define UNP0_UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C__SHIFT 0xb
+#define UNP0_UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C__SHIFT 0xd
+#define UNP0_UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C__SHIFT 0x12
+#define UNP0_UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C__SHIFT 0x1d
+#define UNP0_UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C_MASK 0x000000C0L
+#define UNP0_UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C_MASK 0x00001800L
+#define UNP0_UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C_MASK 0x0000E000L
+#define UNP0_UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C_MASK 0x000C0000L
+#define UNP0_UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C_MASK 0x60000000L
+//UNP0_UNP_GRPH_CONTROL_EXP
+#define UNP0_UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT__SHIFT 0x0
+#define UNP0_UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT_MASK 0x00000007L
+//UNP0_UNP_GRPH_SWAP_CNTL
+#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
+#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
+#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
+#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
+#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
+#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
+#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
+#define UNP0_UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
+//UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L
+#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT 0x8
+#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
+//UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C
+#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x8
+#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
+//UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L
+#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
+//UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
+//UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L
+#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
+#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
+//UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C
+#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
+#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
+//UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L
+#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
+//UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C
+#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
+//UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L
+#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L__SHIFT 0x8
+#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
+//UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C
+#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x8
+#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
+//UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L
+#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
+//UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
+//UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L
+#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
+#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
+//UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C
+#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
+#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
+//UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L
+#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
+//UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C
+#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
+//UNP0_UNP_GRPH_PITCH_L
+#define UNP0_UNP_GRPH_PITCH_L__GRPH_PITCH_L__SHIFT 0x0
+#define UNP0_UNP_GRPH_PITCH_L__GRPH_PITCH_L_MASK 0x00007FFFL
+//UNP0_UNP_GRPH_PITCH_C
+#define UNP0_UNP_GRPH_PITCH_C__GRPH_PITCH_C__SHIFT 0x0
+#define UNP0_UNP_GRPH_PITCH_C__GRPH_PITCH_C_MASK 0x00007FFFL
+//UNP0_UNP_GRPH_SURFACE_OFFSET_X_L
+#define UNP0_UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L__SHIFT 0x0
+#define UNP0_UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L_MASK 0x00003FFFL
+//UNP0_UNP_GRPH_SURFACE_OFFSET_X_C
+#define UNP0_UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C__SHIFT 0x0
+#define UNP0_UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C_MASK 0x00003FFFL
+//UNP0_UNP_GRPH_SURFACE_OFFSET_Y_L
+#define UNP0_UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L__SHIFT 0x0
+#define UNP0_UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L_MASK 0x00003FFFL
+//UNP0_UNP_GRPH_SURFACE_OFFSET_Y_C
+#define UNP0_UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C__SHIFT 0x0
+#define UNP0_UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C_MASK 0x00003FFFL
+//UNP0_UNP_GRPH_X_START_L
+#define UNP0_UNP_GRPH_X_START_L__GRPH_X_START_L__SHIFT 0x0
+#define UNP0_UNP_GRPH_X_START_L__GRPH_X_START_L_MASK 0x00003FFFL
+//UNP0_UNP_GRPH_X_START_C
+#define UNP0_UNP_GRPH_X_START_C__GRPH_X_START_C__SHIFT 0x0
+#define UNP0_UNP_GRPH_X_START_C__GRPH_X_START_C_MASK 0x00003FFFL
+//UNP0_UNP_GRPH_Y_START_L
+#define UNP0_UNP_GRPH_Y_START_L__GRPH_Y_START_L__SHIFT 0x0
+#define UNP0_UNP_GRPH_Y_START_L__GRPH_Y_START_L_MASK 0x00003FFFL
+//UNP0_UNP_GRPH_Y_START_C
+#define UNP0_UNP_GRPH_Y_START_C__GRPH_Y_START_C__SHIFT 0x0
+#define UNP0_UNP_GRPH_Y_START_C__GRPH_Y_START_C_MASK 0x00003FFFL
+//UNP0_UNP_GRPH_X_END_L
+#define UNP0_UNP_GRPH_X_END_L__GRPH_X_END_L__SHIFT 0x0
+#define UNP0_UNP_GRPH_X_END_L__GRPH_X_END_L_MASK 0x00007FFFL
+//UNP0_UNP_GRPH_X_END_C
+#define UNP0_UNP_GRPH_X_END_C__GRPH_X_END_C__SHIFT 0x0
+#define UNP0_UNP_GRPH_X_END_C__GRPH_X_END_C_MASK 0x00007FFFL
+//UNP0_UNP_GRPH_Y_END_L
+#define UNP0_UNP_GRPH_Y_END_L__GRPH_Y_END_L__SHIFT 0x0
+#define UNP0_UNP_GRPH_Y_END_L__GRPH_Y_END_L_MASK 0x00007FFFL
+//UNP0_UNP_GRPH_Y_END_C
+#define UNP0_UNP_GRPH_Y_END_C__GRPH_Y_END_C__SHIFT 0x0
+#define UNP0_UNP_GRPH_Y_END_C__GRPH_Y_END_C_MASK 0x00007FFFL
+//UNP0_UNP_GRPH_UPDATE
+#define UNP0_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
+#define UNP0_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
+#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
+#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
+#define UNP0_UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
+#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
+#define UNP0_UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
+#define UNP0_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
+#define UNP0_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
+#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
+#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
+#define UNP0_UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
+#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
+#define UNP0_UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+#define UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
+//UNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT
+#define UNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L__SHIFT 0x0
+#define UNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C__SHIFT 0x8
+#define UNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L_MASK 0x000000FFL
+#define UNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C_MASK 0x0000FF00L
+//UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L
+#define UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L__SHIFT 0x8
+#define UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L_MASK 0xFFFFFF00L
+//UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C
+#define UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C__SHIFT 0x8
+#define UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C_MASK 0xFFFFFF00L
+//UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L
+#define UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__SHIFT 0x0
+#define UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_MASK 0x000000FFL
+//UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C
+#define UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__SHIFT 0x0
+#define UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_MASK 0x000000FFL
+//UNP0_UNP_DVMM_PTE_CONTROL
+#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
+#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
+#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
+#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
+#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
+#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
+#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
+#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
+#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
+#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
+#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
+#define UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
+//UNP0_UNP_DVMM_PTE_CONTROL_C
+#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C__SHIFT 0x0
+#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C__SHIFT 0x1
+#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C__SHIFT 0x5
+#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C__SHIFT 0x9
+#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C__SHIFT 0x14
+#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C__SHIFT 0x15
+#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C_MASK 0x00000001L
+#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C_MASK 0x0000001EL
+#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C_MASK 0x000001E0L
+#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C_MASK 0x0007FE00L
+#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C_MASK 0x00100000L
+#define UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C_MASK 0x00200000L
+//UNP0_UNP_DVMM_PTE_ARB_CONTROL
+#define UNP0_UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
+#define UNP0_UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
+#define UNP0_UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
+#define UNP0_UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
+//UNP0_UNP_DVMM_PTE_ARB_CONTROL_C
+#define UNP0_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C__SHIFT 0x0
+#define UNP0_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C__SHIFT 0x8
+#define UNP0_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C_MASK 0x0000003FL
+#define UNP0_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C_MASK 0x0000FF00L
+//UNP0_UNP_GRPH_INTERRUPT_STATUS
+#define UNP0_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
+#define UNP0_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
+#define UNP0_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
+#define UNP0_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
+//UNP0_UNP_GRPH_INTERRUPT_CONTROL
+#define UNP0_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
+#define UNP0_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
+#define UNP0_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
+#define UNP0_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
+//UNP0_UNP_GRPH_STEREOSYNC_FLIP
+#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
+#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x4
+#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN__SHIFT 0x8
+#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE__SHIFT 0xc
+#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING__SHIFT 0x12
+#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING__SHIFT 0x13
+#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
+#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000030L
+#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN_MASK 0x00000100L
+#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE_MASK 0x00003000L
+#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
+#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
+#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING_MASK 0x00040000L
+#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING_MASK 0x00080000L
+#define UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
+//UNP0_UNP_FLIP_CONTROL
+#define UNP0_UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x0
+#define UNP0_UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000001L
+//UNP0_UNP_CRC_CONTROL
+#define UNP0_UNP_CRC_CONTROL__UNP_CRC_ENABLE__SHIFT 0x0
+#define UNP0_UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL__SHIFT 0x2
+#define UNP0_UNP_CRC_CONTROL__UNP_CRC_LINE_SEL__SHIFT 0x8
+#define UNP0_UNP_CRC_CONTROL__UNP_CRC_ENABLE_MASK 0x00000001L
+#define UNP0_UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL_MASK 0x0000001CL
+#define UNP0_UNP_CRC_CONTROL__UNP_CRC_LINE_SEL_MASK 0x00000300L
+//UNP0_UNP_CRC_MASK
+#define UNP0_UNP_CRC_MASK__UNP_CRC_MASK__SHIFT 0x0
+#define UNP0_UNP_CRC_MASK__UNP_CRC_MASK_MASK 0xFFFFFFFFL
+//UNP0_UNP_CRC_CURRENT
+#define UNP0_UNP_CRC_CURRENT__UNP_CRC_CURRENT__SHIFT 0x0
+#define UNP0_UNP_CRC_CURRENT__UNP_CRC_CURRENT_MASK 0xFFFFFFFFL
+//UNP0_UNP_CRC_LAST
+#define UNP0_UNP_CRC_LAST__UNP_CRC_LAST__SHIFT 0x0
+#define UNP0_UNP_CRC_LAST__UNP_CRC_LAST_MASK 0xFFFFFFFFL
+//UNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK
+#define UNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK__SHIFT 0x4
+#define UNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK_MASK 0x000001F0L
+//UNP0_UNP_HW_ROTATION
+#define UNP0_UNP_HW_ROTATION__ROTATION_ANGLE__SHIFT 0x0
+#define UNP0_UNP_HW_ROTATION__PIXEL_DROP__SHIFT 0x4
+#define UNP0_UNP_HW_ROTATION__BUFFER_MODE__SHIFT 0x8
+#define UNP0_UNP_HW_ROTATION__ROTATION_ANGLE_MASK 0x00000007L
+#define UNP0_UNP_HW_ROTATION__PIXEL_DROP_MASK 0x00000010L
+#define UNP0_UNP_HW_ROTATION__BUFFER_MODE_MASK 0x00000100L
+
+
+// addressBlock: dce_dc_lbv0_dispdec
+//LBV0_LBV_DATA_FORMAT
+#define LBV0_LBV_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
+#define LBV0_LBV_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
+#define LBV0_LBV_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
+#define LBV0_LBV_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
+#define LBV0_LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
+#define LBV0_LBV_DATA_FORMAT__DITHER_EN__SHIFT 0x6
+#define LBV0_LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN__SHIFT 0x7
+#define LBV0_LBV_DATA_FORMAT__PREFETCH__SHIFT 0xc
+#define LBV0_LBV_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
+#define LBV0_LBV_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
+#define LBV0_LBV_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
+#define LBV0_LBV_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
+#define LBV0_LBV_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
+#define LBV0_LBV_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
+#define LBV0_LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
+#define LBV0_LBV_DATA_FORMAT__DITHER_EN_MASK 0x00000040L
+#define LBV0_LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN_MASK 0x00000080L
+#define LBV0_LBV_DATA_FORMAT__PREFETCH_MASK 0x00001000L
+#define LBV0_LBV_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
+#define LBV0_LBV_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
+//LBV0_LBV_MEMORY_CTRL
+#define LBV0_LBV_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
+#define LBV0_LBV_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+#define LBV0_LBV_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
+#define LBV0_LBV_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00000FFFL
+#define LBV0_LBV_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
+#define LBV0_LBV_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
+//LBV0_LBV_MEMORY_SIZE_STATUS
+#define LBV0_LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
+#define LBV0_LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00000FFFL
+//LBV0_LBV_DESKTOP_HEIGHT
+#define LBV0_LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
+#define LBV0_LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
+//LBV0_LBV_VLINE_START_END
+#define LBV0_LBV_VLINE_START_END__VLINE_START__SHIFT 0x0
+#define LBV0_LBV_VLINE_START_END__VLINE_END__SHIFT 0x10
+#define LBV0_LBV_VLINE_START_END__VLINE_INV__SHIFT 0x1f
+#define LBV0_LBV_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
+#define LBV0_LBV_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
+#define LBV0_LBV_VLINE_START_END__VLINE_INV_MASK 0x80000000L
+//LBV0_LBV_VLINE2_START_END
+#define LBV0_LBV_VLINE2_START_END__VLINE2_START__SHIFT 0x0
+#define LBV0_LBV_VLINE2_START_END__VLINE2_END__SHIFT 0x10
+#define LBV0_LBV_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
+#define LBV0_LBV_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
+#define LBV0_LBV_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
+#define LBV0_LBV_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
+//LBV0_LBV_V_COUNTER
+#define LBV0_LBV_V_COUNTER__V_COUNTER__SHIFT 0x0
+#define LBV0_LBV_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
+//LBV0_LBV_SNAPSHOT_V_COUNTER
+#define LBV0_LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
+#define LBV0_LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
+//LBV0_LBV_V_COUNTER_CHROMA
+#define LBV0_LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA__SHIFT 0x0
+#define LBV0_LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA_MASK 0x00007FFFL
+//LBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA
+#define LBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA__SHIFT 0x0
+#define LBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA_MASK 0x00007FFFL
+//LBV0_LBV_INTERRUPT_MASK
+#define LBV0_LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
+#define LBV0_LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
+#define LBV0_LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
+#define LBV0_LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
+#define LBV0_LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
+#define LBV0_LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
+//LBV0_LBV_VLINE_STATUS
+#define LBV0_LBV_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
+#define LBV0_LBV_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
+#define LBV0_LBV_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
+#define LBV0_LBV_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
+#define LBV0_LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
+#define LBV0_LBV_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
+#define LBV0_LBV_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
+#define LBV0_LBV_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
+#define LBV0_LBV_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
+#define LBV0_LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
+//LBV0_LBV_VLINE2_STATUS
+#define LBV0_LBV_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
+#define LBV0_LBV_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
+#define LBV0_LBV_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
+#define LBV0_LBV_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
+#define LBV0_LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
+#define LBV0_LBV_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
+#define LBV0_LBV_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
+#define LBV0_LBV_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
+#define LBV0_LBV_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
+#define LBV0_LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
+//LBV0_LBV_VBLANK_STATUS
+#define LBV0_LBV_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
+#define LBV0_LBV_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
+#define LBV0_LBV_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
+#define LBV0_LBV_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
+#define LBV0_LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
+#define LBV0_LBV_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
+#define LBV0_LBV_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
+#define LBV0_LBV_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
+#define LBV0_LBV_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
+#define LBV0_LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
+//LBV0_LBV_SYNC_RESET_SEL
+#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
+#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
+#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
+#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
+#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
+#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
+#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
+#define LBV0_LBV_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
+//LBV0_LBV_BLACK_KEYER_R_CR
+#define LBV0_LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
+#define LBV0_LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
+//LBV0_LBV_BLACK_KEYER_G_Y
+#define LBV0_LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
+#define LBV0_LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
+//LBV0_LBV_BLACK_KEYER_B_CB
+#define LBV0_LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
+#define LBV0_LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
+//LBV0_LBV_KEYER_COLOR_CTRL
+#define LBV0_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
+#define LBV0_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
+#define LBV0_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
+#define LBV0_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
+//LBV0_LBV_KEYER_COLOR_R_CR
+#define LBV0_LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
+#define LBV0_LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
+//LBV0_LBV_KEYER_COLOR_G_Y
+#define LBV0_LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
+#define LBV0_LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
+//LBV0_LBV_KEYER_COLOR_B_CB
+#define LBV0_LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
+#define LBV0_LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
+//LBV0_LBV_KEYER_COLOR_REP_R_CR
+#define LBV0_LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
+#define LBV0_LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
+//LBV0_LBV_KEYER_COLOR_REP_G_Y
+#define LBV0_LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
+#define LBV0_LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
+//LBV0_LBV_KEYER_COLOR_REP_B_CB
+#define LBV0_LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
+#define LBV0_LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
+//LBV0_LBV_BUFFER_LEVEL_STATUS
+#define LBV0_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
+#define LBV0_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
+#define LBV0_LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
+#define LBV0_LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
+#define LBV0_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
+#define LBV0_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
+#define LBV0_LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
+#define LBV0_LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
+//LBV0_LBV_BUFFER_URGENCY_CTRL
+#define LBV0_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
+#define LBV0_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
+#define LBV0_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
+#define LBV0_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
+//LBV0_LBV_BUFFER_URGENCY_STATUS
+#define LBV0_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
+#define LBV0_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
+#define LBV0_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
+#define LBV0_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
+//LBV0_LBV_BUFFER_STATUS
+#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
+#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
+#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
+#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
+#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
+#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
+#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
+#define LBV0_LBV_BUFFER_STATUS__LB_ENABLE_HIGH_THROUGHPUT__SHIFT 0x19
+#define LBV0_LBV_BUFFER_STATUS__LB_HIGH_THROUGHPUT_CNTL__SHIFT 0x1a
+#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
+#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
+#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
+#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
+#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
+#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
+#define LBV0_LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
+#define LBV0_LBV_BUFFER_STATUS__LB_ENABLE_HIGH_THROUGHPUT_MASK 0x02000000L
+#define LBV0_LBV_BUFFER_STATUS__LB_HIGH_THROUGHPUT_CNTL_MASK 0x1C000000L
+//LBV0_LBV_NO_OUTSTANDING_REQ_STATUS
+#define LBV0_LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
+#define LBV0_LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_sclv0_dispdec
+//SCLV0_SCLV_COEF_RAM_SELECT
+#define SCLV0_SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define SCLV0_SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
+#define SCLV0_SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
+#define SCLV0_SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x00000003L
+#define SCLV0_SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00007F00L
+#define SCLV0_SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00030000L
+//SCLV0_SCLV_COEF_RAM_TAP_DATA
+#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+#define SCLV0_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+//SCLV0_SCLV_MODE
+#define SCLV0_SCLV_MODE__SCL_MODE__SHIFT 0x0
+#define SCLV0_SCLV_MODE__SCL_MODE_C__SHIFT 0x2
+#define SCLV0_SCLV_MODE__SCL_PSCL_EN__SHIFT 0x4
+#define SCLV0_SCLV_MODE__SCL_PSCL_EN_C__SHIFT 0x5
+#define SCLV0_SCLV_MODE__SCL_INTERLACE_SOURCE__SHIFT 0x8
+#define SCLV0_SCLV_MODE__SCL_MODE_MASK 0x00000003L
+#define SCLV0_SCLV_MODE__SCL_MODE_C_MASK 0x0000000CL
+#define SCLV0_SCLV_MODE__SCL_PSCL_EN_MASK 0x00000010L
+#define SCLV0_SCLV_MODE__SCL_PSCL_EN_C_MASK 0x00000020L
+#define SCLV0_SCLV_MODE__SCL_INTERLACE_SOURCE_MASK 0x00000300L
+//SCLV0_SCLV_TAP_CONTROL
+#define SCLV0_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
+#define SCLV0_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x4
+#define SCLV0_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C__SHIFT 0x8
+#define SCLV0_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C__SHIFT 0xc
+#define SCLV0_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
+#define SCLV0_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000070L
+#define SCLV0_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C_MASK 0x00000700L
+#define SCLV0_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C_MASK 0x00007000L
+//SCLV0_SCLV_CONTROL
+#define SCLV0_SCLV_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+#define SCLV0_SCLV_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
+#define SCLV0_SCLV_CONTROL__SCL_TOTAL_PHASE__SHIFT 0x8
+#define SCLV0_SCLV_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+#define SCLV0_SCLV_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
+#define SCLV0_SCLV_CONTROL__SCL_TOTAL_PHASE_MASK 0x00000100L
+//SCLV0_SCLV_MANUAL_REPLICATE_CONTROL
+#define SCLV0_SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+#define SCLV0_SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+#define SCLV0_SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+#define SCLV0_SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+//SCLV0_SCLV_AUTOMATIC_MODE_CONTROL
+#define SCLV0_SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
+#define SCLV0_SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
+#define SCLV0_SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
+#define SCLV0_SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
+//SCLV0_SCLV_HORZ_FILTER_CONTROL
+#define SCLV0_SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCLV0_SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+//SCLV0_SCLV_HORZ_FILTER_SCALE_RATIO
+#define SCLV0_SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+#define SCLV0_SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+//SCLV0_SCLV_HORZ_FILTER_INIT
+#define SCLV0_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+#define SCLV0_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+#define SCLV0_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+#define SCLV0_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+//SCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C
+#define SCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0
+#define SCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL
+//SCLV0_SCLV_HORZ_FILTER_INIT_C
+#define SCLV0_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0
+#define SCLV0_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18
+#define SCLV0_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL
+#define SCLV0_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L
+//SCLV0_SCLV_VERT_FILTER_CONTROL
+#define SCLV0_SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCLV0_SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+//SCLV0_SCLV_VERT_FILTER_SCALE_RATIO
+#define SCLV0_SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+#define SCLV0_SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+//SCLV0_SCLV_VERT_FILTER_INIT
+#define SCLV0_SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+#define SCLV0_SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+#define SCLV0_SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+#define SCLV0_SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
+//SCLV0_SCLV_VERT_FILTER_INIT_BOT
+#define SCLV0_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+#define SCLV0_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+#define SCLV0_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+#define SCLV0_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
+//SCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C
+#define SCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0
+#define SCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL
+//SCLV0_SCLV_VERT_FILTER_INIT_C
+#define SCLV0_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0
+#define SCLV0_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18
+#define SCLV0_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL
+#define SCLV0_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x07000000L
+//SCLV0_SCLV_VERT_FILTER_INIT_BOT_C
+#define SCLV0_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0
+#define SCLV0_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18
+#define SCLV0_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL
+#define SCLV0_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x07000000L
+//SCLV0_SCLV_ROUND_OFFSET
+#define SCLV0_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
+#define SCLV0_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+#define SCLV0_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
+#define SCLV0_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
+//SCLV0_SCLV_UPDATE
+#define SCLV0_SCLV_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+#define SCLV0_SCLV_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
+#define SCLV0_SCLV_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
+#define SCLV0_SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
+#define SCLV0_SCLV_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+#define SCLV0_SCLV_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
+#define SCLV0_SCLV_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
+#define SCLV0_SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
+//SCLV0_SCLV_ALU_CONTROL
+#define SCLV0_SCLV_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
+#define SCLV0_SCLV_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
+//SCLV0_SCLV_VIEWPORT_START
+#define SCLV0_SCLV_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
+#define SCLV0_SCLV_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
+#define SCLV0_SCLV_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
+#define SCLV0_SCLV_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
+//SCLV0_SCLV_VIEWPORT_START_SECONDARY
+#define SCLV0_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
+#define SCLV0_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
+#define SCLV0_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
+#define SCLV0_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
+//SCLV0_SCLV_VIEWPORT_SIZE
+#define SCLV0_SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
+#define SCLV0_SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
+#define SCLV0_SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00001FFFL
+#define SCLV0_SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x1FFF0000L
+//SCLV0_SCLV_VIEWPORT_START_C
+#define SCLV0_SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C__SHIFT 0x0
+#define SCLV0_SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C__SHIFT 0x10
+#define SCLV0_SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C_MASK 0x00003FFFL
+#define SCLV0_SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C_MASK 0x3FFF0000L
+//SCLV0_SCLV_VIEWPORT_START_SECONDARY_C
+#define SCLV0_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C__SHIFT 0x0
+#define SCLV0_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C__SHIFT 0x10
+#define SCLV0_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C_MASK 0x00003FFFL
+#define SCLV0_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C_MASK 0x3FFF0000L
+//SCLV0_SCLV_VIEWPORT_SIZE_C
+#define SCLV0_SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C__SHIFT 0x0
+#define SCLV0_SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C__SHIFT 0x10
+#define SCLV0_SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C_MASK 0x00001FFFL
+#define SCLV0_SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C_MASK 0x1FFF0000L
+//SCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT
+#define SCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+#define SCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+#define SCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+#define SCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+//SCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM
+#define SCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+#define SCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+#define SCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+#define SCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+//SCLV0_SCLV_MODE_CHANGE_DET1
+#define SCLV0_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
+#define SCLV0_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
+#define SCLV0_SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
+#define SCLV0_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
+#define SCLV0_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
+#define SCLV0_SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
+//SCLV0_SCLV_MODE_CHANGE_DET2
+#define SCLV0_SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
+#define SCLV0_SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
+//SCLV0_SCLV_MODE_CHANGE_DET3
+#define SCLV0_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
+#define SCLV0_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
+#define SCLV0_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
+#define SCLV0_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
+//SCLV0_SCLV_MODE_CHANGE_MASK
+#define SCLV0_SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
+#define SCLV0_SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
+//SCLV0_SCLV_HORZ_FILTER_INIT_BOT
+#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT__SHIFT 0x0
+#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT__SHIFT 0x18
+#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT_MASK 0x0F000000L
+//SCLV0_SCLV_HORZ_FILTER_INIT_BOT_C
+#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C__SHIFT 0x0
+#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C__SHIFT 0x18
+#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL
+#define SCLV0_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C_MASK 0x0F000000L
+
+
+// addressBlock: dce_dc_col_man0_dispdec
+//COL_MAN0_COL_MAN_UPDATE
+#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING__SHIFT 0x0
+#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN__SHIFT 0x1
+#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK__SHIFT 0x10
+#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING_MASK 0x00000001L
+#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN_MASK 0x00000002L
+#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK_MASK 0x00010000L
+#define COL_MAN0_COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+//COL_MAN0_COL_MAN_INPUT_CSC_CONTROL
+#define COL_MAN0_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE__SHIFT 0x0
+#define COL_MAN0_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE__SHIFT 0x8
+#define COL_MAN0_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE__SHIFT 0x10
+#define COL_MAN0_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE_MASK 0x00000003L
+#define COL_MAN0_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE_MASK 0x00000300L
+#define COL_MAN0_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE_MASK 0x00010000L
+//COL_MAN0_INPUT_CSC_C11_C12_A
+#define COL_MAN0_INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A__SHIFT 0x0
+#define COL_MAN0_INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A__SHIFT 0x10
+#define COL_MAN0_INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A_MASK 0x0000FFFFL
+#define COL_MAN0_INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A_MASK 0xFFFF0000L
+//COL_MAN0_INPUT_CSC_C13_C14_A
+#define COL_MAN0_INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A__SHIFT 0x0
+#define COL_MAN0_INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A__SHIFT 0x10
+#define COL_MAN0_INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A_MASK 0x0000FFFFL
+#define COL_MAN0_INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A_MASK 0xFFFF0000L
+//COL_MAN0_INPUT_CSC_C21_C22_A
+#define COL_MAN0_INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A__SHIFT 0x0
+#define COL_MAN0_INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A__SHIFT 0x10
+#define COL_MAN0_INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A_MASK 0x0000FFFFL
+#define COL_MAN0_INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A_MASK 0xFFFF0000L
+//COL_MAN0_INPUT_CSC_C23_C24_A
+#define COL_MAN0_INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A__SHIFT 0x0
+#define COL_MAN0_INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A__SHIFT 0x10
+#define COL_MAN0_INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A_MASK 0x0000FFFFL
+#define COL_MAN0_INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A_MASK 0xFFFF0000L
+//COL_MAN0_INPUT_CSC_C31_C32_A
+#define COL_MAN0_INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A__SHIFT 0x0
+#define COL_MAN0_INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A__SHIFT 0x10
+#define COL_MAN0_INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A_MASK 0x0000FFFFL
+#define COL_MAN0_INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A_MASK 0xFFFF0000L
+//COL_MAN0_INPUT_CSC_C33_C34_A
+#define COL_MAN0_INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A__SHIFT 0x0
+#define COL_MAN0_INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A__SHIFT 0x10
+#define COL_MAN0_INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A_MASK 0x0000FFFFL
+#define COL_MAN0_INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A_MASK 0xFFFF0000L
+//COL_MAN0_INPUT_CSC_C11_C12_B
+#define COL_MAN0_INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B__SHIFT 0x0
+#define COL_MAN0_INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B__SHIFT 0x10
+#define COL_MAN0_INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B_MASK 0x0000FFFFL
+#define COL_MAN0_INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B_MASK 0xFFFF0000L
+//COL_MAN0_INPUT_CSC_C13_C14_B
+#define COL_MAN0_INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B__SHIFT 0x0
+#define COL_MAN0_INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B__SHIFT 0x10
+#define COL_MAN0_INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B_MASK 0x0000FFFFL
+#define COL_MAN0_INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B_MASK 0xFFFF0000L
+//COL_MAN0_INPUT_CSC_C21_C22_B
+#define COL_MAN0_INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B__SHIFT 0x0
+#define COL_MAN0_INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B__SHIFT 0x10
+#define COL_MAN0_INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B_MASK 0x0000FFFFL
+#define COL_MAN0_INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B_MASK 0xFFFF0000L
+//COL_MAN0_INPUT_CSC_C23_C24_B
+#define COL_MAN0_INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B__SHIFT 0x0
+#define COL_MAN0_INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B__SHIFT 0x10
+#define COL_MAN0_INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B_MASK 0x0000FFFFL
+#define COL_MAN0_INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B_MASK 0xFFFF0000L
+//COL_MAN0_INPUT_CSC_C31_C32_B
+#define COL_MAN0_INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B__SHIFT 0x0
+#define COL_MAN0_INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B__SHIFT 0x10
+#define COL_MAN0_INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B_MASK 0x0000FFFFL
+#define COL_MAN0_INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B_MASK 0xFFFF0000L
+//COL_MAN0_INPUT_CSC_C33_C34_B
+#define COL_MAN0_INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B__SHIFT 0x0
+#define COL_MAN0_INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B__SHIFT 0x10
+#define COL_MAN0_INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B_MASK 0x0000FFFFL
+#define COL_MAN0_INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B_MASK 0xFFFF0000L
+//COL_MAN0_PRESCALE_CONTROL
+#define COL_MAN0_PRESCALE_CONTROL__PRESCALE_MODE__SHIFT 0x0
+#define COL_MAN0_PRESCALE_CONTROL__PRESCALE_MODE_MASK 0x00000003L
+//COL_MAN0_PRESCALE_VALUES_R
+#define COL_MAN0_PRESCALE_VALUES_R__PRESCALE_BIAS_R__SHIFT 0x0
+#define COL_MAN0_PRESCALE_VALUES_R__PRESCALE_SCALE_R__SHIFT 0x10
+#define COL_MAN0_PRESCALE_VALUES_R__PRESCALE_BIAS_R_MASK 0x0000FFFFL
+#define COL_MAN0_PRESCALE_VALUES_R__PRESCALE_SCALE_R_MASK 0xFFFF0000L
+//COL_MAN0_PRESCALE_VALUES_G
+#define COL_MAN0_PRESCALE_VALUES_G__PRESCALE_BIAS_G__SHIFT 0x0
+#define COL_MAN0_PRESCALE_VALUES_G__PRESCALE_SCALE_G__SHIFT 0x10
+#define COL_MAN0_PRESCALE_VALUES_G__PRESCALE_BIAS_G_MASK 0x0000FFFFL
+#define COL_MAN0_PRESCALE_VALUES_G__PRESCALE_SCALE_G_MASK 0xFFFF0000L
+//COL_MAN0_PRESCALE_VALUES_B
+#define COL_MAN0_PRESCALE_VALUES_B__PRESCALE_BIAS_B__SHIFT 0x0
+#define COL_MAN0_PRESCALE_VALUES_B__PRESCALE_SCALE_B__SHIFT 0x10
+#define COL_MAN0_PRESCALE_VALUES_B__PRESCALE_BIAS_B_MASK 0x0000FFFFL
+#define COL_MAN0_PRESCALE_VALUES_B__PRESCALE_SCALE_B_MASK 0xFFFF0000L
+//COL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL
+#define COL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE__SHIFT 0x0
+#define COL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE_MASK 0x00000007L
+//COL_MAN0_OUTPUT_CSC_C11_C12_A
+#define COL_MAN0_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A__SHIFT 0x0
+#define COL_MAN0_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A__SHIFT 0x10
+#define COL_MAN0_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A_MASK 0x0000FFFFL
+#define COL_MAN0_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A_MASK 0xFFFF0000L
+//COL_MAN0_OUTPUT_CSC_C13_C14_A
+#define COL_MAN0_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A__SHIFT 0x0
+#define COL_MAN0_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A__SHIFT 0x10
+#define COL_MAN0_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A_MASK 0x0000FFFFL
+#define COL_MAN0_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A_MASK 0xFFFF0000L
+//COL_MAN0_OUTPUT_CSC_C21_C22_A
+#define COL_MAN0_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A__SHIFT 0x0
+#define COL_MAN0_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A__SHIFT 0x10
+#define COL_MAN0_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A_MASK 0x0000FFFFL
+#define COL_MAN0_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A_MASK 0xFFFF0000L
+//COL_MAN0_OUTPUT_CSC_C23_C24_A
+#define COL_MAN0_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A__SHIFT 0x0
+#define COL_MAN0_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A__SHIFT 0x10
+#define COL_MAN0_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A_MASK 0x0000FFFFL
+#define COL_MAN0_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A_MASK 0xFFFF0000L
+//COL_MAN0_OUTPUT_CSC_C31_C32_A
+#define COL_MAN0_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A__SHIFT 0x0
+#define COL_MAN0_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A__SHIFT 0x10
+#define COL_MAN0_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A_MASK 0x0000FFFFL
+#define COL_MAN0_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A_MASK 0xFFFF0000L
+//COL_MAN0_OUTPUT_CSC_C33_C34_A
+#define COL_MAN0_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A__SHIFT 0x0
+#define COL_MAN0_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A__SHIFT 0x10
+#define COL_MAN0_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A_MASK 0x0000FFFFL
+#define COL_MAN0_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A_MASK 0xFFFF0000L
+//COL_MAN0_OUTPUT_CSC_C11_C12_B
+#define COL_MAN0_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B__SHIFT 0x0
+#define COL_MAN0_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B__SHIFT 0x10
+#define COL_MAN0_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B_MASK 0x0000FFFFL
+#define COL_MAN0_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B_MASK 0xFFFF0000L
+//COL_MAN0_OUTPUT_CSC_C13_C14_B
+#define COL_MAN0_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B__SHIFT 0x0
+#define COL_MAN0_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B__SHIFT 0x10
+#define COL_MAN0_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B_MASK 0x0000FFFFL
+#define COL_MAN0_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B_MASK 0xFFFF0000L
+//COL_MAN0_OUTPUT_CSC_C21_C22_B
+#define COL_MAN0_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B__SHIFT 0x0
+#define COL_MAN0_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B__SHIFT 0x10
+#define COL_MAN0_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B_MASK 0x0000FFFFL
+#define COL_MAN0_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B_MASK 0xFFFF0000L
+//COL_MAN0_OUTPUT_CSC_C23_C24_B
+#define COL_MAN0_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B__SHIFT 0x0
+#define COL_MAN0_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B__SHIFT 0x10
+#define COL_MAN0_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B_MASK 0x0000FFFFL
+#define COL_MAN0_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B_MASK 0xFFFF0000L
+//COL_MAN0_OUTPUT_CSC_C31_C32_B
+#define COL_MAN0_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B__SHIFT 0x0
+#define COL_MAN0_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B__SHIFT 0x10
+#define COL_MAN0_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B_MASK 0x0000FFFFL
+#define COL_MAN0_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B_MASK 0xFFFF0000L
+//COL_MAN0_OUTPUT_CSC_C33_C34_B
+#define COL_MAN0_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B__SHIFT 0x0
+#define COL_MAN0_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B__SHIFT 0x10
+#define COL_MAN0_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B_MASK 0x0000FFFFL
+#define COL_MAN0_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B_MASK 0xFFFF0000L
+//COL_MAN0_DENORM_CLAMP_CONTROL
+#define COL_MAN0_DENORM_CLAMP_CONTROL__DENORM_MODE__SHIFT 0x0
+#define COL_MAN0_DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT__SHIFT 0x8
+#define COL_MAN0_DENORM_CLAMP_CONTROL__DENORM_MODE_MASK 0x00000003L
+#define COL_MAN0_DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT_MASK 0x00000100L
+//COL_MAN0_DENORM_CLAMP_RANGE_R_CR
+#define COL_MAN0_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR__SHIFT 0x0
+#define COL_MAN0_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR__SHIFT 0xc
+#define COL_MAN0_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR_MASK 0x00000FFFL
+#define COL_MAN0_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR_MASK 0x00FFF000L
+//COL_MAN0_DENORM_CLAMP_RANGE_G_Y
+#define COL_MAN0_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y__SHIFT 0x0
+#define COL_MAN0_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y__SHIFT 0xc
+#define COL_MAN0_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y_MASK 0x00000FFFL
+#define COL_MAN0_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y_MASK 0x00FFF000L
+//COL_MAN0_DENORM_CLAMP_RANGE_B_CB
+#define COL_MAN0_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB__SHIFT 0x0
+#define COL_MAN0_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB__SHIFT 0xc
+#define COL_MAN0_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB_MASK 0x00000FFFL
+#define COL_MAN0_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB_MASK 0x00FFF000L
+//COL_MAN0_COL_MAN_FP_CONVERTED_FIELD
+#define COL_MAN0_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
+#define COL_MAN0_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
+#define COL_MAN0_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
+#define COL_MAN0_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
+//COL_MAN0_COL_MAN_REGAMMA_CONTROL
+#define COL_MAN0_COL_MAN_REGAMMA_CONTROL__COL_MAN_REGAMMA_MODE__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CONTROL__COL_MAN_REGAMMA_MODE_MASK 0x00000007L
+//COL_MAN0_COL_MAN_REGAMMA_LUT_INDEX
+#define COL_MAN0_COL_MAN_REGAMMA_LUT_INDEX__COL_MAN_REGAMMA_LUT_INDEX__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_LUT_INDEX__COL_MAN_REGAMMA_LUT_INDEX_MASK 0x000001FFL
+//COL_MAN0_COL_MAN_REGAMMA_LUT_DATA
+#define COL_MAN0_COL_MAN_REGAMMA_LUT_DATA__COL_MAN_REGAMMA_LUT_DATA__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_LUT_DATA__COL_MAN_REGAMMA_LUT_DATA_MASK 0x0007FFFFL
+//COL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK
+#define COL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK__COL_MAN_REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK__COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
+//COL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+//COL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+//COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
+//COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+//COL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+//COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
+//COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN0_PACK_FIFO_ERROR
+#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED__SHIFT 0x0
+#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK__SHIFT 0x1
+#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED__SHIFT 0x8
+#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK__SHIFT 0x9
+#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED__SHIFT 0x10
+#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK__SHIFT 0x11
+#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED__SHIFT 0x18
+#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK__SHIFT 0x19
+#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED_MASK 0x00000001L
+#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK_MASK 0x00000002L
+#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED_MASK 0x00000100L
+#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK_MASK 0x00000200L
+#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED_MASK 0x00010000L
+#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK_MASK 0x00020000L
+#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED_MASK 0x01000000L
+#define COL_MAN0_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK_MASK 0x02000000L
+//COL_MAN0_OUTPUT_FIFO_ERROR
+#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED__SHIFT 0x0
+#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK__SHIFT 0x1
+#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED__SHIFT 0x8
+#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK__SHIFT 0x9
+#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED_MASK 0x00000001L
+#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK_MASK 0x00000002L
+#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED_MASK 0x00000100L
+#define COL_MAN0_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK_MASK 0x00000200L
+//COL_MAN0_INPUT_GAMMA_LUT_AUTOFILL
+#define COL_MAN0_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL__SHIFT 0x0
+#define COL_MAN0_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE__SHIFT 0x1
+#define COL_MAN0_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_MASK 0x00000001L
+#define COL_MAN0_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE_MASK 0x00000002L
+//COL_MAN0_INPUT_GAMMA_LUT_RW_INDEX
+#define COL_MAN0_INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX__SHIFT 0x0
+#define COL_MAN0_INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX_MASK 0x000000FFL
+//COL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR
+#define COL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR__SHIFT 0x0
+#define COL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR_MASK 0x0000FFFFL
+//COL_MAN0_INPUT_GAMMA_LUT_PWL_DATA
+#define COL_MAN0_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE__SHIFT 0x0
+#define COL_MAN0_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA__SHIFT 0x10
+#define COL_MAN0_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE_MASK 0x0000FFFFL
+#define COL_MAN0_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA_MASK 0xFFFF0000L
+//COL_MAN0_INPUT_GAMMA_LUT_30_COLOR
+#define COL_MAN0_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE__SHIFT 0x0
+#define COL_MAN0_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN__SHIFT 0xa
+#define COL_MAN0_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED__SHIFT 0x14
+#define COL_MAN0_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE_MASK 0x000003FFL
+#define COL_MAN0_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
+#define COL_MAN0_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED_MASK 0x3FF00000L
+//COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE__SHIFT 0x0
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN__SHIFT 0x1a
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE_MASK 0x00000003L
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN_MASK 0x04000000L
+//COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B__SHIFT 0x1
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN__SHIFT 0x5
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT__SHIFT 0x6
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G__SHIFT 0x8
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN__SHIFT 0xc
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT__SHIFT 0xd
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R__SHIFT 0xf
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN__SHIFT 0x13
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT__SHIFT 0x14
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE__SHIFT 0x16
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK__SHIFT 0x17
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE__SHIFT 0x1a
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x1b
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B_MASK 0x0000001EL
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN_MASK 0x00000020L
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT_MASK 0x000000C0L
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G_MASK 0x00000F00L
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN_MASK 0x00001000L
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT_MASK 0x00006000L
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R_MASK 0x00078000L
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN_MASK 0x00080000L
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT_MASK 0x00300000L
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE_MASK 0x00400000L
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK_MASK 0x03800000L
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE_MASK 0x04000000L
+#define COL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x08000000L
+//COL_MAN0_INPUT_GAMMA_BW_OFFSETS_B
+#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B__SHIFT 0x0
+#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B__SHIFT 0x10
+#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B_MASK 0x0000FFFFL
+#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B_MASK 0xFFFF0000L
+//COL_MAN0_INPUT_GAMMA_BW_OFFSETS_G
+#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G__SHIFT 0x0
+#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G__SHIFT 0x10
+#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G_MASK 0x0000FFFFL
+#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G_MASK 0xFFFF0000L
+//COL_MAN0_INPUT_GAMMA_BW_OFFSETS_R
+#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R__SHIFT 0x0
+#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R__SHIFT 0x10
+#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R_MASK 0x0000FFFFL
+#define COL_MAN0_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R_MASK 0xFFFF0000L
+//COL_MAN0_COL_MAN_DEGAMMA_CONTROL
+#define COL_MAN0_COL_MAN_DEGAMMA_CONTROL__COL_MAN_DEGAMMA_MODE__SHIFT 0x0
+#define COL_MAN0_COL_MAN_DEGAMMA_CONTROL__COL_MAN_DEGAMMA_MODE_MASK 0x00000003L
+//COL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL__COL_MAN_GAMUT_REMAP_MODE__SHIFT 0x0
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL__COL_MAN_GAMUT_REMAP_MODE_MASK 0x00000003L
+//COL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C11__SHIFT 0x0
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C12__SHIFT 0x10
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C11_MASK 0x0000FFFFL
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C12_MASK 0xFFFF0000L
+//COL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C13__SHIFT 0x0
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C14__SHIFT 0x10
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C13_MASK 0x0000FFFFL
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C14_MASK 0xFFFF0000L
+//COL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C21__SHIFT 0x0
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C22__SHIFT 0x10
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C21_MASK 0x0000FFFFL
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C22_MASK 0xFFFF0000L
+//COL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C23__SHIFT 0x0
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C24__SHIFT 0x10
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C23_MASK 0x0000FFFFL
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C24_MASK 0xFFFF0000L
+//COL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C31__SHIFT 0x0
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C32__SHIFT 0x10
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C31_MASK 0x0000FFFFL
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C32_MASK 0xFFFF0000L
+//COL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C33__SHIFT 0x0
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C34__SHIFT 0x10
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C33_MASK 0x0000FFFFL
+#define COL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C34_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dcfev0_dispdec
+//DCFEV0_DCFEV_CLOCK_CONTROL
+#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE__SHIFT 0x3
+#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE__SHIFT 0x7
+#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE__SHIFT 0x9
+#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE__SHIFT 0xb
+#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE__SHIFT 0xd
+#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE__SHIFT 0xf
+#define DCFEV0_DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL__SHIFT 0x18
+#define DCFEV0_DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE__SHIFT 0x1f
+#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE_MASK 0x00000008L
+#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE_MASK 0x00000080L
+#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE_MASK 0x00000200L
+#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE_MASK 0x00000800L
+#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE_MASK 0x00002000L
+#define DCFEV0_DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE_MASK 0x00008000L
+#define DCFEV0_DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL_MASK 0x1F000000L
+#define DCFEV0_DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE_MASK 0x80000000L
+//DCFEV0_DCFEV_SOFT_RESET
+#define DCFEV0_DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET__SHIFT 0x0
+#define DCFEV0_DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET__SHIFT 0x1
+#define DCFEV0_DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET__SHIFT 0x2
+#define DCFEV0_DCFEV_SOFT_RESET__SCLV_SOFT_RESET__SHIFT 0x3
+#define DCFEV0_DCFEV_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
+#define DCFEV0_DCFEV_SOFT_RESET__PSCLV_SOFT_RESET__SHIFT 0x5
+#define DCFEV0_DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET__SHIFT 0x6
+#define DCFEV0_DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
+#define DCFEV0_DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET_MASK 0x00000002L
+#define DCFEV0_DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET_MASK 0x00000004L
+#define DCFEV0_DCFEV_SOFT_RESET__SCLV_SOFT_RESET_MASK 0x00000008L
+#define DCFEV0_DCFEV_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
+#define DCFEV0_DCFEV_SOFT_RESET__PSCLV_SOFT_RESET_MASK 0x00000020L
+#define DCFEV0_DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET_MASK 0x00000040L
+//DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL
+#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x3
+#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS__SHIFT 0x4
+#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS__SHIFT 0x5
+#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET__SHIFT 0x6
+#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL__SHIFT 0x18
+#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE__SHIFT 0x1f
+#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS_MASK 0x00000008L
+#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS_MASK 0x00000010L
+#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS_MASK 0x00000020L
+#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET_MASK 0x00000040L
+#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL_MASK 0x1F000000L
+#define DCFEV0_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE_MASK 0x80000000L
+//DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL__SHIFT 0x0
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE__SHIFT 0x2
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE__SHIFT 0x3
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE__SHIFT 0x4
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE__SHIFT 0x5
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE__SHIFT 0x6
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE__SHIFT 0x7
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE__SHIFT 0x8
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE__SHIFT 0x9
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE__SHIFT 0xa
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE__SHIFT 0xb
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL_MASK 0x00000003L
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE_MASK 0x00000004L
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE_MASK 0x00000008L
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE_MASK 0x00000010L
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE_MASK 0x00000020L
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE_MASK 0x00000040L
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE_MASK 0x00000080L
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE_MASK 0x00000100L
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE_MASK 0x00000200L
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE_MASK 0x00000400L
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE_MASK 0x00000800L
+//DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE__SHIFT 0x0
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE__SHIFT 0x2
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE__SHIFT 0x4
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE__SHIFT 0x6
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE__SHIFT 0x8
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE__SHIFT 0xa
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE__SHIFT 0xc
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE__SHIFT 0xe
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE__SHIFT 0x10
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE__SHIFT 0x12
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE_MASK 0x00000003L
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE_MASK 0x0000000CL
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE_MASK 0x00000030L
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE_MASK 0x000000C0L
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE_MASK 0x00000300L
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE_MASK 0x00000C00L
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE_MASK 0x00003000L
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE_MASK 0x0000C000L
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE_MASK 0x00030000L
+#define DCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE_MASK 0x000C0000L
+//DCFEV0_DCFEV_MEM_PWR_CTRL
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_FORCE__SHIFT 0x0
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_DIS__SHIFT 0x2
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE__SHIFT 0x3
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS__SHIFT 0x5
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE__SHIFT 0x6
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS__SHIFT 0x8
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE__SHIFT 0x9
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS__SHIFT 0xb
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE__SHIFT 0xc
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS__SHIFT 0xe
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE__SHIFT 0xf
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS__SHIFT 0x11
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_FORCE_MASK 0x00000003L
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_DIS_MASK 0x00000004L
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE_MASK 0x00000018L
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS_MASK 0x00000020L
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS_MASK 0x00000100L
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE_MASK 0x00000600L
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS_MASK 0x00000800L
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE_MASK 0x00003000L
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS_MASK 0x00004000L
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE_MASK 0x00018000L
+#define DCFEV0_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS_MASK 0x00020000L
+//DCFEV0_DCFEV_MEM_PWR_CTRL2
+#define DCFEV0_DCFEV_MEM_PWR_CTRL2__COL_MAN_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x0
+#define DCFEV0_DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
+#define DCFEV0_DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
+#define DCFEV0_DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL__SHIFT 0x6
+#define DCFEV0_DCFEV_MEM_PWR_CTRL2__COL_MAN_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x00000003L
+#define DCFEV0_DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
+#define DCFEV0_DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
+#define DCFEV0_DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL_MASK 0x000000C0L
+//DCFEV0_DCFEV_MEM_PWR_STATUS
+#define DCFEV0_DCFEV_MEM_PWR_STATUS__COL_MAN_REGAMMA_MEM_PWR_STATE__SHIFT 0x0
+#define DCFEV0_DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE__SHIFT 0x2
+#define DCFEV0_DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE__SHIFT 0x4
+#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE__SHIFT 0x6
+#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE__SHIFT 0x8
+#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE__SHIFT 0xa
+#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE__SHIFT 0xc
+#define DCFEV0_DCFEV_MEM_PWR_STATUS__COL_MAN_REGAMMA_MEM_PWR_STATE_MASK 0x00000003L
+#define DCFEV0_DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE_MASK 0x0000000CL
+#define DCFEV0_DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE_MASK 0x00000030L
+#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE_MASK 0x000000C0L
+#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE_MASK 0x00000300L
+#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE_MASK 0x00000C00L
+#define DCFEV0_DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE_MASK 0x00003000L
+//DCFEV0_DCFEV_L_FLUSH
+#define DCFEV0_DCFEV_L_FLUSH__FLUSH_OCCURED__SHIFT 0x0
+#define DCFEV0_DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
+#define DCFEV0_DCFEV_L_FLUSH__FLUSH_DEEP__SHIFT 0x2
+#define DCFEV0_DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
+#define DCFEV0_DCFEV_L_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
+#define DCFEV0_DCFEV_L_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
+#define DCFEV0_DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
+#define DCFEV0_DCFEV_L_FLUSH__FLUSH_DEEP_MASK 0x00000004L
+#define DCFEV0_DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
+#define DCFEV0_DCFEV_L_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
+//DCFEV0_DCFEV_C_FLUSH
+#define DCFEV0_DCFEV_C_FLUSH__FLUSH_OCCURED__SHIFT 0x0
+#define DCFEV0_DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
+#define DCFEV0_DCFEV_C_FLUSH__FLUSH_DEEP__SHIFT 0x2
+#define DCFEV0_DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
+#define DCFEV0_DCFEV_C_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
+#define DCFEV0_DCFEV_C_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
+#define DCFEV0_DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
+#define DCFEV0_DCFEV_C_FLUSH__FLUSH_DEEP_MASK 0x00000004L
+#define DCFEV0_DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
+#define DCFEV0_DCFEV_C_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
+//DCFEV0_DCFEV_MISC
+#define DCFEV0_DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
+#define DCFEV0_DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_dc_perfmon11_dispdec
+//DC_PERFMON11_PERFCOUNTER_CNTL
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON11_PERFCOUNTER_CNTL2
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON11_PERFCOUNTER_STATE
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON11_PERFMON_CNTL
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON11_PERFMON_CNTL2
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON11_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON11_PERFMON_CVALUE_LOW
+#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON11_PERFMON_HI
+#define DC_PERFMON11_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON11_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON11_PERFMON_LOW
+#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dmifv_pg0_dispdec
+//DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1
+#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
+#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
+//DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2
+#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
+#define DMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
+//DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL
+#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
+#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18
+#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000003L
+#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000300L
+#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00030000L
+#define DMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x01000000L
+//DMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL
+#define DMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+#define DMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+#define DMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
+#define DMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
+//DMIFV_PG0_DPGV0_PIPE_DPM_CONTROL
+#define DMIFV_PG0_DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
+#define DMIFV_PG0_DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L
+//DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x00000100L
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x00000200L
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
+//DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL
+#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
+#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
+#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x00000001L
+#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
+#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
+#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
+#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
+#define DMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xFFFF0000L
+//DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00000010L
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00000020L
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00000040L
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00000080L
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x00000100L
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x00000200L
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x00000400L
+#define DMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x00000800L
+//DMIFV_PG0_DPGV0_REPEATER_PROGRAM
+#define DMIFV_PG0_DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+#define DMIFV_PG0_DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+#define DMIFV_PG0_DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
+#define DMIFV_PG0_DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
+//DMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL
+#define DMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+#define DMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
+//DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1
+#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
+#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
+//DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2
+#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
+#define DMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
+//DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL
+#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
+#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18
+#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000003L
+#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000300L
+#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00030000L
+#define DMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x01000000L
+//DMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL
+#define DMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+#define DMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+#define DMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
+#define DMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
+//DMIFV_PG0_DPGV1_PIPE_DPM_CONTROL
+#define DMIFV_PG0_DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
+#define DMIFV_PG0_DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L
+//DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x00000100L
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x00000200L
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
+//DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL
+#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
+#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
+#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x00000001L
+#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
+#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
+#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
+#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
+#define DMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xFFFF0000L
+//DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00000010L
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00000020L
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00000040L
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00000080L
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x00000100L
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x00000200L
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x00000400L
+#define DMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x00000800L
+//DMIFV_PG0_DPGV1_REPEATER_PROGRAM
+#define DMIFV_PG0_DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+#define DMIFV_PG0_DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+#define DMIFV_PG0_DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
+#define DMIFV_PG0_DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
+//DMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL
+#define DMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+#define DMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_blndv0_dispdec
+//BLNDV0_BLNDV_CONTROL
+#define BLNDV0_BLNDV_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
+#define BLNDV0_BLNDV_CONTROL__BLND_MODE__SHIFT 0x8
+#define BLNDV0_BLNDV_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
+#define BLNDV0_BLNDV_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
+#define BLNDV0_BLNDV_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
+#define BLNDV0_BLNDV_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
+#define BLNDV0_BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
+#define BLNDV0_BLNDV_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
+#define BLNDV0_BLNDV_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
+#define BLNDV0_BLNDV_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
+#define BLNDV0_BLNDV_CONTROL__BLND_MODE_MASK 0x00000300L
+#define BLNDV0_BLNDV_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
+#define BLNDV0_BLNDV_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
+#define BLNDV0_BLNDV_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
+#define BLNDV0_BLNDV_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
+#define BLNDV0_BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
+#define BLNDV0_BLNDV_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
+#define BLNDV0_BLNDV_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
+//BLNDV0_BLNDV_SM_CONTROL2
+#define BLNDV0_BLNDV_SM_CONTROL2__SM_MODE__SHIFT 0x0
+#define BLNDV0_BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
+#define BLNDV0_BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
+#define BLNDV0_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+#define BLNDV0_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+#define BLNDV0_BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
+#define BLNDV0_BLNDV_SM_CONTROL2__SM_MODE_MASK 0x00000007L
+#define BLNDV0_BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
+#define BLNDV0_BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
+#define BLNDV0_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+#define BLNDV0_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+#define BLNDV0_BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
+//BLNDV0_BLNDV_CONTROL2
+#define BLNDV0_BLNDV_CONTROL2__PTI_ENABLE__SHIFT 0x0
+#define BLNDV0_BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
+#define BLNDV0_BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
+#define BLNDV0_BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
+#define BLNDV0_BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
+#define BLNDV0_BLNDV_CONTROL2__PTI_ENABLE_MASK 0x00000001L
+#define BLNDV0_BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
+#define BLNDV0_BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
+#define BLNDV0_BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
+#define BLNDV0_BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
+//BLNDV0_BLNDV_UPDATE
+#define BLNDV0_BLNDV_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
+#define BLNDV0_BLNDV_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
+#define BLNDV0_BLNDV_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
+#define BLNDV0_BLNDV_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
+#define BLNDV0_BLNDV_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
+#define BLNDV0_BLNDV_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
+//BLNDV0_BLNDV_UNDERFLOW_INTERRUPT
+#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
+#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
+#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
+#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
+#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
+#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
+#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
+#define BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
+//BLNDV0_BLNDV_V_UPDATE_LOCK
+#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
+#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
+#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
+#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
+#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
+#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
+#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
+#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
+#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
+#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
+#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
+#define BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
+//BLNDV0_BLNDV_REG_UPDATE_STATUS
+#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
+#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
+#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
+#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
+#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
+#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
+#define BLNDV0_BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
+#define BLNDV0_BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
+#define BLNDV0_BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
+#define BLNDV0_BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
+#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
+#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
+#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
+#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
+#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
+#define BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
+#define BLNDV0_BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
+#define BLNDV0_BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
+#define BLNDV0_BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
+#define BLNDV0_BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
+
+
+// addressBlock: dce_dc_crtcv0_dispdec
+//CRTCV0_CRTCV_H_BLANK_EARLY_NUM
+#define CRTCV0_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
+#define CRTCV0_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
+#define CRTCV0_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
+#define CRTCV0_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
+//CRTCV0_CRTCV_H_TOTAL
+#define CRTCV0_CRTCV_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
+#define CRTCV0_CRTCV_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
+//CRTCV0_CRTCV_H_BLANK_START_END
+#define CRTCV0_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
+#define CRTCV0_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
+#define CRTCV0_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_H_SYNC_A
+#define CRTCV0_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
+#define CRTCV0_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
+#define CRTCV0_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_H_SYNC_A_CNTL
+#define CRTCV0_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
+#define CRTCV0_CRTCV_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
+#define CRTCV0_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
+#define CRTCV0_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
+#define CRTCV0_CRTCV_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
+#define CRTCV0_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
+//CRTCV0_CRTCV_H_SYNC_B
+#define CRTCV0_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
+#define CRTCV0_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
+#define CRTCV0_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_H_SYNC_B_CNTL
+#define CRTCV0_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
+#define CRTCV0_CRTCV_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
+#define CRTCV0_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
+#define CRTCV0_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
+#define CRTCV0_CRTCV_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
+#define CRTCV0_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
+//CRTCV0_CRTCV_VBI_END
+#define CRTCV0_CRTCV_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
+#define CRTCV0_CRTCV_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
+#define CRTCV0_CRTCV_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_V_TOTAL
+#define CRTCV0_CRTCV_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
+#define CRTCV0_CRTCV_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
+//CRTCV0_CRTCV_V_TOTAL_MIN
+#define CRTCV0_CRTCV_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
+#define CRTCV0_CRTCV_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
+//CRTCV0_CRTCV_V_TOTAL_MAX
+#define CRTCV0_CRTCV_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
+#define CRTCV0_CRTCV_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
+#define CRTCV0_CRTCV_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
+//CRTCV0_CRTCV_V_TOTAL_CONTROL
+#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
+#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
+#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
+#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
+#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
+#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
+#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
+#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
+#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
+#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
+#define CRTCV0_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+//CRTCV0_CRTCV_V_TOTAL_INT_STATUS
+#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+#define CRTCV0_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+//CRTCV0_CRTCV_VSYNC_NOM_INT_STATUS
+#define CRTCV0_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
+#define CRTCV0_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+#define CRTCV0_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
+#define CRTCV0_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+//CRTCV0_CRTCV_V_BLANK_START_END
+#define CRTCV0_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
+#define CRTCV0_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
+#define CRTCV0_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_V_SYNC_A
+#define CRTCV0_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
+#define CRTCV0_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
+#define CRTCV0_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_V_SYNC_A_CNTL
+#define CRTCV0_CRTCV_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
+#define CRTCV0_CRTCV_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
+//CRTCV0_CRTCV_V_SYNC_B
+#define CRTCV0_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
+#define CRTCV0_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
+#define CRTCV0_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_V_SYNC_B_CNTL
+#define CRTCV0_CRTCV_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
+#define CRTCV0_CRTCV_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
+//CRTCV0_CRTCV_DTMTEST_CNTL
+#define CRTCV0_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
+#define CRTCV0_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
+#define CRTCV0_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
+#define CRTCV0_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
+//CRTCV0_CRTCV_DTMTEST_STATUS_POSITION
+#define CRTCV0_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
+#define CRTCV0_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
+#define CRTCV0_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_TRIGA_CNTL
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
+#define CRTCV0_CRTCV_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
+//CRTCV0_CRTCV_TRIGA_MANUAL_TRIG
+#define CRTCV0_CRTCV_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
+#define CRTCV0_CRTCV_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+//CRTCV0_CRTCV_TRIGB_CNTL
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
+#define CRTCV0_CRTCV_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
+//CRTCV0_CRTCV_TRIGB_MANUAL_TRIG
+#define CRTCV0_CRTCV_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
+#define CRTCV0_CRTCV_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+//CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL
+#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+#define CRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+//CRTCV0_CRTCV_FLOW_CONTROL
+#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
+#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+#define CRTCV0_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+//CRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE
+#define CRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+#define CRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+#define CRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
+#define CRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+#define CRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+#define CRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+//CRTCV0_CRTCV_AVSYNC_COUNTER
+#define CRTCV0_CRTCV_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
+#define CRTCV0_CRTCV_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
+//CRTCV0_CRTCV_CONTROL
+#define CRTCV0_CRTCV_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTCV0_CRTCV_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
+#define CRTCV0_CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
+#define CRTCV0_CRTCV_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
+#define CRTCV0_CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
+#define CRTCV0_CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
+#define CRTCV0_CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+#define CRTCV0_CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
+#define CRTCV0_CRTCV_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
+#define CRTCV0_CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+#define CRTCV0_CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+#define CRTCV0_CRTCV_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
+#define CRTCV0_CRTCV_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
+#define CRTCV0_CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
+#define CRTCV0_CRTCV_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
+#define CRTCV0_CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
+#define CRTCV0_CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+#define CRTCV0_CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+#define CRTCV0_CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
+#define CRTCV0_CRTCV_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
+#define CRTCV0_CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+#define CRTCV0_CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+//CRTCV0_CRTCV_BLANK_CONTROL
+#define CRTCV0_CRTCV_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
+#define CRTCV0_CRTCV_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
+#define CRTCV0_CRTCV_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
+#define CRTCV0_CRTCV_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
+#define CRTCV0_CRTCV_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
+#define CRTCV0_CRTCV_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
+//CRTCV0_CRTCV_INTERLACE_CONTROL
+#define CRTCV0_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
+#define CRTCV0_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+#define CRTCV0_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
+#define CRTCV0_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+//CRTCV0_CRTCV_INTERLACE_STATUS
+#define CRTCV0_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+#define CRTCV0_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
+#define CRTCV0_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+#define CRTCV0_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+//CRTCV0_CRTCV_FIELD_INDICATION_CONTROL
+#define CRTCV0_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
+#define CRTCV0_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
+#define CRTCV0_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
+#define CRTCV0_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
+//CRTCV0_CRTCV_PIXEL_DATA_READBACK0
+#define CRTCV0_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+#define CRTCV0_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+#define CRTCV0_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
+#define CRTCV0_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
+//CRTCV0_CRTCV_PIXEL_DATA_READBACK1
+#define CRTCV0_CRTCV_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
+#define CRTCV0_CRTCV_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
+//CRTCV0_CRTCV_STATUS
+#define CRTCV0_CRTCV_STATUS__CRTC_V_BLANK__SHIFT 0x0
+#define CRTCV0_CRTCV_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
+#define CRTCV0_CRTCV_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
+#define CRTCV0_CRTCV_STATUS__CRTC_V_UPDATE__SHIFT 0x3
+#define CRTCV0_CRTCV_STATUS__CRTC_V_START_LINE__SHIFT 0x4
+#define CRTCV0_CRTCV_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+#define CRTCV0_CRTCV_STATUS__CRTC_H_BLANK__SHIFT 0x10
+#define CRTCV0_CRTCV_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
+#define CRTCV0_CRTCV_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
+#define CRTCV0_CRTCV_STATUS__CRTC_V_BLANK_MASK 0x00000001L
+#define CRTCV0_CRTCV_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
+#define CRTCV0_CRTCV_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
+#define CRTCV0_CRTCV_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
+#define CRTCV0_CRTCV_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
+#define CRTCV0_CRTCV_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+#define CRTCV0_CRTCV_STATUS__CRTC_H_BLANK_MASK 0x00010000L
+#define CRTCV0_CRTCV_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
+#define CRTCV0_CRTCV_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
+//CRTCV0_CRTCV_STATUS_POSITION
+#define CRTCV0_CRTCV_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
+#define CRTCV0_CRTCV_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
+#define CRTCV0_CRTCV_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_NOM_VERT_POSITION
+#define CRTCV0_CRTCV_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
+#define CRTCV0_CRTCV_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
+//CRTCV0_CRTCV_STATUS_FRAME_COUNT
+#define CRTCV0_CRTCV_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
+#define CRTCV0_CRTCV_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
+//CRTCV0_CRTCV_STATUS_VF_COUNT
+#define CRTCV0_CRTCV_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
+#define CRTCV0_CRTCV_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
+//CRTCV0_CRTCV_STATUS_HV_COUNT
+#define CRTCV0_CRTCV_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
+#define CRTCV0_CRTCV_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
+//CRTCV0_CRTCV_COUNT_CONTROL
+#define CRTCV0_CRTCV_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
+#define CRTCV0_CRTCV_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
+#define CRTCV0_CRTCV_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+#define CRTCV0_CRTCV_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+//CRTCV0_CRTCV_COUNT_RESET
+#define CRTCV0_CRTCV_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
+#define CRTCV0_CRTCV_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
+//CRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define CRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+#define CRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+//CRTCV0_CRTCV_VERT_SYNC_CONTROL
+#define CRTCV0_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+#define CRTCV0_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+#define CRTCV0_CRTCV_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+#define CRTCV0_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+#define CRTCV0_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+#define CRTCV0_CRTCV_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+//CRTCV0_CRTCV_STEREO_STATUS
+#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
+#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
+#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
+#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
+#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
+#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
+#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
+#define CRTCV0_CRTCV_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+//CRTCV0_CRTCV_STEREO_CONTROL
+#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
+#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
+#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
+#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
+#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
+#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+#define CRTCV0_CRTCV_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
+//CRTCV0_CRTCV_SNAPSHOT_STATUS
+#define CRTCV0_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
+#define CRTCV0_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
+#define CRTCV0_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+#define CRTCV0_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
+#define CRTCV0_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
+#define CRTCV0_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+//CRTCV0_CRTCV_SNAPSHOT_CONTROL
+#define CRTCV0_CRTCV_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+#define CRTCV0_CRTCV_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+//CRTCV0_CRTCV_SNAPSHOT_POSITION
+#define CRTCV0_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+#define CRTCV0_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+#define CRTCV0_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_SNAPSHOT_FRAME
+#define CRTCV0_CRTCV_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+#define CRTCV0_CRTCV_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+//CRTCV0_CRTCV_START_LINE_CONTROL
+#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
+#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
+#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
+#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
+#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
+#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
+#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
+#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
+#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
+#define CRTCV0_CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
+//CRTCV0_CRTCV_INTERRUPT_CONTROL
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+#define CRTCV0_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+//CRTCV0_CRTCV_UPDATE_LOCK
+#define CRTCV0_CRTCV_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
+#define CRTCV0_CRTCV_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
+//CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL
+#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
+#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
+#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
+#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
+#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
+#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
+#define CRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
+//CRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE
+#define CRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
+#define CRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
+//CRTCV0_CRTCV_TEST_PATTERN_CONTROL
+#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
+#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
+#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
+#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
+#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
+#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
+#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
+#define CRTCV0_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
+//CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS
+#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
+#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
+#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
+#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
+#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
+#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
+#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
+#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
+#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
+#define CRTCV0_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
+//CRTCV0_CRTCV_TEST_PATTERN_COLOR
+#define CRTCV0_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
+#define CRTCV0_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
+#define CRTCV0_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
+#define CRTCV0_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
+//CRTCV0_CRTCV_MASTER_UPDATE_LOCK
+#define CRTCV0_CRTCV_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
+#define CRTCV0_CRTCV_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
+#define CRTCV0_CRTCV_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
+#define CRTCV0_CRTCV_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
+#define CRTCV0_CRTCV_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
+#define CRTCV0_CRTCV_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
+//CRTCV0_CRTCV_MASTER_UPDATE_MODE
+#define CRTCV0_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
+#define CRTCV0_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
+#define CRTCV0_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
+#define CRTCV0_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
+//CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT
+#define CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
+#define CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
+#define CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
+#define CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
+//CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER
+#define CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
+#define CRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
+//CRTCV0_CRTCV_MVP_STATUS
+#define CRTCV0_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
+#define CRTCV0_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
+#define CRTCV0_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
+#define CRTCV0_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
+#define CRTCV0_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
+#define CRTCV0_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
+#define CRTCV0_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
+#define CRTCV0_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
+//CRTCV0_CRTCV_MASTER_EN
+#define CRTCV0_CRTCV_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTCV0_CRTCV_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
+//CRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT
+#define CRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
+#define CRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
+#define CRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
+#define CRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
+//CRTCV0_CRTCV_V_UPDATE_INT_STATUS
+#define CRTCV0_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
+#define CRTCV0_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
+#define CRTCV0_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
+#define CRTCV0_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
+//CRTCV0_CRTCV_OVERSCAN_COLOR
+#define CRTCV0_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
+#define CRTCV0_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
+#define CRTCV0_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
+#define CRTCV0_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
+#define CRTCV0_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
+#define CRTCV0_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
+//CRTCV0_CRTCV_OVERSCAN_COLOR_EXT
+#define CRTCV0_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
+#define CRTCV0_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
+#define CRTCV0_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
+#define CRTCV0_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
+#define CRTCV0_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
+#define CRTCV0_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
+//CRTCV0_CRTCV_BLANK_DATA_COLOR
+#define CRTCV0_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+#define CRTCV0_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+#define CRTCV0_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+#define CRTCV0_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+#define CRTCV0_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+#define CRTCV0_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+//CRTCV0_CRTCV_BLANK_DATA_COLOR_EXT
+#define CRTCV0_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+#define CRTCV0_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+#define CRTCV0_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+#define CRTCV0_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
+#define CRTCV0_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
+#define CRTCV0_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
+//CRTCV0_CRTCV_BLACK_COLOR
+#define CRTCV0_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
+#define CRTCV0_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
+#define CRTCV0_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
+#define CRTCV0_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
+#define CRTCV0_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+#define CRTCV0_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+//CRTCV0_CRTCV_BLACK_COLOR_EXT
+#define CRTCV0_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+#define CRTCV0_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+#define CRTCV0_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+#define CRTCV0_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
+#define CRTCV0_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
+#define CRTCV0_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
+//CRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+//CRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
+//CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+//CRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
+//CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+#define CRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+//CRTCV0_CRTCV_CRC_CNTL
+#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
+#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
+#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
+#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
+#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
+#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
+#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
+#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
+#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
+#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
+#define CRTCV0_CRTCV_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
+//CRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL
+#define CRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
+#define CRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
+#define CRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL
+#define CRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
+#define CRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
+#define CRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL
+#define CRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
+#define CRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
+#define CRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL
+#define CRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
+#define CRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
+#define CRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_CRC0_DATA_RG
+#define CRTCV0_CRTCV_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+#define CRTCV0_CRTCV_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+#define CRTCV0_CRTCV_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+#define CRTCV0_CRTCV_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+//CRTCV0_CRTCV_CRC0_DATA_B
+#define CRTCV0_CRTCV_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+#define CRTCV0_CRTCV_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+//CRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL
+#define CRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
+#define CRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
+#define CRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL
+#define CRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
+#define CRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
+#define CRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL
+#define CRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
+#define CRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
+#define CRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL
+#define CRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
+#define CRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
+#define CRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_CRC1_DATA_RG
+#define CRTCV0_CRTCV_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+#define CRTCV0_CRTCV_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+#define CRTCV0_CRTCV_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+#define CRTCV0_CRTCV_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+//CRTCV0_CRTCV_CRC1_DATA_B
+#define CRTCV0_CRTCV_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+#define CRTCV0_CRTCV_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+//CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
+//CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
+//CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
+//CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
+#define CRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
+//CRTCV0_CRTCV_STATIC_SCREEN_CONTROL
+#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
+#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
+#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
+#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
+#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
+#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
+#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
+#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
+#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
+#define CRTCV0_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
+//CRTCV0_CRTCV_3D_STRUCTURE_CONTROL
+#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
+#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
+#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
+#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
+#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+#define CRTCV0_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+//CRTCV0_CRTCV_GSL_VSYNC_GAP
+#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
+#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+#define CRTCV0_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
+//CRTCV0_CRTCV_GSL_WINDOW
+#define CRTCV0_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
+#define CRTCV0_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
+#define CRTCV0_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
+//CRTCV0_CRTCV_GSL_CONTROL
+#define CRTCV0_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
+#define CRTCV0_CRTCV_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
+#define CRTCV0_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+#define CRTCV0_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
+#define CRTCV0_CRTCV_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
+#define CRTCV0_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+
+
+// addressBlock: dce_dc_unp1_dispdec
+//UNP1_UNP_GRPH_ENABLE
+#define UNP1_UNP_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
+#define UNP1_UNP_GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
+//UNP1_UNP_GRPH_CONTROL
+#define UNP1_UNP_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
+#define UNP1_UNP_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2
+#define UNP1_UNP_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
+#define UNP1_UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L__SHIFT 0x6
+#define UNP1_UNP_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
+#define UNP1_UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L__SHIFT 0xb
+#define UNP1_UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L__SHIFT 0xd
+#define UNP1_UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+#define UNP1_UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+#define UNP1_UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L__SHIFT 0x12
+#define UNP1_UNP_GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14
+#define UNP1_UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18
+#define UNP1_UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L__SHIFT 0x1d
+#define UNP1_UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
+#define UNP1_UNP_GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
+#define UNP1_UNP_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x0000000CL
+#define UNP1_UNP_GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
+#define UNP1_UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L_MASK 0x000000C0L
+#define UNP1_UNP_GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
+#define UNP1_UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L_MASK 0x00001800L
+#define UNP1_UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L_MASK 0x0000E000L
+#define UNP1_UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
+#define UNP1_UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
+#define UNP1_UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L_MASK 0x000C0000L
+#define UNP1_UNP_GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0x00F00000L
+#define UNP1_UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1F000000L
+#define UNP1_UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L_MASK 0x60000000L
+#define UNP1_UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
+//UNP1_UNP_GRPH_CONTROL_C
+#define UNP1_UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C__SHIFT 0x6
+#define UNP1_UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C__SHIFT 0xb
+#define UNP1_UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C__SHIFT 0xd
+#define UNP1_UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C__SHIFT 0x12
+#define UNP1_UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C__SHIFT 0x1d
+#define UNP1_UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C_MASK 0x000000C0L
+#define UNP1_UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C_MASK 0x00001800L
+#define UNP1_UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C_MASK 0x0000E000L
+#define UNP1_UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C_MASK 0x000C0000L
+#define UNP1_UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C_MASK 0x60000000L
+//UNP1_UNP_GRPH_CONTROL_EXP
+#define UNP1_UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT__SHIFT 0x0
+#define UNP1_UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT_MASK 0x00000007L
+//UNP1_UNP_GRPH_SWAP_CNTL
+#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
+#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
+#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
+#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
+#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
+#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
+#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000C0L
+#define UNP1_UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
+//UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L
+#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT 0x8
+#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
+//UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C
+#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x8
+#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
+//UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L
+#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
+//UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
+//UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L
+#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
+#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
+//UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C
+#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
+#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
+//UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L
+#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
+//UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C
+#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
+//UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L
+#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L__SHIFT 0x8
+#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
+//UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C
+#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x8
+#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
+//UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L
+#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
+//UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
+//UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L
+#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
+#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xFFFFFF00L
+//UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C
+#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
+#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xFFFFFF00L
+//UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L
+#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0x000000FFL
+//UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C
+#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0x000000FFL
+//UNP1_UNP_GRPH_PITCH_L
+#define UNP1_UNP_GRPH_PITCH_L__GRPH_PITCH_L__SHIFT 0x0
+#define UNP1_UNP_GRPH_PITCH_L__GRPH_PITCH_L_MASK 0x00007FFFL
+//UNP1_UNP_GRPH_PITCH_C
+#define UNP1_UNP_GRPH_PITCH_C__GRPH_PITCH_C__SHIFT 0x0
+#define UNP1_UNP_GRPH_PITCH_C__GRPH_PITCH_C_MASK 0x00007FFFL
+//UNP1_UNP_GRPH_SURFACE_OFFSET_X_L
+#define UNP1_UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L__SHIFT 0x0
+#define UNP1_UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L_MASK 0x00003FFFL
+//UNP1_UNP_GRPH_SURFACE_OFFSET_X_C
+#define UNP1_UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C__SHIFT 0x0
+#define UNP1_UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C_MASK 0x00003FFFL
+//UNP1_UNP_GRPH_SURFACE_OFFSET_Y_L
+#define UNP1_UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L__SHIFT 0x0
+#define UNP1_UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L_MASK 0x00003FFFL
+//UNP1_UNP_GRPH_SURFACE_OFFSET_Y_C
+#define UNP1_UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C__SHIFT 0x0
+#define UNP1_UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C_MASK 0x00003FFFL
+//UNP1_UNP_GRPH_X_START_L
+#define UNP1_UNP_GRPH_X_START_L__GRPH_X_START_L__SHIFT 0x0
+#define UNP1_UNP_GRPH_X_START_L__GRPH_X_START_L_MASK 0x00003FFFL
+//UNP1_UNP_GRPH_X_START_C
+#define UNP1_UNP_GRPH_X_START_C__GRPH_X_START_C__SHIFT 0x0
+#define UNP1_UNP_GRPH_X_START_C__GRPH_X_START_C_MASK 0x00003FFFL
+//UNP1_UNP_GRPH_Y_START_L
+#define UNP1_UNP_GRPH_Y_START_L__GRPH_Y_START_L__SHIFT 0x0
+#define UNP1_UNP_GRPH_Y_START_L__GRPH_Y_START_L_MASK 0x00003FFFL
+//UNP1_UNP_GRPH_Y_START_C
+#define UNP1_UNP_GRPH_Y_START_C__GRPH_Y_START_C__SHIFT 0x0
+#define UNP1_UNP_GRPH_Y_START_C__GRPH_Y_START_C_MASK 0x00003FFFL
+//UNP1_UNP_GRPH_X_END_L
+#define UNP1_UNP_GRPH_X_END_L__GRPH_X_END_L__SHIFT 0x0
+#define UNP1_UNP_GRPH_X_END_L__GRPH_X_END_L_MASK 0x00007FFFL
+//UNP1_UNP_GRPH_X_END_C
+#define UNP1_UNP_GRPH_X_END_C__GRPH_X_END_C__SHIFT 0x0
+#define UNP1_UNP_GRPH_X_END_C__GRPH_X_END_C_MASK 0x00007FFFL
+//UNP1_UNP_GRPH_Y_END_L
+#define UNP1_UNP_GRPH_Y_END_L__GRPH_Y_END_L__SHIFT 0x0
+#define UNP1_UNP_GRPH_Y_END_L__GRPH_Y_END_L_MASK 0x00007FFFL
+//UNP1_UNP_GRPH_Y_END_C
+#define UNP1_UNP_GRPH_Y_END_C__GRPH_Y_END_C__SHIFT 0x0
+#define UNP1_UNP_GRPH_Y_END_C__GRPH_Y_END_C_MASK 0x00007FFFL
+//UNP1_UNP_GRPH_UPDATE
+#define UNP1_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
+#define UNP1_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
+#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
+#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
+#define UNP1_UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
+#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
+#define UNP1_UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
+#define UNP1_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
+#define UNP1_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
+#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
+#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
+#define UNP1_UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
+#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x00100000L
+#define UNP1_UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+#define UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
+//UNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT
+#define UNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L__SHIFT 0x0
+#define UNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C__SHIFT 0x8
+#define UNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L_MASK 0x000000FFL
+#define UNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C_MASK 0x0000FF00L
+//UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L
+#define UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L__SHIFT 0x8
+#define UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L_MASK 0xFFFFFF00L
+//UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C
+#define UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C__SHIFT 0x8
+#define UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C_MASK 0xFFFFFF00L
+//UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L
+#define UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__SHIFT 0x0
+#define UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_MASK 0x000000FFL
+//UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C
+#define UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__SHIFT 0x0
+#define UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_MASK 0x000000FFL
+//UNP1_UNP_DVMM_PTE_CONTROL
+#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
+#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
+#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
+#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
+#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
+#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
+#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x00000001L
+#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x0000001EL
+#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x000001E0L
+#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x0007FE00L
+#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x00100000L
+#define UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x00200000L
+//UNP1_UNP_DVMM_PTE_CONTROL_C
+#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C__SHIFT 0x0
+#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C__SHIFT 0x1
+#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C__SHIFT 0x5
+#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C__SHIFT 0x9
+#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C__SHIFT 0x14
+#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C__SHIFT 0x15
+#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C_MASK 0x00000001L
+#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C_MASK 0x0000001EL
+#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C_MASK 0x000001E0L
+#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C_MASK 0x0007FE00L
+#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C_MASK 0x00100000L
+#define UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C_MASK 0x00200000L
+//UNP1_UNP_DVMM_PTE_ARB_CONTROL
+#define UNP1_UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
+#define UNP1_UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
+#define UNP1_UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x0000003FL
+#define UNP1_UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0x0000FF00L
+//UNP1_UNP_DVMM_PTE_ARB_CONTROL_C
+#define UNP1_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C__SHIFT 0x0
+#define UNP1_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C__SHIFT 0x8
+#define UNP1_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C_MASK 0x0000003FL
+#define UNP1_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C_MASK 0x0000FF00L
+//UNP1_UNP_GRPH_INTERRUPT_STATUS
+#define UNP1_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
+#define UNP1_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
+#define UNP1_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
+#define UNP1_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
+//UNP1_UNP_GRPH_INTERRUPT_CONTROL
+#define UNP1_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
+#define UNP1_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
+#define UNP1_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
+#define UNP1_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
+//UNP1_UNP_GRPH_STEREOSYNC_FLIP
+#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
+#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x4
+#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN__SHIFT 0x8
+#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE__SHIFT 0xc
+#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING__SHIFT 0x12
+#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING__SHIFT 0x13
+#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
+#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000030L
+#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN_MASK 0x00000100L
+#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE_MASK 0x00003000L
+#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
+#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
+#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING_MASK 0x00040000L
+#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING_MASK 0x00080000L
+#define UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
+//UNP1_UNP_FLIP_CONTROL
+#define UNP1_UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x0
+#define UNP1_UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x00000001L
+//UNP1_UNP_CRC_CONTROL
+#define UNP1_UNP_CRC_CONTROL__UNP_CRC_ENABLE__SHIFT 0x0
+#define UNP1_UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL__SHIFT 0x2
+#define UNP1_UNP_CRC_CONTROL__UNP_CRC_LINE_SEL__SHIFT 0x8
+#define UNP1_UNP_CRC_CONTROL__UNP_CRC_ENABLE_MASK 0x00000001L
+#define UNP1_UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL_MASK 0x0000001CL
+#define UNP1_UNP_CRC_CONTROL__UNP_CRC_LINE_SEL_MASK 0x00000300L
+//UNP1_UNP_CRC_MASK
+#define UNP1_UNP_CRC_MASK__UNP_CRC_MASK__SHIFT 0x0
+#define UNP1_UNP_CRC_MASK__UNP_CRC_MASK_MASK 0xFFFFFFFFL
+//UNP1_UNP_CRC_CURRENT
+#define UNP1_UNP_CRC_CURRENT__UNP_CRC_CURRENT__SHIFT 0x0
+#define UNP1_UNP_CRC_CURRENT__UNP_CRC_CURRENT_MASK 0xFFFFFFFFL
+//UNP1_UNP_CRC_LAST
+#define UNP1_UNP_CRC_LAST__UNP_CRC_LAST__SHIFT 0x0
+#define UNP1_UNP_CRC_LAST__UNP_CRC_LAST_MASK 0xFFFFFFFFL
+//UNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK
+#define UNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK__SHIFT 0x4
+#define UNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK_MASK 0x000001F0L
+//UNP1_UNP_HW_ROTATION
+#define UNP1_UNP_HW_ROTATION__ROTATION_ANGLE__SHIFT 0x0
+#define UNP1_UNP_HW_ROTATION__PIXEL_DROP__SHIFT 0x4
+#define UNP1_UNP_HW_ROTATION__BUFFER_MODE__SHIFT 0x8
+#define UNP1_UNP_HW_ROTATION__ROTATION_ANGLE_MASK 0x00000007L
+#define UNP1_UNP_HW_ROTATION__PIXEL_DROP_MASK 0x00000010L
+#define UNP1_UNP_HW_ROTATION__BUFFER_MODE_MASK 0x00000100L
+
+
+// addressBlock: dce_dc_lbv1_dispdec
+//LBV1_LBV_DATA_FORMAT
+#define LBV1_LBV_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
+#define LBV1_LBV_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
+#define LBV1_LBV_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
+#define LBV1_LBV_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
+#define LBV1_LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
+#define LBV1_LBV_DATA_FORMAT__DITHER_EN__SHIFT 0x6
+#define LBV1_LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN__SHIFT 0x7
+#define LBV1_LBV_DATA_FORMAT__PREFETCH__SHIFT 0xc
+#define LBV1_LBV_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
+#define LBV1_LBV_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
+#define LBV1_LBV_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L
+#define LBV1_LBV_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000004L
+#define LBV1_LBV_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000008L
+#define LBV1_LBV_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00000010L
+#define LBV1_LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00000020L
+#define LBV1_LBV_DATA_FORMAT__DITHER_EN_MASK 0x00000040L
+#define LBV1_LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN_MASK 0x00000080L
+#define LBV1_LBV_DATA_FORMAT__PREFETCH_MASK 0x00001000L
+#define LBV1_LBV_DATA_FORMAT__REQUEST_MODE_MASK 0x01000000L
+#define LBV1_LBV_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L
+//LBV1_LBV_MEMORY_CTRL
+#define LBV1_LBV_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
+#define LBV1_LBV_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+#define LBV1_LBV_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
+#define LBV1_LBV_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x00000FFFL
+#define LBV1_LBV_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x000F0000L
+#define LBV1_LBV_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x00300000L
+//LBV1_LBV_MEMORY_SIZE_STATUS
+#define LBV1_LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
+#define LBV1_LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x00000FFFL
+//LBV1_LBV_DESKTOP_HEIGHT
+#define LBV1_LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
+#define LBV1_LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x00007FFFL
+//LBV1_LBV_VLINE_START_END
+#define LBV1_LBV_VLINE_START_END__VLINE_START__SHIFT 0x0
+#define LBV1_LBV_VLINE_START_END__VLINE_END__SHIFT 0x10
+#define LBV1_LBV_VLINE_START_END__VLINE_INV__SHIFT 0x1f
+#define LBV1_LBV_VLINE_START_END__VLINE_START_MASK 0x00003FFFL
+#define LBV1_LBV_VLINE_START_END__VLINE_END_MASK 0x7FFF0000L
+#define LBV1_LBV_VLINE_START_END__VLINE_INV_MASK 0x80000000L
+//LBV1_LBV_VLINE2_START_END
+#define LBV1_LBV_VLINE2_START_END__VLINE2_START__SHIFT 0x0
+#define LBV1_LBV_VLINE2_START_END__VLINE2_END__SHIFT 0x10
+#define LBV1_LBV_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
+#define LBV1_LBV_VLINE2_START_END__VLINE2_START_MASK 0x00003FFFL
+#define LBV1_LBV_VLINE2_START_END__VLINE2_END_MASK 0x7FFF0000L
+#define LBV1_LBV_VLINE2_START_END__VLINE2_INV_MASK 0x80000000L
+//LBV1_LBV_V_COUNTER
+#define LBV1_LBV_V_COUNTER__V_COUNTER__SHIFT 0x0
+#define LBV1_LBV_V_COUNTER__V_COUNTER_MASK 0x00007FFFL
+//LBV1_LBV_SNAPSHOT_V_COUNTER
+#define LBV1_LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
+#define LBV1_LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x00007FFFL
+//LBV1_LBV_V_COUNTER_CHROMA
+#define LBV1_LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA__SHIFT 0x0
+#define LBV1_LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA_MASK 0x00007FFFL
+//LBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA
+#define LBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA__SHIFT 0x0
+#define LBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA_MASK 0x00007FFFL
+//LBV1_LBV_INTERRUPT_MASK
+#define LBV1_LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
+#define LBV1_LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
+#define LBV1_LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
+#define LBV1_LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x00000001L
+#define LBV1_LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x00000010L
+#define LBV1_LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x00000100L
+//LBV1_LBV_VLINE_STATUS
+#define LBV1_LBV_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
+#define LBV1_LBV_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
+#define LBV1_LBV_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
+#define LBV1_LBV_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
+#define LBV1_LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
+#define LBV1_LBV_VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
+#define LBV1_LBV_VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
+#define LBV1_LBV_VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
+#define LBV1_LBV_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
+#define LBV1_LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
+//LBV1_LBV_VLINE2_STATUS
+#define LBV1_LBV_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
+#define LBV1_LBV_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
+#define LBV1_LBV_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
+#define LBV1_LBV_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
+#define LBV1_LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
+#define LBV1_LBV_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x00000001L
+#define LBV1_LBV_VLINE2_STATUS__VLINE2_ACK_MASK 0x00000010L
+#define LBV1_LBV_VLINE2_STATUS__VLINE2_STAT_MASK 0x00001000L
+#define LBV1_LBV_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x00010000L
+#define LBV1_LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x00020000L
+//LBV1_LBV_VBLANK_STATUS
+#define LBV1_LBV_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
+#define LBV1_LBV_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
+#define LBV1_LBV_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
+#define LBV1_LBV_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
+#define LBV1_LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
+#define LBV1_LBV_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
+#define LBV1_LBV_VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
+#define LBV1_LBV_VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
+#define LBV1_LBV_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
+#define LBV1_LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
+//LBV1_LBV_SYNC_RESET_SEL
+#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
+#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
+#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
+#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
+#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
+#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
+#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0x0000FF00L
+#define LBV1_LBV_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0x00C00000L
+//LBV1_LBV_BLACK_KEYER_R_CR
+#define LBV1_LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
+#define LBV1_LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0x0000FFF0L
+//LBV1_LBV_BLACK_KEYER_G_Y
+#define LBV1_LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
+#define LBV1_LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0x0000FFF0L
+//LBV1_LBV_BLACK_KEYER_B_CB
+#define LBV1_LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
+#define LBV1_LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0x0000FFF0L
+//LBV1_LBV_KEYER_COLOR_CTRL
+#define LBV1_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
+#define LBV1_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
+#define LBV1_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x00000001L
+#define LBV1_LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x00000100L
+//LBV1_LBV_KEYER_COLOR_R_CR
+#define LBV1_LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
+#define LBV1_LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0x0000FFF0L
+//LBV1_LBV_KEYER_COLOR_G_Y
+#define LBV1_LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
+#define LBV1_LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0x0000FFF0L
+//LBV1_LBV_KEYER_COLOR_B_CB
+#define LBV1_LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
+#define LBV1_LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0x0000FFF0L
+//LBV1_LBV_KEYER_COLOR_REP_R_CR
+#define LBV1_LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
+#define LBV1_LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0x0000FFF0L
+//LBV1_LBV_KEYER_COLOR_REP_G_Y
+#define LBV1_LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
+#define LBV1_LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0x0000FFF0L
+//LBV1_LBV_KEYER_COLOR_REP_B_CB
+#define LBV1_LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
+#define LBV1_LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0x0000FFF0L
+//LBV1_LBV_BUFFER_LEVEL_STATUS
+#define LBV1_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
+#define LBV1_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
+#define LBV1_LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
+#define LBV1_LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
+#define LBV1_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x0000003FL
+#define LBV1_LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0x0000FC00L
+#define LBV1_LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0x0FFF0000L
+#define LBV1_LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xF0000000L
+//LBV1_LBV_BUFFER_URGENCY_CTRL
+#define LBV1_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
+#define LBV1_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
+#define LBV1_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0x00000FFFL
+#define LBV1_LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0x0FFF0000L
+//LBV1_LBV_BUFFER_URGENCY_STATUS
+#define LBV1_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
+#define LBV1_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
+#define LBV1_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0x00000FFFL
+#define LBV1_LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x00010000L
+//LBV1_LBV_BUFFER_STATUS
+#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
+#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
+#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
+#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
+#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
+#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
+#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
+#define LBV1_LBV_BUFFER_STATUS__LB_ENABLE_HIGH_THROUGHPUT__SHIFT 0x19
+#define LBV1_LBV_BUFFER_STATUS__LB_HIGH_THROUGHPUT_CNTL__SHIFT 0x1a
+#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0x0000000FL
+#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x00000010L
+#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x00000100L
+#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x00001000L
+#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x00010000L
+#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x00100000L
+#define LBV1_LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x01000000L
+#define LBV1_LBV_BUFFER_STATUS__LB_ENABLE_HIGH_THROUGHPUT_MASK 0x02000000L
+#define LBV1_LBV_BUFFER_STATUS__LB_HIGH_THROUGHPUT_CNTL_MASK 0x1C000000L
+//LBV1_LBV_NO_OUTSTANDING_REQ_STATUS
+#define LBV1_LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
+#define LBV1_LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_sclv1_dispdec
+//SCLV1_SCLV_COEF_RAM_SELECT
+#define SCLV1_SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define SCLV1_SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
+#define SCLV1_SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
+#define SCLV1_SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x00000003L
+#define SCLV1_SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00007F00L
+#define SCLV1_SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00030000L
+//SCLV1_SCLV_COEF_RAM_TAP_DATA
+#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+#define SCLV1_SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+//SCLV1_SCLV_MODE
+#define SCLV1_SCLV_MODE__SCL_MODE__SHIFT 0x0
+#define SCLV1_SCLV_MODE__SCL_MODE_C__SHIFT 0x2
+#define SCLV1_SCLV_MODE__SCL_PSCL_EN__SHIFT 0x4
+#define SCLV1_SCLV_MODE__SCL_PSCL_EN_C__SHIFT 0x5
+#define SCLV1_SCLV_MODE__SCL_INTERLACE_SOURCE__SHIFT 0x8
+#define SCLV1_SCLV_MODE__SCL_MODE_MASK 0x00000003L
+#define SCLV1_SCLV_MODE__SCL_MODE_C_MASK 0x0000000CL
+#define SCLV1_SCLV_MODE__SCL_PSCL_EN_MASK 0x00000010L
+#define SCLV1_SCLV_MODE__SCL_PSCL_EN_C_MASK 0x00000020L
+#define SCLV1_SCLV_MODE__SCL_INTERLACE_SOURCE_MASK 0x00000300L
+//SCLV1_SCLV_TAP_CONTROL
+#define SCLV1_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
+#define SCLV1_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x4
+#define SCLV1_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C__SHIFT 0x8
+#define SCLV1_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C__SHIFT 0xc
+#define SCLV1_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
+#define SCLV1_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000070L
+#define SCLV1_SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C_MASK 0x00000700L
+#define SCLV1_SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C_MASK 0x00007000L
+//SCLV1_SCLV_CONTROL
+#define SCLV1_SCLV_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+#define SCLV1_SCLV_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
+#define SCLV1_SCLV_CONTROL__SCL_TOTAL_PHASE__SHIFT 0x8
+#define SCLV1_SCLV_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+#define SCLV1_SCLV_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x00000010L
+#define SCLV1_SCLV_CONTROL__SCL_TOTAL_PHASE_MASK 0x00000100L
+//SCLV1_SCLV_MANUAL_REPLICATE_CONTROL
+#define SCLV1_SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+#define SCLV1_SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+#define SCLV1_SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+#define SCLV1_SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+//SCLV1_SCLV_AUTOMATIC_MODE_CONTROL
+#define SCLV1_SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
+#define SCLV1_SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
+#define SCLV1_SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x00000001L
+#define SCLV1_SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x00010000L
+//SCLV1_SCLV_HORZ_FILTER_CONTROL
+#define SCLV1_SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCLV1_SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+//SCLV1_SCLV_HORZ_FILTER_SCALE_RATIO
+#define SCLV1_SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+#define SCLV1_SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+//SCLV1_SCLV_HORZ_FILTER_INIT
+#define SCLV1_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+#define SCLV1_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+#define SCLV1_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+#define SCLV1_SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+//SCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C
+#define SCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0
+#define SCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL
+//SCLV1_SCLV_HORZ_FILTER_INIT_C
+#define SCLV1_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0
+#define SCLV1_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18
+#define SCLV1_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL
+#define SCLV1_SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L
+//SCLV1_SCLV_VERT_FILTER_CONTROL
+#define SCLV1_SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCLV1_SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00000100L
+//SCLV1_SCLV_VERT_FILTER_SCALE_RATIO
+#define SCLV1_SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+#define SCLV1_SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+//SCLV1_SCLV_VERT_FILTER_INIT
+#define SCLV1_SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+#define SCLV1_SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+#define SCLV1_SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+#define SCLV1_SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x07000000L
+//SCLV1_SCLV_VERT_FILTER_INIT_BOT
+#define SCLV1_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+#define SCLV1_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+#define SCLV1_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+#define SCLV1_SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x07000000L
+//SCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C
+#define SCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0
+#define SCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL
+//SCLV1_SCLV_VERT_FILTER_INIT_C
+#define SCLV1_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0
+#define SCLV1_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18
+#define SCLV1_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL
+#define SCLV1_SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x07000000L
+//SCLV1_SCLV_VERT_FILTER_INIT_BOT_C
+#define SCLV1_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0
+#define SCLV1_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18
+#define SCLV1_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL
+#define SCLV1_SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x07000000L
+//SCLV1_SCLV_ROUND_OFFSET
+#define SCLV1_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
+#define SCLV1_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+#define SCLV1_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0x0000FFFFL
+#define SCLV1_SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L
+//SCLV1_SCLV_UPDATE
+#define SCLV1_SCLV_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+#define SCLV1_SCLV_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
+#define SCLV1_SCLV_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
+#define SCLV1_SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
+#define SCLV1_SCLV_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+#define SCLV1_SCLV_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
+#define SCLV1_SCLV_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
+#define SCLV1_SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x01000000L
+//SCLV1_SCLV_ALU_CONTROL
+#define SCLV1_SCLV_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
+#define SCLV1_SCLV_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
+//SCLV1_SCLV_VIEWPORT_START
+#define SCLV1_SCLV_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
+#define SCLV1_SCLV_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
+#define SCLV1_SCLV_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003FFFL
+#define SCLV1_SCLV_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3FFF0000L
+//SCLV1_SCLV_VIEWPORT_START_SECONDARY
+#define SCLV1_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
+#define SCLV1_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
+#define SCLV1_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x00003FFFL
+#define SCLV1_SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3FFF0000L
+//SCLV1_SCLV_VIEWPORT_SIZE
+#define SCLV1_SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
+#define SCLV1_SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
+#define SCLV1_SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00001FFFL
+#define SCLV1_SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x1FFF0000L
+//SCLV1_SCLV_VIEWPORT_START_C
+#define SCLV1_SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C__SHIFT 0x0
+#define SCLV1_SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C__SHIFT 0x10
+#define SCLV1_SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C_MASK 0x00003FFFL
+#define SCLV1_SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C_MASK 0x3FFF0000L
+//SCLV1_SCLV_VIEWPORT_START_SECONDARY_C
+#define SCLV1_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C__SHIFT 0x0
+#define SCLV1_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C__SHIFT 0x10
+#define SCLV1_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C_MASK 0x00003FFFL
+#define SCLV1_SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C_MASK 0x3FFF0000L
+//SCLV1_SCLV_VIEWPORT_SIZE_C
+#define SCLV1_SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C__SHIFT 0x0
+#define SCLV1_SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C__SHIFT 0x10
+#define SCLV1_SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C_MASK 0x00001FFFL
+#define SCLV1_SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C_MASK 0x1FFF0000L
+//SCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT
+#define SCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+#define SCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+#define SCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+#define SCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+//SCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM
+#define SCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+#define SCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+#define SCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+#define SCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+//SCLV1_SCLV_MODE_CHANGE_DET1
+#define SCLV1_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
+#define SCLV1_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
+#define SCLV1_SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
+#define SCLV1_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
+#define SCLV1_SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
+#define SCLV1_SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0FFFFF80L
+//SCLV1_SCLV_MODE_CHANGE_DET2
+#define SCLV1_SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
+#define SCLV1_SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001FFFFFL
+//SCLV1_SCLV_MODE_CHANGE_DET3
+#define SCLV1_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
+#define SCLV1_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
+#define SCLV1_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003FFFL
+#define SCLV1_SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3FFF0000L
+//SCLV1_SCLV_MODE_CHANGE_MASK
+#define SCLV1_SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
+#define SCLV1_SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
+//SCLV1_SCLV_HORZ_FILTER_INIT_BOT
+#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT__SHIFT 0x0
+#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT__SHIFT 0x18
+#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT_MASK 0x0F000000L
+//SCLV1_SCLV_HORZ_FILTER_INIT_BOT_C
+#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C__SHIFT 0x0
+#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C__SHIFT 0x18
+#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL
+#define SCLV1_SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C_MASK 0x0F000000L
+
+
+// addressBlock: dce_dc_col_man1_dispdec
+//COL_MAN1_COL_MAN_UPDATE
+#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING__SHIFT 0x0
+#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN__SHIFT 0x1
+#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK__SHIFT 0x10
+#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING_MASK 0x00000001L
+#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN_MASK 0x00000002L
+#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK_MASK 0x00010000L
+#define COL_MAN1_COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
+//COL_MAN1_COL_MAN_INPUT_CSC_CONTROL
+#define COL_MAN1_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE__SHIFT 0x0
+#define COL_MAN1_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE__SHIFT 0x8
+#define COL_MAN1_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE__SHIFT 0x10
+#define COL_MAN1_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE_MASK 0x00000003L
+#define COL_MAN1_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE_MASK 0x00000300L
+#define COL_MAN1_COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE_MASK 0x00010000L
+//COL_MAN1_INPUT_CSC_C11_C12_A
+#define COL_MAN1_INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A__SHIFT 0x0
+#define COL_MAN1_INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A__SHIFT 0x10
+#define COL_MAN1_INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A_MASK 0x0000FFFFL
+#define COL_MAN1_INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A_MASK 0xFFFF0000L
+//COL_MAN1_INPUT_CSC_C13_C14_A
+#define COL_MAN1_INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A__SHIFT 0x0
+#define COL_MAN1_INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A__SHIFT 0x10
+#define COL_MAN1_INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A_MASK 0x0000FFFFL
+#define COL_MAN1_INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A_MASK 0xFFFF0000L
+//COL_MAN1_INPUT_CSC_C21_C22_A
+#define COL_MAN1_INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A__SHIFT 0x0
+#define COL_MAN1_INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A__SHIFT 0x10
+#define COL_MAN1_INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A_MASK 0x0000FFFFL
+#define COL_MAN1_INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A_MASK 0xFFFF0000L
+//COL_MAN1_INPUT_CSC_C23_C24_A
+#define COL_MAN1_INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A__SHIFT 0x0
+#define COL_MAN1_INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A__SHIFT 0x10
+#define COL_MAN1_INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A_MASK 0x0000FFFFL
+#define COL_MAN1_INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A_MASK 0xFFFF0000L
+//COL_MAN1_INPUT_CSC_C31_C32_A
+#define COL_MAN1_INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A__SHIFT 0x0
+#define COL_MAN1_INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A__SHIFT 0x10
+#define COL_MAN1_INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A_MASK 0x0000FFFFL
+#define COL_MAN1_INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A_MASK 0xFFFF0000L
+//COL_MAN1_INPUT_CSC_C33_C34_A
+#define COL_MAN1_INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A__SHIFT 0x0
+#define COL_MAN1_INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A__SHIFT 0x10
+#define COL_MAN1_INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A_MASK 0x0000FFFFL
+#define COL_MAN1_INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A_MASK 0xFFFF0000L
+//COL_MAN1_INPUT_CSC_C11_C12_B
+#define COL_MAN1_INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B__SHIFT 0x0
+#define COL_MAN1_INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B__SHIFT 0x10
+#define COL_MAN1_INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B_MASK 0x0000FFFFL
+#define COL_MAN1_INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B_MASK 0xFFFF0000L
+//COL_MAN1_INPUT_CSC_C13_C14_B
+#define COL_MAN1_INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B__SHIFT 0x0
+#define COL_MAN1_INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B__SHIFT 0x10
+#define COL_MAN1_INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B_MASK 0x0000FFFFL
+#define COL_MAN1_INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B_MASK 0xFFFF0000L
+//COL_MAN1_INPUT_CSC_C21_C22_B
+#define COL_MAN1_INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B__SHIFT 0x0
+#define COL_MAN1_INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B__SHIFT 0x10
+#define COL_MAN1_INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B_MASK 0x0000FFFFL
+#define COL_MAN1_INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B_MASK 0xFFFF0000L
+//COL_MAN1_INPUT_CSC_C23_C24_B
+#define COL_MAN1_INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B__SHIFT 0x0
+#define COL_MAN1_INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B__SHIFT 0x10
+#define COL_MAN1_INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B_MASK 0x0000FFFFL
+#define COL_MAN1_INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B_MASK 0xFFFF0000L
+//COL_MAN1_INPUT_CSC_C31_C32_B
+#define COL_MAN1_INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B__SHIFT 0x0
+#define COL_MAN1_INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B__SHIFT 0x10
+#define COL_MAN1_INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B_MASK 0x0000FFFFL
+#define COL_MAN1_INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B_MASK 0xFFFF0000L
+//COL_MAN1_INPUT_CSC_C33_C34_B
+#define COL_MAN1_INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B__SHIFT 0x0
+#define COL_MAN1_INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B__SHIFT 0x10
+#define COL_MAN1_INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B_MASK 0x0000FFFFL
+#define COL_MAN1_INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B_MASK 0xFFFF0000L
+//COL_MAN1_PRESCALE_CONTROL
+#define COL_MAN1_PRESCALE_CONTROL__PRESCALE_MODE__SHIFT 0x0
+#define COL_MAN1_PRESCALE_CONTROL__PRESCALE_MODE_MASK 0x00000003L
+//COL_MAN1_PRESCALE_VALUES_R
+#define COL_MAN1_PRESCALE_VALUES_R__PRESCALE_BIAS_R__SHIFT 0x0
+#define COL_MAN1_PRESCALE_VALUES_R__PRESCALE_SCALE_R__SHIFT 0x10
+#define COL_MAN1_PRESCALE_VALUES_R__PRESCALE_BIAS_R_MASK 0x0000FFFFL
+#define COL_MAN1_PRESCALE_VALUES_R__PRESCALE_SCALE_R_MASK 0xFFFF0000L
+//COL_MAN1_PRESCALE_VALUES_G
+#define COL_MAN1_PRESCALE_VALUES_G__PRESCALE_BIAS_G__SHIFT 0x0
+#define COL_MAN1_PRESCALE_VALUES_G__PRESCALE_SCALE_G__SHIFT 0x10
+#define COL_MAN1_PRESCALE_VALUES_G__PRESCALE_BIAS_G_MASK 0x0000FFFFL
+#define COL_MAN1_PRESCALE_VALUES_G__PRESCALE_SCALE_G_MASK 0xFFFF0000L
+//COL_MAN1_PRESCALE_VALUES_B
+#define COL_MAN1_PRESCALE_VALUES_B__PRESCALE_BIAS_B__SHIFT 0x0
+#define COL_MAN1_PRESCALE_VALUES_B__PRESCALE_SCALE_B__SHIFT 0x10
+#define COL_MAN1_PRESCALE_VALUES_B__PRESCALE_BIAS_B_MASK 0x0000FFFFL
+#define COL_MAN1_PRESCALE_VALUES_B__PRESCALE_SCALE_B_MASK 0xFFFF0000L
+//COL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL
+#define COL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE__SHIFT 0x0
+#define COL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE_MASK 0x00000007L
+//COL_MAN1_OUTPUT_CSC_C11_C12_A
+#define COL_MAN1_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A__SHIFT 0x0
+#define COL_MAN1_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A__SHIFT 0x10
+#define COL_MAN1_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A_MASK 0x0000FFFFL
+#define COL_MAN1_OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A_MASK 0xFFFF0000L
+//COL_MAN1_OUTPUT_CSC_C13_C14_A
+#define COL_MAN1_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A__SHIFT 0x0
+#define COL_MAN1_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A__SHIFT 0x10
+#define COL_MAN1_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A_MASK 0x0000FFFFL
+#define COL_MAN1_OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A_MASK 0xFFFF0000L
+//COL_MAN1_OUTPUT_CSC_C21_C22_A
+#define COL_MAN1_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A__SHIFT 0x0
+#define COL_MAN1_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A__SHIFT 0x10
+#define COL_MAN1_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A_MASK 0x0000FFFFL
+#define COL_MAN1_OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A_MASK 0xFFFF0000L
+//COL_MAN1_OUTPUT_CSC_C23_C24_A
+#define COL_MAN1_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A__SHIFT 0x0
+#define COL_MAN1_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A__SHIFT 0x10
+#define COL_MAN1_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A_MASK 0x0000FFFFL
+#define COL_MAN1_OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A_MASK 0xFFFF0000L
+//COL_MAN1_OUTPUT_CSC_C31_C32_A
+#define COL_MAN1_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A__SHIFT 0x0
+#define COL_MAN1_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A__SHIFT 0x10
+#define COL_MAN1_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A_MASK 0x0000FFFFL
+#define COL_MAN1_OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A_MASK 0xFFFF0000L
+//COL_MAN1_OUTPUT_CSC_C33_C34_A
+#define COL_MAN1_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A__SHIFT 0x0
+#define COL_MAN1_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A__SHIFT 0x10
+#define COL_MAN1_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A_MASK 0x0000FFFFL
+#define COL_MAN1_OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A_MASK 0xFFFF0000L
+//COL_MAN1_OUTPUT_CSC_C11_C12_B
+#define COL_MAN1_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B__SHIFT 0x0
+#define COL_MAN1_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B__SHIFT 0x10
+#define COL_MAN1_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B_MASK 0x0000FFFFL
+#define COL_MAN1_OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B_MASK 0xFFFF0000L
+//COL_MAN1_OUTPUT_CSC_C13_C14_B
+#define COL_MAN1_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B__SHIFT 0x0
+#define COL_MAN1_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B__SHIFT 0x10
+#define COL_MAN1_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B_MASK 0x0000FFFFL
+#define COL_MAN1_OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B_MASK 0xFFFF0000L
+//COL_MAN1_OUTPUT_CSC_C21_C22_B
+#define COL_MAN1_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B__SHIFT 0x0
+#define COL_MAN1_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B__SHIFT 0x10
+#define COL_MAN1_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B_MASK 0x0000FFFFL
+#define COL_MAN1_OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B_MASK 0xFFFF0000L
+//COL_MAN1_OUTPUT_CSC_C23_C24_B
+#define COL_MAN1_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B__SHIFT 0x0
+#define COL_MAN1_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B__SHIFT 0x10
+#define COL_MAN1_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B_MASK 0x0000FFFFL
+#define COL_MAN1_OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B_MASK 0xFFFF0000L
+//COL_MAN1_OUTPUT_CSC_C31_C32_B
+#define COL_MAN1_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B__SHIFT 0x0
+#define COL_MAN1_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B__SHIFT 0x10
+#define COL_MAN1_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B_MASK 0x0000FFFFL
+#define COL_MAN1_OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B_MASK 0xFFFF0000L
+//COL_MAN1_OUTPUT_CSC_C33_C34_B
+#define COL_MAN1_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B__SHIFT 0x0
+#define COL_MAN1_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B__SHIFT 0x10
+#define COL_MAN1_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B_MASK 0x0000FFFFL
+#define COL_MAN1_OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B_MASK 0xFFFF0000L
+//COL_MAN1_DENORM_CLAMP_CONTROL
+#define COL_MAN1_DENORM_CLAMP_CONTROL__DENORM_MODE__SHIFT 0x0
+#define COL_MAN1_DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT__SHIFT 0x8
+#define COL_MAN1_DENORM_CLAMP_CONTROL__DENORM_MODE_MASK 0x00000003L
+#define COL_MAN1_DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT_MASK 0x00000100L
+//COL_MAN1_DENORM_CLAMP_RANGE_R_CR
+#define COL_MAN1_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR__SHIFT 0x0
+#define COL_MAN1_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR__SHIFT 0xc
+#define COL_MAN1_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR_MASK 0x00000FFFL
+#define COL_MAN1_DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR_MASK 0x00FFF000L
+//COL_MAN1_DENORM_CLAMP_RANGE_G_Y
+#define COL_MAN1_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y__SHIFT 0x0
+#define COL_MAN1_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y__SHIFT 0xc
+#define COL_MAN1_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y_MASK 0x00000FFFL
+#define COL_MAN1_DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y_MASK 0x00FFF000L
+//COL_MAN1_DENORM_CLAMP_RANGE_B_CB
+#define COL_MAN1_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB__SHIFT 0x0
+#define COL_MAN1_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB__SHIFT 0xc
+#define COL_MAN1_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB_MASK 0x00000FFFL
+#define COL_MAN1_DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB_MASK 0x00FFF000L
+//COL_MAN1_COL_MAN_FP_CONVERTED_FIELD
+#define COL_MAN1_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
+#define COL_MAN1_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
+#define COL_MAN1_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA_MASK 0x0003FFFFL
+#define COL_MAN1_COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX_MASK 0x07F00000L
+//COL_MAN1_COL_MAN_REGAMMA_CONTROL
+#define COL_MAN1_COL_MAN_REGAMMA_CONTROL__COL_MAN_REGAMMA_MODE__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CONTROL__COL_MAN_REGAMMA_MODE_MASK 0x00000007L
+//COL_MAN1_COL_MAN_REGAMMA_LUT_INDEX
+#define COL_MAN1_COL_MAN_REGAMMA_LUT_INDEX__COL_MAN_REGAMMA_LUT_INDEX__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_LUT_INDEX__COL_MAN_REGAMMA_LUT_INDEX_MASK 0x000001FFL
+//COL_MAN1_COL_MAN_REGAMMA_LUT_DATA
+#define COL_MAN1_COL_MAN_REGAMMA_LUT_DATA__COL_MAN_REGAMMA_LUT_DATA__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_LUT_DATA__COL_MAN_REGAMMA_LUT_DATA_MASK 0x0007FFFFL
+//COL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK
+#define COL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK__COL_MAN_REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK__COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
+//COL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003FFFFL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+//COL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+//COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000FFFFL
+//COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2__COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1__COL_MAN_REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3__COL_MAN_REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5__COL_MAN_REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7__COL_MAN_REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9__COL_MAN_REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11__COL_MAN_REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13__COL_MAN_REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15__COL_MAN_REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003FFFFL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07F00000L
+//COL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL__COL_MAN_REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003FFFFL
+//COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000FFFFL
+//COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000FFFFL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2__COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xFFFF0000L
+//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1__COL_MAN_REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3__COL_MAN_REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5__COL_MAN_REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7__COL_MAN_REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9__COL_MAN_REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11__COL_MAN_REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13__COL_MAN_REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00003800L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x00FF8000L
+#define COL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15__COL_MAN_REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000L
+//COL_MAN1_PACK_FIFO_ERROR
+#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED__SHIFT 0x0
+#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK__SHIFT 0x1
+#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED__SHIFT 0x8
+#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK__SHIFT 0x9
+#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED__SHIFT 0x10
+#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK__SHIFT 0x11
+#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED__SHIFT 0x18
+#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK__SHIFT 0x19
+#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED_MASK 0x00000001L
+#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK_MASK 0x00000002L
+#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED_MASK 0x00000100L
+#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK_MASK 0x00000200L
+#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED_MASK 0x00010000L
+#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK_MASK 0x00020000L
+#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED_MASK 0x01000000L
+#define COL_MAN1_PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK_MASK 0x02000000L
+//COL_MAN1_OUTPUT_FIFO_ERROR
+#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED__SHIFT 0x0
+#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK__SHIFT 0x1
+#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED__SHIFT 0x8
+#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK__SHIFT 0x9
+#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED_MASK 0x00000001L
+#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK_MASK 0x00000002L
+#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED_MASK 0x00000100L
+#define COL_MAN1_OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK_MASK 0x00000200L
+//COL_MAN1_INPUT_GAMMA_LUT_AUTOFILL
+#define COL_MAN1_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL__SHIFT 0x0
+#define COL_MAN1_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE__SHIFT 0x1
+#define COL_MAN1_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_MASK 0x00000001L
+#define COL_MAN1_INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE_MASK 0x00000002L
+//COL_MAN1_INPUT_GAMMA_LUT_RW_INDEX
+#define COL_MAN1_INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX__SHIFT 0x0
+#define COL_MAN1_INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX_MASK 0x000000FFL
+//COL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR
+#define COL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR__SHIFT 0x0
+#define COL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR_MASK 0x0000FFFFL
+//COL_MAN1_INPUT_GAMMA_LUT_PWL_DATA
+#define COL_MAN1_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE__SHIFT 0x0
+#define COL_MAN1_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA__SHIFT 0x10
+#define COL_MAN1_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE_MASK 0x0000FFFFL
+#define COL_MAN1_INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA_MASK 0xFFFF0000L
+//COL_MAN1_INPUT_GAMMA_LUT_30_COLOR
+#define COL_MAN1_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE__SHIFT 0x0
+#define COL_MAN1_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN__SHIFT 0xa
+#define COL_MAN1_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED__SHIFT 0x14
+#define COL_MAN1_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE_MASK 0x000003FFL
+#define COL_MAN1_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN_MASK 0x000FFC00L
+#define COL_MAN1_INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED_MASK 0x3FF00000L
+//COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE__SHIFT 0x0
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN__SHIFT 0x1a
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE_MASK 0x00000003L
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN_MASK 0x04000000L
+//COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B__SHIFT 0x1
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN__SHIFT 0x5
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT__SHIFT 0x6
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G__SHIFT 0x8
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN__SHIFT 0xc
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT__SHIFT 0xd
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R__SHIFT 0xf
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN__SHIFT 0x13
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT__SHIFT 0x14
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE__SHIFT 0x16
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK__SHIFT 0x17
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE__SHIFT 0x1a
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x1b
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B_MASK 0x0000001EL
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN_MASK 0x00000020L
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT_MASK 0x000000C0L
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G_MASK 0x00000F00L
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN_MASK 0x00001000L
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT_MASK 0x00006000L
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R_MASK 0x00078000L
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN_MASK 0x00080000L
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT_MASK 0x00300000L
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE_MASK 0x00400000L
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK_MASK 0x03800000L
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE_MASK 0x04000000L
+#define COL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x08000000L
+//COL_MAN1_INPUT_GAMMA_BW_OFFSETS_B
+#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B__SHIFT 0x0
+#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B__SHIFT 0x10
+#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B_MASK 0x0000FFFFL
+#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B_MASK 0xFFFF0000L
+//COL_MAN1_INPUT_GAMMA_BW_OFFSETS_G
+#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G__SHIFT 0x0
+#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G__SHIFT 0x10
+#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G_MASK 0x0000FFFFL
+#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G_MASK 0xFFFF0000L
+//COL_MAN1_INPUT_GAMMA_BW_OFFSETS_R
+#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R__SHIFT 0x0
+#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R__SHIFT 0x10
+#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R_MASK 0x0000FFFFL
+#define COL_MAN1_INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R_MASK 0xFFFF0000L
+//COL_MAN1_COL_MAN_DEGAMMA_CONTROL
+#define COL_MAN1_COL_MAN_DEGAMMA_CONTROL__COL_MAN_DEGAMMA_MODE__SHIFT 0x0
+#define COL_MAN1_COL_MAN_DEGAMMA_CONTROL__COL_MAN_DEGAMMA_MODE_MASK 0x00000003L
+//COL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL__COL_MAN_GAMUT_REMAP_MODE__SHIFT 0x0
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL__COL_MAN_GAMUT_REMAP_MODE_MASK 0x00000003L
+//COL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C11__SHIFT 0x0
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C12__SHIFT 0x10
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C11_MASK 0x0000FFFFL
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12__COL_MAN_GAMUT_REMAP_C12_MASK 0xFFFF0000L
+//COL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C13__SHIFT 0x0
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C14__SHIFT 0x10
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C13_MASK 0x0000FFFFL
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14__COL_MAN_GAMUT_REMAP_C14_MASK 0xFFFF0000L
+//COL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C21__SHIFT 0x0
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C22__SHIFT 0x10
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C21_MASK 0x0000FFFFL
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22__COL_MAN_GAMUT_REMAP_C22_MASK 0xFFFF0000L
+//COL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C23__SHIFT 0x0
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C24__SHIFT 0x10
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C23_MASK 0x0000FFFFL
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24__COL_MAN_GAMUT_REMAP_C24_MASK 0xFFFF0000L
+//COL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C31__SHIFT 0x0
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C32__SHIFT 0x10
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C31_MASK 0x0000FFFFL
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32__COL_MAN_GAMUT_REMAP_C32_MASK 0xFFFF0000L
+//COL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C33__SHIFT 0x0
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C34__SHIFT 0x10
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C33_MASK 0x0000FFFFL
+#define COL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34__COL_MAN_GAMUT_REMAP_C34_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dcfev1_dispdec
+//DCFEV1_DCFEV_CLOCK_CONTROL
+#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE__SHIFT 0x3
+#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE__SHIFT 0x7
+#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE__SHIFT 0x9
+#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE__SHIFT 0xb
+#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE__SHIFT 0xd
+#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE__SHIFT 0xf
+#define DCFEV1_DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL__SHIFT 0x18
+#define DCFEV1_DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE__SHIFT 0x1f
+#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE_MASK 0x00000008L
+#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE_MASK 0x00000080L
+#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE_MASK 0x00000200L
+#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE_MASK 0x00000800L
+#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE_MASK 0x00002000L
+#define DCFEV1_DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE_MASK 0x00008000L
+#define DCFEV1_DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL_MASK 0x1F000000L
+#define DCFEV1_DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE_MASK 0x80000000L
+//DCFEV1_DCFEV_SOFT_RESET
+#define DCFEV1_DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET__SHIFT 0x0
+#define DCFEV1_DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET__SHIFT 0x1
+#define DCFEV1_DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET__SHIFT 0x2
+#define DCFEV1_DCFEV_SOFT_RESET__SCLV_SOFT_RESET__SHIFT 0x3
+#define DCFEV1_DCFEV_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
+#define DCFEV1_DCFEV_SOFT_RESET__PSCLV_SOFT_RESET__SHIFT 0x5
+#define DCFEV1_DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET__SHIFT 0x6
+#define DCFEV1_DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET_MASK 0x00000001L
+#define DCFEV1_DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET_MASK 0x00000002L
+#define DCFEV1_DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET_MASK 0x00000004L
+#define DCFEV1_DCFEV_SOFT_RESET__SCLV_SOFT_RESET_MASK 0x00000008L
+#define DCFEV1_DCFEV_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x00000010L
+#define DCFEV1_DCFEV_SOFT_RESET__PSCLV_SOFT_RESET_MASK 0x00000020L
+#define DCFEV1_DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET_MASK 0x00000040L
+//DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL
+#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x3
+#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS__SHIFT 0x4
+#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS__SHIFT 0x5
+#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET__SHIFT 0x6
+#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL__SHIFT 0x18
+#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE__SHIFT 0x1f
+#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS_MASK 0x00000008L
+#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS_MASK 0x00000010L
+#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS_MASK 0x00000020L
+#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET_MASK 0x00000040L
+#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL_MASK 0x1F000000L
+#define DCFEV1_DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE_MASK 0x80000000L
+//DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL__SHIFT 0x0
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE__SHIFT 0x2
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE__SHIFT 0x3
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE__SHIFT 0x4
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE__SHIFT 0x5
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE__SHIFT 0x6
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE__SHIFT 0x7
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE__SHIFT 0x8
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE__SHIFT 0x9
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE__SHIFT 0xa
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE__SHIFT 0xb
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL_MASK 0x00000003L
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE_MASK 0x00000004L
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE_MASK 0x00000008L
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE_MASK 0x00000010L
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE_MASK 0x00000020L
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE_MASK 0x00000040L
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE_MASK 0x00000080L
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE_MASK 0x00000100L
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE_MASK 0x00000200L
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE_MASK 0x00000400L
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE_MASK 0x00000800L
+//DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE__SHIFT 0x0
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE__SHIFT 0x2
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE__SHIFT 0x4
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE__SHIFT 0x6
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE__SHIFT 0x8
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE__SHIFT 0xa
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE__SHIFT 0xc
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE__SHIFT 0xe
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE__SHIFT 0x10
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE__SHIFT 0x12
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE_MASK 0x00000003L
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE_MASK 0x0000000CL
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE_MASK 0x00000030L
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE_MASK 0x000000C0L
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE_MASK 0x00000300L
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE_MASK 0x00000C00L
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE_MASK 0x00003000L
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE_MASK 0x0000C000L
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE_MASK 0x00030000L
+#define DCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE_MASK 0x000C0000L
+//DCFEV1_DCFEV_MEM_PWR_CTRL
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_FORCE__SHIFT 0x0
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_DIS__SHIFT 0x2
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE__SHIFT 0x3
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS__SHIFT 0x5
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE__SHIFT 0x6
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS__SHIFT 0x8
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE__SHIFT 0x9
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS__SHIFT 0xb
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE__SHIFT 0xc
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS__SHIFT 0xe
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE__SHIFT 0xf
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS__SHIFT 0x11
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_FORCE_MASK 0x00000003L
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_REGAMMA_MEM_PWR_DIS_MASK 0x00000004L
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE_MASK 0x00000018L
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS_MASK 0x00000020L
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE_MASK 0x000000C0L
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS_MASK 0x00000100L
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE_MASK 0x00000600L
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS_MASK 0x00000800L
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE_MASK 0x00003000L
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS_MASK 0x00004000L
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE_MASK 0x00018000L
+#define DCFEV1_DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS_MASK 0x00020000L
+//DCFEV1_DCFEV_MEM_PWR_CTRL2
+#define DCFEV1_DCFEV_MEM_PWR_CTRL2__COL_MAN_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x0
+#define DCFEV1_DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
+#define DCFEV1_DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
+#define DCFEV1_DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL__SHIFT 0x6
+#define DCFEV1_DCFEV_MEM_PWR_CTRL2__COL_MAN_REGAMMA_MEM_PWR_MODE_SEL_MASK 0x00000003L
+#define DCFEV1_DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL_MASK 0x0000000CL
+#define DCFEV1_DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL_MASK 0x00000030L
+#define DCFEV1_DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL_MASK 0x000000C0L
+//DCFEV1_DCFEV_MEM_PWR_STATUS
+#define DCFEV1_DCFEV_MEM_PWR_STATUS__COL_MAN_REGAMMA_MEM_PWR_STATE__SHIFT 0x0
+#define DCFEV1_DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE__SHIFT 0x2
+#define DCFEV1_DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE__SHIFT 0x4
+#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE__SHIFT 0x6
+#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE__SHIFT 0x8
+#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE__SHIFT 0xa
+#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE__SHIFT 0xc
+#define DCFEV1_DCFEV_MEM_PWR_STATUS__COL_MAN_REGAMMA_MEM_PWR_STATE_MASK 0x00000003L
+#define DCFEV1_DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE_MASK 0x0000000CL
+#define DCFEV1_DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE_MASK 0x00000030L
+#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE_MASK 0x000000C0L
+#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE_MASK 0x00000300L
+#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE_MASK 0x00000C00L
+#define DCFEV1_DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE_MASK 0x00003000L
+//DCFEV1_DCFEV_L_FLUSH
+#define DCFEV1_DCFEV_L_FLUSH__FLUSH_OCCURED__SHIFT 0x0
+#define DCFEV1_DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
+#define DCFEV1_DCFEV_L_FLUSH__FLUSH_DEEP__SHIFT 0x2
+#define DCFEV1_DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
+#define DCFEV1_DCFEV_L_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
+#define DCFEV1_DCFEV_L_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
+#define DCFEV1_DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
+#define DCFEV1_DCFEV_L_FLUSH__FLUSH_DEEP_MASK 0x00000004L
+#define DCFEV1_DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
+#define DCFEV1_DCFEV_L_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
+//DCFEV1_DCFEV_C_FLUSH
+#define DCFEV1_DCFEV_C_FLUSH__FLUSH_OCCURED__SHIFT 0x0
+#define DCFEV1_DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
+#define DCFEV1_DCFEV_C_FLUSH__FLUSH_DEEP__SHIFT 0x2
+#define DCFEV1_DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
+#define DCFEV1_DCFEV_C_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
+#define DCFEV1_DCFEV_C_FLUSH__FLUSH_OCCURED_MASK 0x00000001L
+#define DCFEV1_DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x00000002L
+#define DCFEV1_DCFEV_C_FLUSH__FLUSH_DEEP_MASK 0x00000004L
+#define DCFEV1_DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x00000008L
+#define DCFEV1_DCFEV_C_FLUSH__ALL_MC_REQ_RET_MASK 0x00000010L
+//DCFEV1_DCFEV_MISC
+#define DCFEV1_DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
+#define DCFEV1_DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_dc_perfmon12_dispdec
+//DC_PERFMON12_PERFCOUNTER_CNTL
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON12_PERFCOUNTER_CNTL2
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON12_PERFCOUNTER_STATE
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON12_PERFMON_CNTL
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON12_PERFMON_CNTL2
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON12_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON12_PERFMON_CVALUE_LOW
+#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON12_PERFMON_HI
+#define DC_PERFMON12_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON12_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON12_PERFMON_LOW
+#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dmifv_pg1_dispdec
+//DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1
+#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
+#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
+//DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2
+#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
+#define DMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
+//DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL
+#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
+#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18
+#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000003L
+#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000300L
+#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00030000L
+#define DMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x01000000L
+//DMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL
+#define DMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+#define DMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+#define DMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
+#define DMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
+//DMIFV_PG1_DPGV0_PIPE_DPM_CONTROL
+#define DMIFV_PG1_DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
+#define DMIFV_PG1_DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L
+//DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x00000100L
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x00000200L
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
+//DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL
+#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
+#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
+#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x00000001L
+#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
+#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
+#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
+#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
+#define DMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xFFFF0000L
+//DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00000010L
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00000020L
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00000040L
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00000080L
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x00000100L
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x00000200L
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x00000400L
+#define DMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x00000800L
+//DMIFV_PG1_DPGV0_REPEATER_PROGRAM
+#define DMIFV_PG1_DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+#define DMIFV_PG1_DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+#define DMIFV_PG1_DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
+#define DMIFV_PG1_DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
+//DMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL
+#define DMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+#define DMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
+//DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1
+#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000FFFFL
+#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xFFFF0000L
+//DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2
+#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000FFFFL
+#define DMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xFFFF0000L
+//DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL
+#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
+#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18
+#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00000003L
+#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x00000300L
+#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00030000L
+#define DMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x01000000L
+//DMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL
+#define DMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+#define DMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+#define DMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000FFFFL
+#define DMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xFFFF0000L
+//DMIFV_PG1_DPGV1_PIPE_DPM_CONTROL
+#define DMIFV_PG1_DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
+#define DMIFV_PG1_DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L
+//DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x00000100L
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x00000200L
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xFFFF0000L
+//DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL
+#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
+#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
+#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x00000001L
+#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
+#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
+#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
+#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
+#define DMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xFFFF0000L
+//DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00000010L
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00000020L
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00000040L
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00000080L
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x00000100L
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x00000200L
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x00000400L
+#define DMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x00000800L
+//DMIFV_PG1_DPGV1_REPEATER_PROGRAM
+#define DMIFV_PG1_DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+#define DMIFV_PG1_DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+#define DMIFV_PG1_DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x00000007L
+#define DMIFV_PG1_DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x00000070L
+//DMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL
+#define DMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+#define DMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_blndv1_dispdec
+//BLNDV1_BLNDV_CONTROL
+#define BLNDV1_BLNDV_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
+#define BLNDV1_BLNDV_CONTROL__BLND_MODE__SHIFT 0x8
+#define BLNDV1_BLNDV_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
+#define BLNDV1_BLNDV_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
+#define BLNDV1_BLNDV_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
+#define BLNDV1_BLNDV_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
+#define BLNDV1_BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
+#define BLNDV1_BLNDV_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
+#define BLNDV1_BLNDV_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
+#define BLNDV1_BLNDV_CONTROL__BLND_GLOBAL_GAIN_MASK 0x000000FFL
+#define BLNDV1_BLNDV_CONTROL__BLND_MODE_MASK 0x00000300L
+#define BLNDV1_BLNDV_CONTROL__BLND_STEREO_TYPE_MASK 0x00000C00L
+#define BLNDV1_BLNDV_CONTROL__BLND_STEREO_POLARITY_MASK 0x00001000L
+#define BLNDV1_BLNDV_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x00002000L
+#define BLNDV1_BLNDV_CONTROL__BLND_ALPHA_MODE_MASK 0x00030000L
+#define BLNDV1_BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00040000L
+#define BLNDV1_BLNDV_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x00100000L
+#define BLNDV1_BLNDV_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xFF000000L
+//BLNDV1_BLNDV_SM_CONTROL2
+#define BLNDV1_BLNDV_SM_CONTROL2__SM_MODE__SHIFT 0x0
+#define BLNDV1_BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
+#define BLNDV1_BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
+#define BLNDV1_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+#define BLNDV1_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+#define BLNDV1_BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
+#define BLNDV1_BLNDV_SM_CONTROL2__SM_MODE_MASK 0x00000007L
+#define BLNDV1_BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x00000010L
+#define BLNDV1_BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x00000020L
+#define BLNDV1_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+#define BLNDV1_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+#define BLNDV1_BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x01000000L
+//BLNDV1_BLNDV_CONTROL2
+#define BLNDV1_BLNDV_CONTROL2__PTI_ENABLE__SHIFT 0x0
+#define BLNDV1_BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
+#define BLNDV1_BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
+#define BLNDV1_BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
+#define BLNDV1_BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
+#define BLNDV1_BLNDV_CONTROL2__PTI_ENABLE_MASK 0x00000001L
+#define BLNDV1_BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x00000030L
+#define BLNDV1_BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x00000040L
+#define BLNDV1_BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x00000080L
+#define BLNDV1_BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x00000100L
+//BLNDV1_BLNDV_UPDATE
+#define BLNDV1_BLNDV_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
+#define BLNDV1_BLNDV_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
+#define BLNDV1_BLNDV_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
+#define BLNDV1_BLNDV_UPDATE__BLND_UPDATE_PENDING_MASK 0x00000001L
+#define BLNDV1_BLNDV_UPDATE__BLND_UPDATE_TAKEN_MASK 0x00000100L
+#define BLNDV1_BLNDV_UPDATE__BLND_UPDATE_LOCK_MASK 0x00010000L
+//BLNDV1_BLNDV_UNDERFLOW_INTERRUPT
+#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
+#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
+#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
+#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
+#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x00000001L
+#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x00000100L
+#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x00001000L
+#define BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x00030000L
+//BLNDV1_BLNDV_V_UPDATE_LOCK
+#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
+#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
+#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
+#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
+#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
+#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
+#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x00000001L
+#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x00000002L
+#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x00010000L
+#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000L
+#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000L
+#define BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000L
+//BLNDV1_BLNDV_REG_UPDATE_STATUS
+#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
+#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
+#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
+#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
+#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
+#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
+#define BLNDV1_BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
+#define BLNDV1_BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
+#define BLNDV1_BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
+#define BLNDV1_BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
+#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x00000001L
+#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x00000002L
+#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x00000004L
+#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x00000008L
+#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x00000040L
+#define BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x00000080L
+#define BLNDV1_BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x00000100L
+#define BLNDV1_BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x00000200L
+#define BLNDV1_BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x00000400L
+#define BLNDV1_BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x00000800L
+
+
+// addressBlock: dce_dc_crtcv1_dispdec
+//CRTCV1_CRTCV_H_BLANK_EARLY_NUM
+#define CRTCV1_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
+#define CRTCV1_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
+#define CRTCV1_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003FFL
+#define CRTCV1_CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
+//CRTCV1_CRTCV_H_TOTAL
+#define CRTCV1_CRTCV_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
+#define CRTCV1_CRTCV_H_TOTAL__CRTC_H_TOTAL_MASK 0x00003FFFL
+//CRTCV1_CRTCV_H_BLANK_START_END
+#define CRTCV1_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
+#define CRTCV1_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
+#define CRTCV1_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_H_SYNC_A
+#define CRTCV1_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
+#define CRTCV1_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
+#define CRTCV1_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_H_SYNC_A_CNTL
+#define CRTCV1_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
+#define CRTCV1_CRTCV_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
+#define CRTCV1_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
+#define CRTCV1_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
+#define CRTCV1_CRTCV_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
+#define CRTCV1_CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
+//CRTCV1_CRTCV_H_SYNC_B
+#define CRTCV1_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
+#define CRTCV1_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
+#define CRTCV1_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_H_SYNC_B_CNTL
+#define CRTCV1_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
+#define CRTCV1_CRTCV_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
+#define CRTCV1_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
+#define CRTCV1_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
+#define CRTCV1_CRTCV_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
+#define CRTCV1_CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
+//CRTCV1_CRTCV_VBI_END
+#define CRTCV1_CRTCV_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
+#define CRTCV1_CRTCV_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
+#define CRTCV1_CRTCV_VBI_END__CRTC_VBI_V_END_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_VBI_END__CRTC_VBI_H_END_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_V_TOTAL
+#define CRTCV1_CRTCV_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
+#define CRTCV1_CRTCV_V_TOTAL__CRTC_V_TOTAL_MASK 0x00003FFFL
+//CRTCV1_CRTCV_V_TOTAL_MIN
+#define CRTCV1_CRTCV_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
+#define CRTCV1_CRTCV_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00003FFFL
+//CRTCV1_CRTCV_V_TOTAL_MAX
+#define CRTCV1_CRTCV_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
+#define CRTCV1_CRTCV_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
+#define CRTCV1_CRTCV_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
+//CRTCV1_CRTCV_V_TOTAL_CONTROL
+#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
+#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
+#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
+#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
+#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
+#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
+#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
+#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
+#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
+#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00008000L
+#define CRTCV1_CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+//CRTCV1_CRTCV_V_TOTAL_INT_STATUS
+#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+#define CRTCV1_CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+//CRTCV1_CRTCV_VSYNC_NOM_INT_STATUS
+#define CRTCV1_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
+#define CRTCV1_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+#define CRTCV1_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
+#define CRTCV1_CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+//CRTCV1_CRTCV_V_BLANK_START_END
+#define CRTCV1_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
+#define CRTCV1_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
+#define CRTCV1_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_V_SYNC_A
+#define CRTCV1_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
+#define CRTCV1_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
+#define CRTCV1_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_V_SYNC_A_CNTL
+#define CRTCV1_CRTCV_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
+#define CRTCV1_CRTCV_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
+//CRTCV1_CRTCV_V_SYNC_B
+#define CRTCV1_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
+#define CRTCV1_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
+#define CRTCV1_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_V_SYNC_B_CNTL
+#define CRTCV1_CRTCV_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
+#define CRTCV1_CRTCV_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
+//CRTCV1_CRTCV_DTMTEST_CNTL
+#define CRTCV1_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
+#define CRTCV1_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
+#define CRTCV1_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
+#define CRTCV1_CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001EL
+//CRTCV1_CRTCV_DTMTEST_STATUS_POSITION
+#define CRTCV1_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
+#define CRTCV1_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
+#define CRTCV1_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_TRIGA_CNTL
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000E0L
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1F000000L
+#define CRTCV1_CRTCV_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
+//CRTCV1_CRTCV_TRIGA_MANUAL_TRIG
+#define CRTCV1_CRTCV_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
+#define CRTCV1_CRTCV_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+//CRTCV1_CRTCV_TRIGB_CNTL
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000E0L
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1F000000L
+#define CRTCV1_CRTCV_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
+//CRTCV1_CRTCV_TRIGB_MANUAL_TRIG
+#define CRTCV1_CRTCV_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
+#define CRTCV1_CRTCV_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+//CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL
+#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+#define CRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+//CRTCV1_CRTCV_FLOW_CONTROL
+#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
+#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+#define CRTCV1_CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+//CRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE
+#define CRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+#define CRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+#define CRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
+#define CRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+#define CRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+#define CRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+//CRTCV1_CRTCV_AVSYNC_COUNTER
+#define CRTCV1_CRTCV_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
+#define CRTCV1_CRTCV_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xFFFFFFFFL
+//CRTCV1_CRTCV_CONTROL
+#define CRTCV1_CRTCV_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTCV1_CRTCV_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
+#define CRTCV1_CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
+#define CRTCV1_CRTCV_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
+#define CRTCV1_CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
+#define CRTCV1_CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
+#define CRTCV1_CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+#define CRTCV1_CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
+#define CRTCV1_CRTCV_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
+#define CRTCV1_CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+#define CRTCV1_CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+#define CRTCV1_CRTCV_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
+#define CRTCV1_CRTCV_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
+#define CRTCV1_CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
+#define CRTCV1_CRTCV_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
+#define CRTCV1_CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
+#define CRTCV1_CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+#define CRTCV1_CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+#define CRTCV1_CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
+#define CRTCV1_CRTCV_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
+#define CRTCV1_CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+#define CRTCV1_CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+//CRTCV1_CRTCV_BLANK_CONTROL
+#define CRTCV1_CRTCV_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
+#define CRTCV1_CRTCV_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
+#define CRTCV1_CRTCV_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
+#define CRTCV1_CRTCV_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
+#define CRTCV1_CRTCV_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
+#define CRTCV1_CRTCV_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
+//CRTCV1_CRTCV_INTERLACE_CONTROL
+#define CRTCV1_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
+#define CRTCV1_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+#define CRTCV1_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
+#define CRTCV1_CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+//CRTCV1_CRTCV_INTERLACE_STATUS
+#define CRTCV1_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+#define CRTCV1_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
+#define CRTCV1_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+#define CRTCV1_CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+//CRTCV1_CRTCV_FIELD_INDICATION_CONTROL
+#define CRTCV1_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
+#define CRTCV1_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
+#define CRTCV1_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L
+#define CRTCV1_CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x00000002L
+//CRTCV1_CRTCV_PIXEL_DATA_READBACK0
+#define CRTCV1_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+#define CRTCV1_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+#define CRTCV1_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0x00000FFFL
+#define CRTCV1_CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0x0FFF0000L
+//CRTCV1_CRTCV_PIXEL_DATA_READBACK1
+#define CRTCV1_CRTCV_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
+#define CRTCV1_CRTCV_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0x00000FFFL
+//CRTCV1_CRTCV_STATUS
+#define CRTCV1_CRTCV_STATUS__CRTC_V_BLANK__SHIFT 0x0
+#define CRTCV1_CRTCV_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
+#define CRTCV1_CRTCV_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
+#define CRTCV1_CRTCV_STATUS__CRTC_V_UPDATE__SHIFT 0x3
+#define CRTCV1_CRTCV_STATUS__CRTC_V_START_LINE__SHIFT 0x4
+#define CRTCV1_CRTCV_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+#define CRTCV1_CRTCV_STATUS__CRTC_H_BLANK__SHIFT 0x10
+#define CRTCV1_CRTCV_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
+#define CRTCV1_CRTCV_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
+#define CRTCV1_CRTCV_STATUS__CRTC_V_BLANK_MASK 0x00000001L
+#define CRTCV1_CRTCV_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
+#define CRTCV1_CRTCV_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
+#define CRTCV1_CRTCV_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
+#define CRTCV1_CRTCV_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
+#define CRTCV1_CRTCV_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+#define CRTCV1_CRTCV_STATUS__CRTC_H_BLANK_MASK 0x00010000L
+#define CRTCV1_CRTCV_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
+#define CRTCV1_CRTCV_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
+//CRTCV1_CRTCV_STATUS_POSITION
+#define CRTCV1_CRTCV_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
+#define CRTCV1_CRTCV_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
+#define CRTCV1_CRTCV_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_NOM_VERT_POSITION
+#define CRTCV1_CRTCV_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
+#define CRTCV1_CRTCV_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00003FFFL
+//CRTCV1_CRTCV_STATUS_FRAME_COUNT
+#define CRTCV1_CRTCV_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
+#define CRTCV1_CRTCV_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00FFFFFFL
+//CRTCV1_CRTCV_STATUS_VF_COUNT
+#define CRTCV1_CRTCV_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
+#define CRTCV1_CRTCV_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3FFFFFFFL
+//CRTCV1_CRTCV_STATUS_HV_COUNT
+#define CRTCV1_CRTCV_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
+#define CRTCV1_CRTCV_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3FFFFFFFL
+//CRTCV1_CRTCV_COUNT_CONTROL
+#define CRTCV1_CRTCV_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
+#define CRTCV1_CRTCV_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
+#define CRTCV1_CRTCV_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+#define CRTCV1_CRTCV_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+//CRTCV1_CRTCV_COUNT_RESET
+#define CRTCV1_CRTCV_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
+#define CRTCV1_CRTCV_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
+//CRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define CRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+#define CRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+//CRTCV1_CRTCV_VERT_SYNC_CONTROL
+#define CRTCV1_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+#define CRTCV1_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+#define CRTCV1_CRTCV_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+#define CRTCV1_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+#define CRTCV1_CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+#define CRTCV1_CRTCV_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+//CRTCV1_CRTCV_STEREO_STATUS
+#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
+#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
+#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
+#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
+#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
+#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
+#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x00100000L
+#define CRTCV1_CRTCV_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+//CRTCV1_CRTCV_STEREO_CONTROL
+#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
+#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
+#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
+#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
+#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x00080000L
+#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+#define CRTCV1_CRTCV_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
+//CRTCV1_CRTCV_SNAPSHOT_STATUS
+#define CRTCV1_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
+#define CRTCV1_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
+#define CRTCV1_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+#define CRTCV1_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
+#define CRTCV1_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
+#define CRTCV1_CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+//CRTCV1_CRTCV_SNAPSHOT_CONTROL
+#define CRTCV1_CRTCV_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+#define CRTCV1_CRTCV_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+//CRTCV1_CRTCV_SNAPSHOT_POSITION
+#define CRTCV1_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+#define CRTCV1_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+#define CRTCV1_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_SNAPSHOT_FRAME
+#define CRTCV1_CRTCV_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+#define CRTCV1_CRTCV_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+//CRTCV1_CRTCV_START_LINE_CONTROL
+#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
+#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
+#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
+#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
+#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
+#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
+#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000002L
+#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x00000004L
+#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x00000100L
+#define CRTCV1_CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000FF000L
+//CRTCV1_CRTCV_INTERRUPT_CONTROL
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+#define CRTCV1_CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+//CRTCV1_CRTCV_UPDATE_LOCK
+#define CRTCV1_CRTCV_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
+#define CRTCV1_CRTCV_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
+//CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL
+#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
+#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
+#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x19
+#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
+#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
+#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x01000000L
+#define CRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x02000000L
+//CRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE
+#define CRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
+#define CRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
+//CRTCV1_CRTCV_TEST_PATTERN_CONTROL
+#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
+#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
+#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
+#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
+#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
+#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
+#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
+#define CRTCV1_CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L
+//CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS
+#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
+#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
+#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
+#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
+#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
+#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000FL
+#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000F0L
+#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000F00L
+#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000F000L
+#define CRTCV1_CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L
+//CRTCV1_CRTCV_TEST_PATTERN_COLOR
+#define CRTCV1_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
+#define CRTCV1_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
+#define CRTCV1_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000FFFFL
+#define CRTCV1_CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003F0000L
+//CRTCV1_CRTCV_MASTER_UPDATE_LOCK
+#define CRTCV1_CRTCV_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
+#define CRTCV1_CRTCV_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
+#define CRTCV1_CRTCV_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
+#define CRTCV1_CRTCV_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
+#define CRTCV1_CRTCV_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
+#define CRTCV1_CRTCV_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x00010000L
+//CRTCV1_CRTCV_MASTER_UPDATE_MODE
+#define CRTCV1_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
+#define CRTCV1_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
+#define CRTCV1_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
+#define CRTCV1_CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
+//CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT
+#define CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
+#define CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
+#define CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
+#define CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xFFFFFF00L
+//CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER
+#define CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
+#define CRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000FFL
+//CRTCV1_CRTCV_MVP_STATUS
+#define CRTCV1_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
+#define CRTCV1_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
+#define CRTCV1_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
+#define CRTCV1_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
+#define CRTCV1_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
+#define CRTCV1_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
+#define CRTCV1_CRTCV_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
+#define CRTCV1_CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
+//CRTCV1_CRTCV_MASTER_EN
+#define CRTCV1_CRTCV_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTCV1_CRTCV_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
+//CRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT
+#define CRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
+#define CRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
+#define CRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000FFL
+#define CRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
+//CRTCV1_CRTCV_V_UPDATE_INT_STATUS
+#define CRTCV1_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
+#define CRTCV1_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
+#define CRTCV1_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
+#define CRTCV1_CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
+//CRTCV1_CRTCV_OVERSCAN_COLOR
+#define CRTCV1_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
+#define CRTCV1_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
+#define CRTCV1_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
+#define CRTCV1_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003FFL
+#define CRTCV1_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000FFC00L
+#define CRTCV1_CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3FF00000L
+//CRTCV1_CRTCV_OVERSCAN_COLOR_EXT
+#define CRTCV1_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
+#define CRTCV1_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
+#define CRTCV1_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
+#define CRTCV1_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x00000003L
+#define CRTCV1_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x00000300L
+#define CRTCV1_CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x00030000L
+//CRTCV1_CRTCV_BLANK_DATA_COLOR
+#define CRTCV1_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+#define CRTCV1_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+#define CRTCV1_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+#define CRTCV1_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+#define CRTCV1_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+#define CRTCV1_CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+//CRTCV1_CRTCV_BLANK_DATA_COLOR_EXT
+#define CRTCV1_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+#define CRTCV1_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+#define CRTCV1_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+#define CRTCV1_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x00000003L
+#define CRTCV1_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00000300L
+#define CRTCV1_CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x00030000L
+//CRTCV1_CRTCV_BLACK_COLOR
+#define CRTCV1_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
+#define CRTCV1_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
+#define CRTCV1_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
+#define CRTCV1_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003FFL
+#define CRTCV1_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+#define CRTCV1_CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+//CRTCV1_CRTCV_BLACK_COLOR_EXT
+#define CRTCV1_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+#define CRTCV1_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+#define CRTCV1_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+#define CRTCV1_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x00000003L
+#define CRTCV1_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x00000300L
+#define CRTCV1_CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x00030000L
+//CRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+//CRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00003FFFL
+//CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+//CRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00003FFFL
+//CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+#define CRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+//CRTCV1_CRTCV_CRC_CNTL
+#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
+#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
+#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
+#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
+#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
+#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
+#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_EN_MASK 0x00000001L
+#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x00000010L
+#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x00000300L
+#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
+#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x00700000L
+#define CRTCV1_CRTCV_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x07000000L
+//CRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL
+#define CRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
+#define CRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
+#define CRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL
+#define CRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
+#define CRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
+#define CRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL
+#define CRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
+#define CRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
+#define CRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL
+#define CRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
+#define CRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
+#define CRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_CRC0_DATA_RG
+#define CRTCV1_CRTCV_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+#define CRTCV1_CRTCV_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+#define CRTCV1_CRTCV_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+#define CRTCV1_CRTCV_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+//CRTCV1_CRTCV_CRC0_DATA_B
+#define CRTCV1_CRTCV_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+#define CRTCV1_CRTCV_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+//CRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL
+#define CRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
+#define CRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
+#define CRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL
+#define CRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
+#define CRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
+#define CRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL
+#define CRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
+#define CRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
+#define CRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL
+#define CRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
+#define CRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
+#define CRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_CRC1_DATA_RG
+#define CRTCV1_CRTCV_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+#define CRTCV1_CRTCV_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+#define CRTCV1_CRTCV_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+#define CRTCV1_CRTCV_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+//CRTCV1_CRTCV_CRC1_DATA_B
+#define CRTCV1_CRTCV_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+#define CRTCV1_CRTCV_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+//CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x00000003L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x00000008L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x00000010L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x00000060L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x00000100L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x00000200L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x00001000L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x00002000L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x00004000L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x07000000L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000L
+//CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x00000001L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x00000010L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x00000100L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x00010000L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x00100000L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xE0000000L
+//CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x00000001L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x00000010L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x00000100L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x00010000L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x00100000L
+//CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x00000001L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x00000010L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x00000100L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x00010000L
+#define CRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x00100000L
+//CRTCV1_CRTCV_STATIC_SCREEN_CONTROL
+#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
+#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
+#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
+#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
+#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
+#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x01000000L
+#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x02000000L
+#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x04000000L
+#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x08000000L
+#define CRTCV1_CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000L
+//CRTCV1_CRTCV_3D_STRUCTURE_CONTROL
+#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
+#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
+#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
+#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
+#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+#define CRTCV1_CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+//CRTCV1_CRTCV_GSL_VSYNC_GAP
+#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
+#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+#define CRTCV1_CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xFF000000L
+//CRTCV1_CRTCV_GSL_WINDOW
+#define CRTCV1_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
+#define CRTCV1_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
+#define CRTCV1_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3FFF0000L
+//CRTCV1_CRTCV_GSL_CONTROL
+#define CRTCV1_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
+#define CRTCV1_CRTCV_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
+#define CRTCV1_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+#define CRTCV1_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00003FFFL
+#define CRTCV1_CRTCV_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001F0000L
+#define CRTCV1_CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+
+
+// addressBlock: dce_dc_hpd0_dispdec
+//HPD0_DC_HPD_INT_STATUS
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
+//HPD0_DC_HPD_INT_CONTROL
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
+//HPD0_DC_HPD_CONTROL
+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
+//HPD0_DC_HPD_FAST_TRAIN_CNTL
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
+//HPD0_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
+
+
+// addressBlock: dce_dc_hpd1_dispdec
+//HPD1_DC_HPD_INT_STATUS
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
+//HPD1_DC_HPD_INT_CONTROL
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
+//HPD1_DC_HPD_CONTROL
+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
+//HPD1_DC_HPD_FAST_TRAIN_CNTL
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
+//HPD1_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
+
+
+// addressBlock: dce_dc_hpd2_dispdec
+//HPD2_DC_HPD_INT_STATUS
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
+//HPD2_DC_HPD_INT_CONTROL
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
+//HPD2_DC_HPD_CONTROL
+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
+//HPD2_DC_HPD_FAST_TRAIN_CNTL
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
+//HPD2_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
+
+
+// addressBlock: dce_dc_hpd3_dispdec
+//HPD3_DC_HPD_INT_STATUS
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
+//HPD3_DC_HPD_INT_CONTROL
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
+//HPD3_DC_HPD_CONTROL
+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
+//HPD3_DC_HPD_FAST_TRAIN_CNTL
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
+//HPD3_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
+
+
+// addressBlock: dce_dc_hpd4_dispdec
+//HPD4_DC_HPD_INT_STATUS
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
+//HPD4_DC_HPD_INT_CONTROL
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
+//HPD4_DC_HPD_CONTROL
+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
+//HPD4_DC_HPD_FAST_TRAIN_CNTL
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
+//HPD4_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
+
+
+// addressBlock: dce_dc_hpd5_dispdec
+//HPD5_DC_HPD_INT_STATUS
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
+//HPD5_DC_HPD_INT_CONTROL
+#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
+#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
+#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
+#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
+#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
+#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
+#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
+#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
+#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
+#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
+//HPD5_DC_HPD_CONTROL
+#define HPD5_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
+#define HPD5_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
+#define HPD5_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
+#define HPD5_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
+#define HPD5_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
+#define HPD5_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
+//HPD5_DC_HPD_FAST_TRAIN_CNTL
+#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
+#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
+#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
+#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
+#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
+//HPD5_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
+#define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
+#define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
+#define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
+
+
+// addressBlock: dce_dc_dc_perfmon2_dispdec
+//DC_PERFMON2_PERFCOUNTER_CNTL
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON2_PERFCOUNTER_CNTL2
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON2_PERFCOUNTER_STATE
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON2_PERFMON_CNTL
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON2_PERFMON_CNTL2
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON2_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON2_PERFMON_CVALUE_LOW
+#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON2_PERFMON_HI
+#define DC_PERFMON2_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON2_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON2_PERFMON_LOW
+#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dp_aux0_dispdec
+//DP_AUX0_AUX_CONTROL
+#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT 0x0
+#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT 0x4
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
+#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT 0x1e
+#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT 0x1f
+#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK 0x00000001L
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
+#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK 0x40000000L
+#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK 0x80000000L
+//DP_AUX0_AUX_SW_CONTROL
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
+//DP_AUX0_AUX_ARB_CONTROL
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
+//DP_AUX0_AUX_INTERRUPT_CONTROL
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
+//DP_AUX0_AUX_SW_STATUS
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L
+//DP_AUX0_AUX_LS_STATUS
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
+//DP_AUX0_AUX_SW_DATA
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
+//DP_AUX0_AUX_LS_DATA
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
+//DP_AUX0_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
+//DP_AUX0_AUX_DPHY_TX_CONTROL
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
+//DP_AUX0_AUX_DPHY_RX_CONTROL0
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
+//DP_AUX0_AUX_DPHY_RX_CONTROL1
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
+//DP_AUX0_AUX_DPHY_TX_STATUS
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
+//DP_AUX0_AUX_DPHY_RX_STATUS
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
+//DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
+//DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
+//DP_AUX0_AUX_GTC_SYNC_STATUS
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
+
+
+// addressBlock: dce_dc_dp_aux1_dispdec
+//DP_AUX1_AUX_CONTROL
+#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT 0x0
+#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT 0x4
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
+#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT 0x1e
+#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT 0x1f
+#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK 0x00000001L
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
+#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK 0x40000000L
+#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK 0x80000000L
+//DP_AUX1_AUX_SW_CONTROL
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
+//DP_AUX1_AUX_ARB_CONTROL
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
+//DP_AUX1_AUX_INTERRUPT_CONTROL
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
+//DP_AUX1_AUX_SW_STATUS
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L
+//DP_AUX1_AUX_LS_STATUS
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
+//DP_AUX1_AUX_SW_DATA
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
+//DP_AUX1_AUX_LS_DATA
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
+//DP_AUX1_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
+//DP_AUX1_AUX_DPHY_TX_CONTROL
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
+//DP_AUX1_AUX_DPHY_RX_CONTROL0
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
+//DP_AUX1_AUX_DPHY_RX_CONTROL1
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
+//DP_AUX1_AUX_DPHY_TX_STATUS
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
+//DP_AUX1_AUX_DPHY_RX_STATUS
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
+//DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
+//DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
+//DP_AUX1_AUX_GTC_SYNC_STATUS
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
+
+
+// addressBlock: dce_dc_dp_aux2_dispdec
+//DP_AUX2_AUX_CONTROL
+#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT 0x0
+#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT 0x4
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
+#define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT 0x1e
+#define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT 0x1f
+#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK 0x00000001L
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
+#define DP_AUX2_AUX_CONTROL__SPARE_0_MASK 0x40000000L
+#define DP_AUX2_AUX_CONTROL__SPARE_1_MASK 0x80000000L
+//DP_AUX2_AUX_SW_CONTROL
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
+//DP_AUX2_AUX_ARB_CONTROL
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
+//DP_AUX2_AUX_INTERRUPT_CONTROL
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
+//DP_AUX2_AUX_SW_STATUS
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L
+//DP_AUX2_AUX_LS_STATUS
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
+//DP_AUX2_AUX_SW_DATA
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
+//DP_AUX2_AUX_LS_DATA
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
+//DP_AUX2_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
+//DP_AUX2_AUX_DPHY_TX_CONTROL
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
+//DP_AUX2_AUX_DPHY_RX_CONTROL0
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
+//DP_AUX2_AUX_DPHY_RX_CONTROL1
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
+//DP_AUX2_AUX_DPHY_TX_STATUS
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
+//DP_AUX2_AUX_DPHY_RX_STATUS
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
+//DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
+//DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
+//DP_AUX2_AUX_GTC_SYNC_STATUS
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
+
+
+// addressBlock: dce_dc_dp_aux3_dispdec
+//DP_AUX3_AUX_CONTROL
+#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT 0x0
+#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT 0x4
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
+#define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT 0x1e
+#define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT 0x1f
+#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK 0x00000001L
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
+#define DP_AUX3_AUX_CONTROL__SPARE_0_MASK 0x40000000L
+#define DP_AUX3_AUX_CONTROL__SPARE_1_MASK 0x80000000L
+//DP_AUX3_AUX_SW_CONTROL
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
+//DP_AUX3_AUX_ARB_CONTROL
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
+//DP_AUX3_AUX_INTERRUPT_CONTROL
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
+//DP_AUX3_AUX_SW_STATUS
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L
+//DP_AUX3_AUX_LS_STATUS
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
+//DP_AUX3_AUX_SW_DATA
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
+//DP_AUX3_AUX_LS_DATA
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
+//DP_AUX3_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
+//DP_AUX3_AUX_DPHY_TX_CONTROL
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
+//DP_AUX3_AUX_DPHY_RX_CONTROL0
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
+//DP_AUX3_AUX_DPHY_RX_CONTROL1
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
+//DP_AUX3_AUX_DPHY_TX_STATUS
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
+//DP_AUX3_AUX_DPHY_RX_STATUS
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
+//DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
+//DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
+//DP_AUX3_AUX_GTC_SYNC_STATUS
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
+
+
+// addressBlock: dce_dc_dp_aux4_dispdec
+//DP_AUX4_AUX_CONTROL
+#define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT 0x0
+#define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT 0x4
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
+#define DP_AUX4_AUX_CONTROL__SPARE_0__SHIFT 0x1e
+#define DP_AUX4_AUX_CONTROL__SPARE_1__SHIFT 0x1f
+#define DP_AUX4_AUX_CONTROL__AUX_EN_MASK 0x00000001L
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
+#define DP_AUX4_AUX_CONTROL__SPARE_0_MASK 0x40000000L
+#define DP_AUX4_AUX_CONTROL__SPARE_1_MASK 0x80000000L
+//DP_AUX4_AUX_SW_CONTROL
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
+//DP_AUX4_AUX_ARB_CONTROL
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
+//DP_AUX4_AUX_INTERRUPT_CONTROL
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
+//DP_AUX4_AUX_SW_STATUS
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L
+//DP_AUX4_AUX_LS_STATUS
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
+//DP_AUX4_AUX_SW_DATA
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
+//DP_AUX4_AUX_LS_DATA
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
+//DP_AUX4_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
+//DP_AUX4_AUX_DPHY_TX_CONTROL
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
+//DP_AUX4_AUX_DPHY_RX_CONTROL0
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
+//DP_AUX4_AUX_DPHY_RX_CONTROL1
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
+//DP_AUX4_AUX_DPHY_TX_STATUS
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
+//DP_AUX4_AUX_DPHY_RX_STATUS
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
+//DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
+//DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
+//DP_AUX4_AUX_GTC_SYNC_STATUS
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
+
+
+// addressBlock: dce_dc_dp_aux5_dispdec
+//DP_AUX5_AUX_CONTROL
+#define DP_AUX5_AUX_CONTROL__AUX_EN__SHIFT 0x0
+#define DP_AUX5_AUX_CONTROL__AUX_RESET__SHIFT 0x4
+#define DP_AUX5_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
+#define DP_AUX5_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
+#define DP_AUX5_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
+#define DP_AUX5_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
+#define DP_AUX5_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
+#define DP_AUX5_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
+#define DP_AUX5_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
+#define DP_AUX5_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
+#define DP_AUX5_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
+#define DP_AUX5_AUX_CONTROL__SPARE_0__SHIFT 0x1e
+#define DP_AUX5_AUX_CONTROL__SPARE_1__SHIFT 0x1f
+#define DP_AUX5_AUX_CONTROL__AUX_EN_MASK 0x00000001L
+#define DP_AUX5_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
+#define DP_AUX5_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
+#define DP_AUX5_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
+#define DP_AUX5_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
+#define DP_AUX5_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
+#define DP_AUX5_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
+#define DP_AUX5_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
+#define DP_AUX5_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
+#define DP_AUX5_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
+#define DP_AUX5_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
+#define DP_AUX5_AUX_CONTROL__SPARE_0_MASK 0x40000000L
+#define DP_AUX5_AUX_CONTROL__SPARE_1_MASK 0x80000000L
+//DP_AUX5_AUX_SW_CONTROL
+#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
+#define DP_AUX5_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
+#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
+#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
+#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
+#define DP_AUX5_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
+#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
+#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
+//DP_AUX5_AUX_ARB_CONTROL
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
+//DP_AUX5_AUX_INTERRUPT_CONTROL
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
+//DP_AUX5_AUX_SW_STATUS
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX5_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX5_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L
+//DP_AUX5_AUX_LS_STATUS
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
+//DP_AUX5_AUX_SW_DATA
+#define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
+#define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
+#define DP_AUX5_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
+#define DP_AUX5_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+#define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
+#define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
+#define DP_AUX5_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
+#define DP_AUX5_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
+//DP_AUX5_AUX_LS_DATA
+#define DP_AUX5_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
+#define DP_AUX5_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
+#define DP_AUX5_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
+#define DP_AUX5_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
+//DP_AUX5_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
+#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
+#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
+#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
+#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
+#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
+//DP_AUX5_AUX_DPHY_TX_CONTROL
+#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
+#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
+#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
+#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
+//DP_AUX5_AUX_DPHY_RX_CONTROL0
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
+//DP_AUX5_AUX_DPHY_RX_CONTROL1
+#define DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+#define DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
+//DP_AUX5_AUX_DPHY_TX_STATUS
+#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
+#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
+#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
+#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
+#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
+//DP_AUX5_AUX_DPHY_RX_STATUS
+#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
+#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
+#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
+#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
+#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
+//DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
+#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
+#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
+#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
+#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
+#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
+#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
+#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
+//DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
+//DP_AUX5_AUX_GTC_SYNC_STATUS
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
+
+
+// addressBlock: dce_dc_dig0_dispdec
+//DIG0_DIG_FE_CNTL
+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+#define DIG0_DIG_FE_CNTL__DIG_START__SHIFT 0xa
+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
+#define DIG0_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
+//DIG0_DIG_OUTPUT_CRC_CNTL
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
+//DIG0_DIG_OUTPUT_CRC_RESULT
+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
+//DIG0_DIG_CLOCK_PATTERN
+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
+//DIG0_DIG_TEST_PATTERN
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
+//DIG0_DIG_RANDOM_PATTERN_SEED
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
+//DIG0_DIG_FIFO_STATUS
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+//DIG0_HDMI_CONTROL
+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
+//DIG0_HDMI_STATUS
+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
+//DIG0_HDMI_AUDIO_PACKET_CONTROL
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
+//DIG0_HDMI_ACR_PACKET_CONTROL
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
+//DIG0_HDMI_VBI_PACKET_CONTROL
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
+//DIG0_HDMI_INFOFRAME_CONTROL0
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
+//DIG0_HDMI_INFOFRAME_CONTROL1
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003FL
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L
+//DIG0_AFMT_INTERRUPT_STATUS
+//DIG0_HDMI_GC
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
+//DIG0_AFMT_AUDIO_PACKET_CONTROL2
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
+//DIG0_AFMT_ISRC1_0
+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
+//DIG0_AFMT_ISRC1_1
+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
+//DIG0_AFMT_ISRC1_2
+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
+//DIG0_AFMT_ISRC1_3
+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
+//DIG0_AFMT_ISRC1_4
+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
+//DIG0_AFMT_ISRC2_0
+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
+//DIG0_AFMT_ISRC2_1
+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
+//DIG0_AFMT_ISRC2_2
+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
+//DIG0_AFMT_ISRC2_3
+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
+//DIG0_AFMT_AVI_INFO0
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000C00L
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x0000E000L
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000F0000L
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00C00000L
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0C000000L
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
+#define DIG0_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
+//DIG0_AFMT_AVI_INFO1
+#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
+#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
+#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
+#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
+#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
+#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x000000FFL
+#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000F00L
+#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
+#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000C000L
+#define DIG0_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xFFFF0000L
+//DIG0_AFMT_AVI_INFO2
+#define DIG0_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
+#define DIG0_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
+#define DIG0_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000FFFFL
+#define DIG0_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xFFFF0000L
+//DIG0_AFMT_AVI_INFO3
+#define DIG0_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
+#define DIG0_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
+#define DIG0_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000FFFFL
+#define DIG0_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xFF000000L
+//DIG0_AFMT_MPEG_INFO0
+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
+//DIG0_AFMT_MPEG_INFO1
+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
+//DIG0_AFMT_GENERIC_HDR
+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
+//DIG0_AFMT_GENERIC_0
+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
+//DIG0_AFMT_GENERIC_1
+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
+//DIG0_AFMT_GENERIC_2
+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
+//DIG0_AFMT_GENERIC_3
+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
+//DIG0_AFMT_GENERIC_4
+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
+//DIG0_AFMT_GENERIC_5
+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
+//DIG0_AFMT_GENERIC_6
+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
+//DIG0_AFMT_GENERIC_7
+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L
+//DIG0_HDMI_ACR_32_0
+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
+//DIG0_HDMI_ACR_32_1
+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
+//DIG0_HDMI_ACR_44_0
+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
+//DIG0_HDMI_ACR_44_1
+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
+//DIG0_HDMI_ACR_48_0
+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
+//DIG0_HDMI_ACR_48_1
+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
+//DIG0_HDMI_ACR_STATUS_0
+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
+//DIG0_HDMI_ACR_STATUS_1
+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
+//DIG0_AFMT_AUDIO_INFO0
+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
+//DIG0_AFMT_AUDIO_INFO1
+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
+//DIG0_AFMT_60958_0
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
+//DIG0_AFMT_60958_1
+#define DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+#define DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+#define DIG0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+#define DIG0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+#define DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+#define DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
+#define DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
+#define DIG0_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
+#define DIG0_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
+#define DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
+//DIG0_AFMT_AUDIO_CRC_CONTROL
+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
+//DIG0_AFMT_RAMP_CONTROL0
+#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
+#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
+//DIG0_AFMT_RAMP_CONTROL1
+#define DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+#define DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+#define DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
+#define DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
+//DIG0_AFMT_RAMP_CONTROL2
+#define DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+#define DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
+//DIG0_AFMT_RAMP_CONTROL3
+#define DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+#define DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
+//DIG0_AFMT_60958_2
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
+//DIG0_AFMT_AUDIO_CRC_RESULT
+#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
+#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
+//DIG0_AFMT_STATUS
+#define DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+#define DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+#define DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+#define DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+#define DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
+#define DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
+#define DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
+#define DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
+//DIG0_AFMT_AUDIO_PACKET_CONTROL
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
+//DIG0_AFMT_VBI_PACKET_CONTROL
+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xC0000000L
+//DIG0_AFMT_INFOFRAME_CONTROL0
+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
+//DIG0_AFMT_AUDIO_SRC_CONTROL
+#define DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+#define DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
+//DIG0_DIG_BE_CNTL
+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+#define DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
+#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
+#define DIG0_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
+//DIG0_DIG_BE_EN_CNTL
+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
+//DIG0_TMDS_CNTL
+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
+//DIG0_TMDS_CONTROL_CHAR
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
+//DIG0_TMDS_CONTROL0_FEEDBACK
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
+//DIG0_TMDS_STEREOSYNC_CTL_SEL
+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
+//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
+//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
+//DIG0_TMDS_CTL_BITS
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
+//DIG0_TMDS_DCBALANCER_CONTROL
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
+//DIG0_TMDS_CTL0_1_GEN_CNTL
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
+//DIG0_TMDS_CTL2_3_GEN_CNTL
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
+//DIG0_DIG_VERSION
+#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT 0x0
+#define DIG0_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
+//DIG0_DIG_LANE_ENABLE
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
+#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
+//DIG0_AFMT_CNTL
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
+
+
+// addressBlock: dce_dc_dp0_dispdec
+//DP0_DP_LINK_CNTL
+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
+//DP0_DP_PIXEL_FORMAT
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+#define DP0_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
+#define DP0_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
+#define DP0_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
+#define DP0_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
+//DP0_DP_MSA_COLORIMETRY
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000FFL
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x00000200L
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x00020000L
+//DP0_DP_CONFIG
+#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+#define DP0_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
+//DP0_DP_VID_STREAM_CNTL
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
+//DP0_DP_STEER_FIFO
+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
+//DP0_DP_MSA_MISC
+#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
+#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x00000078L
+#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
+#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
+#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
+//DP0_DP_VID_TIMING
+#define DP0_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+#define DP0_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
+#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+#define DP0_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
+#define DP0_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x00000200L
+#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
+//DP0_DP_VID_N
+#define DP0_DP_VID_N__DP_VID_N__SHIFT 0x0
+#define DP0_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
+//DP0_DP_VID_M
+#define DP0_DP_VID_M__DP_VID_M__SHIFT 0x0
+#define DP0_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
+//DP0_DP_LINK_FRAMING_CNTL
+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
+//DP0_DP_HBR2_EYE_PATTERN
+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
+//DP0_DP_VID_MSA_VBID
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
+//DP0_DP_VID_INTERRUPT_CNTL
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
+//DP0_DP_DPHY_CNTL
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
+//DP0_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
+//DP0_DP_DPHY_SYM0
+#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
+#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
+#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
+//DP0_DP_DPHY_SYM1
+#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
+#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
+#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
+//DP0_DP_DPHY_SYM2
+#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
+#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
+//DP0_DP_DPHY_8B10B_CNTL
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
+//DP0_DP_DPHY_PRBS_CNTL
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
+//DP0_DP_DPHY_SCRAM_CNTL
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
+//DP0_DP_DPHY_CRC_EN
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
+//DP0_DP_DPHY_CRC_CNTL
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
+//DP0_DP_DPHY_CRC_RESULT
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
+//DP0_DP_DPHY_CRC_MST_CNTL
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
+//DP0_DP_DPHY_CRC_MST_STATUS
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
+//DP0_DP_DPHY_FAST_TRAINING
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
+//DP0_DP_DPHY_FAST_TRAINING_STATUS
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
+//DP0_DP_MSA_V_TIMING_OVERRIDE1
+#define DP0_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
+#define DP0_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
+#define DP0_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
+#define DP0_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0003FFF0L
+//DP0_DP_MSA_V_TIMING_OVERRIDE2
+#define DP0_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
+#define DP0_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
+#define DP0_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00003FFFL
+#define DP0_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3FFF0000L
+//DP0_DP_SEC_CNTL
+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+#define DP0_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
+#define DP0_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
+//DP0_DP_SEC_CNTL1
+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
+//DP0_DP_SEC_FRAMING1
+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP0_DP_SEC_FRAMING2
+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP0_DP_SEC_FRAMING3
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP0_DP_SEC_FRAMING4
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
+//DP0_DP_SEC_AUD_N
+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
+//DP0_DP_SEC_AUD_N_READBACK
+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
+//DP0_DP_SEC_AUD_M
+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
+//DP0_DP_SEC_AUD_M_READBACK
+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
+//DP0_DP_SEC_TIMESTAMP
+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
+//DP0_DP_SEC_PACKET_CNTL
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
+//DP0_DP_MSE_RATE_CNTL
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
+//DP0_DP_MSE_RATE_UPDATE
+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
+//DP0_DP_MSE_SAT0
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
+//DP0_DP_MSE_SAT1
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
+//DP0_DP_MSE_SAT2
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
+//DP0_DP_MSE_SAT_UPDATE
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
+//DP0_DP_MSE_LINK_TIMING
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
+//DP0_DP_MSE_MISC_CNTL
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
+//DP0_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
+//DP0_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
+//DP0_DP_MSE_SAT0_STATUS
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
+//DP0_DP_MSE_SAT1_STATUS
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
+//DP0_DP_MSE_SAT2_STATUS
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
+
+
+// addressBlock: dce_dc_dig1_dispdec
+//DIG1_DIG_FE_CNTL
+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+#define DIG1_DIG_FE_CNTL__DIG_START__SHIFT 0xa
+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
+#define DIG1_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
+//DIG1_DIG_OUTPUT_CRC_CNTL
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
+//DIG1_DIG_OUTPUT_CRC_RESULT
+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
+//DIG1_DIG_CLOCK_PATTERN
+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
+//DIG1_DIG_TEST_PATTERN
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
+//DIG1_DIG_RANDOM_PATTERN_SEED
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
+//DIG1_DIG_FIFO_STATUS
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+//DIG1_HDMI_CONTROL
+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
+//DIG1_HDMI_STATUS
+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
+//DIG1_HDMI_AUDIO_PACKET_CONTROL
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
+//DIG1_HDMI_ACR_PACKET_CONTROL
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
+//DIG1_HDMI_VBI_PACKET_CONTROL
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
+//DIG1_HDMI_INFOFRAME_CONTROL0
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
+//DIG1_HDMI_INFOFRAME_CONTROL1
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003FL
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L
+//DIG1_AFMT_INTERRUPT_STATUS
+//DIG1_HDMI_GC
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
+//DIG1_AFMT_AUDIO_PACKET_CONTROL2
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
+//DIG1_AFMT_ISRC1_0
+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
+//DIG1_AFMT_ISRC1_1
+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
+//DIG1_AFMT_ISRC1_2
+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
+//DIG1_AFMT_ISRC1_3
+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
+//DIG1_AFMT_ISRC1_4
+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
+//DIG1_AFMT_ISRC2_0
+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
+//DIG1_AFMT_ISRC2_1
+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
+//DIG1_AFMT_ISRC2_2
+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
+//DIG1_AFMT_ISRC2_3
+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
+//DIG1_AFMT_AVI_INFO0
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000C00L
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x0000E000L
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000F0000L
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00C00000L
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0C000000L
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
+#define DIG1_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
+//DIG1_AFMT_AVI_INFO1
+#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
+#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
+#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
+#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
+#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
+#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x000000FFL
+#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000F00L
+#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
+#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000C000L
+#define DIG1_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xFFFF0000L
+//DIG1_AFMT_AVI_INFO2
+#define DIG1_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
+#define DIG1_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
+#define DIG1_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000FFFFL
+#define DIG1_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xFFFF0000L
+//DIG1_AFMT_AVI_INFO3
+#define DIG1_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
+#define DIG1_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
+#define DIG1_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000FFFFL
+#define DIG1_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xFF000000L
+//DIG1_AFMT_MPEG_INFO0
+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
+//DIG1_AFMT_MPEG_INFO1
+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
+//DIG1_AFMT_GENERIC_HDR
+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
+//DIG1_AFMT_GENERIC_0
+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
+//DIG1_AFMT_GENERIC_1
+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
+//DIG1_AFMT_GENERIC_2
+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
+//DIG1_AFMT_GENERIC_3
+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
+//DIG1_AFMT_GENERIC_4
+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
+//DIG1_AFMT_GENERIC_5
+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
+//DIG1_AFMT_GENERIC_6
+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
+//DIG1_AFMT_GENERIC_7
+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L
+//DIG1_HDMI_ACR_32_0
+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
+//DIG1_HDMI_ACR_32_1
+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
+//DIG1_HDMI_ACR_44_0
+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
+//DIG1_HDMI_ACR_44_1
+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
+//DIG1_HDMI_ACR_48_0
+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
+//DIG1_HDMI_ACR_48_1
+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
+//DIG1_HDMI_ACR_STATUS_0
+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
+//DIG1_HDMI_ACR_STATUS_1
+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
+//DIG1_AFMT_AUDIO_INFO0
+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
+//DIG1_AFMT_AUDIO_INFO1
+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
+//DIG1_AFMT_60958_0
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
+//DIG1_AFMT_60958_1
+#define DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+#define DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+#define DIG1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+#define DIG1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+#define DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+#define DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
+#define DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
+#define DIG1_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
+#define DIG1_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
+#define DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
+//DIG1_AFMT_AUDIO_CRC_CONTROL
+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
+//DIG1_AFMT_RAMP_CONTROL0
+#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
+#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
+//DIG1_AFMT_RAMP_CONTROL1
+#define DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+#define DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+#define DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
+#define DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
+//DIG1_AFMT_RAMP_CONTROL2
+#define DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+#define DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
+//DIG1_AFMT_RAMP_CONTROL3
+#define DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+#define DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
+//DIG1_AFMT_60958_2
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
+//DIG1_AFMT_AUDIO_CRC_RESULT
+#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
+#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
+//DIG1_AFMT_STATUS
+#define DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+#define DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+#define DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+#define DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+#define DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
+#define DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
+#define DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
+#define DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
+//DIG1_AFMT_AUDIO_PACKET_CONTROL
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
+//DIG1_AFMT_VBI_PACKET_CONTROL
+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xC0000000L
+//DIG1_AFMT_INFOFRAME_CONTROL0
+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
+//DIG1_AFMT_AUDIO_SRC_CONTROL
+#define DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+#define DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
+//DIG1_DIG_BE_CNTL
+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+#define DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
+#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
+#define DIG1_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
+//DIG1_DIG_BE_EN_CNTL
+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
+//DIG1_TMDS_CNTL
+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
+//DIG1_TMDS_CONTROL_CHAR
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
+//DIG1_TMDS_CONTROL0_FEEDBACK
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
+//DIG1_TMDS_STEREOSYNC_CTL_SEL
+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
+//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
+//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
+//DIG1_TMDS_CTL_BITS
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
+//DIG1_TMDS_DCBALANCER_CONTROL
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
+//DIG1_TMDS_CTL0_1_GEN_CNTL
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
+//DIG1_TMDS_CTL2_3_GEN_CNTL
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
+//DIG1_DIG_VERSION
+#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT 0x0
+#define DIG1_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
+//DIG1_DIG_LANE_ENABLE
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
+#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
+//DIG1_AFMT_CNTL
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
+
+
+// addressBlock: dce_dc_dp1_dispdec
+//DP1_DP_LINK_CNTL
+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
+//DP1_DP_PIXEL_FORMAT
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+#define DP1_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
+#define DP1_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
+#define DP1_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
+#define DP1_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
+//DP1_DP_MSA_COLORIMETRY
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000FFL
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x00000200L
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x00020000L
+//DP1_DP_CONFIG
+#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+#define DP1_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
+//DP1_DP_VID_STREAM_CNTL
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
+//DP1_DP_STEER_FIFO
+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
+//DP1_DP_MSA_MISC
+#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
+#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x00000078L
+#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
+#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
+#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
+//DP1_DP_VID_TIMING
+#define DP1_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+#define DP1_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
+#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+#define DP1_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
+#define DP1_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x00000200L
+#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
+//DP1_DP_VID_N
+#define DP1_DP_VID_N__DP_VID_N__SHIFT 0x0
+#define DP1_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
+//DP1_DP_VID_M
+#define DP1_DP_VID_M__DP_VID_M__SHIFT 0x0
+#define DP1_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
+//DP1_DP_LINK_FRAMING_CNTL
+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
+//DP1_DP_HBR2_EYE_PATTERN
+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
+//DP1_DP_VID_MSA_VBID
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
+//DP1_DP_VID_INTERRUPT_CNTL
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
+//DP1_DP_DPHY_CNTL
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
+//DP1_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
+//DP1_DP_DPHY_SYM0
+#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
+#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
+#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
+//DP1_DP_DPHY_SYM1
+#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
+#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
+#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
+//DP1_DP_DPHY_SYM2
+#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
+#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
+//DP1_DP_DPHY_8B10B_CNTL
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
+//DP1_DP_DPHY_PRBS_CNTL
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
+//DP1_DP_DPHY_SCRAM_CNTL
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
+//DP1_DP_DPHY_CRC_EN
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
+//DP1_DP_DPHY_CRC_CNTL
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
+//DP1_DP_DPHY_CRC_RESULT
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
+//DP1_DP_DPHY_CRC_MST_CNTL
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
+//DP1_DP_DPHY_CRC_MST_STATUS
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
+//DP1_DP_DPHY_FAST_TRAINING
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
+//DP1_DP_DPHY_FAST_TRAINING_STATUS
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
+//DP1_DP_MSA_V_TIMING_OVERRIDE1
+#define DP1_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
+#define DP1_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
+#define DP1_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
+#define DP1_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0003FFF0L
+//DP1_DP_MSA_V_TIMING_OVERRIDE2
+#define DP1_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
+#define DP1_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
+#define DP1_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00003FFFL
+#define DP1_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3FFF0000L
+//DP1_DP_SEC_CNTL
+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+#define DP1_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
+#define DP1_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
+//DP1_DP_SEC_CNTL1
+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
+//DP1_DP_SEC_FRAMING1
+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP1_DP_SEC_FRAMING2
+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP1_DP_SEC_FRAMING3
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP1_DP_SEC_FRAMING4
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
+//DP1_DP_SEC_AUD_N
+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
+//DP1_DP_SEC_AUD_N_READBACK
+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
+//DP1_DP_SEC_AUD_M
+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
+//DP1_DP_SEC_AUD_M_READBACK
+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
+//DP1_DP_SEC_TIMESTAMP
+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
+//DP1_DP_SEC_PACKET_CNTL
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
+//DP1_DP_MSE_RATE_CNTL
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
+//DP1_DP_MSE_RATE_UPDATE
+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
+//DP1_DP_MSE_SAT0
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
+//DP1_DP_MSE_SAT1
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
+//DP1_DP_MSE_SAT2
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
+//DP1_DP_MSE_SAT_UPDATE
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
+//DP1_DP_MSE_LINK_TIMING
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
+//DP1_DP_MSE_MISC_CNTL
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
+//DP1_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
+//DP1_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
+//DP1_DP_MSE_SAT0_STATUS
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
+//DP1_DP_MSE_SAT1_STATUS
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
+//DP1_DP_MSE_SAT2_STATUS
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
+
+
+// addressBlock: dce_dc_dig2_dispdec
+//DIG2_DIG_FE_CNTL
+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+#define DIG2_DIG_FE_CNTL__DIG_START__SHIFT 0xa
+#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
+#define DIG2_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
+#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
+#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
+#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
+//DIG2_DIG_OUTPUT_CRC_CNTL
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
+//DIG2_DIG_OUTPUT_CRC_RESULT
+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
+//DIG2_DIG_CLOCK_PATTERN
+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
+//DIG2_DIG_TEST_PATTERN
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
+//DIG2_DIG_RANDOM_PATTERN_SEED
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
+//DIG2_DIG_FIFO_STATUS
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+//DIG2_HDMI_CONTROL
+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
+//DIG2_HDMI_STATUS
+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
+//DIG2_HDMI_AUDIO_PACKET_CONTROL
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
+//DIG2_HDMI_ACR_PACKET_CONTROL
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
+//DIG2_HDMI_VBI_PACKET_CONTROL
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
+//DIG2_HDMI_INFOFRAME_CONTROL0
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
+//DIG2_HDMI_INFOFRAME_CONTROL1
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003FL
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L
+//DIG2_AFMT_INTERRUPT_STATUS
+//DIG2_HDMI_GC
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
+//DIG2_AFMT_AUDIO_PACKET_CONTROL2
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
+//DIG2_AFMT_ISRC1_0
+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
+//DIG2_AFMT_ISRC1_1
+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
+//DIG2_AFMT_ISRC1_2
+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
+//DIG2_AFMT_ISRC1_3
+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
+//DIG2_AFMT_ISRC1_4
+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
+//DIG2_AFMT_ISRC2_0
+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
+//DIG2_AFMT_ISRC2_1
+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
+//DIG2_AFMT_ISRC2_2
+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
+//DIG2_AFMT_ISRC2_3
+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
+//DIG2_AFMT_AVI_INFO0
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000C00L
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x0000E000L
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000F0000L
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00C00000L
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0C000000L
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
+#define DIG2_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
+//DIG2_AFMT_AVI_INFO1
+#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
+#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
+#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
+#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
+#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
+#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x000000FFL
+#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000F00L
+#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
+#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000C000L
+#define DIG2_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xFFFF0000L
+//DIG2_AFMT_AVI_INFO2
+#define DIG2_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
+#define DIG2_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
+#define DIG2_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000FFFFL
+#define DIG2_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xFFFF0000L
+//DIG2_AFMT_AVI_INFO3
+#define DIG2_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
+#define DIG2_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
+#define DIG2_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000FFFFL
+#define DIG2_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xFF000000L
+//DIG2_AFMT_MPEG_INFO0
+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
+//DIG2_AFMT_MPEG_INFO1
+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
+//DIG2_AFMT_GENERIC_HDR
+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
+//DIG2_AFMT_GENERIC_0
+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
+//DIG2_AFMT_GENERIC_1
+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
+//DIG2_AFMT_GENERIC_2
+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
+//DIG2_AFMT_GENERIC_3
+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
+//DIG2_AFMT_GENERIC_4
+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
+//DIG2_AFMT_GENERIC_5
+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
+//DIG2_AFMT_GENERIC_6
+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
+//DIG2_AFMT_GENERIC_7
+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L
+//DIG2_HDMI_ACR_32_0
+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
+//DIG2_HDMI_ACR_32_1
+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
+//DIG2_HDMI_ACR_44_0
+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
+//DIG2_HDMI_ACR_44_1
+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
+//DIG2_HDMI_ACR_48_0
+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
+//DIG2_HDMI_ACR_48_1
+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
+//DIG2_HDMI_ACR_STATUS_0
+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
+//DIG2_HDMI_ACR_STATUS_1
+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
+//DIG2_AFMT_AUDIO_INFO0
+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
+//DIG2_AFMT_AUDIO_INFO1
+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
+//DIG2_AFMT_60958_0
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
+//DIG2_AFMT_60958_1
+#define DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+#define DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+#define DIG2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+#define DIG2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+#define DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+#define DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
+#define DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
+#define DIG2_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
+#define DIG2_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
+#define DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
+//DIG2_AFMT_AUDIO_CRC_CONTROL
+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
+//DIG2_AFMT_RAMP_CONTROL0
+#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
+#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
+//DIG2_AFMT_RAMP_CONTROL1
+#define DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+#define DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+#define DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
+#define DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
+//DIG2_AFMT_RAMP_CONTROL2
+#define DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+#define DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
+//DIG2_AFMT_RAMP_CONTROL3
+#define DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+#define DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
+//DIG2_AFMT_60958_2
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
+//DIG2_AFMT_AUDIO_CRC_RESULT
+#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
+#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
+//DIG2_AFMT_STATUS
+#define DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+#define DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+#define DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+#define DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+#define DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
+#define DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
+#define DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
+#define DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
+//DIG2_AFMT_AUDIO_PACKET_CONTROL
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
+//DIG2_AFMT_VBI_PACKET_CONTROL
+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xC0000000L
+//DIG2_AFMT_INFOFRAME_CONTROL0
+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
+//DIG2_AFMT_AUDIO_SRC_CONTROL
+#define DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+#define DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
+//DIG2_DIG_BE_CNTL
+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+#define DIG2_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
+#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
+#define DIG2_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
+//DIG2_DIG_BE_EN_CNTL
+#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
+#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
+//DIG2_TMDS_CNTL
+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
+//DIG2_TMDS_CONTROL_CHAR
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
+//DIG2_TMDS_CONTROL0_FEEDBACK
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
+//DIG2_TMDS_STEREOSYNC_CTL_SEL
+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
+//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
+//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
+//DIG2_TMDS_CTL_BITS
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
+//DIG2_TMDS_DCBALANCER_CONTROL
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
+//DIG2_TMDS_CTL0_1_GEN_CNTL
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
+//DIG2_TMDS_CTL2_3_GEN_CNTL
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
+//DIG2_DIG_VERSION
+#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT 0x0
+#define DIG2_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
+//DIG2_DIG_LANE_ENABLE
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+#define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
+#define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
+//DIG2_AFMT_CNTL
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
+
+
+// addressBlock: dce_dc_dp2_dispdec
+//DP2_DP_LINK_CNTL
+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
+#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
+//DP2_DP_PIXEL_FORMAT
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+#define DP2_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
+#define DP2_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
+#define DP2_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
+#define DP2_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
+//DP2_DP_MSA_COLORIMETRY
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000FFL
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x00000200L
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x00020000L
+//DP2_DP_CONFIG
+#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+#define DP2_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
+//DP2_DP_VID_STREAM_CNTL
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
+//DP2_DP_STEER_FIFO
+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
+//DP2_DP_MSA_MISC
+#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
+#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x00000078L
+#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
+#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
+#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
+//DP2_DP_VID_TIMING
+#define DP2_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+#define DP2_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
+#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+#define DP2_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
+#define DP2_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x00000200L
+#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
+//DP2_DP_VID_N
+#define DP2_DP_VID_N__DP_VID_N__SHIFT 0x0
+#define DP2_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
+//DP2_DP_VID_M
+#define DP2_DP_VID_M__DP_VID_M__SHIFT 0x0
+#define DP2_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
+//DP2_DP_LINK_FRAMING_CNTL
+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
+//DP2_DP_HBR2_EYE_PATTERN
+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
+//DP2_DP_VID_MSA_VBID
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
+//DP2_DP_VID_INTERRUPT_CNTL
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
+//DP2_DP_DPHY_CNTL
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
+//DP2_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
+//DP2_DP_DPHY_SYM0
+#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
+#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
+#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
+//DP2_DP_DPHY_SYM1
+#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
+#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
+#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
+//DP2_DP_DPHY_SYM2
+#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
+#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
+//DP2_DP_DPHY_8B10B_CNTL
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
+//DP2_DP_DPHY_PRBS_CNTL
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
+//DP2_DP_DPHY_SCRAM_CNTL
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
+//DP2_DP_DPHY_CRC_EN
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
+//DP2_DP_DPHY_CRC_CNTL
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
+//DP2_DP_DPHY_CRC_RESULT
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
+//DP2_DP_DPHY_CRC_MST_CNTL
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
+//DP2_DP_DPHY_CRC_MST_STATUS
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
+//DP2_DP_DPHY_FAST_TRAINING
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
+//DP2_DP_DPHY_FAST_TRAINING_STATUS
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
+//DP2_DP_MSA_V_TIMING_OVERRIDE1
+#define DP2_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
+#define DP2_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
+#define DP2_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
+#define DP2_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0003FFF0L
+//DP2_DP_MSA_V_TIMING_OVERRIDE2
+#define DP2_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
+#define DP2_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
+#define DP2_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00003FFFL
+#define DP2_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3FFF0000L
+//DP2_DP_SEC_CNTL
+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+#define DP2_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
+#define DP2_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
+//DP2_DP_SEC_CNTL1
+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
+//DP2_DP_SEC_FRAMING1
+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP2_DP_SEC_FRAMING2
+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP2_DP_SEC_FRAMING3
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP2_DP_SEC_FRAMING4
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
+//DP2_DP_SEC_AUD_N
+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
+//DP2_DP_SEC_AUD_N_READBACK
+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
+//DP2_DP_SEC_AUD_M
+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
+//DP2_DP_SEC_AUD_M_READBACK
+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
+//DP2_DP_SEC_TIMESTAMP
+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
+//DP2_DP_SEC_PACKET_CNTL
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
+//DP2_DP_MSE_RATE_CNTL
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
+//DP2_DP_MSE_RATE_UPDATE
+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
+//DP2_DP_MSE_SAT0
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
+//DP2_DP_MSE_SAT1
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
+//DP2_DP_MSE_SAT2
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
+//DP2_DP_MSE_SAT_UPDATE
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
+//DP2_DP_MSE_LINK_TIMING
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
+//DP2_DP_MSE_MISC_CNTL
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
+//DP2_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
+//DP2_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
+//DP2_DP_MSE_SAT0_STATUS
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
+//DP2_DP_MSE_SAT1_STATUS
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
+//DP2_DP_MSE_SAT2_STATUS
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
+
+
+// addressBlock: dce_dc_dig3_dispdec
+//DIG3_DIG_FE_CNTL
+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+#define DIG3_DIG_FE_CNTL__DIG_START__SHIFT 0xa
+#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
+#define DIG3_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
+#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
+#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
+#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
+//DIG3_DIG_OUTPUT_CRC_CNTL
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
+//DIG3_DIG_OUTPUT_CRC_RESULT
+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
+//DIG3_DIG_CLOCK_PATTERN
+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
+//DIG3_DIG_TEST_PATTERN
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
+//DIG3_DIG_RANDOM_PATTERN_SEED
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
+//DIG3_DIG_FIFO_STATUS
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+//DIG3_HDMI_CONTROL
+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
+//DIG3_HDMI_STATUS
+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
+//DIG3_HDMI_AUDIO_PACKET_CONTROL
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
+//DIG3_HDMI_ACR_PACKET_CONTROL
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
+//DIG3_HDMI_VBI_PACKET_CONTROL
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
+//DIG3_HDMI_INFOFRAME_CONTROL0
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
+//DIG3_HDMI_INFOFRAME_CONTROL1
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003FL
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L
+//DIG3_AFMT_INTERRUPT_STATUS
+//DIG3_HDMI_GC
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
+//DIG3_AFMT_AUDIO_PACKET_CONTROL2
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
+//DIG3_AFMT_ISRC1_0
+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
+//DIG3_AFMT_ISRC1_1
+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
+//DIG3_AFMT_ISRC1_2
+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
+//DIG3_AFMT_ISRC1_3
+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
+//DIG3_AFMT_ISRC1_4
+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
+//DIG3_AFMT_ISRC2_0
+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
+//DIG3_AFMT_ISRC2_1
+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
+//DIG3_AFMT_ISRC2_2
+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
+//DIG3_AFMT_ISRC2_3
+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
+//DIG3_AFMT_AVI_INFO0
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000C00L
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x0000E000L
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000F0000L
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00C00000L
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0C000000L
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
+#define DIG3_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
+//DIG3_AFMT_AVI_INFO1
+#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
+#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
+#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
+#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
+#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
+#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x000000FFL
+#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000F00L
+#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
+#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000C000L
+#define DIG3_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xFFFF0000L
+//DIG3_AFMT_AVI_INFO2
+#define DIG3_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
+#define DIG3_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
+#define DIG3_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000FFFFL
+#define DIG3_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xFFFF0000L
+//DIG3_AFMT_AVI_INFO3
+#define DIG3_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
+#define DIG3_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
+#define DIG3_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000FFFFL
+#define DIG3_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xFF000000L
+//DIG3_AFMT_MPEG_INFO0
+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
+//DIG3_AFMT_MPEG_INFO1
+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
+//DIG3_AFMT_GENERIC_HDR
+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
+//DIG3_AFMT_GENERIC_0
+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
+//DIG3_AFMT_GENERIC_1
+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
+//DIG3_AFMT_GENERIC_2
+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
+//DIG3_AFMT_GENERIC_3
+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
+//DIG3_AFMT_GENERIC_4
+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
+//DIG3_AFMT_GENERIC_5
+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
+//DIG3_AFMT_GENERIC_6
+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
+//DIG3_AFMT_GENERIC_7
+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L
+//DIG3_HDMI_ACR_32_0
+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
+//DIG3_HDMI_ACR_32_1
+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
+//DIG3_HDMI_ACR_44_0
+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
+//DIG3_HDMI_ACR_44_1
+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
+//DIG3_HDMI_ACR_48_0
+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
+//DIG3_HDMI_ACR_48_1
+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
+//DIG3_HDMI_ACR_STATUS_0
+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
+//DIG3_HDMI_ACR_STATUS_1
+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
+//DIG3_AFMT_AUDIO_INFO0
+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
+//DIG3_AFMT_AUDIO_INFO1
+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
+//DIG3_AFMT_60958_0
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
+//DIG3_AFMT_60958_1
+#define DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+#define DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+#define DIG3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+#define DIG3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+#define DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+#define DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
+#define DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
+#define DIG3_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
+#define DIG3_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
+#define DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
+//DIG3_AFMT_AUDIO_CRC_CONTROL
+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
+//DIG3_AFMT_RAMP_CONTROL0
+#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
+#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
+//DIG3_AFMT_RAMP_CONTROL1
+#define DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+#define DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+#define DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
+#define DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
+//DIG3_AFMT_RAMP_CONTROL2
+#define DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+#define DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
+//DIG3_AFMT_RAMP_CONTROL3
+#define DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+#define DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
+//DIG3_AFMT_60958_2
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
+//DIG3_AFMT_AUDIO_CRC_RESULT
+#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
+#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
+//DIG3_AFMT_STATUS
+#define DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+#define DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+#define DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+#define DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+#define DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
+#define DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
+#define DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
+#define DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
+//DIG3_AFMT_AUDIO_PACKET_CONTROL
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
+//DIG3_AFMT_VBI_PACKET_CONTROL
+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xC0000000L
+//DIG3_AFMT_INFOFRAME_CONTROL0
+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
+//DIG3_AFMT_AUDIO_SRC_CONTROL
+#define DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+#define DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
+//DIG3_DIG_BE_CNTL
+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+#define DIG3_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
+#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
+#define DIG3_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
+//DIG3_DIG_BE_EN_CNTL
+#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
+#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
+//DIG3_TMDS_CNTL
+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
+//DIG3_TMDS_CONTROL_CHAR
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
+//DIG3_TMDS_CONTROL0_FEEDBACK
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
+//DIG3_TMDS_STEREOSYNC_CTL_SEL
+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
+//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
+//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
+//DIG3_TMDS_CTL_BITS
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
+//DIG3_TMDS_DCBALANCER_CONTROL
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
+//DIG3_TMDS_CTL0_1_GEN_CNTL
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
+//DIG3_TMDS_CTL2_3_GEN_CNTL
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
+//DIG3_DIG_VERSION
+#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT 0x0
+#define DIG3_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
+//DIG3_DIG_LANE_ENABLE
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+#define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
+#define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
+//DIG3_AFMT_CNTL
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
+
+
+// addressBlock: dce_dc_dp3_dispdec
+//DP3_DP_LINK_CNTL
+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
+#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
+//DP3_DP_PIXEL_FORMAT
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+#define DP3_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
+#define DP3_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
+#define DP3_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
+#define DP3_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
+//DP3_DP_MSA_COLORIMETRY
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000FFL
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x00000200L
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x00020000L
+//DP3_DP_CONFIG
+#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+#define DP3_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
+//DP3_DP_VID_STREAM_CNTL
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
+//DP3_DP_STEER_FIFO
+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
+//DP3_DP_MSA_MISC
+#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
+#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x00000078L
+#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
+#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
+#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
+//DP3_DP_VID_TIMING
+#define DP3_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+#define DP3_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
+#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+#define DP3_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
+#define DP3_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x00000200L
+#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
+//DP3_DP_VID_N
+#define DP3_DP_VID_N__DP_VID_N__SHIFT 0x0
+#define DP3_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
+//DP3_DP_VID_M
+#define DP3_DP_VID_M__DP_VID_M__SHIFT 0x0
+#define DP3_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
+//DP3_DP_LINK_FRAMING_CNTL
+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
+//DP3_DP_HBR2_EYE_PATTERN
+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
+//DP3_DP_VID_MSA_VBID
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
+//DP3_DP_VID_INTERRUPT_CNTL
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
+//DP3_DP_DPHY_CNTL
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
+//DP3_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
+//DP3_DP_DPHY_SYM0
+#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
+#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
+#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
+//DP3_DP_DPHY_SYM1
+#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
+#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
+#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
+//DP3_DP_DPHY_SYM2
+#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
+#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
+//DP3_DP_DPHY_8B10B_CNTL
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
+//DP3_DP_DPHY_PRBS_CNTL
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
+//DP3_DP_DPHY_SCRAM_CNTL
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
+//DP3_DP_DPHY_CRC_EN
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
+//DP3_DP_DPHY_CRC_CNTL
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
+//DP3_DP_DPHY_CRC_RESULT
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
+//DP3_DP_DPHY_CRC_MST_CNTL
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
+//DP3_DP_DPHY_CRC_MST_STATUS
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
+//DP3_DP_DPHY_FAST_TRAINING
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
+//DP3_DP_DPHY_FAST_TRAINING_STATUS
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
+//DP3_DP_MSA_V_TIMING_OVERRIDE1
+#define DP3_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
+#define DP3_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
+#define DP3_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
+#define DP3_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0003FFF0L
+//DP3_DP_MSA_V_TIMING_OVERRIDE2
+#define DP3_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
+#define DP3_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
+#define DP3_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00003FFFL
+#define DP3_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3FFF0000L
+//DP3_DP_SEC_CNTL
+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+#define DP3_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
+#define DP3_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
+//DP3_DP_SEC_CNTL1
+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
+//DP3_DP_SEC_FRAMING1
+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP3_DP_SEC_FRAMING2
+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP3_DP_SEC_FRAMING3
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP3_DP_SEC_FRAMING4
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
+//DP3_DP_SEC_AUD_N
+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
+//DP3_DP_SEC_AUD_N_READBACK
+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
+//DP3_DP_SEC_AUD_M
+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
+//DP3_DP_SEC_AUD_M_READBACK
+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
+//DP3_DP_SEC_TIMESTAMP
+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
+//DP3_DP_SEC_PACKET_CNTL
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
+//DP3_DP_MSE_RATE_CNTL
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
+//DP3_DP_MSE_RATE_UPDATE
+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
+//DP3_DP_MSE_SAT0
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
+//DP3_DP_MSE_SAT1
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
+//DP3_DP_MSE_SAT2
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
+//DP3_DP_MSE_SAT_UPDATE
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
+//DP3_DP_MSE_LINK_TIMING
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
+//DP3_DP_MSE_MISC_CNTL
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
+//DP3_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
+//DP3_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
+//DP3_DP_MSE_SAT0_STATUS
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
+//DP3_DP_MSE_SAT1_STATUS
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
+//DP3_DP_MSE_SAT2_STATUS
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
+
+
+// addressBlock: dce_dc_dig4_dispdec
+//DIG4_DIG_FE_CNTL
+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+#define DIG4_DIG_FE_CNTL__DIG_START__SHIFT 0xa
+#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
+#define DIG4_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
+#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
+#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
+#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
+//DIG4_DIG_OUTPUT_CRC_CNTL
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
+//DIG4_DIG_OUTPUT_CRC_RESULT
+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
+//DIG4_DIG_CLOCK_PATTERN
+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
+//DIG4_DIG_TEST_PATTERN
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
+//DIG4_DIG_RANDOM_PATTERN_SEED
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
+//DIG4_DIG_FIFO_STATUS
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+//DIG4_HDMI_CONTROL
+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
+//DIG4_HDMI_STATUS
+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
+//DIG4_HDMI_AUDIO_PACKET_CONTROL
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
+//DIG4_HDMI_ACR_PACKET_CONTROL
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
+//DIG4_HDMI_VBI_PACKET_CONTROL
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
+//DIG4_HDMI_INFOFRAME_CONTROL0
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
+//DIG4_HDMI_INFOFRAME_CONTROL1
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003FL
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L
+//DIG4_AFMT_INTERRUPT_STATUS
+//DIG4_HDMI_GC
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
+//DIG4_AFMT_AUDIO_PACKET_CONTROL2
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
+//DIG4_AFMT_ISRC1_0
+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
+//DIG4_AFMT_ISRC1_1
+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
+//DIG4_AFMT_ISRC1_2
+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
+//DIG4_AFMT_ISRC1_3
+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
+//DIG4_AFMT_ISRC1_4
+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
+//DIG4_AFMT_ISRC2_0
+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
+//DIG4_AFMT_ISRC2_1
+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
+//DIG4_AFMT_ISRC2_2
+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
+//DIG4_AFMT_ISRC2_3
+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
+//DIG4_AFMT_AVI_INFO0
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000C00L
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x0000E000L
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000F0000L
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00C00000L
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0C000000L
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
+#define DIG4_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
+//DIG4_AFMT_AVI_INFO1
+#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
+#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
+#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
+#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
+#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
+#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x000000FFL
+#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000F00L
+#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
+#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000C000L
+#define DIG4_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xFFFF0000L
+//DIG4_AFMT_AVI_INFO2
+#define DIG4_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
+#define DIG4_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
+#define DIG4_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000FFFFL
+#define DIG4_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xFFFF0000L
+//DIG4_AFMT_AVI_INFO3
+#define DIG4_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
+#define DIG4_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
+#define DIG4_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000FFFFL
+#define DIG4_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xFF000000L
+//DIG4_AFMT_MPEG_INFO0
+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
+//DIG4_AFMT_MPEG_INFO1
+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
+//DIG4_AFMT_GENERIC_HDR
+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
+//DIG4_AFMT_GENERIC_0
+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
+//DIG4_AFMT_GENERIC_1
+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
+//DIG4_AFMT_GENERIC_2
+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
+//DIG4_AFMT_GENERIC_3
+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
+//DIG4_AFMT_GENERIC_4
+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
+//DIG4_AFMT_GENERIC_5
+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
+//DIG4_AFMT_GENERIC_6
+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
+//DIG4_AFMT_GENERIC_7
+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L
+//DIG4_HDMI_ACR_32_0
+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
+//DIG4_HDMI_ACR_32_1
+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
+//DIG4_HDMI_ACR_44_0
+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
+//DIG4_HDMI_ACR_44_1
+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
+//DIG4_HDMI_ACR_48_0
+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
+//DIG4_HDMI_ACR_48_1
+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
+//DIG4_HDMI_ACR_STATUS_0
+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
+//DIG4_HDMI_ACR_STATUS_1
+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
+//DIG4_AFMT_AUDIO_INFO0
+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
+//DIG4_AFMT_AUDIO_INFO1
+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
+//DIG4_AFMT_60958_0
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
+//DIG4_AFMT_60958_1
+#define DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+#define DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+#define DIG4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+#define DIG4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+#define DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+#define DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
+#define DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
+#define DIG4_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
+#define DIG4_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
+#define DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
+//DIG4_AFMT_AUDIO_CRC_CONTROL
+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
+//DIG4_AFMT_RAMP_CONTROL0
+#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
+#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
+//DIG4_AFMT_RAMP_CONTROL1
+#define DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+#define DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+#define DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
+#define DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
+//DIG4_AFMT_RAMP_CONTROL2
+#define DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+#define DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
+//DIG4_AFMT_RAMP_CONTROL3
+#define DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+#define DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
+//DIG4_AFMT_60958_2
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
+//DIG4_AFMT_AUDIO_CRC_RESULT
+#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
+#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
+//DIG4_AFMT_STATUS
+#define DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+#define DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+#define DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+#define DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+#define DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
+#define DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
+#define DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
+#define DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
+//DIG4_AFMT_AUDIO_PACKET_CONTROL
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
+//DIG4_AFMT_VBI_PACKET_CONTROL
+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xC0000000L
+//DIG4_AFMT_INFOFRAME_CONTROL0
+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
+//DIG4_AFMT_AUDIO_SRC_CONTROL
+#define DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+#define DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
+//DIG4_DIG_BE_CNTL
+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+#define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+#define DIG4_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
+#define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
+#define DIG4_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
+//DIG4_DIG_BE_EN_CNTL
+#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
+#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
+//DIG4_TMDS_CNTL
+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
+//DIG4_TMDS_CONTROL_CHAR
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
+//DIG4_TMDS_CONTROL0_FEEDBACK
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
+//DIG4_TMDS_STEREOSYNC_CTL_SEL
+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
+//DIG4_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
+//DIG4_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
+//DIG4_TMDS_CTL_BITS
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
+//DIG4_TMDS_DCBALANCER_CONTROL
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
+//DIG4_TMDS_CTL0_1_GEN_CNTL
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
+//DIG4_TMDS_CTL2_3_GEN_CNTL
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
+//DIG4_DIG_VERSION
+#define DIG4_DIG_VERSION__DIG_TYPE__SHIFT 0x0
+#define DIG4_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
+//DIG4_DIG_LANE_ENABLE
+#define DIG4_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+#define DIG4_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+#define DIG4_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+#define DIG4_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+#define DIG4_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+#define DIG4_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
+#define DIG4_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
+#define DIG4_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
+#define DIG4_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
+#define DIG4_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
+//DIG4_AFMT_CNTL
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
+
+
+// addressBlock: dce_dc_dp4_dispdec
+//DP4_DP_LINK_CNTL
+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
+#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
+//DP4_DP_PIXEL_FORMAT
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+#define DP4_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
+#define DP4_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
+#define DP4_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
+#define DP4_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
+//DP4_DP_MSA_COLORIMETRY
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000FFL
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x00000200L
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x00020000L
+//DP4_DP_CONFIG
+#define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+#define DP4_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
+//DP4_DP_VID_STREAM_CNTL
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
+//DP4_DP_STEER_FIFO
+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
+//DP4_DP_MSA_MISC
+#define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
+#define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+#define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+#define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+#define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x00000078L
+#define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
+#define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
+#define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
+//DP4_DP_VID_TIMING
+#define DP4_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+#define DP4_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
+#define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+#define DP4_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
+#define DP4_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x00000200L
+#define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
+//DP4_DP_VID_N
+#define DP4_DP_VID_N__DP_VID_N__SHIFT 0x0
+#define DP4_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
+//DP4_DP_VID_M
+#define DP4_DP_VID_M__DP_VID_M__SHIFT 0x0
+#define DP4_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
+//DP4_DP_LINK_FRAMING_CNTL
+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
+//DP4_DP_HBR2_EYE_PATTERN
+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
+//DP4_DP_VID_MSA_VBID
+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
+//DP4_DP_VID_INTERRUPT_CNTL
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
+//DP4_DP_DPHY_CNTL
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
+//DP4_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
+//DP4_DP_DPHY_SYM0
+#define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+#define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+#define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+#define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
+#define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
+#define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
+//DP4_DP_DPHY_SYM1
+#define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+#define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+#define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+#define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
+#define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
+#define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
+//DP4_DP_DPHY_SYM2
+#define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+#define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+#define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
+#define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
+//DP4_DP_DPHY_8B10B_CNTL
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
+//DP4_DP_DPHY_PRBS_CNTL
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
+//DP4_DP_DPHY_SCRAM_CNTL
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
+//DP4_DP_DPHY_CRC_EN
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
+//DP4_DP_DPHY_CRC_CNTL
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
+//DP4_DP_DPHY_CRC_RESULT
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
+//DP4_DP_DPHY_CRC_MST_CNTL
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
+//DP4_DP_DPHY_CRC_MST_STATUS
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
+//DP4_DP_DPHY_FAST_TRAINING
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
+//DP4_DP_DPHY_FAST_TRAINING_STATUS
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
+//DP4_DP_MSA_V_TIMING_OVERRIDE1
+#define DP4_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
+#define DP4_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
+#define DP4_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
+#define DP4_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0003FFF0L
+//DP4_DP_MSA_V_TIMING_OVERRIDE2
+#define DP4_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
+#define DP4_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
+#define DP4_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00003FFFL
+#define DP4_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3FFF0000L
+//DP4_DP_SEC_CNTL
+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+#define DP4_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
+#define DP4_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
+//DP4_DP_SEC_CNTL1
+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
+//DP4_DP_SEC_FRAMING1
+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP4_DP_SEC_FRAMING2
+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP4_DP_SEC_FRAMING3
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP4_DP_SEC_FRAMING4
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
+//DP4_DP_SEC_AUD_N
+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
+//DP4_DP_SEC_AUD_N_READBACK
+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
+//DP4_DP_SEC_AUD_M
+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
+//DP4_DP_SEC_AUD_M_READBACK
+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
+//DP4_DP_SEC_TIMESTAMP
+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
+//DP4_DP_SEC_PACKET_CNTL
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
+//DP4_DP_MSE_RATE_CNTL
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
+//DP4_DP_MSE_RATE_UPDATE
+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
+//DP4_DP_MSE_SAT0
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
+//DP4_DP_MSE_SAT1
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
+//DP4_DP_MSE_SAT2
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
+//DP4_DP_MSE_SAT_UPDATE
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
+//DP4_DP_MSE_LINK_TIMING
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
+//DP4_DP_MSE_MISC_CNTL
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
+//DP4_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
+//DP4_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
+//DP4_DP_MSE_SAT0_STATUS
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
+//DP4_DP_MSE_SAT1_STATUS
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
+//DP4_DP_MSE_SAT2_STATUS
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
+
+
+// addressBlock: dce_dc_dig5_dispdec
+//DIG5_DIG_FE_CNTL
+#define DIG5_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+#define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+#define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+#define DIG5_DIG_FE_CNTL__DIG_START__SHIFT 0xa
+#define DIG5_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+#define DIG5_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+#define DIG5_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+#define DIG5_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
+#define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
+#define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
+#define DIG5_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
+#define DIG5_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
+#define DIG5_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
+#define DIG5_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
+//DIG5_DIG_OUTPUT_CRC_CNTL
+#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
+#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
+#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
+//DIG5_DIG_OUTPUT_CRC_RESULT
+#define DIG5_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+#define DIG5_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
+//DIG5_DIG_CLOCK_PATTERN
+#define DIG5_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+#define DIG5_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
+//DIG5_DIG_TEST_PATTERN
+#define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+#define DIG5_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+#define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+#define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+#define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+#define DIG5_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+#define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
+#define DIG5_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
+#define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
+#define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
+#define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
+#define DIG5_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
+//DIG5_DIG_RANDOM_PATTERN_SEED
+#define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+#define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+#define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
+#define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
+//DIG5_DIG_FIFO_STATUS
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+//DIG5_HDMI_CONTROL
+#define DIG5_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+#define DIG5_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
+#define DIG5_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+#define DIG5_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+#define DIG5_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+#define DIG5_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+#define DIG5_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+#define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+#define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+#define DIG5_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
+#define DIG5_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
+#define DIG5_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
+#define DIG5_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
+#define DIG5_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
+#define DIG5_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
+#define DIG5_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
+#define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
+#define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
+//DIG5_HDMI_STATUS
+#define DIG5_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+#define DIG5_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+#define DIG5_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+#define DIG5_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+#define DIG5_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
+#define DIG5_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
+#define DIG5_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
+#define DIG5_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
+//DIG5_HDMI_AUDIO_PACKET_CONTROL
+#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
+#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
+//DIG5_HDMI_ACR_PACKET_CONTROL
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
+//DIG5_HDMI_VBI_PACKET_CONTROL
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
+//DIG5_HDMI_INFOFRAME_CONTROL0
+#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
+#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
+#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
+#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
+#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
+#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
+#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
+#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
+//DIG5_HDMI_INFOFRAME_CONTROL1
+#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
+#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003FL
+#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
+#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
+//DIG5_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L
+//DIG5_AFMT_INTERRUPT_STATUS
+//DIG5_HDMI_GC
+#define DIG5_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+#define DIG5_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+#define DIG5_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+#define DIG5_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+#define DIG5_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+#define DIG5_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
+#define DIG5_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
+#define DIG5_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
+#define DIG5_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
+#define DIG5_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
+//DIG5_AFMT_AUDIO_PACKET_CONTROL2
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
+//DIG5_AFMT_ISRC1_0
+#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
+#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
+#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
+//DIG5_AFMT_ISRC1_1
+#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
+#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
+#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
+#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
+//DIG5_AFMT_ISRC1_2
+#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
+#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
+#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
+#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
+//DIG5_AFMT_ISRC1_3
+#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
+#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
+#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
+#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
+//DIG5_AFMT_ISRC1_4
+#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
+#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
+#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
+#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
+//DIG5_AFMT_ISRC2_0
+#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
+#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
+#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
+#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
+//DIG5_AFMT_ISRC2_1
+#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
+#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
+#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
+#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
+//DIG5_AFMT_ISRC2_2
+#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
+#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
+#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
+#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
+//DIG5_AFMT_ISRC2_3
+#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
+#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
+#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
+#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
+//DIG5_AFMT_AVI_INFO0
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000C00L
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x0000E000L
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000F0000L
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00C00000L
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0C000000L
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
+#define DIG5_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
+//DIG5_AFMT_AVI_INFO1
+#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
+#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
+#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
+#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
+#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
+#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x000000FFL
+#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000F00L
+#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
+#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000C000L
+#define DIG5_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xFFFF0000L
+//DIG5_AFMT_AVI_INFO2
+#define DIG5_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
+#define DIG5_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
+#define DIG5_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000FFFFL
+#define DIG5_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xFFFF0000L
+//DIG5_AFMT_AVI_INFO3
+#define DIG5_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
+#define DIG5_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
+#define DIG5_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000FFFFL
+#define DIG5_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xFF000000L
+//DIG5_AFMT_MPEG_INFO0
+#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
+#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
+#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
+//DIG5_AFMT_MPEG_INFO1
+#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
+#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
+#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
+//DIG5_AFMT_GENERIC_HDR
+#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
+#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
+#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
+#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
+//DIG5_AFMT_GENERIC_0
+#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
+#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
+#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
+#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
+//DIG5_AFMT_GENERIC_1
+#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
+#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
+#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
+#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
+//DIG5_AFMT_GENERIC_2
+#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
+#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
+#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
+#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
+//DIG5_AFMT_GENERIC_3
+#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
+#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
+#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
+#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
+//DIG5_AFMT_GENERIC_4
+#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
+#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
+#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
+#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
+//DIG5_AFMT_GENERIC_5
+#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
+#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
+#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
+#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
+//DIG5_AFMT_GENERIC_6
+#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
+#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
+#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
+#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
+//DIG5_AFMT_GENERIC_7
+#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
+#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
+#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
+#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
+//DIG5_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L
+//DIG5_HDMI_ACR_32_0
+#define DIG5_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+#define DIG5_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
+//DIG5_HDMI_ACR_32_1
+#define DIG5_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+#define DIG5_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
+//DIG5_HDMI_ACR_44_0
+#define DIG5_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+#define DIG5_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
+//DIG5_HDMI_ACR_44_1
+#define DIG5_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+#define DIG5_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
+//DIG5_HDMI_ACR_48_0
+#define DIG5_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+#define DIG5_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
+//DIG5_HDMI_ACR_48_1
+#define DIG5_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+#define DIG5_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
+//DIG5_HDMI_ACR_STATUS_0
+#define DIG5_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+#define DIG5_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
+//DIG5_HDMI_ACR_STATUS_1
+#define DIG5_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+#define DIG5_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
+//DIG5_AFMT_AUDIO_INFO0
+#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
+#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
+#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
+#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
+//DIG5_AFMT_AUDIO_INFO1
+#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
+#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
+#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
+#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
+//DIG5_AFMT_60958_0
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
+//DIG5_AFMT_60958_1
+#define DIG5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+#define DIG5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+#define DIG5_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+#define DIG5_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+#define DIG5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+#define DIG5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
+#define DIG5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
+#define DIG5_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
+#define DIG5_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
+#define DIG5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
+//DIG5_AFMT_AUDIO_CRC_CONTROL
+#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
+#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
+#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
+#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
+#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
+//DIG5_AFMT_RAMP_CONTROL0
+#define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+#define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+#define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
+#define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
+//DIG5_AFMT_RAMP_CONTROL1
+#define DIG5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+#define DIG5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+#define DIG5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
+#define DIG5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
+//DIG5_AFMT_RAMP_CONTROL2
+#define DIG5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+#define DIG5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
+//DIG5_AFMT_RAMP_CONTROL3
+#define DIG5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+#define DIG5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
+//DIG5_AFMT_60958_2
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
+//DIG5_AFMT_AUDIO_CRC_RESULT
+#define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+#define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+#define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
+#define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
+//DIG5_AFMT_STATUS
+#define DIG5_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+#define DIG5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+#define DIG5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+#define DIG5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+#define DIG5_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
+#define DIG5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
+#define DIG5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
+#define DIG5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
+//DIG5_AFMT_AUDIO_PACKET_CONTROL
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
+//DIG5_AFMT_VBI_PACKET_CONTROL
+#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
+#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
+#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
+#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
+#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
+#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xC0000000L
+//DIG5_AFMT_INFOFRAME_CONTROL0
+#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
+#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
+#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
+//DIG5_AFMT_AUDIO_SRC_CONTROL
+#define DIG5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+#define DIG5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
+//DIG5_DIG_BE_CNTL
+#define DIG5_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+#define DIG5_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+#define DIG5_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+#define DIG5_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+#define DIG5_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+#define DIG5_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
+#define DIG5_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
+#define DIG5_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
+#define DIG5_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
+#define DIG5_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
+//DIG5_DIG_BE_EN_CNTL
+#define DIG5_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+#define DIG5_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+#define DIG5_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
+#define DIG5_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
+//DIG5_TMDS_CNTL
+#define DIG5_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+#define DIG5_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
+//DIG5_TMDS_CONTROL_CHAR
+#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
+#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
+#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
+#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
+//DIG5_TMDS_CONTROL0_FEEDBACK
+#define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+#define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+#define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
+#define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
+//DIG5_TMDS_STEREOSYNC_CTL_SEL
+#define DIG5_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+#define DIG5_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
+//DIG5_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+#define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+#define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
+#define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
+//DIG5_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+#define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+#define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
+#define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
+//DIG5_TMDS_CTL_BITS
+#define DIG5_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+#define DIG5_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+#define DIG5_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+#define DIG5_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+#define DIG5_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
+#define DIG5_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
+#define DIG5_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
+#define DIG5_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
+//DIG5_TMDS_DCBALANCER_CONTROL
+#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
+#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
+#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
+#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
+//DIG5_TMDS_CTL0_1_GEN_CNTL
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
+//DIG5_TMDS_CTL2_3_GEN_CNTL
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
+//DIG5_DIG_VERSION
+#define DIG5_DIG_VERSION__DIG_TYPE__SHIFT 0x0
+#define DIG5_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
+//DIG5_DIG_LANE_ENABLE
+#define DIG5_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+#define DIG5_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+#define DIG5_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+#define DIG5_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+#define DIG5_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+#define DIG5_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
+#define DIG5_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
+#define DIG5_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
+#define DIG5_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
+#define DIG5_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
+//DIG5_AFMT_CNTL
+#define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
+#define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
+#define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
+#define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
+
+
+// addressBlock: dce_dc_dp5_dispdec
+//DP5_DP_LINK_CNTL
+#define DP5_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+#define DP5_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+#define DP5_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+#define DP5_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
+#define DP5_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
+#define DP5_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
+//DP5_DP_PIXEL_FORMAT
+#define DP5_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+#define DP5_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
+#define DP5_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
+#define DP5_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+#define DP5_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
+#define DP5_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
+#define DP5_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
+#define DP5_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
+//DP5_DP_MSA_COLORIMETRY
+#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
+#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
+#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
+#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
+#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000FFL
+#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
+#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x00000200L
+#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x00020000L
+//DP5_DP_CONFIG
+#define DP5_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+#define DP5_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
+//DP5_DP_VID_STREAM_CNTL
+#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
+#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
+#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
+#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
+//DP5_DP_STEER_FIFO
+#define DP5_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+#define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+#define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+#define DP5_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
+#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
+#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
+#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
+#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
+#define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
+#define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
+//DP5_DP_MSA_MISC
+#define DP5_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
+#define DP5_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+#define DP5_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+#define DP5_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+#define DP5_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x00000078L
+#define DP5_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
+#define DP5_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
+#define DP5_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
+//DP5_DP_VID_TIMING
+#define DP5_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
+#define DP5_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
+#define DP5_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+#define DP5_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
+#define DP5_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+#define DP5_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
+#define DP5_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
+#define DP5_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
+#define DP5_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x00000200L
+#define DP5_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
+//DP5_DP_VID_N
+#define DP5_DP_VID_N__DP_VID_N__SHIFT 0x0
+#define DP5_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
+//DP5_DP_VID_M
+#define DP5_DP_VID_M__DP_VID_M__SHIFT 0x0
+#define DP5_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
+//DP5_DP_LINK_FRAMING_CNTL
+#define DP5_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+#define DP5_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+#define DP5_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+#define DP5_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
+#define DP5_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
+#define DP5_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
+//DP5_DP_HBR2_EYE_PATTERN
+#define DP5_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+#define DP5_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
+//DP5_DP_VID_MSA_VBID
+#define DP5_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+#define DP5_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
+#define DP5_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+#define DP5_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
+#define DP5_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
+#define DP5_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
+//DP5_DP_VID_INTERRUPT_CNTL
+#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
+#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
+#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
+//DP5_DP_DPHY_CNTL
+#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+#define DP5_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+#define DP5_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
+#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
+#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
+#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
+#define DP5_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
+#define DP5_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
+//DP5_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP5_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+#define DP5_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
+//DP5_DP_DPHY_SYM0
+#define DP5_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+#define DP5_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+#define DP5_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+#define DP5_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
+#define DP5_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
+#define DP5_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
+//DP5_DP_DPHY_SYM1
+#define DP5_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+#define DP5_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+#define DP5_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+#define DP5_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
+#define DP5_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
+#define DP5_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
+//DP5_DP_DPHY_SYM2
+#define DP5_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+#define DP5_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+#define DP5_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
+#define DP5_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
+//DP5_DP_DPHY_8B10B_CNTL
+#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
+#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
+#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
+//DP5_DP_DPHY_PRBS_CNTL
+#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
+#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
+#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
+//DP5_DP_DPHY_SCRAM_CNTL
+#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
+#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
+#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
+#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
+#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
+#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
+#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
+#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
+//DP5_DP_DPHY_CRC_EN
+#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
+#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
+#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
+//DP5_DP_DPHY_CRC_CNTL
+#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
+#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
+#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
+//DP5_DP_DPHY_CRC_RESULT
+#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
+#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
+#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
+#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
+//DP5_DP_DPHY_CRC_MST_CNTL
+#define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+#define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+#define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
+#define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
+//DP5_DP_DPHY_CRC_MST_STATUS
+#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
+#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
+#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
+//DP5_DP_DPHY_FAST_TRAINING
+#define DP5_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+#define DP5_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+#define DP5_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
+#define DP5_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
+#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
+#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
+#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
+//DP5_DP_DPHY_FAST_TRAINING_STATUS
+#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
+#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
+#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
+#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
+//DP5_DP_MSA_V_TIMING_OVERRIDE1
+#define DP5_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
+#define DP5_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
+#define DP5_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
+#define DP5_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0003FFF0L
+//DP5_DP_MSA_V_TIMING_OVERRIDE2
+#define DP5_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
+#define DP5_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
+#define DP5_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00003FFFL
+#define DP5_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3FFF0000L
+//DP5_DP_SEC_CNTL
+#define DP5_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+#define DP5_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+#define DP5_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+#define DP5_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+#define DP5_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+#define DP5_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
+#define DP5_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+#define DP5_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
+#define DP5_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
+#define DP5_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
+#define DP5_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
+#define DP5_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
+#define DP5_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
+#define DP5_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
+//DP5_DP_SEC_CNTL1
+#define DP5_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
+#define DP5_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
+//DP5_DP_SEC_FRAMING1
+#define DP5_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+#define DP5_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP5_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
+#define DP5_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP5_DP_SEC_FRAMING2
+#define DP5_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+#define DP5_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP5_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
+#define DP5_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP5_DP_SEC_FRAMING3
+#define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+#define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
+#define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP5_DP_SEC_FRAMING4
+#define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+#define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+#define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+#define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+#define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
+#define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
+#define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
+#define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
+//DP5_DP_SEC_AUD_N
+#define DP5_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+#define DP5_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
+//DP5_DP_SEC_AUD_N_READBACK
+#define DP5_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+#define DP5_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
+//DP5_DP_SEC_AUD_M
+#define DP5_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+#define DP5_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
+//DP5_DP_SEC_AUD_M_READBACK
+#define DP5_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+#define DP5_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
+//DP5_DP_SEC_TIMESTAMP
+#define DP5_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+#define DP5_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
+//DP5_DP_SEC_PACKET_CNTL
+#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
+#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
+#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
+#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
+//DP5_DP_MSE_RATE_CNTL
+#define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+#define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+#define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
+#define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
+//DP5_DP_MSE_RATE_UPDATE
+#define DP5_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+#define DP5_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
+//DP5_DP_MSE_SAT0
+#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
+#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
+#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
+#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
+//DP5_DP_MSE_SAT1
+#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
+#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
+#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
+#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
+//DP5_DP_MSE_SAT2
+#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
+#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
+#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
+#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
+//DP5_DP_MSE_SAT_UPDATE
+#define DP5_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+#define DP5_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+#define DP5_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
+#define DP5_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
+//DP5_DP_MSE_LINK_TIMING
+#define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+#define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+#define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
+#define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
+//DP5_DP_MSE_MISC_CNTL
+#define DP5_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+#define DP5_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+#define DP5_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+#define DP5_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
+#define DP5_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
+#define DP5_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
+//DP5_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
+#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
+#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
+#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
+#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
+#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
+//DP5_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP5_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
+#define DP5_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
+//DP5_DP_MSE_SAT0_STATUS
+#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
+#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
+#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
+#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
+#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
+#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
+#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
+#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
+//DP5_DP_MSE_SAT1_STATUS
+#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
+#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
+#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
+#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
+#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
+#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
+#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
+#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
+//DP5_DP_MSE_SAT2_STATUS
+#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
+#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
+#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
+#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
+#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
+#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
+#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
+#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
+
+
+// addressBlock: dce_dc_dig6_dispdec
+//DIG6_DIG_FE_CNTL
+#define DIG6_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+#define DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+#define DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+#define DIG6_DIG_FE_CNTL__DIG_START__SHIFT 0xa
+#define DIG6_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+#define DIG6_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+#define DIG6_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+#define DIG6_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
+#define DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
+#define DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
+#define DIG6_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
+#define DIG6_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
+#define DIG6_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
+#define DIG6_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
+//DIG6_DIG_OUTPUT_CRC_CNTL
+#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
+#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
+#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
+//DIG6_DIG_OUTPUT_CRC_RESULT
+#define DIG6_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+#define DIG6_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
+//DIG6_DIG_CLOCK_PATTERN
+#define DIG6_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+#define DIG6_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
+//DIG6_DIG_TEST_PATTERN
+#define DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+#define DIG6_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+#define DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+#define DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+#define DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+#define DIG6_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+#define DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
+#define DIG6_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
+#define DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
+#define DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
+#define DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
+#define DIG6_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
+//DIG6_DIG_RANDOM_PATTERN_SEED
+#define DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+#define DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+#define DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
+#define DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
+//DIG6_DIG_FIFO_STATUS
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+//DIG6_HDMI_CONTROL
+#define DIG6_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+#define DIG6_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
+#define DIG6_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+#define DIG6_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+#define DIG6_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+#define DIG6_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+#define DIG6_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+#define DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+#define DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+#define DIG6_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
+#define DIG6_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
+#define DIG6_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
+#define DIG6_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
+#define DIG6_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
+#define DIG6_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
+#define DIG6_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
+#define DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
+#define DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
+//DIG6_HDMI_STATUS
+#define DIG6_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+#define DIG6_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+#define DIG6_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+#define DIG6_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+#define DIG6_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
+#define DIG6_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
+#define DIG6_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
+#define DIG6_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
+//DIG6_HDMI_AUDIO_PACKET_CONTROL
+#define DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+#define DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+#define DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
+#define DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
+//DIG6_HDMI_ACR_PACKET_CONTROL
+#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
+#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
+#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
+#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
+#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
+#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
+#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
+//DIG6_HDMI_VBI_PACKET_CONTROL
+#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
+#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
+#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
+#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
+#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
+//DIG6_HDMI_INFOFRAME_CONTROL0
+#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
+#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
+#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
+#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
+#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
+#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
+#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
+#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
+//DIG6_HDMI_INFOFRAME_CONTROL1
+#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
+#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003FL
+#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
+#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
+//DIG6_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L
+//DIG6_AFMT_INTERRUPT_STATUS
+//DIG6_HDMI_GC
+#define DIG6_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+#define DIG6_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+#define DIG6_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+#define DIG6_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+#define DIG6_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+#define DIG6_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
+#define DIG6_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
+#define DIG6_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
+#define DIG6_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
+#define DIG6_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
+//DIG6_AFMT_AUDIO_PACKET_CONTROL2
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
+//DIG6_AFMT_ISRC1_0
+#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
+#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
+#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
+//DIG6_AFMT_ISRC1_1
+#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
+#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
+#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
+#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
+//DIG6_AFMT_ISRC1_2
+#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
+#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
+#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
+#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
+//DIG6_AFMT_ISRC1_3
+#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
+#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
+#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
+#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
+//DIG6_AFMT_ISRC1_4
+#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
+#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
+#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
+#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
+//DIG6_AFMT_ISRC2_0
+#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
+#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
+#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
+#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
+//DIG6_AFMT_ISRC2_1
+#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
+#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
+#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
+#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
+//DIG6_AFMT_ISRC2_2
+#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
+#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
+#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
+#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
+//DIG6_AFMT_ISRC2_3
+#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
+#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
+#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
+#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
+//DIG6_AFMT_AVI_INFO0
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000C00L
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x0000E000L
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000F0000L
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00C00000L
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0C000000L
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
+#define DIG6_AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
+//DIG6_AFMT_AVI_INFO1
+#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
+#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
+#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
+#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
+#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
+#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x000000FFL
+#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000F00L
+#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
+#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000C000L
+#define DIG6_AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xFFFF0000L
+//DIG6_AFMT_AVI_INFO2
+#define DIG6_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
+#define DIG6_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
+#define DIG6_AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000FFFFL
+#define DIG6_AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xFFFF0000L
+//DIG6_AFMT_AVI_INFO3
+#define DIG6_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
+#define DIG6_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
+#define DIG6_AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000FFFFL
+#define DIG6_AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xFF000000L
+//DIG6_AFMT_MPEG_INFO0
+#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
+#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
+#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
+//DIG6_AFMT_MPEG_INFO1
+#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
+#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
+#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
+//DIG6_AFMT_GENERIC_HDR
+#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
+#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
+#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
+#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
+//DIG6_AFMT_GENERIC_0
+#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
+#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
+#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
+#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
+//DIG6_AFMT_GENERIC_1
+#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
+#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
+#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
+#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
+//DIG6_AFMT_GENERIC_2
+#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
+#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
+#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
+#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
+//DIG6_AFMT_GENERIC_3
+#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
+#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
+#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
+#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
+//DIG6_AFMT_GENERIC_4
+#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
+#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
+#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
+#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
+//DIG6_AFMT_GENERIC_5
+#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
+#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
+#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
+#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
+//DIG6_AFMT_GENERIC_6
+#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
+#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
+#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
+#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
+//DIG6_AFMT_GENERIC_7
+#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
+#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
+#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
+#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
+//DIG6_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L
+#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L
+//DIG6_HDMI_ACR_32_0
+#define DIG6_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+#define DIG6_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
+//DIG6_HDMI_ACR_32_1
+#define DIG6_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+#define DIG6_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
+//DIG6_HDMI_ACR_44_0
+#define DIG6_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+#define DIG6_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
+//DIG6_HDMI_ACR_44_1
+#define DIG6_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+#define DIG6_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
+//DIG6_HDMI_ACR_48_0
+#define DIG6_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+#define DIG6_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
+//DIG6_HDMI_ACR_48_1
+#define DIG6_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+#define DIG6_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
+//DIG6_HDMI_ACR_STATUS_0
+#define DIG6_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+#define DIG6_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
+//DIG6_HDMI_ACR_STATUS_1
+#define DIG6_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+#define DIG6_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
+//DIG6_AFMT_AUDIO_INFO0
+#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
+#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
+#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
+#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
+//DIG6_AFMT_AUDIO_INFO1
+#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
+#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
+#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
+#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
+//DIG6_AFMT_60958_0
+#define DIG6_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+#define DIG6_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+#define DIG6_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+#define DIG6_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+#define DIG6_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+#define DIG6_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+#define DIG6_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+#define DIG6_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+#define DIG6_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+#define DIG6_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+#define DIG6_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
+#define DIG6_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
+#define DIG6_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
+#define DIG6_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
+#define DIG6_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
+#define DIG6_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
+#define DIG6_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
+#define DIG6_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
+#define DIG6_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
+#define DIG6_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
+//DIG6_AFMT_60958_1
+#define DIG6_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+#define DIG6_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+#define DIG6_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+#define DIG6_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+#define DIG6_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+#define DIG6_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
+#define DIG6_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
+#define DIG6_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
+#define DIG6_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
+#define DIG6_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
+//DIG6_AFMT_AUDIO_CRC_CONTROL
+#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
+#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
+#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
+#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
+#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
+//DIG6_AFMT_RAMP_CONTROL0
+#define DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+#define DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+#define DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
+#define DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
+//DIG6_AFMT_RAMP_CONTROL1
+#define DIG6_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+#define DIG6_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+#define DIG6_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
+#define DIG6_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
+//DIG6_AFMT_RAMP_CONTROL2
+#define DIG6_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+#define DIG6_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
+//DIG6_AFMT_RAMP_CONTROL3
+#define DIG6_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+#define DIG6_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
+//DIG6_AFMT_60958_2
+#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
+#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
+#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
+#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
+//DIG6_AFMT_AUDIO_CRC_RESULT
+#define DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+#define DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+#define DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
+#define DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
+//DIG6_AFMT_STATUS
+#define DIG6_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+#define DIG6_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+#define DIG6_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+#define DIG6_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+#define DIG6_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
+#define DIG6_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
+#define DIG6_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
+#define DIG6_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
+//DIG6_AFMT_AUDIO_PACKET_CONTROL
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
+#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
+//DIG6_AFMT_VBI_PACKET_CONTROL
+#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
+#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
+#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
+#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
+#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
+#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xC0000000L
+//DIG6_AFMT_INFOFRAME_CONTROL0
+#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
+#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
+#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
+//DIG6_AFMT_AUDIO_SRC_CONTROL
+#define DIG6_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+#define DIG6_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
+//DIG6_DIG_BE_CNTL
+#define DIG6_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+#define DIG6_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+#define DIG6_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+#define DIG6_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+#define DIG6_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+#define DIG6_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
+#define DIG6_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
+#define DIG6_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
+#define DIG6_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
+#define DIG6_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
+//DIG6_DIG_BE_EN_CNTL
+#define DIG6_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+#define DIG6_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+#define DIG6_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
+#define DIG6_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
+//DIG6_TMDS_CNTL
+#define DIG6_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+#define DIG6_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
+//DIG6_TMDS_CONTROL_CHAR
+#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
+#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
+#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
+#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
+//DIG6_TMDS_CONTROL0_FEEDBACK
+#define DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+#define DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+#define DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
+#define DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
+//DIG6_TMDS_STEREOSYNC_CTL_SEL
+#define DIG6_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+#define DIG6_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
+//DIG6_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+#define DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+#define DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
+#define DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
+//DIG6_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+#define DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+#define DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
+#define DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
+//DIG6_TMDS_CTL_BITS
+#define DIG6_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+#define DIG6_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+#define DIG6_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+#define DIG6_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+#define DIG6_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
+#define DIG6_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
+#define DIG6_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
+#define DIG6_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
+//DIG6_TMDS_DCBALANCER_CONTROL
+#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
+#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
+#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
+#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
+//DIG6_TMDS_CTL0_1_GEN_CNTL
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
+#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
+//DIG6_TMDS_CTL2_3_GEN_CNTL
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
+//DIG6_DIG_VERSION
+#define DIG6_DIG_VERSION__DIG_TYPE__SHIFT 0x0
+#define DIG6_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
+//DIG6_DIG_LANE_ENABLE
+#define DIG6_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+#define DIG6_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+#define DIG6_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+#define DIG6_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+#define DIG6_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+#define DIG6_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
+#define DIG6_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
+#define DIG6_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
+#define DIG6_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
+#define DIG6_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
+//DIG6_AFMT_CNTL
+#define DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
+#define DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
+#define DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
+#define DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
+
+
+// addressBlock: dce_dc_dp6_dispdec
+//DP6_DP_LINK_CNTL
+#define DP6_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+#define DP6_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+#define DP6_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+#define DP6_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
+#define DP6_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
+#define DP6_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
+//DP6_DP_PIXEL_FORMAT
+#define DP6_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+#define DP6_DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
+#define DP6_DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
+#define DP6_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+#define DP6_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
+#define DP6_DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
+#define DP6_DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
+#define DP6_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
+//DP6_DP_MSA_COLORIMETRY
+#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
+#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
+#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
+#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
+#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000FFL
+#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
+#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x00000200L
+#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x00020000L
+//DP6_DP_CONFIG
+#define DP6_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+#define DP6_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
+//DP6_DP_VID_STREAM_CNTL
+#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
+#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
+#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
+#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
+//DP6_DP_STEER_FIFO
+#define DP6_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+#define DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+#define DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+#define DP6_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
+#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
+#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
+#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
+#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
+#define DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
+#define DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
+//DP6_DP_MSA_MISC
+#define DP6_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
+#define DP6_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+#define DP6_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+#define DP6_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+#define DP6_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x00000078L
+#define DP6_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
+#define DP6_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
+#define DP6_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
+//DP6_DP_VID_TIMING
+#define DP6_DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
+#define DP6_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
+#define DP6_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+#define DP6_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
+#define DP6_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+#define DP6_DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
+#define DP6_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
+#define DP6_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
+#define DP6_DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x00000200L
+#define DP6_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
+//DP6_DP_VID_N
+#define DP6_DP_VID_N__DP_VID_N__SHIFT 0x0
+#define DP6_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
+//DP6_DP_VID_M
+#define DP6_DP_VID_M__DP_VID_M__SHIFT 0x0
+#define DP6_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
+//DP6_DP_LINK_FRAMING_CNTL
+#define DP6_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+#define DP6_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+#define DP6_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+#define DP6_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
+#define DP6_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
+#define DP6_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
+//DP6_DP_HBR2_EYE_PATTERN
+#define DP6_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+#define DP6_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
+//DP6_DP_VID_MSA_VBID
+#define DP6_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+#define DP6_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
+#define DP6_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+#define DP6_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
+#define DP6_DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
+#define DP6_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
+//DP6_DP_VID_INTERRUPT_CNTL
+#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
+#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
+#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
+//DP6_DP_DPHY_CNTL
+#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+#define DP6_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+#define DP6_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
+#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
+#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
+#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
+#define DP6_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
+#define DP6_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
+//DP6_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP6_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+#define DP6_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
+//DP6_DP_DPHY_SYM0
+#define DP6_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+#define DP6_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+#define DP6_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+#define DP6_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
+#define DP6_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
+#define DP6_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
+//DP6_DP_DPHY_SYM1
+#define DP6_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+#define DP6_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+#define DP6_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+#define DP6_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
+#define DP6_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
+#define DP6_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
+//DP6_DP_DPHY_SYM2
+#define DP6_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+#define DP6_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+#define DP6_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
+#define DP6_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
+//DP6_DP_DPHY_8B10B_CNTL
+#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
+#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
+#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
+//DP6_DP_DPHY_PRBS_CNTL
+#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
+#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
+#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
+//DP6_DP_DPHY_SCRAM_CNTL
+#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
+#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
+#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
+#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
+#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
+#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
+#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
+#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
+//DP6_DP_DPHY_CRC_EN
+#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
+#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
+#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
+//DP6_DP_DPHY_CRC_CNTL
+#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
+#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
+#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
+//DP6_DP_DPHY_CRC_RESULT
+#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
+#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
+#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
+#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
+//DP6_DP_DPHY_CRC_MST_CNTL
+#define DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+#define DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+#define DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
+#define DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
+//DP6_DP_DPHY_CRC_MST_STATUS
+#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
+#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
+#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
+//DP6_DP_DPHY_FAST_TRAINING
+#define DP6_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+#define DP6_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+#define DP6_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
+#define DP6_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
+#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
+#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
+#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
+//DP6_DP_DPHY_FAST_TRAINING_STATUS
+#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
+#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
+#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
+#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
+//DP6_DP_MSA_V_TIMING_OVERRIDE1
+#define DP6_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
+#define DP6_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
+#define DP6_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
+#define DP6_DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0003FFF0L
+//DP6_DP_MSA_V_TIMING_OVERRIDE2
+#define DP6_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
+#define DP6_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
+#define DP6_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00003FFFL
+#define DP6_DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3FFF0000L
+//DP6_DP_SEC_CNTL
+#define DP6_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+#define DP6_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+#define DP6_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+#define DP6_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+#define DP6_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+#define DP6_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+#define DP6_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+#define DP6_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+#define DP6_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+#define DP6_DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
+#define DP6_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+#define DP6_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
+#define DP6_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
+#define DP6_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
+#define DP6_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
+#define DP6_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
+#define DP6_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
+#define DP6_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
+#define DP6_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
+#define DP6_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
+#define DP6_DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
+#define DP6_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
+//DP6_DP_SEC_CNTL1
+#define DP6_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
+#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
+#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
+#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
+#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
+#define DP6_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
+#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
+#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
+#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
+#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
+#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
+//DP6_DP_SEC_FRAMING1
+#define DP6_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+#define DP6_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP6_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
+#define DP6_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP6_DP_SEC_FRAMING2
+#define DP6_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+#define DP6_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP6_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
+#define DP6_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP6_DP_SEC_FRAMING3
+#define DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+#define DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
+#define DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP6_DP_SEC_FRAMING4
+#define DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+#define DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+#define DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+#define DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+#define DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
+#define DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
+#define DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
+#define DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
+//DP6_DP_SEC_AUD_N
+#define DP6_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+#define DP6_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
+//DP6_DP_SEC_AUD_N_READBACK
+#define DP6_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+#define DP6_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
+//DP6_DP_SEC_AUD_M
+#define DP6_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+#define DP6_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
+//DP6_DP_SEC_AUD_M_READBACK
+#define DP6_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+#define DP6_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
+//DP6_DP_SEC_TIMESTAMP
+#define DP6_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+#define DP6_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
+//DP6_DP_SEC_PACKET_CNTL
+#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
+#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
+#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
+#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
+//DP6_DP_MSE_RATE_CNTL
+#define DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+#define DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+#define DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
+#define DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
+//DP6_DP_MSE_RATE_UPDATE
+#define DP6_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+#define DP6_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
+//DP6_DP_MSE_SAT0
+#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
+#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
+#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
+#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
+//DP6_DP_MSE_SAT1
+#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
+#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
+#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
+#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
+//DP6_DP_MSE_SAT2
+#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
+#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
+#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
+#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
+//DP6_DP_MSE_SAT_UPDATE
+#define DP6_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+#define DP6_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+#define DP6_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
+#define DP6_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
+//DP6_DP_MSE_LINK_TIMING
+#define DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+#define DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+#define DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
+#define DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
+//DP6_DP_MSE_MISC_CNTL
+#define DP6_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+#define DP6_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+#define DP6_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+#define DP6_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
+#define DP6_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
+#define DP6_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
+//DP6_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
+#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
+#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
+#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
+#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
+#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
+//DP6_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP6_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
+#define DP6_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
+//DP6_DP_MSE_SAT0_STATUS
+#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
+#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
+#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
+#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
+#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
+#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
+#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
+#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
+//DP6_DP_MSE_SAT1_STATUS
+#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
+#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
+#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
+#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
+#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
+#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
+#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
+#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
+//DP6_DP_MSE_SAT2_STATUS
+#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
+#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
+#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
+#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
+#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
+#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
+#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
+#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
+
+
+// addressBlock: dce_dc_dcio_uniphy0_dispdec
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophycmregs0_dispdec
+//DC_COMBOPHYCMREGS0_COMMON_FUSE1
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
+//DC_COMBOPHYCMREGS0_COMMON_FUSE2
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
+//DC_COMBOPHYCMREGS0_COMMON_FUSE3
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
+#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
+//DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM
+#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
+#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
+#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
+#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
+#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
+#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
+#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
+#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
+//DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
+//DC_COMBOPHYCMREGS0_COMMON_TXCNTRL
+#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
+#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
+#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
+#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
+#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
+#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
+#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
+#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
+#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
+#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
+#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
+#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
+#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
+#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
+//DC_COMBOPHYCMREGS0_COMMON_TMDP
+#define DC_COMBOPHYCMREGS0_COMMON_TMDP__tmdp_spare__SHIFT 0x0
+#define DC_COMBOPHYCMREGS0_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
+#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
+//DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL
+#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
+#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
+#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
+#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
+#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
+//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU1
+#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU2
+#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU3
+#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU4
+#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU5
+#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU6
+#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU7
+#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophytxregs0_dispdec
+//DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophypllregs0_dispdec
+//DC_COMBOPHYPLLREGS0_FREQ_CTRL0
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_int__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
+//DC_COMBOPHYPLLREGS0_FREQ_CTRL1
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_int__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
+//DC_COMBOPHYPLLREGS0_FREQ_CTRL2
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_denom__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
+//DC_COMBOPHYPLLREGS0_FREQ_CTRL3
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__refclk_div__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fracn_en__SHIFT 0x6
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__ssc_en__SHIFT 0x8
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fcw_sel__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__refclk_div_MASK 0x00000003L
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fracn_en_MASK 0x00000040L
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__ssc_en_MASK 0x00000100L
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
+#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
+//DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE
+#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
+#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
+#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
+#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
+#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
+#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
+#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
+//DC_COMBOPHYPLLREGS0_BW_CTRL_FINE
+#define DC_COMBOPHYPLLREGS0_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS0_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
+//DC_COMBOPHYPLLREGS0_CAL_CTRL
+#define DC_COMBOPHYPLLREGS0_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_en__SHIFT 0x1
+#define DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS0_CAL_CTRL__meas_win_sel__SHIFT 0x9
+#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
+#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_ratio__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
+#define DC_COMBOPHYPLLREGS0_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
+#define DC_COMBOPHYPLLREGS0_CAL_CTRL__refclk_rate__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS0_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
+#define DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
+#define DC_COMBOPHYPLLREGS0_CAL_CTRL__meas_win_sel_MASK 0x00000600L
+#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
+#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
+#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
+#define DC_COMBOPHYPLLREGS0_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
+#define DC_COMBOPHYPLLREGS0_CAL_CTRL__refclk_rate_MASK 0xFF000000L
+//DC_COMBOPHYPLLREGS0_LOOP_CTRL
+#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
+#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
+#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__prbs_en__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
+#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__phase_offset__SHIFT 0x14
+#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
+#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
+#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
+#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
+#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
+#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__prbs_en_MASK 0x00010000L
+#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
+#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__phase_offset_MASK 0x07F00000L
+//DC_COMBOPHYPLLREGS0_VREG_CFG
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_ac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_en__SHIFT 0x1
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__is_1p2__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_obs_sel__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_on_mode__SHIFT 0x5
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__rlad_tap_sel__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_hi__SHIFT 0xb
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_lo__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__scale_driver__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__sel_bump__SHIFT 0xf
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__sel_rladder_x__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__short_rc_filt_x__SHIFT 0x11
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__vref_pwr_on__SHIFT 0x12
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__dpll_cfg_2__SHIFT 0x14
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_ac_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_en_MASK 0x00000002L
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__is_1p2_MASK 0x00000004L
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_obs_sel_MASK 0x00000018L
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_on_mode_MASK 0x00000060L
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_hi_MASK 0x00000800L
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_lo_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__scale_driver_MASK 0x00006000L
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__sel_bump_MASK 0x00008000L
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__sel_rladder_x_MASK 0x00010000L
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__vref_pwr_on_MASK 0x00040000L
+#define DC_COMBOPHYPLLREGS0_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
+//DC_COMBOPHYPLLREGS0_OBSERVE0
+#define DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS0_OBSERVE0__clear_sticky_lock__SHIFT 0x6
+#define DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_dis__SHIFT 0x8
+#define DC_COMBOPHYPLLREGS0_OBSERVE0__dco_cfg__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS0_OBSERVE0__anaobs_sel__SHIFT 0x15
+#define DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
+#define DC_COMBOPHYPLLREGS0_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
+#define DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_dis_MASK 0x00000100L
+#define DC_COMBOPHYPLLREGS0_OBSERVE0__dco_cfg_MASK 0x0003FC00L
+#define DC_COMBOPHYPLLREGS0_OBSERVE0__anaobs_sel_MASK 0x00E00000L
+//DC_COMBOPHYPLLREGS0_OBSERVE1
+#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_sel__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_sel__SHIFT 0x5
+#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_div__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_div__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS0_OBSERVE1__lock_timer__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_sel_MASK 0x0000000FL
+#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
+#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_div_MASK 0x00000C00L
+#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_div_MASK 0x00006000L
+#define DC_COMBOPHYPLLREGS0_OBSERVE1__lock_timer_MASK 0x3FFF0000L
+//DC_COMBOPHYPLLREGS0_DFT_OUT
+#define DC_COMBOPHYPLLREGS0_DFT_OUT__dft_data__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS0_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_uniphy1_dispdec
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophycmregs1_dispdec
+//DC_COMBOPHYCMREGS1_COMMON_FUSE1
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
+//DC_COMBOPHYCMREGS1_COMMON_FUSE2
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
+//DC_COMBOPHYCMREGS1_COMMON_FUSE3
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
+#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
+//DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM
+#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
+#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
+#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
+#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
+#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
+#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
+#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
+#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
+//DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
+//DC_COMBOPHYCMREGS1_COMMON_TXCNTRL
+#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
+#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
+#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
+#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
+#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
+#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
+#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
+#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
+#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
+#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
+#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
+#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
+#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
+#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
+//DC_COMBOPHYCMREGS1_COMMON_TMDP
+#define DC_COMBOPHYCMREGS1_COMMON_TMDP__tmdp_spare__SHIFT 0x0
+#define DC_COMBOPHYCMREGS1_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
+#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
+//DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL
+#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
+#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
+#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
+#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
+#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
+//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU1
+#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU2
+#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU3
+#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU4
+#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU5
+#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU6
+#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU7
+#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophytxregs1_dispdec
+//DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophypllregs1_dispdec
+//DC_COMBOPHYPLLREGS1_FREQ_CTRL0
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_int__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
+//DC_COMBOPHYPLLREGS1_FREQ_CTRL1
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_int__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
+//DC_COMBOPHYPLLREGS1_FREQ_CTRL2
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_denom__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
+//DC_COMBOPHYPLLREGS1_FREQ_CTRL3
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__refclk_div__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fracn_en__SHIFT 0x6
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__ssc_en__SHIFT 0x8
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fcw_sel__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__refclk_div_MASK 0x00000003L
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fracn_en_MASK 0x00000040L
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__ssc_en_MASK 0x00000100L
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
+#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
+//DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE
+#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
+#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
+#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
+#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
+#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
+#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
+#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
+//DC_COMBOPHYPLLREGS1_BW_CTRL_FINE
+#define DC_COMBOPHYPLLREGS1_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS1_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
+//DC_COMBOPHYPLLREGS1_CAL_CTRL
+#define DC_COMBOPHYPLLREGS1_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_en__SHIFT 0x1
+#define DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS1_CAL_CTRL__meas_win_sel__SHIFT 0x9
+#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
+#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_ratio__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
+#define DC_COMBOPHYPLLREGS1_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
+#define DC_COMBOPHYPLLREGS1_CAL_CTRL__refclk_rate__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS1_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
+#define DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
+#define DC_COMBOPHYPLLREGS1_CAL_CTRL__meas_win_sel_MASK 0x00000600L
+#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
+#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
+#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
+#define DC_COMBOPHYPLLREGS1_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
+#define DC_COMBOPHYPLLREGS1_CAL_CTRL__refclk_rate_MASK 0xFF000000L
+//DC_COMBOPHYPLLREGS1_LOOP_CTRL
+#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
+#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
+#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__prbs_en__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
+#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__phase_offset__SHIFT 0x14
+#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
+#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
+#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
+#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
+#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
+#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__prbs_en_MASK 0x00010000L
+#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
+#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__phase_offset_MASK 0x07F00000L
+//DC_COMBOPHYPLLREGS1_VREG_CFG
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_ac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_en__SHIFT 0x1
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__is_1p2__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_obs_sel__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_on_mode__SHIFT 0x5
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__rlad_tap_sel__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_hi__SHIFT 0xb
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_lo__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__scale_driver__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__sel_bump__SHIFT 0xf
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__sel_rladder_x__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__short_rc_filt_x__SHIFT 0x11
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__vref_pwr_on__SHIFT 0x12
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__dpll_cfg_2__SHIFT 0x14
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_ac_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_en_MASK 0x00000002L
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__is_1p2_MASK 0x00000004L
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_obs_sel_MASK 0x00000018L
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_on_mode_MASK 0x00000060L
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_hi_MASK 0x00000800L
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_lo_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__scale_driver_MASK 0x00006000L
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__sel_bump_MASK 0x00008000L
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__sel_rladder_x_MASK 0x00010000L
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__vref_pwr_on_MASK 0x00040000L
+#define DC_COMBOPHYPLLREGS1_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
+//DC_COMBOPHYPLLREGS1_OBSERVE0
+#define DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS1_OBSERVE0__clear_sticky_lock__SHIFT 0x6
+#define DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_dis__SHIFT 0x8
+#define DC_COMBOPHYPLLREGS1_OBSERVE0__dco_cfg__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS1_OBSERVE0__anaobs_sel__SHIFT 0x15
+#define DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
+#define DC_COMBOPHYPLLREGS1_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
+#define DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_dis_MASK 0x00000100L
+#define DC_COMBOPHYPLLREGS1_OBSERVE0__dco_cfg_MASK 0x0003FC00L
+#define DC_COMBOPHYPLLREGS1_OBSERVE0__anaobs_sel_MASK 0x00E00000L
+//DC_COMBOPHYPLLREGS1_OBSERVE1
+#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_sel__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_sel__SHIFT 0x5
+#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_div__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_div__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS1_OBSERVE1__lock_timer__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_sel_MASK 0x0000000FL
+#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
+#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_div_MASK 0x00000C00L
+#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_div_MASK 0x00006000L
+#define DC_COMBOPHYPLLREGS1_OBSERVE1__lock_timer_MASK 0x3FFF0000L
+//DC_COMBOPHYPLLREGS1_DFT_OUT
+#define DC_COMBOPHYPLLREGS1_DFT_OUT__dft_data__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS1_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_uniphy2_dispdec
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophycmregs2_dispdec
+//DC_COMBOPHYCMREGS2_COMMON_FUSE1
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
+//DC_COMBOPHYCMREGS2_COMMON_FUSE2
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
+//DC_COMBOPHYCMREGS2_COMMON_FUSE3
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
+#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
+//DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM
+#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
+#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
+#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
+#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
+#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
+#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
+#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
+#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
+//DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
+//DC_COMBOPHYCMREGS2_COMMON_TXCNTRL
+#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
+#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
+#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
+#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
+#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
+#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
+#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
+#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
+#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
+#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
+#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
+#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
+#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
+#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
+//DC_COMBOPHYCMREGS2_COMMON_TMDP
+#define DC_COMBOPHYCMREGS2_COMMON_TMDP__tmdp_spare__SHIFT 0x0
+#define DC_COMBOPHYCMREGS2_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
+#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
+//DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL
+#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
+#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
+#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
+#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
+#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
+//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU1
+#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU2
+#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU3
+#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU4
+#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU5
+#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU6
+#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU7
+#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophytxregs2_dispdec
+//DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophypllregs2_dispdec
+//DC_COMBOPHYPLLREGS2_FREQ_CTRL0
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_int__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
+//DC_COMBOPHYPLLREGS2_FREQ_CTRL1
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_int__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
+//DC_COMBOPHYPLLREGS2_FREQ_CTRL2
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_denom__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
+//DC_COMBOPHYPLLREGS2_FREQ_CTRL3
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__refclk_div__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fracn_en__SHIFT 0x6
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__ssc_en__SHIFT 0x8
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fcw_sel__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__refclk_div_MASK 0x00000003L
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fracn_en_MASK 0x00000040L
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__ssc_en_MASK 0x00000100L
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
+#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
+//DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE
+#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
+#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
+#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
+#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
+#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
+#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
+#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
+//DC_COMBOPHYPLLREGS2_BW_CTRL_FINE
+#define DC_COMBOPHYPLLREGS2_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS2_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
+//DC_COMBOPHYPLLREGS2_CAL_CTRL
+#define DC_COMBOPHYPLLREGS2_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_en__SHIFT 0x1
+#define DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS2_CAL_CTRL__meas_win_sel__SHIFT 0x9
+#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
+#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_ratio__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
+#define DC_COMBOPHYPLLREGS2_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
+#define DC_COMBOPHYPLLREGS2_CAL_CTRL__refclk_rate__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS2_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
+#define DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
+#define DC_COMBOPHYPLLREGS2_CAL_CTRL__meas_win_sel_MASK 0x00000600L
+#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
+#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
+#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
+#define DC_COMBOPHYPLLREGS2_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
+#define DC_COMBOPHYPLLREGS2_CAL_CTRL__refclk_rate_MASK 0xFF000000L
+//DC_COMBOPHYPLLREGS2_LOOP_CTRL
+#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
+#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
+#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__prbs_en__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
+#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__phase_offset__SHIFT 0x14
+#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
+#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
+#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
+#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
+#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
+#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__prbs_en_MASK 0x00010000L
+#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
+#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__phase_offset_MASK 0x07F00000L
+//DC_COMBOPHYPLLREGS2_VREG_CFG
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_ac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_en__SHIFT 0x1
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__is_1p2__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_obs_sel__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_on_mode__SHIFT 0x5
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__rlad_tap_sel__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_hi__SHIFT 0xb
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_lo__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__scale_driver__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__sel_bump__SHIFT 0xf
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__sel_rladder_x__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__short_rc_filt_x__SHIFT 0x11
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__vref_pwr_on__SHIFT 0x12
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__dpll_cfg_2__SHIFT 0x14
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_ac_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_en_MASK 0x00000002L
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__is_1p2_MASK 0x00000004L
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_obs_sel_MASK 0x00000018L
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_on_mode_MASK 0x00000060L
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_hi_MASK 0x00000800L
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_lo_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__scale_driver_MASK 0x00006000L
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__sel_bump_MASK 0x00008000L
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__sel_rladder_x_MASK 0x00010000L
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__vref_pwr_on_MASK 0x00040000L
+#define DC_COMBOPHYPLLREGS2_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
+//DC_COMBOPHYPLLREGS2_OBSERVE0
+#define DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS2_OBSERVE0__clear_sticky_lock__SHIFT 0x6
+#define DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_dis__SHIFT 0x8
+#define DC_COMBOPHYPLLREGS2_OBSERVE0__dco_cfg__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS2_OBSERVE0__anaobs_sel__SHIFT 0x15
+#define DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
+#define DC_COMBOPHYPLLREGS2_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
+#define DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_dis_MASK 0x00000100L
+#define DC_COMBOPHYPLLREGS2_OBSERVE0__dco_cfg_MASK 0x0003FC00L
+#define DC_COMBOPHYPLLREGS2_OBSERVE0__anaobs_sel_MASK 0x00E00000L
+//DC_COMBOPHYPLLREGS2_OBSERVE1
+#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_sel__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_sel__SHIFT 0x5
+#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_div__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_div__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS2_OBSERVE1__lock_timer__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_sel_MASK 0x0000000FL
+#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
+#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_div_MASK 0x00000C00L
+#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_div_MASK 0x00006000L
+#define DC_COMBOPHYPLLREGS2_OBSERVE1__lock_timer_MASK 0x3FFF0000L
+//DC_COMBOPHYPLLREGS2_DFT_OUT
+#define DC_COMBOPHYPLLREGS2_DFT_OUT__dft_data__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS2_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_uniphy3_dispdec
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophycmregs3_dispdec
+//DC_COMBOPHYCMREGS3_COMMON_FUSE1
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
+//DC_COMBOPHYCMREGS3_COMMON_FUSE2
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
+//DC_COMBOPHYCMREGS3_COMMON_FUSE3
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
+#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
+//DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM
+#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
+#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
+#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
+#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
+#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
+#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
+#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
+#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
+//DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
+//DC_COMBOPHYCMREGS3_COMMON_TXCNTRL
+#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
+#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
+#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
+#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
+#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
+#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
+#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
+#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
+#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
+#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
+#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
+#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
+#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
+#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
+//DC_COMBOPHYCMREGS3_COMMON_TMDP
+#define DC_COMBOPHYCMREGS3_COMMON_TMDP__tmdp_spare__SHIFT 0x0
+#define DC_COMBOPHYCMREGS3_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
+#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
+//DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL
+#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
+#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
+#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
+#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
+#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
+//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU1
+#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU2
+#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU3
+#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU4
+#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU5
+#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU6
+#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU7
+#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophytxregs3_dispdec
+//DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophypllregs3_dispdec
+//DC_COMBOPHYPLLREGS3_FREQ_CTRL0
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_int__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
+//DC_COMBOPHYPLLREGS3_FREQ_CTRL1
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_int__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
+//DC_COMBOPHYPLLREGS3_FREQ_CTRL2
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_denom__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
+//DC_COMBOPHYPLLREGS3_FREQ_CTRL3
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__refclk_div__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fracn_en__SHIFT 0x6
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__ssc_en__SHIFT 0x8
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fcw_sel__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__refclk_div_MASK 0x00000003L
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fracn_en_MASK 0x00000040L
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__ssc_en_MASK 0x00000100L
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
+#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
+//DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE
+#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
+#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
+#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
+#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
+#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
+#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
+#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
+//DC_COMBOPHYPLLREGS3_BW_CTRL_FINE
+#define DC_COMBOPHYPLLREGS3_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS3_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
+//DC_COMBOPHYPLLREGS3_CAL_CTRL
+#define DC_COMBOPHYPLLREGS3_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_en__SHIFT 0x1
+#define DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS3_CAL_CTRL__meas_win_sel__SHIFT 0x9
+#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
+#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_ratio__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
+#define DC_COMBOPHYPLLREGS3_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
+#define DC_COMBOPHYPLLREGS3_CAL_CTRL__refclk_rate__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS3_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
+#define DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
+#define DC_COMBOPHYPLLREGS3_CAL_CTRL__meas_win_sel_MASK 0x00000600L
+#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
+#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
+#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
+#define DC_COMBOPHYPLLREGS3_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
+#define DC_COMBOPHYPLLREGS3_CAL_CTRL__refclk_rate_MASK 0xFF000000L
+//DC_COMBOPHYPLLREGS3_LOOP_CTRL
+#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
+#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
+#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__prbs_en__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
+#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__phase_offset__SHIFT 0x14
+#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
+#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
+#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
+#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
+#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
+#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__prbs_en_MASK 0x00010000L
+#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
+#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__phase_offset_MASK 0x07F00000L
+//DC_COMBOPHYPLLREGS3_VREG_CFG
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_ac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_en__SHIFT 0x1
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__is_1p2__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_obs_sel__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_on_mode__SHIFT 0x5
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__rlad_tap_sel__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_hi__SHIFT 0xb
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_lo__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__scale_driver__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__sel_bump__SHIFT 0xf
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__sel_rladder_x__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__short_rc_filt_x__SHIFT 0x11
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__vref_pwr_on__SHIFT 0x12
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__dpll_cfg_2__SHIFT 0x14
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_ac_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_en_MASK 0x00000002L
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__is_1p2_MASK 0x00000004L
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_obs_sel_MASK 0x00000018L
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_on_mode_MASK 0x00000060L
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_hi_MASK 0x00000800L
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_lo_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__scale_driver_MASK 0x00006000L
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__sel_bump_MASK 0x00008000L
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__sel_rladder_x_MASK 0x00010000L
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__vref_pwr_on_MASK 0x00040000L
+#define DC_COMBOPHYPLLREGS3_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
+//DC_COMBOPHYPLLREGS3_OBSERVE0
+#define DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS3_OBSERVE0__clear_sticky_lock__SHIFT 0x6
+#define DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_dis__SHIFT 0x8
+#define DC_COMBOPHYPLLREGS3_OBSERVE0__dco_cfg__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS3_OBSERVE0__anaobs_sel__SHIFT 0x15
+#define DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
+#define DC_COMBOPHYPLLREGS3_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
+#define DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_dis_MASK 0x00000100L
+#define DC_COMBOPHYPLLREGS3_OBSERVE0__dco_cfg_MASK 0x0003FC00L
+#define DC_COMBOPHYPLLREGS3_OBSERVE0__anaobs_sel_MASK 0x00E00000L
+//DC_COMBOPHYPLLREGS3_OBSERVE1
+#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_sel__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_sel__SHIFT 0x5
+#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_div__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_div__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS3_OBSERVE1__lock_timer__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_sel_MASK 0x0000000FL
+#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
+#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_div_MASK 0x00000C00L
+#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_div_MASK 0x00006000L
+#define DC_COMBOPHYPLLREGS3_OBSERVE1__lock_timer_MASK 0x3FFF0000L
+//DC_COMBOPHYPLLREGS3_DFT_OUT
+#define DC_COMBOPHYPLLREGS3_DFT_OUT__dft_data__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS3_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_uniphy4_dispdec
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophycmregs4_dispdec
+//DC_COMBOPHYCMREGS4_COMMON_FUSE1
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
+//DC_COMBOPHYCMREGS4_COMMON_FUSE2
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
+//DC_COMBOPHYCMREGS4_COMMON_FUSE3
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
+#define DC_COMBOPHYCMREGS4_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
+//DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM
+#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
+#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
+#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
+#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
+#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
+#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
+#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
+#define DC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
+//DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
+//DC_COMBOPHYCMREGS4_COMMON_TXCNTRL
+#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
+#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
+#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
+#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
+#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
+#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
+#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
+#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
+#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
+#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
+#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
+#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
+#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
+#define DC_COMBOPHYCMREGS4_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
+//DC_COMBOPHYCMREGS4_COMMON_TMDP
+#define DC_COMBOPHYCMREGS4_COMMON_TMDP__tmdp_spare__SHIFT 0x0
+#define DC_COMBOPHYCMREGS4_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
+#define DC_COMBOPHYCMREGS4_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
+//DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL
+#define DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
+#define DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
+#define DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
+#define DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
+#define DC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
+//DC_COMBOPHYCMREGS4_COMMON_DISP_RFU1
+#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS4_COMMON_DISP_RFU2
+#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS4_COMMON_DISP_RFU3
+#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS4_COMMON_DISP_RFU4
+#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS4_COMMON_DISP_RFU5
+#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS4_COMMON_DISP_RFU6
+#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS4_COMMON_DISP_RFU7
+#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYCMREGS4_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophytxregs4_dispdec
+//DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophypllregs4_dispdec
+//DC_COMBOPHYPLLREGS4_FREQ_CTRL0
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL0__fcw0_int__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
+//DC_COMBOPHYPLLREGS4_FREQ_CTRL1
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL1__fcw1_int__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
+//DC_COMBOPHYPLLREGS4_FREQ_CTRL2
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL2__fcw_denom__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
+//DC_COMBOPHYPLLREGS4_FREQ_CTRL3
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__refclk_div__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__fracn_en__SHIFT 0x6
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__ssc_en__SHIFT 0x8
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__fcw_sel__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__refclk_div_MASK 0x00000003L
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__fracn_en_MASK 0x00000040L
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__ssc_en_MASK 0x00000100L
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
+#define DC_COMBOPHYPLLREGS4_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
+//DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE
+#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
+#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
+#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
+#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
+#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
+#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
+#define DC_COMBOPHYPLLREGS4_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
+//DC_COMBOPHYPLLREGS4_BW_CTRL_FINE
+#define DC_COMBOPHYPLLREGS4_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS4_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
+//DC_COMBOPHYPLLREGS4_CAL_CTRL
+#define DC_COMBOPHYPLLREGS4_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS4_CAL_CTRL__tdc_cal_en__SHIFT 0x1
+#define DC_COMBOPHYPLLREGS4_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS4_CAL_CTRL__meas_win_sel__SHIFT 0x9
+#define DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
+#define DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_ratio__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
+#define DC_COMBOPHYPLLREGS4_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
+#define DC_COMBOPHYPLLREGS4_CAL_CTRL__refclk_rate__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS4_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS4_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
+#define DC_COMBOPHYPLLREGS4_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
+#define DC_COMBOPHYPLLREGS4_CAL_CTRL__meas_win_sel_MASK 0x00000600L
+#define DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
+#define DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
+#define DC_COMBOPHYPLLREGS4_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
+#define DC_COMBOPHYPLLREGS4_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
+#define DC_COMBOPHYPLLREGS4_CAL_CTRL__refclk_rate_MASK 0xFF000000L
+//DC_COMBOPHYPLLREGS4_LOOP_CTRL
+#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
+#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
+#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__prbs_en__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
+#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__phase_offset__SHIFT 0x14
+#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
+#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
+#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
+#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
+#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
+#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__prbs_en_MASK 0x00010000L
+#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
+#define DC_COMBOPHYPLLREGS4_LOOP_CTRL__phase_offset_MASK 0x07F00000L
+//DC_COMBOPHYPLLREGS4_VREG_CFG
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__bleeder_ac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__bleeder_en__SHIFT 0x1
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__is_1p2__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_obs_sel__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_on_mode__SHIFT 0x5
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__rlad_tap_sel__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_off_hi__SHIFT 0xb
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_off_lo__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__scale_driver__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__sel_bump__SHIFT 0xf
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__sel_rladder_x__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__short_rc_filt_x__SHIFT 0x11
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__vref_pwr_on__SHIFT 0x12
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__dpll_cfg_2__SHIFT 0x14
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__bleeder_ac_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__bleeder_en_MASK 0x00000002L
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__is_1p2_MASK 0x00000004L
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_obs_sel_MASK 0x00000018L
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_on_mode_MASK 0x00000060L
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_off_hi_MASK 0x00000800L
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__reg_off_lo_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__scale_driver_MASK 0x00006000L
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__sel_bump_MASK 0x00008000L
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__sel_rladder_x_MASK 0x00010000L
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__vref_pwr_on_MASK 0x00040000L
+#define DC_COMBOPHYPLLREGS4_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
+//DC_COMBOPHYPLLREGS4_OBSERVE0
+#define DC_COMBOPHYPLLREGS4_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS4_OBSERVE0__clear_sticky_lock__SHIFT 0x6
+#define DC_COMBOPHYPLLREGS4_OBSERVE0__lock_det_dis__SHIFT 0x8
+#define DC_COMBOPHYPLLREGS4_OBSERVE0__dco_cfg__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS4_OBSERVE0__anaobs_sel__SHIFT 0x15
+#define DC_COMBOPHYPLLREGS4_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
+#define DC_COMBOPHYPLLREGS4_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
+#define DC_COMBOPHYPLLREGS4_OBSERVE0__lock_det_dis_MASK 0x00000100L
+#define DC_COMBOPHYPLLREGS4_OBSERVE0__dco_cfg_MASK 0x0003FC00L
+#define DC_COMBOPHYPLLREGS4_OBSERVE0__anaobs_sel_MASK 0x00E00000L
+//DC_COMBOPHYPLLREGS4_OBSERVE1
+#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_sel__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_trig_sel__SHIFT 0x5
+#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_div__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_trig_div__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS4_OBSERVE1__lock_timer__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_sel_MASK 0x0000000FL
+#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
+#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_div_MASK 0x00000C00L
+#define DC_COMBOPHYPLLREGS4_OBSERVE1__digobs_trig_div_MASK 0x00006000L
+#define DC_COMBOPHYPLLREGS4_OBSERVE1__lock_timer_MASK 0x3FFF0000L
+//DC_COMBOPHYPLLREGS4_DFT_OUT
+#define DC_COMBOPHYPLLREGS4_DFT_OUT__dft_data__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS4_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_uniphy5_dispdec
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophycmregs5_dispdec
+//DC_COMBOPHYCMREGS5_COMMON_FUSE1
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
+//DC_COMBOPHYCMREGS5_COMMON_FUSE2
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
+//DC_COMBOPHYCMREGS5_COMMON_FUSE3
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
+#define DC_COMBOPHYCMREGS5_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
+//DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM
+#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
+#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
+#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
+#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
+#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
+#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
+#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
+#define DC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
+//DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
+//DC_COMBOPHYCMREGS5_COMMON_TXCNTRL
+#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
+#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
+#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
+#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
+#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
+#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
+#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
+#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
+#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
+#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
+#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
+#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
+#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
+#define DC_COMBOPHYCMREGS5_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
+//DC_COMBOPHYCMREGS5_COMMON_TMDP
+#define DC_COMBOPHYCMREGS5_COMMON_TMDP__tmdp_spare__SHIFT 0x0
+#define DC_COMBOPHYCMREGS5_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
+#define DC_COMBOPHYCMREGS5_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
+//DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL
+#define DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
+#define DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
+#define DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
+#define DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
+#define DC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
+//DC_COMBOPHYCMREGS5_COMMON_DISP_RFU1
+#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS5_COMMON_DISP_RFU2
+#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS5_COMMON_DISP_RFU3
+#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS5_COMMON_DISP_RFU4
+#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS5_COMMON_DISP_RFU5
+#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS5_COMMON_DISP_RFU6
+#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS5_COMMON_DISP_RFU7
+#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYCMREGS5_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophytxregs5_dispdec
+//DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophypllregs5_dispdec
+//DC_COMBOPHYPLLREGS5_FREQ_CTRL0
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL0__fcw0_int__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
+//DC_COMBOPHYPLLREGS5_FREQ_CTRL1
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL1__fcw1_int__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
+//DC_COMBOPHYPLLREGS5_FREQ_CTRL2
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL2__fcw_denom__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
+//DC_COMBOPHYPLLREGS5_FREQ_CTRL3
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__refclk_div__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__fracn_en__SHIFT 0x6
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__ssc_en__SHIFT 0x8
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__fcw_sel__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__refclk_div_MASK 0x00000003L
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__fracn_en_MASK 0x00000040L
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__ssc_en_MASK 0x00000100L
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
+#define DC_COMBOPHYPLLREGS5_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
+//DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE
+#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
+#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
+#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
+#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
+#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
+#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
+#define DC_COMBOPHYPLLREGS5_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
+//DC_COMBOPHYPLLREGS5_BW_CTRL_FINE
+#define DC_COMBOPHYPLLREGS5_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS5_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
+//DC_COMBOPHYPLLREGS5_CAL_CTRL
+#define DC_COMBOPHYPLLREGS5_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS5_CAL_CTRL__tdc_cal_en__SHIFT 0x1
+#define DC_COMBOPHYPLLREGS5_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS5_CAL_CTRL__meas_win_sel__SHIFT 0x9
+#define DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
+#define DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_ratio__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
+#define DC_COMBOPHYPLLREGS5_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
+#define DC_COMBOPHYPLLREGS5_CAL_CTRL__refclk_rate__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS5_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS5_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
+#define DC_COMBOPHYPLLREGS5_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
+#define DC_COMBOPHYPLLREGS5_CAL_CTRL__meas_win_sel_MASK 0x00000600L
+#define DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
+#define DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
+#define DC_COMBOPHYPLLREGS5_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
+#define DC_COMBOPHYPLLREGS5_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
+#define DC_COMBOPHYPLLREGS5_CAL_CTRL__refclk_rate_MASK 0xFF000000L
+//DC_COMBOPHYPLLREGS5_LOOP_CTRL
+#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
+#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
+#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__prbs_en__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
+#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__phase_offset__SHIFT 0x14
+#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
+#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
+#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
+#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
+#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
+#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__prbs_en_MASK 0x00010000L
+#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
+#define DC_COMBOPHYPLLREGS5_LOOP_CTRL__phase_offset_MASK 0x07F00000L
+//DC_COMBOPHYPLLREGS5_VREG_CFG
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__bleeder_ac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__bleeder_en__SHIFT 0x1
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__is_1p2__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_obs_sel__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_on_mode__SHIFT 0x5
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__rlad_tap_sel__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_off_hi__SHIFT 0xb
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_off_lo__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__scale_driver__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__sel_bump__SHIFT 0xf
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__sel_rladder_x__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__short_rc_filt_x__SHIFT 0x11
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__vref_pwr_on__SHIFT 0x12
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__dpll_cfg_2__SHIFT 0x14
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__bleeder_ac_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__bleeder_en_MASK 0x00000002L
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__is_1p2_MASK 0x00000004L
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_obs_sel_MASK 0x00000018L
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_on_mode_MASK 0x00000060L
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_off_hi_MASK 0x00000800L
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__reg_off_lo_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__scale_driver_MASK 0x00006000L
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__sel_bump_MASK 0x00008000L
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__sel_rladder_x_MASK 0x00010000L
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__vref_pwr_on_MASK 0x00040000L
+#define DC_COMBOPHYPLLREGS5_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
+//DC_COMBOPHYPLLREGS5_OBSERVE0
+#define DC_COMBOPHYPLLREGS5_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS5_OBSERVE0__clear_sticky_lock__SHIFT 0x6
+#define DC_COMBOPHYPLLREGS5_OBSERVE0__lock_det_dis__SHIFT 0x8
+#define DC_COMBOPHYPLLREGS5_OBSERVE0__dco_cfg__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS5_OBSERVE0__anaobs_sel__SHIFT 0x15
+#define DC_COMBOPHYPLLREGS5_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
+#define DC_COMBOPHYPLLREGS5_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
+#define DC_COMBOPHYPLLREGS5_OBSERVE0__lock_det_dis_MASK 0x00000100L
+#define DC_COMBOPHYPLLREGS5_OBSERVE0__dco_cfg_MASK 0x0003FC00L
+#define DC_COMBOPHYPLLREGS5_OBSERVE0__anaobs_sel_MASK 0x00E00000L
+//DC_COMBOPHYPLLREGS5_OBSERVE1
+#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_sel__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_trig_sel__SHIFT 0x5
+#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_div__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_trig_div__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS5_OBSERVE1__lock_timer__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_sel_MASK 0x0000000FL
+#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
+#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_div_MASK 0x00000C00L
+#define DC_COMBOPHYPLLREGS5_OBSERVE1__digobs_trig_div_MASK 0x00006000L
+#define DC_COMBOPHYPLLREGS5_OBSERVE1__lock_timer_MASK 0x3FFF0000L
+//DC_COMBOPHYPLLREGS5_DFT_OUT
+#define DC_COMBOPHYPLLREGS5_DFT_OUT__dft_data__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS5_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_uniphy6_dispdec
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophycmregs6_dispdec
+//DC_COMBOPHYCMREGS6_COMMON_FUSE1
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
+//DC_COMBOPHYCMREGS6_COMMON_FUSE2
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
+//DC_COMBOPHYCMREGS6_COMMON_FUSE3
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
+#define DC_COMBOPHYCMREGS6_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
+//DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM
+#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
+#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
+#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
+#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
+#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
+#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
+#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
+#define DC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
+//DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
+//DC_COMBOPHYCMREGS6_COMMON_TXCNTRL
+#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
+#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
+#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
+#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
+#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
+#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
+#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
+#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
+#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
+#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
+#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
+#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
+#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
+#define DC_COMBOPHYCMREGS6_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
+//DC_COMBOPHYCMREGS6_COMMON_TMDP
+#define DC_COMBOPHYCMREGS6_COMMON_TMDP__tmdp_spare__SHIFT 0x0
+#define DC_COMBOPHYCMREGS6_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
+#define DC_COMBOPHYCMREGS6_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
+//DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL
+#define DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
+#define DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
+#define DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
+#define DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
+#define DC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
+//DC_COMBOPHYCMREGS6_COMMON_DISP_RFU1
+#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS6_COMMON_DISP_RFU2
+#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS6_COMMON_DISP_RFU3
+#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS6_COMMON_DISP_RFU4
+#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS6_COMMON_DISP_RFU5
+#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS6_COMMON_DISP_RFU6
+#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS6_COMMON_DISP_RFU7
+#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYCMREGS6_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophytxregs6_dispdec
+//DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophypllregs6_dispdec
+//DC_COMBOPHYPLLREGS6_FREQ_CTRL0
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL0__fcw0_int__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
+//DC_COMBOPHYPLLREGS6_FREQ_CTRL1
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL1__fcw1_int__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
+//DC_COMBOPHYPLLREGS6_FREQ_CTRL2
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL2__fcw_denom__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
+//DC_COMBOPHYPLLREGS6_FREQ_CTRL3
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__refclk_div__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__fracn_en__SHIFT 0x6
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__ssc_en__SHIFT 0x8
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__fcw_sel__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__refclk_div_MASK 0x00000003L
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__fracn_en_MASK 0x00000040L
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__ssc_en_MASK 0x00000100L
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
+#define DC_COMBOPHYPLLREGS6_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
+//DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE
+#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
+#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
+#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
+#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
+#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
+#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
+#define DC_COMBOPHYPLLREGS6_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
+//DC_COMBOPHYPLLREGS6_BW_CTRL_FINE
+#define DC_COMBOPHYPLLREGS6_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS6_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
+//DC_COMBOPHYPLLREGS6_CAL_CTRL
+#define DC_COMBOPHYPLLREGS6_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS6_CAL_CTRL__tdc_cal_en__SHIFT 0x1
+#define DC_COMBOPHYPLLREGS6_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS6_CAL_CTRL__meas_win_sel__SHIFT 0x9
+#define DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
+#define DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_ratio__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
+#define DC_COMBOPHYPLLREGS6_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
+#define DC_COMBOPHYPLLREGS6_CAL_CTRL__refclk_rate__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS6_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS6_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
+#define DC_COMBOPHYPLLREGS6_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
+#define DC_COMBOPHYPLLREGS6_CAL_CTRL__meas_win_sel_MASK 0x00000600L
+#define DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
+#define DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
+#define DC_COMBOPHYPLLREGS6_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
+#define DC_COMBOPHYPLLREGS6_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
+#define DC_COMBOPHYPLLREGS6_CAL_CTRL__refclk_rate_MASK 0xFF000000L
+//DC_COMBOPHYPLLREGS6_LOOP_CTRL
+#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
+#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
+#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__prbs_en__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
+#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__phase_offset__SHIFT 0x14
+#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
+#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
+#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
+#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
+#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
+#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__prbs_en_MASK 0x00010000L
+#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
+#define DC_COMBOPHYPLLREGS6_LOOP_CTRL__phase_offset_MASK 0x07F00000L
+//DC_COMBOPHYPLLREGS6_VREG_CFG
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__bleeder_ac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__bleeder_en__SHIFT 0x1
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__is_1p2__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_obs_sel__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_on_mode__SHIFT 0x5
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__rlad_tap_sel__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_off_hi__SHIFT 0xb
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_off_lo__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__scale_driver__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__sel_bump__SHIFT 0xf
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__sel_rladder_x__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__short_rc_filt_x__SHIFT 0x11
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__vref_pwr_on__SHIFT 0x12
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__dpll_cfg_2__SHIFT 0x14
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__bleeder_ac_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__bleeder_en_MASK 0x00000002L
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__is_1p2_MASK 0x00000004L
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_obs_sel_MASK 0x00000018L
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_on_mode_MASK 0x00000060L
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_off_hi_MASK 0x00000800L
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__reg_off_lo_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__scale_driver_MASK 0x00006000L
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__sel_bump_MASK 0x00008000L
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__sel_rladder_x_MASK 0x00010000L
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__vref_pwr_on_MASK 0x00040000L
+#define DC_COMBOPHYPLLREGS6_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
+//DC_COMBOPHYPLLREGS6_OBSERVE0
+#define DC_COMBOPHYPLLREGS6_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS6_OBSERVE0__clear_sticky_lock__SHIFT 0x6
+#define DC_COMBOPHYPLLREGS6_OBSERVE0__lock_det_dis__SHIFT 0x8
+#define DC_COMBOPHYPLLREGS6_OBSERVE0__dco_cfg__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS6_OBSERVE0__anaobs_sel__SHIFT 0x15
+#define DC_COMBOPHYPLLREGS6_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
+#define DC_COMBOPHYPLLREGS6_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
+#define DC_COMBOPHYPLLREGS6_OBSERVE0__lock_det_dis_MASK 0x00000100L
+#define DC_COMBOPHYPLLREGS6_OBSERVE0__dco_cfg_MASK 0x0003FC00L
+#define DC_COMBOPHYPLLREGS6_OBSERVE0__anaobs_sel_MASK 0x00E00000L
+//DC_COMBOPHYPLLREGS6_OBSERVE1
+#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_sel__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_trig_sel__SHIFT 0x5
+#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_div__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_trig_div__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS6_OBSERVE1__lock_timer__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_sel_MASK 0x0000000FL
+#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
+#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_div_MASK 0x00000C00L
+#define DC_COMBOPHYPLLREGS6_OBSERVE1__digobs_trig_div_MASK 0x00006000L
+#define DC_COMBOPHYPLLREGS6_OBSERVE1__lock_timer_MASK 0x3FFF0000L
+//DC_COMBOPHYPLLREGS6_DFT_OUT
+#define DC_COMBOPHYPLLREGS6_DFT_OUT__dft_data__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS6_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_uniphy8_dispdec
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophycmregs8_dispdec
+//DC_COMBOPHYCMREGS8_COMMON_FUSE1
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_spare__SHIFT 0x17
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L
+//DC_COMBOPHYCMREGS8_COMMON_FUSE2
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_spare__SHIFT 0xe
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L
+//DC_COMBOPHYCMREGS8_COMMON_FUSE3
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L
+#define DC_COMBOPHYCMREGS8_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L
+//DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM
+#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
+#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
+#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
+#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
+#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL
+#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L
+#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L
+#define DC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L
+//DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L
+//DC_COMBOPHYCMREGS8_COMMON_TXCNTRL
+#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
+#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
+#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
+#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
+#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
+#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
+#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
+#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL
+#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L
+#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L
+#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L
+#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L
+#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x00008000L
+#define DC_COMBOPHYCMREGS8_COMMON_TXCNTRL__dual_dvi_en_MASK 0x00010000L
+//DC_COMBOPHYCMREGS8_COMMON_TMDP
+#define DC_COMBOPHYCMREGS8_COMMON_TMDP__tmdp_spare__SHIFT 0x0
+#define DC_COMBOPHYCMREGS8_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L
+#define DC_COMBOPHYCMREGS8_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L
+//DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL
+#define DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
+#define DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
+#define DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
+#define DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L
+#define DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL
+#define DC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L
+//DC_COMBOPHYCMREGS8_COMMON_DISP_RFU1
+#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS8_COMMON_DISP_RFU2
+#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS8_COMMON_DISP_RFU3
+#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS8_COMMON_DISP_RFU4
+#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS8_COMMON_DISP_RFU5
+#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS8_COMMON_DISP_RFU6
+#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYCMREGS8_COMMON_DISP_RFU7
+#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYCMREGS8_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophytxregs8_dispdec
+//DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L
+//DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L
+//DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L
+#define DC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL
+//DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
+#define DC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_combophypllregs8_dispdec
+//DC_COMBOPHYPLLREGS8_FREQ_CTRL0
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL0__fcw0_frac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL0__fcw0_int__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L
+//DC_COMBOPHYPLLREGS8_FREQ_CTRL1
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL1__fcw1_frac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL1__fcw1_int__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L
+//DC_COMBOPHYPLLREGS8_FREQ_CTRL2
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL2__fcw_denom__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L
+//DC_COMBOPHYPLLREGS8_FREQ_CTRL3
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__refclk_div__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__vco_pre_div__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__fracn_en__SHIFT 0x6
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__ssc_en__SHIFT 0x8
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__fcw_sel__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__freq_jump_en__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__tdc_resolution__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__refclk_div_MASK 0x00000003L
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__fracn_en_MASK 0x00000040L
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__ssc_en_MASK 0x00000100L
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__fcw_sel_MASK 0x00000400L
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L
+#define DC_COMBOPHYPLLREGS8_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L
+//DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE
+#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
+#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L
+#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL
+#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L
+#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L
+#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L
+#define DC_COMBOPHYPLLREGS8_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L
+//DC_COMBOPHYPLLREGS8_BW_CTRL_FINE
+#define DC_COMBOPHYPLLREGS8_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS8_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL
+//DC_COMBOPHYPLLREGS8_CAL_CTRL
+#define DC_COMBOPHYPLLREGS8_CAL_CTRL__bypass_freq_lock__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS8_CAL_CTRL__tdc_cal_en__SHIFT 0x1
+#define DC_COMBOPHYPLLREGS8_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS8_CAL_CTRL__meas_win_sel__SHIFT 0x9
+#define DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_cal_dis__SHIFT 0xb
+#define DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_ratio__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
+#define DC_COMBOPHYPLLREGS8_CAL_CTRL__nctl_adj_dis__SHIFT 0x17
+#define DC_COMBOPHYPLLREGS8_CAL_CTRL__refclk_rate__SHIFT 0x18
+#define DC_COMBOPHYPLLREGS8_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS8_CAL_CTRL__tdc_cal_en_MASK 0x00000002L
+#define DC_COMBOPHYPLLREGS8_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L
+#define DC_COMBOPHYPLLREGS8_CAL_CTRL__meas_win_sel_MASK 0x00000600L
+#define DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L
+#define DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_ratio_MASK 0x001FE000L
+#define DC_COMBOPHYPLLREGS8_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L
+#define DC_COMBOPHYPLLREGS8_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L
+#define DC_COMBOPHYPLLREGS8_CAL_CTRL__refclk_rate_MASK 0xFF000000L
+//DC_COMBOPHYPLLREGS8_LOOP_CTRL
+#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__fb_slip_dis__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
+#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
+#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__prbs_en__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
+#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__phase_offset__SHIFT 0x14
+#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L
+#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L
+#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L
+#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L
+#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L
+#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__prbs_en_MASK 0x00010000L
+#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L
+#define DC_COMBOPHYPLLREGS8_LOOP_CTRL__phase_offset_MASK 0x07F00000L
+//DC_COMBOPHYPLLREGS8_VREG_CFG
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__bleeder_ac__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__bleeder_en__SHIFT 0x1
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__is_1p2__SHIFT 0x2
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_obs_sel__SHIFT 0x3
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_on_mode__SHIFT 0x5
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__rlad_tap_sel__SHIFT 0x7
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_off_hi__SHIFT 0xb
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_off_lo__SHIFT 0xc
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__scale_driver__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__sel_bump__SHIFT 0xf
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__sel_rladder_x__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__short_rc_filt_x__SHIFT 0x11
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__vref_pwr_on__SHIFT 0x12
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__dpll_cfg_2__SHIFT 0x14
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__bleeder_ac_MASK 0x00000001L
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__bleeder_en_MASK 0x00000002L
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__is_1p2_MASK 0x00000004L
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_obs_sel_MASK 0x00000018L
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_on_mode_MASK 0x00000060L
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__rlad_tap_sel_MASK 0x00000780L
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_off_hi_MASK 0x00000800L
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__reg_off_lo_MASK 0x00001000L
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__scale_driver_MASK 0x00006000L
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__sel_bump_MASK 0x00008000L
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__sel_rladder_x_MASK 0x00010000L
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__short_rc_filt_x_MASK 0x00020000L
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__vref_pwr_on_MASK 0x00040000L
+#define DC_COMBOPHYPLLREGS8_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L
+//DC_COMBOPHYPLLREGS8_OBSERVE0
+#define DC_COMBOPHYPLLREGS8_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS8_OBSERVE0__clear_sticky_lock__SHIFT 0x6
+#define DC_COMBOPHYPLLREGS8_OBSERVE0__lock_det_dis__SHIFT 0x8
+#define DC_COMBOPHYPLLREGS8_OBSERVE0__dco_cfg__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS8_OBSERVE0__anaobs_sel__SHIFT 0x15
+#define DC_COMBOPHYPLLREGS8_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL
+#define DC_COMBOPHYPLLREGS8_OBSERVE0__clear_sticky_lock_MASK 0x00000040L
+#define DC_COMBOPHYPLLREGS8_OBSERVE0__lock_det_dis_MASK 0x00000100L
+#define DC_COMBOPHYPLLREGS8_OBSERVE0__dco_cfg_MASK 0x0003FC00L
+#define DC_COMBOPHYPLLREGS8_OBSERVE0__anaobs_sel_MASK 0x00E00000L
+//DC_COMBOPHYPLLREGS8_OBSERVE1
+#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_sel__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_trig_sel__SHIFT 0x5
+#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_div__SHIFT 0xa
+#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_trig_div__SHIFT 0xd
+#define DC_COMBOPHYPLLREGS8_OBSERVE1__lock_timer__SHIFT 0x10
+#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_sel_MASK 0x0000000FL
+#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L
+#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_div_MASK 0x00000C00L
+#define DC_COMBOPHYPLLREGS8_OBSERVE1__digobs_trig_div_MASK 0x00006000L
+#define DC_COMBOPHYPLLREGS8_OBSERVE1__lock_timer_MASK 0x3FFF0000L
+//DC_COMBOPHYPLLREGS8_DFT_OUT
+#define DC_COMBOPHYPLLREGS8_DFT_OUT__dft_data__SHIFT 0x0
+#define DC_COMBOPHYPLLREGS8_DFT_OUT__dft_data_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dsi0_dispdec
+//DSI0_DISP_DSI_CTRL
+#define DSI0_DISP_DSI_CTRL__DSI_EN__SHIFT 0x0
+#define DSI0_DISP_DSI_CTRL__VIDEO_MODE_EN__SHIFT 0x1
+#define DSI0_DISP_DSI_CTRL__CMD_MODE_EN__SHIFT 0x2
+#define DSI0_DISP_DSI_CTRL__DLN0_EN__SHIFT 0x4
+#define DSI0_DISP_DSI_CTRL__DLN1_EN__SHIFT 0x5
+#define DSI0_DISP_DSI_CTRL__DLN2_EN__SHIFT 0x6
+#define DSI0_DISP_DSI_CTRL__DLN3_EN__SHIFT 0x7
+#define DSI0_DISP_DSI_CTRL__CLKLN_EN__SHIFT 0x8
+#define DSI0_DISP_DSI_CTRL__DLN0_PHY_EN__SHIFT 0xc
+#define DSI0_DISP_DSI_CTRL__DLN1_PHY_EN__SHIFT 0xd
+#define DSI0_DISP_DSI_CTRL__DLN2_PHY_EN__SHIFT 0xe
+#define DSI0_DISP_DSI_CTRL__DLN3_PHY_EN__SHIFT 0xf
+#define DSI0_DISP_DSI_CTRL__RESET_DISPCLK__SHIFT 0x10
+#define DSI0_DISP_DSI_CTRL__RESET_DSICLK__SHIFT 0x11
+#define DSI0_DISP_DSI_CTRL__RESET_BYTECLK__SHIFT 0x12
+#define DSI0_DISP_DSI_CTRL__RESET_ESCCLK__SHIFT 0x13
+#define DSI0_DISP_DSI_CTRL__CRTC_SEL__SHIFT 0x14
+#define DSI0_DISP_DSI_CTRL__ECC_CHK_EN__SHIFT 0x18
+#define DSI0_DISP_DSI_CTRL__CRC_CHK_EN__SHIFT 0x19
+#define DSI0_DISP_DSI_CTRL__PACKET_BYTE_MSB_LSB_FLIP__SHIFT 0x1c
+#define DSI0_DISP_DSI_CTRL__PRE_TRIGGER_EN__SHIFT 0x1d
+#define DSI0_DISP_DSI_CTRL__NEW_INTERLEAVE_MODE_EN__SHIFT 0x1e
+#define DSI0_DISP_DSI_CTRL__DSI_EN_MASK 0x00000001L
+#define DSI0_DISP_DSI_CTRL__VIDEO_MODE_EN_MASK 0x00000002L
+#define DSI0_DISP_DSI_CTRL__CMD_MODE_EN_MASK 0x00000004L
+#define DSI0_DISP_DSI_CTRL__DLN0_EN_MASK 0x00000010L
+#define DSI0_DISP_DSI_CTRL__DLN1_EN_MASK 0x00000020L
+#define DSI0_DISP_DSI_CTRL__DLN2_EN_MASK 0x00000040L
+#define DSI0_DISP_DSI_CTRL__DLN3_EN_MASK 0x00000080L
+#define DSI0_DISP_DSI_CTRL__CLKLN_EN_MASK 0x00000100L
+#define DSI0_DISP_DSI_CTRL__DLN0_PHY_EN_MASK 0x00001000L
+#define DSI0_DISP_DSI_CTRL__DLN1_PHY_EN_MASK 0x00002000L
+#define DSI0_DISP_DSI_CTRL__DLN2_PHY_EN_MASK 0x00004000L
+#define DSI0_DISP_DSI_CTRL__DLN3_PHY_EN_MASK 0x00008000L
+#define DSI0_DISP_DSI_CTRL__RESET_DISPCLK_MASK 0x00010000L
+#define DSI0_DISP_DSI_CTRL__RESET_DSICLK_MASK 0x00020000L
+#define DSI0_DISP_DSI_CTRL__RESET_BYTECLK_MASK 0x00040000L
+#define DSI0_DISP_DSI_CTRL__RESET_ESCCLK_MASK 0x00080000L
+#define DSI0_DISP_DSI_CTRL__CRTC_SEL_MASK 0x00700000L
+#define DSI0_DISP_DSI_CTRL__ECC_CHK_EN_MASK 0x01000000L
+#define DSI0_DISP_DSI_CTRL__CRC_CHK_EN_MASK 0x02000000L
+#define DSI0_DISP_DSI_CTRL__PACKET_BYTE_MSB_LSB_FLIP_MASK 0x10000000L
+#define DSI0_DISP_DSI_CTRL__PRE_TRIGGER_EN_MASK 0x20000000L
+#define DSI0_DISP_DSI_CTRL__NEW_INTERLEAVE_MODE_EN_MASK 0x40000000L
+//DSI0_DISP_DSI_STATUS
+#define DSI0_DISP_DSI_STATUS__CMD_MODE_ENGINE_BUSY__SHIFT 0x0
+#define DSI0_DISP_DSI_STATUS__CMD_MODE_DMA_BUSY__SHIFT 0x1
+#define DSI0_DISP_DSI_STATUS__CMD_MODE_DENG_BUSY__SHIFT 0x2
+#define DSI0_DISP_DSI_STATUS__VIDEO_MODE_ENGINE_BUSY__SHIFT 0x3
+#define DSI0_DISP_DSI_STATUS__BTA_BUSY__SHIFT 0x4
+#define DSI0_DISP_DSI_STATUS__GENERIC_TRIGGER_BUSY__SHIFT 0x5
+#define DSI0_DISP_DSI_STATUS__PHY_RESET_BUSY__SHIFT 0x6
+#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_EMPTY__SHIFT 0x8
+#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_FULL__SHIFT 0x9
+#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_EMPTY__SHIFT 0xa
+#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_FULL__SHIFT 0xb
+#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_EMPTY__SHIFT 0xc
+#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_FULL__SHIFT 0xd
+#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_EMPTY__SHIFT 0xe
+#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_FULL__SHIFT 0xf
+#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW__SHIFT 0x10
+#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_CLR__SHIFT 0x10
+#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW__SHIFT 0x11
+#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_CLR__SHIFT 0x11
+#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW__SHIFT 0x12
+#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_CLR__SHIFT 0x12
+#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW__SHIFT 0x13
+#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_CLR__SHIFT 0x13
+#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_EMPTY__SHIFT 0x14
+#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_FULL__SHIFT 0x15
+#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW__SHIFT 0x16
+#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_CLR__SHIFT 0x16
+#define DSI0_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW__SHIFT 0x17
+#define DSI0_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_CLR__SHIFT 0x17
+#define DSI0_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK__SHIFT 0x18
+#define DSI0_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_CLR__SHIFT 0x18
+#define DSI0_DISP_DSI_STATUS__TE_ABORT__SHIFT 0x19
+#define DSI0_DISP_DSI_STATUS__TE_ABORT_CLR__SHIFT 0x19
+#define DSI0_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH__SHIFT 0x1c
+#define DSI0_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_CLR__SHIFT 0x1c
+#define DSI0_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH__SHIFT 0x1d
+#define DSI0_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_CLR__SHIFT 0x1d
+#define DSI0_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW__SHIFT 0x1e
+#define DSI0_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_CLR__SHIFT 0x1e
+#define DSI0_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION__SHIFT 0x1f
+#define DSI0_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_CLR__SHIFT 0x1f
+#define DSI0_DISP_DSI_STATUS__CMD_MODE_ENGINE_BUSY_MASK 0x00000001L
+#define DSI0_DISP_DSI_STATUS__CMD_MODE_DMA_BUSY_MASK 0x00000002L
+#define DSI0_DISP_DSI_STATUS__CMD_MODE_DENG_BUSY_MASK 0x00000004L
+#define DSI0_DISP_DSI_STATUS__VIDEO_MODE_ENGINE_BUSY_MASK 0x00000008L
+#define DSI0_DISP_DSI_STATUS__BTA_BUSY_MASK 0x00000010L
+#define DSI0_DISP_DSI_STATUS__GENERIC_TRIGGER_BUSY_MASK 0x00000020L
+#define DSI0_DISP_DSI_STATUS__PHY_RESET_BUSY_MASK 0x00000040L
+#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_EMPTY_MASK 0x00000100L
+#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_FULL_MASK 0x00000200L
+#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_EMPTY_MASK 0x00000400L
+#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_FULL_MASK 0x00000800L
+#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_EMPTY_MASK 0x00001000L
+#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_FULL_MASK 0x00002000L
+#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_EMPTY_MASK 0x00004000L
+#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_FULL_MASK 0x00008000L
+#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_MASK 0x00010000L
+#define DSI0_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_CLR_MASK 0x00010000L
+#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_MASK 0x00020000L
+#define DSI0_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_CLR_MASK 0x00020000L
+#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_MASK 0x00040000L
+#define DSI0_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_CLR_MASK 0x00040000L
+#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_MASK 0x00080000L
+#define DSI0_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_CLR_MASK 0x00080000L
+#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_EMPTY_MASK 0x00100000L
+#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_FULL_MASK 0x00200000L
+#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_MASK 0x00400000L
+#define DSI0_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_CLR_MASK 0x00400000L
+#define DSI0_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_MASK 0x00800000L
+#define DSI0_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_CLR_MASK 0x00800000L
+#define DSI0_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_MASK 0x01000000L
+#define DSI0_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_CLR_MASK 0x01000000L
+#define DSI0_DISP_DSI_STATUS__TE_ABORT_MASK 0x02000000L
+#define DSI0_DISP_DSI_STATUS__TE_ABORT_CLR_MASK 0x02000000L
+#define DSI0_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_MASK 0x10000000L
+#define DSI0_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_CLR_MASK 0x10000000L
+#define DSI0_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_MASK 0x20000000L
+#define DSI0_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_CLR_MASK 0x20000000L
+#define DSI0_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_MASK 0x40000000L
+#define DSI0_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_CLR_MASK 0x40000000L
+#define DSI0_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_MASK 0x80000000L
+#define DSI0_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_CLR_MASK 0x80000000L
+//DSI0_DISP_DSI_VIDEO_MODE_CTRL
+#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__VC__SHIFT 0x0
+#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__DST_FORMAT__SHIFT 0x4
+#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__TRAFFIC_MODE__SHIFT 0x8
+#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__BLLP_PWR_MODE__SHIFT 0xc
+#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__EOF_BLLP_PWR_MODE__SHIFT 0xf
+#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__HSA_PWR_MODE__SHIFT 0x10
+#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__HBP_PWR_MODE__SHIFT 0x14
+#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__HFP_PWR_MODE__SHIFT 0x18
+#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__PULSE_MODE_OPT__SHIFT 0x1c
+#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__VC_MASK 0x00000003L
+#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__DST_FORMAT_MASK 0x00000030L
+#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__TRAFFIC_MODE_MASK 0x00000300L
+#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__BLLP_PWR_MODE_MASK 0x00001000L
+#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__EOF_BLLP_PWR_MODE_MASK 0x00008000L
+#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__HSA_PWR_MODE_MASK 0x00010000L
+#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__HBP_PWR_MODE_MASK 0x00100000L
+#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__HFP_PWR_MODE_MASK 0x01000000L
+#define DSI0_DISP_DSI_VIDEO_MODE_CTRL__PULSE_MODE_OPT_MASK 0x10000000L
+//DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE
+#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VS__SHIFT 0x0
+#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VE__SHIFT 0x8
+#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HS__SHIFT 0x10
+#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HE__SHIFT 0x18
+#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VS_MASK 0x0000003FL
+#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VE_MASK 0x00003F00L
+#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HS_MASK 0x003F0000L
+#define DSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HE_MASK 0x3F000000L
+//DSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD
+#define DSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VS_PAYLOAD__SHIFT 0x0
+#define DSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VE_PAYLOAD__SHIFT 0x10
+#define DSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VS_PAYLOAD_MASK 0x0000FFFFL
+#define DSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VE_PAYLOAD_MASK 0xFFFF0000L
+//DSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD
+#define DSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HS_PAYLOAD__SHIFT 0x0
+#define DSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HE_PAYLOAD__SHIFT 0x10
+#define DSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HS_PAYLOAD_MASK 0x0000FFFFL
+#define DSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HE_PAYLOAD_MASK 0xFFFF0000L
+//DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE
+#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB565__SHIFT 0x0
+#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_PACKED__SHIFT 0x8
+#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666__SHIFT 0x10
+#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB888__SHIFT 0x18
+#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB565_MASK 0x0000003FL
+#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_PACKED_MASK 0x00003F00L
+#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_MASK 0x003F0000L
+#define DSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB888_MASK 0x3F000000L
+//DSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE
+#define DSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATA__SHIFT 0x0
+#define DSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATATYPE__SHIFT 0x8
+#define DSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATA_MASK 0x000000FFL
+#define DSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATATYPE_MASK 0x00003F00L
+//DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL
+#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__R_SEL__SHIFT 0x0
+#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__G_SEL__SHIFT 0x4
+#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__B_SEL__SHIFT 0x8
+#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__RGB_SWAP__SHIFT 0xc
+#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__R_SEL_MASK 0x00000001L
+#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__G_SEL_MASK 0x00000010L
+#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__B_SEL_MASK 0x00000100L
+#define DSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL__RGB_SWAP_MASK 0x00007000L
+//DSI0_DISP_DSI_COMMAND_MODE_CTRL
+#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__WC__SHIFT 0x0
+#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__DT__SHIFT 0x10
+#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__VC__SHIFT 0x16
+#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__PACKET_TYPE__SHIFT 0x18
+#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__POWER_MODE__SHIFT 0x1a
+#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__EMBEDDED_MODE__SHIFT 0x1c
+#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__CMD_DATA_ORDER__SHIFT 0x1f
+#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__WC_MASK 0x0000FFFFL
+#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__DT_MASK 0x003F0000L
+#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__VC_MASK 0x00C00000L
+#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__PACKET_TYPE_MASK 0x01000000L
+#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__POWER_MODE_MASK 0x04000000L
+#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__EMBEDDED_MODE_MASK 0x10000000L
+#define DSI0_DISP_DSI_COMMAND_MODE_CTRL__CMD_DATA_ORDER_MASK 0x80000000L
+//DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL
+#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__SRC_FORMAT__SHIFT 0x0
+#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DST_FORMAT__SHIFT 0x4
+#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DATA_BUFFER_ID__SHIFT 0x8
+#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__SHADOW_DATA_BUFFER_ID__SHIFT 0xc
+#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__R_SEL__SHIFT 0x10
+#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__G_SEL__SHIFT 0x11
+#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__B_SEL__SHIFT 0x12
+#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__RGB_SWAP__SHIFT 0x14
+#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DWORD_BYTE_SWAP__SHIFT 0x18
+#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__SRC_FORMAT_MASK 0x0000000FL
+#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DST_FORMAT_MASK 0x000000F0L
+#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DATA_BUFFER_ID_MASK 0x00000100L
+#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__SHADOW_DATA_BUFFER_ID_MASK 0x00001000L
+#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__R_SEL_MASK 0x00010000L
+#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__G_SEL_MASK 0x00020000L
+#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__B_SEL_MASK 0x00040000L
+#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__RGB_SWAP_MASK 0x00700000L
+#define DSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL__DWORD_BYTE_SWAP_MASK 0x03000000L
+//DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL
+#define DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_START__SHIFT 0x0
+#define DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_CONTINUE__SHIFT 0x8
+#define DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__INSERT_DCS_COMMAND__SHIFT 0x10
+#define DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_START_MASK 0x000000FFL
+#define DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_CONTINUE_MASK 0x0000FF00L
+#define DSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__INSERT_DCS_COMMAND_MASK 0x00010000L
+//DSI0_DISP_DSI_DMA_CMD_OFFSET
+#define DSI0_DISP_DSI_DMA_CMD_OFFSET__CMD_OFFSET__SHIFT 0x0
+#define DSI0_DISP_DSI_DMA_CMD_OFFSET__CMD_OFFSET_MASK 0xFFFFFFFFL
+//DSI0_DISP_DSI_DMA_CMD_LENGTH
+#define DSI0_DISP_DSI_DMA_CMD_LENGTH__CMD_LENGTH__SHIFT 0x0
+#define DSI0_DISP_DSI_DMA_CMD_LENGTH__CMD_LENGTH_MASK 0x00FFFFFFL
+//DSI0_DISP_DSI_DMA_DATA_OFFSET_0
+#define DSI0_DISP_DSI_DMA_DATA_OFFSET_0__DATA_SRC_OFFSET0__SHIFT 0x0
+#define DSI0_DISP_DSI_DMA_DATA_OFFSET_0__DATA_SRC_OFFSET0_MASK 0xFFFFFFFFL
+//DSI0_DISP_DSI_DMA_DATA_OFFSET_1
+#define DSI0_DISP_DSI_DMA_DATA_OFFSET_1__DATA_SRC_OFFSET1__SHIFT 0x0
+#define DSI0_DISP_DSI_DMA_DATA_OFFSET_1__DATA_SRC_OFFSET1_MASK 0xFFFFFFFFL
+//DSI0_DISP_DSI_DMA_DATA_PITCH
+#define DSI0_DISP_DSI_DMA_DATA_PITCH__DATA_SRC_PITCH__SHIFT 0x0
+#define DSI0_DISP_DSI_DMA_DATA_PITCH__DATA_SRC_PITCH_MASK 0x00007FFFL
+//DSI0_DISP_DSI_DMA_DATA_WIDTH
+#define DSI0_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH__SHIFT 0x0
+#define DSI0_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_ALIGN__SHIFT 0x18
+#define DSI0_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_MASK 0x000FFFFFL
+#define DSI0_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_ALIGN_MASK 0x07000000L
+//DSI0_DISP_DSI_DMA_DATA_HEIGHT
+#define DSI0_DISP_DSI_DMA_DATA_HEIGHT__DATA_SRC_HEIGHT__SHIFT 0x0
+#define DSI0_DISP_DSI_DMA_DATA_HEIGHT__DATA_SRC_HEIGHT_MASK 0x00000FFFL
+//DSI0_DISP_DSI_DMA_FIFO_CTRL
+#define DSI0_DISP_DSI_DMA_FIFO_CTRL__WRITE_WATERMARK__SHIFT 0x0
+#define DSI0_DISP_DSI_DMA_FIFO_CTRL__READ_WATERMARK__SHIFT 0x4
+#define DSI0_DISP_DSI_DMA_FIFO_CTRL__WRITE_WATERMARK_MASK 0x00000003L
+#define DSI0_DISP_DSI_DMA_FIFO_CTRL__READ_WATERMARK_MASK 0x00000030L
+//DSI0_DISP_DSI_DMA_NULL_PACKET_DATA
+#define DSI0_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATA__SHIFT 0x0
+#define DSI0_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATATYPE__SHIFT 0x8
+#define DSI0_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATA_MASK 0x000000FFL
+#define DSI0_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATATYPE_MASK 0x00003F00L
+//DSI0_DISP_DSI_DENG_DATA_LENGTH
+#define DSI0_DISP_DSI_DENG_DATA_LENGTH__DENG_LENGTH__SHIFT 0x0
+#define DSI0_DISP_DSI_DENG_DATA_LENGTH__USE_DENG_LENGTH__SHIFT 0x1f
+#define DSI0_DISP_DSI_DENG_DATA_LENGTH__DENG_LENGTH_MASK 0x00FFFFFFL
+#define DSI0_DISP_DSI_DENG_DATA_LENGTH__USE_DENG_LENGTH_MASK 0x80000000L
+//DSI0_DISP_DSI_ACK_ERROR_REPORT
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR__SHIFT 0x0
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_CLR__SHIFT 0x0
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR__SHIFT 0x1
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_CLR__SHIFT 0x1
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR__SHIFT 0x2
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_CLR__SHIFT 0x2
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR__SHIFT 0x3
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_CLR__SHIFT 0x3
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__LP_ERR__SHIFT 0x4
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_CLR__SHIFT 0x4
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__HRX_TO__SHIFT 0x5
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_CLR__SHIFT 0x5
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR__SHIFT 0x6
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_CLR__SHIFT 0x6
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR__SHIFT 0x7
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_CLR__SHIFT 0x7
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR__SHIFT 0x8
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_CLR__SHIFT 0x8
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR__SHIFT 0x9
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_CLR__SHIFT 0x9
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR__SHIFT 0xa
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_CLR__SHIFT 0xa
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__DT_ERR__SHIFT 0xb
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_CLR__SHIFT 0xb
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__VC_ERR__SHIFT 0xc
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_CLR__SHIFT 0xc
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION__SHIFT 0xd
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_CLR__SHIFT 0xd
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR__SHIFT 0xf
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_CLR__SHIFT 0xf
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR__SHIFT 0x10
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_CLR__SHIFT 0x10
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR__SHIFT 0x11
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_CLR__SHIFT 0x11
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR__SHIFT 0x14
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_CLR__SHIFT 0x14
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR__SHIFT 0x17
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_CLR__SHIFT 0x17
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ERROR__SHIFT 0x18
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ERROR_CLR__SHIFT 0x18
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ACK__SHIFT 0x1c
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ACK_CLR__SHIFT 0x1c
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_MASK 0x00000001L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_CLR_MASK 0x00000001L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_MASK 0x00000002L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_CLR_MASK 0x00000002L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_MASK 0x00000004L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_CLR_MASK 0x00000004L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_MASK 0x00000008L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_CLR_MASK 0x00000008L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_MASK 0x00000010L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_CLR_MASK 0x00000010L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_MASK 0x00000020L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_CLR_MASK 0x00000020L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_MASK 0x00000040L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_CLR_MASK 0x00000040L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_MASK 0x00000080L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_CLR_MASK 0x00000080L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_MASK 0x00000100L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_CLR_MASK 0x00000100L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_MASK 0x00000200L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_CLR_MASK 0x00000200L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_MASK 0x00000400L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_CLR_MASK 0x00000400L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_MASK 0x00000800L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_CLR_MASK 0x00000800L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_MASK 0x00001000L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_CLR_MASK 0x00001000L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_MASK 0x00002000L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_CLR_MASK 0x00002000L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_MASK 0x00008000L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_CLR_MASK 0x00008000L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_MASK 0x00010000L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_CLR_MASK 0x00010000L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_MASK 0x00020000L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_CLR_MASK 0x00020000L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_MASK 0x00100000L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_CLR_MASK 0x00100000L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_MASK 0x00800000L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_CLR_MASK 0x00800000L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ERROR_MASK 0x01000000L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ERROR_CLR_MASK 0x01000000L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ACK_MASK 0x10000000L
+#define DSI0_DISP_DSI_ACK_ERROR_REPORT__ACK_CLR_MASK 0x10000000L
+//DSI0_DISP_DSI_RDBK_DATA0
+#define DSI0_DISP_DSI_RDBK_DATA0__RD_DATA0__SHIFT 0x0
+#define DSI0_DISP_DSI_RDBK_DATA0__RD_DATA0_MASK 0xFFFFFFFFL
+//DSI0_DISP_DSI_RDBK_DATA1
+#define DSI0_DISP_DSI_RDBK_DATA1__RD_DATA1__SHIFT 0x0
+#define DSI0_DISP_DSI_RDBK_DATA1__RD_DATA1_MASK 0xFFFFFFFFL
+//DSI0_DISP_DSI_RDBK_DATA2
+#define DSI0_DISP_DSI_RDBK_DATA2__RD_DATA2__SHIFT 0x0
+#define DSI0_DISP_DSI_RDBK_DATA2__RD_DATA2_MASK 0xFFFFFFFFL
+//DSI0_DISP_DSI_RDBK_DATA3
+#define DSI0_DISP_DSI_RDBK_DATA3__RD_DATA3__SHIFT 0x0
+#define DSI0_DISP_DSI_RDBK_DATA3__RD_DATA3_MASK 0xFFFFFFFFL
+//DSI0_DISP_DSI_RDBK_DATATYPE0
+#define DSI0_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_1_BYTE__SHIFT 0x0
+#define DSI0_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_2_BYTE__SHIFT 0x8
+#define DSI0_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_1_BYTE__SHIFT 0x10
+#define DSI0_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_2_BYTE__SHIFT 0x18
+#define DSI0_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_1_BYTE_MASK 0x0000003FL
+#define DSI0_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_2_BYTE_MASK 0x00003F00L
+#define DSI0_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_1_BYTE_MASK 0x003F0000L
+#define DSI0_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_2_BYTE_MASK 0x3F000000L
+//DSI0_DISP_DSI_RDBK_DATATYPE1
+#define DSI0_DISP_DSI_RDBK_DATATYPE1__ERROR_REPORT__SHIFT 0x0
+#define DSI0_DISP_DSI_RDBK_DATATYPE1__GENERIC_LONG_RD__SHIFT 0x8
+#define DSI0_DISP_DSI_RDBK_DATATYPE1__DCS_LONG_RD__SHIFT 0x10
+#define DSI0_DISP_DSI_RDBK_DATATYPE1__ERROR_REPORT_MASK 0x0000003FL
+#define DSI0_DISP_DSI_RDBK_DATATYPE1__GENERIC_LONG_RD_MASK 0x00003F00L
+#define DSI0_DISP_DSI_RDBK_DATATYPE1__DCS_LONG_RD_MASK 0x003F0000L
+//DSI0_DISP_DSI_TRIG_CTRL
+#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_MODE__SHIFT 0x0
+#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_SEL__SHIFT 0x4
+#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_MODE__SHIFT 0x10
+#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_SEL__SHIFT 0x14
+#define DSI0_DISP_DSI_TRIG_CTRL__HW_SOURCE_SEL__SHIFT 0x18
+#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_DENG_ORDER__SHIFT 0x1c
+#define DSI0_DISP_DSI_TRIG_CTRL__TE_SEL__SHIFT 0x1f
+#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_MODE_MASK 0x00000001L
+#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_SEL_MASK 0x00000030L
+#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_MODE_MASK 0x00010000L
+#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_SEL_MASK 0x00300000L
+#define DSI0_DISP_DSI_TRIG_CTRL__HW_SOURCE_SEL_MASK 0x0F000000L
+#define DSI0_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_DENG_ORDER_MASK 0x10000000L
+#define DSI0_DISP_DSI_TRIG_CTRL__TE_SEL_MASK 0x80000000L
+//DSI0_DISP_DSI_EXT_MUX
+#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_MUX__SHIFT 0x0
+#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_MODE__SHIFT 0x4
+#define DSI0_DISP_DSI_EXT_MUX__EXT_RESET_POL__SHIFT 0x6
+#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_POL__SHIFT 0x7
+#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TRIG_CNT__SHIFT 0x8
+#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TOTAL__SHIFT 0x14
+#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_MUX_MASK 0x0000000FL
+#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_MODE_MASK 0x00000030L
+#define DSI0_DISP_DSI_EXT_MUX__EXT_RESET_POL_MASK 0x00000040L
+#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_POL_MASK 0x00000080L
+#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TRIG_CNT_MASK 0x000FFF00L
+#define DSI0_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TOTAL_MASK 0xFFF00000L
+//DSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL
+#define DSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_HSYNC_MAX_WIDTH__SHIFT 0x0
+#define DSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_VSYNC_MIN_WIDTH__SHIFT 0x10
+#define DSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_HSYNC_MAX_WIDTH_MASK 0x0000FFFFL
+#define DSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_VSYNC_MIN_WIDTH_MASK 0xFFFF0000L
+//DSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER
+#define DSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
+#define DSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
+//DSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER
+#define DSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
+#define DSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
+//DSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER
+#define DSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
+#define DSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
+//DSI0_DISP_DSI_RESET_SW_TRIGGER
+#define DSI0_DISP_DSI_RESET_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
+#define DSI0_DISP_DSI_RESET_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
+//DSI0_DISP_DSI_EXT_RESET
+#define DSI0_DISP_DSI_EXT_RESET__RESET_PANEL__SHIFT 0x0
+#define DSI0_DISP_DSI_EXT_RESET__RESET_PANEL_MASK 0x00000001L
+//DSI0_DISP_DSI_LANE_CRC_HS_MODE
+#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN0_HS_CRC__SHIFT 0x0
+#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN1_HS_CRC__SHIFT 0x8
+#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN2_HS_CRC__SHIFT 0x10
+#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN3_HS_CRC__SHIFT 0x18
+#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN0_HS_CRC_MASK 0x000000FFL
+#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN1_HS_CRC_MASK 0x0000FF00L
+#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN2_HS_CRC_MASK 0x00FF0000L
+#define DSI0_DISP_DSI_LANE_CRC_HS_MODE__DLN3_HS_CRC_MASK 0xFF000000L
+//DSI0_DISP_DSI_LANE_CRC_LP_MODE
+#define DSI0_DISP_DSI_LANE_CRC_LP_MODE__DLN0_LP_CRC__SHIFT 0x0
+#define DSI0_DISP_DSI_LANE_CRC_LP_MODE__DLN0_LP_CRC_MASK 0x000000FFL
+//DSI0_DISP_DSI_LANE_CRC_CTRL
+#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_HS_DONE_COUNT__SHIFT 0x0
+#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_LP_DONE_COUNT__SHIFT 0x8
+#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_ENABLE__SHIFT 0x10
+#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_HS__SHIFT 0x14
+#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_LP__SHIFT 0x18
+#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_HS_DONE_COUNT_MASK 0x000000FFL
+#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_LP_DONE_COUNT_MASK 0x0000FF00L
+#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_ENABLE_MASK 0x00010000L
+#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_HS_MASK 0x00100000L
+#define DSI0_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_LP_MASK 0x01000000L
+//DSI0_DISP_DSI_PIXEL_CRC_CTRL
+#define DSI0_DISP_DSI_PIXEL_CRC_CTRL__CRC_MAX_PIXEL_COUNT__SHIFT 0x0
+#define DSI0_DISP_DSI_PIXEL_CRC_CTRL__PIXEL_CRC__SHIFT 0x8
+#define DSI0_DISP_DSI_PIXEL_CRC_CTRL__CRC_DONE_PIXEL__SHIFT 0x10
+#define DSI0_DISP_DSI_PIXEL_CRC_CTRL__CRC_MAX_PIXEL_COUNT_MASK 0x000000FFL
+#define DSI0_DISP_DSI_PIXEL_CRC_CTRL__PIXEL_CRC_MASK 0x0000FF00L
+#define DSI0_DISP_DSI_PIXEL_CRC_CTRL__CRC_DONE_PIXEL_MASK 0x00010000L
+//DSI0_DISP_DSI_LANE_CTRL
+#define DSI0_DISP_DSI_LANE_CTRL__DLN0_ULPS_REQUEST__SHIFT 0x0
+#define DSI0_DISP_DSI_LANE_CTRL__DLN1_ULPS_REQUEST__SHIFT 0x1
+#define DSI0_DISP_DSI_LANE_CTRL__DLN2_ULPS_REQUEST__SHIFT 0x2
+#define DSI0_DISP_DSI_LANE_CTRL__DLN3_ULPS_REQUEST__SHIFT 0x3
+#define DSI0_DISP_DSI_LANE_CTRL__DLN0_ULPS_EXIT__SHIFT 0x4
+#define DSI0_DISP_DSI_LANE_CTRL__DLN1_ULPS_EXIT__SHIFT 0x5
+#define DSI0_DISP_DSI_LANE_CTRL__DLN2_ULPS_EXIT__SHIFT 0x6
+#define DSI0_DISP_DSI_LANE_CTRL__DLN3_ULPS_EXIT__SHIFT 0x7
+#define DSI0_DISP_DSI_LANE_CTRL__DLN0_FORCE_TX_STOP__SHIFT 0x8
+#define DSI0_DISP_DSI_LANE_CTRL__DLN1_FORCE_TX_STOP__SHIFT 0x9
+#define DSI0_DISP_DSI_LANE_CTRL__DLN2_FORCE_TX_STOP__SHIFT 0xa
+#define DSI0_DISP_DSI_LANE_CTRL__DLN3_FORCE_TX_STOP__SHIFT 0xb
+#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_ULPS_REQUEST__SHIFT 0xc
+#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_ULPS_EXIT__SHIFT 0x10
+#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_FORCE_TX_STOP__SHIFT 0x14
+#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_HS_FORCE_REQUEST__SHIFT 0x18
+#define DSI0_DISP_DSI_LANE_CTRL__DLN0_ULPS_REQUEST_MASK 0x00000001L
+#define DSI0_DISP_DSI_LANE_CTRL__DLN1_ULPS_REQUEST_MASK 0x00000002L
+#define DSI0_DISP_DSI_LANE_CTRL__DLN2_ULPS_REQUEST_MASK 0x00000004L
+#define DSI0_DISP_DSI_LANE_CTRL__DLN3_ULPS_REQUEST_MASK 0x00000008L
+#define DSI0_DISP_DSI_LANE_CTRL__DLN0_ULPS_EXIT_MASK 0x00000010L
+#define DSI0_DISP_DSI_LANE_CTRL__DLN1_ULPS_EXIT_MASK 0x00000020L
+#define DSI0_DISP_DSI_LANE_CTRL__DLN2_ULPS_EXIT_MASK 0x00000040L
+#define DSI0_DISP_DSI_LANE_CTRL__DLN3_ULPS_EXIT_MASK 0x00000080L
+#define DSI0_DISP_DSI_LANE_CTRL__DLN0_FORCE_TX_STOP_MASK 0x00000100L
+#define DSI0_DISP_DSI_LANE_CTRL__DLN1_FORCE_TX_STOP_MASK 0x00000200L
+#define DSI0_DISP_DSI_LANE_CTRL__DLN2_FORCE_TX_STOP_MASK 0x00000400L
+#define DSI0_DISP_DSI_LANE_CTRL__DLN3_FORCE_TX_STOP_MASK 0x00000800L
+#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_ULPS_REQUEST_MASK 0x00001000L
+#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_ULPS_EXIT_MASK 0x00010000L
+#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_FORCE_TX_STOP_MASK 0x00100000L
+#define DSI0_DISP_DSI_LANE_CTRL__CLKLN_HS_FORCE_REQUEST_MASK 0x01000000L
+//DSI0_DISP_DSI_DLN0_PHY_ERROR
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC__SHIFT 0x0
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_CLR__SHIFT 0x0
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK__SHIFT 0x3
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC__SHIFT 0x4
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_CLR__SHIFT 0x4
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK__SHIFT 0x7
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL__SHIFT 0x8
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_CLR__SHIFT 0x8
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK__SHIFT 0xb
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0__SHIFT 0xc
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_CLR__SHIFT 0xc
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK__SHIFT 0xf
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1__SHIFT 0x10
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_CLR__SHIFT 0x10
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK__SHIFT 0x13
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK 0x00000001L
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_CLR_MASK 0x00000001L
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK_MASK 0x00000008L
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK 0x00000010L
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_CLR_MASK 0x00000010L
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK_MASK 0x00000080L
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK 0x00000100L
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_CLR_MASK 0x00000100L
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK_MASK 0x00000800L
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK 0x00001000L
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_CLR_MASK 0x00001000L
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK_MASK 0x00008000L
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK 0x00010000L
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_CLR_MASK 0x00010000L
+#define DSI0_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK_MASK 0x00080000L
+//DSI0_DISP_DSI_LP_TIMER_CTRL
+#define DSI0_DISP_DSI_LP_TIMER_CTRL__LP_RX_TO__SHIFT 0x0
+#define DSI0_DISP_DSI_LP_TIMER_CTRL__BTA_TO__SHIFT 0x10
+#define DSI0_DISP_DSI_LP_TIMER_CTRL__LP_RX_TO_MASK 0x0000FFFFL
+#define DSI0_DISP_DSI_LP_TIMER_CTRL__BTA_TO_MASK 0xFFFF0000L
+//DSI0_DISP_DSI_HS_TIMER_CTRL
+#define DSI0_DISP_DSI_HS_TIMER_CTRL__HS_TX_TO__SHIFT 0x0
+#define DSI0_DISP_DSI_HS_TIMER_CTRL__HS_TX_TO_MASK 0x0000FFFFL
+//DSI0_DISP_DSI_TIMEOUT_STATUS
+#define DSI0_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT__SHIFT 0x0
+#define DSI0_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_CLR__SHIFT 0x0
+#define DSI0_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT__SHIFT 0x4
+#define DSI0_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_CLR__SHIFT 0x4
+#define DSI0_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT__SHIFT 0x8
+#define DSI0_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_CLR__SHIFT 0x8
+#define DSI0_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_MASK 0x00000001L
+#define DSI0_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_CLR_MASK 0x00000001L
+#define DSI0_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_MASK 0x00000010L
+#define DSI0_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_CLR_MASK 0x00000010L
+#define DSI0_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_MASK 0x00000100L
+#define DSI0_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_CLR_MASK 0x00000100L
+//DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL
+#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_PRE__SHIFT 0x0
+#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_POST__SHIFT 0x8
+#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_PRE_MASK 0x000000FFL
+#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_POST_MASK 0x00003F00L
+//DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2
+#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_PRE_TRIGGER__SHIFT 0x0
+#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_INTER_STOP__SHIFT 0x10
+#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_PRE_TRIGGER_MASK 0x000007FFL
+#define DSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_INTER_STOP_MASK 0xFFFF0000L
+//DSI0_DISP_DSI_EOT_PACKET
+#define DSI0_DISP_DSI_EOT_PACKET__DI__SHIFT 0x0
+#define DSI0_DISP_DSI_EOT_PACKET__WC__SHIFT 0x8
+#define DSI0_DISP_DSI_EOT_PACKET__ECC__SHIFT 0x18
+#define DSI0_DISP_DSI_EOT_PACKET__DI_MASK 0x000000FFL
+#define DSI0_DISP_DSI_EOT_PACKET__WC_MASK 0x00FFFF00L
+#define DSI0_DISP_DSI_EOT_PACKET__ECC_MASK 0xFF000000L
+//DSI0_DISP_DSI_EOT_PACKET_CTRL
+#define DSI0_DISP_DSI_EOT_PACKET_CTRL__TX_EOT_APPEND__SHIFT 0x0
+#define DSI0_DISP_DSI_EOT_PACKET_CTRL__RX_EOT_IGNORE__SHIFT 0x4
+#define DSI0_DISP_DSI_EOT_PACKET_CTRL__TX_EOT_APPEND_MASK 0x00000001L
+#define DSI0_DISP_DSI_EOT_PACKET_CTRL__RX_EOT_IGNORE_MASK 0x00000010L
+//DSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER
+#define DSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER__SW_TRIGGER__SHIFT 0x0
+#define DSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER__ENTRY_COMMAND__SHIFT 0x10
+#define DSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER__SW_TRIGGER_MASK 0x00000001L
+#define DSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER__ENTRY_COMMAND_MASK 0x00FF0000L
+//DSI0_DISP_DSI_MIPI_BIST_CTRL
+#define DSI0_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_RESET__SHIFT 0x0
+#define DSI0_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_EN__SHIFT 0x1
+#define DSI0_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_RESET_MASK 0x00000001L
+#define DSI0_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_EN_MASK 0x00000002L
+//DSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE
+#define DSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_H_SIZE__SHIFT 0x0
+#define DSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_V_SIZE__SHIFT 0x10
+#define DSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_H_SIZE_MASK 0x0000FFFFL
+#define DSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_V_SIZE_MASK 0xFFFF0000L
+//DSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE
+#define DSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_H_SIZE__SHIFT 0x0
+#define DSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_V_SIZE__SHIFT 0x8
+#define DSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_H_SIZE_MASK 0x000000FFL
+#define DSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_V_SIZE_MASK 0x0000FF00L
+//DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG
+#define DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BLANKING_CYCLES__SHIFT 0x0
+#define DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_FRAME_REPEAT__SHIFT 0x10
+#define DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BIST_VIDEO_FRMT__SHIFT 0x18
+#define DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BLANKING_CYCLES_MASK 0x0000FFFFL
+#define DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_FRAME_REPEAT_MASK 0x00FF0000L
+#define DSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BIST_VIDEO_FRMT_MASK 0x01000000L
+//DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL
+#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_POLYNOMIAL__SHIFT 0x0
+#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_POLYNOMIAL__SHIFT 0x8
+#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_POLYNOMIAL__SHIFT 0x10
+#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_EN__SHIFT 0x18
+#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_EN__SHIFT 0x19
+#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_EN__SHIFT 0x1a
+#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_POLYNOMIAL_MASK 0x000000FFL
+#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_POLYNOMIAL_MASK 0x0000FF00L
+#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_POLYNOMIAL_MASK 0x00FF0000L
+#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_EN_MASK 0x01000000L
+#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_EN_MASK 0x02000000L
+#define DSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_EN_MASK 0x04000000L
+//DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT
+#define DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_Y_INIT_LSFR_VAL__SHIFT 0x0
+#define DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_U_INIT_LSFR_VAL__SHIFT 0x8
+#define DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_V_INIT_LSFR_VAL__SHIFT 0x10
+#define DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_Y_INIT_LSFR_VAL_MASK 0x000000FFL
+#define DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_U_INIT_LSFR_VAL_MASK 0x0000FF00L
+#define DSI0_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_V_INIT_LSFR_VAL_MASK 0x00FF0000L
+//DSI0_DISP_DSI_MIPI_BIST_START
+#define DSI0_DISP_DSI_MIPI_BIST_START__MIPI_BIST_START__SHIFT 0x0
+#define DSI0_DISP_DSI_MIPI_BIST_START__MIPI_BIST_START_MASK 0x00000001L
+//DSI0_DISP_DSI_MIPI_BIST_STATUS
+#define DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_STATUS_BUSY__SHIFT 0x0
+#define DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE__SHIFT 0x4
+#define DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_CLR__SHIFT 0x4
+#define DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_STATUS_BUSY_MASK 0x00000001L
+#define DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_MASK 0x00000010L
+#define DSI0_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_CLR_MASK 0x00000010L
+//DSI0_DISP_DSI_ERROR_INTERRUPT_MASK
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_ECC_ERR_MASK__SHIFT 0x0
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_MULTI_ECC_ERR_MASK__SHIFT 0x1
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_CRC_ERR_MASK__SHIFT 0x2
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_INCOMPLETE_PACKET_ERR_MASK__SHIFT 0x3
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__ERROR_PACKET_MASK__SHIFT 0x4
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_PACKET_BLOCK_MASK__SHIFT 0x5
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__TE_ABORT_MASK__SHIFT 0x6
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_ESC_MASK__SHIFT 0x8
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_SYNC_ESC_MASK__SHIFT 0x9
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTROL_MASK__SHIFT 0xa
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP0_MASK__SHIFT 0xc
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP1_MASK__SHIFT 0xd
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__LP_RX_TO_MASK__SHIFT 0x10
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__HS_TX_TO_MASK__SHIFT 0x11
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__BTA_TO_MASK__SHIFT 0x12
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DMAFIFO_UNDERFLOW_MASK__SHIFT 0x14
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__CMDFIFO_UNDERFLOW_MASK__SHIFT 0x15
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DENGFIFO_OVERFLOW_UNDERFLOW_MASK__SHIFT 0x18
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1a
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN1_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1b
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN2_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1c
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN3_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1d
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_LP_FIFO_OVERFLOW_MASK__SHIFT 0x1e
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_OP_CONTENTION_MASK__SHIFT 0x1f
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_ECC_ERR_MASK_MASK 0x00000001L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_MULTI_ECC_ERR_MASK_MASK 0x00000002L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_CRC_ERR_MASK_MASK 0x00000004L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_INCOMPLETE_PACKET_ERR_MASK_MASK 0x00000008L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__ERROR_PACKET_MASK_MASK 0x00000010L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_PACKET_BLOCK_MASK_MASK 0x00000020L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__TE_ABORT_MASK_MASK 0x00000040L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_ESC_MASK_MASK 0x00000100L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_SYNC_ESC_MASK_MASK 0x00000200L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTROL_MASK_MASK 0x00000400L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP0_MASK_MASK 0x00001000L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP1_MASK_MASK 0x00002000L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__LP_RX_TO_MASK_MASK 0x00010000L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__HS_TX_TO_MASK_MASK 0x00020000L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__BTA_TO_MASK_MASK 0x00040000L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DMAFIFO_UNDERFLOW_MASK_MASK 0x00100000L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__CMDFIFO_UNDERFLOW_MASK_MASK 0x00200000L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DENGFIFO_OVERFLOW_UNDERFLOW_MASK_MASK 0x01000000L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_HS_FIFO_OVERFLOW_MASK_MASK 0x04000000L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN1_HS_FIFO_OVERFLOW_MASK_MASK 0x08000000L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN2_HS_FIFO_OVERFLOW_MASK_MASK 0x10000000L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN3_HS_FIFO_OVERFLOW_MASK_MASK 0x20000000L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_LP_FIFO_OVERFLOW_MASK_MASK 0x40000000L
+#define DSI0_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_OP_CONTENTION_MASK_MASK 0x80000000L
+//DSI0_DISP_DSI_INTERRUPT_CTRL
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_STAT__SHIFT 0x0
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_AK__SHIFT 0x0
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_MASK__SHIFT 0x1
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_STAT__SHIFT 0x4
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_AK__SHIFT 0x4
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_MASK__SHIFT 0x5
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_STAT__SHIFT 0x8
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_AK__SHIFT 0x8
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_MASK__SHIFT 0x9
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_STAT__SHIFT 0xc
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_AK__SHIFT 0xc
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_MASK__SHIFT 0xd
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_STAT__SHIFT 0x10
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_AK__SHIFT 0x10
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_MASK__SHIFT 0x11
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_STAT__SHIFT 0x14
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_AK__SHIFT 0x14
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_MASK__SHIFT 0x15
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_STAT__SHIFT 0x18
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_AK__SHIFT 0x18
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_MASK__SHIFT 0x19
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_STAT_MASK 0x00000001L
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_AK_MASK 0x00000001L
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_MASK_MASK 0x00000002L
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_STAT_MASK 0x00000010L
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_AK_MASK 0x00000010L
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_MASK_MASK 0x00000020L
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_STAT_MASK 0x00000100L
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_AK_MASK 0x00000100L
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_MASK_MASK 0x00000200L
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_STAT_MASK 0x00001000L
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_AK_MASK 0x00001000L
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_MASK_MASK 0x00002000L
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_STAT_MASK 0x00010000L
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_AK_MASK 0x00010000L
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_MASK_MASK 0x00020000L
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_STAT_MASK 0x00100000L
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_AK_MASK 0x00100000L
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_MASK_MASK 0x00200000L
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_STAT_MASK 0x01000000L
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_AK_MASK 0x01000000L
+#define DSI0_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_MASK_MASK 0x02000000L
+//DSI0_DISP_DSI_CLK_CTRL
+#define DSI0_DISP_DSI_CLK_CTRL__DISPCLK_G_ON__SHIFT 0x0
+#define DSI0_DISP_DSI_CLK_CTRL__DISPCLK_R_ON__SHIFT 0x1
+#define DSI0_DISP_DSI_CLK_CTRL__DSICLK_G_ON__SHIFT 0x4
+#define DSI0_DISP_DSI_CLK_CTRL__DSICLK_R_ON__SHIFT 0x5
+#define DSI0_DISP_DSI_CLK_CTRL__DSICLK_TRN_ON__SHIFT 0x6
+#define DSI0_DISP_DSI_CLK_CTRL__BYTECLK_G_ON__SHIFT 0x8
+#define DSI0_DISP_DSI_CLK_CTRL__ESCCLK_G_ON__SHIFT 0x10
+#define DSI0_DISP_DSI_CLK_CTRL__TEST_CLK_SEL__SHIFT 0x18
+#define DSI0_DISP_DSI_CLK_CTRL__DISPCLK_G_ON_MASK 0x00000001L
+#define DSI0_DISP_DSI_CLK_CTRL__DISPCLK_R_ON_MASK 0x00000002L
+#define DSI0_DISP_DSI_CLK_CTRL__DSICLK_G_ON_MASK 0x00000010L
+#define DSI0_DISP_DSI_CLK_CTRL__DSICLK_R_ON_MASK 0x00000020L
+#define DSI0_DISP_DSI_CLK_CTRL__DSICLK_TRN_ON_MASK 0x00000040L
+#define DSI0_DISP_DSI_CLK_CTRL__BYTECLK_G_ON_MASK 0x00000100L
+#define DSI0_DISP_DSI_CLK_CTRL__ESCCLK_G_ON_MASK 0x00010000L
+#define DSI0_DISP_DSI_CLK_CTRL__TEST_CLK_SEL_MASK 0x0F000000L
+//DSI0_DISP_DSI_CLK_STATUS
+#define DSI0_DISP_DSI_CLK_STATUS__DISPCLK_R_ACTIVE__SHIFT 0x0
+#define DSI0_DISP_DSI_CLK_STATUS__DISPCLK_G_ACTIVE__SHIFT 0x1
+#define DSI0_DISP_DSI_CLK_STATUS__DSICLK_R_ACTIVE__SHIFT 0x4
+#define DSI0_DISP_DSI_CLK_STATUS__DSICLK_G_ACTIVE__SHIFT 0x5
+#define DSI0_DISP_DSI_CLK_STATUS__DSICLK_TRN_ACTIVE__SHIFT 0x6
+#define DSI0_DISP_DSI_CLK_STATUS__BYTECLK_G_ACTIVE__SHIFT 0x8
+#define DSI0_DISP_DSI_CLK_STATUS__ESCCLK_G_ACTIVE__SHIFT 0x10
+#define DSI0_DISP_DSI_CLK_STATUS__DISPCLK_R_ACTIVE_MASK 0x00000001L
+#define DSI0_DISP_DSI_CLK_STATUS__DISPCLK_G_ACTIVE_MASK 0x00000002L
+#define DSI0_DISP_DSI_CLK_STATUS__DSICLK_R_ACTIVE_MASK 0x00000010L
+#define DSI0_DISP_DSI_CLK_STATUS__DSICLK_G_ACTIVE_MASK 0x00000020L
+#define DSI0_DISP_DSI_CLK_STATUS__DSICLK_TRN_ACTIVE_MASK 0x00000040L
+#define DSI0_DISP_DSI_CLK_STATUS__BYTECLK_G_ACTIVE_MASK 0x00000100L
+#define DSI0_DISP_DSI_CLK_STATUS__ESCCLK_G_ACTIVE_MASK 0x00010000L
+//DSI0_DISP_DSI_DENG_FIFO_STATUS
+#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_LEVEL_ERROR__SHIFT 0x0
+#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_ERROR_ACK__SHIFT 0x9
+#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MAXIMUM_LEVEL__SHIFT 0x11
+#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MINIMUM_LEVEL__SHIFT 0x17
+#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CALIBRATED__SHIFT 0x1d
+#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_OVERWRITE_LEVEL_MASK 0x000001FCL
+#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_ERROR_ACK_MASK 0x00000200L
+#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0001FC00L
+#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MAXIMUM_LEVEL_MASK 0x007E0000L
+#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MINIMUM_LEVEL_MASK 0x0F800000L
+#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CALIBRATED_MASK 0x20000000L
+#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+#define DSI0_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+//DSI0_DISP_DSI_DENG_FIFO_CTRL
+#define DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_EN__SHIFT 0x0
+#define DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_START__SHIFT 0x4
+#define DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_DSICLK_ON__SHIFT 0x8
+#define DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_EN_MASK 0x00000001L
+#define DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_START_MASK 0x00000010L
+#define DSI0_DISP_DSI_DENG_FIFO_CTRL__DENG_DSICLK_ON_MASK 0x00000100L
+//DSI0_DISP_DSI_CMD_FIFO_DATA
+#define DSI0_DISP_DSI_CMD_FIFO_DATA__CMDFIFO_DATA__SHIFT 0x0
+#define DSI0_DISP_DSI_CMD_FIFO_DATA__CMDFIFO_DATA_MASK 0xFFFFFFFFL
+//DSI0_DISP_DSI_CMD_FIFO_CTRL
+#define DSI0_DISP_DSI_CMD_FIFO_CTRL__USE_CMDFIFO__SHIFT 0x0
+#define DSI0_DISP_DSI_CMD_FIFO_CTRL__CMDFIFO_DW_LEVEL__SHIFT 0x4
+#define DSI0_DISP_DSI_CMD_FIFO_CTRL__USE_CMDFIFO_MASK 0x00000001L
+#define DSI0_DISP_DSI_CMD_FIFO_CTRL__CMDFIFO_DW_LEVEL_MASK 0x000007F0L
+//DSI0_DISP_DSI_TE_CTRL
+#define DSI0_DISP_DSI_TE_CTRL__FREEZE_CRTC_HYSTERESIS__SHIFT 0x0
+#define DSI0_DISP_DSI_TE_CTRL__DISABLE_CRTC_FREEZE__SHIFT 0x10
+#define DSI0_DISP_DSI_TE_CTRL__DISABLE_CRTC_FORCE__SHIFT 0x14
+#define DSI0_DISP_DSI_TE_CTRL__CRTC_FREEZE__SHIFT 0x18
+#define DSI0_DISP_DSI_TE_CTRL__CRTC_FREEZE_TRIG__SHIFT 0x18
+#define DSI0_DISP_DSI_TE_CTRL__FREEZE_CRTC_HYSTERESIS_MASK 0x00000FFFL
+#define DSI0_DISP_DSI_TE_CTRL__DISABLE_CRTC_FREEZE_MASK 0x00010000L
+#define DSI0_DISP_DSI_TE_CTRL__DISABLE_CRTC_FORCE_MASK 0x00100000L
+#define DSI0_DISP_DSI_TE_CTRL__CRTC_FREEZE_MASK 0x01000000L
+#define DSI0_DISP_DSI_TE_CTRL__CRTC_FREEZE_TRIG_MASK 0x01000000L
+//DSI0_DISP_DSI_LANE_STATUS
+#define DSI0_DISP_DSI_LANE_STATUS__DLN0_STOPSTATE__SHIFT 0x0
+#define DSI0_DISP_DSI_LANE_STATUS__DLN1_STOPSTATE__SHIFT 0x1
+#define DSI0_DISP_DSI_LANE_STATUS__DLN2_STOPSTATE__SHIFT 0x2
+#define DSI0_DISP_DSI_LANE_STATUS__DLN3_STOPSTATE__SHIFT 0x3
+#define DSI0_DISP_DSI_LANE_STATUS__DLN0_ULPS_ACTIVE_NOT__SHIFT 0x4
+#define DSI0_DISP_DSI_LANE_STATUS__DLN1_ULPS_ACTIVE_NOT__SHIFT 0x5
+#define DSI0_DISP_DSI_LANE_STATUS__DLN2_ULPS_ACTIVE_NOT__SHIFT 0x6
+#define DSI0_DISP_DSI_LANE_STATUS__DLN3_ULPS_ACTIVE_NOT__SHIFT 0x7
+#define DSI0_DISP_DSI_LANE_STATUS__DLN0_DIRECTION__SHIFT 0x8
+#define DSI0_DISP_DSI_LANE_STATUS__CLKLN_STOPSTATE__SHIFT 0x18
+#define DSI0_DISP_DSI_LANE_STATUS__CLKLN_ULPS_ACTIVE_NOT__SHIFT 0x1c
+#define DSI0_DISP_DSI_LANE_STATUS__DLN0_STOPSTATE_MASK 0x00000001L
+#define DSI0_DISP_DSI_LANE_STATUS__DLN1_STOPSTATE_MASK 0x00000002L
+#define DSI0_DISP_DSI_LANE_STATUS__DLN2_STOPSTATE_MASK 0x00000004L
+#define DSI0_DISP_DSI_LANE_STATUS__DLN3_STOPSTATE_MASK 0x00000008L
+#define DSI0_DISP_DSI_LANE_STATUS__DLN0_ULPS_ACTIVE_NOT_MASK 0x00000010L
+#define DSI0_DISP_DSI_LANE_STATUS__DLN1_ULPS_ACTIVE_NOT_MASK 0x00000020L
+#define DSI0_DISP_DSI_LANE_STATUS__DLN2_ULPS_ACTIVE_NOT_MASK 0x00000040L
+#define DSI0_DISP_DSI_LANE_STATUS__DLN3_ULPS_ACTIVE_NOT_MASK 0x00000080L
+#define DSI0_DISP_DSI_LANE_STATUS__DLN0_DIRECTION_MASK 0x00000100L
+#define DSI0_DISP_DSI_LANE_STATUS__CLKLN_STOPSTATE_MASK 0x01000000L
+#define DSI0_DISP_DSI_LANE_STATUS__CLKLN_ULPS_ACTIVE_NOT_MASK 0x10000000L
+//DSI0_DISP_DSI_PERF_CTRL
+#define DSI0_DISP_DSI_PERF_CTRL__PERF_LP_HS_LATENCY_SEL__SHIFT 0x0
+#define DSI0_DISP_DSI_PERF_CTRL__PERF_HS_LP_LATENCY_SEL__SHIFT 0x4
+#define DSI0_DISP_DSI_PERF_CTRL__PERF_LP_HS_LATENCY_SEL_MASK 0x00000003L
+#define DSI0_DISP_DSI_PERF_CTRL__PERF_HS_LP_LATENCY_SEL_MASK 0x00000030L
+//DSI0_DISP_DSI_HSYNC_LENGTH
+#define DSI0_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MAX__SHIFT 0x0
+#define DSI0_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MIN__SHIFT 0x10
+#define DSI0_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MAX_MASK 0x0000FFFFL
+#define DSI0_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MIN_MASK 0xFFFF0000L
+//DSI0_DISP_DSI_RDBK_NUM
+#define DSI0_DISP_DSI_RDBK_NUM__RD_NUM__SHIFT 0x0
+#define DSI0_DISP_DSI_RDBK_NUM__ALL_NUM__SHIFT 0x10
+#define DSI0_DISP_DSI_RDBK_NUM__RD_NUM_MASK 0x0000FFFFL
+#define DSI0_DISP_DSI_RDBK_NUM__ALL_NUM_MASK 0xFFFF0000L
+//DSI0_DISP_DSI_CMD_MEM_PWR_CTRL
+#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_DIS__SHIFT 0x0
+#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_FORCE__SHIFT 0x4
+#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_STATE__SHIFT 0x8
+#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_MODE_SEL__SHIFT 0xc
+#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_DIS_MASK 0x00000001L
+#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_FORCE_MASK 0x00000030L
+#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_STATE_MASK 0x00000300L
+#define DSI0_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_MODE_SEL_MASK 0x00003000L
+
+
+// addressBlock: dce_dc_dsi1_dispdec
+//DSI1_DISP_DSI_CTRL
+#define DSI1_DISP_DSI_CTRL__DSI_EN__SHIFT 0x0
+#define DSI1_DISP_DSI_CTRL__VIDEO_MODE_EN__SHIFT 0x1
+#define DSI1_DISP_DSI_CTRL__CMD_MODE_EN__SHIFT 0x2
+#define DSI1_DISP_DSI_CTRL__DLN0_EN__SHIFT 0x4
+#define DSI1_DISP_DSI_CTRL__DLN1_EN__SHIFT 0x5
+#define DSI1_DISP_DSI_CTRL__DLN2_EN__SHIFT 0x6
+#define DSI1_DISP_DSI_CTRL__DLN3_EN__SHIFT 0x7
+#define DSI1_DISP_DSI_CTRL__CLKLN_EN__SHIFT 0x8
+#define DSI1_DISP_DSI_CTRL__DLN0_PHY_EN__SHIFT 0xc
+#define DSI1_DISP_DSI_CTRL__DLN1_PHY_EN__SHIFT 0xd
+#define DSI1_DISP_DSI_CTRL__DLN2_PHY_EN__SHIFT 0xe
+#define DSI1_DISP_DSI_CTRL__DLN3_PHY_EN__SHIFT 0xf
+#define DSI1_DISP_DSI_CTRL__RESET_DISPCLK__SHIFT 0x10
+#define DSI1_DISP_DSI_CTRL__RESET_DSICLK__SHIFT 0x11
+#define DSI1_DISP_DSI_CTRL__RESET_BYTECLK__SHIFT 0x12
+#define DSI1_DISP_DSI_CTRL__RESET_ESCCLK__SHIFT 0x13
+#define DSI1_DISP_DSI_CTRL__CRTC_SEL__SHIFT 0x14
+#define DSI1_DISP_DSI_CTRL__ECC_CHK_EN__SHIFT 0x18
+#define DSI1_DISP_DSI_CTRL__CRC_CHK_EN__SHIFT 0x19
+#define DSI1_DISP_DSI_CTRL__PACKET_BYTE_MSB_LSB_FLIP__SHIFT 0x1c
+#define DSI1_DISP_DSI_CTRL__PRE_TRIGGER_EN__SHIFT 0x1d
+#define DSI1_DISP_DSI_CTRL__NEW_INTERLEAVE_MODE_EN__SHIFT 0x1e
+#define DSI1_DISP_DSI_CTRL__DSI_EN_MASK 0x00000001L
+#define DSI1_DISP_DSI_CTRL__VIDEO_MODE_EN_MASK 0x00000002L
+#define DSI1_DISP_DSI_CTRL__CMD_MODE_EN_MASK 0x00000004L
+#define DSI1_DISP_DSI_CTRL__DLN0_EN_MASK 0x00000010L
+#define DSI1_DISP_DSI_CTRL__DLN1_EN_MASK 0x00000020L
+#define DSI1_DISP_DSI_CTRL__DLN2_EN_MASK 0x00000040L
+#define DSI1_DISP_DSI_CTRL__DLN3_EN_MASK 0x00000080L
+#define DSI1_DISP_DSI_CTRL__CLKLN_EN_MASK 0x00000100L
+#define DSI1_DISP_DSI_CTRL__DLN0_PHY_EN_MASK 0x00001000L
+#define DSI1_DISP_DSI_CTRL__DLN1_PHY_EN_MASK 0x00002000L
+#define DSI1_DISP_DSI_CTRL__DLN2_PHY_EN_MASK 0x00004000L
+#define DSI1_DISP_DSI_CTRL__DLN3_PHY_EN_MASK 0x00008000L
+#define DSI1_DISP_DSI_CTRL__RESET_DISPCLK_MASK 0x00010000L
+#define DSI1_DISP_DSI_CTRL__RESET_DSICLK_MASK 0x00020000L
+#define DSI1_DISP_DSI_CTRL__RESET_BYTECLK_MASK 0x00040000L
+#define DSI1_DISP_DSI_CTRL__RESET_ESCCLK_MASK 0x00080000L
+#define DSI1_DISP_DSI_CTRL__CRTC_SEL_MASK 0x00700000L
+#define DSI1_DISP_DSI_CTRL__ECC_CHK_EN_MASK 0x01000000L
+#define DSI1_DISP_DSI_CTRL__CRC_CHK_EN_MASK 0x02000000L
+#define DSI1_DISP_DSI_CTRL__PACKET_BYTE_MSB_LSB_FLIP_MASK 0x10000000L
+#define DSI1_DISP_DSI_CTRL__PRE_TRIGGER_EN_MASK 0x20000000L
+#define DSI1_DISP_DSI_CTRL__NEW_INTERLEAVE_MODE_EN_MASK 0x40000000L
+//DSI1_DISP_DSI_STATUS
+#define DSI1_DISP_DSI_STATUS__CMD_MODE_ENGINE_BUSY__SHIFT 0x0
+#define DSI1_DISP_DSI_STATUS__CMD_MODE_DMA_BUSY__SHIFT 0x1
+#define DSI1_DISP_DSI_STATUS__CMD_MODE_DENG_BUSY__SHIFT 0x2
+#define DSI1_DISP_DSI_STATUS__VIDEO_MODE_ENGINE_BUSY__SHIFT 0x3
+#define DSI1_DISP_DSI_STATUS__BTA_BUSY__SHIFT 0x4
+#define DSI1_DISP_DSI_STATUS__GENERIC_TRIGGER_BUSY__SHIFT 0x5
+#define DSI1_DISP_DSI_STATUS__PHY_RESET_BUSY__SHIFT 0x6
+#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_EMPTY__SHIFT 0x8
+#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_FULL__SHIFT 0x9
+#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_EMPTY__SHIFT 0xa
+#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_FULL__SHIFT 0xb
+#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_EMPTY__SHIFT 0xc
+#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_FULL__SHIFT 0xd
+#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_EMPTY__SHIFT 0xe
+#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_FULL__SHIFT 0xf
+#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW__SHIFT 0x10
+#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_CLR__SHIFT 0x10
+#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW__SHIFT 0x11
+#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_CLR__SHIFT 0x11
+#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW__SHIFT 0x12
+#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_CLR__SHIFT 0x12
+#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW__SHIFT 0x13
+#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_CLR__SHIFT 0x13
+#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_EMPTY__SHIFT 0x14
+#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_FULL__SHIFT 0x15
+#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW__SHIFT 0x16
+#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_CLR__SHIFT 0x16
+#define DSI1_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW__SHIFT 0x17
+#define DSI1_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_CLR__SHIFT 0x17
+#define DSI1_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK__SHIFT 0x18
+#define DSI1_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_CLR__SHIFT 0x18
+#define DSI1_DISP_DSI_STATUS__TE_ABORT__SHIFT 0x19
+#define DSI1_DISP_DSI_STATUS__TE_ABORT_CLR__SHIFT 0x19
+#define DSI1_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH__SHIFT 0x1c
+#define DSI1_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_CLR__SHIFT 0x1c
+#define DSI1_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH__SHIFT 0x1d
+#define DSI1_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_CLR__SHIFT 0x1d
+#define DSI1_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW__SHIFT 0x1e
+#define DSI1_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_CLR__SHIFT 0x1e
+#define DSI1_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION__SHIFT 0x1f
+#define DSI1_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_CLR__SHIFT 0x1f
+#define DSI1_DISP_DSI_STATUS__CMD_MODE_ENGINE_BUSY_MASK 0x00000001L
+#define DSI1_DISP_DSI_STATUS__CMD_MODE_DMA_BUSY_MASK 0x00000002L
+#define DSI1_DISP_DSI_STATUS__CMD_MODE_DENG_BUSY_MASK 0x00000004L
+#define DSI1_DISP_DSI_STATUS__VIDEO_MODE_ENGINE_BUSY_MASK 0x00000008L
+#define DSI1_DISP_DSI_STATUS__BTA_BUSY_MASK 0x00000010L
+#define DSI1_DISP_DSI_STATUS__GENERIC_TRIGGER_BUSY_MASK 0x00000020L
+#define DSI1_DISP_DSI_STATUS__PHY_RESET_BUSY_MASK 0x00000040L
+#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_EMPTY_MASK 0x00000100L
+#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_FULL_MASK 0x00000200L
+#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_EMPTY_MASK 0x00000400L
+#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_FULL_MASK 0x00000800L
+#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_EMPTY_MASK 0x00001000L
+#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_FULL_MASK 0x00002000L
+#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_EMPTY_MASK 0x00004000L
+#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_FULL_MASK 0x00008000L
+#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_MASK 0x00010000L
+#define DSI1_DISP_DSI_STATUS__DLN0_HS_FIFO_OVERFLOW_CLR_MASK 0x00010000L
+#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_MASK 0x00020000L
+#define DSI1_DISP_DSI_STATUS__DLN1_HS_FIFO_OVERFLOW_CLR_MASK 0x00020000L
+#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_MASK 0x00040000L
+#define DSI1_DISP_DSI_STATUS__DLN2_HS_FIFO_OVERFLOW_CLR_MASK 0x00040000L
+#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_MASK 0x00080000L
+#define DSI1_DISP_DSI_STATUS__DLN3_HS_FIFO_OVERFLOW_CLR_MASK 0x00080000L
+#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_EMPTY_MASK 0x00100000L
+#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_FULL_MASK 0x00200000L
+#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_MASK 0x00400000L
+#define DSI1_DISP_DSI_STATUS__DLN0_LP_FIFO_OVERFLOW_CLR_MASK 0x00400000L
+#define DSI1_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_MASK 0x00800000L
+#define DSI1_DISP_DSI_STATUS__CMDFIFO_UNDERFLOW_CLR_MASK 0x00800000L
+#define DSI1_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_MASK 0x01000000L
+#define DSI1_DISP_DSI_STATUS__INTERLEAVE_PACKET_BLOCK_CLR_MASK 0x01000000L
+#define DSI1_DISP_DSI_STATUS__TE_ABORT_MASK 0x02000000L
+#define DSI1_DISP_DSI_STATUS__TE_ABORT_CLR_MASK 0x02000000L
+#define DSI1_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_MASK 0x10000000L
+#define DSI1_DISP_DSI_STATUS__DMAFIFO_RD_WATERMARK_REACH_CLR_MASK 0x10000000L
+#define DSI1_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_MASK 0x20000000L
+#define DSI1_DISP_DSI_STATUS__DMAFIFO_WR_WATERMARK_REACH_CLR_MASK 0x20000000L
+#define DSI1_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_MASK 0x40000000L
+#define DSI1_DISP_DSI_STATUS__DMAFIFO_UNDERFLOW_CLR_MASK 0x40000000L
+#define DSI1_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_MASK 0x80000000L
+#define DSI1_DISP_DSI_STATUS__INTERLEAVE_OP_CONTENTION_CLR_MASK 0x80000000L
+//DSI1_DISP_DSI_VIDEO_MODE_CTRL
+#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__VC__SHIFT 0x0
+#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__DST_FORMAT__SHIFT 0x4
+#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__TRAFFIC_MODE__SHIFT 0x8
+#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__BLLP_PWR_MODE__SHIFT 0xc
+#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__EOF_BLLP_PWR_MODE__SHIFT 0xf
+#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__HSA_PWR_MODE__SHIFT 0x10
+#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__HBP_PWR_MODE__SHIFT 0x14
+#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__HFP_PWR_MODE__SHIFT 0x18
+#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__PULSE_MODE_OPT__SHIFT 0x1c
+#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__VC_MASK 0x00000003L
+#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__DST_FORMAT_MASK 0x00000030L
+#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__TRAFFIC_MODE_MASK 0x00000300L
+#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__BLLP_PWR_MODE_MASK 0x00001000L
+#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__EOF_BLLP_PWR_MODE_MASK 0x00008000L
+#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__HSA_PWR_MODE_MASK 0x00010000L
+#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__HBP_PWR_MODE_MASK 0x00100000L
+#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__HFP_PWR_MODE_MASK 0x01000000L
+#define DSI1_DISP_DSI_VIDEO_MODE_CTRL__PULSE_MODE_OPT_MASK 0x10000000L
+//DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE
+#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VS__SHIFT 0x0
+#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VE__SHIFT 0x8
+#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HS__SHIFT 0x10
+#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HE__SHIFT 0x18
+#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VS_MASK 0x0000003FL
+#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__VE_MASK 0x00003F00L
+#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HS_MASK 0x003F0000L
+#define DSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE__HE_MASK 0x3F000000L
+//DSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD
+#define DSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VS_PAYLOAD__SHIFT 0x0
+#define DSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VE_PAYLOAD__SHIFT 0x10
+#define DSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VS_PAYLOAD_MASK 0x0000FFFFL
+#define DSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD__VE_PAYLOAD_MASK 0xFFFF0000L
+//DSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD
+#define DSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HS_PAYLOAD__SHIFT 0x0
+#define DSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HE_PAYLOAD__SHIFT 0x10
+#define DSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HS_PAYLOAD_MASK 0x0000FFFFL
+#define DSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD__HE_PAYLOAD_MASK 0xFFFF0000L
+//DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE
+#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB565__SHIFT 0x0
+#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_PACKED__SHIFT 0x8
+#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666__SHIFT 0x10
+#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB888__SHIFT 0x18
+#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB565_MASK 0x0000003FL
+#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_PACKED_MASK 0x00003F00L
+#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB666_MASK 0x003F0000L
+#define DSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE__RGB888_MASK 0x3F000000L
+//DSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE
+#define DSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATA__SHIFT 0x0
+#define DSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATATYPE__SHIFT 0x8
+#define DSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATA_MASK 0x000000FFL
+#define DSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE__BLANK_PKT_DATATYPE_MASK 0x00003F00L
+//DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL
+#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__R_SEL__SHIFT 0x0
+#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__G_SEL__SHIFT 0x4
+#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__B_SEL__SHIFT 0x8
+#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__RGB_SWAP__SHIFT 0xc
+#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__R_SEL_MASK 0x00000001L
+#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__G_SEL_MASK 0x00000010L
+#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__B_SEL_MASK 0x00000100L
+#define DSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL__RGB_SWAP_MASK 0x00007000L
+//DSI1_DISP_DSI_COMMAND_MODE_CTRL
+#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__WC__SHIFT 0x0
+#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__DT__SHIFT 0x10
+#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__VC__SHIFT 0x16
+#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__PACKET_TYPE__SHIFT 0x18
+#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__POWER_MODE__SHIFT 0x1a
+#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__EMBEDDED_MODE__SHIFT 0x1c
+#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__CMD_DATA_ORDER__SHIFT 0x1f
+#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__WC_MASK 0x0000FFFFL
+#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__DT_MASK 0x003F0000L
+#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__VC_MASK 0x00C00000L
+#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__PACKET_TYPE_MASK 0x01000000L
+#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__POWER_MODE_MASK 0x04000000L
+#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__EMBEDDED_MODE_MASK 0x10000000L
+#define DSI1_DISP_DSI_COMMAND_MODE_CTRL__CMD_DATA_ORDER_MASK 0x80000000L
+//DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL
+#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__SRC_FORMAT__SHIFT 0x0
+#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DST_FORMAT__SHIFT 0x4
+#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DATA_BUFFER_ID__SHIFT 0x8
+#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__SHADOW_DATA_BUFFER_ID__SHIFT 0xc
+#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__R_SEL__SHIFT 0x10
+#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__G_SEL__SHIFT 0x11
+#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__B_SEL__SHIFT 0x12
+#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__RGB_SWAP__SHIFT 0x14
+#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DWORD_BYTE_SWAP__SHIFT 0x18
+#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__SRC_FORMAT_MASK 0x0000000FL
+#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DST_FORMAT_MASK 0x000000F0L
+#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DATA_BUFFER_ID_MASK 0x00000100L
+#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__SHADOW_DATA_BUFFER_ID_MASK 0x00001000L
+#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__R_SEL_MASK 0x00010000L
+#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__G_SEL_MASK 0x00020000L
+#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__B_SEL_MASK 0x00040000L
+#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__RGB_SWAP_MASK 0x00700000L
+#define DSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL__DWORD_BYTE_SWAP_MASK 0x03000000L
+//DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL
+#define DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_START__SHIFT 0x0
+#define DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_CONTINUE__SHIFT 0x8
+#define DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__INSERT_DCS_COMMAND__SHIFT 0x10
+#define DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_START_MASK 0x000000FFL
+#define DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__WR_MEM_CONTINUE_MASK 0x0000FF00L
+#define DSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL__INSERT_DCS_COMMAND_MASK 0x00010000L
+//DSI1_DISP_DSI_DMA_CMD_OFFSET
+#define DSI1_DISP_DSI_DMA_CMD_OFFSET__CMD_OFFSET__SHIFT 0x0
+#define DSI1_DISP_DSI_DMA_CMD_OFFSET__CMD_OFFSET_MASK 0xFFFFFFFFL
+//DSI1_DISP_DSI_DMA_CMD_LENGTH
+#define DSI1_DISP_DSI_DMA_CMD_LENGTH__CMD_LENGTH__SHIFT 0x0
+#define DSI1_DISP_DSI_DMA_CMD_LENGTH__CMD_LENGTH_MASK 0x00FFFFFFL
+//DSI1_DISP_DSI_DMA_DATA_OFFSET_0
+#define DSI1_DISP_DSI_DMA_DATA_OFFSET_0__DATA_SRC_OFFSET0__SHIFT 0x0
+#define DSI1_DISP_DSI_DMA_DATA_OFFSET_0__DATA_SRC_OFFSET0_MASK 0xFFFFFFFFL
+//DSI1_DISP_DSI_DMA_DATA_OFFSET_1
+#define DSI1_DISP_DSI_DMA_DATA_OFFSET_1__DATA_SRC_OFFSET1__SHIFT 0x0
+#define DSI1_DISP_DSI_DMA_DATA_OFFSET_1__DATA_SRC_OFFSET1_MASK 0xFFFFFFFFL
+//DSI1_DISP_DSI_DMA_DATA_PITCH
+#define DSI1_DISP_DSI_DMA_DATA_PITCH__DATA_SRC_PITCH__SHIFT 0x0
+#define DSI1_DISP_DSI_DMA_DATA_PITCH__DATA_SRC_PITCH_MASK 0x00007FFFL
+//DSI1_DISP_DSI_DMA_DATA_WIDTH
+#define DSI1_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH__SHIFT 0x0
+#define DSI1_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_ALIGN__SHIFT 0x18
+#define DSI1_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_MASK 0x000FFFFFL
+#define DSI1_DISP_DSI_DMA_DATA_WIDTH__DATA_SRC_WIDTH_ALIGN_MASK 0x07000000L
+//DSI1_DISP_DSI_DMA_DATA_HEIGHT
+#define DSI1_DISP_DSI_DMA_DATA_HEIGHT__DATA_SRC_HEIGHT__SHIFT 0x0
+#define DSI1_DISP_DSI_DMA_DATA_HEIGHT__DATA_SRC_HEIGHT_MASK 0x00000FFFL
+//DSI1_DISP_DSI_DMA_FIFO_CTRL
+#define DSI1_DISP_DSI_DMA_FIFO_CTRL__WRITE_WATERMARK__SHIFT 0x0
+#define DSI1_DISP_DSI_DMA_FIFO_CTRL__READ_WATERMARK__SHIFT 0x4
+#define DSI1_DISP_DSI_DMA_FIFO_CTRL__WRITE_WATERMARK_MASK 0x00000003L
+#define DSI1_DISP_DSI_DMA_FIFO_CTRL__READ_WATERMARK_MASK 0x00000030L
+//DSI1_DISP_DSI_DMA_NULL_PACKET_DATA
+#define DSI1_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATA__SHIFT 0x0
+#define DSI1_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATATYPE__SHIFT 0x8
+#define DSI1_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATA_MASK 0x000000FFL
+#define DSI1_DISP_DSI_DMA_NULL_PACKET_DATA__NULL_DATATYPE_MASK 0x00003F00L
+//DSI1_DISP_DSI_DENG_DATA_LENGTH
+#define DSI1_DISP_DSI_DENG_DATA_LENGTH__DENG_LENGTH__SHIFT 0x0
+#define DSI1_DISP_DSI_DENG_DATA_LENGTH__USE_DENG_LENGTH__SHIFT 0x1f
+#define DSI1_DISP_DSI_DENG_DATA_LENGTH__DENG_LENGTH_MASK 0x00FFFFFFL
+#define DSI1_DISP_DSI_DENG_DATA_LENGTH__USE_DENG_LENGTH_MASK 0x80000000L
+//DSI1_DISP_DSI_ACK_ERROR_REPORT
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR__SHIFT 0x0
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_CLR__SHIFT 0x0
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR__SHIFT 0x1
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_CLR__SHIFT 0x1
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR__SHIFT 0x2
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_CLR__SHIFT 0x2
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR__SHIFT 0x3
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_CLR__SHIFT 0x3
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__LP_ERR__SHIFT 0x4
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_CLR__SHIFT 0x4
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__HRX_TO__SHIFT 0x5
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_CLR__SHIFT 0x5
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR__SHIFT 0x6
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_CLR__SHIFT 0x6
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR__SHIFT 0x7
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_CLR__SHIFT 0x7
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR__SHIFT 0x8
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_CLR__SHIFT 0x8
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR__SHIFT 0x9
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_CLR__SHIFT 0x9
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR__SHIFT 0xa
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_CLR__SHIFT 0xa
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__DT_ERR__SHIFT 0xb
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_CLR__SHIFT 0xb
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__VC_ERR__SHIFT 0xc
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_CLR__SHIFT 0xc
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION__SHIFT 0xd
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_CLR__SHIFT 0xd
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR__SHIFT 0xf
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_CLR__SHIFT 0xf
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR__SHIFT 0x10
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_CLR__SHIFT 0x10
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR__SHIFT 0x11
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_CLR__SHIFT 0x11
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR__SHIFT 0x14
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_CLR__SHIFT 0x14
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR__SHIFT 0x17
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_CLR__SHIFT 0x17
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ERROR__SHIFT 0x18
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ERROR_CLR__SHIFT 0x18
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ACK__SHIFT 0x1c
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ACK_CLR__SHIFT 0x1c
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_MASK 0x00000001L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_ERR_CLR_MASK 0x00000001L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_MASK 0x00000002L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__SOT_SYNC_ERR_CLR_MASK 0x00000002L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_MASK 0x00000004L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__EOT_ERR_CLR_MASK 0x00000004L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_MASK 0x00000008L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ESC_ERR_CLR_MASK 0x00000008L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_MASK 0x00000010L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__LP_ERR_CLR_MASK 0x00000010L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_MASK 0x00000020L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__HRX_TO_CLR_MASK 0x00000020L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_MASK 0x00000040L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__FALSE_CTRL_ERR_CLR_MASK 0x00000040L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_MASK 0x00000080L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CONTENTION_ERR_CLR_MASK 0x00000080L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_MASK 0x00000100L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ECC_ERR_CLR_MASK 0x00000100L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_MASK 0x00000200L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__MULTI_ECC_ERR_CLR_MASK 0x00000200L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_MASK 0x00000400L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__CRC_ERR_CLR_MASK 0x00000400L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_MASK 0x00000800L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__DT_ERR_CLR_MASK 0x00000800L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_MASK 0x00001000L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__VC_ERR_CLR_MASK 0x00001000L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_MASK 0x00002000L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PROTOCOL_VIOLATION_CLR_MASK 0x00002000L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_MASK 0x00008000L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__PANEL_SPECIFIC_ERR_CLR_MASK 0x00008000L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_MASK 0x00010000L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_ECC_ERR_CLR_MASK 0x00010000L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_MASK 0x00020000L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_MULTI_ECC_ERR_CLR_MASK 0x00020000L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_MASK 0x00100000L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_DATA_CRC_ERR_CLR_MASK 0x00100000L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_MASK 0x00800000L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__RDBK_INCOMPLETE_PACKET_ERR_CLR_MASK 0x00800000L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ERROR_MASK 0x01000000L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ERROR_CLR_MASK 0x01000000L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ACK_MASK 0x10000000L
+#define DSI1_DISP_DSI_ACK_ERROR_REPORT__ACK_CLR_MASK 0x10000000L
+//DSI1_DISP_DSI_RDBK_DATA0
+#define DSI1_DISP_DSI_RDBK_DATA0__RD_DATA0__SHIFT 0x0
+#define DSI1_DISP_DSI_RDBK_DATA0__RD_DATA0_MASK 0xFFFFFFFFL
+//DSI1_DISP_DSI_RDBK_DATA1
+#define DSI1_DISP_DSI_RDBK_DATA1__RD_DATA1__SHIFT 0x0
+#define DSI1_DISP_DSI_RDBK_DATA1__RD_DATA1_MASK 0xFFFFFFFFL
+//DSI1_DISP_DSI_RDBK_DATA2
+#define DSI1_DISP_DSI_RDBK_DATA2__RD_DATA2__SHIFT 0x0
+#define DSI1_DISP_DSI_RDBK_DATA2__RD_DATA2_MASK 0xFFFFFFFFL
+//DSI1_DISP_DSI_RDBK_DATA3
+#define DSI1_DISP_DSI_RDBK_DATA3__RD_DATA3__SHIFT 0x0
+#define DSI1_DISP_DSI_RDBK_DATA3__RD_DATA3_MASK 0xFFFFFFFFL
+//DSI1_DISP_DSI_RDBK_DATATYPE0
+#define DSI1_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_1_BYTE__SHIFT 0x0
+#define DSI1_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_2_BYTE__SHIFT 0x8
+#define DSI1_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_1_BYTE__SHIFT 0x10
+#define DSI1_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_2_BYTE__SHIFT 0x18
+#define DSI1_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_1_BYTE_MASK 0x0000003FL
+#define DSI1_DISP_DSI_RDBK_DATATYPE0__GENERIC_SHORT_RD_2_BYTE_MASK 0x00003F00L
+#define DSI1_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_1_BYTE_MASK 0x003F0000L
+#define DSI1_DISP_DSI_RDBK_DATATYPE0__DCS_SHORT_RD_2_BYTE_MASK 0x3F000000L
+//DSI1_DISP_DSI_RDBK_DATATYPE1
+#define DSI1_DISP_DSI_RDBK_DATATYPE1__ERROR_REPORT__SHIFT 0x0
+#define DSI1_DISP_DSI_RDBK_DATATYPE1__GENERIC_LONG_RD__SHIFT 0x8
+#define DSI1_DISP_DSI_RDBK_DATATYPE1__DCS_LONG_RD__SHIFT 0x10
+#define DSI1_DISP_DSI_RDBK_DATATYPE1__ERROR_REPORT_MASK 0x0000003FL
+#define DSI1_DISP_DSI_RDBK_DATATYPE1__GENERIC_LONG_RD_MASK 0x00003F00L
+#define DSI1_DISP_DSI_RDBK_DATATYPE1__DCS_LONG_RD_MASK 0x003F0000L
+//DSI1_DISP_DSI_TRIG_CTRL
+#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_MODE__SHIFT 0x0
+#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_SEL__SHIFT 0x4
+#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_MODE__SHIFT 0x10
+#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_SEL__SHIFT 0x14
+#define DSI1_DISP_DSI_TRIG_CTRL__HW_SOURCE_SEL__SHIFT 0x18
+#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_DENG_ORDER__SHIFT 0x1c
+#define DSI1_DISP_DSI_TRIG_CTRL__TE_SEL__SHIFT 0x1f
+#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_MODE_MASK 0x00000001L
+#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_TRIGGER_SEL_MASK 0x00000030L
+#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_MODE_MASK 0x00010000L
+#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DENG_TRIGGER_SEL_MASK 0x00300000L
+#define DSI1_DISP_DSI_TRIG_CTRL__HW_SOURCE_SEL_MASK 0x0F000000L
+#define DSI1_DISP_DSI_TRIG_CTRL__COMMAND_MODE_DMA_DENG_ORDER_MASK 0x10000000L
+#define DSI1_DISP_DSI_TRIG_CTRL__TE_SEL_MASK 0x80000000L
+//DSI1_DISP_DSI_EXT_MUX
+#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_MUX__SHIFT 0x0
+#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_MODE__SHIFT 0x4
+#define DSI1_DISP_DSI_EXT_MUX__EXT_RESET_POL__SHIFT 0x6
+#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_POL__SHIFT 0x7
+#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TRIG_CNT__SHIFT 0x8
+#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TOTAL__SHIFT 0x14
+#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_MUX_MASK 0x0000000FL
+#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_MODE_MASK 0x00000030L
+#define DSI1_DISP_DSI_EXT_MUX__EXT_RESET_POL_MASK 0x00000040L
+#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_POL_MASK 0x00000080L
+#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TRIG_CNT_MASK 0x000FFF00L
+#define DSI1_DISP_DSI_EXT_MUX__EXT_TE_HSYNC_TOTAL_MASK 0xFFF00000L
+//DSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL
+#define DSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_HSYNC_MAX_WIDTH__SHIFT 0x0
+#define DSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_VSYNC_MIN_WIDTH__SHIFT 0x10
+#define DSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_HSYNC_MAX_WIDTH_MASK 0x0000FFFFL
+#define DSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL__TE_VSYNC_MIN_WIDTH_MASK 0xFFFF0000L
+//DSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER
+#define DSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
+#define DSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
+//DSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER
+#define DSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
+#define DSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
+//DSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER
+#define DSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
+#define DSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
+//DSI1_DISP_DSI_RESET_SW_TRIGGER
+#define DSI1_DISP_DSI_RESET_SW_TRIGGER__SW_TRIGGER__SHIFT 0x0
+#define DSI1_DISP_DSI_RESET_SW_TRIGGER__SW_TRIGGER_MASK 0x00000001L
+//DSI1_DISP_DSI_EXT_RESET
+#define DSI1_DISP_DSI_EXT_RESET__RESET_PANEL__SHIFT 0x0
+#define DSI1_DISP_DSI_EXT_RESET__RESET_PANEL_MASK 0x00000001L
+//DSI1_DISP_DSI_LANE_CRC_HS_MODE
+#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN0_HS_CRC__SHIFT 0x0
+#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN1_HS_CRC__SHIFT 0x8
+#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN2_HS_CRC__SHIFT 0x10
+#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN3_HS_CRC__SHIFT 0x18
+#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN0_HS_CRC_MASK 0x000000FFL
+#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN1_HS_CRC_MASK 0x0000FF00L
+#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN2_HS_CRC_MASK 0x00FF0000L
+#define DSI1_DISP_DSI_LANE_CRC_HS_MODE__DLN3_HS_CRC_MASK 0xFF000000L
+//DSI1_DISP_DSI_LANE_CRC_LP_MODE
+#define DSI1_DISP_DSI_LANE_CRC_LP_MODE__DLN0_LP_CRC__SHIFT 0x0
+#define DSI1_DISP_DSI_LANE_CRC_LP_MODE__DLN0_LP_CRC_MASK 0x000000FFL
+//DSI1_DISP_DSI_LANE_CRC_CTRL
+#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_HS_DONE_COUNT__SHIFT 0x0
+#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_LP_DONE_COUNT__SHIFT 0x8
+#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_ENABLE__SHIFT 0x10
+#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_HS__SHIFT 0x14
+#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_LP__SHIFT 0x18
+#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_HS_DONE_COUNT_MASK 0x000000FFL
+#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_MAX_LP_DONE_COUNT_MASK 0x0000FF00L
+#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_ENABLE_MASK 0x00010000L
+#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_HS_MASK 0x00100000L
+#define DSI1_DISP_DSI_LANE_CRC_CTRL__CRC_DONE_LP_MASK 0x01000000L
+//DSI1_DISP_DSI_PIXEL_CRC_CTRL
+#define DSI1_DISP_DSI_PIXEL_CRC_CTRL__CRC_MAX_PIXEL_COUNT__SHIFT 0x0
+#define DSI1_DISP_DSI_PIXEL_CRC_CTRL__PIXEL_CRC__SHIFT 0x8
+#define DSI1_DISP_DSI_PIXEL_CRC_CTRL__CRC_DONE_PIXEL__SHIFT 0x10
+#define DSI1_DISP_DSI_PIXEL_CRC_CTRL__CRC_MAX_PIXEL_COUNT_MASK 0x000000FFL
+#define DSI1_DISP_DSI_PIXEL_CRC_CTRL__PIXEL_CRC_MASK 0x0000FF00L
+#define DSI1_DISP_DSI_PIXEL_CRC_CTRL__CRC_DONE_PIXEL_MASK 0x00010000L
+//DSI1_DISP_DSI_LANE_CTRL
+#define DSI1_DISP_DSI_LANE_CTRL__DLN0_ULPS_REQUEST__SHIFT 0x0
+#define DSI1_DISP_DSI_LANE_CTRL__DLN1_ULPS_REQUEST__SHIFT 0x1
+#define DSI1_DISP_DSI_LANE_CTRL__DLN2_ULPS_REQUEST__SHIFT 0x2
+#define DSI1_DISP_DSI_LANE_CTRL__DLN3_ULPS_REQUEST__SHIFT 0x3
+#define DSI1_DISP_DSI_LANE_CTRL__DLN0_ULPS_EXIT__SHIFT 0x4
+#define DSI1_DISP_DSI_LANE_CTRL__DLN1_ULPS_EXIT__SHIFT 0x5
+#define DSI1_DISP_DSI_LANE_CTRL__DLN2_ULPS_EXIT__SHIFT 0x6
+#define DSI1_DISP_DSI_LANE_CTRL__DLN3_ULPS_EXIT__SHIFT 0x7
+#define DSI1_DISP_DSI_LANE_CTRL__DLN0_FORCE_TX_STOP__SHIFT 0x8
+#define DSI1_DISP_DSI_LANE_CTRL__DLN1_FORCE_TX_STOP__SHIFT 0x9
+#define DSI1_DISP_DSI_LANE_CTRL__DLN2_FORCE_TX_STOP__SHIFT 0xa
+#define DSI1_DISP_DSI_LANE_CTRL__DLN3_FORCE_TX_STOP__SHIFT 0xb
+#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_ULPS_REQUEST__SHIFT 0xc
+#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_ULPS_EXIT__SHIFT 0x10
+#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_FORCE_TX_STOP__SHIFT 0x14
+#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_HS_FORCE_REQUEST__SHIFT 0x18
+#define DSI1_DISP_DSI_LANE_CTRL__DLN0_ULPS_REQUEST_MASK 0x00000001L
+#define DSI1_DISP_DSI_LANE_CTRL__DLN1_ULPS_REQUEST_MASK 0x00000002L
+#define DSI1_DISP_DSI_LANE_CTRL__DLN2_ULPS_REQUEST_MASK 0x00000004L
+#define DSI1_DISP_DSI_LANE_CTRL__DLN3_ULPS_REQUEST_MASK 0x00000008L
+#define DSI1_DISP_DSI_LANE_CTRL__DLN0_ULPS_EXIT_MASK 0x00000010L
+#define DSI1_DISP_DSI_LANE_CTRL__DLN1_ULPS_EXIT_MASK 0x00000020L
+#define DSI1_DISP_DSI_LANE_CTRL__DLN2_ULPS_EXIT_MASK 0x00000040L
+#define DSI1_DISP_DSI_LANE_CTRL__DLN3_ULPS_EXIT_MASK 0x00000080L
+#define DSI1_DISP_DSI_LANE_CTRL__DLN0_FORCE_TX_STOP_MASK 0x00000100L
+#define DSI1_DISP_DSI_LANE_CTRL__DLN1_FORCE_TX_STOP_MASK 0x00000200L
+#define DSI1_DISP_DSI_LANE_CTRL__DLN2_FORCE_TX_STOP_MASK 0x00000400L
+#define DSI1_DISP_DSI_LANE_CTRL__DLN3_FORCE_TX_STOP_MASK 0x00000800L
+#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_ULPS_REQUEST_MASK 0x00001000L
+#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_ULPS_EXIT_MASK 0x00010000L
+#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_FORCE_TX_STOP_MASK 0x00100000L
+#define DSI1_DISP_DSI_LANE_CTRL__CLKLN_HS_FORCE_REQUEST_MASK 0x01000000L
+//DSI1_DISP_DSI_DLN0_PHY_ERROR
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC__SHIFT 0x0
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_CLR__SHIFT 0x0
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK__SHIFT 0x3
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC__SHIFT 0x4
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_CLR__SHIFT 0x4
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK__SHIFT 0x7
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL__SHIFT 0x8
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_CLR__SHIFT 0x8
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK__SHIFT 0xb
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0__SHIFT 0xc
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_CLR__SHIFT 0xc
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK__SHIFT 0xf
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1__SHIFT 0x10
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_CLR__SHIFT 0x10
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK__SHIFT 0x13
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK 0x00000001L
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_CLR_MASK 0x00000001L
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_ESC_MASK_MASK 0x00000008L
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK 0x00000010L
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_CLR_MASK 0x00000010L
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_SYNC_ESC_MASK_MASK 0x00000080L
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK 0x00000100L
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_CLR_MASK 0x00000100L
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTROL_MASK_MASK 0x00000800L
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK 0x00001000L
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_CLR_MASK 0x00001000L
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP0_MASK_MASK 0x00008000L
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK 0x00010000L
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_CLR_MASK 0x00010000L
+#define DSI1_DISP_DSI_DLN0_PHY_ERROR__DLN0_ERR_CONTENTION_LP1_MASK_MASK 0x00080000L
+//DSI1_DISP_DSI_LP_TIMER_CTRL
+#define DSI1_DISP_DSI_LP_TIMER_CTRL__LP_RX_TO__SHIFT 0x0
+#define DSI1_DISP_DSI_LP_TIMER_CTRL__BTA_TO__SHIFT 0x10
+#define DSI1_DISP_DSI_LP_TIMER_CTRL__LP_RX_TO_MASK 0x0000FFFFL
+#define DSI1_DISP_DSI_LP_TIMER_CTRL__BTA_TO_MASK 0xFFFF0000L
+//DSI1_DISP_DSI_HS_TIMER_CTRL
+#define DSI1_DISP_DSI_HS_TIMER_CTRL__HS_TX_TO__SHIFT 0x0
+#define DSI1_DISP_DSI_HS_TIMER_CTRL__HS_TX_TO_MASK 0x0000FFFFL
+//DSI1_DISP_DSI_TIMEOUT_STATUS
+#define DSI1_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT__SHIFT 0x0
+#define DSI1_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_CLR__SHIFT 0x0
+#define DSI1_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT__SHIFT 0x4
+#define DSI1_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_CLR__SHIFT 0x4
+#define DSI1_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT__SHIFT 0x8
+#define DSI1_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_CLR__SHIFT 0x8
+#define DSI1_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_MASK 0x00000001L
+#define DSI1_DISP_DSI_TIMEOUT_STATUS__HS_TX_TIMEOUT_CLR_MASK 0x00000001L
+#define DSI1_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_MASK 0x00000010L
+#define DSI1_DISP_DSI_TIMEOUT_STATUS__LP_RX_TIMEOUT_CLR_MASK 0x00000010L
+#define DSI1_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_MASK 0x00000100L
+#define DSI1_DISP_DSI_TIMEOUT_STATUS__BTA_TIMEOUT_CLR_MASK 0x00000100L
+//DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL
+#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_PRE__SHIFT 0x0
+#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_POST__SHIFT 0x8
+#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_PRE_MASK 0x000000FFL
+#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL__T_CLK_POST_MASK 0x00003F00L
+//DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2
+#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_PRE_TRIGGER__SHIFT 0x0
+#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_INTER_STOP__SHIFT 0x10
+#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_PRE_TRIGGER_MASK 0x000007FFL
+#define DSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2__T_INTER_STOP_MASK 0xFFFF0000L
+//DSI1_DISP_DSI_EOT_PACKET
+#define DSI1_DISP_DSI_EOT_PACKET__DI__SHIFT 0x0
+#define DSI1_DISP_DSI_EOT_PACKET__WC__SHIFT 0x8
+#define DSI1_DISP_DSI_EOT_PACKET__ECC__SHIFT 0x18
+#define DSI1_DISP_DSI_EOT_PACKET__DI_MASK 0x000000FFL
+#define DSI1_DISP_DSI_EOT_PACKET__WC_MASK 0x00FFFF00L
+#define DSI1_DISP_DSI_EOT_PACKET__ECC_MASK 0xFF000000L
+//DSI1_DISP_DSI_EOT_PACKET_CTRL
+#define DSI1_DISP_DSI_EOT_PACKET_CTRL__TX_EOT_APPEND__SHIFT 0x0
+#define DSI1_DISP_DSI_EOT_PACKET_CTRL__RX_EOT_IGNORE__SHIFT 0x4
+#define DSI1_DISP_DSI_EOT_PACKET_CTRL__TX_EOT_APPEND_MASK 0x00000001L
+#define DSI1_DISP_DSI_EOT_PACKET_CTRL__RX_EOT_IGNORE_MASK 0x00000010L
+//DSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER
+#define DSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER__SW_TRIGGER__SHIFT 0x0
+#define DSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER__ENTRY_COMMAND__SHIFT 0x10
+#define DSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER__SW_TRIGGER_MASK 0x00000001L
+#define DSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER__ENTRY_COMMAND_MASK 0x00FF0000L
+//DSI1_DISP_DSI_MIPI_BIST_CTRL
+#define DSI1_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_RESET__SHIFT 0x0
+#define DSI1_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_EN__SHIFT 0x1
+#define DSI1_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_RESET_MASK 0x00000001L
+#define DSI1_DISP_DSI_MIPI_BIST_CTRL__MIPI_BIST_EN_MASK 0x00000002L
+//DSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE
+#define DSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_H_SIZE__SHIFT 0x0
+#define DSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_V_SIZE__SHIFT 0x10
+#define DSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_H_SIZE_MASK 0x0000FFFFL
+#define DSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE__MIPI_V_SIZE_MASK 0xFFFF0000L
+//DSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE
+#define DSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_H_SIZE__SHIFT 0x0
+#define DSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_V_SIZE__SHIFT 0x8
+#define DSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_H_SIZE_MASK 0x000000FFL
+#define DSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE__MIPI_V_SIZE_MASK 0x0000FF00L
+//DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG
+#define DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BLANKING_CYCLES__SHIFT 0x0
+#define DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_FRAME_REPEAT__SHIFT 0x10
+#define DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BIST_VIDEO_FRMT__SHIFT 0x18
+#define DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BLANKING_CYCLES_MASK 0x0000FFFFL
+#define DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_FRAME_REPEAT_MASK 0x00FF0000L
+#define DSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG__MIPI_BIST_VIDEO_FRMT_MASK 0x01000000L
+//DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL
+#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_POLYNOMIAL__SHIFT 0x0
+#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_POLYNOMIAL__SHIFT 0x8
+#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_POLYNOMIAL__SHIFT 0x10
+#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_EN__SHIFT 0x18
+#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_EN__SHIFT 0x19
+#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_EN__SHIFT 0x1a
+#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_POLYNOMIAL_MASK 0x000000FFL
+#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_POLYNOMIAL_MASK 0x0000FF00L
+#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_POLYNOMIAL_MASK 0x00FF0000L
+#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_Y_LSFR_EN_MASK 0x01000000L
+#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_U_LSFR_EN_MASK 0x02000000L
+#define DSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL__MIPI_V_LSFR_EN_MASK 0x04000000L
+//DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT
+#define DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_Y_INIT_LSFR_VAL__SHIFT 0x0
+#define DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_U_INIT_LSFR_VAL__SHIFT 0x8
+#define DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_V_INIT_LSFR_VAL__SHIFT 0x10
+#define DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_Y_INIT_LSFR_VAL_MASK 0x000000FFL
+#define DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_U_INIT_LSFR_VAL_MASK 0x0000FF00L
+#define DSI1_DISP_DSI_MIPI_BIST_LSFR_INIT__MIPI_V_INIT_LSFR_VAL_MASK 0x00FF0000L
+//DSI1_DISP_DSI_MIPI_BIST_START
+#define DSI1_DISP_DSI_MIPI_BIST_START__MIPI_BIST_START__SHIFT 0x0
+#define DSI1_DISP_DSI_MIPI_BIST_START__MIPI_BIST_START_MASK 0x00000001L
+//DSI1_DISP_DSI_MIPI_BIST_STATUS
+#define DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_STATUS_BUSY__SHIFT 0x0
+#define DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE__SHIFT 0x4
+#define DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_CLR__SHIFT 0x4
+#define DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_STATUS_BUSY_MASK 0x00000001L
+#define DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_MASK 0x00000010L
+#define DSI1_DISP_DSI_MIPI_BIST_STATUS__MIPI_BIST_DONE_CLR_MASK 0x00000010L
+//DSI1_DISP_DSI_ERROR_INTERRUPT_MASK
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_ECC_ERR_MASK__SHIFT 0x0
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_MULTI_ECC_ERR_MASK__SHIFT 0x1
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_CRC_ERR_MASK__SHIFT 0x2
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_INCOMPLETE_PACKET_ERR_MASK__SHIFT 0x3
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__ERROR_PACKET_MASK__SHIFT 0x4
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_PACKET_BLOCK_MASK__SHIFT 0x5
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__TE_ABORT_MASK__SHIFT 0x6
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_ESC_MASK__SHIFT 0x8
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_SYNC_ESC_MASK__SHIFT 0x9
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTROL_MASK__SHIFT 0xa
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP0_MASK__SHIFT 0xc
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP1_MASK__SHIFT 0xd
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__LP_RX_TO_MASK__SHIFT 0x10
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__HS_TX_TO_MASK__SHIFT 0x11
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__BTA_TO_MASK__SHIFT 0x12
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DMAFIFO_UNDERFLOW_MASK__SHIFT 0x14
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__CMDFIFO_UNDERFLOW_MASK__SHIFT 0x15
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DENGFIFO_OVERFLOW_UNDERFLOW_MASK__SHIFT 0x18
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1a
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN1_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1b
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN2_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1c
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN3_HS_FIFO_OVERFLOW_MASK__SHIFT 0x1d
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_LP_FIFO_OVERFLOW_MASK__SHIFT 0x1e
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_OP_CONTENTION_MASK__SHIFT 0x1f
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_ECC_ERR_MASK_MASK 0x00000001L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_MULTI_ECC_ERR_MASK_MASK 0x00000002L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_DATA_CRC_ERR_MASK_MASK 0x00000004L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__RDBK_INCOMPLETE_PACKET_ERR_MASK_MASK 0x00000008L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__ERROR_PACKET_MASK_MASK 0x00000010L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_PACKET_BLOCK_MASK_MASK 0x00000020L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__TE_ABORT_MASK_MASK 0x00000040L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_ESC_MASK_MASK 0x00000100L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_SYNC_ESC_MASK_MASK 0x00000200L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTROL_MASK_MASK 0x00000400L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP0_MASK_MASK 0x00001000L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_ERR_CONTENTION_LP1_MASK_MASK 0x00002000L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__LP_RX_TO_MASK_MASK 0x00010000L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__HS_TX_TO_MASK_MASK 0x00020000L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__BTA_TO_MASK_MASK 0x00040000L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DMAFIFO_UNDERFLOW_MASK_MASK 0x00100000L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__CMDFIFO_UNDERFLOW_MASK_MASK 0x00200000L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DENGFIFO_OVERFLOW_UNDERFLOW_MASK_MASK 0x01000000L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_HS_FIFO_OVERFLOW_MASK_MASK 0x04000000L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN1_HS_FIFO_OVERFLOW_MASK_MASK 0x08000000L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN2_HS_FIFO_OVERFLOW_MASK_MASK 0x10000000L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN3_HS_FIFO_OVERFLOW_MASK_MASK 0x20000000L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__DLN0_LP_FIFO_OVERFLOW_MASK_MASK 0x40000000L
+#define DSI1_DISP_DSI_ERROR_INTERRUPT_MASK__INTERLEAVE_OP_CONTENTION_MASK_MASK 0x80000000L
+//DSI1_DISP_DSI_INTERRUPT_CTRL
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_STAT__SHIFT 0x0
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_AK__SHIFT 0x0
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_MASK__SHIFT 0x1
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_STAT__SHIFT 0x4
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_AK__SHIFT 0x4
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_MASK__SHIFT 0x5
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_STAT__SHIFT 0x8
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_AK__SHIFT 0x8
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_MASK__SHIFT 0x9
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_STAT__SHIFT 0xc
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_AK__SHIFT 0xc
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_MASK__SHIFT 0xd
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_STAT__SHIFT 0x10
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_AK__SHIFT 0x10
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_MASK__SHIFT 0x11
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_STAT__SHIFT 0x14
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_AK__SHIFT 0x14
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_MASK__SHIFT 0x15
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_STAT__SHIFT 0x18
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_AK__SHIFT 0x18
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_MASK__SHIFT 0x19
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_STAT_MASK 0x00000001L
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_AK_MASK 0x00000001L
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DMA_DONE_MASK_MASK 0x00000002L
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_STAT_MASK 0x00000010L
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_AK_MASK 0x00000010L
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMD_MODE_DENG_DONE_MASK_MASK 0x00000020L
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_STAT_MASK 0x00000100L
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_AK_MASK 0x00000100L
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_VIDEO_MODE_DONE_MASK_MASK 0x00000200L
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_STAT_MASK 0x00001000L
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_AK_MASK 0x00001000L
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_ERROR_MASK_MASK 0x00002000L
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_STAT_MASK 0x00010000L
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_AK_MASK 0x00010000L
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_SW_BTA_DONE_MASK_MASK 0x00020000L
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_STAT_MASK 0x00100000L
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_AK_MASK 0x00100000L
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CMDFIFO_DONE_MASK_MASK 0x00200000L
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_STAT_MASK 0x01000000L
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_AK_MASK 0x01000000L
+#define DSI1_DISP_DSI_INTERRUPT_CTRL__DSI_CAL_DONE_MASK_MASK 0x02000000L
+//DSI1_DISP_DSI_CLK_CTRL
+#define DSI1_DISP_DSI_CLK_CTRL__DISPCLK_G_ON__SHIFT 0x0
+#define DSI1_DISP_DSI_CLK_CTRL__DISPCLK_R_ON__SHIFT 0x1
+#define DSI1_DISP_DSI_CLK_CTRL__DSICLK_G_ON__SHIFT 0x4
+#define DSI1_DISP_DSI_CLK_CTRL__DSICLK_R_ON__SHIFT 0x5
+#define DSI1_DISP_DSI_CLK_CTRL__DSICLK_TRN_ON__SHIFT 0x6
+#define DSI1_DISP_DSI_CLK_CTRL__BYTECLK_G_ON__SHIFT 0x8
+#define DSI1_DISP_DSI_CLK_CTRL__ESCCLK_G_ON__SHIFT 0x10
+#define DSI1_DISP_DSI_CLK_CTRL__TEST_CLK_SEL__SHIFT 0x18
+#define DSI1_DISP_DSI_CLK_CTRL__DISPCLK_G_ON_MASK 0x00000001L
+#define DSI1_DISP_DSI_CLK_CTRL__DISPCLK_R_ON_MASK 0x00000002L
+#define DSI1_DISP_DSI_CLK_CTRL__DSICLK_G_ON_MASK 0x00000010L
+#define DSI1_DISP_DSI_CLK_CTRL__DSICLK_R_ON_MASK 0x00000020L
+#define DSI1_DISP_DSI_CLK_CTRL__DSICLK_TRN_ON_MASK 0x00000040L
+#define DSI1_DISP_DSI_CLK_CTRL__BYTECLK_G_ON_MASK 0x00000100L
+#define DSI1_DISP_DSI_CLK_CTRL__ESCCLK_G_ON_MASK 0x00010000L
+#define DSI1_DISP_DSI_CLK_CTRL__TEST_CLK_SEL_MASK 0x0F000000L
+//DSI1_DISP_DSI_CLK_STATUS
+#define DSI1_DISP_DSI_CLK_STATUS__DISPCLK_R_ACTIVE__SHIFT 0x0
+#define DSI1_DISP_DSI_CLK_STATUS__DISPCLK_G_ACTIVE__SHIFT 0x1
+#define DSI1_DISP_DSI_CLK_STATUS__DSICLK_R_ACTIVE__SHIFT 0x4
+#define DSI1_DISP_DSI_CLK_STATUS__DSICLK_G_ACTIVE__SHIFT 0x5
+#define DSI1_DISP_DSI_CLK_STATUS__DSICLK_TRN_ACTIVE__SHIFT 0x6
+#define DSI1_DISP_DSI_CLK_STATUS__BYTECLK_G_ACTIVE__SHIFT 0x8
+#define DSI1_DISP_DSI_CLK_STATUS__ESCCLK_G_ACTIVE__SHIFT 0x10
+#define DSI1_DISP_DSI_CLK_STATUS__DISPCLK_R_ACTIVE_MASK 0x00000001L
+#define DSI1_DISP_DSI_CLK_STATUS__DISPCLK_G_ACTIVE_MASK 0x00000002L
+#define DSI1_DISP_DSI_CLK_STATUS__DSICLK_R_ACTIVE_MASK 0x00000010L
+#define DSI1_DISP_DSI_CLK_STATUS__DSICLK_G_ACTIVE_MASK 0x00000020L
+#define DSI1_DISP_DSI_CLK_STATUS__DSICLK_TRN_ACTIVE_MASK 0x00000040L
+#define DSI1_DISP_DSI_CLK_STATUS__BYTECLK_G_ACTIVE_MASK 0x00000100L
+#define DSI1_DISP_DSI_CLK_STATUS__ESCCLK_G_ACTIVE_MASK 0x00010000L
+//DSI1_DISP_DSI_DENG_FIFO_STATUS
+#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_LEVEL_ERROR__SHIFT 0x0
+#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_ERROR_ACK__SHIFT 0x9
+#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MAXIMUM_LEVEL__SHIFT 0x11
+#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MINIMUM_LEVEL__SHIFT 0x17
+#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CALIBRATED__SHIFT 0x1d
+#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_OVERWRITE_LEVEL_MASK 0x000001FCL
+#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_ERROR_ACK_MASK 0x00000200L
+#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0001FC00L
+#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MAXIMUM_LEVEL_MASK 0x007E0000L
+#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_MINIMUM_LEVEL_MASK 0x0F800000L
+#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_CALIBRATED_MASK 0x20000000L
+#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+#define DSI1_DISP_DSI_DENG_FIFO_STATUS__DENG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+//DSI1_DISP_DSI_DENG_FIFO_CTRL
+#define DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_EN__SHIFT 0x0
+#define DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_START__SHIFT 0x4
+#define DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_DSICLK_ON__SHIFT 0x8
+#define DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_EN_MASK 0x00000001L
+#define DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_FIFO_START_MASK 0x00000010L
+#define DSI1_DISP_DSI_DENG_FIFO_CTRL__DENG_DSICLK_ON_MASK 0x00000100L
+//DSI1_DISP_DSI_CMD_FIFO_DATA
+#define DSI1_DISP_DSI_CMD_FIFO_DATA__CMDFIFO_DATA__SHIFT 0x0
+#define DSI1_DISP_DSI_CMD_FIFO_DATA__CMDFIFO_DATA_MASK 0xFFFFFFFFL
+//DSI1_DISP_DSI_CMD_FIFO_CTRL
+#define DSI1_DISP_DSI_CMD_FIFO_CTRL__USE_CMDFIFO__SHIFT 0x0
+#define DSI1_DISP_DSI_CMD_FIFO_CTRL__CMDFIFO_DW_LEVEL__SHIFT 0x4
+#define DSI1_DISP_DSI_CMD_FIFO_CTRL__USE_CMDFIFO_MASK 0x00000001L
+#define DSI1_DISP_DSI_CMD_FIFO_CTRL__CMDFIFO_DW_LEVEL_MASK 0x000007F0L
+//DSI1_DISP_DSI_TE_CTRL
+#define DSI1_DISP_DSI_TE_CTRL__FREEZE_CRTC_HYSTERESIS__SHIFT 0x0
+#define DSI1_DISP_DSI_TE_CTRL__DISABLE_CRTC_FREEZE__SHIFT 0x10
+#define DSI1_DISP_DSI_TE_CTRL__DISABLE_CRTC_FORCE__SHIFT 0x14
+#define DSI1_DISP_DSI_TE_CTRL__CRTC_FREEZE__SHIFT 0x18
+#define DSI1_DISP_DSI_TE_CTRL__CRTC_FREEZE_TRIG__SHIFT 0x18
+#define DSI1_DISP_DSI_TE_CTRL__FREEZE_CRTC_HYSTERESIS_MASK 0x00000FFFL
+#define DSI1_DISP_DSI_TE_CTRL__DISABLE_CRTC_FREEZE_MASK 0x00010000L
+#define DSI1_DISP_DSI_TE_CTRL__DISABLE_CRTC_FORCE_MASK 0x00100000L
+#define DSI1_DISP_DSI_TE_CTRL__CRTC_FREEZE_MASK 0x01000000L
+#define DSI1_DISP_DSI_TE_CTRL__CRTC_FREEZE_TRIG_MASK 0x01000000L
+//DSI1_DISP_DSI_LANE_STATUS
+#define DSI1_DISP_DSI_LANE_STATUS__DLN0_STOPSTATE__SHIFT 0x0
+#define DSI1_DISP_DSI_LANE_STATUS__DLN1_STOPSTATE__SHIFT 0x1
+#define DSI1_DISP_DSI_LANE_STATUS__DLN2_STOPSTATE__SHIFT 0x2
+#define DSI1_DISP_DSI_LANE_STATUS__DLN3_STOPSTATE__SHIFT 0x3
+#define DSI1_DISP_DSI_LANE_STATUS__DLN0_ULPS_ACTIVE_NOT__SHIFT 0x4
+#define DSI1_DISP_DSI_LANE_STATUS__DLN1_ULPS_ACTIVE_NOT__SHIFT 0x5
+#define DSI1_DISP_DSI_LANE_STATUS__DLN2_ULPS_ACTIVE_NOT__SHIFT 0x6
+#define DSI1_DISP_DSI_LANE_STATUS__DLN3_ULPS_ACTIVE_NOT__SHIFT 0x7
+#define DSI1_DISP_DSI_LANE_STATUS__DLN0_DIRECTION__SHIFT 0x8
+#define DSI1_DISP_DSI_LANE_STATUS__CLKLN_STOPSTATE__SHIFT 0x18
+#define DSI1_DISP_DSI_LANE_STATUS__CLKLN_ULPS_ACTIVE_NOT__SHIFT 0x1c
+#define DSI1_DISP_DSI_LANE_STATUS__DLN0_STOPSTATE_MASK 0x00000001L
+#define DSI1_DISP_DSI_LANE_STATUS__DLN1_STOPSTATE_MASK 0x00000002L
+#define DSI1_DISP_DSI_LANE_STATUS__DLN2_STOPSTATE_MASK 0x00000004L
+#define DSI1_DISP_DSI_LANE_STATUS__DLN3_STOPSTATE_MASK 0x00000008L
+#define DSI1_DISP_DSI_LANE_STATUS__DLN0_ULPS_ACTIVE_NOT_MASK 0x00000010L
+#define DSI1_DISP_DSI_LANE_STATUS__DLN1_ULPS_ACTIVE_NOT_MASK 0x00000020L
+#define DSI1_DISP_DSI_LANE_STATUS__DLN2_ULPS_ACTIVE_NOT_MASK 0x00000040L
+#define DSI1_DISP_DSI_LANE_STATUS__DLN3_ULPS_ACTIVE_NOT_MASK 0x00000080L
+#define DSI1_DISP_DSI_LANE_STATUS__DLN0_DIRECTION_MASK 0x00000100L
+#define DSI1_DISP_DSI_LANE_STATUS__CLKLN_STOPSTATE_MASK 0x01000000L
+#define DSI1_DISP_DSI_LANE_STATUS__CLKLN_ULPS_ACTIVE_NOT_MASK 0x10000000L
+//DSI1_DISP_DSI_PERF_CTRL
+#define DSI1_DISP_DSI_PERF_CTRL__PERF_LP_HS_LATENCY_SEL__SHIFT 0x0
+#define DSI1_DISP_DSI_PERF_CTRL__PERF_HS_LP_LATENCY_SEL__SHIFT 0x4
+#define DSI1_DISP_DSI_PERF_CTRL__PERF_LP_HS_LATENCY_SEL_MASK 0x00000003L
+#define DSI1_DISP_DSI_PERF_CTRL__PERF_HS_LP_LATENCY_SEL_MASK 0x00000030L
+//DSI1_DISP_DSI_HSYNC_LENGTH
+#define DSI1_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MAX__SHIFT 0x0
+#define DSI1_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MIN__SHIFT 0x10
+#define DSI1_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MAX_MASK 0x0000FFFFL
+#define DSI1_DISP_DSI_HSYNC_LENGTH__HSYNC_LENGTH_MIN_MASK 0xFFFF0000L
+//DSI1_DISP_DSI_RDBK_NUM
+#define DSI1_DISP_DSI_RDBK_NUM__RD_NUM__SHIFT 0x0
+#define DSI1_DISP_DSI_RDBK_NUM__ALL_NUM__SHIFT 0x10
+#define DSI1_DISP_DSI_RDBK_NUM__RD_NUM_MASK 0x0000FFFFL
+#define DSI1_DISP_DSI_RDBK_NUM__ALL_NUM_MASK 0xFFFF0000L
+//DSI1_DISP_DSI_CMD_MEM_PWR_CTRL
+#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_DIS__SHIFT 0x0
+#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_FORCE__SHIFT 0x4
+#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_STATE__SHIFT 0x8
+#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_MODE_SEL__SHIFT 0xc
+#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_DIS_MASK 0x00000001L
+#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_FORCE_MASK 0x00000030L
+#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_STATE_MASK 0x00000300L
+#define DSI1_DISP_DSI_CMD_MEM_PWR_CTRL__CMD_MEM_PWR_MODE_SEL_MASK 0x00003000L
+
+
+// addressBlock: dce_dc_dprx_sd0_dispdec
+//DPRX_SD0_DPRX_SD_CONTROL
+#define DPRX_SD0_DPRX_SD_CONTROL__SD_ENABLE__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_CONTROL__SD_RESET__SHIFT 0x4
+#define DPRX_SD0_DPRX_SD_CONTROL__SD_CLOCK_ENABLE__SHIFT 0x8
+#define DPRX_SD0_DPRX_SD_CONTROL__SD_CLOCK_ON__SHIFT 0xc
+#define DPRX_SD0_DPRX_SD_CONTROL__SD_ENABLE_MASK 0x00000001L
+#define DPRX_SD0_DPRX_SD_CONTROL__SD_RESET_MASK 0x00000010L
+#define DPRX_SD0_DPRX_SD_CONTROL__SD_CLOCK_ENABLE_MASK 0x00000100L
+#define DPRX_SD0_DPRX_SD_CONTROL__SD_CLOCK_ON_MASK 0x00001000L
+//DPRX_SD0_DPRX_SD_STREAM_ENABLE
+#define DPRX_SD0_DPRX_SD_STREAM_ENABLE__VID_STREAM_ENABLE__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_STREAM_ENABLE__VID_STREAM_STATUS__SHIFT 0x8
+#define DPRX_SD0_DPRX_SD_STREAM_ENABLE__VID_STREAM_ENABLE_MASK 0x00000001L
+#define DPRX_SD0_DPRX_SD_STREAM_ENABLE__VID_STREAM_STATUS_MASK 0x00000100L
+//DPRX_SD0_DPRX_SD_MSA0
+#define DPRX_SD0_DPRX_SD_MSA0__MSA0__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_MSA0__MSA0_MASK 0xFFFFFFFFL
+//DPRX_SD0_DPRX_SD_MSA1
+#define DPRX_SD0_DPRX_SD_MSA1__MSA1__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_MSA1__MSA1_MASK 0xFFFFFFFFL
+//DPRX_SD0_DPRX_SD_MSA2
+#define DPRX_SD0_DPRX_SD_MSA2__MSA2__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_MSA2__MSA2_MASK 0xFFFFFFFFL
+//DPRX_SD0_DPRX_SD_MSA3
+#define DPRX_SD0_DPRX_SD_MSA3__MSA3__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_MSA3__MSA3_MASK 0xFFFFFFFFL
+//DPRX_SD0_DPRX_SD_MSA4
+#define DPRX_SD0_DPRX_SD_MSA4__MSA4__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_MSA4__MSA4_MASK 0xFFFFFFFFL
+//DPRX_SD0_DPRX_SD_MSA5
+#define DPRX_SD0_DPRX_SD_MSA5__MSA5__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_MSA5__MSA5_MASK 0xFFFFFFFFL
+//DPRX_SD0_DPRX_SD_MSA6
+#define DPRX_SD0_DPRX_SD_MSA6__MSA6__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_MSA6__MSA6_MASK 0xFFFFFFFFL
+//DPRX_SD0_DPRX_SD_MSA7
+#define DPRX_SD0_DPRX_SD_MSA7__MSA7__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_MSA7__MSA7_MASK 0xFFFFFFFFL
+//DPRX_SD0_DPRX_SD_MSA8
+#define DPRX_SD0_DPRX_SD_MSA8__MSA8__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_MSA8__MSA8_MASK 0xFFFFFFFFL
+//DPRX_SD0_DPRX_SD_VBID
+#define DPRX_SD0_DPRX_SD_VBID__VBID__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_VBID__VBID_MASK 0x000000FFL
+//DPRX_SD0_DPRX_SD_CURRENT_LINE
+#define DPRX_SD0_DPRX_SD_CURRENT_LINE__CURRENT_LINE__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_CURRENT_LINE__CURRENT_FRAME__SHIFT 0x10
+#define DPRX_SD0_DPRX_SD_CURRENT_LINE__CURRENT_LINE_MASK 0x0000FFFFL
+#define DPRX_SD0_DPRX_SD_CURRENT_LINE__CURRENT_FRAME_MASK 0x00FF0000L
+//DPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT
+#define DPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT__DISPLAY_TIMER_SNAPSHOT__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT__DISPLAY_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//DPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE
+#define DPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_MODE__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_UPDATE_LOCKED__SHIFT 0x8
+#define DPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_MODE_MASK 0x00000001L
+#define DPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_UPDATE_LOCKED_MASK 0x00000100L
+//DPRX_SD0_DPRX_SD_MSE_SAT
+#define DPRX_SD0_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_START__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_END__SHIFT 0x8
+#define DPRX_SD0_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_START_MASK 0x0000003FL
+#define DPRX_SD0_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_END_MASK 0x00003F00L
+//DPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE
+#define DPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE__MSE_SAT_FORCE_UPDATE__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE__MSE_SAT_FORCE_UPDATE_MASK 0x00000001L
+//DPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE
+#define DPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_START_ACTIVE__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_END_ACTIVE__SHIFT 0x8
+#define DPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_START_ACTIVE_MASK 0x0000003FL
+#define DPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_END_ACTIVE_MASK 0x00003F00L
+//DPRX_SD0_DPRX_SD_V_PARAMETER
+#define DPRX_SD0_DPRX_SD_V_PARAMETER__V_BLANK_HEIGHT__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_V_PARAMETER__V_BLANK_HEIGHT_MASK 0x0000FFFFL
+//DPRX_SD0_DPRX_SD_PIXEL_FORMAT
+#define DPRX_SD0_DPRX_SD_PIXEL_FORMAT__PIXEL_ENCODING__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_PIXEL_FORMAT__COMPONENT_DEPTH__SHIFT 0x8
+#define DPRX_SD0_DPRX_SD_PIXEL_FORMAT__PIXEL_ENCODING_MASK 0x00000003L
+#define DPRX_SD0_DPRX_SD_PIXEL_FORMAT__COMPONENT_DEPTH_MASK 0x00000700L
+//DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS
+#define DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_FLAG__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_ACK__SHIFT 0x4
+#define DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_MASK__SHIFT 0x8
+#define DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_FLAG_MASK 0x00000001L
+#define DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_ACK_MASK 0x00000010L
+#define DPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_MASK_MASK 0x00000100L
+//DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED
+#define DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_FLAG__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_ACK__SHIFT 0x4
+#define DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_MASK__SHIFT 0x8
+#define DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_FLAG_MASK 0x00000001L
+#define DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_ACK_MASK 0x00000010L
+#define DPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_MASK_MASK 0x00000100L
+//DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS
+#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_FLAG__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_ACK__SHIFT 0x4
+#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_MASK__SHIFT 0x8
+#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_TYPE__SHIFT 0xc
+#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_FLAG_MASK 0x00000001L
+#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_ACK_MASK 0x00000010L
+#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_MASK_MASK 0x00000100L
+#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_TYPE_MASK 0x00001000L
+//DPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL
+#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL__LINE_NUMBER0_INTERRUPT__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL__LINE_NUMBER0_INTERRUPT_MASK 0x0000FFFFL
+//DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS
+#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_FLAG__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_ACK__SHIFT 0x4
+#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_MASK__SHIFT 0x8
+#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_TYPE__SHIFT 0xc
+#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_FLAG_MASK 0x00000001L
+#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_ACK_MASK 0x00000010L
+#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_MASK_MASK 0x00000100L
+#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_TYPE_MASK 0x00001000L
+//DPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL
+#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL__LINE_NUMBER1_INTERRUPT__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL__LINE_NUMBER1_INTERRUPT_MASK 0x0000FFFFL
+//DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BS1_ERROR__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__VBID_ERROR__SHIFT 0x1
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__MVID_ERROR__SHIFT 0x2
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__MAUD_ERROR__SHIFT 0x3
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__IDLE_ERROR__SHIFT 0x4
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_BS_ERROR__SHIFT 0x5
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_OTHER_ERROR__SHIFT 0x6
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__PIX_ERROR__SHIFT 0x7
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_BS_ERROR__SHIFT 0x8
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_OTHER_ERROR__SHIFT 0x9
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_BS_ERROR__SHIFT 0xa
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_OTHER_ERROR__SHIFT 0xb
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_BS_ERROR__SHIFT 0xc
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_OTHER_ERROR__SHIFT 0xd
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILTER_BE_ERROR__SHIFT 0xe
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BS1_ERROR_MASK 0x00000001L
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__VBID_ERROR_MASK 0x00000002L
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__MVID_ERROR_MASK 0x00000004L
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__MAUD_ERROR_MASK 0x00000008L
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__IDLE_ERROR_MASK 0x00000010L
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_BS_ERROR_MASK 0x00000020L
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_OTHER_ERROR_MASK 0x00000040L
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__PIX_ERROR_MASK 0x00000080L
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_BS_ERROR_MASK 0x00000100L
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_OTHER_ERROR_MASK 0x00000200L
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_BS_ERROR_MASK 0x00000400L
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_OTHER_ERROR_MASK 0x00000800L
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_BS_ERROR_MASK 0x00001000L
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_OTHER_ERROR_MASK 0x00002000L
+#define DPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR__FILTER_BE_ERROR_MASK 0x00004000L
+//DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE
+#define DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_1_ERROR__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_2_ERROR__SHIFT 0x1
+#define DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_FAIL__SHIFT 0x2
+#define DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_1_ERROR_MASK 0x00000001L
+#define DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_2_ERROR_MASK 0x00000002L
+#define DPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_FAIL_MASK 0x00000004L
+//DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_MSA_SS0_ERROR__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_SS1_ERROR__SHIFT 0x1
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_DATA_ERROR__SHIFT 0x2
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_EXPIRE_ERROR__SHIFT 0x4
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_SE_ILLEGAL_SE_ERROR__SHIFT 0x5
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_ERROR__SHIFT 0x6
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS1_ERROR__SHIFT 0x8
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS2_ERROR__SHIFT 0x9
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_DATA_ERROR__SHIFT 0xa
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_EXPIRE_ERROR__SHIFT 0xb
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ILLEGAL_SE_ERROR__SHIFT 0xc
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ERROR__SHIFT 0xd
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_MSA_SS0_ERROR_MASK 0x00000001L
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_SS1_ERROR_MASK 0x00000002L
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_DATA_ERROR_MASK 0x00000004L
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_EXPIRE_ERROR_MASK 0x00000010L
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_SE_ILLEGAL_SE_ERROR_MASK 0x00000020L
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_ERROR_MASK 0x00000040L
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS1_ERROR_MASK 0x00000100L
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS2_ERROR_MASK 0x00000200L
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_DATA_ERROR_MASK 0x00000400L
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_EXPIRE_ERROR_MASK 0x00000800L
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ILLEGAL_SE_ERROR_MASK 0x00001000L
+#define DPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ERROR_MASK 0x00002000L
+//DPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED
+#define DPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED__VCPF_PHASE_LOCKED__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED__VCPF_PHASE_LOCKED_MASK 0x00000001L
+//DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR
+#define DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_PHASE_ERROR__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_1_SYMBOL_ERROR__SHIFT 0x1
+#define DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_2_SYMBOL_ERROR__SHIFT 0x2
+#define DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_PHASE_ERROR_MASK 0x00000001L
+#define DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_1_SYMBOL_ERROR_MASK 0x00000002L
+#define DPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR__VCPF_2_SYMBOL_ERROR_MASK 0x00000004L
+//DPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR
+#define DPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_CONTROL_SEQUENCE_ERROR__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_DATA_SEQUENCE_ERROR__SHIFT 0x8
+#define DPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_CONTROL_SEQUENCE_ERROR_MASK 0x00000001L
+#define DPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_DATA_SEQUENCE_ERROR_MASK 0x00000100L
+//DPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR
+#define DPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR__PIXEL_FIFO_OVERFLOW_ERROR__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR__PIXEL_FIFO_OVERFLOW_ERROR_MASK 0x00000001L
+//DPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH
+#define DPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH__MAXIMUM_SDP_PAYLOAD_LENGTH__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH__MAXIMUM_SDP_PAYLOAD_LENGTH_MASK 0x000003FFL
+//DPRX_SD0_DPRX_SD_SDP_STEER
+#define DPRX_SD0_DPRX_SD_SDP_STEER__FILTER_AUDIO_TIMESTAMP_SDP_EN__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_SDP_STEER__FILTER_AUDIO_TIMESTAMP_SDP_EN_MASK 0x00000001L
+//DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS
+#define DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_FLAG__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_ACK__SHIFT 0x4
+#define DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_MASK__SHIFT 0x8
+#define DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_FLAG_MASK 0x00000001L
+#define DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_ACK_MASK 0x00000010L
+#define DPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_MASK_MASK 0x00000100L
+//DPRX_SD0_DPRX_SD_SDP_LEVEL
+#define DPRX_SD0_DPRX_SD_SDP_LEVEL__SDP_FIFO_LEVEL__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_SDP_LEVEL__SDP_CURRENT_SLICE__SHIFT 0x8
+#define DPRX_SD0_DPRX_SD_SDP_LEVEL__SDP_FIFO_LEVEL_MASK 0x0000001FL
+#define DPRX_SD0_DPRX_SD_SDP_LEVEL__SDP_CURRENT_SLICE_MASK 0x00000F00L
+//DPRX_SD0_DPRX_SD_SDP_DATA
+#define DPRX_SD0_DPRX_SD_SDP_DATA__SDP_DATA__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_SDP_DATA__SDP_DATA_MASK 0xFFFFFFFFL
+//DPRX_SD0_DPRX_SD_SDP_ERROR
+#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_FIFO_OVERFLOW_ERROR__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_HEADER_ERROR__SHIFT 0x1
+#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_PAYLOAD_ERROR__SHIFT 0x2
+#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_LENGTH_ERROR__SHIFT 0x3
+#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_RS_CORRECTED_ERROR__SHIFT 0x4
+#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_RS_UNCORRECTABLE_ERROR__SHIFT 0x5
+#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_AUDIO_PAYLOAD_ERROR__SHIFT 0x6
+#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_FIFO_OVERFLOW_ERROR_MASK 0x00000001L
+#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_HEADER_ERROR_MASK 0x00000002L
+#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_PAYLOAD_ERROR_MASK 0x00000004L
+#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_LENGTH_ERROR_MASK 0x00000008L
+#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_RS_CORRECTED_ERROR_MASK 0x00000010L
+#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_RS_UNCORRECTABLE_ERROR_MASK 0x00000020L
+#define DPRX_SD0_DPRX_SD_SDP_ERROR__SDP_AUDIO_PAYLOAD_ERROR_MASK 0x00000040L
+//DPRX_SD0_DPRX_SD_AUDIO_HEADER
+#define DPRX_SD0_DPRX_SD_AUDIO_HEADER__AUDIO_HEADER__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_AUDIO_HEADER__AUDIO_HEADER_MASK 0xFFFFFFFFL
+//DPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR
+#define DPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR__AUDIO_FIFO_OVERFLOW_ERROR__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR__AUDIO_FIFO_OVERFLOW_ERROR_MASK 0x00000001L
+//DPRX_SD0_DPRX_SD_SDP_CONTROL
+#define DPRX_SD0_DPRX_SD_SDP_CONTROL__RS_DECODER_ENABLE__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_SDP_CONTROL__RS_ERROR_CORRECTION_ENABLE__SHIFT 0x4
+#define DPRX_SD0_DPRX_SD_SDP_CONTROL__RS_DECODER_ENABLE_MASK 0x00000001L
+#define DPRX_SD0_DPRX_SD_SDP_CONTROL__RS_ERROR_CORRECTION_ENABLE_MASK 0x00000010L
+//DPRX_SD0_DPRX_SD_V_TOTAL_MEASURED
+#define DPRX_SD0_DPRX_SD_V_TOTAL_MEASURED__V_ACTIVE_LINE_TOTAL__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_V_TOTAL_MEASURED__V_LINE_TOTAL__SHIFT 0x10
+#define DPRX_SD0_DPRX_SD_V_TOTAL_MEASURED__V_ACTIVE_LINE_TOTAL_MASK 0x0000FFFFL
+#define DPRX_SD0_DPRX_SD_V_TOTAL_MEASURED__V_LINE_TOTAL_MASK 0xFFFF0000L
+//DPRX_SD0_DPRX_SD_H_TOTAL_MEASURED
+#define DPRX_SD0_DPRX_SD_H_TOTAL_MEASURED__H_ACTIVE_SYMBOL_TOTAL__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_H_TOTAL_MEASURED__H_ACTIVE_SYMBOL_TOTAL_MASK 0x0000FFFFL
+//DPRX_SD0_DPRX_SD_BS_COUNTER
+#define DPRX_SD0_DPRX_SD_BS_COUNTER__BS_COUNTER__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_BS_COUNTER__BS_COUNTER_MASK 0x000003FFL
+//DPRX_SD0_DPRX_SD_MSE_ACT_HANDLED
+#define DPRX_SD0_DPRX_SD_MSE_ACT_HANDLED__MSE_ACT_HANDLED__SHIFT 0x0
+#define DPRX_SD0_DPRX_SD_MSE_ACT_HANDLED__MSE_ACT_HANDLED_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_dprx_sd1_dispdec
+//DPRX_SD1_DPRX_SD_CONTROL
+#define DPRX_SD1_DPRX_SD_CONTROL__SD_ENABLE__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_CONTROL__SD_RESET__SHIFT 0x4
+#define DPRX_SD1_DPRX_SD_CONTROL__SD_CLOCK_ENABLE__SHIFT 0x8
+#define DPRX_SD1_DPRX_SD_CONTROL__SD_CLOCK_ON__SHIFT 0xc
+#define DPRX_SD1_DPRX_SD_CONTROL__SD_ENABLE_MASK 0x00000001L
+#define DPRX_SD1_DPRX_SD_CONTROL__SD_RESET_MASK 0x00000010L
+#define DPRX_SD1_DPRX_SD_CONTROL__SD_CLOCK_ENABLE_MASK 0x00000100L
+#define DPRX_SD1_DPRX_SD_CONTROL__SD_CLOCK_ON_MASK 0x00001000L
+//DPRX_SD1_DPRX_SD_STREAM_ENABLE
+#define DPRX_SD1_DPRX_SD_STREAM_ENABLE__VID_STREAM_ENABLE__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_STREAM_ENABLE__VID_STREAM_STATUS__SHIFT 0x8
+#define DPRX_SD1_DPRX_SD_STREAM_ENABLE__VID_STREAM_ENABLE_MASK 0x00000001L
+#define DPRX_SD1_DPRX_SD_STREAM_ENABLE__VID_STREAM_STATUS_MASK 0x00000100L
+//DPRX_SD1_DPRX_SD_MSA0
+#define DPRX_SD1_DPRX_SD_MSA0__MSA0__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_MSA0__MSA0_MASK 0xFFFFFFFFL
+//DPRX_SD1_DPRX_SD_MSA1
+#define DPRX_SD1_DPRX_SD_MSA1__MSA1__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_MSA1__MSA1_MASK 0xFFFFFFFFL
+//DPRX_SD1_DPRX_SD_MSA2
+#define DPRX_SD1_DPRX_SD_MSA2__MSA2__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_MSA2__MSA2_MASK 0xFFFFFFFFL
+//DPRX_SD1_DPRX_SD_MSA3
+#define DPRX_SD1_DPRX_SD_MSA3__MSA3__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_MSA3__MSA3_MASK 0xFFFFFFFFL
+//DPRX_SD1_DPRX_SD_MSA4
+#define DPRX_SD1_DPRX_SD_MSA4__MSA4__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_MSA4__MSA4_MASK 0xFFFFFFFFL
+//DPRX_SD1_DPRX_SD_MSA5
+#define DPRX_SD1_DPRX_SD_MSA5__MSA5__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_MSA5__MSA5_MASK 0xFFFFFFFFL
+//DPRX_SD1_DPRX_SD_MSA6
+#define DPRX_SD1_DPRX_SD_MSA6__MSA6__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_MSA6__MSA6_MASK 0xFFFFFFFFL
+//DPRX_SD1_DPRX_SD_MSA7
+#define DPRX_SD1_DPRX_SD_MSA7__MSA7__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_MSA7__MSA7_MASK 0xFFFFFFFFL
+//DPRX_SD1_DPRX_SD_MSA8
+#define DPRX_SD1_DPRX_SD_MSA8__MSA8__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_MSA8__MSA8_MASK 0xFFFFFFFFL
+//DPRX_SD1_DPRX_SD_VBID
+#define DPRX_SD1_DPRX_SD_VBID__VBID__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_VBID__VBID_MASK 0x000000FFL
+//DPRX_SD1_DPRX_SD_CURRENT_LINE
+#define DPRX_SD1_DPRX_SD_CURRENT_LINE__CURRENT_LINE__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_CURRENT_LINE__CURRENT_FRAME__SHIFT 0x10
+#define DPRX_SD1_DPRX_SD_CURRENT_LINE__CURRENT_LINE_MASK 0x0000FFFFL
+#define DPRX_SD1_DPRX_SD_CURRENT_LINE__CURRENT_FRAME_MASK 0x00FF0000L
+//DPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT
+#define DPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT__DISPLAY_TIMER_SNAPSHOT__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT__DISPLAY_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//DPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE
+#define DPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_MODE__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_UPDATE_LOCKED__SHIFT 0x8
+#define DPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_MODE_MASK 0x00000001L
+#define DPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE__DISPLAY_TIMER_UPDATE_LOCKED_MASK 0x00000100L
+//DPRX_SD1_DPRX_SD_MSE_SAT
+#define DPRX_SD1_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_START__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_END__SHIFT 0x8
+#define DPRX_SD1_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_START_MASK 0x0000003FL
+#define DPRX_SD1_DPRX_SD_MSE_SAT__MSE_SAT_SLOT_END_MASK 0x00003F00L
+//DPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE
+#define DPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE__MSE_SAT_FORCE_UPDATE__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE__MSE_SAT_FORCE_UPDATE_MASK 0x00000001L
+//DPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE
+#define DPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_START_ACTIVE__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_END_ACTIVE__SHIFT 0x8
+#define DPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_START_ACTIVE_MASK 0x0000003FL
+#define DPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE__MSE_SAT_SLOT_END_ACTIVE_MASK 0x00003F00L
+//DPRX_SD1_DPRX_SD_V_PARAMETER
+#define DPRX_SD1_DPRX_SD_V_PARAMETER__V_BLANK_HEIGHT__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_V_PARAMETER__V_BLANK_HEIGHT_MASK 0x0000FFFFL
+//DPRX_SD1_DPRX_SD_PIXEL_FORMAT
+#define DPRX_SD1_DPRX_SD_PIXEL_FORMAT__PIXEL_ENCODING__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_PIXEL_FORMAT__COMPONENT_DEPTH__SHIFT 0x8
+#define DPRX_SD1_DPRX_SD_PIXEL_FORMAT__PIXEL_ENCODING_MASK 0x00000003L
+#define DPRX_SD1_DPRX_SD_PIXEL_FORMAT__COMPONENT_DEPTH_MASK 0x00000700L
+//DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS
+#define DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_FLAG__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_ACK__SHIFT 0x4
+#define DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_MASK__SHIFT 0x8
+#define DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_FLAG_MASK 0x00000001L
+#define DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_ACK_MASK 0x00000010L
+#define DPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS__MSA_RECEIVED_MASK_MASK 0x00000100L
+//DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED
+#define DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_FLAG__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_ACK__SHIFT 0x4
+#define DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_MASK__SHIFT 0x8
+#define DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_FLAG_MASK 0x00000001L
+#define DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_ACK_MASK 0x00000010L
+#define DPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED__VBID_VID_STREAM_STATUS_TOGGLED_MASK_MASK 0x00000100L
+//DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS
+#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_FLAG__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_ACK__SHIFT 0x4
+#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_MASK__SHIFT 0x8
+#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_TYPE__SHIFT 0xc
+#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_FLAG_MASK 0x00000001L
+#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_ACK_MASK 0x00000010L
+#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_MASK_MASK 0x00000100L
+#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS__LINE_NUMBER0_TYPE_MASK 0x00001000L
+//DPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL
+#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL__LINE_NUMBER0_INTERRUPT__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL__LINE_NUMBER0_INTERRUPT_MASK 0x0000FFFFL
+//DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS
+#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_FLAG__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_ACK__SHIFT 0x4
+#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_MASK__SHIFT 0x8
+#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_TYPE__SHIFT 0xc
+#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_FLAG_MASK 0x00000001L
+#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_ACK_MASK 0x00000010L
+#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_MASK_MASK 0x00000100L
+#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS__LINE_NUMBER1_TYPE_MASK 0x00001000L
+//DPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL
+#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL__LINE_NUMBER1_INTERRUPT__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL__LINE_NUMBER1_INTERRUPT_MASK 0x0000FFFFL
+//DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BS1_ERROR__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__VBID_ERROR__SHIFT 0x1
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__MVID_ERROR__SHIFT 0x2
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__MAUD_ERROR__SHIFT 0x3
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__IDLE_ERROR__SHIFT 0x4
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_BS_ERROR__SHIFT 0x5
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_OTHER_ERROR__SHIFT 0x6
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__PIX_ERROR__SHIFT 0x7
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_BS_ERROR__SHIFT 0x8
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_OTHER_ERROR__SHIFT 0x9
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_BS_ERROR__SHIFT 0xa
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_OTHER_ERROR__SHIFT 0xb
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_BS_ERROR__SHIFT 0xc
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_OTHER_ERROR__SHIFT 0xd
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILTER_BE_ERROR__SHIFT 0xe
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BS1_ERROR_MASK 0x00000001L
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__VBID_ERROR_MASK 0x00000002L
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__MVID_ERROR_MASK 0x00000004L
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__MAUD_ERROR_MASK 0x00000008L
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__IDLE_ERROR_MASK 0x00000010L
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_BS_ERROR_MASK 0x00000020L
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__BE_OTHER_ERROR_MASK 0x00000040L
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__PIX_ERROR_MASK 0x00000080L
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_BS_ERROR_MASK 0x00000100L
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FS_OTHER_ERROR_MASK 0x00000200L
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_BS_ERROR_MASK 0x00000400L
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILL_OTHER_ERROR_MASK 0x00000800L
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_BS_ERROR_MASK 0x00001000L
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FE_OTHER_ERROR_MASK 0x00002000L
+#define DPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR__FILTER_BE_ERROR_MASK 0x00004000L
+//DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE
+#define DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_1_ERROR__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_2_ERROR__SHIFT 0x1
+#define DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_FAIL__SHIFT 0x2
+#define DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_1_ERROR_MASK 0x00000001L
+#define DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_2_ERROR_MASK 0x00000002L
+#define DPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE__VBID_MAJORITY_VOTE_FAIL_MASK 0x00000004L
+//DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_MSA_SS0_ERROR__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_SS1_ERROR__SHIFT 0x1
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_DATA_ERROR__SHIFT 0x2
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_EXPIRE_ERROR__SHIFT 0x4
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_SE_ILLEGAL_SE_ERROR__SHIFT 0x5
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_ERROR__SHIFT 0x6
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS1_ERROR__SHIFT 0x8
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS2_ERROR__SHIFT 0x9
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_DATA_ERROR__SHIFT 0xa
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_EXPIRE_ERROR__SHIFT 0xb
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ILLEGAL_SE_ERROR__SHIFT 0xc
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ERROR__SHIFT 0xd
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_MSA_SS0_ERROR_MASK 0x00000001L
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_SS1_ERROR_MASK 0x00000002L
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_MSA_DATA_ERROR_MASK 0x00000004L
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_EXPIRE_ERROR_MASK 0x00000010L
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_SE_ILLEGAL_SE_ERROR_MASK 0x00000020L
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_SDP_DATA_ERROR_MASK 0x00000040L
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS1_ERROR_MASK 0x00000100L
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SS2_ERROR_MASK 0x00000200L
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_DATA_ERROR_MASK 0x00000400L
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_EXPIRE_ERROR_MASK 0x00000800L
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ILLEGAL_SE_ERROR_MASK 0x00001000L
+#define DPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR__SEC_NESTED_MSA_SE_ERROR_MASK 0x00002000L
+//DPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED
+#define DPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED__VCPF_PHASE_LOCKED__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED__VCPF_PHASE_LOCKED_MASK 0x00000001L
+//DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR
+#define DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_PHASE_ERROR__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_1_SYMBOL_ERROR__SHIFT 0x1
+#define DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_2_SYMBOL_ERROR__SHIFT 0x2
+#define DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_PHASE_ERROR_MASK 0x00000001L
+#define DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_1_SYMBOL_ERROR_MASK 0x00000002L
+#define DPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR__VCPF_2_SYMBOL_ERROR_MASK 0x00000004L
+//DPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR
+#define DPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_CONTROL_SEQUENCE_ERROR__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_DATA_SEQUENCE_ERROR__SHIFT 0x8
+#define DPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_CONTROL_SEQUENCE_ERROR_MASK 0x00000001L
+#define DPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR__CORRECTED_DATA_SEQUENCE_ERROR_MASK 0x00000100L
+//DPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR
+#define DPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR__PIXEL_FIFO_OVERFLOW_ERROR__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR__PIXEL_FIFO_OVERFLOW_ERROR_MASK 0x00000001L
+//DPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH
+#define DPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH__MAXIMUM_SDP_PAYLOAD_LENGTH__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH__MAXIMUM_SDP_PAYLOAD_LENGTH_MASK 0x000003FFL
+//DPRX_SD1_DPRX_SD_SDP_STEER
+#define DPRX_SD1_DPRX_SD_SDP_STEER__FILTER_AUDIO_TIMESTAMP_SDP_EN__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_SDP_STEER__FILTER_AUDIO_TIMESTAMP_SDP_EN_MASK 0x00000001L
+//DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS
+#define DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_FLAG__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_ACK__SHIFT 0x4
+#define DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_MASK__SHIFT 0x8
+#define DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_FLAG_MASK 0x00000001L
+#define DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_ACK_MASK 0x00000010L
+#define DPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS__SDP_RECEIVED_MASK_MASK 0x00000100L
+//DPRX_SD1_DPRX_SD_SDP_LEVEL
+#define DPRX_SD1_DPRX_SD_SDP_LEVEL__SDP_FIFO_LEVEL__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_SDP_LEVEL__SDP_CURRENT_SLICE__SHIFT 0x8
+#define DPRX_SD1_DPRX_SD_SDP_LEVEL__SDP_FIFO_LEVEL_MASK 0x0000001FL
+#define DPRX_SD1_DPRX_SD_SDP_LEVEL__SDP_CURRENT_SLICE_MASK 0x00000F00L
+//DPRX_SD1_DPRX_SD_SDP_DATA
+#define DPRX_SD1_DPRX_SD_SDP_DATA__SDP_DATA__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_SDP_DATA__SDP_DATA_MASK 0xFFFFFFFFL
+//DPRX_SD1_DPRX_SD_SDP_ERROR
+#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_FIFO_OVERFLOW_ERROR__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_HEADER_ERROR__SHIFT 0x1
+#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_PAYLOAD_ERROR__SHIFT 0x2
+#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_LENGTH_ERROR__SHIFT 0x3
+#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_RS_CORRECTED_ERROR__SHIFT 0x4
+#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_RS_UNCORRECTABLE_ERROR__SHIFT 0x5
+#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_AUDIO_PAYLOAD_ERROR__SHIFT 0x6
+#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_FIFO_OVERFLOW_ERROR_MASK 0x00000001L
+#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_HEADER_ERROR_MASK 0x00000002L
+#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_PAYLOAD_ERROR_MASK 0x00000004L
+#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_NON_AUDIO_LENGTH_ERROR_MASK 0x00000008L
+#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_RS_CORRECTED_ERROR_MASK 0x00000010L
+#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_RS_UNCORRECTABLE_ERROR_MASK 0x00000020L
+#define DPRX_SD1_DPRX_SD_SDP_ERROR__SDP_AUDIO_PAYLOAD_ERROR_MASK 0x00000040L
+//DPRX_SD1_DPRX_SD_AUDIO_HEADER
+#define DPRX_SD1_DPRX_SD_AUDIO_HEADER__AUDIO_HEADER__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_AUDIO_HEADER__AUDIO_HEADER_MASK 0xFFFFFFFFL
+//DPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR
+#define DPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR__AUDIO_FIFO_OVERFLOW_ERROR__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR__AUDIO_FIFO_OVERFLOW_ERROR_MASK 0x00000001L
+//DPRX_SD1_DPRX_SD_SDP_CONTROL
+#define DPRX_SD1_DPRX_SD_SDP_CONTROL__RS_DECODER_ENABLE__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_SDP_CONTROL__RS_ERROR_CORRECTION_ENABLE__SHIFT 0x4
+#define DPRX_SD1_DPRX_SD_SDP_CONTROL__RS_DECODER_ENABLE_MASK 0x00000001L
+#define DPRX_SD1_DPRX_SD_SDP_CONTROL__RS_ERROR_CORRECTION_ENABLE_MASK 0x00000010L
+//DPRX_SD1_DPRX_SD_V_TOTAL_MEASURED
+#define DPRX_SD1_DPRX_SD_V_TOTAL_MEASURED__V_ACTIVE_LINE_TOTAL__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_V_TOTAL_MEASURED__V_LINE_TOTAL__SHIFT 0x10
+#define DPRX_SD1_DPRX_SD_V_TOTAL_MEASURED__V_ACTIVE_LINE_TOTAL_MASK 0x0000FFFFL
+#define DPRX_SD1_DPRX_SD_V_TOTAL_MEASURED__V_LINE_TOTAL_MASK 0xFFFF0000L
+//DPRX_SD1_DPRX_SD_H_TOTAL_MEASURED
+#define DPRX_SD1_DPRX_SD_H_TOTAL_MEASURED__H_ACTIVE_SYMBOL_TOTAL__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_H_TOTAL_MEASURED__H_ACTIVE_SYMBOL_TOTAL_MASK 0x0000FFFFL
+//DPRX_SD1_DPRX_SD_BS_COUNTER
+#define DPRX_SD1_DPRX_SD_BS_COUNTER__BS_COUNTER__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_BS_COUNTER__BS_COUNTER_MASK 0x000003FFL
+//DPRX_SD1_DPRX_SD_MSE_ACT_HANDLED
+#define DPRX_SD1_DPRX_SD_MSE_ACT_HANDLED__MSE_ACT_HANDLED__SHIFT 0x0
+#define DPRX_SD1_DPRX_SD_MSE_ACT_HANDLED__MSE_ACT_HANDLED_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_dc_perfmon10_dispdec
+//DC_PERFMON10_PERFCOUNTER_CNTL
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x11
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1b
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x003E0000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x08000000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON10_PERFCOUNTER_CNTL2
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON10_PERFCOUNTER_STATE
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON10_PERFMON_CNTL
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON10_PERFMON_CNTL2
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON10_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON10_PERFMON_CVALUE_LOW
+#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON10_PERFMON_HI
+#define DC_PERFMON10_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON10_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON10_PERFMON_LOW
+#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dc_zcalregs_dispdec
+//COMP_EN_CTL
+#define COMP_EN_CTL__comp_en__SHIFT 0x0
+#define COMP_EN_CTL__comp_en_override__SHIFT 0x2
+#define COMP_EN_CTL__comp_done__SHIFT 0x4
+#define COMP_EN_CTL__zcal_code_override__SHIFT 0x6
+#define COMP_EN_CTL__zcal_cal_rtt__SHIFT 0x7
+#define COMP_EN_CTL__zcal_base_en__SHIFT 0x8
+#define COMP_EN_CTL__zcal_ht_rtt_sel__SHIFT 0x9
+#define COMP_EN_CTL__zcal_code__SHIFT 0xa
+#define COMP_EN_CTL__zcal_ron_cal_mode__SHIFT 0x10
+#define COMP_EN_CTL__zcal_ana_dbg_sel__SHIFT 0x11
+#define COMP_EN_CTL__cfg_cml_cmos_sel__SHIFT 0x13
+#define COMP_EN_CTL__dsm_sel__SHIFT 0x14
+#define COMP_EN_CTL__comp_en_MASK 0x00000001L
+#define COMP_EN_CTL__comp_en_override_MASK 0x00000004L
+#define COMP_EN_CTL__comp_done_MASK 0x00000010L
+#define COMP_EN_CTL__zcal_code_override_MASK 0x00000040L
+#define COMP_EN_CTL__zcal_cal_rtt_MASK 0x00000080L
+#define COMP_EN_CTL__zcal_base_en_MASK 0x00000100L
+#define COMP_EN_CTL__zcal_ht_rtt_sel_MASK 0x00000200L
+#define COMP_EN_CTL__zcal_code_MASK 0x00007C00L
+#define COMP_EN_CTL__zcal_ron_cal_mode_MASK 0x00010000L
+#define COMP_EN_CTL__zcal_ana_dbg_sel_MASK 0x00060000L
+#define COMP_EN_CTL__cfg_cml_cmos_sel_MASK 0x00080000L
+#define COMP_EN_CTL__dsm_sel_MASK 0x00F00000L
+//COMP_EN_DFX
+#define COMP_EN_DFX__autocal_ron_code__SHIFT 0x0
+#define COMP_EN_DFX__autocal_rtt_code__SHIFT 0x5
+#define COMP_EN_DFX__pre_fused_ron_code__SHIFT 0xb
+#define COMP_EN_DFX__pre_fused_rtt_code__SHIFT 0x10
+#define COMP_EN_DFX__broadcast_ron_code__SHIFT 0x16
+#define COMP_EN_DFX__broadcast_rtt_code__SHIFT 0x1b
+#define COMP_EN_DFX__autocal_ron_code_MASK 0x0000001FL
+#define COMP_EN_DFX__autocal_rtt_code_MASK 0x000003E0L
+#define COMP_EN_DFX__pre_fused_ron_code_MASK 0x0000F800L
+#define COMP_EN_DFX__pre_fused_rtt_code_MASK 0x001F0000L
+#define COMP_EN_DFX__broadcast_ron_code_MASK 0x07C00000L
+#define COMP_EN_DFX__broadcast_rtt_code_MASK 0xF8000000L
+//ZCAL_FUSES
+#define ZCAL_FUSES__fuse_valid__SHIFT 0x0
+#define ZCAL_FUSES__fuse_ron_override_val__SHIFT 0x3
+#define ZCAL_FUSES__fuse_ron_ctl__SHIFT 0xa
+#define ZCAL_FUSES__fuse_rtt_override_val__SHIFT 0xd
+#define ZCAL_FUSES__fuse_rtt_ctl__SHIFT 0x14
+#define ZCAL_FUSES__fuse_refresh_cal_en__SHIFT 0x16
+#define ZCAL_FUSES__fuse_spare__SHIFT 0x17
+#define ZCAL_FUSES__fuse_valid_MASK 0x00000001L
+#define ZCAL_FUSES__fuse_ron_override_val_MASK 0x000001F8L
+#define ZCAL_FUSES__fuse_ron_ctl_MASK 0x00000C00L
+#define ZCAL_FUSES__fuse_rtt_override_val_MASK 0x0007E000L
+#define ZCAL_FUSES__fuse_rtt_ctl_MASK 0x00300000L
+#define ZCAL_FUSES__fuse_refresh_cal_en_MASK 0x00400000L
+#define ZCAL_FUSES__fuse_spare_MASK 0xFF800000L
+
+
+// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
+
+
+// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
+
+
+// addressBlock: dce_dc_dispdec[948..986]
+
+
+// addressBlock: dce_dc_azdec
+//CORB_WRITE_POINTER
+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0
+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL
+//CORB_READ_POINTER
+#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0
+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf
+#define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL
+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L
+//CORB_CONTROL
+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0
+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1
+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L
+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L
+//CORB_STATUS
+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0
+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x01L
+//CORB_SIZE
+#define CORB_SIZE__CORB_SIZE__SHIFT 0x0
+#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4
+#define CORB_SIZE__CORB_SIZE_MASK 0x0003L
+#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0x00F0L
+//RIRB_LOWER_BASE_ADDRESS
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+//RIRB_UPPER_BASE_ADDRESS
+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//RIRB_WRITE_POINTER
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0x00FFL
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000L
+//RESPONSE_INTERRUPT_COUNT
+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0
+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0x00FFL
+//RIRB_CONTROL
+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0
+#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1
+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2
+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x01L
+#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x02L
+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x04L
+//RIRB_STATUS
+#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0
+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2
+#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x01L
+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x04L
+//RIRB_SIZE
+#define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0
+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4
+#define RIRB_SIZE__RIRB_SIZE_MASK 0x0003L
+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0x00F0L
+//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL
+//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL
+//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL
+//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL
+//AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL
+//AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL
+//IMMEDIATE_COMMAND_OUTPUT_INTERFACE
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0x0FFFFFFFL
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xF0000000L
+//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL
+//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0000FFFFL
+//IMMEDIATE_RESPONSE_INPUT_INTERFACE
+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0
+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xFFFFFFFFL
+//IMMEDIATE_COMMAND_STATUS
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x00000001L
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x00000002L
+//DMA_POSITION_LOWER_BASE_ADDRESS
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x00000001L
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007EL
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+//DMA_POSITION_UPPER_BASE_ADDRESS
+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//WALL_CLOCK_COUNTER_ALIAS
+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0
+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azstream0_azdec
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azstream1_azdec
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azstream2_azdec
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azstream3_azdec
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azstream4_azdec
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azstream5_azdec
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azstream6_azdec
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_azstream7_azdec
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream0_streamind
+//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream1_streamind
+//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream2_streamind
+//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream3_streamind
+//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream4_streamind
+//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream5_streamind
+//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream6_streamind
+//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream7_streamind
+//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream8_streamind
+//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream9_streamind
+//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream10_streamind
+//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream11_streamind
+//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream12_streamind
+//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream13_streamind
+//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream14_streamind
+//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream15_streamind
+//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0endpoint0_endpointind
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+
+
+// addressBlock: azf0endpoint1_endpointind
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+
+
+// addressBlock: azf0endpoint2_endpointind
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+
+
+// addressBlock: azf0endpoint3_endpointind
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+
+
+// addressBlock: azf0endpoint4_endpointind
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+
+
+// addressBlock: azf0endpoint5_endpointind
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+
+
+// addressBlock: azf0endpoint6_endpointind
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+
+
+// addressBlock: azf0endpoint7_endpointind
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+
+
+// addressBlock: azf0inputendpoint0_inputendpointind
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+
+
+// addressBlock: azf0inputendpoint1_inputendpointind
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+
+
+// addressBlock: azf0inputendpoint2_inputendpointind
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+
+
+// addressBlock: azf0inputendpoint3_inputendpointind
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+
+
+// addressBlock: azf0inputendpoint4_inputendpointind
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+
+
+// addressBlock: azf0inputendpoint5_inputendpointind
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+
+
+// addressBlock: azf0inputendpoint6_inputendpointind
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+
+
+// addressBlock: azf0inputendpoint7_inputendpointind
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+
+
+// addressBlock: f2codecind
+//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x00008000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x0000007FL
+//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x00000080L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x0000007FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x00000100L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x00000200L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0x0000FC00L
+//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x00000003L
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x00000078L
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x00000080L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x00000007L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x00000078L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+//AZALIA_F2_CODEC_PIN_CONTROL_HBR
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+
+
+// addressBlock: descriptorind
+//AUDIO_DESCRIPTOR0
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR1
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR2
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR3
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR4
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR5
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR6
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR7
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR8
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR9
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR10
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR11
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR12
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR13
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+
+
+// addressBlock: sinkinfoind
+//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0x0000FFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0x0000FFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xFFFFFFFFL
+//SINK_DESCRIPTION0
+#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION1
+#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION2
+#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION3
+#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION4
+#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION5
+#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION6
+#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION7
+#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION8
+#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION9
+#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION10
+#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION11
+#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION12
+#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION13
+#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION14
+#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION15
+#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION16
+#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION17
+#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0x000000FFL
+
+
+// addressBlock: azinputcrc0resultind
+//AZALIA_INPUT_CRC0_CHANNEL0
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL1
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL2
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL3
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL4
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL5
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL6
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL7
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azinputcrc1resultind
+//AZALIA_INPUT_CRC1_CHANNEL0
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL1
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL2
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL3
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL4
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL5
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL6
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL7
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azcrc0resultind
+//AZALIA_CRC0_CHANNEL0
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL1
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL2
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL3
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL4
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL5
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL6
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL7
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azcrc1resultind
+//AZALIA_CRC1_CHANNEL0
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL1
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL2
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL3
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL4
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL5
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL6
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL7
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL
+
+
+// addressBlock: vgaseqind
+//SEQ00
+#define SEQ00__SEQ_RST0B__SHIFT 0x0
+#define SEQ00__SEQ_RST1B__SHIFT 0x1
+#define SEQ00__SEQ_RST0B_MASK 0x01L
+#define SEQ00__SEQ_RST1B_MASK 0x02L
+//SEQ01
+#define SEQ01__SEQ_DOT8__SHIFT 0x0
+#define SEQ01__SEQ_SHIFT2__SHIFT 0x2
+#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3
+#define SEQ01__SEQ_SHIFT4__SHIFT 0x4
+#define SEQ01__SEQ_MAXBW__SHIFT 0x5
+#define SEQ01__SEQ_DOT8_MASK 0x01L
+#define SEQ01__SEQ_SHIFT2_MASK 0x04L
+#define SEQ01__SEQ_PCLKBY2_MASK 0x08L
+#define SEQ01__SEQ_SHIFT4_MASK 0x10L
+#define SEQ01__SEQ_MAXBW_MASK 0x20L
+//SEQ02
+#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0
+#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1
+#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2
+#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3
+#define SEQ02__SEQ_MAP0_EN_MASK 0x01L
+#define SEQ02__SEQ_MAP1_EN_MASK 0x02L
+#define SEQ02__SEQ_MAP2_EN_MASK 0x04L
+#define SEQ02__SEQ_MAP3_EN_MASK 0x08L
+//SEQ03
+#define SEQ03__SEQ_FONT_B1__SHIFT 0x0
+#define SEQ03__SEQ_FONT_B2__SHIFT 0x1
+#define SEQ03__SEQ_FONT_A1__SHIFT 0x2
+#define SEQ03__SEQ_FONT_A2__SHIFT 0x3
+#define SEQ03__SEQ_FONT_B0__SHIFT 0x4
+#define SEQ03__SEQ_FONT_A0__SHIFT 0x5
+#define SEQ03__SEQ_FONT_B1_MASK 0x01L
+#define SEQ03__SEQ_FONT_B2_MASK 0x02L
+#define SEQ03__SEQ_FONT_A1_MASK 0x04L
+#define SEQ03__SEQ_FONT_A2_MASK 0x08L
+#define SEQ03__SEQ_FONT_B0_MASK 0x10L
+#define SEQ03__SEQ_FONT_A0_MASK 0x20L
+//SEQ04
+#define SEQ04__SEQ_256K__SHIFT 0x1
+#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2
+#define SEQ04__SEQ_CHAIN__SHIFT 0x3
+#define SEQ04__SEQ_256K_MASK 0x02L
+#define SEQ04__SEQ_ODDEVEN_MASK 0x04L
+#define SEQ04__SEQ_CHAIN_MASK 0x08L
+
+
+// addressBlock: vgacrtind
+//CRT00
+#define CRT00__H_TOTAL__SHIFT 0x0
+#define CRT00__H_TOTAL_MASK 0xFFL
+//CRT01
+#define CRT01__H_DISP_END__SHIFT 0x0
+#define CRT01__H_DISP_END_MASK 0xFFL
+//CRT02
+#define CRT02__H_BLANK_START__SHIFT 0x0
+#define CRT02__H_BLANK_START_MASK 0xFFL
+//CRT03
+#define CRT03__H_BLANK_END__SHIFT 0x0
+#define CRT03__H_DE_SKEW__SHIFT 0x5
+#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7
+#define CRT03__H_BLANK_END_MASK 0x1FL
+#define CRT03__H_DE_SKEW_MASK 0x60L
+#define CRT03__CR10CR11_R_DIS_B_MASK 0x80L
+//CRT04
+#define CRT04__H_SYNC_START__SHIFT 0x0
+#define CRT04__H_SYNC_START_MASK 0xFFL
+//CRT05
+#define CRT05__H_SYNC_END__SHIFT 0x0
+#define CRT05__H_SYNC_SKEW__SHIFT 0x5
+#define CRT05__H_BLANK_END_B5__SHIFT 0x7
+#define CRT05__H_SYNC_END_MASK 0x1FL
+#define CRT05__H_SYNC_SKEW_MASK 0x60L
+#define CRT05__H_BLANK_END_B5_MASK 0x80L
+//CRT06
+#define CRT06__V_TOTAL__SHIFT 0x0
+#define CRT06__V_TOTAL_MASK 0xFFL
+//CRT07
+#define CRT07__V_TOTAL_B8__SHIFT 0x0
+#define CRT07__V_DISP_END_B8__SHIFT 0x1
+#define CRT07__V_SYNC_START_B8__SHIFT 0x2
+#define CRT07__V_BLANK_START_B8__SHIFT 0x3
+#define CRT07__LINE_CMP_B8__SHIFT 0x4
+#define CRT07__V_TOTAL_B9__SHIFT 0x5
+#define CRT07__V_DISP_END_B9__SHIFT 0x6
+#define CRT07__V_SYNC_START_B9__SHIFT 0x7
+#define CRT07__V_TOTAL_B8_MASK 0x01L
+#define CRT07__V_DISP_END_B8_MASK 0x02L
+#define CRT07__V_SYNC_START_B8_MASK 0x04L
+#define CRT07__V_BLANK_START_B8_MASK 0x08L
+#define CRT07__LINE_CMP_B8_MASK 0x10L
+#define CRT07__V_TOTAL_B9_MASK 0x20L
+#define CRT07__V_DISP_END_B9_MASK 0x40L
+#define CRT07__V_SYNC_START_B9_MASK 0x80L
+//CRT08
+#define CRT08__ROW_SCAN_START__SHIFT 0x0
+#define CRT08__BYTE_PAN__SHIFT 0x5
+#define CRT08__ROW_SCAN_START_MASK 0x1FL
+#define CRT08__BYTE_PAN_MASK 0x60L
+//CRT09
+#define CRT09__MAX_ROW_SCAN__SHIFT 0x0
+#define CRT09__V_BLANK_START_B9__SHIFT 0x5
+#define CRT09__LINE_CMP_B9__SHIFT 0x6
+#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7
+#define CRT09__MAX_ROW_SCAN_MASK 0x1FL
+#define CRT09__V_BLANK_START_B9_MASK 0x20L
+#define CRT09__LINE_CMP_B9_MASK 0x40L
+#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80L
+//CRT0A
+#define CRT0A__CURSOR_START__SHIFT 0x0
+#define CRT0A__CURSOR_DISABLE__SHIFT 0x5
+#define CRT0A__CURSOR_START_MASK 0x1FL
+#define CRT0A__CURSOR_DISABLE_MASK 0x20L
+//CRT0B
+#define CRT0B__CURSOR_END__SHIFT 0x0
+#define CRT0B__CURSOR_SKEW__SHIFT 0x5
+#define CRT0B__CURSOR_END_MASK 0x1FL
+#define CRT0B__CURSOR_SKEW_MASK 0x60L
+//CRT0C
+#define CRT0C__DISP_START__SHIFT 0x0
+#define CRT0C__DISP_START_MASK 0xFFL
+//CRT0D
+#define CRT0D__DISP_START__SHIFT 0x0
+#define CRT0D__DISP_START_MASK 0xFFL
+//CRT0E
+#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0
+#define CRT0E__CURSOR_LOC_HI_MASK 0xFFL
+//CRT0F
+#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0
+#define CRT0F__CURSOR_LOC_LO_MASK 0xFFL
+//CRT10
+#define CRT10__V_SYNC_START__SHIFT 0x0
+#define CRT10__V_SYNC_START_MASK 0xFFL
+//CRT11
+#define CRT11__V_SYNC_END__SHIFT 0x0
+#define CRT11__V_INTR_CLR__SHIFT 0x4
+#define CRT11__V_INTR_EN__SHIFT 0x5
+#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6
+#define CRT11__C0T7_WR_ONLY__SHIFT 0x7
+#define CRT11__V_SYNC_END_MASK 0x0FL
+#define CRT11__V_INTR_CLR_MASK 0x10L
+#define CRT11__V_INTR_EN_MASK 0x20L
+#define CRT11__SEL5_REFRESH_CYC_MASK 0x40L
+#define CRT11__C0T7_WR_ONLY_MASK 0x80L
+//CRT12
+#define CRT12__V_DISP_END__SHIFT 0x0
+#define CRT12__V_DISP_END_MASK 0xFFL
+//CRT13
+#define CRT13__DISP_PITCH__SHIFT 0x0
+#define CRT13__DISP_PITCH_MASK 0xFFL
+//CRT14
+#define CRT14__UNDRLN_LOC__SHIFT 0x0
+#define CRT14__ADDR_CNT_BY4__SHIFT 0x5
+#define CRT14__DOUBLE_WORD__SHIFT 0x6
+#define CRT14__UNDRLN_LOC_MASK 0x1FL
+#define CRT14__ADDR_CNT_BY4_MASK 0x20L
+#define CRT14__DOUBLE_WORD_MASK 0x40L
+//CRT15
+#define CRT15__V_BLANK_START__SHIFT 0x0
+#define CRT15__V_BLANK_START_MASK 0xFFL
+//CRT16
+#define CRT16__V_BLANK_END__SHIFT 0x0
+#define CRT16__V_BLANK_END_MASK 0xFFL
+//CRT17
+#define CRT17__RA0_AS_A13B__SHIFT 0x0
+#define CRT17__RA1_AS_A14B__SHIFT 0x1
+#define CRT17__VCOUNT_BY2__SHIFT 0x2
+#define CRT17__ADDR_CNT_BY2__SHIFT 0x3
+#define CRT17__WRAP_A15TOA0__SHIFT 0x5
+#define CRT17__BYTE_MODE__SHIFT 0x6
+#define CRT17__CRTC_SYNC_EN__SHIFT 0x7
+#define CRT17__RA0_AS_A13B_MASK 0x01L
+#define CRT17__RA1_AS_A14B_MASK 0x02L
+#define CRT17__VCOUNT_BY2_MASK 0x04L
+#define CRT17__ADDR_CNT_BY2_MASK 0x08L
+#define CRT17__WRAP_A15TOA0_MASK 0x20L
+#define CRT17__BYTE_MODE_MASK 0x40L
+#define CRT17__CRTC_SYNC_EN_MASK 0x80L
+//CRT18
+#define CRT18__LINE_CMP__SHIFT 0x0
+#define CRT18__LINE_CMP_MASK 0xFFL
+//CRT1E
+#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1
+#define CRT1E__GRPH_DEC_RD1_MASK 0x02L
+//CRT1F
+#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0
+#define CRT1F__GRPH_DEC_RD0_MASK 0xFFL
+//CRT22
+#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0
+#define CRT22__GRPH_LATCH_DATA_MASK 0xFFL
+
+
+// addressBlock: vgagrphind
+//GRA00
+#define GRA00__GRPH_SET_RESET0__SHIFT 0x0
+#define GRA00__GRPH_SET_RESET1__SHIFT 0x1
+#define GRA00__GRPH_SET_RESET2__SHIFT 0x2
+#define GRA00__GRPH_SET_RESET3__SHIFT 0x3
+#define GRA00__GRPH_SET_RESET0_MASK 0x01L
+#define GRA00__GRPH_SET_RESET1_MASK 0x02L
+#define GRA00__GRPH_SET_RESET2_MASK 0x04L
+#define GRA00__GRPH_SET_RESET3_MASK 0x08L
+//GRA01
+#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0
+#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1
+#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2
+#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3
+#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x01L
+#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x02L
+#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x04L
+#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x08L
+//GRA02
+#define GRA02__GRPH_CCOMP__SHIFT 0x0
+#define GRA02__GRPH_CCOMP_MASK 0x0FL
+//GRA03
+#define GRA03__GRPH_ROTATE__SHIFT 0x0
+#define GRA03__GRPH_FN_SEL__SHIFT 0x3
+#define GRA03__GRPH_ROTATE_MASK 0x07L
+#define GRA03__GRPH_FN_SEL_MASK 0x18L
+//GRA04
+#define GRA04__GRPH_RMAP__SHIFT 0x0
+#define GRA04__GRPH_RMAP_MASK 0x03L
+//GRA05
+#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0
+#define GRA05__GRPH_READ1__SHIFT 0x3
+#define GRA05__CGA_ODDEVEN__SHIFT 0x4
+#define GRA05__GRPH_OES__SHIFT 0x5
+#define GRA05__GRPH_PACK__SHIFT 0x6
+#define GRA05__GRPH_WRITE_MODE_MASK 0x03L
+#define GRA05__GRPH_READ1_MASK 0x08L
+#define GRA05__CGA_ODDEVEN_MASK 0x10L
+#define GRA05__GRPH_OES_MASK 0x20L
+#define GRA05__GRPH_PACK_MASK 0x40L
+//GRA06
+#define GRA06__GRPH_GRAPHICS__SHIFT 0x0
+#define GRA06__GRPH_ODDEVEN__SHIFT 0x1
+#define GRA06__GRPH_ADRSEL__SHIFT 0x2
+#define GRA06__GRPH_GRAPHICS_MASK 0x01L
+#define GRA06__GRPH_ODDEVEN_MASK 0x02L
+#define GRA06__GRPH_ADRSEL_MASK 0x0CL
+//GRA07
+#define GRA07__GRPH_XCARE0__SHIFT 0x0
+#define GRA07__GRPH_XCARE1__SHIFT 0x1
+#define GRA07__GRPH_XCARE2__SHIFT 0x2
+#define GRA07__GRPH_XCARE3__SHIFT 0x3
+#define GRA07__GRPH_XCARE0_MASK 0x01L
+#define GRA07__GRPH_XCARE1_MASK 0x02L
+#define GRA07__GRPH_XCARE2_MASK 0x04L
+#define GRA07__GRPH_XCARE3_MASK 0x08L
+//GRA08
+#define GRA08__GRPH_BMSK__SHIFT 0x0
+#define GRA08__GRPH_BMSK_MASK 0xFFL
+
+
+// addressBlock: vgaattrind
+//ATTR00
+#define ATTR00__ATTR_PAL__SHIFT 0x0
+#define ATTR00__ATTR_PAL_MASK 0x3FL
+//ATTR01
+#define ATTR01__ATTR_PAL__SHIFT 0x0
+#define ATTR01__ATTR_PAL_MASK 0x3FL
+//ATTR02
+#define ATTR02__ATTR_PAL__SHIFT 0x0
+#define ATTR02__ATTR_PAL_MASK 0x3FL
+//ATTR03
+#define ATTR03__ATTR_PAL__SHIFT 0x0
+#define ATTR03__ATTR_PAL_MASK 0x3FL
+//ATTR04
+#define ATTR04__ATTR_PAL__SHIFT 0x0
+#define ATTR04__ATTR_PAL_MASK 0x3FL
+//ATTR05
+#define ATTR05__ATTR_PAL__SHIFT 0x0
+#define ATTR05__ATTR_PAL_MASK 0x3FL
+//ATTR06
+#define ATTR06__ATTR_PAL__SHIFT 0x0
+#define ATTR06__ATTR_PAL_MASK 0x3FL
+//ATTR07
+#define ATTR07__ATTR_PAL__SHIFT 0x0
+#define ATTR07__ATTR_PAL_MASK 0x3FL
+//ATTR08
+#define ATTR08__ATTR_PAL__SHIFT 0x0
+#define ATTR08__ATTR_PAL_MASK 0x3FL
+//ATTR09
+#define ATTR09__ATTR_PAL__SHIFT 0x0
+#define ATTR09__ATTR_PAL_MASK 0x3FL
+//ATTR0A
+#define ATTR0A__ATTR_PAL__SHIFT 0x0
+#define ATTR0A__ATTR_PAL_MASK 0x3FL
+//ATTR0B
+#define ATTR0B__ATTR_PAL__SHIFT 0x0
+#define ATTR0B__ATTR_PAL_MASK 0x3FL
+//ATTR0C
+#define ATTR0C__ATTR_PAL__SHIFT 0x0
+#define ATTR0C__ATTR_PAL_MASK 0x3FL
+//ATTR0D
+#define ATTR0D__ATTR_PAL__SHIFT 0x0
+#define ATTR0D__ATTR_PAL_MASK 0x3FL
+//ATTR0E
+#define ATTR0E__ATTR_PAL__SHIFT 0x0
+#define ATTR0E__ATTR_PAL_MASK 0x3FL
+//ATTR0F
+#define ATTR0F__ATTR_PAL__SHIFT 0x0
+#define ATTR0F__ATTR_PAL_MASK 0x3FL
+//ATTR10
+#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0
+#define ATTR10__ATTR_MONO_EN__SHIFT 0x1
+#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2
+#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3
+#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5
+#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6
+#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7
+#define ATTR10__ATTR_GRPH_MODE_MASK 0x01L
+#define ATTR10__ATTR_MONO_EN_MASK 0x02L
+#define ATTR10__ATTR_LGRPH_EN_MASK 0x04L
+#define ATTR10__ATTR_BLINK_EN_MASK 0x08L
+#define ATTR10__ATTR_PANTOPONLY_MASK 0x20L
+#define ATTR10__ATTR_PCLKBY2_MASK 0x40L
+#define ATTR10__ATTR_CSEL_EN_MASK 0x80L
+//ATTR11
+#define ATTR11__ATTR_OVSC__SHIFT 0x0
+#define ATTR11__ATTR_OVSC_MASK 0xFFL
+//ATTR12
+#define ATTR12__ATTR_MAP_EN__SHIFT 0x0
+#define ATTR12__ATTR_VSMUX__SHIFT 0x4
+#define ATTR12__ATTR_MAP_EN_MASK 0x0FL
+#define ATTR12__ATTR_VSMUX_MASK 0x30L
+//ATTR13
+#define ATTR13__ATTR_PPAN__SHIFT 0x0
+#define ATTR13__ATTR_PPAN_MASK 0x0FL
+//ATTR14
+#define ATTR14__ATTR_CSEL1__SHIFT 0x0
+#define ATTR14__ATTR_CSEL2__SHIFT 0x2
+#define ATTR14__ATTR_CSEL1_MASK 0x03L
+#define ATTR14__ATTR_CSEL2_MASK 0x0CL
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_default.h
new file mode 100644
index 000000000000..663d3af35baf
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_default.h
@@ -0,0 +1,3873 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _gc_9_0_DEFAULT_HEADER
+#define _gc_9_0_DEFAULT_HEADER
+
+
+// addressBlock: gc_grbmdec
+#define mmGRBM_CNTL_DEFAULT 0x00000018
+#define mmGRBM_SKEW_CNTL_DEFAULT 0x00000020
+#define mmGRBM_STATUS2_DEFAULT 0x00000000
+#define mmGRBM_PWR_CNTL_DEFAULT 0x00000000
+#define mmGRBM_STATUS_DEFAULT 0x00000000
+#define mmGRBM_STATUS_SE0_DEFAULT 0x00000000
+#define mmGRBM_STATUS_SE1_DEFAULT 0x00000000
+#define mmGRBM_SOFT_RESET_DEFAULT 0x00000000
+#define mmGRBM_CGTT_CLK_CNTL_DEFAULT 0x00000100
+#define mmGRBM_GFX_CLKEN_CNTL_DEFAULT 0x00001008
+#define mmGRBM_WAIT_IDLE_CLOCKS_DEFAULT 0x00000030
+#define mmGRBM_STATUS_SE2_DEFAULT 0x00000000
+#define mmGRBM_STATUS_SE3_DEFAULT 0x00000000
+#define mmGRBM_READ_ERROR_DEFAULT 0x00000000
+#define mmGRBM_READ_ERROR2_DEFAULT 0x00000000
+#define mmGRBM_INT_CNTL_DEFAULT 0x00000000
+#define mmGRBM_TRAP_OP_DEFAULT 0x00000000
+#define mmGRBM_TRAP_ADDR_DEFAULT 0x00000000
+#define mmGRBM_TRAP_ADDR_MSK_DEFAULT 0x0003ffff
+#define mmGRBM_TRAP_WD_DEFAULT 0x00000000
+#define mmGRBM_TRAP_WD_MSK_DEFAULT 0xffffffff
+#define mmGRBM_DSM_BYPASS_DEFAULT 0x00000000
+#define mmGRBM_WRITE_ERROR_DEFAULT 0x00000000
+#define mmGRBM_IOV_ERROR_DEFAULT 0x00000000
+#define mmGRBM_CHIP_REVISION_DEFAULT 0x00000000
+#define mmGRBM_GFX_CNTL_DEFAULT 0x00000000
+#define mmGRBM_RSMU_CFG_DEFAULT 0x00011000
+#define mmGRBM_IH_CREDIT_DEFAULT 0x00010000
+#define mmGRBM_PWR_CNTL2_DEFAULT 0x00010000
+#define mmGRBM_UTCL2_INVAL_RANGE_START_DEFAULT 0x00002891
+#define mmGRBM_UTCL2_INVAL_RANGE_END_DEFAULT 0x000028ea
+#define mmGRBM_RSMU_READ_ERROR_DEFAULT 0x00000000
+#define mmGRBM_CHICKEN_BITS_DEFAULT 0x00000000
+#define mmGRBM_NOWHERE_DEFAULT 0x00000000
+#define mmGRBM_SCRATCH_REG0_DEFAULT 0x00000000
+#define mmGRBM_SCRATCH_REG1_DEFAULT 0x00000000
+#define mmGRBM_SCRATCH_REG2_DEFAULT 0x00000000
+#define mmGRBM_SCRATCH_REG3_DEFAULT 0x00000000
+#define mmGRBM_SCRATCH_REG4_DEFAULT 0x00000000
+#define mmGRBM_SCRATCH_REG5_DEFAULT 0x00000000
+#define mmGRBM_SCRATCH_REG6_DEFAULT 0x00000000
+#define mmGRBM_SCRATCH_REG7_DEFAULT 0x00000000
+
+
+// addressBlock: gc_cpdec
+#define mmCP_CPC_STATUS_DEFAULT 0x00000000
+#define mmCP_CPC_BUSY_STAT_DEFAULT 0x00000000
+#define mmCP_CPC_STALLED_STAT1_DEFAULT 0x00000000
+#define mmCP_CPF_STATUS_DEFAULT 0x00000000
+#define mmCP_CPF_BUSY_STAT_DEFAULT 0x00000000
+#define mmCP_CPF_STALLED_STAT1_DEFAULT 0x00000000
+#define mmCP_CPC_GRBM_FREE_COUNT_DEFAULT 0x00000008
+#define mmCP_MEC_CNTL_DEFAULT 0x50000000
+#define mmCP_MEC_ME1_HEADER_DUMP_DEFAULT 0x00000000
+#define mmCP_MEC_ME2_HEADER_DUMP_DEFAULT 0x00000000
+#define mmCP_CPC_SCRATCH_INDEX_DEFAULT 0x00000000
+#define mmCP_CPC_SCRATCH_DATA_DEFAULT 0x00000000
+#define mmCP_CPF_GRBM_FREE_COUNT_DEFAULT 0x00000004
+#define mmCP_CPC_HALT_HYST_COUNT_DEFAULT 0x00000002
+#define mmCP_PRT_LOD_STATS_CNTL0_DEFAULT 0x00000000
+#define mmCP_PRT_LOD_STATS_CNTL1_DEFAULT 0x00000000
+#define mmCP_PRT_LOD_STATS_CNTL2_DEFAULT 0x00000000
+#define mmCP_PRT_LOD_STATS_CNTL3_DEFAULT 0x00000000
+#define mmCP_CE_COMPARE_COUNT_DEFAULT 0x00000000
+#define mmCP_CE_DE_COUNT_DEFAULT 0x00000000
+#define mmCP_DE_CE_COUNT_DEFAULT 0x00000000
+#define mmCP_DE_LAST_INVAL_COUNT_DEFAULT 0x00000000
+#define mmCP_DE_DE_COUNT_DEFAULT 0x00000000
+#define mmCP_STALLED_STAT3_DEFAULT 0x00000000
+#define mmCP_STALLED_STAT1_DEFAULT 0x00000000
+#define mmCP_STALLED_STAT2_DEFAULT 0x00000000
+#define mmCP_BUSY_STAT_DEFAULT 0x00000000
+#define mmCP_STAT_DEFAULT 0x00000000
+#define mmCP_ME_HEADER_DUMP_DEFAULT 0x00000000
+#define mmCP_PFP_HEADER_DUMP_DEFAULT 0x00000000
+#define mmCP_GRBM_FREE_COUNT_DEFAULT 0x00080808
+#define mmCP_CE_HEADER_DUMP_DEFAULT 0x00000000
+#define mmCP_PFP_INSTR_PNTR_DEFAULT 0x00000000
+#define mmCP_ME_INSTR_PNTR_DEFAULT 0x00000000
+#define mmCP_CE_INSTR_PNTR_DEFAULT 0x00000000
+#define mmCP_MEC1_INSTR_PNTR_DEFAULT 0x00000000
+#define mmCP_MEC2_INSTR_PNTR_DEFAULT 0x00000000
+#define mmCP_CSF_STAT_DEFAULT 0x00000000
+#define mmCP_ME_CNTL_DEFAULT 0x15000000
+#define mmCP_CNTX_STAT_DEFAULT 0x00000000
+#define mmCP_ME_PREEMPTION_DEFAULT 0x00000000
+#define mmCP_ROQ_THRESHOLDS_DEFAULT 0x00003010
+#define mmCP_MEQ_STQ_THRESHOLD_DEFAULT 0x00000010
+#define mmCP_RB2_RPTR_DEFAULT 0x00000000
+#define mmCP_RB1_RPTR_DEFAULT 0x00000000
+#define mmCP_RB0_RPTR_DEFAULT 0x00000000
+#define mmCP_RB_RPTR_DEFAULT 0x00000000
+#define mmCP_RB_WPTR_DELAY_DEFAULT 0x00000000
+#define mmCP_RB_WPTR_POLL_CNTL_DEFAULT 0x00400100
+#define mmCP_ROQ1_THRESHOLDS_DEFAULT 0x30101010
+#define mmCP_ROQ2_THRESHOLDS_DEFAULT 0x40403030
+#define mmCP_STQ_THRESHOLDS_DEFAULT 0x00804000
+#define mmCP_QUEUE_THRESHOLDS_DEFAULT 0x00002b16
+#define mmCP_MEQ_THRESHOLDS_DEFAULT 0x00008040
+#define mmCP_ROQ_AVAIL_DEFAULT 0x00000000
+#define mmCP_STQ_AVAIL_DEFAULT 0x00000000
+#define mmCP_ROQ2_AVAIL_DEFAULT 0x00000000
+#define mmCP_MEQ_AVAIL_DEFAULT 0x00000000
+#define mmCP_CMD_INDEX_DEFAULT 0x00000000
+#define mmCP_CMD_DATA_DEFAULT 0x00000000
+#define mmCP_ROQ_RB_STAT_DEFAULT 0x00000000
+#define mmCP_ROQ_IB1_STAT_DEFAULT 0x00000000
+#define mmCP_ROQ_IB2_STAT_DEFAULT 0x00000000
+#define mmCP_STQ_STAT_DEFAULT 0x00000000
+#define mmCP_STQ_WR_STAT_DEFAULT 0x00000000
+#define mmCP_MEQ_STAT_DEFAULT 0x00000000
+#define mmCP_CEQ1_AVAIL_DEFAULT 0x00000000
+#define mmCP_CEQ2_AVAIL_DEFAULT 0x00000000
+#define mmCP_CE_ROQ_RB_STAT_DEFAULT 0x00000000
+#define mmCP_CE_ROQ_IB1_STAT_DEFAULT 0x00000000
+#define mmCP_CE_ROQ_IB2_STAT_DEFAULT 0x00000000
+#define mmCP_INT_STAT_DEBUG_DEFAULT 0x00000000
+
+
+// addressBlock: gc_padec
+#define mmVGT_VTX_VECT_EJECT_REG_DEFAULT 0x0000007d
+#define mmVGT_DMA_DATA_FIFO_DEPTH_DEFAULT 0x00040180
+#define mmVGT_DMA_REQ_FIFO_DEPTH_DEFAULT 0x00000020
+#define mmVGT_DRAW_INIT_FIFO_DEPTH_DEFAULT 0x00000020
+#define mmVGT_LAST_COPY_STATE_DEFAULT 0x00000000
+#define mmVGT_CACHE_INVALIDATION_DEFAULT 0x09000000
+#define mmVGT_RESET_DEBUG_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_DELAY_DEFAULT 0x00092420
+#define mmVGT_FIFO_DEPTHS_DEFAULT 0x08000040
+#define mmVGT_GS_VERTEX_REUSE_DEFAULT 0x00000010
+#define mmVGT_MC_LAT_CNTL_DEFAULT 0x000000fe
+#define mmIA_CNTL_STATUS_DEFAULT 0x00000000
+#define mmVGT_CNTL_STATUS_DEFAULT 0x00000000
+#define mmWD_CNTL_STATUS_DEFAULT 0x00000000
+#define mmCC_GC_PRIM_CONFIG_DEFAULT 0x00000000
+#define mmGC_USER_PRIM_CONFIG_DEFAULT 0x00000000
+#define mmWD_QOS_DEFAULT 0x00000000
+#define mmWD_UTCL1_CNTL_DEFAULT 0x00000080
+#define mmWD_UTCL1_STATUS_DEFAULT 0x00000000
+#define mmIA_UTCL1_CNTL_DEFAULT 0x00000080
+#define mmIA_UTCL1_STATUS_DEFAULT 0x00000000
+#define mmVGT_SYS_CONFIG_DEFAULT 0x00000011
+#define mmVGT_VS_MAX_WAVE_ID_DEFAULT 0x000001ff
+#define mmVGT_GS_MAX_WAVE_ID_DEFAULT 0x000003ff
+#define mmGFX_PIPE_CONTROL_DEFAULT 0x00000000
+#define mmCC_GC_SHADER_ARRAY_CONFIG_DEFAULT 0x00000000
+#define mmGC_USER_SHADER_ARRAY_CONFIG_DEFAULT 0x00000000
+#define mmVGT_DMA_PRIMITIVE_TYPE_DEFAULT 0x00000000
+#define mmVGT_DMA_CONTROL_DEFAULT 0x000000ff
+#define mmVGT_DMA_LS_HS_CONFIG_DEFAULT 0x00000000
+#define mmWD_BUF_RESOURCE_1_DEFAULT 0x00000000
+#define mmWD_BUF_RESOURCE_2_DEFAULT 0x00000000
+#define mmPA_CL_CNTL_STATUS_DEFAULT 0x00000000
+#define mmPA_CL_ENHANCE_DEFAULT 0x00000007
+#define mmPA_CL_RESET_DEBUG_DEFAULT 0x00000000
+#define mmPA_SU_CNTL_STATUS_DEFAULT 0x00000000
+#define mmPA_SC_FIFO_DEPTH_CNTL_DEFAULT 0x00000100
+#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000
+#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000
+#define mmPA_SC_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000
+#define mmPA_SC_FORCE_EOV_MAX_CNTS_DEFAULT 0x00ffffff
+#define mmPA_SC_BINNER_EVENT_CNTL_0_DEFAULT 0x842a4402
+#define mmPA_SC_BINNER_EVENT_CNTL_1_DEFAULT 0x8a000008
+#define mmPA_SC_BINNER_EVENT_CNTL_2_DEFAULT 0x9118aaa8
+#define mmPA_SC_BINNER_EVENT_CNTL_3_DEFAULT 0x82400025
+#define mmPA_SC_BINNER_TIMEOUT_COUNTER_DEFAULT 0x00000000
+#define mmPA_SC_BINNER_PERF_CNTL_0_DEFAULT 0x00000000
+#define mmPA_SC_BINNER_PERF_CNTL_1_DEFAULT 0x00000000
+#define mmPA_SC_BINNER_PERF_CNTL_2_DEFAULT 0x00000000
+#define mmPA_SC_BINNER_PERF_CNTL_3_DEFAULT 0x00000000
+#define mmPA_SC_FIFO_SIZE_DEFAULT 0x00000000
+#define mmPA_SC_IF_FIFO_SIZE_DEFAULT 0x00000000
+#define mmPA_SC_PKR_WAVE_TABLE_CNTL_DEFAULT 0x00000000
+#define mmPA_UTCL1_CNTL1_DEFAULT 0x00000600
+#define mmPA_UTCL1_CNTL2_DEFAULT 0x00000000
+#define mmPA_SIDEBAND_REQUEST_DELAYS_DEFAULT 0x08000020
+#define mmPA_SC_ENHANCE_DEFAULT 0x00000001
+#define mmPA_SC_ENHANCE_1_DEFAULT 0x00040000
+#define mmPA_SC_DSM_CNTL_DEFAULT 0x00000000
+#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_DEFAULT 0x00000000
+
+
+// addressBlock: gc_sqdec
+#define mmSQ_CONFIG_DEFAULT 0x01180000
+#define mmSQC_CONFIG_DEFAULT 0x010a2000
+#define mmLDS_CONFIG_DEFAULT 0x00000000
+#define mmSQ_RANDOM_WAVE_PRI_DEFAULT 0x0000007f
+#define mmSQ_REG_CREDITS_DEFAULT 0x00000820
+#define mmSQ_FIFO_SIZES_DEFAULT 0x00000f01
+#define mmSQ_DSM_CNTL_DEFAULT 0x00000000
+#define mmSQ_DSM_CNTL2_DEFAULT 0x00000000
+#define mmSQ_RUNTIME_CONFIG_DEFAULT 0x00000000
+#define mmSH_MEM_BASES_DEFAULT 0x00000000
+#define mmSH_MEM_CONFIG_DEFAULT 0x00000000
+#define mmCC_GC_SHADER_RATE_CONFIG_DEFAULT 0x00000000
+#define mmGC_USER_SHADER_RATE_CONFIG_DEFAULT 0x00000000
+#define mmSQ_INTERRUPT_AUTO_MASK_DEFAULT 0x00ffffff
+#define mmSQ_INTERRUPT_MSG_CTRL_DEFAULT 0x00000000
+#define mmSQ_UTCL1_CNTL1_DEFAULT 0x00000580
+#define mmSQ_UTCL1_CNTL2_DEFAULT 0x00000000
+#define mmSQ_UTCL1_STATUS_DEFAULT 0x00000000
+#define mmSQ_SHADER_TBA_LO_DEFAULT 0x00000000
+#define mmSQ_SHADER_TBA_HI_DEFAULT 0x00000000
+#define mmSQ_SHADER_TMA_LO_DEFAULT 0x00000000
+#define mmSQ_SHADER_TMA_HI_DEFAULT 0x00000000
+#define mmSQC_DSM_CNTL_DEFAULT 0x00000000
+#define mmSQC_DSM_CNTLA_DEFAULT 0x00000000
+#define mmSQC_DSM_CNTLB_DEFAULT 0x00000000
+#define mmSQC_DSM_CNTL2_DEFAULT 0x00000000
+#define mmSQC_DSM_CNTL2A_DEFAULT 0x00000000
+#define mmSQC_DSM_CNTL2B_DEFAULT 0x00000000
+#define mmSQC_EDC_FUE_CNTL_DEFAULT 0x00000000
+#define mmSQC_EDC_CNT2_DEFAULT 0x00000000
+#define mmSQC_EDC_CNT3_DEFAULT 0x00000000
+#define mmSQ_REG_TIMESTAMP_DEFAULT 0x00000000
+#define mmSQ_CMD_TIMESTAMP_DEFAULT 0x00000000
+#define mmSQ_IND_INDEX_DEFAULT 0x00000000
+#define mmSQ_IND_DATA_DEFAULT 0x00000000
+#define mmSQ_CMD_DEFAULT 0x00000000
+#define mmSQ_TIME_HI_DEFAULT 0x00000000
+#define mmSQ_TIME_LO_DEFAULT 0x00000000
+#define mmSQ_DS_0_DEFAULT 0x00000000
+#define mmSQ_DS_1_DEFAULT 0x00000000
+#define mmSQ_EXP_0_DEFAULT 0x00000000
+#define mmSQ_EXP_1_DEFAULT 0x00000000
+#define mmSQ_FLAT_0_DEFAULT 0x00000000
+#define mmSQ_FLAT_1_DEFAULT 0x00000000
+#define mmSQ_GLBL_0_DEFAULT 0x00000000
+#define mmSQ_GLBL_1_DEFAULT 0x00000000
+#define mmSQ_INST_DEFAULT 0x00000000
+#define mmSQ_MIMG_0_DEFAULT 0x00000000
+#define mmSQ_MIMG_1_DEFAULT 0x00000000
+#define mmSQ_MTBUF_0_DEFAULT 0x00000000
+#define mmSQ_MTBUF_1_DEFAULT 0x00000000
+#define mmSQ_MUBUF_0_DEFAULT 0x00000000
+#define mmSQ_MUBUF_1_DEFAULT 0x00000000
+#define mmSQ_SCRATCH_0_DEFAULT 0x00000000
+#define mmSQ_SCRATCH_1_DEFAULT 0x00000000
+#define mmSQ_SMEM_0_DEFAULT 0x00000000
+#define mmSQ_SMEM_1_DEFAULT 0x00000000
+#define mmSQ_SOP1_DEFAULT 0x00000000
+#define mmSQ_SOP2_DEFAULT 0x00000000
+#define mmSQ_SOPC_DEFAULT 0x00000000
+#define mmSQ_SOPK_DEFAULT 0x00000000
+#define mmSQ_SOPP_DEFAULT 0x00000000
+#define mmSQ_VINTRP_DEFAULT 0x00000000
+#define mmSQ_VOP1_DEFAULT 0x00000000
+#define mmSQ_VOP2_DEFAULT 0x00000000
+#define mmSQ_VOP3P_0_DEFAULT 0x00000000
+#define mmSQ_VOP3P_1_DEFAULT 0x00000000
+#define mmSQ_VOP3_0_DEFAULT 0x00000000
+#define mmSQ_VOP3_0_SDST_ENC_DEFAULT 0x00000000
+#define mmSQ_VOP3_1_DEFAULT 0x00000000
+#define mmSQ_VOPC_DEFAULT 0x00000000
+#define mmSQ_VOP_DPP_DEFAULT 0x00000000
+#define mmSQ_VOP_SDWA_DEFAULT 0x00000000
+#define mmSQ_VOP_SDWA_SDST_ENC_DEFAULT 0x00000000
+#define mmSQ_LB_CTR_CTRL_DEFAULT 0x00000000
+#define mmSQ_LB_DATA0_DEFAULT 0x00000000
+#define mmSQ_LB_DATA1_DEFAULT 0x00000000
+#define mmSQ_LB_DATA2_DEFAULT 0x00000000
+#define mmSQ_LB_DATA3_DEFAULT 0x00000000
+#define mmSQ_LB_CTR_SEL_DEFAULT 0x00000000
+#define mmSQ_LB_CTR0_CU_DEFAULT 0xffffffff
+#define mmSQ_LB_CTR1_CU_DEFAULT 0xffffffff
+#define mmSQ_LB_CTR2_CU_DEFAULT 0xffffffff
+#define mmSQ_LB_CTR3_CU_DEFAULT 0xffffffff
+#define mmSQC_EDC_CNT_DEFAULT 0x00000000
+#define mmSQ_EDC_SEC_CNT_DEFAULT 0x00000000
+#define mmSQ_EDC_DED_CNT_DEFAULT 0x00000000
+#define mmSQ_EDC_INFO_DEFAULT 0x00000000
+#define mmSQ_EDC_CNT_DEFAULT 0x00000000
+#define mmSQ_EDC_FUE_CNTL_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_WORD_CMN_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_WORD_EVENT_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_WORD_INST_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_WORD_ISSUE_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_WORD_MISC_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_WORD_WAVE_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_WORD_WAVE_START_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_DEFAULT 0x00000000
+#define mmSQ_WREXEC_EXEC_HI_DEFAULT 0x00000000
+#define mmSQ_WREXEC_EXEC_LO_DEFAULT 0x00000000
+#define mmSQ_BUF_RSRC_WORD0_DEFAULT 0x00000000
+#define mmSQ_BUF_RSRC_WORD1_DEFAULT 0x00000000
+#define mmSQ_BUF_RSRC_WORD2_DEFAULT 0x00000000
+#define mmSQ_BUF_RSRC_WORD3_DEFAULT 0x00000000
+#define mmSQ_IMG_RSRC_WORD0_DEFAULT 0x00000000
+#define mmSQ_IMG_RSRC_WORD1_DEFAULT 0x00000000
+#define mmSQ_IMG_RSRC_WORD2_DEFAULT 0x00000000
+#define mmSQ_IMG_RSRC_WORD3_DEFAULT 0x00000000
+#define mmSQ_IMG_RSRC_WORD4_DEFAULT 0x00000000
+#define mmSQ_IMG_RSRC_WORD5_DEFAULT 0x00000000
+#define mmSQ_IMG_RSRC_WORD6_DEFAULT 0x00000000
+#define mmSQ_IMG_RSRC_WORD7_DEFAULT 0x00000000
+#define mmSQ_IMG_SAMP_WORD0_DEFAULT 0x00000000
+#define mmSQ_IMG_SAMP_WORD1_DEFAULT 0x00000000
+#define mmSQ_IMG_SAMP_WORD2_DEFAULT 0x00000000
+#define mmSQ_IMG_SAMP_WORD3_DEFAULT 0x00000000
+#define mmSQ_FLAT_SCRATCH_WORD0_DEFAULT 0x00000000
+#define mmSQ_FLAT_SCRATCH_WORD1_DEFAULT 0x00000000
+#define mmSQ_M0_GPR_IDX_WORD_DEFAULT 0x00000000
+#define mmSQC_ICACHE_UTCL1_CNTL1_DEFAULT 0x00000480
+#define mmSQC_ICACHE_UTCL1_CNTL2_DEFAULT 0x00000000
+#define mmSQC_DCACHE_UTCL1_CNTL1_DEFAULT 0x00000500
+#define mmSQC_DCACHE_UTCL1_CNTL2_DEFAULT 0x00000000
+#define mmSQC_ICACHE_UTCL1_STATUS_DEFAULT 0x00000000
+#define mmSQC_DCACHE_UTCL1_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: gc_shsdec
+#define mmSX_DEBUG_BUSY_DEFAULT 0x00000000
+#define mmSX_DEBUG_BUSY_2_DEFAULT 0x00000000
+#define mmSX_DEBUG_BUSY_3_DEFAULT 0x00000000
+#define mmSX_DEBUG_BUSY_4_DEFAULT 0x00000000
+#define mmSX_DEBUG_BUSY_5_DEFAULT 0x00000000
+#define mmSX_DEBUG_1_DEFAULT 0x00000020
+#define mmSPI_PS_MAX_WAVE_ID_DEFAULT 0x0200017f
+#define mmSPI_START_PHASE_DEFAULT 0x00000000
+#define mmSPI_GFX_CNTL_DEFAULT 0x00000000
+#define mmSPI_DEBUG_READ_DEFAULT 0x00000000
+#define mmSPI_DSM_CNTL_DEFAULT 0x00000000
+#define mmSPI_DSM_CNTL2_DEFAULT 0x00000000
+#define mmSPI_EDC_CNT_DEFAULT 0x00000000
+#define mmSPI_DEBUG_BUSY_DEFAULT 0x00000000
+#define mmSPI_CONFIG_PS_CU_EN_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_CNTL_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_LIMIT_0_DEFAULT 0x00000100
+#define mmSPI_WF_LIFETIME_LIMIT_1_DEFAULT 0x00000100
+#define mmSPI_WF_LIFETIME_LIMIT_2_DEFAULT 0x00000100
+#define mmSPI_WF_LIFETIME_LIMIT_3_DEFAULT 0x00000100
+#define mmSPI_WF_LIFETIME_LIMIT_4_DEFAULT 0x00000100
+#define mmSPI_WF_LIFETIME_LIMIT_5_DEFAULT 0x00000100
+#define mmSPI_WF_LIFETIME_LIMIT_6_DEFAULT 0x00000100
+#define mmSPI_WF_LIFETIME_LIMIT_7_DEFAULT 0x00000100
+#define mmSPI_WF_LIFETIME_LIMIT_8_DEFAULT 0x00000100
+#define mmSPI_WF_LIFETIME_LIMIT_9_DEFAULT 0x00000100
+#define mmSPI_WF_LIFETIME_STATUS_0_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_1_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_2_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_3_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_4_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_5_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_6_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_7_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_8_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_9_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_10_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_11_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_12_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_13_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_14_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_15_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_16_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_17_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_18_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_19_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_20_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_DEBUG_DEFAULT 0x00000000
+#define mmSPI_LB_CTR_CTRL_DEFAULT 0x00000000
+#define mmSPI_LB_CU_MASK_DEFAULT 0x0000ffff
+#define mmSPI_LB_DATA_REG_DEFAULT 0x00000000
+#define mmSPI_PG_ENABLE_STATIC_CU_MASK_DEFAULT 0x0000ffff
+#define mmSPI_GDS_CREDITS_DEFAULT 0x00001080
+#define mmSPI_SX_EXPORT_BUFFER_SIZES_DEFAULT 0x08000400
+#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES_DEFAULT 0x00200040
+#define mmSPI_CSQ_WF_ACTIVE_STATUS_DEFAULT 0x00000000
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_0_DEFAULT 0x00000000
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_1_DEFAULT 0x00000000
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_2_DEFAULT 0x00000000
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_3_DEFAULT 0x00000000
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_4_DEFAULT 0x00000000
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_5_DEFAULT 0x00000000
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_6_DEFAULT 0x00000000
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_7_DEFAULT 0x00000000
+#define mmSPI_LB_DATA_WAVES_DEFAULT 0x00000000
+#define mmSPI_LB_DATA_PERCU_WAVE_HSGS_DEFAULT 0x00000000
+#define mmSPI_LB_DATA_PERCU_WAVE_VSPS_DEFAULT 0x00000000
+#define mmSPI_LB_DATA_PERCU_WAVE_CS_DEFAULT 0x00000000
+#define mmSPIS_DEBUG_READ_DEFAULT 0x00000000
+#define mmBCI_DEBUG_READ_DEFAULT 0x00000000
+#define mmSPI_P0_TRAP_SCREEN_PSBA_LO_DEFAULT 0x00000000
+#define mmSPI_P0_TRAP_SCREEN_PSBA_HI_DEFAULT 0x00000000
+#define mmSPI_P0_TRAP_SCREEN_PSMA_LO_DEFAULT 0x00000000
+#define mmSPI_P0_TRAP_SCREEN_PSMA_HI_DEFAULT 0x00000000
+#define mmSPI_P0_TRAP_SCREEN_GPR_MIN_DEFAULT 0x00000000
+#define mmSPI_P1_TRAP_SCREEN_PSBA_LO_DEFAULT 0x00000000
+#define mmSPI_P1_TRAP_SCREEN_PSBA_HI_DEFAULT 0x00000000
+#define mmSPI_P1_TRAP_SCREEN_PSMA_LO_DEFAULT 0x00000000
+#define mmSPI_P1_TRAP_SCREEN_PSMA_HI_DEFAULT 0x00000000
+#define mmSPI_P1_TRAP_SCREEN_GPR_MIN_DEFAULT 0x00000000
+
+
+// addressBlock: gc_tpdec
+#define mmTD_CNTL_DEFAULT 0x00000000
+#define mmTD_STATUS_DEFAULT 0x00000000
+#define mmTD_DSM_CNTL_DEFAULT 0x00000000
+#define mmTD_DSM_CNTL2_DEFAULT 0x00000000
+#define mmTD_SCRATCH_DEFAULT 0x00000000
+#define mmTA_CNTL_DEFAULT 0x8004d850
+#define mmTA_CNTL_AUX_DEFAULT 0x00000000
+#define mmTA_RESERVED_010C_DEFAULT 0x00000000
+#define mmTA_GRAD_ADJ_DEFAULT 0x40000040
+#define mmTA_STATUS_DEFAULT 0x00000000
+#define mmTA_SCRATCH_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gdsdec
+#define mmGDS_CONFIG_DEFAULT 0x00000000
+#define mmGDS_CNTL_STATUS_DEFAULT 0x00000000
+#define mmGDS_ENHANCE2_DEFAULT 0x00000000
+#define mmGDS_PROTECTION_FAULT_DEFAULT 0x00000000
+#define mmGDS_VM_PROTECTION_FAULT_DEFAULT 0x00000000
+#define mmGDS_EDC_CNT_DEFAULT 0x00000000
+#define mmGDS_EDC_GRBM_CNT_DEFAULT 0x00000000
+#define mmGDS_EDC_OA_DED_DEFAULT 0x00000000
+#define mmGDS_DSM_CNTL_DEFAULT 0x00000000
+#define mmGDS_EDC_OA_PHY_CNT_DEFAULT 0x00000000
+#define mmGDS_EDC_OA_PIPE_CNT_DEFAULT 0x00000000
+#define mmGDS_DSM_CNTL2_DEFAULT 0x00000000
+#define mmGDS_WD_GDS_CSB_DEFAULT 0x00000000
+
+
+// addressBlock: gc_rbdec
+#define mmDB_DEBUG_DEFAULT 0x00000000
+#define mmDB_DEBUG2_DEFAULT 0x00000000
+#define mmDB_DEBUG3_DEFAULT 0x00000000
+#define mmDB_DEBUG4_DEFAULT 0x00000000
+#define mmDB_CREDIT_LIMIT_DEFAULT 0x00000000
+#define mmDB_WATERMARKS_DEFAULT 0x01020204
+#define mmDB_SUBTILE_CONTROL_DEFAULT 0x00000000
+#define mmDB_FREE_CACHELINES_DEFAULT 0x00000000
+#define mmDB_FIFO_DEPTH1_DEFAULT 0x00000000
+#define mmDB_FIFO_DEPTH2_DEFAULT 0x00000000
+#define mmDB_EXCEPTION_CONTROL_DEFAULT 0x00000000
+#define mmDB_RING_CONTROL_DEFAULT 0x00000001
+#define mmDB_MEM_ARB_WATERMARKS_DEFAULT 0x04040404
+#define mmDB_RMI_CACHE_POLICY_DEFAULT 0x0f0f0f07
+#define mmDB_DFSM_CONFIG_DEFAULT 0x00007f00
+#define mmDB_DFSM_WATERMARK_DEFAULT 0x00640064
+#define mmDB_DFSM_TILES_IN_FLIGHT_DEFAULT 0x05dc03e8
+#define mmDB_DFSM_PRIMS_IN_FLIGHT_DEFAULT 0x00fa00c8
+#define mmDB_DFSM_WATCHDOG_DEFAULT 0x000f4240
+#define mmDB_DFSM_FLUSH_ENABLE_DEFAULT 0x000003ff
+#define mmDB_DFSM_FLUSH_AUX_EVENT_DEFAULT 0x00000000
+#define mmCC_RB_REDUNDANCY_DEFAULT 0x00000000
+#define mmCC_RB_BACKEND_DISABLE_DEFAULT 0x00000000
+#define mmGB_ADDR_CONFIG_DEFAULT 0x2a110012
+#define mmGB_BACKEND_MAP_DEFAULT 0x76541032
+#define mmGB_GPU_ID_DEFAULT 0x00000000
+#define mmCC_RB_DAISY_CHAIN_DEFAULT 0x76543210
+#define mmGB_ADDR_CONFIG_READ_DEFAULT 0x2a110012
+#define mmGB_TILE_MODE0_DEFAULT 0x00000000
+#define mmGB_TILE_MODE1_DEFAULT 0x00000000
+#define mmGB_TILE_MODE2_DEFAULT 0x00000000
+#define mmGB_TILE_MODE3_DEFAULT 0x00000000
+#define mmGB_TILE_MODE4_DEFAULT 0x00000000
+#define mmGB_TILE_MODE5_DEFAULT 0x00000000
+#define mmGB_TILE_MODE6_DEFAULT 0x00000000
+#define mmGB_TILE_MODE7_DEFAULT 0x00000000
+#define mmGB_TILE_MODE8_DEFAULT 0x00000000
+#define mmGB_TILE_MODE9_DEFAULT 0x00000000
+#define mmGB_TILE_MODE10_DEFAULT 0x00000000
+#define mmGB_TILE_MODE11_DEFAULT 0x00000000
+#define mmGB_TILE_MODE12_DEFAULT 0x00000000
+#define mmGB_TILE_MODE13_DEFAULT 0x00000000
+#define mmGB_TILE_MODE14_DEFAULT 0x00000000
+#define mmGB_TILE_MODE15_DEFAULT 0x00000000
+#define mmGB_TILE_MODE16_DEFAULT 0x00000000
+#define mmGB_TILE_MODE17_DEFAULT 0x00000000
+#define mmGB_TILE_MODE18_DEFAULT 0x00000000
+#define mmGB_TILE_MODE19_DEFAULT 0x00000000
+#define mmGB_TILE_MODE20_DEFAULT 0x00000000
+#define mmGB_TILE_MODE21_DEFAULT 0x00000000
+#define mmGB_TILE_MODE22_DEFAULT 0x00000000
+#define mmGB_TILE_MODE23_DEFAULT 0x00000000
+#define mmGB_TILE_MODE24_DEFAULT 0x00000000
+#define mmGB_TILE_MODE25_DEFAULT 0x00000000
+#define mmGB_TILE_MODE26_DEFAULT 0x00000000
+#define mmGB_TILE_MODE27_DEFAULT 0x00000000
+#define mmGB_TILE_MODE28_DEFAULT 0x00000000
+#define mmGB_TILE_MODE29_DEFAULT 0x00000000
+#define mmGB_TILE_MODE30_DEFAULT 0x00000000
+#define mmGB_TILE_MODE31_DEFAULT 0x00000000
+#define mmGB_MACROTILE_MODE0_DEFAULT 0x00000000
+#define mmGB_MACROTILE_MODE1_DEFAULT 0x00000000
+#define mmGB_MACROTILE_MODE2_DEFAULT 0x00000000
+#define mmGB_MACROTILE_MODE3_DEFAULT 0x00000000
+#define mmGB_MACROTILE_MODE4_DEFAULT 0x00000000
+#define mmGB_MACROTILE_MODE5_DEFAULT 0x00000000
+#define mmGB_MACROTILE_MODE6_DEFAULT 0x00000000
+#define mmGB_MACROTILE_MODE7_DEFAULT 0x00000000
+#define mmGB_MACROTILE_MODE8_DEFAULT 0x00000000
+#define mmGB_MACROTILE_MODE9_DEFAULT 0x00000000
+#define mmGB_MACROTILE_MODE10_DEFAULT 0x00000000
+#define mmGB_MACROTILE_MODE11_DEFAULT 0x00000000
+#define mmGB_MACROTILE_MODE12_DEFAULT 0x00000000
+#define mmGB_MACROTILE_MODE13_DEFAULT 0x00000000
+#define mmGB_MACROTILE_MODE14_DEFAULT 0x00000000
+#define mmGB_MACROTILE_MODE15_DEFAULT 0x00000000
+#define mmCB_HW_CONTROL_DEFAULT 0x00014107
+#define mmCB_HW_CONTROL_1_DEFAULT 0x10000000
+#define mmCB_HW_CONTROL_2_DEFAULT 0x00000000
+#define mmCB_HW_CONTROL_3_DEFAULT 0x00000000
+#define mmCB_HW_MEM_ARBITER_RD_DEFAULT 0x00029000
+#define mmCB_HW_MEM_ARBITER_WR_DEFAULT 0x00029000
+#define mmCB_DCC_CONFIG_DEFAULT 0x04000000
+#define mmGC_USER_RB_REDUNDANCY_DEFAULT 0x00000000
+#define mmGC_USER_RB_BACKEND_DISABLE_DEFAULT 0x00000000
+
+
+// addressBlock: gc_rmi_rmidec
+#define mmRMI_GENERAL_CNTL_DEFAULT 0x00000000
+#define mmRMI_GENERAL_CNTL1_DEFAULT 0x00001a03
+#define mmRMI_GENERAL_STATUS_DEFAULT 0x00000000
+#define mmRMI_SUBBLOCK_STATUS0_DEFAULT 0x00000000
+#define mmRMI_SUBBLOCK_STATUS1_DEFAULT 0x00000000
+#define mmRMI_SUBBLOCK_STATUS2_DEFAULT 0x00000000
+#define mmRMI_SUBBLOCK_STATUS3_DEFAULT 0x00000000
+#define mmRMI_XBAR_CONFIG_DEFAULT 0x00000f00
+#define mmRMI_PROBE_POP_LOGIC_CNTL_DEFAULT 0x000340d0
+#define mmRMI_UTC_XNACK_N_MISC_CNTL_DEFAULT 0x00000564
+#define mmRMI_DEMUX_CNTL_DEFAULT 0x02000200
+#define mmRMI_UTCL1_CNTL1_DEFAULT 0x00020000
+#define mmRMI_UTCL1_CNTL2_DEFAULT 0x00010000
+#define mmRMI_UTC_UNIT_CONFIG_DEFAULT 0x00000000
+#define mmRMI_TCIW_FORMATTER0_CNTL_DEFAULT 0x4404001e
+#define mmRMI_TCIW_FORMATTER1_CNTL_DEFAULT 0x4404001e
+#define mmRMI_SCOREBOARD_CNTL_DEFAULT 0x001ffe00
+#define mmRMI_SCOREBOARD_STATUS0_DEFAULT 0x00000000
+#define mmRMI_SCOREBOARD_STATUS1_DEFAULT 0x00000000
+#define mmRMI_SCOREBOARD_STATUS2_DEFAULT 0x00000000
+#define mmRMI_XBAR_ARBITER_CONFIG_DEFAULT 0x08000800
+#define mmRMI_XBAR_ARBITER_CONFIG_1_DEFAULT 0xffffffff
+#define mmRMI_CLOCK_CNTRL_DEFAULT 0x04208822
+#define mmRMI_UTCL1_STATUS_DEFAULT 0x00000000
+#define mmRMI_XNACK_DEBUG_DEFAULT 0x00000000
+#define mmRMI_SPARE_DEFAULT 0x00000001
+#define mmRMI_SPARE_1_DEFAULT 0x00000000
+#define mmRMI_SPARE_2_DEFAULT 0x00000000
+
+
+// addressBlock: gc_utcl2_atcl2dec
+#define mmATC_L2_CNTL_DEFAULT 0x000001c9
+#define mmATC_L2_CNTL2_DEFAULT 0x00000100
+#define mmATC_L2_CACHE_DATA0_DEFAULT 0x00000000
+#define mmATC_L2_CACHE_DATA1_DEFAULT 0x00000000
+#define mmATC_L2_CACHE_DATA2_DEFAULT 0x00000000
+#define mmATC_L2_CNTL3_DEFAULT 0x000001f8
+#define mmATC_L2_STATUS_DEFAULT 0x00000000
+#define mmATC_L2_STATUS2_DEFAULT 0x00000000
+#define mmATC_L2_MISC_CG_DEFAULT 0x00000200
+#define mmATC_L2_MEM_POWER_LS_DEFAULT 0x00000208
+#define mmATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080
+
+
+// addressBlock: gc_utcl2_vml2pfdec
+#define mmVM_L2_CNTL_DEFAULT 0x00080602
+#define mmVM_L2_CNTL2_DEFAULT 0x00000000
+#define mmVM_L2_CNTL3_DEFAULT 0x80100007
+#define mmVM_L2_STATUS_DEFAULT 0x00000000
+#define mmVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090
+#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc
+#define mmVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000
+#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff
+#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff
+#define mmVM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000
+#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000
+#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000
+#define mmVM_L2_CNTL4_DEFAULT 0x000000c1
+#define mmVM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000
+#define mmVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000
+#define mmVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000
+#define mmVM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000
+#define mmVM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080
+
+
+// addressBlock: gc_utcl2_vml2vcdec
+#define mmVM_CONTEXT0_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT1_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT2_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT3_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT4_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT5_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT6_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT7_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT8_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT9_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT10_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT11_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT12_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT13_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT14_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT15_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXTS_DISABLE_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG0_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG1_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG2_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG3_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG4_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG5_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG6_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG7_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG8_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG9_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG10_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG11_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG12_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG13_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG14_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG15_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG16_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG17_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+
+
+// addressBlock: gc_utcl2_vmsharedpfdec
+#define mmMC_VM_NB_MMIOBASE_DEFAULT 0x00000000
+#define mmMC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000
+#define mmMC_VM_NB_PCI_CTRL_DEFAULT 0x00000000
+#define mmMC_VM_NB_PCI_ARB_DEFAULT 0x00000008
+#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000
+#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000
+#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000
+#define mmMC_VM_FB_OFFSET_DEFAULT 0x00000000
+#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000
+#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000
+#define mmMC_VM_STEERING_DEFAULT 0x00000001
+#define mmMC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000
+#define mmMC_MEM_POWER_LS_DEFAULT 0x00000208
+#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000
+#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000
+#define mmMC_VM_APT_CNTL_DEFAULT 0x00000000
+#define mmMC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000
+#define mmMC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff
+#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: gc_utcl2_vmsharedvcdec
+#define mmMC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000
+#define mmMC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000
+#define mmMC_VM_AGP_TOP_DEFAULT 0x00000000
+#define mmMC_VM_AGP_BOT_DEFAULT 0x00000000
+#define mmMC_VM_AGP_BASE_DEFAULT 0x00000000
+#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000
+#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000
+#define mmMC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00002501
+
+
+// addressBlock: gc_tcdec
+#define mmTCP_INVALIDATE_DEFAULT 0x00000000
+#define mmTCP_STATUS_DEFAULT 0x00000000
+#define mmTCP_CNTL_DEFAULT 0x2f9c0000
+#define mmTCP_CHAN_STEER_LO_DEFAULT 0x76543210
+#define mmTCP_CHAN_STEER_HI_DEFAULT 0xfedcba98
+#define mmTCP_ADDR_CONFIG_DEFAULT 0x000000ff
+#define mmTCP_CREDIT_DEFAULT 0x804001c0
+#define mmTCP_BUFFER_ADDR_HASH_CNTL_DEFAULT 0x00000000
+#define mmTCP_EDC_CNT_DEFAULT 0x00000000
+#define mmTC_CFG_L1_LOAD_POLICY0_DEFAULT 0x00000000
+#define mmTC_CFG_L1_LOAD_POLICY1_DEFAULT 0x00000000
+#define mmTC_CFG_L1_STORE_POLICY_DEFAULT 0x00000000
+#define mmTC_CFG_L2_LOAD_POLICY0_DEFAULT 0x00000000
+#define mmTC_CFG_L2_LOAD_POLICY1_DEFAULT 0x00000000
+#define mmTC_CFG_L2_STORE_POLICY0_DEFAULT 0x00000000
+#define mmTC_CFG_L2_STORE_POLICY1_DEFAULT 0x00000000
+#define mmTC_CFG_L2_ATOMIC_POLICY_DEFAULT 0x00000000
+#define mmTC_CFG_L1_VOLATILE_DEFAULT 0x00000000
+#define mmTC_CFG_L2_VOLATILE_DEFAULT 0x00000000
+#define mmTCI_STATUS_DEFAULT 0x00000000
+#define mmTCI_CNTL_1_DEFAULT 0x40080022
+#define mmTCI_CNTL_2_DEFAULT 0x00000041
+#define mmTCC_CTRL_DEFAULT 0xf30fff7f
+#define mmTCC_CTRL2_DEFAULT 0x0000000f
+#define mmTCC_EDC_CNT_DEFAULT 0x00000000
+#define mmTCC_EDC_CNT2_DEFAULT 0x00000000
+#define mmTCC_REDUNDANCY_DEFAULT 0x00000000
+#define mmTCC_EXE_DISABLE_DEFAULT 0x00000000
+#define mmTCC_DSM_CNTL_DEFAULT 0x00000000
+#define mmTCC_DSM_CNTLA_DEFAULT 0x00000000
+#define mmTCC_DSM_CNTL2_DEFAULT 0x00000000
+#define mmTCC_DSM_CNTL2A_DEFAULT 0x00000000
+#define mmTCC_DSM_CNTL2B_DEFAULT 0x00000000
+#define mmTCC_WBINVL2_DEFAULT 0x00000010
+#define mmTCC_SOFT_RESET_DEFAULT 0x00000000
+#define mmTCA_CTRL_DEFAULT 0x00000088
+#define mmTCA_BURST_MASK_DEFAULT 0xffffffff
+#define mmTCA_BURST_CTRL_DEFAULT 0x00000007
+#define mmTCA_DSM_CNTL_DEFAULT 0x00000000
+#define mmTCA_DSM_CNTL2_DEFAULT 0x00000000
+#define mmTCA_EDC_CNT_DEFAULT 0x00000000
+
+
+// addressBlock: gc_shdec
+#define mmSPI_SHADER_PGM_RSRC3_PS_DEFAULT 0x0000ffff
+#define mmSPI_SHADER_PGM_LO_PS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_HI_PS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC1_PS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC2_PS_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_0_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_1_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_2_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_3_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_4_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_5_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_6_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_7_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_8_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_9_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_10_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_11_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_12_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_13_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_14_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_15_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_16_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_17_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_18_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_19_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_20_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_21_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_22_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_23_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_24_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_25_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_26_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_27_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_28_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_29_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_30_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_31_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC3_VS_DEFAULT 0x0000ffff
+#define mmSPI_SHADER_LATE_ALLOC_VS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_LO_VS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_HI_VS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC1_VS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC2_VS_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_0_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_1_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_2_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_3_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_4_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_5_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_6_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_7_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_8_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_9_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_10_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_11_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_12_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_13_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_14_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_15_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_16_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_17_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_18_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_19_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_20_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_21_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_22_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_23_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_24_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_25_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_26_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_27_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_28_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_29_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_30_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_31_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC2_GS_VS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC4_GS_DEFAULT 0x00000800
+#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_LO_ES_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_HI_ES_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC3_GS_DEFAULT 0x0000fffe
+#define mmSPI_SHADER_PGM_LO_GS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_HI_GS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC1_GS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC2_GS_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_0_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_1_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_2_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_3_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_4_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_5_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_6_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_7_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_8_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_9_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_10_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_11_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_12_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_13_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_14_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_15_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_16_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_17_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_18_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_19_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_20_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_21_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_22_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_23_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_24_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_25_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_26_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_27_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_28_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_29_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_30_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_31_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC4_HS_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_LO_LS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_HI_LS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC3_HS_DEFAULT 0xffff0000
+#define mmSPI_SHADER_PGM_LO_HS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_HI_HS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC1_HS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC2_HS_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_0_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_1_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_2_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_3_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_4_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_5_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_6_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_7_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_8_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_9_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_10_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_11_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_12_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_13_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_14_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_15_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_16_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_17_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_18_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_19_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_20_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_21_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_22_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_23_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_24_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_25_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_26_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_27_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_28_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_29_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_30_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_31_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_0_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_1_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_2_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_3_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_4_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_5_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_6_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_7_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_8_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_9_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_10_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_11_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_12_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_13_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_14_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_15_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_16_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_17_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_18_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_19_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_20_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_21_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_22_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_23_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_24_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_25_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_26_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_27_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_28_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_29_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_30_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_COMMON_31_DEFAULT 0x00000000
+#define mmCOMPUTE_DISPATCH_INITIATOR_DEFAULT 0x00000000
+#define mmCOMPUTE_DIM_X_DEFAULT 0x00000000
+#define mmCOMPUTE_DIM_Y_DEFAULT 0x00000000
+#define mmCOMPUTE_DIM_Z_DEFAULT 0x00000000
+#define mmCOMPUTE_START_X_DEFAULT 0x00000000
+#define mmCOMPUTE_START_Y_DEFAULT 0x00000000
+#define mmCOMPUTE_START_Z_DEFAULT 0x00000000
+#define mmCOMPUTE_NUM_THREAD_X_DEFAULT 0x00000000
+#define mmCOMPUTE_NUM_THREAD_Y_DEFAULT 0x00000000
+#define mmCOMPUTE_NUM_THREAD_Z_DEFAULT 0x00000000
+#define mmCOMPUTE_PIPELINESTAT_ENABLE_DEFAULT 0x00000001
+#define mmCOMPUTE_PERFCOUNT_ENABLE_DEFAULT 0x00000000
+#define mmCOMPUTE_PGM_LO_DEFAULT 0x00000000
+#define mmCOMPUTE_PGM_HI_DEFAULT 0x00000000
+#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO_DEFAULT 0x00000000
+#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI_DEFAULT 0x00000000
+#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_DEFAULT 0x00000000
+#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_DEFAULT 0x00000000
+#define mmCOMPUTE_PGM_RSRC1_DEFAULT 0x00000000
+#define mmCOMPUTE_PGM_RSRC2_DEFAULT 0x00000000
+#define mmCOMPUTE_VMID_DEFAULT 0x00000000
+#define mmCOMPUTE_RESOURCE_LIMITS_DEFAULT 0x00000000
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0_DEFAULT 0xffffffff
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1_DEFAULT 0xffffffff
+#define mmCOMPUTE_TMPRING_SIZE_DEFAULT 0x00000000
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_DEFAULT 0xffffffff
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_DEFAULT 0xffffffff
+#define mmCOMPUTE_RESTART_X_DEFAULT 0x00000000
+#define mmCOMPUTE_RESTART_Y_DEFAULT 0x00000000
+#define mmCOMPUTE_RESTART_Z_DEFAULT 0x00000000
+#define mmCOMPUTE_THREAD_TRACE_ENABLE_DEFAULT 0x00000000
+#define mmCOMPUTE_MISC_RESERVED_DEFAULT 0x00000002
+#define mmCOMPUTE_DISPATCH_ID_DEFAULT 0x00000000
+#define mmCOMPUTE_THREADGROUP_ID_DEFAULT 0x00000000
+#define mmCOMPUTE_RELAUNCH_DEFAULT 0x00000000
+#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO_DEFAULT 0x00000000
+#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_0_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_1_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_2_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_3_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_4_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_5_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_6_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_7_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_8_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_9_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_10_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_11_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_12_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_13_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_14_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_15_DEFAULT 0x00000000
+#define mmCOMPUTE_NOWHERE_DEFAULT 0x00000000
+
+
+// addressBlock: gc_cppdec
+#define mmCP_DFY_CNTL_DEFAULT 0x00000000
+#define mmCP_DFY_STAT_DEFAULT 0x00000000
+#define mmCP_DFY_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DFY_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_DFY_DATA_0_DEFAULT 0x00000000
+#define mmCP_DFY_DATA_1_DEFAULT 0x00000000
+#define mmCP_DFY_DATA_2_DEFAULT 0x00000000
+#define mmCP_DFY_DATA_3_DEFAULT 0x00000000
+#define mmCP_DFY_DATA_4_DEFAULT 0x00000000
+#define mmCP_DFY_DATA_5_DEFAULT 0x00000000
+#define mmCP_DFY_DATA_6_DEFAULT 0x00000000
+#define mmCP_DFY_DATA_7_DEFAULT 0x00000000
+#define mmCP_DFY_DATA_8_DEFAULT 0x00000000
+#define mmCP_DFY_DATA_9_DEFAULT 0x00000000
+#define mmCP_DFY_DATA_10_DEFAULT 0x00000000
+#define mmCP_DFY_DATA_11_DEFAULT 0x00000000
+#define mmCP_DFY_DATA_12_DEFAULT 0x00000000
+#define mmCP_DFY_DATA_13_DEFAULT 0x00000000
+#define mmCP_DFY_DATA_14_DEFAULT 0x00000000
+#define mmCP_DFY_DATA_15_DEFAULT 0x00000000
+#define mmCP_DFY_CMD_DEFAULT 0x00000000
+#define mmCP_EOPQ_WAIT_TIME_DEFAULT 0x0000052c
+#define mmCP_CPC_MGCG_SYNC_CNTL_DEFAULT 0x00001020
+#define mmCPC_INT_INFO_DEFAULT 0x00000000
+#define mmCP_VIRT_STATUS_DEFAULT 0x00000000
+#define mmCPC_INT_ADDR_DEFAULT 0x00000000
+#define mmCPC_INT_PASID_DEFAULT 0x00000000
+#define mmCP_GFX_ERROR_DEFAULT 0x00000000
+#define mmCPG_UTCL1_CNTL_DEFAULT 0x00000080
+#define mmCPC_UTCL1_CNTL_DEFAULT 0x00000080
+#define mmCPF_UTCL1_CNTL_DEFAULT 0x00000080
+#define mmCP_AQL_SMM_STATUS_DEFAULT 0x00000000
+#define mmCP_RB0_BASE_DEFAULT 0x00000000
+#define mmCP_RB_BASE_DEFAULT 0x00000000
+#define mmCP_RB0_CNTL_DEFAULT 0x00400000
+#define mmCP_RB_CNTL_DEFAULT 0x00400000
+#define mmCP_RB_RPTR_WR_DEFAULT 0x00000000
+#define mmCP_RB0_RPTR_ADDR_DEFAULT 0x00000000
+#define mmCP_RB_RPTR_ADDR_DEFAULT 0x00000000
+#define mmCP_RB0_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_RB0_BUFSZ_MASK_DEFAULT 0x00000000
+#define mmCP_RB_BUFSZ_MASK_DEFAULT 0x00000000
+#define mmCP_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmGC_PRIV_MODE_DEFAULT 0x00000000
+#define mmCP_INT_CNTL_DEFAULT 0x00000000
+#define mmCP_INT_STATUS_DEFAULT 0x00000000
+#define mmCP_DEVICE_ID_DEFAULT 0x00000000
+#define mmCP_ME0_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020
+#define mmCP_RING_PRIORITY_CNTS_DEFAULT 0x08081020
+#define mmCP_ME0_PIPE0_PRIORITY_DEFAULT 0x00000002
+#define mmCP_RING0_PRIORITY_DEFAULT 0x00000002
+#define mmCP_ME0_PIPE1_PRIORITY_DEFAULT 0x00000002
+#define mmCP_RING1_PRIORITY_DEFAULT 0x00000002
+#define mmCP_ME0_PIPE2_PRIORITY_DEFAULT 0x00000002
+#define mmCP_RING2_PRIORITY_DEFAULT 0x00000002
+#define mmCP_FATAL_ERROR_DEFAULT 0x00000000
+#define mmCP_RB_VMID_DEFAULT 0x00000000
+#define mmCP_ME0_PIPE0_VMID_DEFAULT 0x00000000
+#define mmCP_ME0_PIPE1_VMID_DEFAULT 0x00000000
+#define mmCP_RB0_WPTR_DEFAULT 0x00000000
+#define mmCP_RB_WPTR_DEFAULT 0x00000000
+#define mmCP_RB0_WPTR_HI_DEFAULT 0x00000000
+#define mmCP_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmCP_RB1_WPTR_DEFAULT 0x00000000
+#define mmCP_RB1_WPTR_HI_DEFAULT 0x00000000
+#define mmCP_RB2_WPTR_DEFAULT 0x00000000
+#define mmCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000
+#define mmCP_RB_DOORBELL_RANGE_LOWER_DEFAULT 0x00000000
+#define mmCP_RB_DOORBELL_RANGE_UPPER_DEFAULT 0x00000044
+#define mmCP_MEC_DOORBELL_RANGE_LOWER_DEFAULT 0x00000048
+#define mmCP_MEC_DOORBELL_RANGE_UPPER_DEFAULT 0x0ffffffc
+#define mmCPG_UTCL1_ERROR_DEFAULT 0x00000000
+#define mmCPC_UTCL1_ERROR_DEFAULT 0x00000000
+#define mmCP_RB1_BASE_DEFAULT 0x00000000
+#define mmCP_RB1_CNTL_DEFAULT 0x00400000
+#define mmCP_RB1_RPTR_ADDR_DEFAULT 0x00000000
+#define mmCP_RB1_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_RB2_BASE_DEFAULT 0x00000000
+#define mmCP_RB2_CNTL_DEFAULT 0x00400000
+#define mmCP_RB2_RPTR_ADDR_DEFAULT 0x00000000
+#define mmCP_RB2_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_RB0_ACTIVE_DEFAULT 0x00000001
+#define mmCP_RB_ACTIVE_DEFAULT 0x00000001
+#define mmCP_INT_CNTL_RING0_DEFAULT 0x00000000
+#define mmCP_INT_CNTL_RING1_DEFAULT 0x00000000
+#define mmCP_INT_CNTL_RING2_DEFAULT 0x00000000
+#define mmCP_INT_STATUS_RING0_DEFAULT 0x00000000
+#define mmCP_INT_STATUS_RING1_DEFAULT 0x00000000
+#define mmCP_INT_STATUS_RING2_DEFAULT 0x00000000
+#define mmCP_PWR_CNTL_DEFAULT 0x00000000
+#define mmCP_MEM_SLP_CNTL_DEFAULT 0x00020200
+#define mmCP_ECC_FIRSTOCCURRENCE_DEFAULT 0x00000000
+#define mmCP_ECC_FIRSTOCCURRENCE_RING0_DEFAULT 0x00000000
+#define mmCP_ECC_FIRSTOCCURRENCE_RING1_DEFAULT 0x00000000
+#define mmCP_ECC_FIRSTOCCURRENCE_RING2_DEFAULT 0x00000000
+#define mmGB_EDC_MODE_DEFAULT 0x00000000
+#define mmCP_PQ_WPTR_POLL_CNTL_DEFAULT 0x00000001
+#define mmCP_PQ_WPTR_POLL_CNTL1_DEFAULT 0x00000000
+#define mmCP_ME1_PIPE0_INT_CNTL_DEFAULT 0x00000000
+#define mmCP_ME1_PIPE1_INT_CNTL_DEFAULT 0x00000000
+#define mmCP_ME1_PIPE2_INT_CNTL_DEFAULT 0x00000000
+#define mmCP_ME1_PIPE3_INT_CNTL_DEFAULT 0x00000000
+#define mmCP_ME2_PIPE0_INT_CNTL_DEFAULT 0x00000000
+#define mmCP_ME2_PIPE1_INT_CNTL_DEFAULT 0x00000000
+#define mmCP_ME2_PIPE2_INT_CNTL_DEFAULT 0x00000000
+#define mmCP_ME2_PIPE3_INT_CNTL_DEFAULT 0x00000000
+#define mmCP_ME1_PIPE0_INT_STATUS_DEFAULT 0x00000000
+#define mmCP_ME1_PIPE1_INT_STATUS_DEFAULT 0x00000000
+#define mmCP_ME1_PIPE2_INT_STATUS_DEFAULT 0x00000000
+#define mmCP_ME1_PIPE3_INT_STATUS_DEFAULT 0x00000000
+#define mmCP_ME2_PIPE0_INT_STATUS_DEFAULT 0x00000000
+#define mmCP_ME2_PIPE1_INT_STATUS_DEFAULT 0x00000000
+#define mmCP_ME2_PIPE2_INT_STATUS_DEFAULT 0x00000000
+#define mmCP_ME2_PIPE3_INT_STATUS_DEFAULT 0x00000000
+#define mmCP_ME1_INT_STAT_DEBUG_DEFAULT 0x00000000
+#define mmCP_ME2_INT_STAT_DEBUG_DEFAULT 0x00000000
+#define mmCC_GC_EDC_CONFIG_DEFAULT 0x00000000
+#define mmCP_ME1_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020
+#define mmCP_ME1_PIPE0_PRIORITY_DEFAULT 0x00000002
+#define mmCP_ME1_PIPE1_PRIORITY_DEFAULT 0x00000002
+#define mmCP_ME1_PIPE2_PRIORITY_DEFAULT 0x00000002
+#define mmCP_ME1_PIPE3_PRIORITY_DEFAULT 0x00000002
+#define mmCP_ME2_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020
+#define mmCP_ME2_PIPE0_PRIORITY_DEFAULT 0x00000002
+#define mmCP_ME2_PIPE1_PRIORITY_DEFAULT 0x00000002
+#define mmCP_ME2_PIPE2_PRIORITY_DEFAULT 0x00000002
+#define mmCP_ME2_PIPE3_PRIORITY_DEFAULT 0x00000002
+#define mmCP_CE_PRGRM_CNTR_START_DEFAULT 0x00000000
+#define mmCP_PFP_PRGRM_CNTR_START_DEFAULT 0x00000000
+#define mmCP_ME_PRGRM_CNTR_START_DEFAULT 0x00000000
+#define mmCP_MEC1_PRGRM_CNTR_START_DEFAULT 0x00000000
+#define mmCP_MEC2_PRGRM_CNTR_START_DEFAULT 0x00000000
+#define mmCP_CE_INTR_ROUTINE_START_DEFAULT 0x00000002
+#define mmCP_PFP_INTR_ROUTINE_START_DEFAULT 0x00000002
+#define mmCP_ME_INTR_ROUTINE_START_DEFAULT 0x00000002
+#define mmCP_MEC1_INTR_ROUTINE_START_DEFAULT 0x00000002
+#define mmCP_MEC2_INTR_ROUTINE_START_DEFAULT 0x00000002
+#define mmCP_CONTEXT_CNTL_DEFAULT 0x00750075
+#define mmCP_MAX_CONTEXT_DEFAULT 0x00000007
+#define mmCP_IQ_WAIT_TIME1_DEFAULT 0x40404040
+#define mmCP_IQ_WAIT_TIME2_DEFAULT 0x40404040
+#define mmCP_RB0_BASE_HI_DEFAULT 0x00000000
+#define mmCP_RB1_BASE_HI_DEFAULT 0x00000000
+#define mmCP_VMID_RESET_DEFAULT 0x00000000
+#define mmCPC_INT_CNTL_DEFAULT 0x00000000
+#define mmCPC_INT_STATUS_DEFAULT 0x00000000
+#define mmCP_VMID_PREEMPT_DEFAULT 0x00000000
+#define mmCPC_INT_CNTX_ID_DEFAULT 0x00000000
+#define mmCP_PQ_STATUS_DEFAULT 0x00000000
+#define mmCP_CPC_IC_BASE_LO_DEFAULT 0x00000000
+#define mmCP_CPC_IC_BASE_HI_DEFAULT 0x00000000
+#define mmCP_CPC_IC_BASE_CNTL_DEFAULT 0x00000000
+#define mmCP_CPC_IC_OP_CNTL_DEFAULT 0x00000000
+#define mmCP_MEC1_F32_INT_DIS_DEFAULT 0x00000000
+#define mmCP_MEC2_F32_INT_DIS_DEFAULT 0x00000000
+#define mmCP_VMID_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: gc_cppdec2
+#define mmCP_RB_DOORBELL_CONTROL_SCH_0_DEFAULT 0x00000000
+#define mmCP_RB_DOORBELL_CONTROL_SCH_1_DEFAULT 0x00000000
+#define mmCP_RB_DOORBELL_CONTROL_SCH_2_DEFAULT 0x00000000
+#define mmCP_RB_DOORBELL_CONTROL_SCH_3_DEFAULT 0x00000000
+#define mmCP_RB_DOORBELL_CONTROL_SCH_4_DEFAULT 0x00000000
+#define mmCP_RB_DOORBELL_CONTROL_SCH_5_DEFAULT 0x00000000
+#define mmCP_RB_DOORBELL_CONTROL_SCH_6_DEFAULT 0x00000000
+#define mmCP_RB_DOORBELL_CONTROL_SCH_7_DEFAULT 0x00000000
+#define mmCP_RB_DOORBELL_CLEAR_DEFAULT 0x00000000
+#define mmCP_GFX_MQD_CONTROL_DEFAULT 0x00000100
+#define mmCP_GFX_MQD_BASE_ADDR_DEFAULT 0x00000000
+#define mmCP_GFX_MQD_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_RB_STATUS_DEFAULT 0x00000000
+#define mmCPG_UTCL1_STATUS_DEFAULT 0x00000000
+#define mmCPC_UTCL1_STATUS_DEFAULT 0x00000000
+#define mmCPF_UTCL1_STATUS_DEFAULT 0x00000000
+#define mmCP_SD_CNTL_DEFAULT 0x0000001f
+#define mmCP_SOFT_RESET_CNTL_DEFAULT 0x00000000
+#define mmCP_CPC_GFX_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: gc_spipdec
+#define mmSPI_ARB_PRIORITY_DEFAULT 0x00000000
+#define mmSPI_ARB_CYCLES_0_DEFAULT 0x00000000
+#define mmSPI_ARB_CYCLES_1_DEFAULT 0x00000000
+#define mmSPI_CDBG_SYS_GFX_DEFAULT 0x00000000
+#define mmSPI_CDBG_SYS_HP3D_DEFAULT 0x00000000
+#define mmSPI_CDBG_SYS_CS0_DEFAULT 0x00000000
+#define mmSPI_CDBG_SYS_CS1_DEFAULT 0x00000000
+#define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT 0x07ffffff
+#define mmSPI_WCL_PIPE_PERCENT_HP3D_DEFAULT 0x07c1f07f
+#define mmSPI_WCL_PIPE_PERCENT_CS0_DEFAULT 0x0000007f
+#define mmSPI_WCL_PIPE_PERCENT_CS1_DEFAULT 0x0000007f
+#define mmSPI_WCL_PIPE_PERCENT_CS2_DEFAULT 0x0000007f
+#define mmSPI_WCL_PIPE_PERCENT_CS3_DEFAULT 0x0000007f
+#define mmSPI_WCL_PIPE_PERCENT_CS4_DEFAULT 0x0000007f
+#define mmSPI_WCL_PIPE_PERCENT_CS5_DEFAULT 0x0000007f
+#define mmSPI_WCL_PIPE_PERCENT_CS6_DEFAULT 0x0000007f
+#define mmSPI_WCL_PIPE_PERCENT_CS7_DEFAULT 0x0000007f
+#define mmSPI_GDBG_WAVE_CNTL_DEFAULT 0x00000000
+#define mmSPI_GDBG_TRAP_CONFIG_DEFAULT 0x00000000
+#define mmSPI_GDBG_TRAP_MASK_DEFAULT 0x00000000
+#define mmSPI_GDBG_WAVE_CNTL2_DEFAULT 0x00000000
+#define mmSPI_GDBG_WAVE_CNTL3_DEFAULT 0x00000000
+#define mmSPI_GDBG_TRAP_DATA0_DEFAULT 0x00000000
+#define mmSPI_GDBG_TRAP_DATA1_DEFAULT 0x00000000
+#define mmSPI_RESET_DEBUG_DEFAULT 0x00000000
+#define mmSPI_COMPUTE_QUEUE_RESET_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_0_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_1_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_2_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_3_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_4_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_5_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_6_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_7_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_8_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_9_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_0_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_1_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_2_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_3_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_4_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_5_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_6_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_7_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_8_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_9_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_10_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_11_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_10_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_11_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_12_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_13_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_14_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_15_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_12_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_13_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_14_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_15_DEFAULT 0x00000000
+#define mmSPI_COMPUTE_WF_CTX_SAVE_DEFAULT 0x00000000
+#define mmSPI_ARB_CNTL_0_DEFAULT 0x00000000
+
+
+// addressBlock: gc_cpphqddec
+#define mmCP_HQD_GFX_CONTROL_DEFAULT 0x00000000
+#define mmCP_HQD_GFX_STATUS_DEFAULT 0x00000000
+#define mmCP_HPD_ROQ_OFFSETS_DEFAULT 0x00200604
+#define mmCP_HPD_STATUS0_DEFAULT 0x01000000
+#define mmCP_HPD_UTCL1_CNTL_DEFAULT 0x00000000
+#define mmCP_HPD_UTCL1_ERROR_DEFAULT 0x00000000
+#define mmCP_HPD_UTCL1_ERROR_ADDR_DEFAULT 0x00000000
+#define mmCP_MQD_BASE_ADDR_DEFAULT 0x00000000
+#define mmCP_MQD_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_HQD_ACTIVE_DEFAULT 0x00000000
+#define mmCP_HQD_VMID_DEFAULT 0x00000000
+#define mmCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05301
+#define mmCP_HQD_PIPE_PRIORITY_DEFAULT 0x00000000
+#define mmCP_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000
+#define mmCP_HQD_QUANTUM_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_BASE_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_BASE_HI_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_RPTR_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_WPTR_POLL_ADDR_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_CONTROL_DEFAULT 0x00308509
+#define mmCP_HQD_IB_BASE_ADDR_DEFAULT 0x00000000
+#define mmCP_HQD_IB_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_HQD_IB_RPTR_DEFAULT 0x00000000
+#define mmCP_HQD_IB_CONTROL_DEFAULT 0x00300000
+#define mmCP_HQD_IQ_TIMER_DEFAULT 0x00000000
+#define mmCP_HQD_IQ_RPTR_DEFAULT 0x00000000
+#define mmCP_HQD_DEQUEUE_REQUEST_DEFAULT 0x00000000
+#define mmCP_HQD_DMA_OFFLOAD_DEFAULT 0x00000000
+#define mmCP_HQD_OFFLOAD_DEFAULT 0x00000000
+#define mmCP_HQD_SEMA_CMD_DEFAULT 0x00000000
+#define mmCP_HQD_MSG_TYPE_DEFAULT 0x00000000
+#define mmCP_HQD_ATOMIC0_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_HQD_ATOMIC0_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_HQD_ATOMIC1_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_HQD_ATOMIC1_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_HQD_HQ_SCHEDULER0_DEFAULT 0x00000000
+#define mmCP_HQD_HQ_STATUS0_DEFAULT 0x40000000
+#define mmCP_HQD_HQ_CONTROL0_DEFAULT 0x00000000
+#define mmCP_HQD_HQ_SCHEDULER1_DEFAULT 0x00000000
+#define mmCP_MQD_CONTROL_DEFAULT 0x00000100
+#define mmCP_HQD_HQ_STATUS1_DEFAULT 0x00000000
+#define mmCP_HQD_HQ_CONTROL1_DEFAULT 0x00000000
+#define mmCP_HQD_EOP_BASE_ADDR_DEFAULT 0x00000000
+#define mmCP_HQD_EOP_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_HQD_EOP_CONTROL_DEFAULT 0x00000006
+#define mmCP_HQD_EOP_RPTR_DEFAULT 0x40000000
+#define mmCP_HQD_EOP_WPTR_DEFAULT 0x007f8000
+#define mmCP_HQD_EOP_EVENTS_DEFAULT 0x00000000
+#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_HQD_CTX_SAVE_CONTROL_DEFAULT 0x00000000
+#define mmCP_HQD_CNTL_STACK_OFFSET_DEFAULT 0x00000000
+#define mmCP_HQD_CNTL_STACK_SIZE_DEFAULT 0x00000000
+#define mmCP_HQD_WG_STATE_OFFSET_DEFAULT 0x00000000
+#define mmCP_HQD_CTX_SAVE_SIZE_DEFAULT 0x00000000
+#define mmCP_HQD_GDS_RESOURCE_STATE_DEFAULT 0x00000000
+#define mmCP_HQD_ERROR_DEFAULT 0x00000000
+#define mmCP_HQD_EOP_WPTR_MEM_DEFAULT 0x00000000
+#define mmCP_HQD_AQL_CONTROL_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_WPTR_LO_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_WPTR_HI_DEFAULT 0x00000000
+
+
+// addressBlock: gc_didtdec
+#define mmDIDT_IND_INDEX_DEFAULT 0x00000000
+#define mmDIDT_IND_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gccacdec
+#define mmGC_CAC_CTRL_1_DEFAULT 0x01000000
+#define mmGC_CAC_CTRL_2_DEFAULT 0x00000000
+#define mmGC_CAC_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmGC_CAC_AGGR_LOWER_DEFAULT 0x00000000
+#define mmGC_CAC_AGGR_UPPER_DEFAULT 0x00000000
+#define mmGC_CAC_SOFT_CTRL_DEFAULT 0x00000000
+#define mmGC_DIDT_CTRL0_DEFAULT 0x00000000
+#define mmGC_DIDT_CTRL1_DEFAULT 0xffff0000
+#define mmGC_DIDT_CTRL2_DEFAULT 0x1880000f
+#define mmGC_DIDT_WEIGHT_DEFAULT 0x00000000
+#define mmGC_DIDT_WEIGHT_1_DEFAULT 0x00000000
+#define mmGC_EDC_CTRL_DEFAULT 0x00000000
+#define mmGC_EDC_THRESHOLD_DEFAULT 0x00000000
+#define mmGC_EDC_STATUS_DEFAULT 0x00000000
+#define mmGC_EDC_OVERFLOW_DEFAULT 0x00000000
+#define mmGC_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
+#define mmGC_DIDT_DROOP_CTRL_DEFAULT 0x00000000
+#define mmGC_EDC_DROOP_CTRL_DEFAULT 0x00100000
+#define mmGC_CAC_IND_INDEX_DEFAULT 0x00000000
+#define mmGC_CAC_IND_DATA_DEFAULT 0x00000000
+#define mmSE_CAC_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmSE_CAC_IND_INDEX_DEFAULT 0x00000000
+#define mmSE_CAC_IND_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: gc_tcpdec
+#define mmTCP_WATCH0_ADDR_H_DEFAULT 0x00000000
+#define mmTCP_WATCH0_ADDR_L_DEFAULT 0x00000000
+#define mmTCP_WATCH0_CNTL_DEFAULT 0x00000000
+#define mmTCP_WATCH1_ADDR_H_DEFAULT 0x00000000
+#define mmTCP_WATCH1_ADDR_L_DEFAULT 0x00000000
+#define mmTCP_WATCH1_CNTL_DEFAULT 0x00000000
+#define mmTCP_WATCH2_ADDR_H_DEFAULT 0x00000000
+#define mmTCP_WATCH2_ADDR_L_DEFAULT 0x00000000
+#define mmTCP_WATCH2_CNTL_DEFAULT 0x00000000
+#define mmTCP_WATCH3_ADDR_H_DEFAULT 0x00000000
+#define mmTCP_WATCH3_ADDR_L_DEFAULT 0x00000000
+#define mmTCP_WATCH3_CNTL_DEFAULT 0x00000000
+#define mmTCP_GATCL1_CNTL_DEFAULT 0x00000000
+#define mmTCP_ATC_EDC_GATCL1_CNT_DEFAULT 0x00000000
+#define mmTCP_GATCL1_DSM_CNTL_DEFAULT 0x00000000
+#define mmTCP_CNTL2_DEFAULT 0x0000000a
+#define mmTCP_UTCL1_CNTL1_DEFAULT 0x00800400
+#define mmTCP_UTCL1_CNTL2_DEFAULT 0x00000000
+#define mmTCP_UTCL1_STATUS_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER_FILTER_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER_FILTER_EN_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gdspdec
+#define mmGDS_VMID0_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID0_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID1_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID1_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID2_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID2_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID3_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID3_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID4_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID4_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID5_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID5_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID6_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID6_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID7_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID7_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID8_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID8_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID9_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID9_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID10_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID10_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID11_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID11_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID12_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID12_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID13_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID13_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID14_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID14_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID15_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID15_SIZE_DEFAULT 0x00010000
+#define mmGDS_GWS_VMID0_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID1_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID2_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID3_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID4_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID5_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID6_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID7_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID8_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID9_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID10_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID11_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID12_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID13_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID14_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID15_DEFAULT 0x00400000
+#define mmGDS_OA_VMID0_DEFAULT 0x00000000
+#define mmGDS_OA_VMID1_DEFAULT 0x00000000
+#define mmGDS_OA_VMID2_DEFAULT 0x00000000
+#define mmGDS_OA_VMID3_DEFAULT 0x00000000
+#define mmGDS_OA_VMID4_DEFAULT 0x00000000
+#define mmGDS_OA_VMID5_DEFAULT 0x00000000
+#define mmGDS_OA_VMID6_DEFAULT 0x00000000
+#define mmGDS_OA_VMID7_DEFAULT 0x00000000
+#define mmGDS_OA_VMID8_DEFAULT 0x00000000
+#define mmGDS_OA_VMID9_DEFAULT 0x00000000
+#define mmGDS_OA_VMID10_DEFAULT 0x00000000
+#define mmGDS_OA_VMID11_DEFAULT 0x00000000
+#define mmGDS_OA_VMID12_DEFAULT 0x00000000
+#define mmGDS_OA_VMID13_DEFAULT 0x00000000
+#define mmGDS_OA_VMID14_DEFAULT 0x00000000
+#define mmGDS_OA_VMID15_DEFAULT 0x00000000
+#define mmGDS_GWS_RESET0_DEFAULT 0x00000000
+#define mmGDS_GWS_RESET1_DEFAULT 0x00000000
+#define mmGDS_GWS_RESOURCE_RESET_DEFAULT 0x00000000
+#define mmGDS_COMPUTE_MAX_WAVE_ID_DEFAULT 0x000007ff
+#define mmGDS_OA_RESET_MASK_DEFAULT 0x00000000
+#define mmGDS_OA_RESET_DEFAULT 0x00000000
+#define mmGDS_ENHANCE_DEFAULT 0x00000000
+#define mmGDS_OA_CGPG_RESTORE_DEFAULT 0x00000000
+#define mmGDS_CS_CTXSW_STATUS_DEFAULT 0x00000000
+#define mmGDS_CS_CTXSW_CNT0_DEFAULT 0x00000000
+#define mmGDS_CS_CTXSW_CNT1_DEFAULT 0x00000000
+#define mmGDS_CS_CTXSW_CNT2_DEFAULT 0x00000000
+#define mmGDS_CS_CTXSW_CNT3_DEFAULT 0x00000000
+#define mmGDS_GFX_CTXSW_STATUS_DEFAULT 0x00000000
+#define mmGDS_VS_CTXSW_CNT0_DEFAULT 0x00000000
+#define mmGDS_VS_CTXSW_CNT1_DEFAULT 0x00000000
+#define mmGDS_VS_CTXSW_CNT2_DEFAULT 0x00000000
+#define mmGDS_VS_CTXSW_CNT3_DEFAULT 0x00000000
+#define mmGDS_PS0_CTXSW_CNT0_DEFAULT 0x00000000
+#define mmGDS_PS0_CTXSW_CNT1_DEFAULT 0x00000000
+#define mmGDS_PS0_CTXSW_CNT2_DEFAULT 0x00000000
+#define mmGDS_PS0_CTXSW_CNT3_DEFAULT 0x00000000
+#define mmGDS_PS1_CTXSW_CNT0_DEFAULT 0x00000000
+#define mmGDS_PS1_CTXSW_CNT1_DEFAULT 0x00000000
+#define mmGDS_PS1_CTXSW_CNT2_DEFAULT 0x00000000
+#define mmGDS_PS1_CTXSW_CNT3_DEFAULT 0x00000000
+#define mmGDS_PS2_CTXSW_CNT0_DEFAULT 0x00000000
+#define mmGDS_PS2_CTXSW_CNT1_DEFAULT 0x00000000
+#define mmGDS_PS2_CTXSW_CNT2_DEFAULT 0x00000000
+#define mmGDS_PS2_CTXSW_CNT3_DEFAULT 0x00000000
+#define mmGDS_PS3_CTXSW_CNT0_DEFAULT 0x00000000
+#define mmGDS_PS3_CTXSW_CNT1_DEFAULT 0x00000000
+#define mmGDS_PS3_CTXSW_CNT2_DEFAULT 0x00000000
+#define mmGDS_PS3_CTXSW_CNT3_DEFAULT 0x00000000
+#define mmGDS_PS4_CTXSW_CNT0_DEFAULT 0x00000000
+#define mmGDS_PS4_CTXSW_CNT1_DEFAULT 0x00000000
+#define mmGDS_PS4_CTXSW_CNT2_DEFAULT 0x00000000
+#define mmGDS_PS4_CTXSW_CNT3_DEFAULT 0x00000000
+#define mmGDS_PS5_CTXSW_CNT0_DEFAULT 0x00000000
+#define mmGDS_PS5_CTXSW_CNT1_DEFAULT 0x00000000
+#define mmGDS_PS5_CTXSW_CNT2_DEFAULT 0x00000000
+#define mmGDS_PS5_CTXSW_CNT3_DEFAULT 0x00000000
+#define mmGDS_PS6_CTXSW_CNT0_DEFAULT 0x00000000
+#define mmGDS_PS6_CTXSW_CNT1_DEFAULT 0x00000000
+#define mmGDS_PS6_CTXSW_CNT2_DEFAULT 0x00000000
+#define mmGDS_PS6_CTXSW_CNT3_DEFAULT 0x00000000
+#define mmGDS_PS7_CTXSW_CNT0_DEFAULT 0x00000000
+#define mmGDS_PS7_CTXSW_CNT1_DEFAULT 0x00000000
+#define mmGDS_PS7_CTXSW_CNT2_DEFAULT 0x00000000
+#define mmGDS_PS7_CTXSW_CNT3_DEFAULT 0x00000000
+#define mmGDS_GS_CTXSW_CNT0_DEFAULT 0x00000000
+#define mmGDS_GS_CTXSW_CNT1_DEFAULT 0x00000000
+#define mmGDS_GS_CTXSW_CNT2_DEFAULT 0x00000000
+#define mmGDS_GS_CTXSW_CNT3_DEFAULT 0x00000000
+
+
+// addressBlock: gc_rasdec
+#define mmRAS_SIGNATURE_CONTROL_DEFAULT 0x00000000
+#define mmRAS_SIGNATURE_MASK_DEFAULT 0x00000000
+#define mmRAS_SX_SIGNATURE0_DEFAULT 0x00000000
+#define mmRAS_SX_SIGNATURE1_DEFAULT 0x00000000
+#define mmRAS_SX_SIGNATURE2_DEFAULT 0x00000000
+#define mmRAS_SX_SIGNATURE3_DEFAULT 0x00000000
+#define mmRAS_DB_SIGNATURE0_DEFAULT 0x00000000
+#define mmRAS_PA_SIGNATURE0_DEFAULT 0x00000000
+#define mmRAS_VGT_SIGNATURE0_DEFAULT 0x00000000
+#define mmRAS_SQ_SIGNATURE0_DEFAULT 0x00000000
+#define mmRAS_SC_SIGNATURE0_DEFAULT 0x00000000
+#define mmRAS_SC_SIGNATURE1_DEFAULT 0x00000000
+#define mmRAS_SC_SIGNATURE2_DEFAULT 0x00000000
+#define mmRAS_SC_SIGNATURE3_DEFAULT 0x00000000
+#define mmRAS_SC_SIGNATURE4_DEFAULT 0x00000000
+#define mmRAS_SC_SIGNATURE5_DEFAULT 0x00000000
+#define mmRAS_SC_SIGNATURE6_DEFAULT 0x00000000
+#define mmRAS_SC_SIGNATURE7_DEFAULT 0x00000000
+#define mmRAS_IA_SIGNATURE0_DEFAULT 0x00000000
+#define mmRAS_IA_SIGNATURE1_DEFAULT 0x00000000
+#define mmRAS_SPI_SIGNATURE0_DEFAULT 0x00000000
+#define mmRAS_SPI_SIGNATURE1_DEFAULT 0x00000000
+#define mmRAS_TA_SIGNATURE0_DEFAULT 0x00000000
+#define mmRAS_TD_SIGNATURE0_DEFAULT 0x00000000
+#define mmRAS_CB_SIGNATURE0_DEFAULT 0x00000000
+#define mmRAS_BCI_SIGNATURE0_DEFAULT 0x00000000
+#define mmRAS_BCI_SIGNATURE1_DEFAULT 0x00000000
+#define mmRAS_TA_SIGNATURE1_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gfxdec0
+#define mmDB_RENDER_CONTROL_DEFAULT 0x00000000
+#define mmDB_COUNT_CONTROL_DEFAULT 0x00000000
+#define mmDB_DEPTH_VIEW_DEFAULT 0x00000000
+#define mmDB_RENDER_OVERRIDE_DEFAULT 0x00000000
+#define mmDB_RENDER_OVERRIDE2_DEFAULT 0x00000000
+#define mmDB_HTILE_DATA_BASE_DEFAULT 0x00000000
+#define mmDB_HTILE_DATA_BASE_HI_DEFAULT 0x00000000
+#define mmDB_DEPTH_SIZE_DEFAULT 0x00000000
+#define mmDB_DEPTH_BOUNDS_MIN_DEFAULT 0x00000000
+#define mmDB_DEPTH_BOUNDS_MAX_DEFAULT 0x00000000
+#define mmDB_STENCIL_CLEAR_DEFAULT 0x00000000
+#define mmDB_DEPTH_CLEAR_DEFAULT 0x00000000
+#define mmPA_SC_SCREEN_SCISSOR_TL_DEFAULT 0x00000000
+#define mmPA_SC_SCREEN_SCISSOR_BR_DEFAULT 0x00000000
+#define mmDB_Z_INFO_DEFAULT 0x00000000
+#define mmDB_STENCIL_INFO_DEFAULT 0x00000000
+#define mmDB_Z_READ_BASE_DEFAULT 0x00000000
+#define mmDB_Z_READ_BASE_HI_DEFAULT 0x00000000
+#define mmDB_STENCIL_READ_BASE_DEFAULT 0x00000000
+#define mmDB_STENCIL_READ_BASE_HI_DEFAULT 0x00000000
+#define mmDB_Z_WRITE_BASE_DEFAULT 0x00000000
+#define mmDB_Z_WRITE_BASE_HI_DEFAULT 0x00000000
+#define mmDB_STENCIL_WRITE_BASE_DEFAULT 0x00000000
+#define mmDB_STENCIL_WRITE_BASE_HI_DEFAULT 0x00000000
+#define mmDB_DFSM_CONTROL_DEFAULT 0x00000000
+#define mmDB_RENDER_FILTER_DEFAULT 0x00000000
+#define mmDB_Z_INFO2_DEFAULT 0x00000000
+#define mmDB_STENCIL_INFO2_DEFAULT 0x00000000
+#define mmTA_BC_BASE_ADDR_DEFAULT 0x00000000
+#define mmTA_BC_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmCOHER_DEST_BASE_HI_0_DEFAULT 0x00000000
+#define mmCOHER_DEST_BASE_HI_1_DEFAULT 0x00000000
+#define mmCOHER_DEST_BASE_HI_2_DEFAULT 0x00000000
+#define mmCOHER_DEST_BASE_HI_3_DEFAULT 0x00000000
+#define mmCOHER_DEST_BASE_2_DEFAULT 0x00000000
+#define mmCOHER_DEST_BASE_3_DEFAULT 0x00000000
+#define mmPA_SC_WINDOW_OFFSET_DEFAULT 0x00000000
+#define mmPA_SC_WINDOW_SCISSOR_TL_DEFAULT 0x00000000
+#define mmPA_SC_WINDOW_SCISSOR_BR_DEFAULT 0x00000000
+#define mmPA_SC_CLIPRECT_RULE_DEFAULT 0x00000000
+#define mmPA_SC_CLIPRECT_0_TL_DEFAULT 0x00000000
+#define mmPA_SC_CLIPRECT_0_BR_DEFAULT 0x00000000
+#define mmPA_SC_CLIPRECT_1_TL_DEFAULT 0x00000000
+#define mmPA_SC_CLIPRECT_1_BR_DEFAULT 0x00000000
+#define mmPA_SC_CLIPRECT_2_TL_DEFAULT 0x00000000
+#define mmPA_SC_CLIPRECT_2_BR_DEFAULT 0x00000000
+#define mmPA_SC_CLIPRECT_3_TL_DEFAULT 0x00000000
+#define mmPA_SC_CLIPRECT_3_BR_DEFAULT 0x00000000
+#define mmPA_SC_EDGERULE_DEFAULT 0x00000000
+#define mmPA_SU_HARDWARE_SCREEN_OFFSET_DEFAULT 0x00000000
+#define mmCB_TARGET_MASK_DEFAULT 0x00000000
+#define mmCB_SHADER_MASK_DEFAULT 0x00000000
+#define mmPA_SC_GENERIC_SCISSOR_TL_DEFAULT 0x00000000
+#define mmPA_SC_GENERIC_SCISSOR_BR_DEFAULT 0x00000000
+#define mmCOHER_DEST_BASE_0_DEFAULT 0x00000000
+#define mmCOHER_DEST_BASE_1_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_0_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_0_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_1_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_1_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_2_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_2_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_3_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_3_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_4_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_4_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_5_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_5_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_6_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_6_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_7_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_7_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_8_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_8_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_9_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_9_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_10_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_10_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_11_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_11_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_12_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_12_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_13_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_13_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_14_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_14_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_15_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_15_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_0_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_0_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_1_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_1_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_2_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_2_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_3_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_3_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_4_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_4_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_5_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_5_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_6_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_6_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_7_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_7_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_8_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_8_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_9_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_9_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_10_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_10_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_11_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_11_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_12_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_12_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_13_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_13_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_14_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_14_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_15_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_15_DEFAULT 0x00000000
+#define mmPA_SC_RASTER_CONFIG_DEFAULT 0x00000000
+#define mmPA_SC_RASTER_CONFIG_1_DEFAULT 0x00000000
+#define mmPA_SC_SCREEN_EXTENT_CONTROL_DEFAULT 0x00000000
+#define mmPA_SC_TILE_STEERING_OVERRIDE_DEFAULT 0x00000000
+#define mmCP_PERFMON_CNTX_CNTL_DEFAULT 0x00000000
+#define mmCP_PIPEID_DEFAULT 0x00000000
+#define mmCP_RINGID_DEFAULT 0x00000000
+#define mmCP_VMID_DEFAULT 0x00000000
+#define mmPA_SC_RIGHT_VERT_GRID_DEFAULT 0x00000000
+#define mmPA_SC_LEFT_VERT_GRID_DEFAULT 0x00000000
+#define mmPA_SC_HORIZ_GRID_DEFAULT 0x00000000
+#define mmPA_SC_FOV_WINDOW_LR_DEFAULT 0x00000000
+#define mmPA_SC_FOV_WINDOW_TB_DEFAULT 0x00000000
+#define mmVGT_MULTI_PRIM_IB_RESET_INDX_DEFAULT 0x00000000
+#define mmCB_BLEND_RED_DEFAULT 0x00000000
+#define mmCB_BLEND_GREEN_DEFAULT 0x00000000
+#define mmCB_BLEND_BLUE_DEFAULT 0x00000000
+#define mmCB_BLEND_ALPHA_DEFAULT 0x00000000
+#define mmCB_DCC_CONTROL_DEFAULT 0x00000000
+#define mmDB_STENCIL_CONTROL_DEFAULT 0x00000000
+#define mmDB_STENCILREFMASK_DEFAULT 0x00000000
+#define mmDB_STENCILREFMASK_BF_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_1_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_1_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_1_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_1_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_1_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_1_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_2_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_2_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_2_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_2_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_2_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_2_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_3_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_3_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_3_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_3_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_3_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_3_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_4_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_4_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_4_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_4_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_4_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_4_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_5_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_5_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_5_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_5_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_5_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_5_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_6_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_6_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_6_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_6_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_6_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_6_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_7_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_7_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_7_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_7_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_7_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_7_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_8_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_8_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_8_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_8_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_8_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_8_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_9_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_9_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_9_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_9_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_9_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_9_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_10_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_10_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_10_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_10_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_10_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_10_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_11_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_11_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_11_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_11_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_11_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_11_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_12_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_12_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_12_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_12_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_12_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_12_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_13_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_13_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_13_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_13_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_13_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_13_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_14_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_14_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_14_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_14_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_14_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_14_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_15_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_15_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_15_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_15_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_15_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_15_DEFAULT 0x00000000
+#define mmPA_CL_UCP_0_X_DEFAULT 0x00000000
+#define mmPA_CL_UCP_0_Y_DEFAULT 0x00000000
+#define mmPA_CL_UCP_0_Z_DEFAULT 0x00000000
+#define mmPA_CL_UCP_0_W_DEFAULT 0x00000000
+#define mmPA_CL_UCP_1_X_DEFAULT 0x00000000
+#define mmPA_CL_UCP_1_Y_DEFAULT 0x00000000
+#define mmPA_CL_UCP_1_Z_DEFAULT 0x00000000
+#define mmPA_CL_UCP_1_W_DEFAULT 0x00000000
+#define mmPA_CL_UCP_2_X_DEFAULT 0x00000000
+#define mmPA_CL_UCP_2_Y_DEFAULT 0x00000000
+#define mmPA_CL_UCP_2_Z_DEFAULT 0x00000000
+#define mmPA_CL_UCP_2_W_DEFAULT 0x00000000
+#define mmPA_CL_UCP_3_X_DEFAULT 0x00000000
+#define mmPA_CL_UCP_3_Y_DEFAULT 0x00000000
+#define mmPA_CL_UCP_3_Z_DEFAULT 0x00000000
+#define mmPA_CL_UCP_3_W_DEFAULT 0x00000000
+#define mmPA_CL_UCP_4_X_DEFAULT 0x00000000
+#define mmPA_CL_UCP_4_Y_DEFAULT 0x00000000
+#define mmPA_CL_UCP_4_Z_DEFAULT 0x00000000
+#define mmPA_CL_UCP_4_W_DEFAULT 0x00000000
+#define mmPA_CL_UCP_5_X_DEFAULT 0x00000000
+#define mmPA_CL_UCP_5_Y_DEFAULT 0x00000000
+#define mmPA_CL_UCP_5_Z_DEFAULT 0x00000000
+#define mmPA_CL_UCP_5_W_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_0_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_1_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_2_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_3_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_4_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_5_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_6_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_7_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_8_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_9_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_10_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_11_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_12_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_13_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_14_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_15_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_16_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_17_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_18_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_19_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_20_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_21_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_22_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_23_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_24_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_25_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_26_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_27_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_28_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_29_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_30_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_31_DEFAULT 0x00000000
+#define mmSPI_VS_OUT_CONFIG_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_ENA_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_ADDR_DEFAULT 0x00000000
+#define mmSPI_INTERP_CONTROL_0_DEFAULT 0x00000000
+#define mmSPI_PS_IN_CONTROL_DEFAULT 0x00000000
+#define mmSPI_BARYC_CNTL_DEFAULT 0x00000000
+#define mmSPI_TMPRING_SIZE_DEFAULT 0x00000000
+#define mmSPI_SHADER_POS_FORMAT_DEFAULT 0x00000000
+#define mmSPI_SHADER_Z_FORMAT_DEFAULT 0x00000000
+#define mmSPI_SHADER_COL_FORMAT_DEFAULT 0x00000000
+#define mmSX_PS_DOWNCONVERT_DEFAULT 0x00000000
+#define mmSX_BLEND_OPT_EPSILON_DEFAULT 0x00000000
+#define mmSX_BLEND_OPT_CONTROL_DEFAULT 0x00000000
+#define mmSX_MRT0_BLEND_OPT_DEFAULT 0x00000000
+#define mmSX_MRT1_BLEND_OPT_DEFAULT 0x00000000
+#define mmSX_MRT2_BLEND_OPT_DEFAULT 0x00000000
+#define mmSX_MRT3_BLEND_OPT_DEFAULT 0x00000000
+#define mmSX_MRT4_BLEND_OPT_DEFAULT 0x00000000
+#define mmSX_MRT5_BLEND_OPT_DEFAULT 0x00000000
+#define mmSX_MRT6_BLEND_OPT_DEFAULT 0x00000000
+#define mmSX_MRT7_BLEND_OPT_DEFAULT 0x00000000
+#define mmCB_BLEND0_CONTROL_DEFAULT 0x00000000
+#define mmCB_BLEND1_CONTROL_DEFAULT 0x00000000
+#define mmCB_BLEND2_CONTROL_DEFAULT 0x00000000
+#define mmCB_BLEND3_CONTROL_DEFAULT 0x00000000
+#define mmCB_BLEND4_CONTROL_DEFAULT 0x00000000
+#define mmCB_BLEND5_CONTROL_DEFAULT 0x00000000
+#define mmCB_BLEND6_CONTROL_DEFAULT 0x00000000
+#define mmCB_BLEND7_CONTROL_DEFAULT 0x00000000
+#define mmCB_MRT0_EPITCH_DEFAULT 0x00000000
+#define mmCB_MRT1_EPITCH_DEFAULT 0x00000000
+#define mmCB_MRT2_EPITCH_DEFAULT 0x00000000
+#define mmCB_MRT3_EPITCH_DEFAULT 0x00000000
+#define mmCB_MRT4_EPITCH_DEFAULT 0x00000000
+#define mmCB_MRT5_EPITCH_DEFAULT 0x00000000
+#define mmCB_MRT6_EPITCH_DEFAULT 0x00000000
+#define mmCB_MRT7_EPITCH_DEFAULT 0x00000000
+#define mmCS_COPY_STATE_DEFAULT 0x00000000
+#define mmGFX_COPY_STATE_DEFAULT 0x00000000
+#define mmPA_CL_POINT_X_RAD_DEFAULT 0x00000000
+#define mmPA_CL_POINT_Y_RAD_DEFAULT 0x00000000
+#define mmPA_CL_POINT_SIZE_DEFAULT 0x00000000
+#define mmPA_CL_POINT_CULL_RAD_DEFAULT 0x00000000
+#define mmVGT_DMA_BASE_HI_DEFAULT 0x00000000
+#define mmVGT_DMA_BASE_DEFAULT 0x00000000
+#define mmVGT_DRAW_INITIATOR_DEFAULT 0x00000000
+#define mmVGT_IMMED_DATA_DEFAULT 0x00000000
+#define mmVGT_EVENT_ADDRESS_REG_DEFAULT 0x00000000
+#define mmDB_DEPTH_CONTROL_DEFAULT 0x00000000
+#define mmDB_EQAA_DEFAULT 0x00000000
+#define mmCB_COLOR_CONTROL_DEFAULT 0x00000000
+#define mmDB_SHADER_CONTROL_DEFAULT 0x00000000
+#define mmPA_CL_CLIP_CNTL_DEFAULT 0x00000000
+#define mmPA_SU_SC_MODE_CNTL_DEFAULT 0x00000000
+#define mmPA_CL_VTE_CNTL_DEFAULT 0x00000000
+#define mmPA_CL_VS_OUT_CNTL_DEFAULT 0x00000000
+#define mmPA_CL_NANINF_CNTL_DEFAULT 0x00000000
+#define mmPA_SU_LINE_STIPPLE_CNTL_DEFAULT 0x00000000
+#define mmPA_SU_LINE_STIPPLE_SCALE_DEFAULT 0x00000000
+#define mmPA_SU_PRIM_FILTER_CNTL_DEFAULT 0x00000000
+#define mmPA_SU_SMALL_PRIM_FILTER_CNTL_DEFAULT 0x00000000
+#define mmPA_CL_OBJPRIM_ID_CNTL_DEFAULT 0x00000000
+#define mmPA_CL_NGG_CNTL_DEFAULT 0x00000000
+#define mmPA_SU_OVER_RASTERIZATION_CNTL_DEFAULT 0x00000000
+#define mmPA_SU_POINT_SIZE_DEFAULT 0x00000000
+#define mmPA_SU_POINT_MINMAX_DEFAULT 0x00000000
+#define mmPA_SU_LINE_CNTL_DEFAULT 0x00000000
+#define mmPA_SC_LINE_STIPPLE_DEFAULT 0x00000000
+#define mmVGT_OUTPUT_PATH_CNTL_DEFAULT 0x00000000
+#define mmVGT_HOS_CNTL_DEFAULT 0x00000000
+#define mmVGT_HOS_MAX_TESS_LEVEL_DEFAULT 0x00000000
+#define mmVGT_HOS_MIN_TESS_LEVEL_DEFAULT 0x00000000
+#define mmVGT_HOS_REUSE_DEPTH_DEFAULT 0x00000000
+#define mmVGT_GROUP_PRIM_TYPE_DEFAULT 0x00000000
+#define mmVGT_GROUP_FIRST_DECR_DEFAULT 0x00000000
+#define mmVGT_GROUP_DECR_DEFAULT 0x00000000
+#define mmVGT_GROUP_VECT_0_CNTL_DEFAULT 0x00000000
+#define mmVGT_GROUP_VECT_1_CNTL_DEFAULT 0x00000000
+#define mmVGT_GROUP_VECT_0_FMT_CNTL_DEFAULT 0x00000000
+#define mmVGT_GROUP_VECT_1_FMT_CNTL_DEFAULT 0x00000000
+#define mmVGT_GS_MODE_DEFAULT 0x00000000
+#define mmVGT_GS_ONCHIP_CNTL_DEFAULT 0x00000000
+#define mmPA_SC_MODE_CNTL_0_DEFAULT 0x00000000
+#define mmPA_SC_MODE_CNTL_1_DEFAULT 0x06000000
+#define mmVGT_ENHANCE_DEFAULT 0x00000000
+#define mmVGT_GS_PER_ES_DEFAULT 0x00000000
+#define mmVGT_ES_PER_GS_DEFAULT 0x00000000
+#define mmVGT_GS_PER_VS_DEFAULT 0x00000000
+#define mmVGT_GSVS_RING_OFFSET_1_DEFAULT 0x00000000
+#define mmVGT_GSVS_RING_OFFSET_2_DEFAULT 0x00000000
+#define mmVGT_GSVS_RING_OFFSET_3_DEFAULT 0x00000000
+#define mmVGT_GS_OUT_PRIM_TYPE_DEFAULT 0x00000000
+#define mmIA_ENHANCE_DEFAULT 0x00000000
+#define mmVGT_DMA_SIZE_DEFAULT 0x00000000
+#define mmVGT_DMA_MAX_SIZE_DEFAULT 0x00000000
+#define mmVGT_DMA_INDEX_TYPE_DEFAULT 0x00000000
+#define mmWD_ENHANCE_DEFAULT 0x00000000
+#define mmVGT_PRIMITIVEID_EN_DEFAULT 0x00000000
+#define mmVGT_DMA_NUM_INSTANCES_DEFAULT 0x00000000
+#define mmVGT_PRIMITIVEID_RESET_DEFAULT 0x00000000
+#define mmVGT_EVENT_INITIATOR_DEFAULT 0x00000000
+#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_DEFAULT 0x00000000
+#define mmVGT_DRAW_PAYLOAD_CNTL_DEFAULT 0x00000000
+#define mmVGT_INDEX_PAYLOAD_CNTL_DEFAULT 0x00000000
+#define mmVGT_INSTANCE_STEP_RATE_0_DEFAULT 0x00000000
+#define mmVGT_INSTANCE_STEP_RATE_1_DEFAULT 0x00000000
+#define mmVGT_ESGS_RING_ITEMSIZE_DEFAULT 0x00000000
+#define mmVGT_GSVS_RING_ITEMSIZE_DEFAULT 0x00000000
+#define mmVGT_REUSE_OFF_DEFAULT 0x00000000
+#define mmVGT_VTX_CNT_EN_DEFAULT 0x00000000
+#define mmDB_HTILE_SURFACE_DEFAULT 0x00000000
+#define mmDB_SRESULTS_COMPARE_STATE0_DEFAULT 0x00000000
+#define mmDB_SRESULTS_COMPARE_STATE1_DEFAULT 0x00000000
+#define mmDB_PRELOAD_CONTROL_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_SIZE_0_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_VTX_STRIDE_0_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_OFFSET_0_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_SIZE_1_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_VTX_STRIDE_1_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_OFFSET_1_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_SIZE_2_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_VTX_STRIDE_2_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_OFFSET_2_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_SIZE_3_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_VTX_STRIDE_3_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_OFFSET_3_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_DEFAULT 0x00000000
+#define mmVGT_GS_MAX_VERT_OUT_DEFAULT 0x00000000
+#define mmVGT_TESS_DISTRIBUTION_DEFAULT 0x00000000
+#define mmVGT_SHADER_STAGES_EN_DEFAULT 0x00000000
+#define mmVGT_LS_HS_CONFIG_DEFAULT 0x00000000
+#define mmVGT_GS_VERT_ITEMSIZE_DEFAULT 0x00000000
+#define mmVGT_GS_VERT_ITEMSIZE_1_DEFAULT 0x00000000
+#define mmVGT_GS_VERT_ITEMSIZE_2_DEFAULT 0x00000000
+#define mmVGT_GS_VERT_ITEMSIZE_3_DEFAULT 0x00000000
+#define mmVGT_TF_PARAM_DEFAULT 0x00000000
+#define mmDB_ALPHA_TO_MASK_DEFAULT 0x00000000
+#define mmVGT_DISPATCH_DRAW_INDEX_DEFAULT 0x00000000
+#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_DEFAULT 0x00000000
+#define mmPA_SU_POLY_OFFSET_CLAMP_DEFAULT 0x00000000
+#define mmPA_SU_POLY_OFFSET_FRONT_SCALE_DEFAULT 0x00000000
+#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET_DEFAULT 0x00000000
+#define mmPA_SU_POLY_OFFSET_BACK_SCALE_DEFAULT 0x00000000
+#define mmPA_SU_POLY_OFFSET_BACK_OFFSET_DEFAULT 0x00000000
+#define mmVGT_GS_INSTANCE_CNT_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_CONFIG_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_CONFIG_DEFAULT 0x00000000
+#define mmVGT_DMA_EVENT_INITIATOR_DEFAULT 0x00000000
+#define mmPA_SC_CENTROID_PRIORITY_0_DEFAULT 0x00000000
+#define mmPA_SC_CENTROID_PRIORITY_1_DEFAULT 0x00000000
+#define mmPA_SC_LINE_CNTL_DEFAULT 0x00000000
+#define mmPA_SC_AA_CONFIG_DEFAULT 0x00000000
+#define mmPA_SU_VTX_CNTL_DEFAULT 0x00000000
+#define mmPA_CL_GB_VERT_CLIP_ADJ_DEFAULT 0x00000000
+#define mmPA_CL_GB_VERT_DISC_ADJ_DEFAULT 0x00000000
+#define mmPA_CL_GB_HORZ_CLIP_ADJ_DEFAULT 0x00000000
+#define mmPA_CL_GB_HORZ_DISC_ADJ_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_DEFAULT 0x00000000
+#define mmPA_SC_AA_MASK_X0Y0_X1Y0_DEFAULT 0x00000000
+#define mmPA_SC_AA_MASK_X0Y1_X1Y1_DEFAULT 0x00000000
+#define mmPA_SC_SHADER_CONTROL_DEFAULT 0x00000000
+#define mmPA_SC_BINNER_CNTL_0_DEFAULT 0x00000000
+#define mmPA_SC_BINNER_CNTL_1_DEFAULT 0x00000000
+#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_DEFAULT 0x00000000
+#define mmPA_SC_NGG_MODE_CNTL_DEFAULT 0x00000000
+#define mmVGT_VERTEX_REUSE_BLOCK_CNTL_DEFAULT 0x00000000
+#define mmVGT_OUT_DEALLOC_CNTL_DEFAULT 0x00000000
+#define mmCB_COLOR0_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR0_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR0_ATTRIB2_DEFAULT 0x00000000
+#define mmCB_COLOR0_VIEW_DEFAULT 0x00000000
+#define mmCB_COLOR0_INFO_DEFAULT 0x00000000
+#define mmCB_COLOR0_ATTRIB_DEFAULT 0x00000000
+#define mmCB_COLOR0_DCC_CONTROL_DEFAULT 0x00000000
+#define mmCB_COLOR0_CMASK_DEFAULT 0x00000000
+#define mmCB_COLOR0_CMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR0_FMASK_DEFAULT 0x00000000
+#define mmCB_COLOR0_FMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR0_CLEAR_WORD0_DEFAULT 0x00000000
+#define mmCB_COLOR0_CLEAR_WORD1_DEFAULT 0x00000000
+#define mmCB_COLOR0_DCC_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR0_DCC_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR1_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR1_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR1_ATTRIB2_DEFAULT 0x00000000
+#define mmCB_COLOR1_VIEW_DEFAULT 0x00000000
+#define mmCB_COLOR1_INFO_DEFAULT 0x00000000
+#define mmCB_COLOR1_ATTRIB_DEFAULT 0x00000000
+#define mmCB_COLOR1_DCC_CONTROL_DEFAULT 0x00000000
+#define mmCB_COLOR1_CMASK_DEFAULT 0x00000000
+#define mmCB_COLOR1_CMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR1_FMASK_DEFAULT 0x00000000
+#define mmCB_COLOR1_FMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR1_CLEAR_WORD0_DEFAULT 0x00000000
+#define mmCB_COLOR1_CLEAR_WORD1_DEFAULT 0x00000000
+#define mmCB_COLOR1_DCC_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR1_DCC_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR2_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR2_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR2_ATTRIB2_DEFAULT 0x00000000
+#define mmCB_COLOR2_VIEW_DEFAULT 0x00000000
+#define mmCB_COLOR2_INFO_DEFAULT 0x00000000
+#define mmCB_COLOR2_ATTRIB_DEFAULT 0x00000000
+#define mmCB_COLOR2_DCC_CONTROL_DEFAULT 0x00000000
+#define mmCB_COLOR2_CMASK_DEFAULT 0x00000000
+#define mmCB_COLOR2_CMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR2_FMASK_DEFAULT 0x00000000
+#define mmCB_COLOR2_FMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR2_CLEAR_WORD0_DEFAULT 0x00000000
+#define mmCB_COLOR2_CLEAR_WORD1_DEFAULT 0x00000000
+#define mmCB_COLOR2_DCC_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR2_DCC_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR3_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR3_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR3_ATTRIB2_DEFAULT 0x00000000
+#define mmCB_COLOR3_VIEW_DEFAULT 0x00000000
+#define mmCB_COLOR3_INFO_DEFAULT 0x00000000
+#define mmCB_COLOR3_ATTRIB_DEFAULT 0x00000000
+#define mmCB_COLOR3_DCC_CONTROL_DEFAULT 0x00000000
+#define mmCB_COLOR3_CMASK_DEFAULT 0x00000000
+#define mmCB_COLOR3_CMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR3_FMASK_DEFAULT 0x00000000
+#define mmCB_COLOR3_FMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR3_CLEAR_WORD0_DEFAULT 0x00000000
+#define mmCB_COLOR3_CLEAR_WORD1_DEFAULT 0x00000000
+#define mmCB_COLOR3_DCC_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR3_DCC_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR4_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR4_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR4_ATTRIB2_DEFAULT 0x00000000
+#define mmCB_COLOR4_VIEW_DEFAULT 0x00000000
+#define mmCB_COLOR4_INFO_DEFAULT 0x00000000
+#define mmCB_COLOR4_ATTRIB_DEFAULT 0x00000000
+#define mmCB_COLOR4_DCC_CONTROL_DEFAULT 0x00000000
+#define mmCB_COLOR4_CMASK_DEFAULT 0x00000000
+#define mmCB_COLOR4_CMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR4_FMASK_DEFAULT 0x00000000
+#define mmCB_COLOR4_FMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR4_CLEAR_WORD0_DEFAULT 0x00000000
+#define mmCB_COLOR4_CLEAR_WORD1_DEFAULT 0x00000000
+#define mmCB_COLOR4_DCC_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR4_DCC_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR5_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR5_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR5_ATTRIB2_DEFAULT 0x00000000
+#define mmCB_COLOR5_VIEW_DEFAULT 0x00000000
+#define mmCB_COLOR5_INFO_DEFAULT 0x00000000
+#define mmCB_COLOR5_ATTRIB_DEFAULT 0x00000000
+#define mmCB_COLOR5_DCC_CONTROL_DEFAULT 0x00000000
+#define mmCB_COLOR5_CMASK_DEFAULT 0x00000000
+#define mmCB_COLOR5_CMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR5_FMASK_DEFAULT 0x00000000
+#define mmCB_COLOR5_FMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR5_CLEAR_WORD0_DEFAULT 0x00000000
+#define mmCB_COLOR5_CLEAR_WORD1_DEFAULT 0x00000000
+#define mmCB_COLOR5_DCC_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR5_DCC_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR6_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR6_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR6_ATTRIB2_DEFAULT 0x00000000
+#define mmCB_COLOR6_VIEW_DEFAULT 0x00000000
+#define mmCB_COLOR6_INFO_DEFAULT 0x00000000
+#define mmCB_COLOR6_ATTRIB_DEFAULT 0x00000000
+#define mmCB_COLOR6_DCC_CONTROL_DEFAULT 0x00000000
+#define mmCB_COLOR6_CMASK_DEFAULT 0x00000000
+#define mmCB_COLOR6_CMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR6_FMASK_DEFAULT 0x00000000
+#define mmCB_COLOR6_FMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR6_CLEAR_WORD0_DEFAULT 0x00000000
+#define mmCB_COLOR6_CLEAR_WORD1_DEFAULT 0x00000000
+#define mmCB_COLOR6_DCC_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR6_DCC_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR7_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR7_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR7_ATTRIB2_DEFAULT 0x00000000
+#define mmCB_COLOR7_VIEW_DEFAULT 0x00000000
+#define mmCB_COLOR7_INFO_DEFAULT 0x00000000
+#define mmCB_COLOR7_ATTRIB_DEFAULT 0x00000000
+#define mmCB_COLOR7_DCC_CONTROL_DEFAULT 0x00000000
+#define mmCB_COLOR7_CMASK_DEFAULT 0x00000000
+#define mmCB_COLOR7_CMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR7_FMASK_DEFAULT 0x00000000
+#define mmCB_COLOR7_FMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR7_CLEAR_WORD0_DEFAULT 0x00000000
+#define mmCB_COLOR7_CLEAR_WORD1_DEFAULT 0x00000000
+#define mmCB_COLOR7_DCC_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR7_DCC_BASE_EXT_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gfxudec
+#define mmCP_EOP_DONE_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_EOP_DONE_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_EOP_DONE_DATA_LO_DEFAULT 0x00000000
+#define mmCP_EOP_DONE_DATA_HI_DEFAULT 0x00000000
+#define mmCP_EOP_LAST_FENCE_LO_DEFAULT 0x00000000
+#define mmCP_EOP_LAST_FENCE_HI_DEFAULT 0x00000000
+#define mmCP_STREAM_OUT_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_STREAM_OUT_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_DEFAULT 0x00000000
+#define mmCP_PIPE_STATS_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_PIPE_STATS_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_VGT_IAVERT_COUNT_LO_DEFAULT 0x00000000
+#define mmCP_VGT_IAVERT_COUNT_HI_DEFAULT 0x00000000
+#define mmCP_VGT_IAPRIM_COUNT_LO_DEFAULT 0x00000000
+#define mmCP_VGT_IAPRIM_COUNT_HI_DEFAULT 0x00000000
+#define mmCP_VGT_GSPRIM_COUNT_LO_DEFAULT 0x00000000
+#define mmCP_VGT_GSPRIM_COUNT_HI_DEFAULT 0x00000000
+#define mmCP_VGT_VSINVOC_COUNT_LO_DEFAULT 0x00000000
+#define mmCP_VGT_VSINVOC_COUNT_HI_DEFAULT 0x00000000
+#define mmCP_VGT_GSINVOC_COUNT_LO_DEFAULT 0x00000000
+#define mmCP_VGT_GSINVOC_COUNT_HI_DEFAULT 0x00000000
+#define mmCP_VGT_HSINVOC_COUNT_LO_DEFAULT 0x00000000
+#define mmCP_VGT_HSINVOC_COUNT_HI_DEFAULT 0x00000000
+#define mmCP_VGT_DSINVOC_COUNT_LO_DEFAULT 0x00000000
+#define mmCP_VGT_DSINVOC_COUNT_HI_DEFAULT 0x00000000
+#define mmCP_PA_CINVOC_COUNT_LO_DEFAULT 0x00000000
+#define mmCP_PA_CINVOC_COUNT_HI_DEFAULT 0x00000000
+#define mmCP_PA_CPRIM_COUNT_LO_DEFAULT 0x00000000
+#define mmCP_PA_CPRIM_COUNT_HI_DEFAULT 0x00000000
+#define mmCP_SC_PSINVOC_COUNT0_LO_DEFAULT 0x00000000
+#define mmCP_SC_PSINVOC_COUNT0_HI_DEFAULT 0x00000000
+#define mmCP_SC_PSINVOC_COUNT1_LO_DEFAULT 0x00000000
+#define mmCP_SC_PSINVOC_COUNT1_HI_DEFAULT 0x00000000
+#define mmCP_VGT_CSINVOC_COUNT_LO_DEFAULT 0x00000000
+#define mmCP_VGT_CSINVOC_COUNT_HI_DEFAULT 0x00000000
+#define mmCP_PIPE_STATS_CONTROL_DEFAULT 0x00000000
+#define mmCP_STREAM_OUT_CONTROL_DEFAULT 0x00000000
+#define mmCP_STRMOUT_CNTL_DEFAULT 0x00000000
+#define mmSCRATCH_REG0_DEFAULT 0x00000000
+#define mmSCRATCH_REG1_DEFAULT 0x00000000
+#define mmSCRATCH_REG2_DEFAULT 0x00000000
+#define mmSCRATCH_REG3_DEFAULT 0x00000000
+#define mmSCRATCH_REG4_DEFAULT 0x00000000
+#define mmSCRATCH_REG5_DEFAULT 0x00000000
+#define mmSCRATCH_REG6_DEFAULT 0x00000000
+#define mmSCRATCH_REG7_DEFAULT 0x00000000
+#define mmCP_APPEND_DATA_HI_DEFAULT 0x00000000
+#define mmCP_APPEND_LAST_CS_FENCE_HI_DEFAULT 0x00000000
+#define mmCP_APPEND_LAST_PS_FENCE_HI_DEFAULT 0x00000000
+#define mmSCRATCH_UMSK_DEFAULT 0x00000000
+#define mmSCRATCH_ADDR_DEFAULT 0x00000000
+#define mmCP_PFP_ATOMIC_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_PFP_ATOMIC_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_APPEND_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_APPEND_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_APPEND_DATA_LO_DEFAULT 0x00000000
+#define mmCP_APPEND_LAST_CS_FENCE_LO_DEFAULT 0x00000000
+#define mmCP_APPEND_LAST_PS_FENCE_LO_DEFAULT 0x00000000
+#define mmCP_ATOMIC_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_ME_ATOMIC_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_ATOMIC_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_ME_ATOMIC_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_ME_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_ME_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_ME_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_ME_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_ME_MC_WADDR_LO_DEFAULT 0x00000000
+#define mmCP_ME_MC_WADDR_HI_DEFAULT 0x00000000
+#define mmCP_ME_MC_WDATA_LO_DEFAULT 0x00000000
+#define mmCP_ME_MC_WDATA_HI_DEFAULT 0x00000000
+#define mmCP_ME_MC_RADDR_LO_DEFAULT 0x00000000
+#define mmCP_ME_MC_RADDR_HI_DEFAULT 0x00000000
+#define mmCP_SEM_WAIT_TIMER_DEFAULT 0x00000000
+#define mmCP_SIG_SEM_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_SIG_SEM_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_WAIT_REG_MEM_TIMEOUT_DEFAULT 0x00000000
+#define mmCP_WAIT_SEM_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_WAIT_SEM_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DMA_PFP_CONTROL_DEFAULT 0x00000000
+#define mmCP_DMA_ME_CONTROL_DEFAULT 0x00000000
+#define mmCP_COHER_BASE_HI_DEFAULT 0x00000000
+#define mmCP_COHER_START_DELAY_DEFAULT 0x00000020
+#define mmCP_COHER_CNTL_DEFAULT 0x00000000
+#define mmCP_COHER_SIZE_DEFAULT 0x00000000
+#define mmCP_COHER_BASE_DEFAULT 0x00000000
+#define mmCP_COHER_STATUS_DEFAULT 0x00000000
+#define mmCP_DMA_ME_SRC_ADDR_DEFAULT 0x00000000
+#define mmCP_DMA_ME_SRC_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DMA_ME_DST_ADDR_DEFAULT 0x00000000
+#define mmCP_DMA_ME_DST_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DMA_ME_COMMAND_DEFAULT 0x00000000
+#define mmCP_DMA_PFP_SRC_ADDR_DEFAULT 0x00000000
+#define mmCP_DMA_PFP_SRC_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DMA_PFP_DST_ADDR_DEFAULT 0x00000000
+#define mmCP_DMA_PFP_DST_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DMA_PFP_COMMAND_DEFAULT 0x00000000
+#define mmCP_DMA_CNTL_DEFAULT 0x00080030
+#define mmCP_DMA_READ_TAGS_DEFAULT 0x00000000
+#define mmCP_COHER_SIZE_HI_DEFAULT 0x00000000
+#define mmCP_PFP_IB_CONTROL_DEFAULT 0x00000000
+#define mmCP_PFP_LOAD_CONTROL_DEFAULT 0x00000000
+#define mmCP_SCRATCH_INDEX_DEFAULT 0x00000000
+#define mmCP_SCRATCH_DATA_DEFAULT 0x00000000
+#define mmCP_RB_OFFSET_DEFAULT 0x00000000
+#define mmCP_IB1_OFFSET_DEFAULT 0x00000000
+#define mmCP_IB2_OFFSET_DEFAULT 0x00000000
+#define mmCP_IB1_PREAMBLE_BEGIN_DEFAULT 0x00000000
+#define mmCP_IB1_PREAMBLE_END_DEFAULT 0x00000000
+#define mmCP_IB2_PREAMBLE_BEGIN_DEFAULT 0x00000000
+#define mmCP_IB2_PREAMBLE_END_DEFAULT 0x00000000
+#define mmCP_CE_IB1_OFFSET_DEFAULT 0x00000000
+#define mmCP_CE_IB2_OFFSET_DEFAULT 0x00000000
+#define mmCP_CE_COUNTER_DEFAULT 0x00000000
+#define mmCP_CE_RB_OFFSET_DEFAULT 0x00000000
+#define mmCP_CE_INIT_CMD_BUFSZ_DEFAULT 0x00000000
+#define mmCP_CE_IB1_CMD_BUFSZ_DEFAULT 0x00000000
+#define mmCP_CE_IB2_CMD_BUFSZ_DEFAULT 0x00000000
+#define mmCP_IB1_CMD_BUFSZ_DEFAULT 0x00000000
+#define mmCP_IB2_CMD_BUFSZ_DEFAULT 0x00000000
+#define mmCP_ST_CMD_BUFSZ_DEFAULT 0x00000000
+#define mmCP_CE_INIT_BASE_LO_DEFAULT 0x00000000
+#define mmCP_CE_INIT_BASE_HI_DEFAULT 0x00000000
+#define mmCP_CE_INIT_BUFSZ_DEFAULT 0x00000000
+#define mmCP_CE_IB1_BASE_LO_DEFAULT 0x00000000
+#define mmCP_CE_IB1_BASE_HI_DEFAULT 0x00000000
+#define mmCP_CE_IB1_BUFSZ_DEFAULT 0x00000000
+#define mmCP_CE_IB2_BASE_LO_DEFAULT 0x00000000
+#define mmCP_CE_IB2_BASE_HI_DEFAULT 0x00000000
+#define mmCP_CE_IB2_BUFSZ_DEFAULT 0x00000000
+#define mmCP_IB1_BASE_LO_DEFAULT 0x00000000
+#define mmCP_IB1_BASE_HI_DEFAULT 0x00000000
+#define mmCP_IB1_BUFSZ_DEFAULT 0x00000000
+#define mmCP_IB2_BASE_LO_DEFAULT 0x00000000
+#define mmCP_IB2_BASE_HI_DEFAULT 0x00000000
+#define mmCP_IB2_BUFSZ_DEFAULT 0x00000000
+#define mmCP_ST_BASE_LO_DEFAULT 0x00000000
+#define mmCP_ST_BASE_HI_DEFAULT 0x00000000
+#define mmCP_ST_BUFSZ_DEFAULT 0x00000000
+#define mmCP_EOP_DONE_EVENT_CNTL_DEFAULT 0x00000000
+#define mmCP_EOP_DONE_DATA_CNTL_DEFAULT 0x00000000
+#define mmCP_EOP_DONE_CNTX_ID_DEFAULT 0x00000000
+#define mmCP_PFP_COMPLETION_STATUS_DEFAULT 0x00000000
+#define mmCP_CE_COMPLETION_STATUS_DEFAULT 0x00000000
+#define mmCP_PRED_NOT_VISIBLE_DEFAULT 0x00000000
+#define mmCP_PFP_METADATA_BASE_ADDR_DEFAULT 0x00000000
+#define mmCP_PFP_METADATA_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_CE_METADATA_BASE_ADDR_DEFAULT 0x00000000
+#define mmCP_CE_METADATA_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DRAW_INDX_INDR_ADDR_DEFAULT 0x00000000
+#define mmCP_DRAW_INDX_INDR_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DISPATCH_INDR_ADDR_DEFAULT 0x00000000
+#define mmCP_DISPATCH_INDR_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_INDEX_BASE_ADDR_DEFAULT 0x00000000
+#define mmCP_INDEX_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_INDEX_TYPE_DEFAULT 0x00000000
+#define mmCP_GDS_BKUP_ADDR_DEFAULT 0x00000000
+#define mmCP_GDS_BKUP_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_SAMPLE_STATUS_DEFAULT 0x00000000
+#define mmCP_ME_COHER_CNTL_DEFAULT 0x00000000
+#define mmCP_ME_COHER_SIZE_DEFAULT 0x00000000
+#define mmCP_ME_COHER_SIZE_HI_DEFAULT 0x00000000
+#define mmCP_ME_COHER_BASE_DEFAULT 0x00000000
+#define mmCP_ME_COHER_BASE_HI_DEFAULT 0x00000000
+#define mmCP_ME_COHER_STATUS_DEFAULT 0x00000000
+#define mmRLC_GPM_PERF_COUNT_0_DEFAULT 0x00000000
+#define mmRLC_GPM_PERF_COUNT_1_DEFAULT 0x00000000
+#define mmGRBM_GFX_INDEX_DEFAULT 0xe0000000
+#define mmVGT_GSVS_RING_SIZE_DEFAULT 0x00000000
+#define mmVGT_PRIMITIVE_TYPE_DEFAULT 0x00000000
+#define mmVGT_INDEX_TYPE_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_DEFAULT 0x00000000
+#define mmVGT_MAX_VTX_INDX_DEFAULT 0x00000000
+#define mmVGT_MIN_VTX_INDX_DEFAULT 0x00000000
+#define mmVGT_INDX_OFFSET_DEFAULT 0x00000000
+#define mmVGT_MULTI_PRIM_IB_RESET_EN_DEFAULT 0x00000000
+#define mmVGT_NUM_INDICES_DEFAULT 0x00000000
+#define mmVGT_NUM_INSTANCES_DEFAULT 0x00000000
+#define mmVGT_TF_RING_SIZE_DEFAULT 0x00002000
+#define mmVGT_HS_OFFCHIP_PARAM_DEFAULT 0x00000000
+#define mmVGT_TF_MEMORY_BASE_DEFAULT 0x00000000
+#define mmVGT_TF_MEMORY_BASE_HI_DEFAULT 0x00000000
+#define mmWD_POS_BUF_BASE_DEFAULT 0x00000000
+#define mmWD_POS_BUF_BASE_HI_DEFAULT 0x00000000
+#define mmWD_CNTL_SB_BUF_BASE_DEFAULT 0x00000000
+#define mmWD_CNTL_SB_BUF_BASE_HI_DEFAULT 0x00000000
+#define mmWD_INDEX_BUF_BASE_DEFAULT 0x00000000
+#define mmWD_INDEX_BUF_BASE_HI_DEFAULT 0x00000000
+#define mmIA_MULTI_VGT_PARAM_DEFAULT 0x006000ff
+#define mmVGT_OBJECT_ID_DEFAULT 0x00000000
+#define mmVGT_INSTANCE_BASE_ID_DEFAULT 0x00000000
+#define mmPA_SU_LINE_STIPPLE_VALUE_DEFAULT 0x00000000
+#define mmPA_SC_LINE_STIPPLE_STATE_DEFAULT 0x00000000
+#define mmPA_SC_SCREEN_EXTENT_MIN_0_DEFAULT 0x7fff7fff
+#define mmPA_SC_SCREEN_EXTENT_MAX_0_DEFAULT 0x80008000
+#define mmPA_SC_SCREEN_EXTENT_MIN_1_DEFAULT 0x7fff7fff
+#define mmPA_SC_SCREEN_EXTENT_MAX_1_DEFAULT 0x80008000
+#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000
+#define mmPA_SC_P3D_TRAP_SCREEN_H_DEFAULT 0x00000000
+#define mmPA_SC_P3D_TRAP_SCREEN_V_DEFAULT 0x00000000
+#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000
+#define mmPA_SC_P3D_TRAP_SCREEN_COUNT_DEFAULT 0x00000000
+#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000
+#define mmPA_SC_HP3D_TRAP_SCREEN_H_DEFAULT 0x00000000
+#define mmPA_SC_HP3D_TRAP_SCREEN_V_DEFAULT 0x00000000
+#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000
+#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT_DEFAULT 0x00000000
+#define mmPA_SC_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000
+#define mmPA_SC_TRAP_SCREEN_H_DEFAULT 0x00000000
+#define mmPA_SC_TRAP_SCREEN_V_DEFAULT 0x00000000
+#define mmPA_SC_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000
+#define mmPA_SC_TRAP_SCREEN_COUNT_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_BASE_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_SIZE_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_MASK_DEFAULT 0x0000cf80
+#define mmSQ_THREAD_TRACE_TOKEN_MASK_DEFAULT 0x00ffffff
+#define mmSQ_THREAD_TRACE_PERF_MASK_DEFAULT 0xffffffff
+#define mmSQ_THREAD_TRACE_CTRL_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_MODE_DEFAULT 0x02049249
+#define mmSQ_THREAD_TRACE_BASE2_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_TOKEN_MASK2_DEFAULT 0xffffffff
+#define mmSQ_THREAD_TRACE_WPTR_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_STATUS_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_HIWATER_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_CNTR_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_USERDATA_0_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_USERDATA_1_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_USERDATA_2_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_USERDATA_3_DEFAULT 0x00000000
+#define mmSQC_CACHES_DEFAULT 0x00000000
+#define mmSQC_WRITEBACK_DEFAULT 0x00000000
+#define mmTA_CS_BC_BASE_ADDR_DEFAULT 0x00000000
+#define mmTA_CS_BC_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmTA_GRAD_ADJ_UCONFIG_DEFAULT 0x40000040
+#define mmDB_OCCLUSION_COUNT0_LOW_DEFAULT 0x00000000
+#define mmDB_OCCLUSION_COUNT0_HI_DEFAULT 0x00000000
+#define mmDB_OCCLUSION_COUNT1_LOW_DEFAULT 0x00000000
+#define mmDB_OCCLUSION_COUNT1_HI_DEFAULT 0x00000000
+#define mmDB_OCCLUSION_COUNT2_LOW_DEFAULT 0x00000000
+#define mmDB_OCCLUSION_COUNT2_HI_DEFAULT 0x00000000
+#define mmDB_OCCLUSION_COUNT3_LOW_DEFAULT 0x00000000
+#define mmDB_OCCLUSION_COUNT3_HI_DEFAULT 0x00000000
+#define mmDB_ZPASS_COUNT_LOW_DEFAULT 0x00000000
+#define mmDB_ZPASS_COUNT_HI_DEFAULT 0x00000000
+#define mmGDS_RD_ADDR_DEFAULT 0x00000000
+#define mmGDS_RD_DATA_DEFAULT 0x00000000
+#define mmGDS_RD_BURST_ADDR_DEFAULT 0x00000000
+#define mmGDS_RD_BURST_COUNT_DEFAULT 0x00000000
+#define mmGDS_RD_BURST_DATA_DEFAULT 0x00000000
+#define mmGDS_WR_ADDR_DEFAULT 0x00000000
+#define mmGDS_WR_DATA_DEFAULT 0x00000000
+#define mmGDS_WR_BURST_ADDR_DEFAULT 0x00000000
+#define mmGDS_WR_BURST_DATA_DEFAULT 0x00000000
+#define mmGDS_WRITE_COMPLETE_DEFAULT 0x00000000
+#define mmGDS_ATOM_CNTL_DEFAULT 0x00000000
+#define mmGDS_ATOM_COMPLETE_DEFAULT 0x00000001
+#define mmGDS_ATOM_BASE_DEFAULT 0x00000000
+#define mmGDS_ATOM_SIZE_DEFAULT 0x00000000
+#define mmGDS_ATOM_OFFSET0_DEFAULT 0x00000000
+#define mmGDS_ATOM_OFFSET1_DEFAULT 0x00000000
+#define mmGDS_ATOM_DST_DEFAULT 0x00000000
+#define mmGDS_ATOM_OP_DEFAULT 0x00000000
+#define mmGDS_ATOM_SRC0_DEFAULT 0x00000000
+#define mmGDS_ATOM_SRC0_U_DEFAULT 0x00000000
+#define mmGDS_ATOM_SRC1_DEFAULT 0x00000000
+#define mmGDS_ATOM_SRC1_U_DEFAULT 0x00000000
+#define mmGDS_ATOM_READ0_DEFAULT 0x00000000
+#define mmGDS_ATOM_READ0_U_DEFAULT 0x00000000
+#define mmGDS_ATOM_READ1_DEFAULT 0x00000000
+#define mmGDS_ATOM_READ1_U_DEFAULT 0x00000000
+#define mmGDS_GWS_RESOURCE_CNTL_DEFAULT 0x00000000
+#define mmGDS_GWS_RESOURCE_DEFAULT 0x00000000
+#define mmGDS_GWS_RESOURCE_CNT_DEFAULT 0x00000000
+#define mmGDS_OA_CNTL_DEFAULT 0x00000000
+#define mmGDS_OA_COUNTER_DEFAULT 0x00000000
+#define mmGDS_OA_ADDRESS_DEFAULT 0x00000000
+#define mmGDS_OA_INCDEC_DEFAULT 0x00000000
+#define mmGDS_OA_RING_SIZE_DEFAULT 0x00000000
+#define mmSPI_CONFIG_CNTL_DEFAULT 0x0062c688
+#define mmSPI_CONFIG_CNTL_1_DEFAULT 0x01000106
+#define mmSPI_CONFIG_CNTL_2_DEFAULT 0x00000011
+
+
+// addressBlock: gc_perfddec
+#define mmCPG_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmCPG_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmCPG_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmCPG_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmCPC_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmCPC_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmCPC_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmCPC_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmCPF_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmCPF_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmCPF_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmCPF_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmCPF_LATENCY_STATS_DATA_DEFAULT 0x00000000
+#define mmCPG_LATENCY_STATS_DATA_DEFAULT 0x00000000
+#define mmCPC_LATENCY_STATS_DATA_DEFAULT 0x00000000
+#define mmGRBM_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmGRBM_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmGRBM_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmGRBM_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmGRBM_SE0_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmGRBM_SE0_PERFCOUNTER_HI_DEFAULT 0x00000000
+#define mmGRBM_SE1_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmGRBM_SE1_PERFCOUNTER_HI_DEFAULT 0x00000000
+#define mmGRBM_SE2_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmGRBM_SE2_PERFCOUNTER_HI_DEFAULT 0x00000000
+#define mmGRBM_SE3_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmGRBM_SE3_PERFCOUNTER_HI_DEFAULT 0x00000000
+#define mmWD_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmWD_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmWD_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmWD_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmWD_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmWD_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmWD_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmWD_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmIA_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmIA_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmIA_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmIA_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmIA_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmIA_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmIA_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmIA_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmVGT_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmVGT_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmVGT_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmVGT_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmVGT_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmVGT_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmVGT_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmVGT_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER4_LO_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER4_HI_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER5_LO_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER5_HI_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER6_LO_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER6_HI_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER7_LO_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER7_HI_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER4_HI_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER4_LO_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER5_HI_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER5_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER4_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER4_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER5_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER5_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER6_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER6_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER7_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER7_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER8_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER8_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER9_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER9_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER10_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER10_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER11_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER11_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER12_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER12_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER13_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER13_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER14_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER14_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER15_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER15_HI_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmTA_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmTA_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmTA_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmTA_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmTD_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmTD_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmTD_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmTD_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmTCC_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmTCC_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmTCC_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmTCC_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmTCC_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmTCC_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmTCC_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmTCC_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmTCA_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmTCA_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmTCA_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmTCA_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmTCA_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmTCA_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmTCA_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmTCA_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmRLC_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmRLC_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmRLC_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmRLC_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER3_HI_DEFAULT 0x00000000
+
+
+// addressBlock: gc_utcl2_atcl2pfcntrdec
+#define mmATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000
+
+
+// addressBlock: gc_utcl2_vml2prdec
+#define mmMC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmMC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000
+
+
+// addressBlock: gc_perfsdec
+#define mmCPG_PERFCOUNTER1_SELECT_DEFAULT 0x11000401
+#define mmCPG_PERFCOUNTER0_SELECT1_DEFAULT 0x11000401
+#define mmCPG_PERFCOUNTER0_SELECT_DEFAULT 0x11000401
+#define mmCPC_PERFCOUNTER1_SELECT_DEFAULT 0x11000401
+#define mmCPC_PERFCOUNTER0_SELECT1_DEFAULT 0x11000401
+#define mmCPF_PERFCOUNTER1_SELECT_DEFAULT 0x11000401
+#define mmCPF_PERFCOUNTER0_SELECT1_DEFAULT 0x11000401
+#define mmCPF_PERFCOUNTER0_SELECT_DEFAULT 0x11000401
+#define mmCP_PERFMON_CNTL_DEFAULT 0x00000000
+#define mmCPC_PERFCOUNTER0_SELECT_DEFAULT 0x11000401
+#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT 0x00000000
+#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT 0x00000000
+#define mmCPF_LATENCY_STATS_SELECT_DEFAULT 0x00000000
+#define mmCPG_LATENCY_STATS_SELECT_DEFAULT 0x00000000
+#define mmCPC_LATENCY_STATS_SELECT_DEFAULT 0x00000000
+#define mmCP_DRAW_OBJECT_DEFAULT 0x00000000
+#define mmCP_DRAW_OBJECT_COUNTER_DEFAULT 0x00000000
+#define mmCP_DRAW_WINDOW_MASK_HI_DEFAULT 0x00000000
+#define mmCP_DRAW_WINDOW_HI_DEFAULT 0x00000000
+#define mmCP_DRAW_WINDOW_LO_DEFAULT 0x00000000
+#define mmCP_DRAW_WINDOW_CNTL_DEFAULT 0x00000007
+#define mmGRBM_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmGRBM_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmGRBM_SE0_PERFCOUNTER_SELECT_DEFAULT 0x00000000
+#define mmGRBM_SE1_PERFCOUNTER_SELECT_DEFAULT 0x00000000
+#define mmGRBM_SE2_PERFCOUNTER_SELECT_DEFAULT 0x00000000
+#define mmGRBM_SE3_PERFCOUNTER_SELECT_DEFAULT 0x00000000
+#define mmWD_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmWD_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmWD_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
+#define mmWD_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
+#define mmIA_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmIA_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmIA_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
+#define mmIA_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
+#define mmIA_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmVGT_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmVGT_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmVGT_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
+#define mmVGT_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
+#define mmVGT_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmVGT_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000
+#define mmVGT_PERFCOUNTER_SEID_MASK_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER4_SELECT_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER5_SELECT_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER6_SELECT_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER7_SELECT_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
+#define mmSPI_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff
+#define mmSPI_PERFCOUNTER2_SELECT_DEFAULT 0x000fffff
+#define mmSPI_PERFCOUNTER3_SELECT_DEFAULT 0x000fffff
+#define mmSPI_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
+#define mmSPI_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff
+#define mmSPI_PERFCOUNTER2_SELECT1_DEFAULT 0x000fffff
+#define mmSPI_PERFCOUNTER3_SELECT1_DEFAULT 0x000fffff
+#define mmSPI_PERFCOUNTER4_SELECT_DEFAULT 0x000000ff
+#define mmSPI_PERFCOUNTER5_SELECT_DEFAULT 0x000000ff
+#define mmSPI_PERFCOUNTER_BINS_DEFAULT 0xfcb87430
+#define mmSQ_PERFCOUNTER0_SELECT_DEFAULT 0x0f0ff000
+#define mmSQ_PERFCOUNTER1_SELECT_DEFAULT 0x0f0ff000
+#define mmSQ_PERFCOUNTER2_SELECT_DEFAULT 0x0f0ff000
+#define mmSQ_PERFCOUNTER3_SELECT_DEFAULT 0x0f0ff000
+#define mmSQ_PERFCOUNTER4_SELECT_DEFAULT 0x0f0ff000
+#define mmSQ_PERFCOUNTER5_SELECT_DEFAULT 0x0f0ff000
+#define mmSQ_PERFCOUNTER6_SELECT_DEFAULT 0x0f0ff000
+#define mmSQ_PERFCOUNTER7_SELECT_DEFAULT 0x0f0ff000
+#define mmSQ_PERFCOUNTER8_SELECT_DEFAULT 0x0f0ff000
+#define mmSQ_PERFCOUNTER9_SELECT_DEFAULT 0x0f0ff000
+#define mmSQ_PERFCOUNTER10_SELECT_DEFAULT 0x0f0ff000
+#define mmSQ_PERFCOUNTER11_SELECT_DEFAULT 0x0f0ff000
+#define mmSQ_PERFCOUNTER12_SELECT_DEFAULT 0x0f0ff000
+#define mmSQ_PERFCOUNTER13_SELECT_DEFAULT 0x0f0ff000
+#define mmSQ_PERFCOUNTER14_SELECT_DEFAULT 0x0f0ff000
+#define mmSQ_PERFCOUNTER15_SELECT_DEFAULT 0x0f0ff000
+#define mmSQ_PERFCOUNTER_CTRL_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER_MASK_DEFAULT 0xffffffff
+#define mmSQ_PERFCOUNTER_CTRL2_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmTA_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmTA_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmTA_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmTD_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmTD_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmTD_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
+#define mmTCP_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
+#define mmTCP_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff
+#define mmTCP_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff
+#define mmTCP_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff
+#define mmTCP_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff
+#define mmTCC_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
+#define mmTCC_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
+#define mmTCC_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff
+#define mmTCC_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff
+#define mmTCC_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff
+#define mmTCC_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff
+#define mmTCA_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
+#define mmTCA_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
+#define mmTCA_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff
+#define mmTCA_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff
+#define mmTCA_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff
+#define mmTCA_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff
+#define mmCB_PERFCOUNTER_FILTER_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
+#define mmRLC_SPM_PERFMON_CNTL_DEFAULT 0x00000000
+#define mmRLC_SPM_PERFMON_RING_BASE_LO_DEFAULT 0x00000000
+#define mmRLC_SPM_PERFMON_RING_BASE_HI_DEFAULT 0x00000000
+#define mmRLC_SPM_PERFMON_RING_SIZE_DEFAULT 0x00000000
+#define mmRLC_SPM_PERFMON_SEGMENT_SIZE_DEFAULT 0x00000000
+#define mmRLC_SPM_SE_MUXSEL_ADDR_DEFAULT 0x00000000
+#define mmRLC_SPM_SE_MUXSEL_DATA_DEFAULT 0x00000000
+#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_DEFAULT 0x00000000
+#define mmRLC_SPM_GLOBAL_MUXSEL_DATA_DEFAULT 0x00000000
+#define mmRLC_SPM_RING_RDPTR_DEFAULT 0x00000000
+#define mmRLC_SPM_SEGMENT_THRESHOLD_DEFAULT 0x00000000
+#define mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
+#define mmRLC_PERFMON_CLK_CNTL_DEFAULT 0x00000001
+#define mmRLC_PERFMON_CNTL_DEFAULT 0x00000000
+#define mmRLC_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmRLC_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_PERF_CNT_CNTL_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER2_SELECT1_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
+#define mmRMI_PERF_COUNTER_CNTL_DEFAULT 0x00080240
+
+
+// addressBlock: gc_utcl2_atcl2pfcntldec
+#define mmATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+
+
+// addressBlock: gc_utcl2_vml2pldec
+#define mmMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000
+#define mmMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000
+#define mmMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000
+#define mmMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000
+#define mmMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000
+#define mmMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000
+#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+
+
+// addressBlock: gc_rlcpdec
+#define mmRLC_CNTL_DEFAULT 0x00000001
+#define mmRLC_STAT_DEFAULT 0x00000000
+#define mmRLC_SAFE_MODE_DEFAULT 0x00000000
+#define mmRLC_MEM_SLP_CNTL_DEFAULT 0x00020200
+#define mmSMU_RLC_RESPONSE_DEFAULT 0x00000000
+#define mmRLC_RLCV_SAFE_MODE_DEFAULT 0x00000000
+#define mmRLC_SMU_SAFE_MODE_DEFAULT 0x00000000
+#define mmRLC_RLCV_COMMAND_DEFAULT 0x00000000
+#define mmRLC_REFCLOCK_TIMESTAMP_LSB_DEFAULT 0x00000000
+#define mmRLC_REFCLOCK_TIMESTAMP_MSB_DEFAULT 0x00000000
+#define mmRLC_GPM_TIMER_INT_0_DEFAULT 0x00000000
+#define mmRLC_GPM_TIMER_INT_1_DEFAULT 0x00000000
+#define mmRLC_GPM_TIMER_INT_2_DEFAULT 0x00000000
+#define mmRLC_GPM_TIMER_CTRL_DEFAULT 0x00000000
+#define mmRLC_LB_CNTR_MAX_DEFAULT 0xffffffff
+#define mmRLC_GPM_TIMER_STAT_DEFAULT 0x00000000
+#define mmRLC_GPM_TIMER_INT_3_DEFAULT 0x00000000
+#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_1_DEFAULT 0x00000000
+#define mmRLC_SERDES_NONCU_MASTER_BUSY_1_DEFAULT 0x00000000
+#define mmRLC_INT_STAT_DEFAULT 0x00000000
+#define mmRLC_LB_CNTL_DEFAULT 0x00000010
+#define mmRLC_MGCG_CTRL_DEFAULT 0x00018800
+#define mmRLC_LB_CNTR_INIT_DEFAULT 0x00000000
+#define mmRLC_LOAD_BALANCE_CNTR_DEFAULT 0x00000000
+#define mmRLC_JUMP_TABLE_RESTORE_DEFAULT 0x00000000
+#define mmRLC_PG_DELAY_2_DEFAULT 0x00000004
+#define mmRLC_GPU_CLOCK_COUNT_LSB_DEFAULT 0x00000000
+#define mmRLC_GPU_CLOCK_COUNT_MSB_DEFAULT 0x00000000
+#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_DEFAULT 0x00000000
+#define mmRLC_UCODE_CNTL_DEFAULT 0x00000000
+#define mmRLC_GPM_THREAD_RESET_DEFAULT 0x0000000f
+#define mmRLC_GPM_CP_DMA_COMPLETE_T0_DEFAULT 0x00000000
+#define mmRLC_GPM_CP_DMA_COMPLETE_T1_DEFAULT 0x00000000
+#define mmRLC_FIREWALL_VIOLATION_DEFAULT 0x00000000
+#define mmRLC_GPM_STAT_DEFAULT 0x00100016
+#define mmRLC_GPU_CLOCK_32_RES_SEL_DEFAULT 0x00000000
+#define mmRLC_GPU_CLOCK_32_DEFAULT 0x00000000
+#define mmRLC_PG_CNTL_DEFAULT 0x00000000
+#define mmRLC_GPM_THREAD_PRIORITY_DEFAULT 0x08080808
+#define mmRLC_GPM_THREAD_ENABLE_DEFAULT 0x00000001
+#define mmRLC_CGTT_MGCG_OVERRIDE_DEFAULT 0xffffffff
+#define mmRLC_CGCG_CGLS_CTRL_DEFAULT 0x0001003c
+#define mmRLC_CGCG_RAMP_CTRL_DEFAULT 0x00021711
+#define mmRLC_DYN_PG_STATUS_DEFAULT 0xffffffff
+#define mmRLC_DYN_PG_REQUEST_DEFAULT 0xffffffff
+#define mmRLC_PG_DELAY_DEFAULT 0x00101010
+#define mmRLC_CU_STATUS_DEFAULT 0x00000000
+#define mmRLC_LB_INIT_CU_MASK_DEFAULT 0xffffffff
+#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK_DEFAULT 0x00000001
+#define mmRLC_LB_PARAMS_DEFAULT 0x00601008
+#define mmRLC_THREAD1_DELAY_DEFAULT 0x00400401
+#define mmRLC_PG_ALWAYS_ON_CU_MASK_DEFAULT 0x00000003
+#define mmRLC_MAX_PG_CU_DEFAULT 0x00000010
+#define mmRLC_AUTO_PG_CTRL_DEFAULT 0x00000000
+#define mmRLC_SMU_GRBM_REG_SAVE_CTRL_DEFAULT 0x00000000
+#define mmRLC_SERDES_RD_MASTER_INDEX_DEFAULT 0x00000000
+#define mmRLC_SERDES_RD_DATA_0_DEFAULT 0x00000000
+#define mmRLC_SERDES_RD_DATA_1_DEFAULT 0x00000000
+#define mmRLC_SERDES_RD_DATA_2_DEFAULT 0x00000000
+#define mmRLC_SERDES_WR_CU_MASTER_MASK_DEFAULT 0x00000000
+#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_DEFAULT 0x00000000
+#define mmRLC_SERDES_WR_CTRL_DEFAULT 0x00000000
+#define mmRLC_SERDES_WR_DATA_DEFAULT 0x00000000
+#define mmRLC_SERDES_CU_MASTER_BUSY_DEFAULT 0x00000000
+#define mmRLC_SERDES_NONCU_MASTER_BUSY_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_0_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_1_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_2_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_3_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_4_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_5_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_6_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_7_DEFAULT 0x00000000
+#define mmRLC_GPM_SCRATCH_ADDR_DEFAULT 0x00000000
+#define mmRLC_GPM_SCRATCH_DATA_DEFAULT 0x00000000
+#define mmRLC_STATIC_PG_STATUS_DEFAULT 0xffffffff
+#define mmRLC_SPM_MC_CNTL_DEFAULT 0x00000000
+#define mmRLC_SPM_INT_CNTL_DEFAULT 0x00000000
+#define mmRLC_SPM_INT_STATUS_DEFAULT 0x00000000
+#define mmRLC_SMU_MESSAGE_DEFAULT 0x00000000
+#define mmRLC_GPM_LOG_SIZE_DEFAULT 0x00000000
+#define mmRLC_PG_DELAY_3_DEFAULT 0x00000000
+#define mmRLC_GPR_REG1_DEFAULT 0x00000000
+#define mmRLC_GPR_REG2_DEFAULT 0x00000000
+#define mmRLC_GPM_LOG_CONT_DEFAULT 0x00000000
+#define mmRLC_GPM_INT_DISABLE_TH0_DEFAULT 0x00000000
+#define mmRLC_GPM_INT_DISABLE_TH1_DEFAULT 0x00000000
+#define mmRLC_GPM_INT_FORCE_TH0_DEFAULT 0x00000000
+#define mmRLC_GPM_INT_FORCE_TH1_DEFAULT 0x00000000
+#define mmRLC_SRM_CNTL_DEFAULT 0x00000002
+#define mmRLC_SRM_ARAM_ADDR_DEFAULT 0x00000000
+#define mmRLC_SRM_ARAM_DATA_DEFAULT 0x00000000
+#define mmRLC_SRM_DRAM_ADDR_DEFAULT 0x00000000
+#define mmRLC_SRM_DRAM_DATA_DEFAULT 0x00000000
+#define mmRLC_SRM_GPM_COMMAND_DEFAULT 0x00000000
+#define mmRLC_SRM_GPM_COMMAND_STATUS_DEFAULT 0x00000000
+#define mmRLC_SRM_RLCV_COMMAND_DEFAULT 0x00000000
+#define mmRLC_SRM_RLCV_COMMAND_STATUS_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_ADDR_0_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_ADDR_1_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_ADDR_2_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_ADDR_3_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_ADDR_4_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_ADDR_5_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_ADDR_6_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_ADDR_7_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_DATA_0_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_DATA_1_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_DATA_2_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_DATA_3_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_DATA_4_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_DATA_5_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_DATA_6_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_DATA_7_DEFAULT 0x00000000
+#define mmRLC_SRM_STAT_DEFAULT 0x00000000
+#define mmRLC_SRM_GPM_ABORT_DEFAULT 0x00000000
+#define mmRLC_CSIB_ADDR_LO_DEFAULT 0x00000000
+#define mmRLC_CSIB_ADDR_HI_DEFAULT 0x00000000
+#define mmRLC_CSIB_LENGTH_DEFAULT 0x00000000
+#define mmRLC_SMU_COMMAND_DEFAULT 0x00000000
+#define mmRLC_CP_SCHEDULERS_DEFAULT 0x58504840
+#define mmRLC_SMU_ARGUMENT_1_DEFAULT 0x00000000
+#define mmRLC_SMU_ARGUMENT_2_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_8_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_9_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_10_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_11_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_12_DEFAULT 0x00000000
+#define mmRLC_GPM_UTCL1_CNTL_0_DEFAULT 0x00000080
+#define mmRLC_GPM_UTCL1_CNTL_1_DEFAULT 0x00000080
+#define mmRLC_GPM_UTCL1_CNTL_2_DEFAULT 0x00000080
+#define mmRLC_SPM_UTCL1_CNTL_DEFAULT 0x00000080
+#define mmRLC_UTCL1_STATUS_2_DEFAULT 0x00000000
+#define mmRLC_LB_THR_CONFIG_2_DEFAULT 0x00000000
+#define mmRLC_LB_THR_CONFIG_3_DEFAULT 0x00000000
+#define mmRLC_LB_THR_CONFIG_4_DEFAULT 0x00000000
+#define mmRLC_SPM_UTCL1_ERROR_1_DEFAULT 0x00000000
+#define mmRLC_SPM_UTCL1_ERROR_2_DEFAULT 0x00000000
+#define mmRLC_GPM_UTCL1_TH0_ERROR_1_DEFAULT 0x00000000
+#define mmRLC_LB_THR_CONFIG_1_DEFAULT 0x00000000
+#define mmRLC_GPM_UTCL1_TH0_ERROR_2_DEFAULT 0x00000000
+#define mmRLC_GPM_UTCL1_TH1_ERROR_1_DEFAULT 0x00000000
+#define mmRLC_GPM_UTCL1_TH1_ERROR_2_DEFAULT 0x00000000
+#define mmRLC_GPM_UTCL1_TH2_ERROR_1_DEFAULT 0x00000000
+#define mmRLC_GPM_UTCL1_TH2_ERROR_2_DEFAULT 0x00000000
+#define mmRLC_CGCG_CGLS_CTRL_3D_DEFAULT 0x0001003c
+#define mmRLC_CGCG_RAMP_CTRL_3D_DEFAULT 0x00021711
+#define mmRLC_SEMAPHORE_0_DEFAULT 0x00000000
+#define mmRLC_SEMAPHORE_1_DEFAULT 0x00000000
+#define mmRLC_CP_EOF_INT_DEFAULT 0x00000000
+#define mmRLC_CP_EOF_INT_CNT_DEFAULT 0x00000000
+#define mmRLC_SPARE_INT_DEFAULT 0x00000000
+#define mmRLC_PREWALKER_UTCL1_CNTL_DEFAULT 0x00000080
+#define mmRLC_PREWALKER_UTCL1_TRIG_DEFAULT 0x00000000
+#define mmRLC_PREWALKER_UTCL1_ADDR_LSB_DEFAULT 0x00000000
+#define mmRLC_PREWALKER_UTCL1_ADDR_MSB_DEFAULT 0x00000000
+#define mmRLC_PREWALKER_UTCL1_SIZE_LSB_DEFAULT 0x00000000
+#define mmRLC_PREWALKER_UTCL1_SIZE_MSB_DEFAULT 0x00000000
+#define mmRLC_DSM_TRIG_DEFAULT 0x00000000
+#define mmRLC_UTCL1_STATUS_DEFAULT 0x00000000
+#define mmRLC_R2I_CNTL_0_DEFAULT 0x00000000
+#define mmRLC_R2I_CNTL_1_DEFAULT 0x00000000
+#define mmRLC_R2I_CNTL_2_DEFAULT 0x00000000
+#define mmRLC_R2I_CNTL_3_DEFAULT 0x00000000
+#define mmRLC_UTCL2_CNTL_DEFAULT 0x00000000
+#define mmRLC_LBPW_CU_STAT_DEFAULT 0x00000000
+#define mmRLC_DS_CNTL_DEFAULT 0x00030003
+#define mmRLC_RLCV_SPARE_INT_DEFAULT 0x00000000
+
+
+// addressBlock: gc_pwrdec
+#define mmCGTS_SM_CTRL_REG_DEFAULT 0x00600200
+#define mmCGTS_RD_CTRL_REG_DEFAULT 0x00000000
+#define mmCGTS_RD_REG_DEFAULT 0x00000000
+#define mmCGTS_TCC_DISABLE_DEFAULT 0x00000000
+#define mmCGTS_USER_TCC_DISABLE_DEFAULT 0x00000000
+#define mmCGTS_CU0_SP0_CTRL_REG_DEFAULT 0x00010000
+#define mmCGTS_CU0_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
+#define mmCGTS_CU0_TA_SQC_CTRL_REG_DEFAULT 0x00040007
+#define mmCGTS_CU0_SP1_CTRL_REG_DEFAULT 0x00060005
+#define mmCGTS_CU0_TD_TCP_CTRL_REG_DEFAULT 0x00090008
+#define mmCGTS_CU1_SP0_CTRL_REG_DEFAULT 0x00010000
+#define mmCGTS_CU1_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
+#define mmCGTS_CU1_TA_SQC_CTRL_REG_DEFAULT 0x00000007
+#define mmCGTS_CU1_SP1_CTRL_REG_DEFAULT 0x00060005
+#define mmCGTS_CU1_TD_TCP_CTRL_REG_DEFAULT 0x00090008
+#define mmCGTS_CU2_SP0_CTRL_REG_DEFAULT 0x00010000
+#define mmCGTS_CU2_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
+#define mmCGTS_CU2_TA_SQC_CTRL_REG_DEFAULT 0x00000007
+#define mmCGTS_CU2_SP1_CTRL_REG_DEFAULT 0x00060005
+#define mmCGTS_CU2_TD_TCP_CTRL_REG_DEFAULT 0x00090008
+#define mmCGTS_CU3_SP0_CTRL_REG_DEFAULT 0x00010000
+#define mmCGTS_CU3_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
+#define mmCGTS_CU3_TA_SQC_CTRL_REG_DEFAULT 0x00040007
+#define mmCGTS_CU3_SP1_CTRL_REG_DEFAULT 0x00060005
+#define mmCGTS_CU3_TD_TCP_CTRL_REG_DEFAULT 0x00090008
+#define mmCGTS_CU4_SP0_CTRL_REG_DEFAULT 0x00010000
+#define mmCGTS_CU4_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
+#define mmCGTS_CU4_TA_SQC_CTRL_REG_DEFAULT 0x00000007
+#define mmCGTS_CU4_SP1_CTRL_REG_DEFAULT 0x00060005
+#define mmCGTS_CU4_TD_TCP_CTRL_REG_DEFAULT 0x00090008
+#define mmCGTS_CU5_SP0_CTRL_REG_DEFAULT 0x00010000
+#define mmCGTS_CU5_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
+#define mmCGTS_CU5_TA_SQC_CTRL_REG_DEFAULT 0x00000007
+#define mmCGTS_CU5_SP1_CTRL_REG_DEFAULT 0x00060005
+#define mmCGTS_CU5_TD_TCP_CTRL_REG_DEFAULT 0x00090008
+#define mmCGTS_CU6_SP0_CTRL_REG_DEFAULT 0x00010000
+#define mmCGTS_CU6_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
+#define mmCGTS_CU6_TA_SQC_CTRL_REG_DEFAULT 0x00040007
+#define mmCGTS_CU6_SP1_CTRL_REG_DEFAULT 0x00060005
+#define mmCGTS_CU6_TD_TCP_CTRL_REG_DEFAULT 0x00090008
+#define mmCGTS_CU7_SP0_CTRL_REG_DEFAULT 0x00010000
+#define mmCGTS_CU7_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
+#define mmCGTS_CU7_TA_SQC_CTRL_REG_DEFAULT 0x00000007
+#define mmCGTS_CU7_SP1_CTRL_REG_DEFAULT 0x00060005
+#define mmCGTS_CU7_TD_TCP_CTRL_REG_DEFAULT 0x00090008
+#define mmCGTS_CU8_SP0_CTRL_REG_DEFAULT 0x00010000
+#define mmCGTS_CU8_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
+#define mmCGTS_CU8_TA_SQC_CTRL_REG_DEFAULT 0x00000007
+#define mmCGTS_CU8_SP1_CTRL_REG_DEFAULT 0x00060005
+#define mmCGTS_CU8_TD_TCP_CTRL_REG_DEFAULT 0x00090008
+#define mmCGTS_CU9_SP0_CTRL_REG_DEFAULT 0x00010000
+#define mmCGTS_CU9_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
+#define mmCGTS_CU9_TA_SQC_CTRL_REG_DEFAULT 0x00040007
+#define mmCGTS_CU9_SP1_CTRL_REG_DEFAULT 0x00060005
+#define mmCGTS_CU9_TD_TCP_CTRL_REG_DEFAULT 0x00090008
+#define mmCGTS_CU10_SP0_CTRL_REG_DEFAULT 0x00010000
+#define mmCGTS_CU10_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
+#define mmCGTS_CU10_TA_SQC_CTRL_REG_DEFAULT 0x00000007
+#define mmCGTS_CU10_SP1_CTRL_REG_DEFAULT 0x00060005
+#define mmCGTS_CU10_TD_TCP_CTRL_REG_DEFAULT 0x00090008
+#define mmCGTS_CU11_SP0_CTRL_REG_DEFAULT 0x00010000
+#define mmCGTS_CU11_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
+#define mmCGTS_CU11_TA_SQC_CTRL_REG_DEFAULT 0x00000007
+#define mmCGTS_CU11_SP1_CTRL_REG_DEFAULT 0x00060005
+#define mmCGTS_CU11_TD_TCP_CTRL_REG_DEFAULT 0x00090008
+#define mmCGTS_CU12_SP0_CTRL_REG_DEFAULT 0x00010000
+#define mmCGTS_CU12_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
+#define mmCGTS_CU12_TA_SQC_CTRL_REG_DEFAULT 0x00040007
+#define mmCGTS_CU12_SP1_CTRL_REG_DEFAULT 0x00060005
+#define mmCGTS_CU12_TD_TCP_CTRL_REG_DEFAULT 0x00090008
+#define mmCGTS_CU13_SP0_CTRL_REG_DEFAULT 0x00010000
+#define mmCGTS_CU13_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
+#define mmCGTS_CU13_TA_SQC_CTRL_REG_DEFAULT 0x00000007
+#define mmCGTS_CU13_SP1_CTRL_REG_DEFAULT 0x00060005
+#define mmCGTS_CU13_TD_TCP_CTRL_REG_DEFAULT 0x00090008
+#define mmCGTS_CU14_SP0_CTRL_REG_DEFAULT 0x00010000
+#define mmCGTS_CU14_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
+#define mmCGTS_CU14_TA_SQC_CTRL_REG_DEFAULT 0x00000007
+#define mmCGTS_CU14_SP1_CTRL_REG_DEFAULT 0x00060005
+#define mmCGTS_CU14_TD_TCP_CTRL_REG_DEFAULT 0x00090008
+#define mmCGTS_CU15_SP0_CTRL_REG_DEFAULT 0x00010000
+#define mmCGTS_CU15_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
+#define mmCGTS_CU15_TA_SQC_CTRL_REG_DEFAULT 0x00040007
+#define mmCGTS_CU15_SP1_CTRL_REG_DEFAULT 0x00060005
+#define mmCGTS_CU15_TD_TCP_CTRL_REG_DEFAULT 0x00090008
+#define mmCGTS_CU0_TCPI_CTRL_REG_DEFAULT 0x0000000a
+#define mmCGTS_CU1_TCPI_CTRL_REG_DEFAULT 0x00000001
+#define mmCGTS_CU2_TCPI_CTRL_REG_DEFAULT 0x0000000a
+#define mmCGTS_CU3_TCPI_CTRL_REG_DEFAULT 0x0000000a
+#define mmCGTS_CU4_TCPI_CTRL_REG_DEFAULT 0x0000000a
+#define mmCGTS_CU5_TCPI_CTRL_REG_DEFAULT 0x0000000a
+#define mmCGTS_CU6_TCPI_CTRL_REG_DEFAULT 0x0000000a
+#define mmCGTS_CU7_TCPI_CTRL_REG_DEFAULT 0x0000000a
+#define mmCGTS_CU8_TCPI_CTRL_REG_DEFAULT 0x0000000a
+#define mmCGTS_CU9_TCPI_CTRL_REG_DEFAULT 0x0000000a
+#define mmCGTS_CU10_TCPI_CTRL_REG_DEFAULT 0x0000000a
+#define mmCGTS_CU11_TCPI_CTRL_REG_DEFAULT 0x0000000a
+#define mmCGTS_CU12_TCPI_CTRL_REG_DEFAULT 0x0000000a
+#define mmCGTS_CU13_TCPI_CTRL_REG_DEFAULT 0x0000000a
+#define mmCGTS_CU14_TCPI_CTRL_REG_DEFAULT 0x0000000a
+#define mmCGTS_CU15_TCPI_CTRL_REG_DEFAULT 0x0000000a
+#define mmCGTT_SPI_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_PC_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_BCI_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_VGT_CLK_CTRL_DEFAULT 0x00018100
+#define mmCGTT_IA_CLK_CTRL_DEFAULT 0x06000100
+#define mmCGTT_WD_CLK_CTRL_DEFAULT 0x00018100
+#define mmCGTT_PA_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_SC_CLK_CTRL0_DEFAULT 0x00000100
+#define mmCGTT_SC_CLK_CTRL1_DEFAULT 0x00000100
+#define mmCGTT_SQ_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_SQG_CLK_CTRL_DEFAULT 0x00000100
+#define mmSQ_ALU_CLK_CTRL_DEFAULT 0x00000000
+#define mmSQ_TEX_CLK_CTRL_DEFAULT 0x00000000
+#define mmSQ_LDS_CLK_CTRL_DEFAULT 0x00000000
+#define mmSQ_POWER_THROTTLE_DEFAULT 0x3fff3fff
+#define mmSQ_POWER_THROTTLE2_DEFAULT 0x18800004
+#define mmCGTT_SX_CLK_CTRL0_DEFAULT 0x00000100
+#define mmCGTT_SX_CLK_CTRL1_DEFAULT 0x00000100
+#define mmCGTT_SX_CLK_CTRL2_DEFAULT 0x00000100
+#define mmCGTT_SX_CLK_CTRL3_DEFAULT 0x00000100
+#define mmCGTT_SX_CLK_CTRL4_DEFAULT 0x00000100
+#define mmTD_CGTT_CTRL_DEFAULT 0x00000100
+#define mmTA_CGTT_CTRL_DEFAULT 0x00000100
+#define mmCGTT_TCPI_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_TCI_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_GDS_CLK_CTRL_DEFAULT 0x00000100
+#define mmDB_CGTT_CLK_CTRL_0_DEFAULT 0x00000100
+#define mmCB_CGTT_SCLK_CTRL_DEFAULT 0x00000100
+#define mmTCC_CGTT_SCLK_CTRL_DEFAULT 0x00000100
+#define mmTCA_CGTT_SCLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_CP_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_CPF_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_CPC_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_RLC_CLK_CTRL_DEFAULT 0x00000100
+#define mmRLC_GFX_RM_CNTL_DEFAULT 0x00000000
+#define mmRMI_CGTT_SCLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_TCPF_CLK_CTRL_DEFAULT 0x00000100
+
+
+// addressBlock: gc_ea_pwrdec
+#define mmGCEA_CGTT_CLK_CTRL_DEFAULT 0x00000100
+
+
+// addressBlock: gc_utcl2_vmsharedhvdec
+#define mmMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000
+#define mmVM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100
+#define mmMC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000
+#define mmMC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000
+#define mmMC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000
+#define mmMC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000
+#define mmMC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000
+#define mmMC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000
+#define mmMC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000
+#define mmMC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000
+#define mmMC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000
+#define mmMC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000
+#define mmMC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000
+#define mmMC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000
+#define mmMC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000
+#define mmMC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000
+#define mmMC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000
+#define mmMC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000
+#define mmMC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000
+#define mmMC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000
+#define mmMC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000
+#define mmMC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000
+#define mmMC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000
+#define mmMC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000
+#define mmMC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000
+#define mmMC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000
+#define mmVM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000
+#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000
+#define mmUTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080
+
+
+// addressBlock: gc_hypdec
+#define mmCP_HYP_PFP_UCODE_ADDR_DEFAULT 0x00000000
+#define mmCP_PFP_UCODE_ADDR_DEFAULT 0x00000000
+#define mmCP_HYP_PFP_UCODE_DATA_DEFAULT 0x00000000
+#define mmCP_PFP_UCODE_DATA_DEFAULT 0x00000000
+#define mmCP_HYP_ME_UCODE_ADDR_DEFAULT 0x00000000
+#define mmCP_ME_RAM_RADDR_DEFAULT 0x00000000
+#define mmCP_ME_RAM_WADDR_DEFAULT 0x00000000
+#define mmCP_HYP_ME_UCODE_DATA_DEFAULT 0x00000000
+#define mmCP_ME_RAM_DATA_DEFAULT 0x00000000
+#define mmCP_CE_UCODE_ADDR_DEFAULT 0x00000000
+#define mmCP_HYP_CE_UCODE_ADDR_DEFAULT 0x00000000
+#define mmCP_CE_UCODE_DATA_DEFAULT 0x00000000
+#define mmCP_HYP_CE_UCODE_DATA_DEFAULT 0x00000000
+#define mmCP_HYP_MEC1_UCODE_ADDR_DEFAULT 0x00000000
+#define mmCP_MEC_ME1_UCODE_ADDR_DEFAULT 0x00000000
+#define mmCP_HYP_MEC1_UCODE_DATA_DEFAULT 0x00000000
+#define mmCP_MEC_ME1_UCODE_DATA_DEFAULT 0x00000000
+#define mmCP_HYP_MEC2_UCODE_ADDR_DEFAULT 0x00000000
+#define mmCP_MEC_ME2_UCODE_ADDR_DEFAULT 0x00000000
+#define mmCP_HYP_MEC2_UCODE_DATA_DEFAULT 0x00000000
+#define mmCP_MEC_ME2_UCODE_DATA_DEFAULT 0x00000000
+#define mmRLC_GPM_UCODE_ADDR_DEFAULT 0x00000000
+#define mmRLC_GPM_UCODE_DATA_DEFAULT 0x00000000
+#define mmGRBM_GFX_INDEX_SR_SELECT_DEFAULT 0x00000000
+#define mmGRBM_GFX_INDEX_SR_DATA_DEFAULT 0xe0000000
+#define mmGRBM_GFX_CNTL_SR_SELECT_DEFAULT 0x00000000
+#define mmGRBM_GFX_CNTL_SR_DATA_DEFAULT 0x00000000
+#define mmGRBM_CAM_INDEX_DEFAULT 0x00000000
+#define mmGRBM_HYP_CAM_INDEX_DEFAULT 0x00000000
+#define mmGRBM_CAM_DATA_DEFAULT 0x00000000
+#define mmGRBM_HYP_CAM_DATA_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_VF_ENABLE_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_CFG_REG6_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_CFG_REG8_DEFAULT 0x00000000
+#define mmRLC_RLCV_TIMER_INT_0_DEFAULT 0x00000000
+#define mmRLC_RLCV_TIMER_CTRL_DEFAULT 0x00000000
+#define mmRLC_RLCV_TIMER_STAT_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_DEFAULT 0x0000ffff
+#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_VF_MASK_DEFAULT 0x00010001
+#define mmRLC_HYP_SEMAPHORE_2_DEFAULT 0x00000000
+#define mmRLC_HYP_SEMAPHORE_3_DEFAULT 0x00000000
+#define mmRLC_CLK_CNTL_DEFAULT 0x00000003
+#define mmRLC_GPU_IOV_SCH_BLOCK_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_CFG_REG1_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_CFG_REG2_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_VM_BUSY_STATUS_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SCH_0_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_ACTIVE_FCN_ID_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SCH_3_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SCH_1_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SCH_2_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_UCODE_ADDR_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_UCODE_DATA_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SCRATCH_ADDR_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SCRATCH_DATA_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_F32_CNTL_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_F32_RESET_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SDMA0_STATUS_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SDMA1_STATUS_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SMU_RESPONSE_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_VIRT_RESET_REQ_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_RLC_RESPONSE_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_INT_DISABLE_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_INT_FORCE_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: gccacind
+#define ixGC_CAC_CNTL_DEFAULT 0x000001fe
+#define ixGC_CAC_OVR_SEL_DEFAULT 0x00000000
+#define ixGC_CAC_OVR_VAL_DEFAULT 0x00000000
+#define ixGC_CAC_WEIGHT_BCI_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_CB_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_CB_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_CBR_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_CBR_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_CP_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_CP_1_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_DB_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_DB_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_DBR_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_DBR_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_GDS_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_GDS_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_IA_0_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_LDS_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_LDS_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_PA_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_PC_0_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_SC_0_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_SPI_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_SPI_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_SPI_2_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_SQ_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_SQ_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_SQ_2_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_SQ_3_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_SQ_4_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_SX_0_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_SXRB_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_TA_0_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_TCC_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_TCC_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_TCC_2_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_TCP_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_TCP_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_TCP_2_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_TD_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_TD_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_TD_2_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_VGT_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_VGT_1_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_WD_0_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_CU_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_CU_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_CU_2_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_CU_3_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_CU_4_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_CU_5_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_CU_6_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_CU_7_DEFAULT 0x00010001
+#define ixGC_CAC_ACC_BCI0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CB0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CB1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CB2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CB3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CBR0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CBR1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CBR2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CBR3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CP0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CP1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CP2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_DB0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_DB1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_DB2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_DB3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_DBR0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_DBR1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_DBR2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_DBR3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_GDS0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_GDS1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_GDS2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_GDS3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_IA0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_LDS0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_LDS1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_LDS2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_LDS3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_PA0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_PA1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_PC0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SC0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SPI0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SPI1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SPI2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SPI3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SPI4_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SPI5_DEFAULT 0x00000000
+#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_0_DEFAULT 0x00010001
+#define ixGC_CAC_ACC_EA0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_EA1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_EA2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_EA3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ATCL20_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_EA_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_UTCL2_ATCL2_DEFAULT 0x00000000
+#define ixGC_CAC_WEIGHT_EA_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_EA_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_RMI_0_DEFAULT 0x00000001
+#define ixGC_CAC_ACC_RMI0_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_RMI_DEFAULT 0x00000000
+#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_1_DEFAULT 0x00010001
+#define ixGC_CAC_ACC_UTCL2_ATCL21_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ATCL22_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ATCL23_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_EA4_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_EA5_DEFAULT 0x00000000
+#define ixGC_CAC_WEIGHT_EA_2_DEFAULT 0x00010001
+#define ixGC_CAC_ACC_SQ0_LOWER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ0_UPPER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ1_LOWER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ1_UPPER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ2_LOWER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ2_UPPER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ3_LOWER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ3_UPPER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ4_LOWER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ4_UPPER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ5_LOWER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ5_UPPER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ6_LOWER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ6_UPPER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ7_LOWER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ7_UPPER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ8_LOWER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ8_UPPER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SX0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SXRB0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SXRB1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TA0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TCC0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TCC1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TCC2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TCC3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TCC4_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TCP0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TCP1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TCP2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TCP3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TCP4_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TD0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TD1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TD2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TD3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TD4_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TD5_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_VGT0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_VGT1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_VGT2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_WD0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CU0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CU1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CU2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CU3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CU4_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CU5_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CU6_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CU7_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CU8_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CU9_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CU10_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CU11_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CU12_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CU13_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CU14_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CU15_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_BCI_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_CB_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_CBR_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_CP_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_DB_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_DBR_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_GDS_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_IA_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_LDS_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_PA_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_PC_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_SC_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_SPI_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_CU_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_SQ_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_SX_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_SXRB_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_TA_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_TCC_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_TCP_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_TD_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_VGT_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_WD_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_BCI1_DEFAULT 0x00000000
+#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_2_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_2_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_3_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_4_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_VML2_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_VML2_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_VML2_2_DEFAULT 0x00010001
+#define ixGC_CAC_ACC_UTCL2_ATCL24_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ROUTER0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ROUTER1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ROUTER2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ROUTER3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ROUTER4_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ROUTER5_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ROUTER6_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ROUTER7_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ROUTER8_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ROUTER9_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_VML20_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_VML21_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_VML22_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_VML23_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_VML24_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_UTCL2_ROUTER_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_UTCL2_VML2_DEFAULT 0x00000000
+#define ixGC_CAC_WEIGHT_UTCL2_WALKER_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_WALKER_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_WALKER_2_DEFAULT 0x00010001
+#define ixGC_CAC_ACC_UTCL2_WALKER0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_WALKER1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_WALKER2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_WALKER3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_WALKER4_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_UTCL2_WALKER_DEFAULT 0x00000000
+
+
+// addressBlock: secacind
+#define ixSE_CAC_CNTL_DEFAULT 0x000001fe
+#define ixSE_CAC_OVR_SEL_DEFAULT 0x00000000
+#define ixSE_CAC_OVR_VAL_DEFAULT 0x00000000
+
+
+// addressBlock: sqind
+#define ixSQ_WAVE_MODE_DEFAULT 0x00000000
+#define ixSQ_WAVE_STATUS_DEFAULT 0x00000000
+#define ixSQ_WAVE_TRAPSTS_DEFAULT 0x00000000
+#define ixSQ_WAVE_HW_ID_DEFAULT 0x00000000
+#define ixSQ_WAVE_GPR_ALLOC_DEFAULT 0x00000000
+#define ixSQ_WAVE_LDS_ALLOC_DEFAULT 0x00000000
+#define ixSQ_WAVE_IB_STS_DEFAULT 0x00000000
+#define ixSQ_WAVE_PC_LO_DEFAULT 0x00000000
+#define ixSQ_WAVE_PC_HI_DEFAULT 0x00000000
+#define ixSQ_WAVE_INST_DW0_DEFAULT 0x00000000
+#define ixSQ_WAVE_INST_DW1_DEFAULT 0x00000000
+#define ixSQ_WAVE_IB_DBG0_DEFAULT 0x00000000
+#define ixSQ_WAVE_IB_DBG1_DEFAULT 0x00000000
+#define ixSQ_WAVE_FLUSH_IB_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP0_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP1_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP2_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP3_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP4_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP5_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP6_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP7_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP8_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP9_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP10_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP11_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP12_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP13_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP14_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP15_DEFAULT 0x00000000
+#define ixSQ_WAVE_M0_DEFAULT 0x00000000
+#define ixSQ_WAVE_EXEC_LO_DEFAULT 0x00000000
+#define ixSQ_WAVE_EXEC_HI_DEFAULT 0x00000000
+#define ixSQ_INTERRUPT_WORD_AUTO_CTXID_DEFAULT 0x00000000
+#define ixSQ_INTERRUPT_WORD_AUTO_HI_DEFAULT 0x00000000
+#define ixSQ_INTERRUPT_WORD_AUTO_LO_DEFAULT 0x00000000
+#define ixSQ_INTERRUPT_WORD_CMN_CTXID_DEFAULT 0x00000000
+#define ixSQ_INTERRUPT_WORD_CMN_HI_DEFAULT 0x00000000
+#define ixSQ_INTERRUPT_WORD_WAVE_CTXID_DEFAULT 0x00000000
+#define ixSQ_INTERRUPT_WORD_WAVE_HI_DEFAULT 0x00000000
+#define ixSQ_INTERRUPT_WORD_WAVE_LO_DEFAULT 0x00000000
+
+
+// addressBlock: didtind
+#define ixDIDT_SQ_CTRL0_DEFAULT 0x0000ff00
+#define ixDIDT_SQ_CTRL1_DEFAULT 0x00ff00ff
+#define ixDIDT_SQ_CTRL2_DEFAULT 0x18800004
+#define ixDIDT_SQ_STALL_CTRL_DEFAULT 0x00fff000
+#define ixDIDT_SQ_TUNING_CTRL_DEFAULT 0x00010004
+#define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff
+#define ixDIDT_SQ_CTRL3_DEFAULT 0x00038000
+#define ixDIDT_SQ_STALL_PATTERN_1_2_DEFAULT 0x01010001
+#define ixDIDT_SQ_STALL_PATTERN_3_4_DEFAULT 0x11110421
+#define ixDIDT_SQ_STALL_PATTERN_5_6_DEFAULT 0x25291249
+#define ixDIDT_SQ_STALL_PATTERN_7_DEFAULT 0x00002aaa
+#define ixDIDT_SQ_WEIGHT0_3_DEFAULT 0x00000000
+#define ixDIDT_SQ_WEIGHT4_7_DEFAULT 0x00000000
+#define ixDIDT_SQ_WEIGHT8_11_DEFAULT 0x00000000
+#define ixDIDT_SQ_EDC_CTRL_DEFAULT 0x00001c00
+#define ixDIDT_SQ_EDC_THRESHOLD_DEFAULT 0x00000000
+#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001
+#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421
+#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249
+#define ixDIDT_SQ_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa
+#define ixDIDT_SQ_EDC_STATUS_DEFAULT 0x00000000
+#define ixDIDT_SQ_EDC_STALL_DELAY_1_DEFAULT 0x00000000
+#define ixDIDT_SQ_EDC_STALL_DELAY_2_DEFAULT 0x00000000
+#define ixDIDT_SQ_EDC_STALL_DELAY_3_DEFAULT 0x00000000
+#define ixDIDT_SQ_EDC_STALL_DELAY_4_DEFAULT 0x00000000
+#define ixDIDT_SQ_EDC_OVERFLOW_DEFAULT 0x00000000
+#define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
+#define ixDIDT_DB_CTRL0_DEFAULT 0x0000ff00
+#define ixDIDT_DB_CTRL1_DEFAULT 0x00ff00ff
+#define ixDIDT_DB_CTRL2_DEFAULT 0x18800004
+#define ixDIDT_DB_STALL_CTRL_DEFAULT 0x00fff000
+#define ixDIDT_DB_TUNING_CTRL_DEFAULT 0x00010004
+#define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff
+#define ixDIDT_DB_CTRL3_DEFAULT 0x00038000
+#define ixDIDT_DB_STALL_PATTERN_1_2_DEFAULT 0x01010001
+#define ixDIDT_DB_STALL_PATTERN_3_4_DEFAULT 0x11110421
+#define ixDIDT_DB_STALL_PATTERN_5_6_DEFAULT 0x25291249
+#define ixDIDT_DB_STALL_PATTERN_7_DEFAULT 0x00002aaa
+#define ixDIDT_DB_WEIGHT0_3_DEFAULT 0x00000000
+#define ixDIDT_DB_WEIGHT4_7_DEFAULT 0x00000000
+#define ixDIDT_DB_WEIGHT8_11_DEFAULT 0x00000000
+#define ixDIDT_DB_EDC_CTRL_DEFAULT 0x00001c00
+#define ixDIDT_DB_EDC_THRESHOLD_DEFAULT 0x00000000
+#define ixDIDT_DB_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001
+#define ixDIDT_DB_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421
+#define ixDIDT_DB_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249
+#define ixDIDT_DB_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa
+#define ixDIDT_DB_EDC_STATUS_DEFAULT 0x00000000
+#define ixDIDT_DB_EDC_STALL_DELAY_1_DEFAULT 0x00000000
+#define ixDIDT_DB_EDC_OVERFLOW_DEFAULT 0x00000000
+#define ixDIDT_DB_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
+#define ixDIDT_TD_CTRL0_DEFAULT 0x0000ff00
+#define ixDIDT_TD_CTRL1_DEFAULT 0x00ff00ff
+#define ixDIDT_TD_CTRL2_DEFAULT 0x18800004
+#define ixDIDT_TD_STALL_CTRL_DEFAULT 0x00fff000
+#define ixDIDT_TD_TUNING_CTRL_DEFAULT 0x00010004
+#define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff
+#define ixDIDT_TD_CTRL3_DEFAULT 0x00038000
+#define ixDIDT_TD_STALL_PATTERN_1_2_DEFAULT 0x01010001
+#define ixDIDT_TD_STALL_PATTERN_3_4_DEFAULT 0x11110421
+#define ixDIDT_TD_STALL_PATTERN_5_6_DEFAULT 0x25291249
+#define ixDIDT_TD_STALL_PATTERN_7_DEFAULT 0x00002aaa
+#define ixDIDT_TD_WEIGHT0_3_DEFAULT 0x00000000
+#define ixDIDT_TD_WEIGHT4_7_DEFAULT 0x00000000
+#define ixDIDT_TD_WEIGHT8_11_DEFAULT 0x00000000
+#define ixDIDT_TD_EDC_CTRL_DEFAULT 0x00001c00
+#define ixDIDT_TD_EDC_THRESHOLD_DEFAULT 0x00000000
+#define ixDIDT_TD_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001
+#define ixDIDT_TD_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421
+#define ixDIDT_TD_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249
+#define ixDIDT_TD_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa
+#define ixDIDT_TD_EDC_STATUS_DEFAULT 0x00000000
+#define ixDIDT_TD_EDC_STALL_DELAY_1_DEFAULT 0x00000000
+#define ixDIDT_TD_EDC_STALL_DELAY_2_DEFAULT 0x00000000
+#define ixDIDT_TD_EDC_STALL_DELAY_3_DEFAULT 0x00000000
+#define ixDIDT_TD_EDC_STALL_DELAY_4_DEFAULT 0x00000000
+#define ixDIDT_TD_EDC_OVERFLOW_DEFAULT 0x00000000
+#define ixDIDT_TD_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
+#define ixDIDT_TCP_CTRL0_DEFAULT 0x0000ff00
+#define ixDIDT_TCP_CTRL1_DEFAULT 0x00ff00ff
+#define ixDIDT_TCP_CTRL2_DEFAULT 0x18800004
+#define ixDIDT_TCP_STALL_CTRL_DEFAULT 0x00fff000
+#define ixDIDT_TCP_TUNING_CTRL_DEFAULT 0x00010004
+#define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff
+#define ixDIDT_TCP_CTRL3_DEFAULT 0x00038000
+#define ixDIDT_TCP_STALL_PATTERN_1_2_DEFAULT 0x01010001
+#define ixDIDT_TCP_STALL_PATTERN_3_4_DEFAULT 0x11110421
+#define ixDIDT_TCP_STALL_PATTERN_5_6_DEFAULT 0x25291249
+#define ixDIDT_TCP_STALL_PATTERN_7_DEFAULT 0x00002aaa
+#define ixDIDT_TCP_WEIGHT0_3_DEFAULT 0x00000000
+#define ixDIDT_TCP_WEIGHT4_7_DEFAULT 0x00000000
+#define ixDIDT_TCP_WEIGHT8_11_DEFAULT 0x00000000
+#define ixDIDT_TCP_EDC_CTRL_DEFAULT 0x00001c00
+#define ixDIDT_TCP_EDC_THRESHOLD_DEFAULT 0x00000000
+#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001
+#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421
+#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249
+#define ixDIDT_TCP_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa
+#define ixDIDT_TCP_EDC_STATUS_DEFAULT 0x00000000
+#define ixDIDT_TCP_EDC_STALL_DELAY_1_DEFAULT 0x00000000
+#define ixDIDT_TCP_EDC_STALL_DELAY_2_DEFAULT 0x00000000
+#define ixDIDT_TCP_EDC_STALL_DELAY_3_DEFAULT 0x00000000
+#define ixDIDT_TCP_EDC_STALL_DELAY_4_DEFAULT 0x00000000
+#define ixDIDT_TCP_EDC_OVERFLOW_DEFAULT 0x00000000
+#define ixDIDT_TCP_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
+#define ixDIDT_DBR_CTRL0_DEFAULT 0x0000ff00
+#define ixDIDT_DBR_CTRL1_DEFAULT 0x00ff00ff
+#define ixDIDT_DBR_CTRL2_DEFAULT 0x18800004
+#define ixDIDT_DBR_STALL_CTRL_DEFAULT 0x00fff000
+#define ixDIDT_DBR_TUNING_CTRL_DEFAULT 0x00010004
+#define ixDIDT_DBR_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff
+#define ixDIDT_DBR_CTRL3_DEFAULT 0x00038000
+#define ixDIDT_DBR_STALL_PATTERN_1_2_DEFAULT 0x01010001
+#define ixDIDT_DBR_STALL_PATTERN_3_4_DEFAULT 0x11110421
+#define ixDIDT_DBR_STALL_PATTERN_5_6_DEFAULT 0x25291249
+#define ixDIDT_DBR_STALL_PATTERN_7_DEFAULT 0x00002aaa
+#define ixDIDT_DBR_WEIGHT0_3_DEFAULT 0x00000000
+#define ixDIDT_DBR_WEIGHT4_7_DEFAULT 0x00000000
+#define ixDIDT_DBR_WEIGHT8_11_DEFAULT 0x00000000
+#define ixDIDT_DBR_EDC_CTRL_DEFAULT 0x00001c00
+#define ixDIDT_DBR_EDC_THRESHOLD_DEFAULT 0x00000000
+#define ixDIDT_DBR_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001
+#define ixDIDT_DBR_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421
+#define ixDIDT_DBR_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249
+#define ixDIDT_DBR_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa
+#define ixDIDT_DBR_EDC_STATUS_DEFAULT 0x00000000
+#define ixDIDT_DBR_EDC_STALL_DELAY_1_DEFAULT 0x00000000
+#define ixDIDT_DBR_EDC_OVERFLOW_DEFAULT 0x00000000
+#define ixDIDT_DBR_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
+#define ixDIDT_SQ_STALL_EVENT_COUNTER_DEFAULT 0x00000000
+#define ixDIDT_DB_STALL_EVENT_COUNTER_DEFAULT 0x00000000
+#define ixDIDT_TD_STALL_EVENT_COUNTER_DEFAULT 0x00000000
+#define ixDIDT_TCP_STALL_EVENT_COUNTER_DEFAULT 0x00000000
+#define ixDIDT_DBR_STALL_EVENT_COUNTER_DEFAULT 0x00000000
+
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_offset.h
new file mode 100644
index 000000000000..e6d6171aa8b9
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_offset.h
@@ -0,0 +1,7230 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _gc_9_0_OFFSET_HEADER
+#define _gc_9_0_OFFSET_HEADER
+
+
+
+// addressBlock: gc_grbmdec
+// base address: 0x8000
+#define mmGRBM_CNTL 0x0000
+#define mmGRBM_CNTL_BASE_IDX 0
+#define mmGRBM_SKEW_CNTL 0x0001
+#define mmGRBM_SKEW_CNTL_BASE_IDX 0
+#define mmGRBM_STATUS2 0x0002
+#define mmGRBM_STATUS2_BASE_IDX 0
+#define mmGRBM_PWR_CNTL 0x0003
+#define mmGRBM_PWR_CNTL_BASE_IDX 0
+#define mmGRBM_STATUS 0x0004
+#define mmGRBM_STATUS_BASE_IDX 0
+#define mmGRBM_STATUS_SE0 0x0005
+#define mmGRBM_STATUS_SE0_BASE_IDX 0
+#define mmGRBM_STATUS_SE1 0x0006
+#define mmGRBM_STATUS_SE1_BASE_IDX 0
+#define mmGRBM_SOFT_RESET 0x0008
+#define mmGRBM_SOFT_RESET_BASE_IDX 0
+#define mmGRBM_CGTT_CLK_CNTL 0x000b
+#define mmGRBM_CGTT_CLK_CNTL_BASE_IDX 0
+#define mmGRBM_GFX_CLKEN_CNTL 0x000c
+#define mmGRBM_GFX_CLKEN_CNTL_BASE_IDX 0
+#define mmGRBM_WAIT_IDLE_CLOCKS 0x000d
+#define mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0
+#define mmGRBM_STATUS_SE2 0x000e
+#define mmGRBM_STATUS_SE2_BASE_IDX 0
+#define mmGRBM_STATUS_SE3 0x000f
+#define mmGRBM_STATUS_SE3_BASE_IDX 0
+#define mmGRBM_READ_ERROR 0x0016
+#define mmGRBM_READ_ERROR_BASE_IDX 0
+#define mmGRBM_READ_ERROR2 0x0017
+#define mmGRBM_READ_ERROR2_BASE_IDX 0
+#define mmGRBM_INT_CNTL 0x0018
+#define mmGRBM_INT_CNTL_BASE_IDX 0
+#define mmGRBM_TRAP_OP 0x0019
+#define mmGRBM_TRAP_OP_BASE_IDX 0
+#define mmGRBM_TRAP_ADDR 0x001a
+#define mmGRBM_TRAP_ADDR_BASE_IDX 0
+#define mmGRBM_TRAP_ADDR_MSK 0x001b
+#define mmGRBM_TRAP_ADDR_MSK_BASE_IDX 0
+#define mmGRBM_TRAP_WD 0x001c
+#define mmGRBM_TRAP_WD_BASE_IDX 0
+#define mmGRBM_TRAP_WD_MSK 0x001d
+#define mmGRBM_TRAP_WD_MSK_BASE_IDX 0
+#define mmGRBM_DSM_BYPASS 0x001e
+#define mmGRBM_DSM_BYPASS_BASE_IDX 0
+#define mmGRBM_WRITE_ERROR 0x001f
+#define mmGRBM_WRITE_ERROR_BASE_IDX 0
+#define mmGRBM_IOV_ERROR 0x0020
+#define mmGRBM_IOV_ERROR_BASE_IDX 0
+#define mmGRBM_CHIP_REVISION 0x0021
+#define mmGRBM_CHIP_REVISION_BASE_IDX 0
+#define mmGRBM_GFX_CNTL 0x0022
+#define mmGRBM_GFX_CNTL_BASE_IDX 0
+#define mmGRBM_RSMU_CFG 0x0023
+#define mmGRBM_RSMU_CFG_BASE_IDX 0
+#define mmGRBM_IH_CREDIT 0x0024
+#define mmGRBM_IH_CREDIT_BASE_IDX 0
+#define mmGRBM_PWR_CNTL2 0x0025
+#define mmGRBM_PWR_CNTL2_BASE_IDX 0
+#define mmGRBM_UTCL2_INVAL_RANGE_START 0x0026
+#define mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0
+#define mmGRBM_UTCL2_INVAL_RANGE_END 0x0027
+#define mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0
+#define mmGRBM_RSMU_READ_ERROR 0x0028
+#define mmGRBM_RSMU_READ_ERROR_BASE_IDX 0
+#define mmGRBM_CHICKEN_BITS 0x0029
+#define mmGRBM_CHICKEN_BITS_BASE_IDX 0
+#define mmGRBM_NOWHERE 0x003f
+#define mmGRBM_NOWHERE_BASE_IDX 0
+#define mmGRBM_SCRATCH_REG0 0x0040
+#define mmGRBM_SCRATCH_REG0_BASE_IDX 0
+#define mmGRBM_SCRATCH_REG1 0x0041
+#define mmGRBM_SCRATCH_REG1_BASE_IDX 0
+#define mmGRBM_SCRATCH_REG2 0x0042
+#define mmGRBM_SCRATCH_REG2_BASE_IDX 0
+#define mmGRBM_SCRATCH_REG3 0x0043
+#define mmGRBM_SCRATCH_REG3_BASE_IDX 0
+#define mmGRBM_SCRATCH_REG4 0x0044
+#define mmGRBM_SCRATCH_REG4_BASE_IDX 0
+#define mmGRBM_SCRATCH_REG5 0x0045
+#define mmGRBM_SCRATCH_REG5_BASE_IDX 0
+#define mmGRBM_SCRATCH_REG6 0x0046
+#define mmGRBM_SCRATCH_REG6_BASE_IDX 0
+#define mmGRBM_SCRATCH_REG7 0x0047
+#define mmGRBM_SCRATCH_REG7_BASE_IDX 0
+
+
+// addressBlock: gc_cpdec
+// base address: 0x8200
+#define mmCP_CPC_STATUS 0x0084
+#define mmCP_CPC_STATUS_BASE_IDX 0
+#define mmCP_CPC_BUSY_STAT 0x0085
+#define mmCP_CPC_BUSY_STAT_BASE_IDX 0
+#define mmCP_CPC_STALLED_STAT1 0x0086
+#define mmCP_CPC_STALLED_STAT1_BASE_IDX 0
+#define mmCP_CPF_STATUS 0x0087
+#define mmCP_CPF_STATUS_BASE_IDX 0
+#define mmCP_CPF_BUSY_STAT 0x0088
+#define mmCP_CPF_BUSY_STAT_BASE_IDX 0
+#define mmCP_CPF_STALLED_STAT1 0x0089
+#define mmCP_CPF_STALLED_STAT1_BASE_IDX 0
+#define mmCP_CPC_GRBM_FREE_COUNT 0x008b
+#define mmCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0
+#define mmCP_MEC_CNTL 0x008d
+#define mmCP_MEC_CNTL_BASE_IDX 0
+#define mmCP_MEC_ME1_HEADER_DUMP 0x008e
+#define mmCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0
+#define mmCP_MEC_ME2_HEADER_DUMP 0x008f
+#define mmCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0
+#define mmCP_CPC_SCRATCH_INDEX 0x0090
+#define mmCP_CPC_SCRATCH_INDEX_BASE_IDX 0
+#define mmCP_CPC_SCRATCH_DATA 0x0091
+#define mmCP_CPC_SCRATCH_DATA_BASE_IDX 0
+#define mmCP_CPF_GRBM_FREE_COUNT 0x0092
+#define mmCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0
+#define mmCP_CPC_HALT_HYST_COUNT 0x00a7
+#define mmCP_CPC_HALT_HYST_COUNT_BASE_IDX 0
+#define mmCP_PRT_LOD_STATS_CNTL0 0x00ad
+#define mmCP_PRT_LOD_STATS_CNTL0_BASE_IDX 0
+#define mmCP_PRT_LOD_STATS_CNTL1 0x00ae
+#define mmCP_PRT_LOD_STATS_CNTL1_BASE_IDX 0
+#define mmCP_PRT_LOD_STATS_CNTL2 0x00af
+#define mmCP_PRT_LOD_STATS_CNTL2_BASE_IDX 0
+#define mmCP_PRT_LOD_STATS_CNTL3 0x00b0
+#define mmCP_PRT_LOD_STATS_CNTL3_BASE_IDX 0
+#define mmCP_CE_COMPARE_COUNT 0x00c0
+#define mmCP_CE_COMPARE_COUNT_BASE_IDX 0
+#define mmCP_CE_DE_COUNT 0x00c1
+#define mmCP_CE_DE_COUNT_BASE_IDX 0
+#define mmCP_DE_CE_COUNT 0x00c2
+#define mmCP_DE_CE_COUNT_BASE_IDX 0
+#define mmCP_DE_LAST_INVAL_COUNT 0x00c3
+#define mmCP_DE_LAST_INVAL_COUNT_BASE_IDX 0
+#define mmCP_DE_DE_COUNT 0x00c4
+#define mmCP_DE_DE_COUNT_BASE_IDX 0
+#define mmCP_STALLED_STAT3 0x019c
+#define mmCP_STALLED_STAT3_BASE_IDX 0
+#define mmCP_STALLED_STAT1 0x019d
+#define mmCP_STALLED_STAT1_BASE_IDX 0
+#define mmCP_STALLED_STAT2 0x019e
+#define mmCP_STALLED_STAT2_BASE_IDX 0
+#define mmCP_BUSY_STAT 0x019f
+#define mmCP_BUSY_STAT_BASE_IDX 0
+#define mmCP_STAT 0x01a0
+#define mmCP_STAT_BASE_IDX 0
+#define mmCP_ME_HEADER_DUMP 0x01a1
+#define mmCP_ME_HEADER_DUMP_BASE_IDX 0
+#define mmCP_PFP_HEADER_DUMP 0x01a2
+#define mmCP_PFP_HEADER_DUMP_BASE_IDX 0
+#define mmCP_GRBM_FREE_COUNT 0x01a3
+#define mmCP_GRBM_FREE_COUNT_BASE_IDX 0
+#define mmCP_CE_HEADER_DUMP 0x01a4
+#define mmCP_CE_HEADER_DUMP_BASE_IDX 0
+#define mmCP_PFP_INSTR_PNTR 0x01a5
+#define mmCP_PFP_INSTR_PNTR_BASE_IDX 0
+#define mmCP_ME_INSTR_PNTR 0x01a6
+#define mmCP_ME_INSTR_PNTR_BASE_IDX 0
+#define mmCP_CE_INSTR_PNTR 0x01a7
+#define mmCP_CE_INSTR_PNTR_BASE_IDX 0
+#define mmCP_MEC1_INSTR_PNTR 0x01a8
+#define mmCP_MEC1_INSTR_PNTR_BASE_IDX 0
+#define mmCP_MEC2_INSTR_PNTR 0x01a9
+#define mmCP_MEC2_INSTR_PNTR_BASE_IDX 0
+#define mmCP_CSF_STAT 0x01b4
+#define mmCP_CSF_STAT_BASE_IDX 0
+#define mmCP_ME_CNTL 0x01b6
+#define mmCP_ME_CNTL_BASE_IDX 0
+#define mmCP_CNTX_STAT 0x01b8
+#define mmCP_CNTX_STAT_BASE_IDX 0
+#define mmCP_ME_PREEMPTION 0x01b9
+#define mmCP_ME_PREEMPTION_BASE_IDX 0
+#define mmCP_ROQ_THRESHOLDS 0x01bc
+#define mmCP_ROQ_THRESHOLDS_BASE_IDX 0
+#define mmCP_MEQ_STQ_THRESHOLD 0x01bd
+#define mmCP_MEQ_STQ_THRESHOLD_BASE_IDX 0
+#define mmCP_RB2_RPTR 0x01be
+#define mmCP_RB2_RPTR_BASE_IDX 0
+#define mmCP_RB1_RPTR 0x01bf
+#define mmCP_RB1_RPTR_BASE_IDX 0
+#define mmCP_RB0_RPTR 0x01c0
+#define mmCP_RB0_RPTR_BASE_IDX 0
+#define mmCP_RB_RPTR 0x01c0
+#define mmCP_RB_RPTR_BASE_IDX 0
+#define mmCP_RB_WPTR_DELAY 0x01c1
+#define mmCP_RB_WPTR_DELAY_BASE_IDX 0
+#define mmCP_RB_WPTR_POLL_CNTL 0x01c2
+#define mmCP_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmCP_ROQ1_THRESHOLDS 0x01d5
+#define mmCP_ROQ1_THRESHOLDS_BASE_IDX 0
+#define mmCP_ROQ2_THRESHOLDS 0x01d6
+#define mmCP_ROQ2_THRESHOLDS_BASE_IDX 0
+#define mmCP_STQ_THRESHOLDS 0x01d7
+#define mmCP_STQ_THRESHOLDS_BASE_IDX 0
+#define mmCP_QUEUE_THRESHOLDS 0x01d8
+#define mmCP_QUEUE_THRESHOLDS_BASE_IDX 0
+#define mmCP_MEQ_THRESHOLDS 0x01d9
+#define mmCP_MEQ_THRESHOLDS_BASE_IDX 0
+#define mmCP_ROQ_AVAIL 0x01da
+#define mmCP_ROQ_AVAIL_BASE_IDX 0
+#define mmCP_STQ_AVAIL 0x01db
+#define mmCP_STQ_AVAIL_BASE_IDX 0
+#define mmCP_ROQ2_AVAIL 0x01dc
+#define mmCP_ROQ2_AVAIL_BASE_IDX 0
+#define mmCP_MEQ_AVAIL 0x01dd
+#define mmCP_MEQ_AVAIL_BASE_IDX 0
+#define mmCP_CMD_INDEX 0x01de
+#define mmCP_CMD_INDEX_BASE_IDX 0
+#define mmCP_CMD_DATA 0x01df
+#define mmCP_CMD_DATA_BASE_IDX 0
+#define mmCP_ROQ_RB_STAT 0x01e0
+#define mmCP_ROQ_RB_STAT_BASE_IDX 0
+#define mmCP_ROQ_IB1_STAT 0x01e1
+#define mmCP_ROQ_IB1_STAT_BASE_IDX 0
+#define mmCP_ROQ_IB2_STAT 0x01e2
+#define mmCP_ROQ_IB2_STAT_BASE_IDX 0
+#define mmCP_STQ_STAT 0x01e3
+#define mmCP_STQ_STAT_BASE_IDX 0
+#define mmCP_STQ_WR_STAT 0x01e4
+#define mmCP_STQ_WR_STAT_BASE_IDX 0
+#define mmCP_MEQ_STAT 0x01e5
+#define mmCP_MEQ_STAT_BASE_IDX 0
+#define mmCP_CEQ1_AVAIL 0x01e6
+#define mmCP_CEQ1_AVAIL_BASE_IDX 0
+#define mmCP_CEQ2_AVAIL 0x01e7
+#define mmCP_CEQ2_AVAIL_BASE_IDX 0
+#define mmCP_CE_ROQ_RB_STAT 0x01e8
+#define mmCP_CE_ROQ_RB_STAT_BASE_IDX 0
+#define mmCP_CE_ROQ_IB1_STAT 0x01e9
+#define mmCP_CE_ROQ_IB1_STAT_BASE_IDX 0
+#define mmCP_CE_ROQ_IB2_STAT 0x01ea
+#define mmCP_CE_ROQ_IB2_STAT_BASE_IDX 0
+#define mmCP_INT_STAT_DEBUG 0x01f7
+#define mmCP_INT_STAT_DEBUG_BASE_IDX 0
+
+
+// addressBlock: gc_padec
+// base address: 0x8800
+#define mmVGT_VTX_VECT_EJECT_REG 0x022c
+#define mmVGT_VTX_VECT_EJECT_REG_BASE_IDX 0
+#define mmVGT_DMA_DATA_FIFO_DEPTH 0x022d
+#define mmVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0
+#define mmVGT_DMA_REQ_FIFO_DEPTH 0x022e
+#define mmVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0
+#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x022f
+#define mmVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0
+#define mmVGT_LAST_COPY_STATE 0x0230
+#define mmVGT_LAST_COPY_STATE_BASE_IDX 0
+#define mmVGT_CACHE_INVALIDATION 0x0231
+#define mmVGT_CACHE_INVALIDATION_BASE_IDX 0
+#define mmVGT_RESET_DEBUG 0x0232
+#define mmVGT_RESET_DEBUG_BASE_IDX 0
+#define mmVGT_STRMOUT_DELAY 0x0233
+#define mmVGT_STRMOUT_DELAY_BASE_IDX 0
+#define mmVGT_FIFO_DEPTHS 0x0234
+#define mmVGT_FIFO_DEPTHS_BASE_IDX 0
+#define mmVGT_GS_VERTEX_REUSE 0x0235
+#define mmVGT_GS_VERTEX_REUSE_BASE_IDX 0
+#define mmVGT_MC_LAT_CNTL 0x0236
+#define mmVGT_MC_LAT_CNTL_BASE_IDX 0
+#define mmIA_CNTL_STATUS 0x0237
+#define mmIA_CNTL_STATUS_BASE_IDX 0
+#define mmVGT_CNTL_STATUS 0x023c
+#define mmVGT_CNTL_STATUS_BASE_IDX 0
+#define mmWD_CNTL_STATUS 0x023f
+#define mmWD_CNTL_STATUS_BASE_IDX 0
+#define mmCC_GC_PRIM_CONFIG 0x0240
+#define mmCC_GC_PRIM_CONFIG_BASE_IDX 0
+#define mmGC_USER_PRIM_CONFIG 0x0241
+#define mmGC_USER_PRIM_CONFIG_BASE_IDX 0
+#define mmWD_QOS 0x0242
+#define mmWD_QOS_BASE_IDX 0
+#define mmWD_UTCL1_CNTL 0x0243
+#define mmWD_UTCL1_CNTL_BASE_IDX 0
+#define mmWD_UTCL1_STATUS 0x0244
+#define mmWD_UTCL1_STATUS_BASE_IDX 0
+#define mmIA_UTCL1_CNTL 0x0246
+#define mmIA_UTCL1_CNTL_BASE_IDX 0
+#define mmIA_UTCL1_STATUS 0x0247
+#define mmIA_UTCL1_STATUS_BASE_IDX 0
+#define mmVGT_SYS_CONFIG 0x0263
+#define mmVGT_SYS_CONFIG_BASE_IDX 0
+#define mmVGT_VS_MAX_WAVE_ID 0x0268
+#define mmVGT_VS_MAX_WAVE_ID_BASE_IDX 0
+#define mmVGT_GS_MAX_WAVE_ID 0x0269
+#define mmVGT_GS_MAX_WAVE_ID_BASE_IDX 0
+#define mmGFX_PIPE_CONTROL 0x026d
+#define mmGFX_PIPE_CONTROL_BASE_IDX 0
+#define mmCC_GC_SHADER_ARRAY_CONFIG 0x026f
+#define mmCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0
+#define mmGC_USER_SHADER_ARRAY_CONFIG 0x0270
+#define mmGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 0
+#define mmVGT_DMA_PRIMITIVE_TYPE 0x0271
+#define mmVGT_DMA_PRIMITIVE_TYPE_BASE_IDX 0
+#define mmVGT_DMA_CONTROL 0x0272
+#define mmVGT_DMA_CONTROL_BASE_IDX 0
+#define mmVGT_DMA_LS_HS_CONFIG 0x0273
+#define mmVGT_DMA_LS_HS_CONFIG_BASE_IDX 0
+#define mmWD_BUF_RESOURCE_1 0x0276
+#define mmWD_BUF_RESOURCE_1_BASE_IDX 0
+#define mmWD_BUF_RESOURCE_2 0x0277
+#define mmWD_BUF_RESOURCE_2_BASE_IDX 0
+#define mmPA_CL_CNTL_STATUS 0x0284
+#define mmPA_CL_CNTL_STATUS_BASE_IDX 0
+#define mmPA_CL_ENHANCE 0x0285
+#define mmPA_CL_ENHANCE_BASE_IDX 0
+#define mmPA_CL_RESET_DEBUG 0x0286
+#define mmPA_CL_RESET_DEBUG_BASE_IDX 0
+#define mmPA_SU_CNTL_STATUS 0x0294
+#define mmPA_SU_CNTL_STATUS_BASE_IDX 0
+#define mmPA_SC_FIFO_DEPTH_CNTL 0x0295
+#define mmPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0
+#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x02c0
+#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0
+#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x02c1
+#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0
+#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x02c2
+#define mmPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 0
+#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x02c9
+#define mmPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 0
+#define mmPA_SC_BINNER_EVENT_CNTL_0 0x02cc
+#define mmPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 0
+#define mmPA_SC_BINNER_EVENT_CNTL_1 0x02cd
+#define mmPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 0
+#define mmPA_SC_BINNER_EVENT_CNTL_2 0x02ce
+#define mmPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 0
+#define mmPA_SC_BINNER_EVENT_CNTL_3 0x02cf
+#define mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 0
+#define mmPA_SC_BINNER_TIMEOUT_COUNTER 0x02d0
+#define mmPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 0
+#define mmPA_SC_BINNER_PERF_CNTL_0 0x02d1
+#define mmPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 0
+#define mmPA_SC_BINNER_PERF_CNTL_1 0x02d2
+#define mmPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 0
+#define mmPA_SC_BINNER_PERF_CNTL_2 0x02d3
+#define mmPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 0
+#define mmPA_SC_BINNER_PERF_CNTL_3 0x02d4
+#define mmPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 0
+#define mmPA_SC_FIFO_SIZE 0x02f3
+#define mmPA_SC_FIFO_SIZE_BASE_IDX 0
+#define mmPA_SC_IF_FIFO_SIZE 0x02f5
+#define mmPA_SC_IF_FIFO_SIZE_BASE_IDX 0
+#define mmPA_SC_PKR_WAVE_TABLE_CNTL 0x02f8
+#define mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 0
+#define mmPA_UTCL1_CNTL1 0x02f9
+#define mmPA_UTCL1_CNTL1_BASE_IDX 0
+#define mmPA_UTCL1_CNTL2 0x02fa
+#define mmPA_UTCL1_CNTL2_BASE_IDX 0
+#define mmPA_SIDEBAND_REQUEST_DELAYS 0x02fb
+#define mmPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX 0
+#define mmPA_SC_ENHANCE 0x02fc
+#define mmPA_SC_ENHANCE_BASE_IDX 0
+#define mmPA_SC_ENHANCE_1 0x02fd
+#define mmPA_SC_ENHANCE_1_BASE_IDX 0
+#define mmPA_SC_DSM_CNTL 0x02fe
+#define mmPA_SC_DSM_CNTL_BASE_IDX 0
+#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE 0x02ff
+#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 0
+
+
+// addressBlock: gc_sqdec
+// base address: 0x8c00
+#define mmSQ_CONFIG 0x0300
+#define mmSQ_CONFIG_BASE_IDX 0
+#define mmSQC_CONFIG 0x0301
+#define mmSQC_CONFIG_BASE_IDX 0
+#define mmLDS_CONFIG 0x0302
+#define mmLDS_CONFIG_BASE_IDX 0
+#define mmSQ_RANDOM_WAVE_PRI 0x0303
+#define mmSQ_RANDOM_WAVE_PRI_BASE_IDX 0
+#define mmSQ_REG_CREDITS 0x0304
+#define mmSQ_REG_CREDITS_BASE_IDX 0
+#define mmSQ_FIFO_SIZES 0x0305
+#define mmSQ_FIFO_SIZES_BASE_IDX 0
+#define mmSQ_DSM_CNTL 0x0306
+#define mmSQ_DSM_CNTL_BASE_IDX 0
+#define mmSQ_DSM_CNTL2 0x0307
+#define mmSQ_DSM_CNTL2_BASE_IDX 0
+#define mmSQ_RUNTIME_CONFIG 0x0308
+#define mmSQ_RUNTIME_CONFIG_BASE_IDX 0
+#define mmSH_MEM_BASES 0x030a
+#define mmSH_MEM_BASES_BASE_IDX 0
+#define mmSH_MEM_CONFIG 0x030d
+#define mmSH_MEM_CONFIG_BASE_IDX 0
+#define mmCC_GC_SHADER_RATE_CONFIG 0x0312
+#define mmCC_GC_SHADER_RATE_CONFIG_BASE_IDX 0
+#define mmGC_USER_SHADER_RATE_CONFIG 0x0313
+#define mmGC_USER_SHADER_RATE_CONFIG_BASE_IDX 0
+#define mmSQ_INTERRUPT_AUTO_MASK 0x0314
+#define mmSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0
+#define mmSQ_INTERRUPT_MSG_CTRL 0x0315
+#define mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0
+#define mmSQ_UTCL1_CNTL1 0x0317
+#define mmSQ_UTCL1_CNTL1_BASE_IDX 0
+#define mmSQ_UTCL1_CNTL2 0x0318
+#define mmSQ_UTCL1_CNTL2_BASE_IDX 0
+#define mmSQ_UTCL1_STATUS 0x0319
+#define mmSQ_UTCL1_STATUS_BASE_IDX 0
+#define mmSQ_SHADER_TBA_LO 0x031c
+#define mmSQ_SHADER_TBA_LO_BASE_IDX 0
+#define mmSQ_SHADER_TBA_HI 0x031d
+#define mmSQ_SHADER_TBA_HI_BASE_IDX 0
+#define mmSQ_SHADER_TMA_LO 0x031e
+#define mmSQ_SHADER_TMA_LO_BASE_IDX 0
+#define mmSQ_SHADER_TMA_HI 0x031f
+#define mmSQ_SHADER_TMA_HI_BASE_IDX 0
+#define mmSQC_DSM_CNTL 0x0320
+#define mmSQC_DSM_CNTL_BASE_IDX 0
+#define mmSQC_DSM_CNTLA 0x0321
+#define mmSQC_DSM_CNTLA_BASE_IDX 0
+#define mmSQC_DSM_CNTLB 0x0322
+#define mmSQC_DSM_CNTLB_BASE_IDX 0
+#define mmSQC_DSM_CNTL2 0x0325
+#define mmSQC_DSM_CNTL2_BASE_IDX 0
+#define mmSQC_DSM_CNTL2A 0x0326
+#define mmSQC_DSM_CNTL2A_BASE_IDX 0
+#define mmSQC_DSM_CNTL2B 0x0327
+#define mmSQC_DSM_CNTL2B_BASE_IDX 0
+#define mmSQC_EDC_FUE_CNTL 0x032b
+#define mmSQC_EDC_FUE_CNTL_BASE_IDX 0
+#define mmSQC_EDC_CNT2 0x032c
+#define mmSQC_EDC_CNT2_BASE_IDX 0
+#define mmSQC_EDC_CNT3 0x032d
+#define mmSQC_EDC_CNT3_BASE_IDX 0
+#define mmSQ_REG_TIMESTAMP 0x0374
+#define mmSQ_REG_TIMESTAMP_BASE_IDX 0
+#define mmSQ_CMD_TIMESTAMP 0x0375
+#define mmSQ_CMD_TIMESTAMP_BASE_IDX 0
+#define mmSQ_IND_INDEX 0x0378
+#define mmSQ_IND_INDEX_BASE_IDX 0
+#define mmSQ_IND_DATA 0x0379
+#define mmSQ_IND_DATA_BASE_IDX 0
+#define mmSQ_CMD 0x037b
+#define mmSQ_CMD_BASE_IDX 0
+#define mmSQ_TIME_HI 0x037c
+#define mmSQ_TIME_HI_BASE_IDX 0
+#define mmSQ_TIME_LO 0x037d
+#define mmSQ_TIME_LO_BASE_IDX 0
+#define mmSQ_DS_0 0x037f
+#define mmSQ_DS_0_BASE_IDX 0
+#define mmSQ_DS_1 0x037f
+#define mmSQ_DS_1_BASE_IDX 0
+#define mmSQ_EXP_0 0x037f
+#define mmSQ_EXP_0_BASE_IDX 0
+#define mmSQ_EXP_1 0x037f
+#define mmSQ_EXP_1_BASE_IDX 0
+#define mmSQ_FLAT_0 0x037f
+#define mmSQ_FLAT_0_BASE_IDX 0
+#define mmSQ_FLAT_1 0x037f
+#define mmSQ_FLAT_1_BASE_IDX 0
+#define mmSQ_GLBL_0 0x037f
+#define mmSQ_GLBL_0_BASE_IDX 0
+#define mmSQ_GLBL_1 0x037f
+#define mmSQ_GLBL_1_BASE_IDX 0
+#define mmSQ_INST 0x037f
+#define mmSQ_INST_BASE_IDX 0
+#define mmSQ_MIMG_0 0x037f
+#define mmSQ_MIMG_0_BASE_IDX 0
+#define mmSQ_MIMG_1 0x037f
+#define mmSQ_MIMG_1_BASE_IDX 0
+#define mmSQ_MTBUF_0 0x037f
+#define mmSQ_MTBUF_0_BASE_IDX 0
+#define mmSQ_MTBUF_1 0x037f
+#define mmSQ_MTBUF_1_BASE_IDX 0
+#define mmSQ_MUBUF_0 0x037f
+#define mmSQ_MUBUF_0_BASE_IDX 0
+#define mmSQ_MUBUF_1 0x037f
+#define mmSQ_MUBUF_1_BASE_IDX 0
+#define mmSQ_SCRATCH_0 0x037f
+#define mmSQ_SCRATCH_0_BASE_IDX 0
+#define mmSQ_SCRATCH_1 0x037f
+#define mmSQ_SCRATCH_1_BASE_IDX 0
+#define mmSQ_SMEM_0 0x037f
+#define mmSQ_SMEM_0_BASE_IDX 0
+#define mmSQ_SMEM_1 0x037f
+#define mmSQ_SMEM_1_BASE_IDX 0
+#define mmSQ_SOP1 0x037f
+#define mmSQ_SOP1_BASE_IDX 0
+#define mmSQ_SOP2 0x037f
+#define mmSQ_SOP2_BASE_IDX 0
+#define mmSQ_SOPC 0x037f
+#define mmSQ_SOPC_BASE_IDX 0
+#define mmSQ_SOPK 0x037f
+#define mmSQ_SOPK_BASE_IDX 0
+#define mmSQ_SOPP 0x037f
+#define mmSQ_SOPP_BASE_IDX 0
+#define mmSQ_VINTRP 0x037f
+#define mmSQ_VINTRP_BASE_IDX 0
+#define mmSQ_VOP1 0x037f
+#define mmSQ_VOP1_BASE_IDX 0
+#define mmSQ_VOP2 0x037f
+#define mmSQ_VOP2_BASE_IDX 0
+#define mmSQ_VOP3P_0 0x037f
+#define mmSQ_VOP3P_0_BASE_IDX 0
+#define mmSQ_VOP3P_1 0x037f
+#define mmSQ_VOP3P_1_BASE_IDX 0
+#define mmSQ_VOP3_0 0x037f
+#define mmSQ_VOP3_0_BASE_IDX 0
+#define mmSQ_VOP3_0_SDST_ENC 0x037f
+#define mmSQ_VOP3_0_SDST_ENC_BASE_IDX 0
+#define mmSQ_VOP3_1 0x037f
+#define mmSQ_VOP3_1_BASE_IDX 0
+#define mmSQ_VOPC 0x037f
+#define mmSQ_VOPC_BASE_IDX 0
+#define mmSQ_VOP_DPP 0x037f
+#define mmSQ_VOP_DPP_BASE_IDX 0
+#define mmSQ_VOP_SDWA 0x037f
+#define mmSQ_VOP_SDWA_BASE_IDX 0
+#define mmSQ_VOP_SDWA_SDST_ENC 0x037f
+#define mmSQ_VOP_SDWA_SDST_ENC_BASE_IDX 0
+#define mmSQ_LB_CTR_CTRL 0x0398
+#define mmSQ_LB_CTR_CTRL_BASE_IDX 0
+#define mmSQ_LB_DATA0 0x0399
+#define mmSQ_LB_DATA0_BASE_IDX 0
+#define mmSQ_LB_DATA1 0x039a
+#define mmSQ_LB_DATA1_BASE_IDX 0
+#define mmSQ_LB_DATA2 0x039b
+#define mmSQ_LB_DATA2_BASE_IDX 0
+#define mmSQ_LB_DATA3 0x039c
+#define mmSQ_LB_DATA3_BASE_IDX 0
+#define mmSQ_LB_CTR_SEL 0x039d
+#define mmSQ_LB_CTR_SEL_BASE_IDX 0
+#define mmSQ_LB_CTR0_CU 0x039e
+#define mmSQ_LB_CTR0_CU_BASE_IDX 0
+#define mmSQ_LB_CTR1_CU 0x039f
+#define mmSQ_LB_CTR1_CU_BASE_IDX 0
+#define mmSQ_LB_CTR2_CU 0x03a0
+#define mmSQ_LB_CTR2_CU_BASE_IDX 0
+#define mmSQ_LB_CTR3_CU 0x03a1
+#define mmSQ_LB_CTR3_CU_BASE_IDX 0
+#define mmSQC_EDC_CNT 0x03a2
+#define mmSQC_EDC_CNT_BASE_IDX 0
+#define mmSQ_EDC_SEC_CNT 0x03a3
+#define mmSQ_EDC_SEC_CNT_BASE_IDX 0
+#define mmSQ_EDC_DED_CNT 0x03a4
+#define mmSQ_EDC_DED_CNT_BASE_IDX 0
+#define mmSQ_EDC_INFO 0x03a5
+#define mmSQ_EDC_INFO_BASE_IDX 0
+#define mmSQ_EDC_CNT 0x03a6
+#define mmSQ_EDC_CNT_BASE_IDX 0
+#define mmSQ_EDC_FUE_CNTL 0x03a7
+#define mmSQ_EDC_FUE_CNTL_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_WORD_CMN 0x03b0
+#define mmSQ_THREAD_TRACE_WORD_CMN_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_WORD_EVENT 0x03b0
+#define mmSQ_THREAD_TRACE_WORD_EVENT_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_WORD_INST 0x03b0
+#define mmSQ_THREAD_TRACE_WORD_INST_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x03b0
+#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x03b0
+#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x03b0
+#define mmSQ_THREAD_TRACE_WORD_ISSUE_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_WORD_MISC 0x03b0
+#define mmSQ_THREAD_TRACE_WORD_MISC_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x03b0
+#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x03b0
+#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x03b0
+#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x03b0
+#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x03b0
+#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x03b0
+#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_WORD_WAVE 0x03b0
+#define mmSQ_THREAD_TRACE_WORD_WAVE_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x03b0
+#define mmSQ_THREAD_TRACE_WORD_WAVE_START_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x03b1
+#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x03b1
+#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x03b1
+#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x03b1
+#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_BASE_IDX 0
+#define mmSQ_WREXEC_EXEC_HI 0x03b1
+#define mmSQ_WREXEC_EXEC_HI_BASE_IDX 0
+#define mmSQ_WREXEC_EXEC_LO 0x03b1
+#define mmSQ_WREXEC_EXEC_LO_BASE_IDX 0
+#define mmSQ_BUF_RSRC_WORD0 0x03c0
+#define mmSQ_BUF_RSRC_WORD0_BASE_IDX 0
+#define mmSQ_BUF_RSRC_WORD1 0x03c1
+#define mmSQ_BUF_RSRC_WORD1_BASE_IDX 0
+#define mmSQ_BUF_RSRC_WORD2 0x03c2
+#define mmSQ_BUF_RSRC_WORD2_BASE_IDX 0
+#define mmSQ_BUF_RSRC_WORD3 0x03c3
+#define mmSQ_BUF_RSRC_WORD3_BASE_IDX 0
+#define mmSQ_IMG_RSRC_WORD0 0x03c4
+#define mmSQ_IMG_RSRC_WORD0_BASE_IDX 0
+#define mmSQ_IMG_RSRC_WORD1 0x03c5
+#define mmSQ_IMG_RSRC_WORD1_BASE_IDX 0
+#define mmSQ_IMG_RSRC_WORD2 0x03c6
+#define mmSQ_IMG_RSRC_WORD2_BASE_IDX 0
+#define mmSQ_IMG_RSRC_WORD3 0x03c7
+#define mmSQ_IMG_RSRC_WORD3_BASE_IDX 0
+#define mmSQ_IMG_RSRC_WORD4 0x03c8
+#define mmSQ_IMG_RSRC_WORD4_BASE_IDX 0
+#define mmSQ_IMG_RSRC_WORD5 0x03c9
+#define mmSQ_IMG_RSRC_WORD5_BASE_IDX 0
+#define mmSQ_IMG_RSRC_WORD6 0x03ca
+#define mmSQ_IMG_RSRC_WORD6_BASE_IDX 0
+#define mmSQ_IMG_RSRC_WORD7 0x03cb
+#define mmSQ_IMG_RSRC_WORD7_BASE_IDX 0
+#define mmSQ_IMG_SAMP_WORD0 0x03cc
+#define mmSQ_IMG_SAMP_WORD0_BASE_IDX 0
+#define mmSQ_IMG_SAMP_WORD1 0x03cd
+#define mmSQ_IMG_SAMP_WORD1_BASE_IDX 0
+#define mmSQ_IMG_SAMP_WORD2 0x03ce
+#define mmSQ_IMG_SAMP_WORD2_BASE_IDX 0
+#define mmSQ_IMG_SAMP_WORD3 0x03cf
+#define mmSQ_IMG_SAMP_WORD3_BASE_IDX 0
+#define mmSQ_FLAT_SCRATCH_WORD0 0x03d0
+#define mmSQ_FLAT_SCRATCH_WORD0_BASE_IDX 0
+#define mmSQ_FLAT_SCRATCH_WORD1 0x03d1
+#define mmSQ_FLAT_SCRATCH_WORD1_BASE_IDX 0
+#define mmSQ_M0_GPR_IDX_WORD 0x03d2
+#define mmSQ_M0_GPR_IDX_WORD_BASE_IDX 0
+#define mmSQC_ICACHE_UTCL1_CNTL1 0x03d3
+#define mmSQC_ICACHE_UTCL1_CNTL1_BASE_IDX 0
+#define mmSQC_ICACHE_UTCL1_CNTL2 0x03d4
+#define mmSQC_ICACHE_UTCL1_CNTL2_BASE_IDX 0
+#define mmSQC_DCACHE_UTCL1_CNTL1 0x03d5
+#define mmSQC_DCACHE_UTCL1_CNTL1_BASE_IDX 0
+#define mmSQC_DCACHE_UTCL1_CNTL2 0x03d6
+#define mmSQC_DCACHE_UTCL1_CNTL2_BASE_IDX 0
+#define mmSQC_ICACHE_UTCL1_STATUS 0x03d7
+#define mmSQC_ICACHE_UTCL1_STATUS_BASE_IDX 0
+#define mmSQC_DCACHE_UTCL1_STATUS 0x03d8
+#define mmSQC_DCACHE_UTCL1_STATUS_BASE_IDX 0
+
+
+// addressBlock: gc_shsdec
+// base address: 0x9000
+#define mmSX_DEBUG_BUSY 0x0414
+#define mmSX_DEBUG_BUSY_BASE_IDX 0
+#define mmSX_DEBUG_BUSY_2 0x0415
+#define mmSX_DEBUG_BUSY_2_BASE_IDX 0
+#define mmSX_DEBUG_BUSY_3 0x0416
+#define mmSX_DEBUG_BUSY_3_BASE_IDX 0
+#define mmSX_DEBUG_BUSY_4 0x0417
+#define mmSX_DEBUG_BUSY_4_BASE_IDX 0
+#define mmSX_DEBUG_BUSY_5 0x0418
+#define mmSX_DEBUG_BUSY_5_BASE_IDX 0
+#define mmSX_DEBUG_1 0x0419
+#define mmSX_DEBUG_1_BASE_IDX 0
+#define mmSPI_PS_MAX_WAVE_ID 0x043a
+#define mmSPI_PS_MAX_WAVE_ID_BASE_IDX 0
+#define mmSPI_START_PHASE 0x043b
+#define mmSPI_START_PHASE_BASE_IDX 0
+#define mmSPI_GFX_CNTL 0x043c
+#define mmSPI_GFX_CNTL_BASE_IDX 0
+#define mmSPI_DEBUG_READ 0x0442
+#define mmSPI_DEBUG_READ_BASE_IDX 0
+#define mmSPI_DSM_CNTL 0x0443
+#define mmSPI_DSM_CNTL_BASE_IDX 0
+#define mmSPI_DSM_CNTL2 0x0444
+#define mmSPI_DSM_CNTL2_BASE_IDX 0
+#define mmSPI_EDC_CNT 0x0445
+#define mmSPI_EDC_CNT_BASE_IDX 0
+#define mmSPI_DEBUG_BUSY 0x0450
+#define mmSPI_DEBUG_BUSY_BASE_IDX 0
+#define mmSPI_CONFIG_PS_CU_EN 0x0452
+#define mmSPI_CONFIG_PS_CU_EN_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_CNTL 0x04aa
+#define mmSPI_WF_LIFETIME_CNTL_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_LIMIT_0 0x04ab
+#define mmSPI_WF_LIFETIME_LIMIT_0_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_LIMIT_1 0x04ac
+#define mmSPI_WF_LIFETIME_LIMIT_1_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_LIMIT_2 0x04ad
+#define mmSPI_WF_LIFETIME_LIMIT_2_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_LIMIT_3 0x04ae
+#define mmSPI_WF_LIFETIME_LIMIT_3_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_LIMIT_4 0x04af
+#define mmSPI_WF_LIFETIME_LIMIT_4_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_LIMIT_5 0x04b0
+#define mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_LIMIT_6 0x04b1
+#define mmSPI_WF_LIFETIME_LIMIT_6_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_LIMIT_7 0x04b2
+#define mmSPI_WF_LIFETIME_LIMIT_7_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_LIMIT_8 0x04b3
+#define mmSPI_WF_LIFETIME_LIMIT_8_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_LIMIT_9 0x04b4
+#define mmSPI_WF_LIFETIME_LIMIT_9_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_0 0x04b5
+#define mmSPI_WF_LIFETIME_STATUS_0_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_1 0x04b6
+#define mmSPI_WF_LIFETIME_STATUS_1_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_2 0x04b7
+#define mmSPI_WF_LIFETIME_STATUS_2_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_3 0x04b8
+#define mmSPI_WF_LIFETIME_STATUS_3_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_4 0x04b9
+#define mmSPI_WF_LIFETIME_STATUS_4_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_5 0x04ba
+#define mmSPI_WF_LIFETIME_STATUS_5_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_6 0x04bb
+#define mmSPI_WF_LIFETIME_STATUS_6_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_7 0x04bc
+#define mmSPI_WF_LIFETIME_STATUS_7_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_8 0x04bd
+#define mmSPI_WF_LIFETIME_STATUS_8_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_9 0x04be
+#define mmSPI_WF_LIFETIME_STATUS_9_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_10 0x04bf
+#define mmSPI_WF_LIFETIME_STATUS_10_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_11 0x04c0
+#define mmSPI_WF_LIFETIME_STATUS_11_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_12 0x04c1
+#define mmSPI_WF_LIFETIME_STATUS_12_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_13 0x04c2
+#define mmSPI_WF_LIFETIME_STATUS_13_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_14 0x04c3
+#define mmSPI_WF_LIFETIME_STATUS_14_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_15 0x04c4
+#define mmSPI_WF_LIFETIME_STATUS_15_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_16 0x04c5
+#define mmSPI_WF_LIFETIME_STATUS_16_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_17 0x04c6
+#define mmSPI_WF_LIFETIME_STATUS_17_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_18 0x04c7
+#define mmSPI_WF_LIFETIME_STATUS_18_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_19 0x04c8
+#define mmSPI_WF_LIFETIME_STATUS_19_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_20 0x04c9
+#define mmSPI_WF_LIFETIME_STATUS_20_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_DEBUG 0x04ca
+#define mmSPI_WF_LIFETIME_DEBUG_BASE_IDX 0
+#define mmSPI_LB_CTR_CTRL 0x04d4
+#define mmSPI_LB_CTR_CTRL_BASE_IDX 0
+#define mmSPI_LB_CU_MASK 0x04d5
+#define mmSPI_LB_CU_MASK_BASE_IDX 0
+#define mmSPI_LB_DATA_REG 0x04d6
+#define mmSPI_LB_DATA_REG_BASE_IDX 0
+#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x04d7
+#define mmSPI_PG_ENABLE_STATIC_CU_MASK_BASE_IDX 0
+#define mmSPI_GDS_CREDITS 0x04d8
+#define mmSPI_GDS_CREDITS_BASE_IDX 0
+#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x04d9
+#define mmSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX 0
+#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x04da
+#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX 0
+#define mmSPI_CSQ_WF_ACTIVE_STATUS 0x04db
+#define mmSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX 0
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x04dc
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX 0
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x04dd
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX 0
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x04de
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX 0
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x04df
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX 0
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x04e0
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_4_BASE_IDX 0
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x04e1
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_5_BASE_IDX 0
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x04e2
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_6_BASE_IDX 0
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x04e3
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_7_BASE_IDX 0
+#define mmSPI_LB_DATA_WAVES 0x04e4
+#define mmSPI_LB_DATA_WAVES_BASE_IDX 0
+#define mmSPI_LB_DATA_PERCU_WAVE_HSGS 0x04e5
+#define mmSPI_LB_DATA_PERCU_WAVE_HSGS_BASE_IDX 0
+#define mmSPI_LB_DATA_PERCU_WAVE_VSPS 0x04e6
+#define mmSPI_LB_DATA_PERCU_WAVE_VSPS_BASE_IDX 0
+#define mmSPI_LB_DATA_PERCU_WAVE_CS 0x04e7
+#define mmSPI_LB_DATA_PERCU_WAVE_CS_BASE_IDX 0
+#define mmSPIS_DEBUG_READ 0x04ea
+#define mmSPIS_DEBUG_READ_BASE_IDX 0
+#define mmBCI_DEBUG_READ 0x04eb
+#define mmBCI_DEBUG_READ_BASE_IDX 0
+#define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x04ec
+#define mmSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX 0
+#define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x04ed
+#define mmSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX 0
+#define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x04ee
+#define mmSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX 0
+#define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x04ef
+#define mmSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX 0
+#define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x04f0
+#define mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 0
+#define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x04f1
+#define mmSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX 0
+#define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x04f2
+#define mmSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX 0
+#define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x04f3
+#define mmSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX 0
+#define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x04f4
+#define mmSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX 0
+#define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x04f5
+#define mmSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX 0
+
+
+// addressBlock: gc_tpdec
+// base address: 0x9400
+#define mmTD_CNTL 0x0525
+#define mmTD_CNTL_BASE_IDX 0
+#define mmTD_STATUS 0x0526
+#define mmTD_STATUS_BASE_IDX 0
+#define mmTD_DSM_CNTL 0x052f
+#define mmTD_DSM_CNTL_BASE_IDX 0
+#define mmTD_DSM_CNTL2 0x0530
+#define mmTD_DSM_CNTL2_BASE_IDX 0
+#define mmTD_SCRATCH 0x0533
+#define mmTD_SCRATCH_BASE_IDX 0
+#define mmTA_CNTL 0x0541
+#define mmTA_CNTL_BASE_IDX 0
+#define mmTA_CNTL_AUX 0x0542
+#define mmTA_CNTL_AUX_BASE_IDX 0
+#define mmTA_RESERVED_010C 0x0543
+#define mmTA_RESERVED_010C_BASE_IDX 0
+#define mmTA_GRAD_ADJ 0x0544
+#define mmTA_GRAD_ADJ_BASE_IDX 0
+#define mmTA_STATUS 0x0548
+#define mmTA_STATUS_BASE_IDX 0
+#define mmTA_SCRATCH 0x0564
+#define mmTA_SCRATCH_BASE_IDX 0
+
+
+// addressBlock: gc_gdsdec
+// base address: 0x9700
+#define mmGDS_CONFIG 0x05c0
+#define mmGDS_CONFIG_BASE_IDX 0
+#define mmGDS_CNTL_STATUS 0x05c1
+#define mmGDS_CNTL_STATUS_BASE_IDX 0
+#define mmGDS_ENHANCE2 0x05c2
+#define mmGDS_ENHANCE2_BASE_IDX 0
+#define mmGDS_PROTECTION_FAULT 0x05c3
+#define mmGDS_PROTECTION_FAULT_BASE_IDX 0
+#define mmGDS_VM_PROTECTION_FAULT 0x05c4
+#define mmGDS_VM_PROTECTION_FAULT_BASE_IDX 0
+#define mmGDS_EDC_CNT 0x05c5
+#define mmGDS_EDC_CNT_BASE_IDX 0
+#define mmGDS_EDC_GRBM_CNT 0x05c6
+#define mmGDS_EDC_GRBM_CNT_BASE_IDX 0
+#define mmGDS_EDC_OA_DED 0x05c7
+#define mmGDS_EDC_OA_DED_BASE_IDX 0
+#define mmGDS_DSM_CNTL 0x05ca
+#define mmGDS_DSM_CNTL_BASE_IDX 0
+#define mmGDS_EDC_OA_PHY_CNT 0x05cb
+#define mmGDS_EDC_OA_PHY_CNT_BASE_IDX 0
+#define mmGDS_EDC_OA_PIPE_CNT 0x05cc
+#define mmGDS_EDC_OA_PIPE_CNT_BASE_IDX 0
+#define mmGDS_DSM_CNTL2 0x05cd
+#define mmGDS_DSM_CNTL2_BASE_IDX 0
+#define mmGDS_WD_GDS_CSB 0x05ce
+#define mmGDS_WD_GDS_CSB_BASE_IDX 0
+
+
+// addressBlock: gc_rbdec
+// base address: 0x9800
+#define mmDB_DEBUG 0x060c
+#define mmDB_DEBUG_BASE_IDX 0
+#define mmDB_DEBUG2 0x060d
+#define mmDB_DEBUG2_BASE_IDX 0
+#define mmDB_DEBUG3 0x060e
+#define mmDB_DEBUG3_BASE_IDX 0
+#define mmDB_DEBUG4 0x060f
+#define mmDB_DEBUG4_BASE_IDX 0
+#define mmDB_CREDIT_LIMIT 0x0614
+#define mmDB_CREDIT_LIMIT_BASE_IDX 0
+#define mmDB_WATERMARKS 0x0615
+#define mmDB_WATERMARKS_BASE_IDX 0
+#define mmDB_SUBTILE_CONTROL 0x0616
+#define mmDB_SUBTILE_CONTROL_BASE_IDX 0
+#define mmDB_FREE_CACHELINES 0x0617
+#define mmDB_FREE_CACHELINES_BASE_IDX 0
+#define mmDB_FIFO_DEPTH1 0x0618
+#define mmDB_FIFO_DEPTH1_BASE_IDX 0
+#define mmDB_FIFO_DEPTH2 0x0619
+#define mmDB_FIFO_DEPTH2_BASE_IDX 0
+#define mmDB_EXCEPTION_CONTROL 0x061a
+#define mmDB_EXCEPTION_CONTROL_BASE_IDX 0
+#define mmDB_RING_CONTROL 0x061b
+#define mmDB_RING_CONTROL_BASE_IDX 0
+#define mmDB_MEM_ARB_WATERMARKS 0x061c
+#define mmDB_MEM_ARB_WATERMARKS_BASE_IDX 0
+#define mmDB_RMI_CACHE_POLICY 0x061e
+#define mmDB_RMI_CACHE_POLICY_BASE_IDX 0
+#define mmDB_DFSM_CONFIG 0x0630
+#define mmDB_DFSM_CONFIG_BASE_IDX 0
+#define mmDB_DFSM_WATERMARK 0x0631
+#define mmDB_DFSM_WATERMARK_BASE_IDX 0
+#define mmDB_DFSM_TILES_IN_FLIGHT 0x0632
+#define mmDB_DFSM_TILES_IN_FLIGHT_BASE_IDX 0
+#define mmDB_DFSM_PRIMS_IN_FLIGHT 0x0633
+#define mmDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX 0
+#define mmDB_DFSM_WATCHDOG 0x0634
+#define mmDB_DFSM_WATCHDOG_BASE_IDX 0
+#define mmDB_DFSM_FLUSH_ENABLE 0x0635
+#define mmDB_DFSM_FLUSH_ENABLE_BASE_IDX 0
+#define mmDB_DFSM_FLUSH_AUX_EVENT 0x0636
+#define mmDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX 0
+#define mmCC_RB_REDUNDANCY 0x063c
+#define mmCC_RB_REDUNDANCY_BASE_IDX 0
+#define mmCC_RB_BACKEND_DISABLE 0x063d
+#define mmCC_RB_BACKEND_DISABLE_BASE_IDX 0
+#define mmGB_ADDR_CONFIG 0x063e
+#define mmGB_ADDR_CONFIG_BASE_IDX 0
+#define mmGB_BACKEND_MAP 0x063f
+#define mmGB_BACKEND_MAP_BASE_IDX 0
+#define mmGB_GPU_ID 0x0640
+#define mmGB_GPU_ID_BASE_IDX 0
+#define mmCC_RB_DAISY_CHAIN 0x0641
+#define mmCC_RB_DAISY_CHAIN_BASE_IDX 0
+#define mmGB_ADDR_CONFIG_READ 0x0642
+#define mmGB_ADDR_CONFIG_READ_BASE_IDX 0
+#define mmGB_TILE_MODE0 0x0644
+#define mmGB_TILE_MODE0_BASE_IDX 0
+#define mmGB_TILE_MODE1 0x0645
+#define mmGB_TILE_MODE1_BASE_IDX 0
+#define mmGB_TILE_MODE2 0x0646
+#define mmGB_TILE_MODE2_BASE_IDX 0
+#define mmGB_TILE_MODE3 0x0647
+#define mmGB_TILE_MODE3_BASE_IDX 0
+#define mmGB_TILE_MODE4 0x0648
+#define mmGB_TILE_MODE4_BASE_IDX 0
+#define mmGB_TILE_MODE5 0x0649
+#define mmGB_TILE_MODE5_BASE_IDX 0
+#define mmGB_TILE_MODE6 0x064a
+#define mmGB_TILE_MODE6_BASE_IDX 0
+#define mmGB_TILE_MODE7 0x064b
+#define mmGB_TILE_MODE7_BASE_IDX 0
+#define mmGB_TILE_MODE8 0x064c
+#define mmGB_TILE_MODE8_BASE_IDX 0
+#define mmGB_TILE_MODE9 0x064d
+#define mmGB_TILE_MODE9_BASE_IDX 0
+#define mmGB_TILE_MODE10 0x064e
+#define mmGB_TILE_MODE10_BASE_IDX 0
+#define mmGB_TILE_MODE11 0x064f
+#define mmGB_TILE_MODE11_BASE_IDX 0
+#define mmGB_TILE_MODE12 0x0650
+#define mmGB_TILE_MODE12_BASE_IDX 0
+#define mmGB_TILE_MODE13 0x0651
+#define mmGB_TILE_MODE13_BASE_IDX 0
+#define mmGB_TILE_MODE14 0x0652
+#define mmGB_TILE_MODE14_BASE_IDX 0
+#define mmGB_TILE_MODE15 0x0653
+#define mmGB_TILE_MODE15_BASE_IDX 0
+#define mmGB_TILE_MODE16 0x0654
+#define mmGB_TILE_MODE16_BASE_IDX 0
+#define mmGB_TILE_MODE17 0x0655
+#define mmGB_TILE_MODE17_BASE_IDX 0
+#define mmGB_TILE_MODE18 0x0656
+#define mmGB_TILE_MODE18_BASE_IDX 0
+#define mmGB_TILE_MODE19 0x0657
+#define mmGB_TILE_MODE19_BASE_IDX 0
+#define mmGB_TILE_MODE20 0x0658
+#define mmGB_TILE_MODE20_BASE_IDX 0
+#define mmGB_TILE_MODE21 0x0659
+#define mmGB_TILE_MODE21_BASE_IDX 0
+#define mmGB_TILE_MODE22 0x065a
+#define mmGB_TILE_MODE22_BASE_IDX 0
+#define mmGB_TILE_MODE23 0x065b
+#define mmGB_TILE_MODE23_BASE_IDX 0
+#define mmGB_TILE_MODE24 0x065c
+#define mmGB_TILE_MODE24_BASE_IDX 0
+#define mmGB_TILE_MODE25 0x065d
+#define mmGB_TILE_MODE25_BASE_IDX 0
+#define mmGB_TILE_MODE26 0x065e
+#define mmGB_TILE_MODE26_BASE_IDX 0
+#define mmGB_TILE_MODE27 0x065f
+#define mmGB_TILE_MODE27_BASE_IDX 0
+#define mmGB_TILE_MODE28 0x0660
+#define mmGB_TILE_MODE28_BASE_IDX 0
+#define mmGB_TILE_MODE29 0x0661
+#define mmGB_TILE_MODE29_BASE_IDX 0
+#define mmGB_TILE_MODE30 0x0662
+#define mmGB_TILE_MODE30_BASE_IDX 0
+#define mmGB_TILE_MODE31 0x0663
+#define mmGB_TILE_MODE31_BASE_IDX 0
+#define mmGB_MACROTILE_MODE0 0x0664
+#define mmGB_MACROTILE_MODE0_BASE_IDX 0
+#define mmGB_MACROTILE_MODE1 0x0665
+#define mmGB_MACROTILE_MODE1_BASE_IDX 0
+#define mmGB_MACROTILE_MODE2 0x0666
+#define mmGB_MACROTILE_MODE2_BASE_IDX 0
+#define mmGB_MACROTILE_MODE3 0x0667
+#define mmGB_MACROTILE_MODE3_BASE_IDX 0
+#define mmGB_MACROTILE_MODE4 0x0668
+#define mmGB_MACROTILE_MODE4_BASE_IDX 0
+#define mmGB_MACROTILE_MODE5 0x0669
+#define mmGB_MACROTILE_MODE5_BASE_IDX 0
+#define mmGB_MACROTILE_MODE6 0x066a
+#define mmGB_MACROTILE_MODE6_BASE_IDX 0
+#define mmGB_MACROTILE_MODE7 0x066b
+#define mmGB_MACROTILE_MODE7_BASE_IDX 0
+#define mmGB_MACROTILE_MODE8 0x066c
+#define mmGB_MACROTILE_MODE8_BASE_IDX 0
+#define mmGB_MACROTILE_MODE9 0x066d
+#define mmGB_MACROTILE_MODE9_BASE_IDX 0
+#define mmGB_MACROTILE_MODE10 0x066e
+#define mmGB_MACROTILE_MODE10_BASE_IDX 0
+#define mmGB_MACROTILE_MODE11 0x066f
+#define mmGB_MACROTILE_MODE11_BASE_IDX 0
+#define mmGB_MACROTILE_MODE12 0x0670
+#define mmGB_MACROTILE_MODE12_BASE_IDX 0
+#define mmGB_MACROTILE_MODE13 0x0671
+#define mmGB_MACROTILE_MODE13_BASE_IDX 0
+#define mmGB_MACROTILE_MODE14 0x0672
+#define mmGB_MACROTILE_MODE14_BASE_IDX 0
+#define mmGB_MACROTILE_MODE15 0x0673
+#define mmGB_MACROTILE_MODE15_BASE_IDX 0
+#define mmCB_HW_CONTROL 0x0680
+#define mmCB_HW_CONTROL_BASE_IDX 0
+#define mmCB_HW_CONTROL_1 0x0681
+#define mmCB_HW_CONTROL_1_BASE_IDX 0
+#define mmCB_HW_CONTROL_2 0x0682
+#define mmCB_HW_CONTROL_2_BASE_IDX 0
+#define mmCB_HW_CONTROL_3 0x0683
+#define mmCB_HW_CONTROL_3_BASE_IDX 0
+#define mmCB_HW_MEM_ARBITER_RD 0x0686
+#define mmCB_HW_MEM_ARBITER_RD_BASE_IDX 0
+#define mmCB_HW_MEM_ARBITER_WR 0x0687
+#define mmCB_HW_MEM_ARBITER_WR_BASE_IDX 0
+#define mmCB_DCC_CONFIG 0x0688
+#define mmCB_DCC_CONFIG_BASE_IDX 0
+#define mmGC_USER_RB_REDUNDANCY 0x06de
+#define mmGC_USER_RB_REDUNDANCY_BASE_IDX 0
+#define mmGC_USER_RB_BACKEND_DISABLE 0x06df
+#define mmGC_USER_RB_BACKEND_DISABLE_BASE_IDX 0
+
+
+// addressBlock: gc_rmi_rmidec
+// base address: 0x9e00
+#define mmRMI_GENERAL_CNTL 0x0780
+#define mmRMI_GENERAL_CNTL_BASE_IDX 0
+#define mmRMI_GENERAL_CNTL1 0x0781
+#define mmRMI_GENERAL_CNTL1_BASE_IDX 0
+#define mmRMI_GENERAL_STATUS 0x0782
+#define mmRMI_GENERAL_STATUS_BASE_IDX 0
+#define mmRMI_SUBBLOCK_STATUS0 0x0783
+#define mmRMI_SUBBLOCK_STATUS0_BASE_IDX 0
+#define mmRMI_SUBBLOCK_STATUS1 0x0784
+#define mmRMI_SUBBLOCK_STATUS1_BASE_IDX 0
+#define mmRMI_SUBBLOCK_STATUS2 0x0785
+#define mmRMI_SUBBLOCK_STATUS2_BASE_IDX 0
+#define mmRMI_SUBBLOCK_STATUS3 0x0786
+#define mmRMI_SUBBLOCK_STATUS3_BASE_IDX 0
+#define mmRMI_XBAR_CONFIG 0x0787
+#define mmRMI_XBAR_CONFIG_BASE_IDX 0
+#define mmRMI_PROBE_POP_LOGIC_CNTL 0x0788
+#define mmRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX 0
+#define mmRMI_UTC_XNACK_N_MISC_CNTL 0x0789
+#define mmRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX 0
+#define mmRMI_DEMUX_CNTL 0x078a
+#define mmRMI_DEMUX_CNTL_BASE_IDX 0
+#define mmRMI_UTCL1_CNTL1 0x078b
+#define mmRMI_UTCL1_CNTL1_BASE_IDX 0
+#define mmRMI_UTCL1_CNTL2 0x078c
+#define mmRMI_UTCL1_CNTL2_BASE_IDX 0
+#define mmRMI_UTC_UNIT_CONFIG 0x078d
+#define mmRMI_UTC_UNIT_CONFIG_BASE_IDX 0
+#define mmRMI_TCIW_FORMATTER0_CNTL 0x078e
+#define mmRMI_TCIW_FORMATTER0_CNTL_BASE_IDX 0
+#define mmRMI_TCIW_FORMATTER1_CNTL 0x078f
+#define mmRMI_TCIW_FORMATTER1_CNTL_BASE_IDX 0
+#define mmRMI_SCOREBOARD_CNTL 0x0790
+#define mmRMI_SCOREBOARD_CNTL_BASE_IDX 0
+#define mmRMI_SCOREBOARD_STATUS0 0x0791
+#define mmRMI_SCOREBOARD_STATUS0_BASE_IDX 0
+#define mmRMI_SCOREBOARD_STATUS1 0x0792
+#define mmRMI_SCOREBOARD_STATUS1_BASE_IDX 0
+#define mmRMI_SCOREBOARD_STATUS2 0x0793
+#define mmRMI_SCOREBOARD_STATUS2_BASE_IDX 0
+#define mmRMI_XBAR_ARBITER_CONFIG 0x0794
+#define mmRMI_XBAR_ARBITER_CONFIG_BASE_IDX 0
+#define mmRMI_XBAR_ARBITER_CONFIG_1 0x0795
+#define mmRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX 0
+#define mmRMI_CLOCK_CNTRL 0x0796
+#define mmRMI_CLOCK_CNTRL_BASE_IDX 0
+#define mmRMI_UTCL1_STATUS 0x0797
+#define mmRMI_UTCL1_STATUS_BASE_IDX 0
+#define mmRMI_XNACK_DEBUG 0x079d
+#define mmRMI_XNACK_DEBUG_BASE_IDX 0
+#define mmRMI_SPARE 0x079e
+#define mmRMI_SPARE_BASE_IDX 0
+#define mmRMI_SPARE_1 0x079f
+#define mmRMI_SPARE_1_BASE_IDX 0
+#define mmRMI_SPARE_2 0x07a0
+#define mmRMI_SPARE_2_BASE_IDX 0
+
+
+// addressBlock: gc_utcl2_atcl2dec
+// base address: 0xa000
+#define mmATC_L2_CNTL 0x0800
+#define mmATC_L2_CNTL_BASE_IDX 0
+#define mmATC_L2_CNTL2 0x0801
+#define mmATC_L2_CNTL2_BASE_IDX 0
+#define mmATC_L2_CACHE_DATA0 0x0804
+#define mmATC_L2_CACHE_DATA0_BASE_IDX 0
+#define mmATC_L2_CACHE_DATA1 0x0805
+#define mmATC_L2_CACHE_DATA1_BASE_IDX 0
+#define mmATC_L2_CACHE_DATA2 0x0806
+#define mmATC_L2_CACHE_DATA2_BASE_IDX 0
+#define mmATC_L2_CNTL3 0x0807
+#define mmATC_L2_CNTL3_BASE_IDX 0
+#define mmATC_L2_STATUS 0x0808
+#define mmATC_L2_STATUS_BASE_IDX 0
+#define mmATC_L2_STATUS2 0x0809
+#define mmATC_L2_STATUS2_BASE_IDX 0
+#define mmATC_L2_MISC_CG 0x080a
+#define mmATC_L2_MISC_CG_BASE_IDX 0
+#define mmATC_L2_MEM_POWER_LS 0x080b
+#define mmATC_L2_MEM_POWER_LS_BASE_IDX 0
+#define mmATC_L2_CGTT_CLK_CTRL 0x080c
+#define mmATC_L2_CGTT_CLK_CTRL_BASE_IDX 0
+
+
+// addressBlock: gc_utcl2_vml2pfdec
+// base address: 0xa100
+#define mmVM_L2_CNTL 0x0840
+#define mmVM_L2_CNTL_BASE_IDX 0
+#define mmVM_L2_CNTL2 0x0841
+#define mmVM_L2_CNTL2_BASE_IDX 0
+#define mmVM_L2_CNTL3 0x0842
+#define mmVM_L2_CNTL3_BASE_IDX 0
+#define mmVM_L2_STATUS 0x0843
+#define mmVM_L2_STATUS_BASE_IDX 0
+#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x0844
+#define mmVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0
+#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0845
+#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0
+#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0846
+#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0
+#define mmVM_L2_PROTECTION_FAULT_CNTL 0x0847
+#define mmVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0
+#define mmVM_L2_PROTECTION_FAULT_CNTL2 0x0848
+#define mmVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0
+#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0849
+#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0
+#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4 0x084a
+#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0
+#define mmVM_L2_PROTECTION_FAULT_STATUS 0x084b
+#define mmVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0
+#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32 0x084c
+#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0
+#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32 0x084d
+#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0
+#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x084e
+#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0
+#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x084f
+#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0851
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0852
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0853
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0854
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0
+#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0855
+#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0
+#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0856
+#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0
+#define mmVM_L2_CNTL4 0x0857
+#define mmVM_L2_CNTL4_BASE_IDX 0
+#define mmVM_L2_MM_GROUP_RT_CLASSES 0x0858
+#define mmVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0
+#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x0859
+#define mmVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0
+#define mmVM_L2_BANK_SELECT_RESERVED_CID2 0x085a
+#define mmVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0
+#define mmVM_L2_CACHE_PARITY_CNTL 0x085b
+#define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0
+#define mmVM_L2_CGTT_CLK_CTRL 0x085e
+#define mmVM_L2_CGTT_CLK_CTRL_BASE_IDX 0
+
+
+// addressBlock: gc_utcl2_vml2vcdec
+// base address: 0xa200
+#define mmVM_CONTEXT0_CNTL 0x0880
+#define mmVM_CONTEXT0_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT1_CNTL 0x0881
+#define mmVM_CONTEXT1_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT2_CNTL 0x0882
+#define mmVM_CONTEXT2_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT3_CNTL 0x0883
+#define mmVM_CONTEXT3_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT4_CNTL 0x0884
+#define mmVM_CONTEXT4_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT5_CNTL 0x0885
+#define mmVM_CONTEXT5_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT6_CNTL 0x0886
+#define mmVM_CONTEXT6_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT7_CNTL 0x0887
+#define mmVM_CONTEXT7_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT8_CNTL 0x0888
+#define mmVM_CONTEXT8_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT9_CNTL 0x0889
+#define mmVM_CONTEXT9_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT10_CNTL 0x088a
+#define mmVM_CONTEXT10_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT11_CNTL 0x088b
+#define mmVM_CONTEXT11_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT12_CNTL 0x088c
+#define mmVM_CONTEXT12_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT13_CNTL 0x088d
+#define mmVM_CONTEXT13_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT14_CNTL 0x088e
+#define mmVM_CONTEXT14_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT15_CNTL 0x088f
+#define mmVM_CONTEXT15_CNTL_BASE_IDX 0
+#define mmVM_CONTEXTS_DISABLE 0x0890
+#define mmVM_CONTEXTS_DISABLE_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG0_SEM 0x0891
+#define mmVM_INVALIDATE_ENG0_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG1_SEM 0x0892
+#define mmVM_INVALIDATE_ENG1_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG2_SEM 0x0893
+#define mmVM_INVALIDATE_ENG2_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG3_SEM 0x0894
+#define mmVM_INVALIDATE_ENG3_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG4_SEM 0x0895
+#define mmVM_INVALIDATE_ENG4_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG5_SEM 0x0896
+#define mmVM_INVALIDATE_ENG5_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG6_SEM 0x0897
+#define mmVM_INVALIDATE_ENG6_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG7_SEM 0x0898
+#define mmVM_INVALIDATE_ENG7_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG8_SEM 0x0899
+#define mmVM_INVALIDATE_ENG8_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG9_SEM 0x089a
+#define mmVM_INVALIDATE_ENG9_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG10_SEM 0x089b
+#define mmVM_INVALIDATE_ENG10_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG11_SEM 0x089c
+#define mmVM_INVALIDATE_ENG11_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG12_SEM 0x089d
+#define mmVM_INVALIDATE_ENG12_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG13_SEM 0x089e
+#define mmVM_INVALIDATE_ENG13_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG14_SEM 0x089f
+#define mmVM_INVALIDATE_ENG14_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG15_SEM 0x08a0
+#define mmVM_INVALIDATE_ENG15_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG16_SEM 0x08a1
+#define mmVM_INVALIDATE_ENG16_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG17_SEM 0x08a2
+#define mmVM_INVALIDATE_ENG17_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG0_REQ 0x08a3
+#define mmVM_INVALIDATE_ENG0_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG1_REQ 0x08a4
+#define mmVM_INVALIDATE_ENG1_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG2_REQ 0x08a5
+#define mmVM_INVALIDATE_ENG2_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG3_REQ 0x08a6
+#define mmVM_INVALIDATE_ENG3_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG4_REQ 0x08a7
+#define mmVM_INVALIDATE_ENG4_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG5_REQ 0x08a8
+#define mmVM_INVALIDATE_ENG5_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG6_REQ 0x08a9
+#define mmVM_INVALIDATE_ENG6_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG7_REQ 0x08aa
+#define mmVM_INVALIDATE_ENG7_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG8_REQ 0x08ab
+#define mmVM_INVALIDATE_ENG8_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG9_REQ 0x08ac
+#define mmVM_INVALIDATE_ENG9_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG10_REQ 0x08ad
+#define mmVM_INVALIDATE_ENG10_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG11_REQ 0x08ae
+#define mmVM_INVALIDATE_ENG11_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG12_REQ 0x08af
+#define mmVM_INVALIDATE_ENG12_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG13_REQ 0x08b0
+#define mmVM_INVALIDATE_ENG13_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG14_REQ 0x08b1
+#define mmVM_INVALIDATE_ENG14_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG15_REQ 0x08b2
+#define mmVM_INVALIDATE_ENG15_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG16_REQ 0x08b3
+#define mmVM_INVALIDATE_ENG16_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG17_REQ 0x08b4
+#define mmVM_INVALIDATE_ENG17_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG0_ACK 0x08b5
+#define mmVM_INVALIDATE_ENG0_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG1_ACK 0x08b6
+#define mmVM_INVALIDATE_ENG1_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG2_ACK 0x08b7
+#define mmVM_INVALIDATE_ENG2_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG3_ACK 0x08b8
+#define mmVM_INVALIDATE_ENG3_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG4_ACK 0x08b9
+#define mmVM_INVALIDATE_ENG4_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG5_ACK 0x08ba
+#define mmVM_INVALIDATE_ENG5_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG6_ACK 0x08bb
+#define mmVM_INVALIDATE_ENG6_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG7_ACK 0x08bc
+#define mmVM_INVALIDATE_ENG7_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG8_ACK 0x08bd
+#define mmVM_INVALIDATE_ENG8_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG9_ACK 0x08be
+#define mmVM_INVALIDATE_ENG9_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG10_ACK 0x08bf
+#define mmVM_INVALIDATE_ENG10_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG11_ACK 0x08c0
+#define mmVM_INVALIDATE_ENG11_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG12_ACK 0x08c1
+#define mmVM_INVALIDATE_ENG12_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG13_ACK 0x08c2
+#define mmVM_INVALIDATE_ENG13_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG14_ACK 0x08c3
+#define mmVM_INVALIDATE_ENG14_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG15_ACK 0x08c4
+#define mmVM_INVALIDATE_ENG15_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG16_ACK 0x08c5
+#define mmVM_INVALIDATE_ENG16_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG17_ACK 0x08c6
+#define mmVM_INVALIDATE_ENG17_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x08c7
+#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x08c8
+#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x08c9
+#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x08ca
+#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x08cb
+#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x08cc
+#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x08cd
+#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x08ce
+#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x08cf
+#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x08d0
+#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x08d1
+#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x08d2
+#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x08d3
+#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x08d4
+#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x08d5
+#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x08d6
+#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x08d7
+#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x08d8
+#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x08d9
+#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x08da
+#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x08db
+#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x08dc
+#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x08dd
+#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x08de
+#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x08df
+#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x08e0
+#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x08e1
+#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x08e2
+#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x08e3
+#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x08e4
+#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x08e5
+#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x08e6
+#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x08e7
+#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x08e8
+#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x08e9
+#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x08ea
+#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x08eb
+#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x08ec
+#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x08ed
+#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x08ee
+#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x08ef
+#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x08f0
+#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x08f1
+#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x08f2
+#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x08f3
+#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x08f4
+#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x08f5
+#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x08f6
+#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x08f7
+#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x08f8
+#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x08f9
+#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x08fa
+#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x08fb
+#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x08fc
+#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x08fd
+#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x08fe
+#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x08ff
+#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0900
+#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0901
+#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0902
+#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0903
+#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0904
+#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0905
+#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0906
+#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0907
+#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0908
+#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0909
+#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x090a
+#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x090b
+#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x090c
+#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x090d
+#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x090e
+#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x090f
+#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0910
+#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0911
+#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0912
+#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0913
+#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0914
+#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0915
+#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0916
+#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0917
+#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0918
+#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0919
+#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x091a
+#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x091b
+#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x091c
+#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x091d
+#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x091e
+#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x091f
+#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0920
+#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0921
+#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0922
+#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0923
+#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0924
+#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0925
+#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0926
+#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0927
+#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0928
+#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0929
+#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x092a
+#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x092b
+#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x092c
+#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x092d
+#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x092e
+#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x092f
+#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0930
+#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0931
+#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0932
+#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0933
+#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0934
+#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0935
+#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0936
+#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0937
+#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0938
+#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0939
+#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x093a
+#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x093b
+#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x093c
+#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x093d
+#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x093e
+#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x093f
+#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0940
+#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0941
+#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0942
+#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0943
+#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0944
+#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0945
+#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0946
+#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0947
+#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0948
+#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0949
+#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x094a
+#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+
+
+// addressBlock: gc_utcl2_vmsharedpfdec
+// base address: 0xa590
+#define mmMC_VM_NB_MMIOBASE 0x0964
+#define mmMC_VM_NB_MMIOBASE_BASE_IDX 0
+#define mmMC_VM_NB_MMIOLIMIT 0x0965
+#define mmMC_VM_NB_MMIOLIMIT_BASE_IDX 0
+#define mmMC_VM_NB_PCI_CTRL 0x0966
+#define mmMC_VM_NB_PCI_CTRL_BASE_IDX 0
+#define mmMC_VM_NB_PCI_ARB 0x0967
+#define mmMC_VM_NB_PCI_ARB_BASE_IDX 0
+#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0968
+#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0
+#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0969
+#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0
+#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0x096a
+#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0
+#define mmMC_VM_FB_OFFSET 0x096b
+#define mmMC_VM_FB_OFFSET_BASE_IDX 0
+#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x096c
+#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0
+#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x096d
+#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0
+#define mmMC_VM_STEERING 0x096e
+#define mmMC_VM_STEERING_BASE_IDX 0
+#define mmMC_SHARED_VIRT_RESET_REQ 0x096f
+#define mmMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0
+#define mmMC_MEM_POWER_LS 0x0970
+#define mmMC_MEM_POWER_LS_BASE_IDX 0
+#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0971
+#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0
+#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0972
+#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0
+#define mmMC_VM_APT_CNTL 0x0973
+#define mmMC_VM_APT_CNTL_BASE_IDX 0
+#define mmMC_VM_LOCAL_HBM_ADDRESS_START 0x0974
+#define mmMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0
+#define mmMC_VM_LOCAL_HBM_ADDRESS_END 0x0975
+#define mmMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0
+#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0976
+#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0
+
+
+// addressBlock: gc_utcl2_vmsharedvcdec
+// base address: 0xa600
+#define mmMC_VM_FB_LOCATION_BASE 0x0980
+#define mmMC_VM_FB_LOCATION_BASE_BASE_IDX 0
+#define mmMC_VM_FB_LOCATION_TOP 0x0981
+#define mmMC_VM_FB_LOCATION_TOP_BASE_IDX 0
+#define mmMC_VM_AGP_TOP 0x0982
+#define mmMC_VM_AGP_TOP_BASE_IDX 0
+#define mmMC_VM_AGP_BOT 0x0983
+#define mmMC_VM_AGP_BOT_BASE_IDX 0
+#define mmMC_VM_AGP_BASE 0x0984
+#define mmMC_VM_AGP_BASE_BASE_IDX 0
+#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0985
+#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0
+#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0986
+#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0
+#define mmMC_VM_MX_L1_TLB_CNTL 0x0987
+#define mmMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0
+
+
+// addressBlock: gc_tcdec
+// base address: 0xac00
+#define mmTCP_INVALIDATE 0x0b00
+#define mmTCP_INVALIDATE_BASE_IDX 0
+#define mmTCP_STATUS 0x0b01
+#define mmTCP_STATUS_BASE_IDX 0
+#define mmTCP_CNTL 0x0b02
+#define mmTCP_CNTL_BASE_IDX 0
+#define mmTCP_CHAN_STEER_LO 0x0b03
+#define mmTCP_CHAN_STEER_LO_BASE_IDX 0
+#define mmTCP_CHAN_STEER_HI 0x0b04
+#define mmTCP_CHAN_STEER_HI_BASE_IDX 0
+#define mmTCP_ADDR_CONFIG 0x0b05
+#define mmTCP_ADDR_CONFIG_BASE_IDX 0
+#define mmTCP_CREDIT 0x0b06
+#define mmTCP_CREDIT_BASE_IDX 0
+#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x0b16
+#define mmTCP_BUFFER_ADDR_HASH_CNTL_BASE_IDX 0
+#define mmTCP_EDC_CNT 0x0b17
+#define mmTCP_EDC_CNT_BASE_IDX 0
+#define mmTC_CFG_L1_LOAD_POLICY0 0x0b1a
+#define mmTC_CFG_L1_LOAD_POLICY0_BASE_IDX 0
+#define mmTC_CFG_L1_LOAD_POLICY1 0x0b1b
+#define mmTC_CFG_L1_LOAD_POLICY1_BASE_IDX 0
+#define mmTC_CFG_L1_STORE_POLICY 0x0b1c
+#define mmTC_CFG_L1_STORE_POLICY_BASE_IDX 0
+#define mmTC_CFG_L2_LOAD_POLICY0 0x0b1d
+#define mmTC_CFG_L2_LOAD_POLICY0_BASE_IDX 0
+#define mmTC_CFG_L2_LOAD_POLICY1 0x0b1e
+#define mmTC_CFG_L2_LOAD_POLICY1_BASE_IDX 0
+#define mmTC_CFG_L2_STORE_POLICY0 0x0b1f
+#define mmTC_CFG_L2_STORE_POLICY0_BASE_IDX 0
+#define mmTC_CFG_L2_STORE_POLICY1 0x0b20
+#define mmTC_CFG_L2_STORE_POLICY1_BASE_IDX 0
+#define mmTC_CFG_L2_ATOMIC_POLICY 0x0b21
+#define mmTC_CFG_L2_ATOMIC_POLICY_BASE_IDX 0
+#define mmTC_CFG_L1_VOLATILE 0x0b22
+#define mmTC_CFG_L1_VOLATILE_BASE_IDX 0
+#define mmTC_CFG_L2_VOLATILE 0x0b23
+#define mmTC_CFG_L2_VOLATILE_BASE_IDX 0
+#define mmTCI_STATUS 0x0b61
+#define mmTCI_STATUS_BASE_IDX 0
+#define mmTCI_CNTL_1 0x0b62
+#define mmTCI_CNTL_1_BASE_IDX 0
+#define mmTCI_CNTL_2 0x0b63
+#define mmTCI_CNTL_2_BASE_IDX 0
+#define mmTCC_CTRL 0x0b80
+#define mmTCC_CTRL_BASE_IDX 0
+#define mmTCC_CTRL2 0x0b81
+#define mmTCC_CTRL2_BASE_IDX 0
+#define mmTCC_EDC_CNT 0x0b82
+#define mmTCC_EDC_CNT_BASE_IDX 0
+#define mmTCC_EDC_CNT2 0x0b83
+#define mmTCC_EDC_CNT2_BASE_IDX 0
+#define mmTCC_REDUNDANCY 0x0b84
+#define mmTCC_REDUNDANCY_BASE_IDX 0
+#define mmTCC_EXE_DISABLE 0x0b85
+#define mmTCC_EXE_DISABLE_BASE_IDX 0
+#define mmTCC_DSM_CNTL 0x0b86
+#define mmTCC_DSM_CNTL_BASE_IDX 0
+#define mmTCC_DSM_CNTLA 0x0b87
+#define mmTCC_DSM_CNTLA_BASE_IDX 0
+#define mmTCC_DSM_CNTL2 0x0b88
+#define mmTCC_DSM_CNTL2_BASE_IDX 0
+#define mmTCC_DSM_CNTL2A 0x0b89
+#define mmTCC_DSM_CNTL2A_BASE_IDX 0
+#define mmTCC_DSM_CNTL2B 0x0b8a
+#define mmTCC_DSM_CNTL2B_BASE_IDX 0
+#define mmTCC_WBINVL2 0x0b8b
+#define mmTCC_WBINVL2_BASE_IDX 0
+#define mmTCC_SOFT_RESET 0x0b8c
+#define mmTCC_SOFT_RESET_BASE_IDX 0
+#define mmTCA_CTRL 0x0bc0
+#define mmTCA_CTRL_BASE_IDX 0
+#define mmTCA_BURST_MASK 0x0bc1
+#define mmTCA_BURST_MASK_BASE_IDX 0
+#define mmTCA_BURST_CTRL 0x0bc2
+#define mmTCA_BURST_CTRL_BASE_IDX 0
+#define mmTCA_DSM_CNTL 0x0bc3
+#define mmTCA_DSM_CNTL_BASE_IDX 0
+#define mmTCA_DSM_CNTL2 0x0bc4
+#define mmTCA_DSM_CNTL2_BASE_IDX 0
+#define mmTCA_EDC_CNT 0x0bc5
+#define mmTCA_EDC_CNT_BASE_IDX 0
+
+
+// addressBlock: gc_shdec
+// base address: 0xb000
+#define mmSPI_SHADER_PGM_RSRC3_PS 0x0c07
+#define mmSPI_SHADER_PGM_RSRC3_PS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_LO_PS 0x0c08
+#define mmSPI_SHADER_PGM_LO_PS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_HI_PS 0x0c09
+#define mmSPI_SHADER_PGM_HI_PS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC1_PS 0x0c0a
+#define mmSPI_SHADER_PGM_RSRC1_PS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC2_PS 0x0c0b
+#define mmSPI_SHADER_PGM_RSRC2_PS_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_0 0x0c0c
+#define mmSPI_SHADER_USER_DATA_PS_0_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_1 0x0c0d
+#define mmSPI_SHADER_USER_DATA_PS_1_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_2 0x0c0e
+#define mmSPI_SHADER_USER_DATA_PS_2_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_3 0x0c0f
+#define mmSPI_SHADER_USER_DATA_PS_3_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_4 0x0c10
+#define mmSPI_SHADER_USER_DATA_PS_4_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_5 0x0c11
+#define mmSPI_SHADER_USER_DATA_PS_5_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_6 0x0c12
+#define mmSPI_SHADER_USER_DATA_PS_6_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_7 0x0c13
+#define mmSPI_SHADER_USER_DATA_PS_7_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_8 0x0c14
+#define mmSPI_SHADER_USER_DATA_PS_8_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_9 0x0c15
+#define mmSPI_SHADER_USER_DATA_PS_9_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_10 0x0c16
+#define mmSPI_SHADER_USER_DATA_PS_10_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_11 0x0c17
+#define mmSPI_SHADER_USER_DATA_PS_11_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_12 0x0c18
+#define mmSPI_SHADER_USER_DATA_PS_12_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_13 0x0c19
+#define mmSPI_SHADER_USER_DATA_PS_13_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_14 0x0c1a
+#define mmSPI_SHADER_USER_DATA_PS_14_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_15 0x0c1b
+#define mmSPI_SHADER_USER_DATA_PS_15_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_16 0x0c1c
+#define mmSPI_SHADER_USER_DATA_PS_16_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_17 0x0c1d
+#define mmSPI_SHADER_USER_DATA_PS_17_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_18 0x0c1e
+#define mmSPI_SHADER_USER_DATA_PS_18_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_19 0x0c1f
+#define mmSPI_SHADER_USER_DATA_PS_19_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_20 0x0c20
+#define mmSPI_SHADER_USER_DATA_PS_20_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_21 0x0c21
+#define mmSPI_SHADER_USER_DATA_PS_21_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_22 0x0c22
+#define mmSPI_SHADER_USER_DATA_PS_22_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_23 0x0c23
+#define mmSPI_SHADER_USER_DATA_PS_23_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_24 0x0c24
+#define mmSPI_SHADER_USER_DATA_PS_24_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_25 0x0c25
+#define mmSPI_SHADER_USER_DATA_PS_25_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_26 0x0c26
+#define mmSPI_SHADER_USER_DATA_PS_26_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_27 0x0c27
+#define mmSPI_SHADER_USER_DATA_PS_27_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_28 0x0c28
+#define mmSPI_SHADER_USER_DATA_PS_28_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_29 0x0c29
+#define mmSPI_SHADER_USER_DATA_PS_29_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_30 0x0c2a
+#define mmSPI_SHADER_USER_DATA_PS_30_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_31 0x0c2b
+#define mmSPI_SHADER_USER_DATA_PS_31_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC3_VS 0x0c46
+#define mmSPI_SHADER_PGM_RSRC3_VS_BASE_IDX 0
+#define mmSPI_SHADER_LATE_ALLOC_VS 0x0c47
+#define mmSPI_SHADER_LATE_ALLOC_VS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_LO_VS 0x0c48
+#define mmSPI_SHADER_PGM_LO_VS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_HI_VS 0x0c49
+#define mmSPI_SHADER_PGM_HI_VS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC1_VS 0x0c4a
+#define mmSPI_SHADER_PGM_RSRC1_VS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC2_VS 0x0c4b
+#define mmSPI_SHADER_PGM_RSRC2_VS_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_0 0x0c4c
+#define mmSPI_SHADER_USER_DATA_VS_0_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_1 0x0c4d
+#define mmSPI_SHADER_USER_DATA_VS_1_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_2 0x0c4e
+#define mmSPI_SHADER_USER_DATA_VS_2_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_3 0x0c4f
+#define mmSPI_SHADER_USER_DATA_VS_3_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_4 0x0c50
+#define mmSPI_SHADER_USER_DATA_VS_4_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_5 0x0c51
+#define mmSPI_SHADER_USER_DATA_VS_5_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_6 0x0c52
+#define mmSPI_SHADER_USER_DATA_VS_6_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_7 0x0c53
+#define mmSPI_SHADER_USER_DATA_VS_7_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_8 0x0c54
+#define mmSPI_SHADER_USER_DATA_VS_8_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_9 0x0c55
+#define mmSPI_SHADER_USER_DATA_VS_9_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_10 0x0c56
+#define mmSPI_SHADER_USER_DATA_VS_10_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_11 0x0c57
+#define mmSPI_SHADER_USER_DATA_VS_11_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_12 0x0c58
+#define mmSPI_SHADER_USER_DATA_VS_12_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_13 0x0c59
+#define mmSPI_SHADER_USER_DATA_VS_13_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_14 0x0c5a
+#define mmSPI_SHADER_USER_DATA_VS_14_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_15 0x0c5b
+#define mmSPI_SHADER_USER_DATA_VS_15_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_16 0x0c5c
+#define mmSPI_SHADER_USER_DATA_VS_16_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_17 0x0c5d
+#define mmSPI_SHADER_USER_DATA_VS_17_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_18 0x0c5e
+#define mmSPI_SHADER_USER_DATA_VS_18_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_19 0x0c5f
+#define mmSPI_SHADER_USER_DATA_VS_19_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_20 0x0c60
+#define mmSPI_SHADER_USER_DATA_VS_20_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_21 0x0c61
+#define mmSPI_SHADER_USER_DATA_VS_21_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_22 0x0c62
+#define mmSPI_SHADER_USER_DATA_VS_22_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_23 0x0c63
+#define mmSPI_SHADER_USER_DATA_VS_23_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_24 0x0c64
+#define mmSPI_SHADER_USER_DATA_VS_24_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_25 0x0c65
+#define mmSPI_SHADER_USER_DATA_VS_25_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_26 0x0c66
+#define mmSPI_SHADER_USER_DATA_VS_26_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_27 0x0c67
+#define mmSPI_SHADER_USER_DATA_VS_27_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_28 0x0c68
+#define mmSPI_SHADER_USER_DATA_VS_28_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_29 0x0c69
+#define mmSPI_SHADER_USER_DATA_VS_29_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_30 0x0c6a
+#define mmSPI_SHADER_USER_DATA_VS_30_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_31 0x0c6b
+#define mmSPI_SHADER_USER_DATA_VS_31_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC2_GS_VS 0x0c7c
+#define mmSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC4_GS 0x0c81
+#define mmSPI_SHADER_PGM_RSRC4_GS_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS 0x0c82
+#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS 0x0c83
+#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_LO_ES 0x0c84
+#define mmSPI_SHADER_PGM_LO_ES_BASE_IDX 0
+#define mmSPI_SHADER_PGM_HI_ES 0x0c85
+#define mmSPI_SHADER_PGM_HI_ES_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC3_GS 0x0c87
+#define mmSPI_SHADER_PGM_RSRC3_GS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_LO_GS 0x0c88
+#define mmSPI_SHADER_PGM_LO_GS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_HI_GS 0x0c89
+#define mmSPI_SHADER_PGM_HI_GS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC1_GS 0x0c8a
+#define mmSPI_SHADER_PGM_RSRC1_GS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC2_GS 0x0c8b
+#define mmSPI_SHADER_PGM_RSRC2_GS_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_0 0x0ccc
+#define mmSPI_SHADER_USER_DATA_ES_0_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_1 0x0ccd
+#define mmSPI_SHADER_USER_DATA_ES_1_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_2 0x0cce
+#define mmSPI_SHADER_USER_DATA_ES_2_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_3 0x0ccf
+#define mmSPI_SHADER_USER_DATA_ES_3_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_4 0x0cd0
+#define mmSPI_SHADER_USER_DATA_ES_4_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_5 0x0cd1
+#define mmSPI_SHADER_USER_DATA_ES_5_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_6 0x0cd2
+#define mmSPI_SHADER_USER_DATA_ES_6_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_7 0x0cd3
+#define mmSPI_SHADER_USER_DATA_ES_7_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_8 0x0cd4
+#define mmSPI_SHADER_USER_DATA_ES_8_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_9 0x0cd5
+#define mmSPI_SHADER_USER_DATA_ES_9_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_10 0x0cd6
+#define mmSPI_SHADER_USER_DATA_ES_10_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_11 0x0cd7
+#define mmSPI_SHADER_USER_DATA_ES_11_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_12 0x0cd8
+#define mmSPI_SHADER_USER_DATA_ES_12_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_13 0x0cd9
+#define mmSPI_SHADER_USER_DATA_ES_13_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_14 0x0cda
+#define mmSPI_SHADER_USER_DATA_ES_14_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_15 0x0cdb
+#define mmSPI_SHADER_USER_DATA_ES_15_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_16 0x0cdc
+#define mmSPI_SHADER_USER_DATA_ES_16_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_17 0x0cdd
+#define mmSPI_SHADER_USER_DATA_ES_17_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_18 0x0cde
+#define mmSPI_SHADER_USER_DATA_ES_18_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_19 0x0cdf
+#define mmSPI_SHADER_USER_DATA_ES_19_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_20 0x0ce0
+#define mmSPI_SHADER_USER_DATA_ES_20_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_21 0x0ce1
+#define mmSPI_SHADER_USER_DATA_ES_21_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_22 0x0ce2
+#define mmSPI_SHADER_USER_DATA_ES_22_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_23 0x0ce3
+#define mmSPI_SHADER_USER_DATA_ES_23_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_24 0x0ce4
+#define mmSPI_SHADER_USER_DATA_ES_24_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_25 0x0ce5
+#define mmSPI_SHADER_USER_DATA_ES_25_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_26 0x0ce6
+#define mmSPI_SHADER_USER_DATA_ES_26_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_27 0x0ce7
+#define mmSPI_SHADER_USER_DATA_ES_27_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_28 0x0ce8
+#define mmSPI_SHADER_USER_DATA_ES_28_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_29 0x0ce9
+#define mmSPI_SHADER_USER_DATA_ES_29_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_30 0x0cea
+#define mmSPI_SHADER_USER_DATA_ES_30_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_31 0x0ceb
+#define mmSPI_SHADER_USER_DATA_ES_31_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC4_HS 0x0d01
+#define mmSPI_SHADER_PGM_RSRC4_HS_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS 0x0d02
+#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS 0x0d03
+#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_LO_LS 0x0d04
+#define mmSPI_SHADER_PGM_LO_LS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_HI_LS 0x0d05
+#define mmSPI_SHADER_PGM_HI_LS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC3_HS 0x0d07
+#define mmSPI_SHADER_PGM_RSRC3_HS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_LO_HS 0x0d08
+#define mmSPI_SHADER_PGM_LO_HS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_HI_HS 0x0d09
+#define mmSPI_SHADER_PGM_HI_HS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC1_HS 0x0d0a
+#define mmSPI_SHADER_PGM_RSRC1_HS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC2_HS 0x0d0b
+#define mmSPI_SHADER_PGM_RSRC2_HS_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_0 0x0d0c
+#define mmSPI_SHADER_USER_DATA_LS_0_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_1 0x0d0d
+#define mmSPI_SHADER_USER_DATA_LS_1_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_2 0x0d0e
+#define mmSPI_SHADER_USER_DATA_LS_2_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_3 0x0d0f
+#define mmSPI_SHADER_USER_DATA_LS_3_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_4 0x0d10
+#define mmSPI_SHADER_USER_DATA_LS_4_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_5 0x0d11
+#define mmSPI_SHADER_USER_DATA_LS_5_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_6 0x0d12
+#define mmSPI_SHADER_USER_DATA_LS_6_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_7 0x0d13
+#define mmSPI_SHADER_USER_DATA_LS_7_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_8 0x0d14
+#define mmSPI_SHADER_USER_DATA_LS_8_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_9 0x0d15
+#define mmSPI_SHADER_USER_DATA_LS_9_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_10 0x0d16
+#define mmSPI_SHADER_USER_DATA_LS_10_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_11 0x0d17
+#define mmSPI_SHADER_USER_DATA_LS_11_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_12 0x0d18
+#define mmSPI_SHADER_USER_DATA_LS_12_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_13 0x0d19
+#define mmSPI_SHADER_USER_DATA_LS_13_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_14 0x0d1a
+#define mmSPI_SHADER_USER_DATA_LS_14_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_15 0x0d1b
+#define mmSPI_SHADER_USER_DATA_LS_15_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_16 0x0d1c
+#define mmSPI_SHADER_USER_DATA_LS_16_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_17 0x0d1d
+#define mmSPI_SHADER_USER_DATA_LS_17_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_18 0x0d1e
+#define mmSPI_SHADER_USER_DATA_LS_18_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_19 0x0d1f
+#define mmSPI_SHADER_USER_DATA_LS_19_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_20 0x0d20
+#define mmSPI_SHADER_USER_DATA_LS_20_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_21 0x0d21
+#define mmSPI_SHADER_USER_DATA_LS_21_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_22 0x0d22
+#define mmSPI_SHADER_USER_DATA_LS_22_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_23 0x0d23
+#define mmSPI_SHADER_USER_DATA_LS_23_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_24 0x0d24
+#define mmSPI_SHADER_USER_DATA_LS_24_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_25 0x0d25
+#define mmSPI_SHADER_USER_DATA_LS_25_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_26 0x0d26
+#define mmSPI_SHADER_USER_DATA_LS_26_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_27 0x0d27
+#define mmSPI_SHADER_USER_DATA_LS_27_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_28 0x0d28
+#define mmSPI_SHADER_USER_DATA_LS_28_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_29 0x0d29
+#define mmSPI_SHADER_USER_DATA_LS_29_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_30 0x0d2a
+#define mmSPI_SHADER_USER_DATA_LS_30_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_31 0x0d2b
+#define mmSPI_SHADER_USER_DATA_LS_31_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_0 0x0d4c
+#define mmSPI_SHADER_USER_DATA_COMMON_0_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_1 0x0d4d
+#define mmSPI_SHADER_USER_DATA_COMMON_1_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_2 0x0d4e
+#define mmSPI_SHADER_USER_DATA_COMMON_2_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_3 0x0d4f
+#define mmSPI_SHADER_USER_DATA_COMMON_3_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_4 0x0d50
+#define mmSPI_SHADER_USER_DATA_COMMON_4_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_5 0x0d51
+#define mmSPI_SHADER_USER_DATA_COMMON_5_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_6 0x0d52
+#define mmSPI_SHADER_USER_DATA_COMMON_6_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_7 0x0d53
+#define mmSPI_SHADER_USER_DATA_COMMON_7_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_8 0x0d54
+#define mmSPI_SHADER_USER_DATA_COMMON_8_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_9 0x0d55
+#define mmSPI_SHADER_USER_DATA_COMMON_9_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_10 0x0d56
+#define mmSPI_SHADER_USER_DATA_COMMON_10_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_11 0x0d57
+#define mmSPI_SHADER_USER_DATA_COMMON_11_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_12 0x0d58
+#define mmSPI_SHADER_USER_DATA_COMMON_12_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_13 0x0d59
+#define mmSPI_SHADER_USER_DATA_COMMON_13_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_14 0x0d5a
+#define mmSPI_SHADER_USER_DATA_COMMON_14_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_15 0x0d5b
+#define mmSPI_SHADER_USER_DATA_COMMON_15_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_16 0x0d5c
+#define mmSPI_SHADER_USER_DATA_COMMON_16_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_17 0x0d5d
+#define mmSPI_SHADER_USER_DATA_COMMON_17_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_18 0x0d5e
+#define mmSPI_SHADER_USER_DATA_COMMON_18_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_19 0x0d5f
+#define mmSPI_SHADER_USER_DATA_COMMON_19_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_20 0x0d60
+#define mmSPI_SHADER_USER_DATA_COMMON_20_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_21 0x0d61
+#define mmSPI_SHADER_USER_DATA_COMMON_21_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_22 0x0d62
+#define mmSPI_SHADER_USER_DATA_COMMON_22_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_23 0x0d63
+#define mmSPI_SHADER_USER_DATA_COMMON_23_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_24 0x0d64
+#define mmSPI_SHADER_USER_DATA_COMMON_24_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_25 0x0d65
+#define mmSPI_SHADER_USER_DATA_COMMON_25_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_26 0x0d66
+#define mmSPI_SHADER_USER_DATA_COMMON_26_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_27 0x0d67
+#define mmSPI_SHADER_USER_DATA_COMMON_27_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_28 0x0d68
+#define mmSPI_SHADER_USER_DATA_COMMON_28_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_29 0x0d69
+#define mmSPI_SHADER_USER_DATA_COMMON_29_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_30 0x0d6a
+#define mmSPI_SHADER_USER_DATA_COMMON_30_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_COMMON_31 0x0d6b
+#define mmSPI_SHADER_USER_DATA_COMMON_31_BASE_IDX 0
+#define mmCOMPUTE_DISPATCH_INITIATOR 0x0e00
+#define mmCOMPUTE_DISPATCH_INITIATOR_BASE_IDX 0
+#define mmCOMPUTE_DIM_X 0x0e01
+#define mmCOMPUTE_DIM_X_BASE_IDX 0
+#define mmCOMPUTE_DIM_Y 0x0e02
+#define mmCOMPUTE_DIM_Y_BASE_IDX 0
+#define mmCOMPUTE_DIM_Z 0x0e03
+#define mmCOMPUTE_DIM_Z_BASE_IDX 0
+#define mmCOMPUTE_START_X 0x0e04
+#define mmCOMPUTE_START_X_BASE_IDX 0
+#define mmCOMPUTE_START_Y 0x0e05
+#define mmCOMPUTE_START_Y_BASE_IDX 0
+#define mmCOMPUTE_START_Z 0x0e06
+#define mmCOMPUTE_START_Z_BASE_IDX 0
+#define mmCOMPUTE_NUM_THREAD_X 0x0e07
+#define mmCOMPUTE_NUM_THREAD_X_BASE_IDX 0
+#define mmCOMPUTE_NUM_THREAD_Y 0x0e08
+#define mmCOMPUTE_NUM_THREAD_Y_BASE_IDX 0
+#define mmCOMPUTE_NUM_THREAD_Z 0x0e09
+#define mmCOMPUTE_NUM_THREAD_Z_BASE_IDX 0
+#define mmCOMPUTE_PIPELINESTAT_ENABLE 0x0e0a
+#define mmCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 0
+#define mmCOMPUTE_PERFCOUNT_ENABLE 0x0e0b
+#define mmCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX 0
+#define mmCOMPUTE_PGM_LO 0x0e0c
+#define mmCOMPUTE_PGM_LO_BASE_IDX 0
+#define mmCOMPUTE_PGM_HI 0x0e0d
+#define mmCOMPUTE_PGM_HI_BASE_IDX 0
+#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO 0x0e0e
+#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 0
+#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI 0x0e0f
+#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 0
+#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x0e10
+#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 0
+#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x0e11
+#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 0
+#define mmCOMPUTE_PGM_RSRC1 0x0e12
+#define mmCOMPUTE_PGM_RSRC1_BASE_IDX 0
+#define mmCOMPUTE_PGM_RSRC2 0x0e13
+#define mmCOMPUTE_PGM_RSRC2_BASE_IDX 0
+#define mmCOMPUTE_VMID 0x0e14
+#define mmCOMPUTE_VMID_BASE_IDX 0
+#define mmCOMPUTE_RESOURCE_LIMITS 0x0e15
+#define mmCOMPUTE_RESOURCE_LIMITS_BASE_IDX 0
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x0e16
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 0
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x0e17
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 0
+#define mmCOMPUTE_TMPRING_SIZE 0x0e18
+#define mmCOMPUTE_TMPRING_SIZE_BASE_IDX 0
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x0e19
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x0e1a
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0
+#define mmCOMPUTE_RESTART_X 0x0e1b
+#define mmCOMPUTE_RESTART_X_BASE_IDX 0
+#define mmCOMPUTE_RESTART_Y 0x0e1c
+#define mmCOMPUTE_RESTART_Y_BASE_IDX 0
+#define mmCOMPUTE_RESTART_Z 0x0e1d
+#define mmCOMPUTE_RESTART_Z_BASE_IDX 0
+#define mmCOMPUTE_THREAD_TRACE_ENABLE 0x0e1e
+#define mmCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 0
+#define mmCOMPUTE_MISC_RESERVED 0x0e1f
+#define mmCOMPUTE_MISC_RESERVED_BASE_IDX 0
+#define mmCOMPUTE_DISPATCH_ID 0x0e20
+#define mmCOMPUTE_DISPATCH_ID_BASE_IDX 0
+#define mmCOMPUTE_THREADGROUP_ID 0x0e21
+#define mmCOMPUTE_THREADGROUP_ID_BASE_IDX 0
+#define mmCOMPUTE_RELAUNCH 0x0e22
+#define mmCOMPUTE_RELAUNCH_BASE_IDX 0
+#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO 0x0e23
+#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 0
+#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI 0x0e24
+#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_0 0x0e40
+#define mmCOMPUTE_USER_DATA_0_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_1 0x0e41
+#define mmCOMPUTE_USER_DATA_1_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_2 0x0e42
+#define mmCOMPUTE_USER_DATA_2_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_3 0x0e43
+#define mmCOMPUTE_USER_DATA_3_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_4 0x0e44
+#define mmCOMPUTE_USER_DATA_4_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_5 0x0e45
+#define mmCOMPUTE_USER_DATA_5_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_6 0x0e46
+#define mmCOMPUTE_USER_DATA_6_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_7 0x0e47
+#define mmCOMPUTE_USER_DATA_7_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_8 0x0e48
+#define mmCOMPUTE_USER_DATA_8_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_9 0x0e49
+#define mmCOMPUTE_USER_DATA_9_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_10 0x0e4a
+#define mmCOMPUTE_USER_DATA_10_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_11 0x0e4b
+#define mmCOMPUTE_USER_DATA_11_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_12 0x0e4c
+#define mmCOMPUTE_USER_DATA_12_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_13 0x0e4d
+#define mmCOMPUTE_USER_DATA_13_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_14 0x0e4e
+#define mmCOMPUTE_USER_DATA_14_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_15 0x0e4f
+#define mmCOMPUTE_USER_DATA_15_BASE_IDX 0
+#define mmCOMPUTE_NOWHERE 0x0e7f
+#define mmCOMPUTE_NOWHERE_BASE_IDX 0
+
+
+// addressBlock: gc_cppdec
+// base address: 0xc080
+#define mmCP_DFY_CNTL 0x1020
+#define mmCP_DFY_CNTL_BASE_IDX 0
+#define mmCP_DFY_STAT 0x1021
+#define mmCP_DFY_STAT_BASE_IDX 0
+#define mmCP_DFY_ADDR_HI 0x1022
+#define mmCP_DFY_ADDR_HI_BASE_IDX 0
+#define mmCP_DFY_ADDR_LO 0x1023
+#define mmCP_DFY_ADDR_LO_BASE_IDX 0
+#define mmCP_DFY_DATA_0 0x1024
+#define mmCP_DFY_DATA_0_BASE_IDX 0
+#define mmCP_DFY_DATA_1 0x1025
+#define mmCP_DFY_DATA_1_BASE_IDX 0
+#define mmCP_DFY_DATA_2 0x1026
+#define mmCP_DFY_DATA_2_BASE_IDX 0
+#define mmCP_DFY_DATA_3 0x1027
+#define mmCP_DFY_DATA_3_BASE_IDX 0
+#define mmCP_DFY_DATA_4 0x1028
+#define mmCP_DFY_DATA_4_BASE_IDX 0
+#define mmCP_DFY_DATA_5 0x1029
+#define mmCP_DFY_DATA_5_BASE_IDX 0
+#define mmCP_DFY_DATA_6 0x102a
+#define mmCP_DFY_DATA_6_BASE_IDX 0
+#define mmCP_DFY_DATA_7 0x102b
+#define mmCP_DFY_DATA_7_BASE_IDX 0
+#define mmCP_DFY_DATA_8 0x102c
+#define mmCP_DFY_DATA_8_BASE_IDX 0
+#define mmCP_DFY_DATA_9 0x102d
+#define mmCP_DFY_DATA_9_BASE_IDX 0
+#define mmCP_DFY_DATA_10 0x102e
+#define mmCP_DFY_DATA_10_BASE_IDX 0
+#define mmCP_DFY_DATA_11 0x102f
+#define mmCP_DFY_DATA_11_BASE_IDX 0
+#define mmCP_DFY_DATA_12 0x1030
+#define mmCP_DFY_DATA_12_BASE_IDX 0
+#define mmCP_DFY_DATA_13 0x1031
+#define mmCP_DFY_DATA_13_BASE_IDX 0
+#define mmCP_DFY_DATA_14 0x1032
+#define mmCP_DFY_DATA_14_BASE_IDX 0
+#define mmCP_DFY_DATA_15 0x1033
+#define mmCP_DFY_DATA_15_BASE_IDX 0
+#define mmCP_DFY_CMD 0x1034
+#define mmCP_DFY_CMD_BASE_IDX 0
+#define mmCP_EOPQ_WAIT_TIME 0x1035
+#define mmCP_EOPQ_WAIT_TIME_BASE_IDX 0
+#define mmCP_CPC_MGCG_SYNC_CNTL 0x1036
+#define mmCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0
+#define mmCPC_INT_INFO 0x1037
+#define mmCPC_INT_INFO_BASE_IDX 0
+#define mmCP_VIRT_STATUS 0x1038
+#define mmCP_VIRT_STATUS_BASE_IDX 0
+#define mmCPC_INT_ADDR 0x1039
+#define mmCPC_INT_ADDR_BASE_IDX 0
+#define mmCPC_INT_PASID 0x103a
+#define mmCPC_INT_PASID_BASE_IDX 0
+#define mmCP_GFX_ERROR 0x103b
+#define mmCP_GFX_ERROR_BASE_IDX 0
+#define mmCPG_UTCL1_CNTL 0x103c
+#define mmCPG_UTCL1_CNTL_BASE_IDX 0
+#define mmCPC_UTCL1_CNTL 0x103d
+#define mmCPC_UTCL1_CNTL_BASE_IDX 0
+#define mmCPF_UTCL1_CNTL 0x103e
+#define mmCPF_UTCL1_CNTL_BASE_IDX 0
+#define mmCP_AQL_SMM_STATUS 0x103f
+#define mmCP_AQL_SMM_STATUS_BASE_IDX 0
+#define mmCP_RB0_BASE 0x1040
+#define mmCP_RB0_BASE_BASE_IDX 0
+#define mmCP_RB_BASE 0x1040
+#define mmCP_RB_BASE_BASE_IDX 0
+#define mmCP_RB0_CNTL 0x1041
+#define mmCP_RB0_CNTL_BASE_IDX 0
+#define mmCP_RB_CNTL 0x1041
+#define mmCP_RB_CNTL_BASE_IDX 0
+#define mmCP_RB_RPTR_WR 0x1042
+#define mmCP_RB_RPTR_WR_BASE_IDX 0
+#define mmCP_RB0_RPTR_ADDR 0x1043
+#define mmCP_RB0_RPTR_ADDR_BASE_IDX 0
+#define mmCP_RB_RPTR_ADDR 0x1043
+#define mmCP_RB_RPTR_ADDR_BASE_IDX 0
+#define mmCP_RB0_RPTR_ADDR_HI 0x1044
+#define mmCP_RB0_RPTR_ADDR_HI_BASE_IDX 0
+#define mmCP_RB_RPTR_ADDR_HI 0x1044
+#define mmCP_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmCP_RB0_BUFSZ_MASK 0x1045
+#define mmCP_RB0_BUFSZ_MASK_BASE_IDX 0
+#define mmCP_RB_BUFSZ_MASK 0x1045
+#define mmCP_RB_BUFSZ_MASK_BASE_IDX 0
+#define mmCP_RB_WPTR_POLL_ADDR_LO 0x1046
+#define mmCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmCP_RB_WPTR_POLL_ADDR_HI 0x1047
+#define mmCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmGC_PRIV_MODE 0x1048
+#define mmGC_PRIV_MODE_BASE_IDX 0
+#define mmCP_INT_CNTL 0x1049
+#define mmCP_INT_CNTL_BASE_IDX 0
+#define mmCP_INT_STATUS 0x104a
+#define mmCP_INT_STATUS_BASE_IDX 0
+#define mmCP_DEVICE_ID 0x104b
+#define mmCP_DEVICE_ID_BASE_IDX 0
+#define mmCP_ME0_PIPE_PRIORITY_CNTS 0x104c
+#define mmCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0
+#define mmCP_RING_PRIORITY_CNTS 0x104c
+#define mmCP_RING_PRIORITY_CNTS_BASE_IDX 0
+#define mmCP_ME0_PIPE0_PRIORITY 0x104d
+#define mmCP_ME0_PIPE0_PRIORITY_BASE_IDX 0
+#define mmCP_RING0_PRIORITY 0x104d
+#define mmCP_RING0_PRIORITY_BASE_IDX 0
+#define mmCP_ME0_PIPE1_PRIORITY 0x104e
+#define mmCP_ME0_PIPE1_PRIORITY_BASE_IDX 0
+#define mmCP_RING1_PRIORITY 0x104e
+#define mmCP_RING1_PRIORITY_BASE_IDX 0
+#define mmCP_ME0_PIPE2_PRIORITY 0x104f
+#define mmCP_ME0_PIPE2_PRIORITY_BASE_IDX 0
+#define mmCP_RING2_PRIORITY 0x104f
+#define mmCP_RING2_PRIORITY_BASE_IDX 0
+#define mmCP_FATAL_ERROR 0x1050
+#define mmCP_FATAL_ERROR_BASE_IDX 0
+#define mmCP_RB_VMID 0x1051
+#define mmCP_RB_VMID_BASE_IDX 0
+#define mmCP_ME0_PIPE0_VMID 0x1052
+#define mmCP_ME0_PIPE0_VMID_BASE_IDX 0
+#define mmCP_ME0_PIPE1_VMID 0x1053
+#define mmCP_ME0_PIPE1_VMID_BASE_IDX 0
+#define mmCP_RB0_WPTR 0x1054
+#define mmCP_RB0_WPTR_BASE_IDX 0
+#define mmCP_RB_WPTR 0x1054
+#define mmCP_RB_WPTR_BASE_IDX 0
+#define mmCP_RB0_WPTR_HI 0x1055
+#define mmCP_RB0_WPTR_HI_BASE_IDX 0
+#define mmCP_RB_WPTR_HI 0x1055
+#define mmCP_RB_WPTR_HI_BASE_IDX 0
+#define mmCP_RB1_WPTR 0x1056
+#define mmCP_RB1_WPTR_BASE_IDX 0
+#define mmCP_RB1_WPTR_HI 0x1057
+#define mmCP_RB1_WPTR_HI_BASE_IDX 0
+#define mmCP_RB2_WPTR 0x1058
+#define mmCP_RB2_WPTR_BASE_IDX 0
+#define mmCP_RB_DOORBELL_CONTROL 0x1059
+#define mmCP_RB_DOORBELL_CONTROL_BASE_IDX 0
+#define mmCP_RB_DOORBELL_RANGE_LOWER 0x105a
+#define mmCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0
+#define mmCP_RB_DOORBELL_RANGE_UPPER 0x105b
+#define mmCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0
+#define mmCP_MEC_DOORBELL_RANGE_LOWER 0x105c
+#define mmCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0
+#define mmCP_MEC_DOORBELL_RANGE_UPPER 0x105d
+#define mmCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0
+#define mmCPG_UTCL1_ERROR 0x105e
+#define mmCPG_UTCL1_ERROR_BASE_IDX 0
+#define mmCPC_UTCL1_ERROR 0x105f
+#define mmCPC_UTCL1_ERROR_BASE_IDX 0
+#define mmCP_RB1_BASE 0x1060
+#define mmCP_RB1_BASE_BASE_IDX 0
+#define mmCP_RB1_CNTL 0x1061
+#define mmCP_RB1_CNTL_BASE_IDX 0
+#define mmCP_RB1_RPTR_ADDR 0x1062
+#define mmCP_RB1_RPTR_ADDR_BASE_IDX 0
+#define mmCP_RB1_RPTR_ADDR_HI 0x1063
+#define mmCP_RB1_RPTR_ADDR_HI_BASE_IDX 0
+#define mmCP_RB2_BASE 0x1065
+#define mmCP_RB2_BASE_BASE_IDX 0
+#define mmCP_RB2_CNTL 0x1066
+#define mmCP_RB2_CNTL_BASE_IDX 0
+#define mmCP_RB2_RPTR_ADDR 0x1067
+#define mmCP_RB2_RPTR_ADDR_BASE_IDX 0
+#define mmCP_RB2_RPTR_ADDR_HI 0x1068
+#define mmCP_RB2_RPTR_ADDR_HI_BASE_IDX 0
+#define mmCP_RB0_ACTIVE 0x1069
+#define mmCP_RB0_ACTIVE_BASE_IDX 0
+#define mmCP_RB_ACTIVE 0x1069
+#define mmCP_RB_ACTIVE_BASE_IDX 0
+#define mmCP_INT_CNTL_RING0 0x106a
+#define mmCP_INT_CNTL_RING0_BASE_IDX 0
+#define mmCP_INT_CNTL_RING1 0x106b
+#define mmCP_INT_CNTL_RING1_BASE_IDX 0
+#define mmCP_INT_CNTL_RING2 0x106c
+#define mmCP_INT_CNTL_RING2_BASE_IDX 0
+#define mmCP_INT_STATUS_RING0 0x106d
+#define mmCP_INT_STATUS_RING0_BASE_IDX 0
+#define mmCP_INT_STATUS_RING1 0x106e
+#define mmCP_INT_STATUS_RING1_BASE_IDX 0
+#define mmCP_INT_STATUS_RING2 0x106f
+#define mmCP_INT_STATUS_RING2_BASE_IDX 0
+#define mmCP_PWR_CNTL 0x1078
+#define mmCP_PWR_CNTL_BASE_IDX 0
+#define mmCP_MEM_SLP_CNTL 0x1079
+#define mmCP_MEM_SLP_CNTL_BASE_IDX 0
+#define mmCP_ECC_FIRSTOCCURRENCE 0x107a
+#define mmCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0
+#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x107b
+#define mmCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0
+#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x107c
+#define mmCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0
+#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x107d
+#define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0
+#define mmGB_EDC_MODE 0x107e
+#define mmGB_EDC_MODE_BASE_IDX 0
+#define mmCP_CPF_DEBUG 0x1080
+#define mmCP_PQ_WPTR_POLL_CNTL 0x1083
+#define mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmCP_PQ_WPTR_POLL_CNTL1 0x1084
+#define mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0
+#define mmCP_ME1_PIPE0_INT_CNTL 0x1085
+#define mmCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0
+#define mmCP_ME1_PIPE1_INT_CNTL 0x1086
+#define mmCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0
+#define mmCP_ME1_PIPE2_INT_CNTL 0x1087
+#define mmCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0
+#define mmCP_ME1_PIPE3_INT_CNTL 0x1088
+#define mmCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0
+#define mmCP_ME2_PIPE0_INT_CNTL 0x1089
+#define mmCP_ME2_PIPE0_INT_CNTL_BASE_IDX 0
+#define mmCP_ME2_PIPE1_INT_CNTL 0x108a
+#define mmCP_ME2_PIPE1_INT_CNTL_BASE_IDX 0
+#define mmCP_ME2_PIPE2_INT_CNTL 0x108b
+#define mmCP_ME2_PIPE2_INT_CNTL_BASE_IDX 0
+#define mmCP_ME2_PIPE3_INT_CNTL 0x108c
+#define mmCP_ME2_PIPE3_INT_CNTL_BASE_IDX 0
+#define mmCP_ME1_PIPE0_INT_STATUS 0x108d
+#define mmCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0
+#define mmCP_ME1_PIPE1_INT_STATUS 0x108e
+#define mmCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0
+#define mmCP_ME1_PIPE2_INT_STATUS 0x108f
+#define mmCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0
+#define mmCP_ME1_PIPE3_INT_STATUS 0x1090
+#define mmCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0
+#define mmCP_ME2_PIPE0_INT_STATUS 0x1091
+#define mmCP_ME2_PIPE0_INT_STATUS_BASE_IDX 0
+#define mmCP_ME2_PIPE1_INT_STATUS 0x1092
+#define mmCP_ME2_PIPE1_INT_STATUS_BASE_IDX 0
+#define mmCP_ME2_PIPE2_INT_STATUS 0x1093
+#define mmCP_ME2_PIPE2_INT_STATUS_BASE_IDX 0
+#define mmCP_ME2_PIPE3_INT_STATUS 0x1094
+#define mmCP_ME2_PIPE3_INT_STATUS_BASE_IDX 0
+#define mmCP_ME1_INT_STAT_DEBUG 0x1095
+#define mmCP_ME1_INT_STAT_DEBUG_BASE_IDX 0
+#define mmCP_ME2_INT_STAT_DEBUG 0x1096
+#define mmCP_ME2_INT_STAT_DEBUG_BASE_IDX 0
+#define mmCC_GC_EDC_CONFIG 0x1098
+#define mmCC_GC_EDC_CONFIG_BASE_IDX 0
+#define mmCP_ME1_PIPE_PRIORITY_CNTS 0x1099
+#define mmCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0
+#define mmCP_ME1_PIPE0_PRIORITY 0x109a
+#define mmCP_ME1_PIPE0_PRIORITY_BASE_IDX 0
+#define mmCP_ME1_PIPE1_PRIORITY 0x109b
+#define mmCP_ME1_PIPE1_PRIORITY_BASE_IDX 0
+#define mmCP_ME1_PIPE2_PRIORITY 0x109c
+#define mmCP_ME1_PIPE2_PRIORITY_BASE_IDX 0
+#define mmCP_ME1_PIPE3_PRIORITY 0x109d
+#define mmCP_ME1_PIPE3_PRIORITY_BASE_IDX 0
+#define mmCP_ME2_PIPE_PRIORITY_CNTS 0x109e
+#define mmCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX 0
+#define mmCP_ME2_PIPE0_PRIORITY 0x109f
+#define mmCP_ME2_PIPE0_PRIORITY_BASE_IDX 0
+#define mmCP_ME2_PIPE1_PRIORITY 0x10a0
+#define mmCP_ME2_PIPE1_PRIORITY_BASE_IDX 0
+#define mmCP_ME2_PIPE2_PRIORITY 0x10a1
+#define mmCP_ME2_PIPE2_PRIORITY_BASE_IDX 0
+#define mmCP_ME2_PIPE3_PRIORITY 0x10a2
+#define mmCP_ME2_PIPE3_PRIORITY_BASE_IDX 0
+#define mmCP_CE_PRGRM_CNTR_START 0x10a3
+#define mmCP_CE_PRGRM_CNTR_START_BASE_IDX 0
+#define mmCP_PFP_PRGRM_CNTR_START 0x10a4
+#define mmCP_PFP_PRGRM_CNTR_START_BASE_IDX 0
+#define mmCP_ME_PRGRM_CNTR_START 0x10a5
+#define mmCP_ME_PRGRM_CNTR_START_BASE_IDX 0
+#define mmCP_MEC1_PRGRM_CNTR_START 0x10a6
+#define mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0
+#define mmCP_MEC2_PRGRM_CNTR_START 0x10a7
+#define mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX 0
+#define mmCP_CE_INTR_ROUTINE_START 0x10a8
+#define mmCP_CE_INTR_ROUTINE_START_BASE_IDX 0
+#define mmCP_PFP_INTR_ROUTINE_START 0x10a9
+#define mmCP_PFP_INTR_ROUTINE_START_BASE_IDX 0
+#define mmCP_ME_INTR_ROUTINE_START 0x10aa
+#define mmCP_ME_INTR_ROUTINE_START_BASE_IDX 0
+#define mmCP_MEC1_INTR_ROUTINE_START 0x10ab
+#define mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0
+#define mmCP_MEC2_INTR_ROUTINE_START 0x10ac
+#define mmCP_MEC2_INTR_ROUTINE_START_BASE_IDX 0
+#define mmCP_CONTEXT_CNTL 0x10ad
+#define mmCP_CONTEXT_CNTL_BASE_IDX 0
+#define mmCP_MAX_CONTEXT 0x10ae
+#define mmCP_MAX_CONTEXT_BASE_IDX 0
+#define mmCP_IQ_WAIT_TIME1 0x10af
+#define mmCP_IQ_WAIT_TIME1_BASE_IDX 0
+#define mmCP_IQ_WAIT_TIME2 0x10b0
+#define mmCP_IQ_WAIT_TIME2_BASE_IDX 0
+#define mmCP_RB0_BASE_HI 0x10b1
+#define mmCP_RB0_BASE_HI_BASE_IDX 0
+#define mmCP_RB1_BASE_HI 0x10b2
+#define mmCP_RB1_BASE_HI_BASE_IDX 0
+#define mmCP_VMID_RESET 0x10b3
+#define mmCP_VMID_RESET_BASE_IDX 0
+#define mmCPC_INT_CNTL 0x10b4
+#define mmCPC_INT_CNTL_BASE_IDX 0
+#define mmCPC_INT_STATUS 0x10b5
+#define mmCPC_INT_STATUS_BASE_IDX 0
+#define mmCP_VMID_PREEMPT 0x10b6
+#define mmCP_VMID_PREEMPT_BASE_IDX 0
+#define mmCPC_INT_CNTX_ID 0x10b7
+#define mmCPC_INT_CNTX_ID_BASE_IDX 0
+#define mmCP_PQ_STATUS 0x10b8
+#define mmCP_PQ_STATUS_BASE_IDX 0
+#define mmCP_CPC_IC_BASE_LO 0x10b9
+#define mmCP_CPC_IC_BASE_LO_BASE_IDX 0
+#define mmCP_CPC_IC_BASE_HI 0x10ba
+#define mmCP_CPC_IC_BASE_HI_BASE_IDX 0
+#define mmCP_CPC_IC_BASE_CNTL 0x10bb
+#define mmCP_CPC_IC_BASE_CNTL_BASE_IDX 0
+#define mmCP_CPC_IC_OP_CNTL 0x10bc
+#define mmCP_CPC_IC_OP_CNTL_BASE_IDX 0
+#define mmCP_MEC1_F32_INT_DIS 0x10bd
+#define mmCP_MEC1_F32_INT_DIS_BASE_IDX 0
+#define mmCP_MEC2_F32_INT_DIS 0x10be
+#define mmCP_MEC2_F32_INT_DIS_BASE_IDX 0
+#define mmCP_VMID_STATUS 0x10bf
+#define mmCP_VMID_STATUS_BASE_IDX 0
+
+
+// addressBlock: gc_cppdec2
+// base address: 0xc600
+#define mmCP_RB_DOORBELL_CONTROL_SCH_0 0x1180
+#define mmCP_RB_DOORBELL_CONTROL_SCH_0_BASE_IDX 0
+#define mmCP_RB_DOORBELL_CONTROL_SCH_1 0x1181
+#define mmCP_RB_DOORBELL_CONTROL_SCH_1_BASE_IDX 0
+#define mmCP_RB_DOORBELL_CONTROL_SCH_2 0x1182
+#define mmCP_RB_DOORBELL_CONTROL_SCH_2_BASE_IDX 0
+#define mmCP_RB_DOORBELL_CONTROL_SCH_3 0x1183
+#define mmCP_RB_DOORBELL_CONTROL_SCH_3_BASE_IDX 0
+#define mmCP_RB_DOORBELL_CONTROL_SCH_4 0x1184
+#define mmCP_RB_DOORBELL_CONTROL_SCH_4_BASE_IDX 0
+#define mmCP_RB_DOORBELL_CONTROL_SCH_5 0x1185
+#define mmCP_RB_DOORBELL_CONTROL_SCH_5_BASE_IDX 0
+#define mmCP_RB_DOORBELL_CONTROL_SCH_6 0x1186
+#define mmCP_RB_DOORBELL_CONTROL_SCH_6_BASE_IDX 0
+#define mmCP_RB_DOORBELL_CONTROL_SCH_7 0x1187
+#define mmCP_RB_DOORBELL_CONTROL_SCH_7_BASE_IDX 0
+#define mmCP_RB_DOORBELL_CLEAR 0x1188
+#define mmCP_RB_DOORBELL_CLEAR_BASE_IDX 0
+#define mmCP_GFX_MQD_CONTROL 0x11a0
+#define mmCP_GFX_MQD_CONTROL_BASE_IDX 0
+#define mmCP_GFX_MQD_BASE_ADDR 0x11a1
+#define mmCP_GFX_MQD_BASE_ADDR_BASE_IDX 0
+#define mmCP_GFX_MQD_BASE_ADDR_HI 0x11a2
+#define mmCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0
+#define mmCP_RB_STATUS 0x11a3
+#define mmCP_RB_STATUS_BASE_IDX 0
+#define mmCPG_UTCL1_STATUS 0x11b4
+#define mmCPG_UTCL1_STATUS_BASE_IDX 0
+#define mmCPC_UTCL1_STATUS 0x11b5
+#define mmCPC_UTCL1_STATUS_BASE_IDX 0
+#define mmCPF_UTCL1_STATUS 0x11b6
+#define mmCPF_UTCL1_STATUS_BASE_IDX 0
+#define mmCP_SD_CNTL 0x11b7
+#define mmCP_SD_CNTL_BASE_IDX 0
+#define mmCP_SOFT_RESET_CNTL 0x11b9
+#define mmCP_SOFT_RESET_CNTL_BASE_IDX 0
+#define mmCP_CPC_GFX_CNTL 0x11ba
+#define mmCP_CPC_GFX_CNTL_BASE_IDX 0
+
+
+// addressBlock: gc_spipdec
+// base address: 0xc700
+#define mmSPI_ARB_PRIORITY 0x11c0
+#define mmSPI_ARB_PRIORITY_BASE_IDX 0
+#define mmSPI_ARB_CYCLES_0 0x11c1
+#define mmSPI_ARB_CYCLES_0_BASE_IDX 0
+#define mmSPI_ARB_CYCLES_1 0x11c2
+#define mmSPI_ARB_CYCLES_1_BASE_IDX 0
+#define mmSPI_CDBG_SYS_GFX 0x11c3
+#define mmSPI_CDBG_SYS_GFX_BASE_IDX 0
+#define mmSPI_CDBG_SYS_HP3D 0x11c4
+#define mmSPI_CDBG_SYS_HP3D_BASE_IDX 0
+#define mmSPI_CDBG_SYS_CS0 0x11c5
+#define mmSPI_CDBG_SYS_CS0_BASE_IDX 0
+#define mmSPI_CDBG_SYS_CS1 0x11c6
+#define mmSPI_CDBG_SYS_CS1_BASE_IDX 0
+#define mmSPI_WCL_PIPE_PERCENT_GFX 0x11c7
+#define mmSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX 0
+#define mmSPI_WCL_PIPE_PERCENT_HP3D 0x11c8
+#define mmSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX 0
+#define mmSPI_WCL_PIPE_PERCENT_CS0 0x11c9
+#define mmSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX 0
+#define mmSPI_WCL_PIPE_PERCENT_CS1 0x11ca
+#define mmSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX 0
+#define mmSPI_WCL_PIPE_PERCENT_CS2 0x11cb
+#define mmSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX 0
+#define mmSPI_WCL_PIPE_PERCENT_CS3 0x11cc
+#define mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0
+#define mmSPI_WCL_PIPE_PERCENT_CS4 0x11cd
+#define mmSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX 0
+#define mmSPI_WCL_PIPE_PERCENT_CS5 0x11ce
+#define mmSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX 0
+#define mmSPI_WCL_PIPE_PERCENT_CS6 0x11cf
+#define mmSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0
+#define mmSPI_WCL_PIPE_PERCENT_CS7 0x11d0
+#define mmSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0
+#define mmSPI_GDBG_WAVE_CNTL 0x11d1
+#define mmSPI_GDBG_WAVE_CNTL_BASE_IDX 0
+#define mmSPI_GDBG_TRAP_CONFIG 0x11d2
+#define mmSPI_GDBG_TRAP_CONFIG_BASE_IDX 0
+#define mmSPI_GDBG_TRAP_MASK 0x11d3
+#define mmSPI_GDBG_TRAP_MASK_BASE_IDX 0
+#define mmSPI_GDBG_WAVE_CNTL2 0x11d4
+#define mmSPI_GDBG_WAVE_CNTL2_BASE_IDX 0
+#define mmSPI_GDBG_WAVE_CNTL3 0x11d5
+#define mmSPI_GDBG_WAVE_CNTL3_BASE_IDX 0
+#define mmSPI_GDBG_TRAP_DATA0 0x11d8
+#define mmSPI_GDBG_TRAP_DATA0_BASE_IDX 0
+#define mmSPI_GDBG_TRAP_DATA1 0x11d9
+#define mmSPI_GDBG_TRAP_DATA1_BASE_IDX 0
+#define mmSPI_RESET_DEBUG 0x11da
+#define mmSPI_RESET_DEBUG_BASE_IDX 0
+#define mmSPI_COMPUTE_QUEUE_RESET 0x11db
+#define mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_0 0x11dc
+#define mmSPI_RESOURCE_RESERVE_CU_0_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_1 0x11dd
+#define mmSPI_RESOURCE_RESERVE_CU_1_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_2 0x11de
+#define mmSPI_RESOURCE_RESERVE_CU_2_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_3 0x11df
+#define mmSPI_RESOURCE_RESERVE_CU_3_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_4 0x11e0
+#define mmSPI_RESOURCE_RESERVE_CU_4_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_5 0x11e1
+#define mmSPI_RESOURCE_RESERVE_CU_5_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_6 0x11e2
+#define mmSPI_RESOURCE_RESERVE_CU_6_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_7 0x11e3
+#define mmSPI_RESOURCE_RESERVE_CU_7_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_8 0x11e4
+#define mmSPI_RESOURCE_RESERVE_CU_8_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_9 0x11e5
+#define mmSPI_RESOURCE_RESERVE_CU_9_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x11e6
+#define mmSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x11e7
+#define mmSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x11e8
+#define mmSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x11e9
+#define mmSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x11ea
+#define mmSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x11eb
+#define mmSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x11ec
+#define mmSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x11ed
+#define mmSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x11ee
+#define mmSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x11ef
+#define mmSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_10 0x11f0
+#define mmSPI_RESOURCE_RESERVE_CU_10_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_11 0x11f1
+#define mmSPI_RESOURCE_RESERVE_CU_11_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_10 0x11f2
+#define mmSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_11 0x11f3
+#define mmSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_12 0x11f4
+#define mmSPI_RESOURCE_RESERVE_CU_12_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_13 0x11f5
+#define mmSPI_RESOURCE_RESERVE_CU_13_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_14 0x11f6
+#define mmSPI_RESOURCE_RESERVE_CU_14_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_15 0x11f7
+#define mmSPI_RESOURCE_RESERVE_CU_15_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_12 0x11f8
+#define mmSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_13 0x11f9
+#define mmSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_14 0x11fa
+#define mmSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_15 0x11fb
+#define mmSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX 0
+#define mmSPI_COMPUTE_WF_CTX_SAVE 0x11fc
+#define mmSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX 0
+#define mmSPI_ARB_CNTL_0 0x11fd
+#define mmSPI_ARB_CNTL_0_BASE_IDX 0
+
+
+// addressBlock: gc_cpphqddec
+// base address: 0xc800
+#define mmCP_HQD_GFX_CONTROL 0x123e
+#define mmCP_HQD_GFX_CONTROL_BASE_IDX 0
+#define mmCP_HQD_GFX_STATUS 0x123f
+#define mmCP_HQD_GFX_STATUS_BASE_IDX 0
+#define mmCP_HPD_ROQ_OFFSETS 0x1240
+#define mmCP_HPD_ROQ_OFFSETS_BASE_IDX 0
+#define mmCP_HPD_STATUS0 0x1241
+#define mmCP_HPD_STATUS0_BASE_IDX 0
+#define mmCP_HPD_UTCL1_CNTL 0x1242
+#define mmCP_HPD_UTCL1_CNTL_BASE_IDX 0
+#define mmCP_HPD_UTCL1_ERROR 0x1243
+#define mmCP_HPD_UTCL1_ERROR_BASE_IDX 0
+#define mmCP_HPD_UTCL1_ERROR_ADDR 0x1244
+#define mmCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0
+#define mmCP_MQD_BASE_ADDR 0x1245
+#define mmCP_MQD_BASE_ADDR_BASE_IDX 0
+#define mmCP_MQD_BASE_ADDR_HI 0x1246
+#define mmCP_MQD_BASE_ADDR_HI_BASE_IDX 0
+#define mmCP_HQD_ACTIVE 0x1247
+#define mmCP_HQD_ACTIVE_BASE_IDX 0
+#define mmCP_HQD_VMID 0x1248
+#define mmCP_HQD_VMID_BASE_IDX 0
+#define mmCP_HQD_PERSISTENT_STATE 0x1249
+#define mmCP_HQD_PERSISTENT_STATE_BASE_IDX 0
+#define mmCP_HQD_PIPE_PRIORITY 0x124a
+#define mmCP_HQD_PIPE_PRIORITY_BASE_IDX 0
+#define mmCP_HQD_QUEUE_PRIORITY 0x124b
+#define mmCP_HQD_QUEUE_PRIORITY_BASE_IDX 0
+#define mmCP_HQD_QUANTUM 0x124c
+#define mmCP_HQD_QUANTUM_BASE_IDX 0
+#define mmCP_HQD_PQ_BASE 0x124d
+#define mmCP_HQD_PQ_BASE_BASE_IDX 0
+#define mmCP_HQD_PQ_BASE_HI 0x124e
+#define mmCP_HQD_PQ_BASE_HI_BASE_IDX 0
+#define mmCP_HQD_PQ_RPTR 0x124f
+#define mmCP_HQD_PQ_RPTR_BASE_IDX 0
+#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x1250
+#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0
+#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251
+#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0
+#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x1252
+#define mmCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0
+#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1253
+#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1254
+#define mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0
+#define mmCP_HQD_PQ_CONTROL 0x1256
+#define mmCP_HQD_PQ_CONTROL_BASE_IDX 0
+#define mmCP_HQD_IB_BASE_ADDR 0x1257
+#define mmCP_HQD_IB_BASE_ADDR_BASE_IDX 0
+#define mmCP_HQD_IB_BASE_ADDR_HI 0x1258
+#define mmCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0
+#define mmCP_HQD_IB_RPTR 0x1259
+#define mmCP_HQD_IB_RPTR_BASE_IDX 0
+#define mmCP_HQD_IB_CONTROL 0x125a
+#define mmCP_HQD_IB_CONTROL_BASE_IDX 0
+#define mmCP_HQD_IQ_TIMER 0x125b
+#define mmCP_HQD_IQ_TIMER_BASE_IDX 0
+#define mmCP_HQD_IQ_RPTR 0x125c
+#define mmCP_HQD_IQ_RPTR_BASE_IDX 0
+#define mmCP_HQD_DEQUEUE_REQUEST 0x125d
+#define mmCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0
+#define mmCP_HQD_DMA_OFFLOAD 0x125e
+#define mmCP_HQD_DMA_OFFLOAD_BASE_IDX 0
+#define mmCP_HQD_OFFLOAD 0x125e
+#define mmCP_HQD_OFFLOAD_BASE_IDX 0
+#define mmCP_HQD_SEMA_CMD 0x125f
+#define mmCP_HQD_SEMA_CMD_BASE_IDX 0
+#define mmCP_HQD_MSG_TYPE 0x1260
+#define mmCP_HQD_MSG_TYPE_BASE_IDX 0
+#define mmCP_HQD_ATOMIC0_PREOP_LO 0x1261
+#define mmCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0
+#define mmCP_HQD_ATOMIC0_PREOP_HI 0x1262
+#define mmCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0
+#define mmCP_HQD_ATOMIC1_PREOP_LO 0x1263
+#define mmCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0
+#define mmCP_HQD_ATOMIC1_PREOP_HI 0x1264
+#define mmCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0
+#define mmCP_HQD_HQ_SCHEDULER0 0x1265
+#define mmCP_HQD_HQ_SCHEDULER0_BASE_IDX 0
+#define mmCP_HQD_HQ_STATUS0 0x1265
+#define mmCP_HQD_HQ_STATUS0_BASE_IDX 0
+#define mmCP_HQD_HQ_CONTROL0 0x1266
+#define mmCP_HQD_HQ_CONTROL0_BASE_IDX 0
+#define mmCP_HQD_HQ_SCHEDULER1 0x1266
+#define mmCP_HQD_HQ_SCHEDULER1_BASE_IDX 0
+#define mmCP_MQD_CONTROL 0x1267
+#define mmCP_MQD_CONTROL_BASE_IDX 0
+#define mmCP_HQD_HQ_STATUS1 0x1268
+#define mmCP_HQD_HQ_STATUS1_BASE_IDX 0
+#define mmCP_HQD_HQ_CONTROL1 0x1269
+#define mmCP_HQD_HQ_CONTROL1_BASE_IDX 0
+#define mmCP_HQD_EOP_BASE_ADDR 0x126a
+#define mmCP_HQD_EOP_BASE_ADDR_BASE_IDX 0
+#define mmCP_HQD_EOP_BASE_ADDR_HI 0x126b
+#define mmCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0
+#define mmCP_HQD_EOP_CONTROL 0x126c
+#define mmCP_HQD_EOP_CONTROL_BASE_IDX 0
+#define mmCP_HQD_EOP_RPTR 0x126d
+#define mmCP_HQD_EOP_RPTR_BASE_IDX 0
+#define mmCP_HQD_EOP_WPTR 0x126e
+#define mmCP_HQD_EOP_WPTR_BASE_IDX 0
+#define mmCP_HQD_EOP_EVENTS 0x126f
+#define mmCP_HQD_EOP_EVENTS_BASE_IDX 0
+#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x1270
+#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0
+#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x1271
+#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0
+#define mmCP_HQD_CTX_SAVE_CONTROL 0x1272
+#define mmCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0
+#define mmCP_HQD_CNTL_STACK_OFFSET 0x1273
+#define mmCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0
+#define mmCP_HQD_CNTL_STACK_SIZE 0x1274
+#define mmCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0
+#define mmCP_HQD_WG_STATE_OFFSET 0x1275
+#define mmCP_HQD_WG_STATE_OFFSET_BASE_IDX 0
+#define mmCP_HQD_CTX_SAVE_SIZE 0x1276
+#define mmCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0
+#define mmCP_HQD_GDS_RESOURCE_STATE 0x1277
+#define mmCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0
+#define mmCP_HQD_ERROR 0x1278
+#define mmCP_HQD_ERROR_BASE_IDX 0
+#define mmCP_HQD_EOP_WPTR_MEM 0x1279
+#define mmCP_HQD_EOP_WPTR_MEM_BASE_IDX 0
+#define mmCP_HQD_AQL_CONTROL 0x127a
+#define mmCP_HQD_AQL_CONTROL_BASE_IDX 0
+#define mmCP_HQD_PQ_WPTR_LO 0x127b
+#define mmCP_HQD_PQ_WPTR_LO_BASE_IDX 0
+#define mmCP_HQD_PQ_WPTR_HI 0x127c
+#define mmCP_HQD_PQ_WPTR_HI_BASE_IDX 0
+
+
+// addressBlock: gc_didtdec
+// base address: 0xca00
+#define mmDIDT_IND_INDEX 0x1280
+#define mmDIDT_IND_INDEX_BASE_IDX 0
+#define mmDIDT_IND_DATA 0x1281
+#define mmDIDT_IND_DATA_BASE_IDX 0
+
+
+// addressBlock: gc_gccacdec
+// base address: 0xca10
+#define mmGC_CAC_CTRL_1 0x1284
+#define mmGC_CAC_CTRL_1_BASE_IDX 0
+#define mmGC_CAC_CTRL_2 0x1285
+#define mmGC_CAC_CTRL_2_BASE_IDX 0
+#define mmGC_CAC_CGTT_CLK_CTRL 0x1286
+#define mmGC_CAC_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmGC_CAC_AGGR_LOWER 0x1287
+#define mmGC_CAC_AGGR_LOWER_BASE_IDX 0
+#define mmGC_CAC_AGGR_UPPER 0x1288
+#define mmGC_CAC_AGGR_UPPER_BASE_IDX 0
+#define mmGC_CAC_SOFT_CTRL 0x128d
+#define mmGC_CAC_SOFT_CTRL_BASE_IDX 0
+#define mmGC_DIDT_CTRL0 0x128e
+#define mmGC_DIDT_CTRL0_BASE_IDX 0
+#define mmGC_DIDT_CTRL1 0x128f
+#define mmGC_DIDT_CTRL1_BASE_IDX 0
+#define mmGC_DIDT_CTRL2 0x1290
+#define mmGC_DIDT_CTRL2_BASE_IDX 0
+#define mmGC_DIDT_WEIGHT 0x1291
+#define mmGC_DIDT_WEIGHT_BASE_IDX 0
+#define mmGC_DIDT_WEIGHT_1 0x1292
+#define mmGC_DIDT_WEIGHT_1_BASE_IDX 0
+#define mmGC_EDC_CTRL 0x1293
+#define mmGC_EDC_CTRL_BASE_IDX 0
+#define mmGC_EDC_THRESHOLD 0x1294
+#define mmGC_EDC_THRESHOLD_BASE_IDX 0
+#define mmGC_EDC_STATUS 0x1295
+#define mmGC_EDC_STATUS_BASE_IDX 0
+#define mmGC_EDC_OVERFLOW 0x1296
+#define mmGC_EDC_OVERFLOW_BASE_IDX 0
+#define mmGC_EDC_ROLLING_POWER_DELTA 0x1297
+#define mmGC_EDC_ROLLING_POWER_DELTA_BASE_IDX 0
+#define mmGC_DIDT_DROOP_CTRL 0x1298
+#define mmGC_DIDT_DROOP_CTRL_BASE_IDX 0
+#define mmGC_EDC_DROOP_CTRL 0x1299
+#define mmGC_EDC_DROOP_CTRL_BASE_IDX 0
+#define mmGC_CAC_IND_INDEX 0x129a
+#define mmGC_CAC_IND_INDEX_BASE_IDX 0
+#define mmGC_CAC_IND_DATA 0x129b
+#define mmGC_CAC_IND_DATA_BASE_IDX 0
+#define mmSE_CAC_CGTT_CLK_CTRL 0x129c
+#define mmSE_CAC_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmSE_CAC_IND_INDEX 0x129d
+#define mmSE_CAC_IND_INDEX_BASE_IDX 0
+#define mmSE_CAC_IND_DATA 0x129e
+#define mmSE_CAC_IND_DATA_BASE_IDX 0
+
+
+// addressBlock: gc_tcpdec
+// base address: 0xca80
+#define mmTCP_WATCH0_ADDR_H 0x12a0
+#define mmTCP_WATCH0_ADDR_H_BASE_IDX 0
+#define mmTCP_WATCH0_ADDR_L 0x12a1
+#define mmTCP_WATCH0_ADDR_L_BASE_IDX 0
+#define mmTCP_WATCH0_CNTL 0x12a2
+#define mmTCP_WATCH0_CNTL_BASE_IDX 0
+#define mmTCP_WATCH1_ADDR_H 0x12a3
+#define mmTCP_WATCH1_ADDR_H_BASE_IDX 0
+#define mmTCP_WATCH1_ADDR_L 0x12a4
+#define mmTCP_WATCH1_ADDR_L_BASE_IDX 0
+#define mmTCP_WATCH1_CNTL 0x12a5
+#define mmTCP_WATCH1_CNTL_BASE_IDX 0
+#define mmTCP_WATCH2_ADDR_H 0x12a6
+#define mmTCP_WATCH2_ADDR_H_BASE_IDX 0
+#define mmTCP_WATCH2_ADDR_L 0x12a7
+#define mmTCP_WATCH2_ADDR_L_BASE_IDX 0
+#define mmTCP_WATCH2_CNTL 0x12a8
+#define mmTCP_WATCH2_CNTL_BASE_IDX 0
+#define mmTCP_WATCH3_ADDR_H 0x12a9
+#define mmTCP_WATCH3_ADDR_H_BASE_IDX 0
+#define mmTCP_WATCH3_ADDR_L 0x12aa
+#define mmTCP_WATCH3_ADDR_L_BASE_IDX 0
+#define mmTCP_WATCH3_CNTL 0x12ab
+#define mmTCP_WATCH3_CNTL_BASE_IDX 0
+#define mmTCP_GATCL1_CNTL 0x12b0
+#define mmTCP_GATCL1_CNTL_BASE_IDX 0
+#define mmTCP_ATC_EDC_GATCL1_CNT 0x12b1
+#define mmTCP_ATC_EDC_GATCL1_CNT_BASE_IDX 0
+#define mmTCP_GATCL1_DSM_CNTL 0x12b2
+#define mmTCP_GATCL1_DSM_CNTL_BASE_IDX 0
+#define mmTCP_CNTL2 0x12b4
+#define mmTCP_CNTL2_BASE_IDX 0
+#define mmTCP_UTCL1_CNTL1 0x12b5
+#define mmTCP_UTCL1_CNTL1_BASE_IDX 0
+#define mmTCP_UTCL1_CNTL2 0x12b6
+#define mmTCP_UTCL1_CNTL2_BASE_IDX 0
+#define mmTCP_UTCL1_STATUS 0x12b7
+#define mmTCP_UTCL1_STATUS_BASE_IDX 0
+#define mmTCP_PERFCOUNTER_FILTER 0x12b9
+#define mmTCP_PERFCOUNTER_FILTER_BASE_IDX 0
+#define mmTCP_PERFCOUNTER_FILTER_EN 0x12ba
+#define mmTCP_PERFCOUNTER_FILTER_EN_BASE_IDX 0
+
+
+// addressBlock: gc_gdspdec
+// base address: 0xcc00
+#define mmGDS_VMID0_BASE 0x1300
+#define mmGDS_VMID0_BASE_BASE_IDX 0
+#define mmGDS_VMID0_SIZE 0x1301
+#define mmGDS_VMID0_SIZE_BASE_IDX 0
+#define mmGDS_VMID1_BASE 0x1302
+#define mmGDS_VMID1_BASE_BASE_IDX 0
+#define mmGDS_VMID1_SIZE 0x1303
+#define mmGDS_VMID1_SIZE_BASE_IDX 0
+#define mmGDS_VMID2_BASE 0x1304
+#define mmGDS_VMID2_BASE_BASE_IDX 0
+#define mmGDS_VMID2_SIZE 0x1305
+#define mmGDS_VMID2_SIZE_BASE_IDX 0
+#define mmGDS_VMID3_BASE 0x1306
+#define mmGDS_VMID3_BASE_BASE_IDX 0
+#define mmGDS_VMID3_SIZE 0x1307
+#define mmGDS_VMID3_SIZE_BASE_IDX 0
+#define mmGDS_VMID4_BASE 0x1308
+#define mmGDS_VMID4_BASE_BASE_IDX 0
+#define mmGDS_VMID4_SIZE 0x1309
+#define mmGDS_VMID4_SIZE_BASE_IDX 0
+#define mmGDS_VMID5_BASE 0x130a
+#define mmGDS_VMID5_BASE_BASE_IDX 0
+#define mmGDS_VMID5_SIZE 0x130b
+#define mmGDS_VMID5_SIZE_BASE_IDX 0
+#define mmGDS_VMID6_BASE 0x130c
+#define mmGDS_VMID6_BASE_BASE_IDX 0
+#define mmGDS_VMID6_SIZE 0x130d
+#define mmGDS_VMID6_SIZE_BASE_IDX 0
+#define mmGDS_VMID7_BASE 0x130e
+#define mmGDS_VMID7_BASE_BASE_IDX 0
+#define mmGDS_VMID7_SIZE 0x130f
+#define mmGDS_VMID7_SIZE_BASE_IDX 0
+#define mmGDS_VMID8_BASE 0x1310
+#define mmGDS_VMID8_BASE_BASE_IDX 0
+#define mmGDS_VMID8_SIZE 0x1311
+#define mmGDS_VMID8_SIZE_BASE_IDX 0
+#define mmGDS_VMID9_BASE 0x1312
+#define mmGDS_VMID9_BASE_BASE_IDX 0
+#define mmGDS_VMID9_SIZE 0x1313
+#define mmGDS_VMID9_SIZE_BASE_IDX 0
+#define mmGDS_VMID10_BASE 0x1314
+#define mmGDS_VMID10_BASE_BASE_IDX 0
+#define mmGDS_VMID10_SIZE 0x1315
+#define mmGDS_VMID10_SIZE_BASE_IDX 0
+#define mmGDS_VMID11_BASE 0x1316
+#define mmGDS_VMID11_BASE_BASE_IDX 0
+#define mmGDS_VMID11_SIZE 0x1317
+#define mmGDS_VMID11_SIZE_BASE_IDX 0
+#define mmGDS_VMID12_BASE 0x1318
+#define mmGDS_VMID12_BASE_BASE_IDX 0
+#define mmGDS_VMID12_SIZE 0x1319
+#define mmGDS_VMID12_SIZE_BASE_IDX 0
+#define mmGDS_VMID13_BASE 0x131a
+#define mmGDS_VMID13_BASE_BASE_IDX 0
+#define mmGDS_VMID13_SIZE 0x131b
+#define mmGDS_VMID13_SIZE_BASE_IDX 0
+#define mmGDS_VMID14_BASE 0x131c
+#define mmGDS_VMID14_BASE_BASE_IDX 0
+#define mmGDS_VMID14_SIZE 0x131d
+#define mmGDS_VMID14_SIZE_BASE_IDX 0
+#define mmGDS_VMID15_BASE 0x131e
+#define mmGDS_VMID15_BASE_BASE_IDX 0
+#define mmGDS_VMID15_SIZE 0x131f
+#define mmGDS_VMID15_SIZE_BASE_IDX 0
+#define mmGDS_GWS_VMID0 0x1320
+#define mmGDS_GWS_VMID0_BASE_IDX 0
+#define mmGDS_GWS_VMID1 0x1321
+#define mmGDS_GWS_VMID1_BASE_IDX 0
+#define mmGDS_GWS_VMID2 0x1322
+#define mmGDS_GWS_VMID2_BASE_IDX 0
+#define mmGDS_GWS_VMID3 0x1323
+#define mmGDS_GWS_VMID3_BASE_IDX 0
+#define mmGDS_GWS_VMID4 0x1324
+#define mmGDS_GWS_VMID4_BASE_IDX 0
+#define mmGDS_GWS_VMID5 0x1325
+#define mmGDS_GWS_VMID5_BASE_IDX 0
+#define mmGDS_GWS_VMID6 0x1326
+#define mmGDS_GWS_VMID6_BASE_IDX 0
+#define mmGDS_GWS_VMID7 0x1327
+#define mmGDS_GWS_VMID7_BASE_IDX 0
+#define mmGDS_GWS_VMID8 0x1328
+#define mmGDS_GWS_VMID8_BASE_IDX 0
+#define mmGDS_GWS_VMID9 0x1329
+#define mmGDS_GWS_VMID9_BASE_IDX 0
+#define mmGDS_GWS_VMID10 0x132a
+#define mmGDS_GWS_VMID10_BASE_IDX 0
+#define mmGDS_GWS_VMID11 0x132b
+#define mmGDS_GWS_VMID11_BASE_IDX 0
+#define mmGDS_GWS_VMID12 0x132c
+#define mmGDS_GWS_VMID12_BASE_IDX 0
+#define mmGDS_GWS_VMID13 0x132d
+#define mmGDS_GWS_VMID13_BASE_IDX 0
+#define mmGDS_GWS_VMID14 0x132e
+#define mmGDS_GWS_VMID14_BASE_IDX 0
+#define mmGDS_GWS_VMID15 0x132f
+#define mmGDS_GWS_VMID15_BASE_IDX 0
+#define mmGDS_OA_VMID0 0x1330
+#define mmGDS_OA_VMID0_BASE_IDX 0
+#define mmGDS_OA_VMID1 0x1331
+#define mmGDS_OA_VMID1_BASE_IDX 0
+#define mmGDS_OA_VMID2 0x1332
+#define mmGDS_OA_VMID2_BASE_IDX 0
+#define mmGDS_OA_VMID3 0x1333
+#define mmGDS_OA_VMID3_BASE_IDX 0
+#define mmGDS_OA_VMID4 0x1334
+#define mmGDS_OA_VMID4_BASE_IDX 0
+#define mmGDS_OA_VMID5 0x1335
+#define mmGDS_OA_VMID5_BASE_IDX 0
+#define mmGDS_OA_VMID6 0x1336
+#define mmGDS_OA_VMID6_BASE_IDX 0
+#define mmGDS_OA_VMID7 0x1337
+#define mmGDS_OA_VMID7_BASE_IDX 0
+#define mmGDS_OA_VMID8 0x1338
+#define mmGDS_OA_VMID8_BASE_IDX 0
+#define mmGDS_OA_VMID9 0x1339
+#define mmGDS_OA_VMID9_BASE_IDX 0
+#define mmGDS_OA_VMID10 0x133a
+#define mmGDS_OA_VMID10_BASE_IDX 0
+#define mmGDS_OA_VMID11 0x133b
+#define mmGDS_OA_VMID11_BASE_IDX 0
+#define mmGDS_OA_VMID12 0x133c
+#define mmGDS_OA_VMID12_BASE_IDX 0
+#define mmGDS_OA_VMID13 0x133d
+#define mmGDS_OA_VMID13_BASE_IDX 0
+#define mmGDS_OA_VMID14 0x133e
+#define mmGDS_OA_VMID14_BASE_IDX 0
+#define mmGDS_OA_VMID15 0x133f
+#define mmGDS_OA_VMID15_BASE_IDX 0
+#define mmGDS_GWS_RESET0 0x1344
+#define mmGDS_GWS_RESET0_BASE_IDX 0
+#define mmGDS_GWS_RESET1 0x1345
+#define mmGDS_GWS_RESET1_BASE_IDX 0
+#define mmGDS_GWS_RESOURCE_RESET 0x1346
+#define mmGDS_GWS_RESOURCE_RESET_BASE_IDX 0
+#define mmGDS_COMPUTE_MAX_WAVE_ID 0x1348
+#define mmGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 0
+#define mmGDS_OA_RESET_MASK 0x1349
+#define mmGDS_OA_RESET_MASK_BASE_IDX 0
+#define mmGDS_OA_RESET 0x134a
+#define mmGDS_OA_RESET_BASE_IDX 0
+#define mmGDS_ENHANCE 0x134b
+#define mmGDS_ENHANCE_BASE_IDX 0
+#define mmGDS_OA_CGPG_RESTORE 0x134c
+#define mmGDS_OA_CGPG_RESTORE_BASE_IDX 0
+#define mmGDS_CS_CTXSW_STATUS 0x134d
+#define mmGDS_CS_CTXSW_STATUS_BASE_IDX 0
+#define mmGDS_CS_CTXSW_CNT0 0x134e
+#define mmGDS_CS_CTXSW_CNT0_BASE_IDX 0
+#define mmGDS_CS_CTXSW_CNT1 0x134f
+#define mmGDS_CS_CTXSW_CNT1_BASE_IDX 0
+#define mmGDS_CS_CTXSW_CNT2 0x1350
+#define mmGDS_CS_CTXSW_CNT2_BASE_IDX 0
+#define mmGDS_CS_CTXSW_CNT3 0x1351
+#define mmGDS_CS_CTXSW_CNT3_BASE_IDX 0
+#define mmGDS_GFX_CTXSW_STATUS 0x1352
+#define mmGDS_GFX_CTXSW_STATUS_BASE_IDX 0
+#define mmGDS_VS_CTXSW_CNT0 0x1353
+#define mmGDS_VS_CTXSW_CNT0_BASE_IDX 0
+#define mmGDS_VS_CTXSW_CNT1 0x1354
+#define mmGDS_VS_CTXSW_CNT1_BASE_IDX 0
+#define mmGDS_VS_CTXSW_CNT2 0x1355
+#define mmGDS_VS_CTXSW_CNT2_BASE_IDX 0
+#define mmGDS_VS_CTXSW_CNT3 0x1356
+#define mmGDS_VS_CTXSW_CNT3_BASE_IDX 0
+#define mmGDS_PS0_CTXSW_CNT0 0x1357
+#define mmGDS_PS0_CTXSW_CNT0_BASE_IDX 0
+#define mmGDS_PS0_CTXSW_CNT1 0x1358
+#define mmGDS_PS0_CTXSW_CNT1_BASE_IDX 0
+#define mmGDS_PS0_CTXSW_CNT2 0x1359
+#define mmGDS_PS0_CTXSW_CNT2_BASE_IDX 0
+#define mmGDS_PS0_CTXSW_CNT3 0x135a
+#define mmGDS_PS0_CTXSW_CNT3_BASE_IDX 0
+#define mmGDS_PS1_CTXSW_CNT0 0x135b
+#define mmGDS_PS1_CTXSW_CNT0_BASE_IDX 0
+#define mmGDS_PS1_CTXSW_CNT1 0x135c
+#define mmGDS_PS1_CTXSW_CNT1_BASE_IDX 0
+#define mmGDS_PS1_CTXSW_CNT2 0x135d
+#define mmGDS_PS1_CTXSW_CNT2_BASE_IDX 0
+#define mmGDS_PS1_CTXSW_CNT3 0x135e
+#define mmGDS_PS1_CTXSW_CNT3_BASE_IDX 0
+#define mmGDS_PS2_CTXSW_CNT0 0x135f
+#define mmGDS_PS2_CTXSW_CNT0_BASE_IDX 0
+#define mmGDS_PS2_CTXSW_CNT1 0x1360
+#define mmGDS_PS2_CTXSW_CNT1_BASE_IDX 0
+#define mmGDS_PS2_CTXSW_CNT2 0x1361
+#define mmGDS_PS2_CTXSW_CNT2_BASE_IDX 0
+#define mmGDS_PS2_CTXSW_CNT3 0x1362
+#define mmGDS_PS2_CTXSW_CNT3_BASE_IDX 0
+#define mmGDS_PS3_CTXSW_CNT0 0x1363
+#define mmGDS_PS3_CTXSW_CNT0_BASE_IDX 0
+#define mmGDS_PS3_CTXSW_CNT1 0x1364
+#define mmGDS_PS3_CTXSW_CNT1_BASE_IDX 0
+#define mmGDS_PS3_CTXSW_CNT2 0x1365
+#define mmGDS_PS3_CTXSW_CNT2_BASE_IDX 0
+#define mmGDS_PS3_CTXSW_CNT3 0x1366
+#define mmGDS_PS3_CTXSW_CNT3_BASE_IDX 0
+#define mmGDS_PS4_CTXSW_CNT0 0x1367
+#define mmGDS_PS4_CTXSW_CNT0_BASE_IDX 0
+#define mmGDS_PS4_CTXSW_CNT1 0x1368
+#define mmGDS_PS4_CTXSW_CNT1_BASE_IDX 0
+#define mmGDS_PS4_CTXSW_CNT2 0x1369
+#define mmGDS_PS4_CTXSW_CNT2_BASE_IDX 0
+#define mmGDS_PS4_CTXSW_CNT3 0x136a
+#define mmGDS_PS4_CTXSW_CNT3_BASE_IDX 0
+#define mmGDS_PS5_CTXSW_CNT0 0x136b
+#define mmGDS_PS5_CTXSW_CNT0_BASE_IDX 0
+#define mmGDS_PS5_CTXSW_CNT1 0x136c
+#define mmGDS_PS5_CTXSW_CNT1_BASE_IDX 0
+#define mmGDS_PS5_CTXSW_CNT2 0x136d
+#define mmGDS_PS5_CTXSW_CNT2_BASE_IDX 0
+#define mmGDS_PS5_CTXSW_CNT3 0x136e
+#define mmGDS_PS5_CTXSW_CNT3_BASE_IDX 0
+#define mmGDS_PS6_CTXSW_CNT0 0x136f
+#define mmGDS_PS6_CTXSW_CNT0_BASE_IDX 0
+#define mmGDS_PS6_CTXSW_CNT1 0x1370
+#define mmGDS_PS6_CTXSW_CNT1_BASE_IDX 0
+#define mmGDS_PS6_CTXSW_CNT2 0x1371
+#define mmGDS_PS6_CTXSW_CNT2_BASE_IDX 0
+#define mmGDS_PS6_CTXSW_CNT3 0x1372
+#define mmGDS_PS6_CTXSW_CNT3_BASE_IDX 0
+#define mmGDS_PS7_CTXSW_CNT0 0x1373
+#define mmGDS_PS7_CTXSW_CNT0_BASE_IDX 0
+#define mmGDS_PS7_CTXSW_CNT1 0x1374
+#define mmGDS_PS7_CTXSW_CNT1_BASE_IDX 0
+#define mmGDS_PS7_CTXSW_CNT2 0x1375
+#define mmGDS_PS7_CTXSW_CNT2_BASE_IDX 0
+#define mmGDS_PS7_CTXSW_CNT3 0x1376
+#define mmGDS_PS7_CTXSW_CNT3_BASE_IDX 0
+#define mmGDS_GS_CTXSW_CNT0 0x1377
+#define mmGDS_GS_CTXSW_CNT0_BASE_IDX 0
+#define mmGDS_GS_CTXSW_CNT1 0x1378
+#define mmGDS_GS_CTXSW_CNT1_BASE_IDX 0
+#define mmGDS_GS_CTXSW_CNT2 0x1379
+#define mmGDS_GS_CTXSW_CNT2_BASE_IDX 0
+#define mmGDS_GS_CTXSW_CNT3 0x137a
+#define mmGDS_GS_CTXSW_CNT3_BASE_IDX 0
+
+
+// addressBlock: gc_rasdec
+// base address: 0xce00
+#define mmRAS_SIGNATURE_CONTROL 0x1380
+#define mmRAS_SIGNATURE_CONTROL_BASE_IDX 0
+#define mmRAS_SIGNATURE_MASK 0x1381
+#define mmRAS_SIGNATURE_MASK_BASE_IDX 0
+#define mmRAS_SX_SIGNATURE0 0x1382
+#define mmRAS_SX_SIGNATURE0_BASE_IDX 0
+#define mmRAS_SX_SIGNATURE1 0x1383
+#define mmRAS_SX_SIGNATURE1_BASE_IDX 0
+#define mmRAS_SX_SIGNATURE2 0x1384
+#define mmRAS_SX_SIGNATURE2_BASE_IDX 0
+#define mmRAS_SX_SIGNATURE3 0x1385
+#define mmRAS_SX_SIGNATURE3_BASE_IDX 0
+#define mmRAS_DB_SIGNATURE0 0x138b
+#define mmRAS_DB_SIGNATURE0_BASE_IDX 0
+#define mmRAS_PA_SIGNATURE0 0x138c
+#define mmRAS_PA_SIGNATURE0_BASE_IDX 0
+#define mmRAS_VGT_SIGNATURE0 0x138d
+#define mmRAS_VGT_SIGNATURE0_BASE_IDX 0
+#define mmRAS_SQ_SIGNATURE0 0x138e
+#define mmRAS_SQ_SIGNATURE0_BASE_IDX 0
+#define mmRAS_SC_SIGNATURE0 0x138f
+#define mmRAS_SC_SIGNATURE0_BASE_IDX 0
+#define mmRAS_SC_SIGNATURE1 0x1390
+#define mmRAS_SC_SIGNATURE1_BASE_IDX 0
+#define mmRAS_SC_SIGNATURE2 0x1391
+#define mmRAS_SC_SIGNATURE2_BASE_IDX 0
+#define mmRAS_SC_SIGNATURE3 0x1392
+#define mmRAS_SC_SIGNATURE3_BASE_IDX 0
+#define mmRAS_SC_SIGNATURE4 0x1393
+#define mmRAS_SC_SIGNATURE4_BASE_IDX 0
+#define mmRAS_SC_SIGNATURE5 0x1394
+#define mmRAS_SC_SIGNATURE5_BASE_IDX 0
+#define mmRAS_SC_SIGNATURE6 0x1395
+#define mmRAS_SC_SIGNATURE6_BASE_IDX 0
+#define mmRAS_SC_SIGNATURE7 0x1396
+#define mmRAS_SC_SIGNATURE7_BASE_IDX 0
+#define mmRAS_IA_SIGNATURE0 0x1397
+#define mmRAS_IA_SIGNATURE0_BASE_IDX 0
+#define mmRAS_IA_SIGNATURE1 0x1398
+#define mmRAS_IA_SIGNATURE1_BASE_IDX 0
+#define mmRAS_SPI_SIGNATURE0 0x1399
+#define mmRAS_SPI_SIGNATURE0_BASE_IDX 0
+#define mmRAS_SPI_SIGNATURE1 0x139a
+#define mmRAS_SPI_SIGNATURE1_BASE_IDX 0
+#define mmRAS_TA_SIGNATURE0 0x139b
+#define mmRAS_TA_SIGNATURE0_BASE_IDX 0
+#define mmRAS_TD_SIGNATURE0 0x139c
+#define mmRAS_TD_SIGNATURE0_BASE_IDX 0
+#define mmRAS_CB_SIGNATURE0 0x139d
+#define mmRAS_CB_SIGNATURE0_BASE_IDX 0
+#define mmRAS_BCI_SIGNATURE0 0x139e
+#define mmRAS_BCI_SIGNATURE0_BASE_IDX 0
+#define mmRAS_BCI_SIGNATURE1 0x139f
+#define mmRAS_BCI_SIGNATURE1_BASE_IDX 0
+#define mmRAS_TA_SIGNATURE1 0x13a0
+#define mmRAS_TA_SIGNATURE1_BASE_IDX 0
+
+
+// addressBlock: gc_gfxdec0
+// base address: 0x28000
+#define mmDB_RENDER_CONTROL 0x0000
+#define mmDB_RENDER_CONTROL_BASE_IDX 1
+#define mmDB_COUNT_CONTROL 0x0001
+#define mmDB_COUNT_CONTROL_BASE_IDX 1
+#define mmDB_DEPTH_VIEW 0x0002
+#define mmDB_DEPTH_VIEW_BASE_IDX 1
+#define mmDB_RENDER_OVERRIDE 0x0003
+#define mmDB_RENDER_OVERRIDE_BASE_IDX 1
+#define mmDB_RENDER_OVERRIDE2 0x0004
+#define mmDB_RENDER_OVERRIDE2_BASE_IDX 1
+#define mmDB_HTILE_DATA_BASE 0x0005
+#define mmDB_HTILE_DATA_BASE_BASE_IDX 1
+#define mmDB_HTILE_DATA_BASE_HI 0x0006
+#define mmDB_HTILE_DATA_BASE_HI_BASE_IDX 1
+#define mmDB_DEPTH_SIZE 0x0007
+#define mmDB_DEPTH_SIZE_BASE_IDX 1
+#define mmDB_DEPTH_BOUNDS_MIN 0x0008
+#define mmDB_DEPTH_BOUNDS_MIN_BASE_IDX 1
+#define mmDB_DEPTH_BOUNDS_MAX 0x0009
+#define mmDB_DEPTH_BOUNDS_MAX_BASE_IDX 1
+#define mmDB_STENCIL_CLEAR 0x000a
+#define mmDB_STENCIL_CLEAR_BASE_IDX 1
+#define mmDB_DEPTH_CLEAR 0x000b
+#define mmDB_DEPTH_CLEAR_BASE_IDX 1
+#define mmPA_SC_SCREEN_SCISSOR_TL 0x000c
+#define mmPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1
+#define mmPA_SC_SCREEN_SCISSOR_BR 0x000d
+#define mmPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1
+#define mmDB_Z_INFO 0x000e
+#define mmDB_Z_INFO_BASE_IDX 1
+#define mmDB_STENCIL_INFO 0x000f
+#define mmDB_STENCIL_INFO_BASE_IDX 1
+#define mmDB_Z_READ_BASE 0x0010
+#define mmDB_Z_READ_BASE_BASE_IDX 1
+#define mmDB_Z_READ_BASE_HI 0x0011
+#define mmDB_Z_READ_BASE_HI_BASE_IDX 1
+#define mmDB_STENCIL_READ_BASE 0x0012
+#define mmDB_STENCIL_READ_BASE_BASE_IDX 1
+#define mmDB_STENCIL_READ_BASE_HI 0x0013
+#define mmDB_STENCIL_READ_BASE_HI_BASE_IDX 1
+#define mmDB_Z_WRITE_BASE 0x0014
+#define mmDB_Z_WRITE_BASE_BASE_IDX 1
+#define mmDB_Z_WRITE_BASE_HI 0x0015
+#define mmDB_Z_WRITE_BASE_HI_BASE_IDX 1
+#define mmDB_STENCIL_WRITE_BASE 0x0016
+#define mmDB_STENCIL_WRITE_BASE_BASE_IDX 1
+#define mmDB_STENCIL_WRITE_BASE_HI 0x0017
+#define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1
+#define mmDB_DFSM_CONTROL 0x0018
+#define mmDB_DFSM_CONTROL_BASE_IDX 1
+#define mmDB_RENDER_FILTER 0x0019
+#define mmDB_RENDER_FILTER_BASE_IDX 1
+#define mmDB_Z_INFO2 0x001a
+#define mmDB_Z_INFO2_BASE_IDX 1
+#define mmDB_STENCIL_INFO2 0x001b
+#define mmDB_STENCIL_INFO2_BASE_IDX 1
+#define mmTA_BC_BASE_ADDR 0x0020
+#define mmTA_BC_BASE_ADDR_BASE_IDX 1
+#define mmTA_BC_BASE_ADDR_HI 0x0021
+#define mmTA_BC_BASE_ADDR_HI_BASE_IDX 1
+#define mmCOHER_DEST_BASE_HI_0 0x007a
+#define mmCOHER_DEST_BASE_HI_0_BASE_IDX 1
+#define mmCOHER_DEST_BASE_HI_1 0x007b
+#define mmCOHER_DEST_BASE_HI_1_BASE_IDX 1
+#define mmCOHER_DEST_BASE_HI_2 0x007c
+#define mmCOHER_DEST_BASE_HI_2_BASE_IDX 1
+#define mmCOHER_DEST_BASE_HI_3 0x007d
+#define mmCOHER_DEST_BASE_HI_3_BASE_IDX 1
+#define mmCOHER_DEST_BASE_2 0x007e
+#define mmCOHER_DEST_BASE_2_BASE_IDX 1
+#define mmCOHER_DEST_BASE_3 0x007f
+#define mmCOHER_DEST_BASE_3_BASE_IDX 1
+#define mmPA_SC_WINDOW_OFFSET 0x0080
+#define mmPA_SC_WINDOW_OFFSET_BASE_IDX 1
+#define mmPA_SC_WINDOW_SCISSOR_TL 0x0081
+#define mmPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1
+#define mmPA_SC_WINDOW_SCISSOR_BR 0x0082
+#define mmPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1
+#define mmPA_SC_CLIPRECT_RULE 0x0083
+#define mmPA_SC_CLIPRECT_RULE_BASE_IDX 1
+#define mmPA_SC_CLIPRECT_0_TL 0x0084
+#define mmPA_SC_CLIPRECT_0_TL_BASE_IDX 1
+#define mmPA_SC_CLIPRECT_0_BR 0x0085
+#define mmPA_SC_CLIPRECT_0_BR_BASE_IDX 1
+#define mmPA_SC_CLIPRECT_1_TL 0x0086
+#define mmPA_SC_CLIPRECT_1_TL_BASE_IDX 1
+#define mmPA_SC_CLIPRECT_1_BR 0x0087
+#define mmPA_SC_CLIPRECT_1_BR_BASE_IDX 1
+#define mmPA_SC_CLIPRECT_2_TL 0x0088
+#define mmPA_SC_CLIPRECT_2_TL_BASE_IDX 1
+#define mmPA_SC_CLIPRECT_2_BR 0x0089
+#define mmPA_SC_CLIPRECT_2_BR_BASE_IDX 1
+#define mmPA_SC_CLIPRECT_3_TL 0x008a
+#define mmPA_SC_CLIPRECT_3_TL_BASE_IDX 1
+#define mmPA_SC_CLIPRECT_3_BR 0x008b
+#define mmPA_SC_CLIPRECT_3_BR_BASE_IDX 1
+#define mmPA_SC_EDGERULE 0x008c
+#define mmPA_SC_EDGERULE_BASE_IDX 1
+#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0x008d
+#define mmPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1
+#define mmCB_TARGET_MASK 0x008e
+#define mmCB_TARGET_MASK_BASE_IDX 1
+#define mmCB_SHADER_MASK 0x008f
+#define mmCB_SHADER_MASK_BASE_IDX 1
+#define mmPA_SC_GENERIC_SCISSOR_TL 0x0090
+#define mmPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1
+#define mmPA_SC_GENERIC_SCISSOR_BR 0x0091
+#define mmPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1
+#define mmCOHER_DEST_BASE_0 0x0092
+#define mmCOHER_DEST_BASE_0_BASE_IDX 1
+#define mmCOHER_DEST_BASE_1 0x0093
+#define mmCOHER_DEST_BASE_1_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_0_TL 0x0094
+#define mmPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_0_BR 0x0095
+#define mmPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_1_TL 0x0096
+#define mmPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_1_BR 0x0097
+#define mmPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_2_TL 0x0098
+#define mmPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_2_BR 0x0099
+#define mmPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_3_TL 0x009a
+#define mmPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_3_BR 0x009b
+#define mmPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_4_TL 0x009c
+#define mmPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_4_BR 0x009d
+#define mmPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_5_TL 0x009e
+#define mmPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_5_BR 0x009f
+#define mmPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_6_TL 0x00a0
+#define mmPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_6_BR 0x00a1
+#define mmPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_7_TL 0x00a2
+#define mmPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_7_BR 0x00a3
+#define mmPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_8_TL 0x00a4
+#define mmPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_8_BR 0x00a5
+#define mmPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_9_TL 0x00a6
+#define mmPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_9_BR 0x00a7
+#define mmPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_10_TL 0x00a8
+#define mmPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_10_BR 0x00a9
+#define mmPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_11_TL 0x00aa
+#define mmPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_11_BR 0x00ab
+#define mmPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_12_TL 0x00ac
+#define mmPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_12_BR 0x00ad
+#define mmPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_13_TL 0x00ae
+#define mmPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_13_BR 0x00af
+#define mmPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_14_TL 0x00b0
+#define mmPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_14_BR 0x00b1
+#define mmPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_15_TL 0x00b2
+#define mmPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_15_BR 0x00b3
+#define mmPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_0 0x00b4
+#define mmPA_SC_VPORT_ZMIN_0_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_0 0x00b5
+#define mmPA_SC_VPORT_ZMAX_0_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_1 0x00b6
+#define mmPA_SC_VPORT_ZMIN_1_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_1 0x00b7
+#define mmPA_SC_VPORT_ZMAX_1_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_2 0x00b8
+#define mmPA_SC_VPORT_ZMIN_2_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_2 0x00b9
+#define mmPA_SC_VPORT_ZMAX_2_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_3 0x00ba
+#define mmPA_SC_VPORT_ZMIN_3_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_3 0x00bb
+#define mmPA_SC_VPORT_ZMAX_3_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_4 0x00bc
+#define mmPA_SC_VPORT_ZMIN_4_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_4 0x00bd
+#define mmPA_SC_VPORT_ZMAX_4_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_5 0x00be
+#define mmPA_SC_VPORT_ZMIN_5_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_5 0x00bf
+#define mmPA_SC_VPORT_ZMAX_5_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_6 0x00c0
+#define mmPA_SC_VPORT_ZMIN_6_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_6 0x00c1
+#define mmPA_SC_VPORT_ZMAX_6_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_7 0x00c2
+#define mmPA_SC_VPORT_ZMIN_7_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_7 0x00c3
+#define mmPA_SC_VPORT_ZMAX_7_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_8 0x00c4
+#define mmPA_SC_VPORT_ZMIN_8_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_8 0x00c5
+#define mmPA_SC_VPORT_ZMAX_8_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_9 0x00c6
+#define mmPA_SC_VPORT_ZMIN_9_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_9 0x00c7
+#define mmPA_SC_VPORT_ZMAX_9_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_10 0x00c8
+#define mmPA_SC_VPORT_ZMIN_10_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_10 0x00c9
+#define mmPA_SC_VPORT_ZMAX_10_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_11 0x00ca
+#define mmPA_SC_VPORT_ZMIN_11_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_11 0x00cb
+#define mmPA_SC_VPORT_ZMAX_11_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_12 0x00cc
+#define mmPA_SC_VPORT_ZMIN_12_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_12 0x00cd
+#define mmPA_SC_VPORT_ZMAX_12_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_13 0x00ce
+#define mmPA_SC_VPORT_ZMIN_13_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_13 0x00cf
+#define mmPA_SC_VPORT_ZMAX_13_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_14 0x00d0
+#define mmPA_SC_VPORT_ZMIN_14_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_14 0x00d1
+#define mmPA_SC_VPORT_ZMAX_14_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_15 0x00d2
+#define mmPA_SC_VPORT_ZMIN_15_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_15 0x00d3
+#define mmPA_SC_VPORT_ZMAX_15_BASE_IDX 1
+#define mmPA_SC_RASTER_CONFIG 0x00d4
+#define mmPA_SC_RASTER_CONFIG_BASE_IDX 1
+#define mmPA_SC_RASTER_CONFIG_1 0x00d5
+#define mmPA_SC_RASTER_CONFIG_1_BASE_IDX 1
+#define mmPA_SC_SCREEN_EXTENT_CONTROL 0x00d6
+#define mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1
+#define mmPA_SC_TILE_STEERING_OVERRIDE 0x00d7
+#define mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1
+#define mmCP_PERFMON_CNTX_CNTL 0x00d8
+#define mmCP_PERFMON_CNTX_CNTL_BASE_IDX 1
+#define mmCP_PIPEID 0x00d9
+#define mmCP_PIPEID_BASE_IDX 1
+#define mmCP_RINGID 0x00d9
+#define mmCP_RINGID_BASE_IDX 1
+#define mmCP_VMID 0x00da
+#define mmCP_VMID_BASE_IDX 1
+#define mmPA_SC_RIGHT_VERT_GRID 0x00e8
+#define mmPA_SC_RIGHT_VERT_GRID_BASE_IDX 1
+#define mmPA_SC_LEFT_VERT_GRID 0x00e9
+#define mmPA_SC_LEFT_VERT_GRID_BASE_IDX 1
+#define mmPA_SC_HORIZ_GRID 0x00ea
+#define mmPA_SC_HORIZ_GRID_BASE_IDX 1
+#define mmPA_SC_FOV_WINDOW_LR 0x00eb
+#define mmPA_SC_FOV_WINDOW_LR_BASE_IDX 1
+#define mmPA_SC_FOV_WINDOW_TB 0x00ec
+#define mmPA_SC_FOV_WINDOW_TB_BASE_IDX 1
+#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x0103
+#define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1
+#define mmCB_BLEND_RED 0x0105
+#define mmCB_BLEND_RED_BASE_IDX 1
+#define mmCB_BLEND_GREEN 0x0106
+#define mmCB_BLEND_GREEN_BASE_IDX 1
+#define mmCB_BLEND_BLUE 0x0107
+#define mmCB_BLEND_BLUE_BASE_IDX 1
+#define mmCB_BLEND_ALPHA 0x0108
+#define mmCB_BLEND_ALPHA_BASE_IDX 1
+#define mmCB_DCC_CONTROL 0x0109
+#define mmCB_DCC_CONTROL_BASE_IDX 1
+#define mmDB_STENCIL_CONTROL 0x010b
+#define mmDB_STENCIL_CONTROL_BASE_IDX 1
+#define mmDB_STENCILREFMASK 0x010c
+#define mmDB_STENCILREFMASK_BASE_IDX 1
+#define mmDB_STENCILREFMASK_BF 0x010d
+#define mmDB_STENCILREFMASK_BF_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE 0x010f
+#define mmPA_CL_VPORT_XSCALE_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET 0x0110
+#define mmPA_CL_VPORT_XOFFSET_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE 0x0111
+#define mmPA_CL_VPORT_YSCALE_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET 0x0112
+#define mmPA_CL_VPORT_YOFFSET_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE 0x0113
+#define mmPA_CL_VPORT_ZSCALE_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET 0x0114
+#define mmPA_CL_VPORT_ZOFFSET_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_1 0x0115
+#define mmPA_CL_VPORT_XSCALE_1_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_1 0x0116
+#define mmPA_CL_VPORT_XOFFSET_1_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_1 0x0117
+#define mmPA_CL_VPORT_YSCALE_1_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_1 0x0118
+#define mmPA_CL_VPORT_YOFFSET_1_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_1 0x0119
+#define mmPA_CL_VPORT_ZSCALE_1_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_1 0x011a
+#define mmPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_2 0x011b
+#define mmPA_CL_VPORT_XSCALE_2_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_2 0x011c
+#define mmPA_CL_VPORT_XOFFSET_2_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_2 0x011d
+#define mmPA_CL_VPORT_YSCALE_2_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_2 0x011e
+#define mmPA_CL_VPORT_YOFFSET_2_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_2 0x011f
+#define mmPA_CL_VPORT_ZSCALE_2_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_2 0x0120
+#define mmPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_3 0x0121
+#define mmPA_CL_VPORT_XSCALE_3_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_3 0x0122
+#define mmPA_CL_VPORT_XOFFSET_3_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_3 0x0123
+#define mmPA_CL_VPORT_YSCALE_3_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_3 0x0124
+#define mmPA_CL_VPORT_YOFFSET_3_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_3 0x0125
+#define mmPA_CL_VPORT_ZSCALE_3_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_3 0x0126
+#define mmPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_4 0x0127
+#define mmPA_CL_VPORT_XSCALE_4_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_4 0x0128
+#define mmPA_CL_VPORT_XOFFSET_4_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_4 0x0129
+#define mmPA_CL_VPORT_YSCALE_4_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_4 0x012a
+#define mmPA_CL_VPORT_YOFFSET_4_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_4 0x012b
+#define mmPA_CL_VPORT_ZSCALE_4_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_4 0x012c
+#define mmPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_5 0x012d
+#define mmPA_CL_VPORT_XSCALE_5_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_5 0x012e
+#define mmPA_CL_VPORT_XOFFSET_5_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_5 0x012f
+#define mmPA_CL_VPORT_YSCALE_5_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_5 0x0130
+#define mmPA_CL_VPORT_YOFFSET_5_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_5 0x0131
+#define mmPA_CL_VPORT_ZSCALE_5_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_5 0x0132
+#define mmPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_6 0x0133
+#define mmPA_CL_VPORT_XSCALE_6_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_6 0x0134
+#define mmPA_CL_VPORT_XOFFSET_6_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_6 0x0135
+#define mmPA_CL_VPORT_YSCALE_6_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_6 0x0136
+#define mmPA_CL_VPORT_YOFFSET_6_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_6 0x0137
+#define mmPA_CL_VPORT_ZSCALE_6_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_6 0x0138
+#define mmPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_7 0x0139
+#define mmPA_CL_VPORT_XSCALE_7_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_7 0x013a
+#define mmPA_CL_VPORT_XOFFSET_7_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_7 0x013b
+#define mmPA_CL_VPORT_YSCALE_7_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_7 0x013c
+#define mmPA_CL_VPORT_YOFFSET_7_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_7 0x013d
+#define mmPA_CL_VPORT_ZSCALE_7_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_7 0x013e
+#define mmPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_8 0x013f
+#define mmPA_CL_VPORT_XSCALE_8_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_8 0x0140
+#define mmPA_CL_VPORT_XOFFSET_8_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_8 0x0141
+#define mmPA_CL_VPORT_YSCALE_8_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_8 0x0142
+#define mmPA_CL_VPORT_YOFFSET_8_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_8 0x0143
+#define mmPA_CL_VPORT_ZSCALE_8_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_8 0x0144
+#define mmPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_9 0x0145
+#define mmPA_CL_VPORT_XSCALE_9_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_9 0x0146
+#define mmPA_CL_VPORT_XOFFSET_9_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_9 0x0147
+#define mmPA_CL_VPORT_YSCALE_9_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_9 0x0148
+#define mmPA_CL_VPORT_YOFFSET_9_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_9 0x0149
+#define mmPA_CL_VPORT_ZSCALE_9_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_9 0x014a
+#define mmPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_10 0x014b
+#define mmPA_CL_VPORT_XSCALE_10_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_10 0x014c
+#define mmPA_CL_VPORT_XOFFSET_10_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_10 0x014d
+#define mmPA_CL_VPORT_YSCALE_10_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_10 0x014e
+#define mmPA_CL_VPORT_YOFFSET_10_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_10 0x014f
+#define mmPA_CL_VPORT_ZSCALE_10_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_10 0x0150
+#define mmPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_11 0x0151
+#define mmPA_CL_VPORT_XSCALE_11_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_11 0x0152
+#define mmPA_CL_VPORT_XOFFSET_11_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_11 0x0153
+#define mmPA_CL_VPORT_YSCALE_11_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_11 0x0154
+#define mmPA_CL_VPORT_YOFFSET_11_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_11 0x0155
+#define mmPA_CL_VPORT_ZSCALE_11_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_11 0x0156
+#define mmPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_12 0x0157
+#define mmPA_CL_VPORT_XSCALE_12_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_12 0x0158
+#define mmPA_CL_VPORT_XOFFSET_12_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_12 0x0159
+#define mmPA_CL_VPORT_YSCALE_12_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_12 0x015a
+#define mmPA_CL_VPORT_YOFFSET_12_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_12 0x015b
+#define mmPA_CL_VPORT_ZSCALE_12_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_12 0x015c
+#define mmPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_13 0x015d
+#define mmPA_CL_VPORT_XSCALE_13_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_13 0x015e
+#define mmPA_CL_VPORT_XOFFSET_13_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_13 0x015f
+#define mmPA_CL_VPORT_YSCALE_13_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_13 0x0160
+#define mmPA_CL_VPORT_YOFFSET_13_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_13 0x0161
+#define mmPA_CL_VPORT_ZSCALE_13_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_13 0x0162
+#define mmPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_14 0x0163
+#define mmPA_CL_VPORT_XSCALE_14_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_14 0x0164
+#define mmPA_CL_VPORT_XOFFSET_14_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_14 0x0165
+#define mmPA_CL_VPORT_YSCALE_14_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_14 0x0166
+#define mmPA_CL_VPORT_YOFFSET_14_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_14 0x0167
+#define mmPA_CL_VPORT_ZSCALE_14_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_14 0x0168
+#define mmPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_15 0x0169
+#define mmPA_CL_VPORT_XSCALE_15_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_15 0x016a
+#define mmPA_CL_VPORT_XOFFSET_15_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_15 0x016b
+#define mmPA_CL_VPORT_YSCALE_15_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_15 0x016c
+#define mmPA_CL_VPORT_YOFFSET_15_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_15 0x016d
+#define mmPA_CL_VPORT_ZSCALE_15_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_15 0x016e
+#define mmPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1
+#define mmPA_CL_UCP_0_X 0x016f
+#define mmPA_CL_UCP_0_X_BASE_IDX 1
+#define mmPA_CL_UCP_0_Y 0x0170
+#define mmPA_CL_UCP_0_Y_BASE_IDX 1
+#define mmPA_CL_UCP_0_Z 0x0171
+#define mmPA_CL_UCP_0_Z_BASE_IDX 1
+#define mmPA_CL_UCP_0_W 0x0172
+#define mmPA_CL_UCP_0_W_BASE_IDX 1
+#define mmPA_CL_UCP_1_X 0x0173
+#define mmPA_CL_UCP_1_X_BASE_IDX 1
+#define mmPA_CL_UCP_1_Y 0x0174
+#define mmPA_CL_UCP_1_Y_BASE_IDX 1
+#define mmPA_CL_UCP_1_Z 0x0175
+#define mmPA_CL_UCP_1_Z_BASE_IDX 1
+#define mmPA_CL_UCP_1_W 0x0176
+#define mmPA_CL_UCP_1_W_BASE_IDX 1
+#define mmPA_CL_UCP_2_X 0x0177
+#define mmPA_CL_UCP_2_X_BASE_IDX 1
+#define mmPA_CL_UCP_2_Y 0x0178
+#define mmPA_CL_UCP_2_Y_BASE_IDX 1
+#define mmPA_CL_UCP_2_Z 0x0179
+#define mmPA_CL_UCP_2_Z_BASE_IDX 1
+#define mmPA_CL_UCP_2_W 0x017a
+#define mmPA_CL_UCP_2_W_BASE_IDX 1
+#define mmPA_CL_UCP_3_X 0x017b
+#define mmPA_CL_UCP_3_X_BASE_IDX 1
+#define mmPA_CL_UCP_3_Y 0x017c
+#define mmPA_CL_UCP_3_Y_BASE_IDX 1
+#define mmPA_CL_UCP_3_Z 0x017d
+#define mmPA_CL_UCP_3_Z_BASE_IDX 1
+#define mmPA_CL_UCP_3_W 0x017e
+#define mmPA_CL_UCP_3_W_BASE_IDX 1
+#define mmPA_CL_UCP_4_X 0x017f
+#define mmPA_CL_UCP_4_X_BASE_IDX 1
+#define mmPA_CL_UCP_4_Y 0x0180
+#define mmPA_CL_UCP_4_Y_BASE_IDX 1
+#define mmPA_CL_UCP_4_Z 0x0181
+#define mmPA_CL_UCP_4_Z_BASE_IDX 1
+#define mmPA_CL_UCP_4_W 0x0182
+#define mmPA_CL_UCP_4_W_BASE_IDX 1
+#define mmPA_CL_UCP_5_X 0x0183
+#define mmPA_CL_UCP_5_X_BASE_IDX 1
+#define mmPA_CL_UCP_5_Y 0x0184
+#define mmPA_CL_UCP_5_Y_BASE_IDX 1
+#define mmPA_CL_UCP_5_Z 0x0185
+#define mmPA_CL_UCP_5_Z_BASE_IDX 1
+#define mmPA_CL_UCP_5_W 0x0186
+#define mmPA_CL_UCP_5_W_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_0 0x0191
+#define mmSPI_PS_INPUT_CNTL_0_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_1 0x0192
+#define mmSPI_PS_INPUT_CNTL_1_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_2 0x0193
+#define mmSPI_PS_INPUT_CNTL_2_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_3 0x0194
+#define mmSPI_PS_INPUT_CNTL_3_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_4 0x0195
+#define mmSPI_PS_INPUT_CNTL_4_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_5 0x0196
+#define mmSPI_PS_INPUT_CNTL_5_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_6 0x0197
+#define mmSPI_PS_INPUT_CNTL_6_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_7 0x0198
+#define mmSPI_PS_INPUT_CNTL_7_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_8 0x0199
+#define mmSPI_PS_INPUT_CNTL_8_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_9 0x019a
+#define mmSPI_PS_INPUT_CNTL_9_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_10 0x019b
+#define mmSPI_PS_INPUT_CNTL_10_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_11 0x019c
+#define mmSPI_PS_INPUT_CNTL_11_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_12 0x019d
+#define mmSPI_PS_INPUT_CNTL_12_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_13 0x019e
+#define mmSPI_PS_INPUT_CNTL_13_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_14 0x019f
+#define mmSPI_PS_INPUT_CNTL_14_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_15 0x01a0
+#define mmSPI_PS_INPUT_CNTL_15_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_16 0x01a1
+#define mmSPI_PS_INPUT_CNTL_16_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_17 0x01a2
+#define mmSPI_PS_INPUT_CNTL_17_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_18 0x01a3
+#define mmSPI_PS_INPUT_CNTL_18_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_19 0x01a4
+#define mmSPI_PS_INPUT_CNTL_19_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_20 0x01a5
+#define mmSPI_PS_INPUT_CNTL_20_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_21 0x01a6
+#define mmSPI_PS_INPUT_CNTL_21_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_22 0x01a7
+#define mmSPI_PS_INPUT_CNTL_22_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_23 0x01a8
+#define mmSPI_PS_INPUT_CNTL_23_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_24 0x01a9
+#define mmSPI_PS_INPUT_CNTL_24_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_25 0x01aa
+#define mmSPI_PS_INPUT_CNTL_25_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_26 0x01ab
+#define mmSPI_PS_INPUT_CNTL_26_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_27 0x01ac
+#define mmSPI_PS_INPUT_CNTL_27_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_28 0x01ad
+#define mmSPI_PS_INPUT_CNTL_28_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_29 0x01ae
+#define mmSPI_PS_INPUT_CNTL_29_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_30 0x01af
+#define mmSPI_PS_INPUT_CNTL_30_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_31 0x01b0
+#define mmSPI_PS_INPUT_CNTL_31_BASE_IDX 1
+#define mmSPI_VS_OUT_CONFIG 0x01b1
+#define mmSPI_VS_OUT_CONFIG_BASE_IDX 1
+#define mmSPI_PS_INPUT_ENA 0x01b3
+#define mmSPI_PS_INPUT_ENA_BASE_IDX 1
+#define mmSPI_PS_INPUT_ADDR 0x01b4
+#define mmSPI_PS_INPUT_ADDR_BASE_IDX 1
+#define mmSPI_INTERP_CONTROL_0 0x01b5
+#define mmSPI_INTERP_CONTROL_0_BASE_IDX 1
+#define mmSPI_PS_IN_CONTROL 0x01b6
+#define mmSPI_PS_IN_CONTROL_BASE_IDX 1
+#define mmSPI_BARYC_CNTL 0x01b8
+#define mmSPI_BARYC_CNTL_BASE_IDX 1
+#define mmSPI_TMPRING_SIZE 0x01ba
+#define mmSPI_TMPRING_SIZE_BASE_IDX 1
+#define mmSPI_SHADER_POS_FORMAT 0x01c3
+#define mmSPI_SHADER_POS_FORMAT_BASE_IDX 1
+#define mmSPI_SHADER_Z_FORMAT 0x01c4
+#define mmSPI_SHADER_Z_FORMAT_BASE_IDX 1
+#define mmSPI_SHADER_COL_FORMAT 0x01c5
+#define mmSPI_SHADER_COL_FORMAT_BASE_IDX 1
+#define mmSX_PS_DOWNCONVERT 0x01d5
+#define mmSX_PS_DOWNCONVERT_BASE_IDX 1
+#define mmSX_BLEND_OPT_EPSILON 0x01d6
+#define mmSX_BLEND_OPT_EPSILON_BASE_IDX 1
+#define mmSX_BLEND_OPT_CONTROL 0x01d7
+#define mmSX_BLEND_OPT_CONTROL_BASE_IDX 1
+#define mmSX_MRT0_BLEND_OPT 0x01d8
+#define mmSX_MRT0_BLEND_OPT_BASE_IDX 1
+#define mmSX_MRT1_BLEND_OPT 0x01d9
+#define mmSX_MRT1_BLEND_OPT_BASE_IDX 1
+#define mmSX_MRT2_BLEND_OPT 0x01da
+#define mmSX_MRT2_BLEND_OPT_BASE_IDX 1
+#define mmSX_MRT3_BLEND_OPT 0x01db
+#define mmSX_MRT3_BLEND_OPT_BASE_IDX 1
+#define mmSX_MRT4_BLEND_OPT 0x01dc
+#define mmSX_MRT4_BLEND_OPT_BASE_IDX 1
+#define mmSX_MRT5_BLEND_OPT 0x01dd
+#define mmSX_MRT5_BLEND_OPT_BASE_IDX 1
+#define mmSX_MRT6_BLEND_OPT 0x01de
+#define mmSX_MRT6_BLEND_OPT_BASE_IDX 1
+#define mmSX_MRT7_BLEND_OPT 0x01df
+#define mmSX_MRT7_BLEND_OPT_BASE_IDX 1
+#define mmCB_BLEND0_CONTROL 0x01e0
+#define mmCB_BLEND0_CONTROL_BASE_IDX 1
+#define mmCB_BLEND1_CONTROL 0x01e1
+#define mmCB_BLEND1_CONTROL_BASE_IDX 1
+#define mmCB_BLEND2_CONTROL 0x01e2
+#define mmCB_BLEND2_CONTROL_BASE_IDX 1
+#define mmCB_BLEND3_CONTROL 0x01e3
+#define mmCB_BLEND3_CONTROL_BASE_IDX 1
+#define mmCB_BLEND4_CONTROL 0x01e4
+#define mmCB_BLEND4_CONTROL_BASE_IDX 1
+#define mmCB_BLEND5_CONTROL 0x01e5
+#define mmCB_BLEND5_CONTROL_BASE_IDX 1
+#define mmCB_BLEND6_CONTROL 0x01e6
+#define mmCB_BLEND6_CONTROL_BASE_IDX 1
+#define mmCB_BLEND7_CONTROL 0x01e7
+#define mmCB_BLEND7_CONTROL_BASE_IDX 1
+#define mmCB_MRT0_EPITCH 0x01e8
+#define mmCB_MRT0_EPITCH_BASE_IDX 1
+#define mmCB_MRT1_EPITCH 0x01e9
+#define mmCB_MRT1_EPITCH_BASE_IDX 1
+#define mmCB_MRT2_EPITCH 0x01ea
+#define mmCB_MRT2_EPITCH_BASE_IDX 1
+#define mmCB_MRT3_EPITCH 0x01eb
+#define mmCB_MRT3_EPITCH_BASE_IDX 1
+#define mmCB_MRT4_EPITCH 0x01ec
+#define mmCB_MRT4_EPITCH_BASE_IDX 1
+#define mmCB_MRT5_EPITCH 0x01ed
+#define mmCB_MRT5_EPITCH_BASE_IDX 1
+#define mmCB_MRT6_EPITCH 0x01ee
+#define mmCB_MRT6_EPITCH_BASE_IDX 1
+#define mmCB_MRT7_EPITCH 0x01ef
+#define mmCB_MRT7_EPITCH_BASE_IDX 1
+#define mmCS_COPY_STATE 0x01f3
+#define mmCS_COPY_STATE_BASE_IDX 1
+#define mmGFX_COPY_STATE 0x01f4
+#define mmGFX_COPY_STATE_BASE_IDX 1
+#define mmPA_CL_POINT_X_RAD 0x01f5
+#define mmPA_CL_POINT_X_RAD_BASE_IDX 1
+#define mmPA_CL_POINT_Y_RAD 0x01f6
+#define mmPA_CL_POINT_Y_RAD_BASE_IDX 1
+#define mmPA_CL_POINT_SIZE 0x01f7
+#define mmPA_CL_POINT_SIZE_BASE_IDX 1
+#define mmPA_CL_POINT_CULL_RAD 0x01f8
+#define mmPA_CL_POINT_CULL_RAD_BASE_IDX 1
+#define mmVGT_DMA_BASE_HI 0x01f9
+#define mmVGT_DMA_BASE_HI_BASE_IDX 1
+#define mmVGT_DMA_BASE 0x01fa
+#define mmVGT_DMA_BASE_BASE_IDX 1
+#define mmVGT_DRAW_INITIATOR 0x01fc
+#define mmVGT_DRAW_INITIATOR_BASE_IDX 1
+#define mmVGT_IMMED_DATA 0x01fd
+#define mmVGT_IMMED_DATA_BASE_IDX 1
+#define mmVGT_EVENT_ADDRESS_REG 0x01fe
+#define mmVGT_EVENT_ADDRESS_REG_BASE_IDX 1
+#define mmDB_DEPTH_CONTROL 0x0200
+#define mmDB_DEPTH_CONTROL_BASE_IDX 1
+#define mmDB_EQAA 0x0201
+#define mmDB_EQAA_BASE_IDX 1
+#define mmCB_COLOR_CONTROL 0x0202
+#define mmCB_COLOR_CONTROL_BASE_IDX 1
+#define mmDB_SHADER_CONTROL 0x0203
+#define mmDB_SHADER_CONTROL_BASE_IDX 1
+#define mmPA_CL_CLIP_CNTL 0x0204
+#define mmPA_CL_CLIP_CNTL_BASE_IDX 1
+#define mmPA_SU_SC_MODE_CNTL 0x0205
+#define mmPA_SU_SC_MODE_CNTL_BASE_IDX 1
+#define mmPA_CL_VTE_CNTL 0x0206
+#define mmPA_CL_VTE_CNTL_BASE_IDX 1
+#define mmPA_CL_VS_OUT_CNTL 0x0207
+#define mmPA_CL_VS_OUT_CNTL_BASE_IDX 1
+#define mmPA_CL_NANINF_CNTL 0x0208
+#define mmPA_CL_NANINF_CNTL_BASE_IDX 1
+#define mmPA_SU_LINE_STIPPLE_CNTL 0x0209
+#define mmPA_SU_LINE_STIPPLE_CNTL_BASE_IDX 1
+#define mmPA_SU_LINE_STIPPLE_SCALE 0x020a
+#define mmPA_SU_LINE_STIPPLE_SCALE_BASE_IDX 1
+#define mmPA_SU_PRIM_FILTER_CNTL 0x020b
+#define mmPA_SU_PRIM_FILTER_CNTL_BASE_IDX 1
+#define mmPA_SU_SMALL_PRIM_FILTER_CNTL 0x020c
+#define mmPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX 1
+#define mmPA_CL_OBJPRIM_ID_CNTL 0x020d
+#define mmPA_CL_OBJPRIM_ID_CNTL_BASE_IDX 1
+#define mmPA_CL_NGG_CNTL 0x020e
+#define mmPA_CL_NGG_CNTL_BASE_IDX 1
+#define mmPA_SU_OVER_RASTERIZATION_CNTL 0x020f
+#define mmPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX 1
+#define mmPA_SU_POINT_SIZE 0x0280
+#define mmPA_SU_POINT_SIZE_BASE_IDX 1
+#define mmPA_SU_POINT_MINMAX 0x0281
+#define mmPA_SU_POINT_MINMAX_BASE_IDX 1
+#define mmPA_SU_LINE_CNTL 0x0282
+#define mmPA_SU_LINE_CNTL_BASE_IDX 1
+#define mmPA_SC_LINE_STIPPLE 0x0283
+#define mmPA_SC_LINE_STIPPLE_BASE_IDX 1
+#define mmVGT_OUTPUT_PATH_CNTL 0x0284
+#define mmVGT_OUTPUT_PATH_CNTL_BASE_IDX 1
+#define mmVGT_HOS_CNTL 0x0285
+#define mmVGT_HOS_CNTL_BASE_IDX 1
+#define mmVGT_HOS_MAX_TESS_LEVEL 0x0286
+#define mmVGT_HOS_MAX_TESS_LEVEL_BASE_IDX 1
+#define mmVGT_HOS_MIN_TESS_LEVEL 0x0287
+#define mmVGT_HOS_MIN_TESS_LEVEL_BASE_IDX 1
+#define mmVGT_HOS_REUSE_DEPTH 0x0288
+#define mmVGT_HOS_REUSE_DEPTH_BASE_IDX 1
+#define mmVGT_GROUP_PRIM_TYPE 0x0289
+#define mmVGT_GROUP_PRIM_TYPE_BASE_IDX 1
+#define mmVGT_GROUP_FIRST_DECR 0x028a
+#define mmVGT_GROUP_FIRST_DECR_BASE_IDX 1
+#define mmVGT_GROUP_DECR 0x028b
+#define mmVGT_GROUP_DECR_BASE_IDX 1
+#define mmVGT_GROUP_VECT_0_CNTL 0x028c
+#define mmVGT_GROUP_VECT_0_CNTL_BASE_IDX 1
+#define mmVGT_GROUP_VECT_1_CNTL 0x028d
+#define mmVGT_GROUP_VECT_1_CNTL_BASE_IDX 1
+#define mmVGT_GROUP_VECT_0_FMT_CNTL 0x028e
+#define mmVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX 1
+#define mmVGT_GROUP_VECT_1_FMT_CNTL 0x028f
+#define mmVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX 1
+#define mmVGT_GS_MODE 0x0290
+#define mmVGT_GS_MODE_BASE_IDX 1
+#define mmVGT_GS_ONCHIP_CNTL 0x0291
+#define mmVGT_GS_ONCHIP_CNTL_BASE_IDX 1
+#define mmPA_SC_MODE_CNTL_0 0x0292
+#define mmPA_SC_MODE_CNTL_0_BASE_IDX 1
+#define mmPA_SC_MODE_CNTL_1 0x0293
+#define mmPA_SC_MODE_CNTL_1_BASE_IDX 1
+#define mmVGT_ENHANCE 0x0294
+#define mmVGT_ENHANCE_BASE_IDX 1
+#define mmVGT_GS_PER_ES 0x0295
+#define mmVGT_GS_PER_ES_BASE_IDX 1
+#define mmVGT_ES_PER_GS 0x0296
+#define mmVGT_ES_PER_GS_BASE_IDX 1
+#define mmVGT_GS_PER_VS 0x0297
+#define mmVGT_GS_PER_VS_BASE_IDX 1
+#define mmVGT_GSVS_RING_OFFSET_1 0x0298
+#define mmVGT_GSVS_RING_OFFSET_1_BASE_IDX 1
+#define mmVGT_GSVS_RING_OFFSET_2 0x0299
+#define mmVGT_GSVS_RING_OFFSET_2_BASE_IDX 1
+#define mmVGT_GSVS_RING_OFFSET_3 0x029a
+#define mmVGT_GSVS_RING_OFFSET_3_BASE_IDX 1
+#define mmVGT_GS_OUT_PRIM_TYPE 0x029b
+#define mmVGT_GS_OUT_PRIM_TYPE_BASE_IDX 1
+#define mmIA_ENHANCE 0x029c
+#define mmIA_ENHANCE_BASE_IDX 1
+#define mmVGT_DMA_SIZE 0x029d
+#define mmVGT_DMA_SIZE_BASE_IDX 1
+#define mmVGT_DMA_MAX_SIZE 0x029e
+#define mmVGT_DMA_MAX_SIZE_BASE_IDX 1
+#define mmVGT_DMA_INDEX_TYPE 0x029f
+#define mmVGT_DMA_INDEX_TYPE_BASE_IDX 1
+#define mmWD_ENHANCE 0x02a0
+#define mmWD_ENHANCE_BASE_IDX 1
+#define mmVGT_PRIMITIVEID_EN 0x02a1
+#define mmVGT_PRIMITIVEID_EN_BASE_IDX 1
+#define mmVGT_DMA_NUM_INSTANCES 0x02a2
+#define mmVGT_DMA_NUM_INSTANCES_BASE_IDX 1
+#define mmVGT_PRIMITIVEID_RESET 0x02a3
+#define mmVGT_PRIMITIVEID_RESET_BASE_IDX 1
+#define mmVGT_EVENT_INITIATOR 0x02a4
+#define mmVGT_EVENT_INITIATOR_BASE_IDX 1
+#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP 0x02a5
+#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1
+#define mmVGT_DRAW_PAYLOAD_CNTL 0x02a6
+#define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1
+#define mmVGT_INDEX_PAYLOAD_CNTL 0x02a7
+#define mmVGT_INDEX_PAYLOAD_CNTL_BASE_IDX 1
+#define mmVGT_INSTANCE_STEP_RATE_0 0x02a8
+#define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1
+#define mmVGT_INSTANCE_STEP_RATE_1 0x02a9
+#define mmVGT_INSTANCE_STEP_RATE_1_BASE_IDX 1
+#define mmVGT_ESGS_RING_ITEMSIZE 0x02ab
+#define mmVGT_ESGS_RING_ITEMSIZE_BASE_IDX 1
+#define mmVGT_GSVS_RING_ITEMSIZE 0x02ac
+#define mmVGT_GSVS_RING_ITEMSIZE_BASE_IDX 1
+#define mmVGT_REUSE_OFF 0x02ad
+#define mmVGT_REUSE_OFF_BASE_IDX 1
+#define mmVGT_VTX_CNT_EN 0x02ae
+#define mmVGT_VTX_CNT_EN_BASE_IDX 1
+#define mmDB_HTILE_SURFACE 0x02af
+#define mmDB_HTILE_SURFACE_BASE_IDX 1
+#define mmDB_SRESULTS_COMPARE_STATE0 0x02b0
+#define mmDB_SRESULTS_COMPARE_STATE0_BASE_IDX 1
+#define mmDB_SRESULTS_COMPARE_STATE1 0x02b1
+#define mmDB_SRESULTS_COMPARE_STATE1_BASE_IDX 1
+#define mmDB_PRELOAD_CONTROL 0x02b2
+#define mmDB_PRELOAD_CONTROL_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_SIZE_0 0x02b4
+#define mmVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX 1
+#define mmVGT_STRMOUT_VTX_STRIDE_0 0x02b5
+#define mmVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0x02b7
+#define mmVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_SIZE_1 0x02b8
+#define mmVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX 1
+#define mmVGT_STRMOUT_VTX_STRIDE_1 0x02b9
+#define mmVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0x02bb
+#define mmVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_SIZE_2 0x02bc
+#define mmVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX 1
+#define mmVGT_STRMOUT_VTX_STRIDE_2 0x02bd
+#define mmVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0x02bf
+#define mmVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_SIZE_3 0x02c0
+#define mmVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX 1
+#define mmVGT_STRMOUT_VTX_STRIDE_3 0x02c1
+#define mmVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0x02c3
+#define mmVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX 1
+#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x02ca
+#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX 1
+#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x02cb
+#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX 1
+#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x02cc
+#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX 1
+#define mmVGT_GS_MAX_VERT_OUT 0x02ce
+#define mmVGT_GS_MAX_VERT_OUT_BASE_IDX 1
+#define mmVGT_TESS_DISTRIBUTION 0x02d4
+#define mmVGT_TESS_DISTRIBUTION_BASE_IDX 1
+#define mmVGT_SHADER_STAGES_EN 0x02d5
+#define mmVGT_SHADER_STAGES_EN_BASE_IDX 1
+#define mmVGT_LS_HS_CONFIG 0x02d6
+#define mmVGT_LS_HS_CONFIG_BASE_IDX 1
+#define mmVGT_GS_VERT_ITEMSIZE 0x02d7
+#define mmVGT_GS_VERT_ITEMSIZE_BASE_IDX 1
+#define mmVGT_GS_VERT_ITEMSIZE_1 0x02d8
+#define mmVGT_GS_VERT_ITEMSIZE_1_BASE_IDX 1
+#define mmVGT_GS_VERT_ITEMSIZE_2 0x02d9
+#define mmVGT_GS_VERT_ITEMSIZE_2_BASE_IDX 1
+#define mmVGT_GS_VERT_ITEMSIZE_3 0x02da
+#define mmVGT_GS_VERT_ITEMSIZE_3_BASE_IDX 1
+#define mmVGT_TF_PARAM 0x02db
+#define mmVGT_TF_PARAM_BASE_IDX 1
+#define mmDB_ALPHA_TO_MASK 0x02dc
+#define mmDB_ALPHA_TO_MASK_BASE_IDX 1
+#define mmVGT_DISPATCH_DRAW_INDEX 0x02dd
+#define mmVGT_DISPATCH_DRAW_INDEX_BASE_IDX 1
+#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0x02de
+#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX 1
+#define mmPA_SU_POLY_OFFSET_CLAMP 0x02df
+#define mmPA_SU_POLY_OFFSET_CLAMP_BASE_IDX 1
+#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x02e0
+#define mmPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX 1
+#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x02e1
+#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX 1
+#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x02e2
+#define mmPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX 1
+#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x02e3
+#define mmPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX 1
+#define mmVGT_GS_INSTANCE_CNT 0x02e4
+#define mmVGT_GS_INSTANCE_CNT_BASE_IDX 1
+#define mmVGT_STRMOUT_CONFIG 0x02e5
+#define mmVGT_STRMOUT_CONFIG_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_CONFIG 0x02e6
+#define mmVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX 1
+#define mmVGT_DMA_EVENT_INITIATOR 0x02e7
+#define mmVGT_DMA_EVENT_INITIATOR_BASE_IDX 1
+#define mmPA_SC_CENTROID_PRIORITY_0 0x02f5
+#define mmPA_SC_CENTROID_PRIORITY_0_BASE_IDX 1
+#define mmPA_SC_CENTROID_PRIORITY_1 0x02f6
+#define mmPA_SC_CENTROID_PRIORITY_1_BASE_IDX 1
+#define mmPA_SC_LINE_CNTL 0x02f7
+#define mmPA_SC_LINE_CNTL_BASE_IDX 1
+#define mmPA_SC_AA_CONFIG 0x02f8
+#define mmPA_SC_AA_CONFIG_BASE_IDX 1
+#define mmPA_SU_VTX_CNTL 0x02f9
+#define mmPA_SU_VTX_CNTL_BASE_IDX 1
+#define mmPA_CL_GB_VERT_CLIP_ADJ 0x02fa
+#define mmPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX 1
+#define mmPA_CL_GB_VERT_DISC_ADJ 0x02fb
+#define mmPA_CL_GB_VERT_DISC_ADJ_BASE_IDX 1
+#define mmPA_CL_GB_HORZ_CLIP_ADJ 0x02fc
+#define mmPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX 1
+#define mmPA_CL_GB_HORZ_DISC_ADJ 0x02fd
+#define mmPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x02fe
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x02ff
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x0300
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x0301
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x0302
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x0303
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x0304
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x0305
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x0306
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x0307
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x0308
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x0309
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x030a
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x030b
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x030c
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x030d
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX 1
+#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0x030e
+#define mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 1
+#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0x030f
+#define mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 1
+#define mmPA_SC_SHADER_CONTROL 0x0310
+#define mmPA_SC_SHADER_CONTROL_BASE_IDX 1
+#define mmPA_SC_BINNER_CNTL_0 0x0311
+#define mmPA_SC_BINNER_CNTL_0_BASE_IDX 1
+#define mmPA_SC_BINNER_CNTL_1 0x0312
+#define mmPA_SC_BINNER_CNTL_1_BASE_IDX 1
+#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0x0313
+#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX 1
+#define mmPA_SC_NGG_MODE_CNTL 0x0314
+#define mmPA_SC_NGG_MODE_CNTL_BASE_IDX 1
+#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0x0316
+#define mmVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX 1
+#define mmVGT_OUT_DEALLOC_CNTL 0x0317
+#define mmVGT_OUT_DEALLOC_CNTL_BASE_IDX 1
+#define mmCB_COLOR0_BASE 0x0318
+#define mmCB_COLOR0_BASE_BASE_IDX 1
+#define mmCB_COLOR0_BASE_EXT 0x0319
+#define mmCB_COLOR0_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR0_ATTRIB2 0x031a
+#define mmCB_COLOR0_ATTRIB2_BASE_IDX 1
+#define mmCB_COLOR0_VIEW 0x031b
+#define mmCB_COLOR0_VIEW_BASE_IDX 1
+#define mmCB_COLOR0_INFO 0x031c
+#define mmCB_COLOR0_INFO_BASE_IDX 1
+#define mmCB_COLOR0_ATTRIB 0x031d
+#define mmCB_COLOR0_ATTRIB_BASE_IDX 1
+#define mmCB_COLOR0_DCC_CONTROL 0x031e
+#define mmCB_COLOR0_DCC_CONTROL_BASE_IDX 1
+#define mmCB_COLOR0_CMASK 0x031f
+#define mmCB_COLOR0_CMASK_BASE_IDX 1
+#define mmCB_COLOR0_CMASK_BASE_EXT 0x0320
+#define mmCB_COLOR0_CMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR0_FMASK 0x0321
+#define mmCB_COLOR0_FMASK_BASE_IDX 1
+#define mmCB_COLOR0_FMASK_BASE_EXT 0x0322
+#define mmCB_COLOR0_FMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR0_CLEAR_WORD0 0x0323
+#define mmCB_COLOR0_CLEAR_WORD0_BASE_IDX 1
+#define mmCB_COLOR0_CLEAR_WORD1 0x0324
+#define mmCB_COLOR0_CLEAR_WORD1_BASE_IDX 1
+#define mmCB_COLOR0_DCC_BASE 0x0325
+#define mmCB_COLOR0_DCC_BASE_BASE_IDX 1
+#define mmCB_COLOR0_DCC_BASE_EXT 0x0326
+#define mmCB_COLOR0_DCC_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR1_BASE 0x0327
+#define mmCB_COLOR1_BASE_BASE_IDX 1
+#define mmCB_COLOR1_BASE_EXT 0x0328
+#define mmCB_COLOR1_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR1_ATTRIB2 0x0329
+#define mmCB_COLOR1_ATTRIB2_BASE_IDX 1
+#define mmCB_COLOR1_VIEW 0x032a
+#define mmCB_COLOR1_VIEW_BASE_IDX 1
+#define mmCB_COLOR1_INFO 0x032b
+#define mmCB_COLOR1_INFO_BASE_IDX 1
+#define mmCB_COLOR1_ATTRIB 0x032c
+#define mmCB_COLOR1_ATTRIB_BASE_IDX 1
+#define mmCB_COLOR1_DCC_CONTROL 0x032d
+#define mmCB_COLOR1_DCC_CONTROL_BASE_IDX 1
+#define mmCB_COLOR1_CMASK 0x032e
+#define mmCB_COLOR1_CMASK_BASE_IDX 1
+#define mmCB_COLOR1_CMASK_BASE_EXT 0x032f
+#define mmCB_COLOR1_CMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR1_FMASK 0x0330
+#define mmCB_COLOR1_FMASK_BASE_IDX 1
+#define mmCB_COLOR1_FMASK_BASE_EXT 0x0331
+#define mmCB_COLOR1_FMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR1_CLEAR_WORD0 0x0332
+#define mmCB_COLOR1_CLEAR_WORD0_BASE_IDX 1
+#define mmCB_COLOR1_CLEAR_WORD1 0x0333
+#define mmCB_COLOR1_CLEAR_WORD1_BASE_IDX 1
+#define mmCB_COLOR1_DCC_BASE 0x0334
+#define mmCB_COLOR1_DCC_BASE_BASE_IDX 1
+#define mmCB_COLOR1_DCC_BASE_EXT 0x0335
+#define mmCB_COLOR1_DCC_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR2_BASE 0x0336
+#define mmCB_COLOR2_BASE_BASE_IDX 1
+#define mmCB_COLOR2_BASE_EXT 0x0337
+#define mmCB_COLOR2_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR2_ATTRIB2 0x0338
+#define mmCB_COLOR2_ATTRIB2_BASE_IDX 1
+#define mmCB_COLOR2_VIEW 0x0339
+#define mmCB_COLOR2_VIEW_BASE_IDX 1
+#define mmCB_COLOR2_INFO 0x033a
+#define mmCB_COLOR2_INFO_BASE_IDX 1
+#define mmCB_COLOR2_ATTRIB 0x033b
+#define mmCB_COLOR2_ATTRIB_BASE_IDX 1
+#define mmCB_COLOR2_DCC_CONTROL 0x033c
+#define mmCB_COLOR2_DCC_CONTROL_BASE_IDX 1
+#define mmCB_COLOR2_CMASK 0x033d
+#define mmCB_COLOR2_CMASK_BASE_IDX 1
+#define mmCB_COLOR2_CMASK_BASE_EXT 0x033e
+#define mmCB_COLOR2_CMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR2_FMASK 0x033f
+#define mmCB_COLOR2_FMASK_BASE_IDX 1
+#define mmCB_COLOR2_FMASK_BASE_EXT 0x0340
+#define mmCB_COLOR2_FMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR2_CLEAR_WORD0 0x0341
+#define mmCB_COLOR2_CLEAR_WORD0_BASE_IDX 1
+#define mmCB_COLOR2_CLEAR_WORD1 0x0342
+#define mmCB_COLOR2_CLEAR_WORD1_BASE_IDX 1
+#define mmCB_COLOR2_DCC_BASE 0x0343
+#define mmCB_COLOR2_DCC_BASE_BASE_IDX 1
+#define mmCB_COLOR2_DCC_BASE_EXT 0x0344
+#define mmCB_COLOR2_DCC_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR3_BASE 0x0345
+#define mmCB_COLOR3_BASE_BASE_IDX 1
+#define mmCB_COLOR3_BASE_EXT 0x0346
+#define mmCB_COLOR3_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR3_ATTRIB2 0x0347
+#define mmCB_COLOR3_ATTRIB2_BASE_IDX 1
+#define mmCB_COLOR3_VIEW 0x0348
+#define mmCB_COLOR3_VIEW_BASE_IDX 1
+#define mmCB_COLOR3_INFO 0x0349
+#define mmCB_COLOR3_INFO_BASE_IDX 1
+#define mmCB_COLOR3_ATTRIB 0x034a
+#define mmCB_COLOR3_ATTRIB_BASE_IDX 1
+#define mmCB_COLOR3_DCC_CONTROL 0x034b
+#define mmCB_COLOR3_DCC_CONTROL_BASE_IDX 1
+#define mmCB_COLOR3_CMASK 0x034c
+#define mmCB_COLOR3_CMASK_BASE_IDX 1
+#define mmCB_COLOR3_CMASK_BASE_EXT 0x034d
+#define mmCB_COLOR3_CMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR3_FMASK 0x034e
+#define mmCB_COLOR3_FMASK_BASE_IDX 1
+#define mmCB_COLOR3_FMASK_BASE_EXT 0x034f
+#define mmCB_COLOR3_FMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR3_CLEAR_WORD0 0x0350
+#define mmCB_COLOR3_CLEAR_WORD0_BASE_IDX 1
+#define mmCB_COLOR3_CLEAR_WORD1 0x0351
+#define mmCB_COLOR3_CLEAR_WORD1_BASE_IDX 1
+#define mmCB_COLOR3_DCC_BASE 0x0352
+#define mmCB_COLOR3_DCC_BASE_BASE_IDX 1
+#define mmCB_COLOR3_DCC_BASE_EXT 0x0353
+#define mmCB_COLOR3_DCC_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR4_BASE 0x0354
+#define mmCB_COLOR4_BASE_BASE_IDX 1
+#define mmCB_COLOR4_BASE_EXT 0x0355
+#define mmCB_COLOR4_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR4_ATTRIB2 0x0356
+#define mmCB_COLOR4_ATTRIB2_BASE_IDX 1
+#define mmCB_COLOR4_VIEW 0x0357
+#define mmCB_COLOR4_VIEW_BASE_IDX 1
+#define mmCB_COLOR4_INFO 0x0358
+#define mmCB_COLOR4_INFO_BASE_IDX 1
+#define mmCB_COLOR4_ATTRIB 0x0359
+#define mmCB_COLOR4_ATTRIB_BASE_IDX 1
+#define mmCB_COLOR4_DCC_CONTROL 0x035a
+#define mmCB_COLOR4_DCC_CONTROL_BASE_IDX 1
+#define mmCB_COLOR4_CMASK 0x035b
+#define mmCB_COLOR4_CMASK_BASE_IDX 1
+#define mmCB_COLOR4_CMASK_BASE_EXT 0x035c
+#define mmCB_COLOR4_CMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR4_FMASK 0x035d
+#define mmCB_COLOR4_FMASK_BASE_IDX 1
+#define mmCB_COLOR4_FMASK_BASE_EXT 0x035e
+#define mmCB_COLOR4_FMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR4_CLEAR_WORD0 0x035f
+#define mmCB_COLOR4_CLEAR_WORD0_BASE_IDX 1
+#define mmCB_COLOR4_CLEAR_WORD1 0x0360
+#define mmCB_COLOR4_CLEAR_WORD1_BASE_IDX 1
+#define mmCB_COLOR4_DCC_BASE 0x0361
+#define mmCB_COLOR4_DCC_BASE_BASE_IDX 1
+#define mmCB_COLOR4_DCC_BASE_EXT 0x0362
+#define mmCB_COLOR4_DCC_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR5_BASE 0x0363
+#define mmCB_COLOR5_BASE_BASE_IDX 1
+#define mmCB_COLOR5_BASE_EXT 0x0364
+#define mmCB_COLOR5_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR5_ATTRIB2 0x0365
+#define mmCB_COLOR5_ATTRIB2_BASE_IDX 1
+#define mmCB_COLOR5_VIEW 0x0366
+#define mmCB_COLOR5_VIEW_BASE_IDX 1
+#define mmCB_COLOR5_INFO 0x0367
+#define mmCB_COLOR5_INFO_BASE_IDX 1
+#define mmCB_COLOR5_ATTRIB 0x0368
+#define mmCB_COLOR5_ATTRIB_BASE_IDX 1
+#define mmCB_COLOR5_DCC_CONTROL 0x0369
+#define mmCB_COLOR5_DCC_CONTROL_BASE_IDX 1
+#define mmCB_COLOR5_CMASK 0x036a
+#define mmCB_COLOR5_CMASK_BASE_IDX 1
+#define mmCB_COLOR5_CMASK_BASE_EXT 0x036b
+#define mmCB_COLOR5_CMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR5_FMASK 0x036c
+#define mmCB_COLOR5_FMASK_BASE_IDX 1
+#define mmCB_COLOR5_FMASK_BASE_EXT 0x036d
+#define mmCB_COLOR5_FMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR5_CLEAR_WORD0 0x036e
+#define mmCB_COLOR5_CLEAR_WORD0_BASE_IDX 1
+#define mmCB_COLOR5_CLEAR_WORD1 0x036f
+#define mmCB_COLOR5_CLEAR_WORD1_BASE_IDX 1
+#define mmCB_COLOR5_DCC_BASE 0x0370
+#define mmCB_COLOR5_DCC_BASE_BASE_IDX 1
+#define mmCB_COLOR5_DCC_BASE_EXT 0x0371
+#define mmCB_COLOR5_DCC_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR6_BASE 0x0372
+#define mmCB_COLOR6_BASE_BASE_IDX 1
+#define mmCB_COLOR6_BASE_EXT 0x0373
+#define mmCB_COLOR6_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR6_ATTRIB2 0x0374
+#define mmCB_COLOR6_ATTRIB2_BASE_IDX 1
+#define mmCB_COLOR6_VIEW 0x0375
+#define mmCB_COLOR6_VIEW_BASE_IDX 1
+#define mmCB_COLOR6_INFO 0x0376
+#define mmCB_COLOR6_INFO_BASE_IDX 1
+#define mmCB_COLOR6_ATTRIB 0x0377
+#define mmCB_COLOR6_ATTRIB_BASE_IDX 1
+#define mmCB_COLOR6_DCC_CONTROL 0x0378
+#define mmCB_COLOR6_DCC_CONTROL_BASE_IDX 1
+#define mmCB_COLOR6_CMASK 0x0379
+#define mmCB_COLOR6_CMASK_BASE_IDX 1
+#define mmCB_COLOR6_CMASK_BASE_EXT 0x037a
+#define mmCB_COLOR6_CMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR6_FMASK 0x037b
+#define mmCB_COLOR6_FMASK_BASE_IDX 1
+#define mmCB_COLOR6_FMASK_BASE_EXT 0x037c
+#define mmCB_COLOR6_FMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR6_CLEAR_WORD0 0x037d
+#define mmCB_COLOR6_CLEAR_WORD0_BASE_IDX 1
+#define mmCB_COLOR6_CLEAR_WORD1 0x037e
+#define mmCB_COLOR6_CLEAR_WORD1_BASE_IDX 1
+#define mmCB_COLOR6_DCC_BASE 0x037f
+#define mmCB_COLOR6_DCC_BASE_BASE_IDX 1
+#define mmCB_COLOR6_DCC_BASE_EXT 0x0380
+#define mmCB_COLOR6_DCC_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR7_BASE 0x0381
+#define mmCB_COLOR7_BASE_BASE_IDX 1
+#define mmCB_COLOR7_BASE_EXT 0x0382
+#define mmCB_COLOR7_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR7_ATTRIB2 0x0383
+#define mmCB_COLOR7_ATTRIB2_BASE_IDX 1
+#define mmCB_COLOR7_VIEW 0x0384
+#define mmCB_COLOR7_VIEW_BASE_IDX 1
+#define mmCB_COLOR7_INFO 0x0385
+#define mmCB_COLOR7_INFO_BASE_IDX 1
+#define mmCB_COLOR7_ATTRIB 0x0386
+#define mmCB_COLOR7_ATTRIB_BASE_IDX 1
+#define mmCB_COLOR7_DCC_CONTROL 0x0387
+#define mmCB_COLOR7_DCC_CONTROL_BASE_IDX 1
+#define mmCB_COLOR7_CMASK 0x0388
+#define mmCB_COLOR7_CMASK_BASE_IDX 1
+#define mmCB_COLOR7_CMASK_BASE_EXT 0x0389
+#define mmCB_COLOR7_CMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR7_FMASK 0x038a
+#define mmCB_COLOR7_FMASK_BASE_IDX 1
+#define mmCB_COLOR7_FMASK_BASE_EXT 0x038b
+#define mmCB_COLOR7_FMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR7_CLEAR_WORD0 0x038c
+#define mmCB_COLOR7_CLEAR_WORD0_BASE_IDX 1
+#define mmCB_COLOR7_CLEAR_WORD1 0x038d
+#define mmCB_COLOR7_CLEAR_WORD1_BASE_IDX 1
+#define mmCB_COLOR7_DCC_BASE 0x038e
+#define mmCB_COLOR7_DCC_BASE_BASE_IDX 1
+#define mmCB_COLOR7_DCC_BASE_EXT 0x038f
+#define mmCB_COLOR7_DCC_BASE_EXT_BASE_IDX 1
+
+
+// addressBlock: gc_gfxudec
+// base address: 0x30000
+#define mmCP_EOP_DONE_ADDR_LO 0x2000
+#define mmCP_EOP_DONE_ADDR_LO_BASE_IDX 1
+#define mmCP_EOP_DONE_ADDR_HI 0x2001
+#define mmCP_EOP_DONE_ADDR_HI_BASE_IDX 1
+#define mmCP_EOP_DONE_DATA_LO 0x2002
+#define mmCP_EOP_DONE_DATA_LO_BASE_IDX 1
+#define mmCP_EOP_DONE_DATA_HI 0x2003
+#define mmCP_EOP_DONE_DATA_HI_BASE_IDX 1
+#define mmCP_EOP_LAST_FENCE_LO 0x2004
+#define mmCP_EOP_LAST_FENCE_LO_BASE_IDX 1
+#define mmCP_EOP_LAST_FENCE_HI 0x2005
+#define mmCP_EOP_LAST_FENCE_HI_BASE_IDX 1
+#define mmCP_STREAM_OUT_ADDR_LO 0x2006
+#define mmCP_STREAM_OUT_ADDR_LO_BASE_IDX 1
+#define mmCP_STREAM_OUT_ADDR_HI 0x2007
+#define mmCP_STREAM_OUT_ADDR_HI_BASE_IDX 1
+#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0x2008
+#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX 1
+#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0x2009
+#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX 1
+#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0x200a
+#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX 1
+#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0x200b
+#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX 1
+#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0x200c
+#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX 1
+#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0x200d
+#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX 1
+#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0x200e
+#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX 1
+#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0x200f
+#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX 1
+#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0x2010
+#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX 1
+#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0x2011
+#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX 1
+#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0x2012
+#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX 1
+#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0x2013
+#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX 1
+#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0x2014
+#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX 1
+#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0x2015
+#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX 1
+#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0x2016
+#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX 1
+#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0x2017
+#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX 1
+#define mmCP_PIPE_STATS_ADDR_LO 0x2018
+#define mmCP_PIPE_STATS_ADDR_LO_BASE_IDX 1
+#define mmCP_PIPE_STATS_ADDR_HI 0x2019
+#define mmCP_PIPE_STATS_ADDR_HI_BASE_IDX 1
+#define mmCP_VGT_IAVERT_COUNT_LO 0x201a
+#define mmCP_VGT_IAVERT_COUNT_LO_BASE_IDX 1
+#define mmCP_VGT_IAVERT_COUNT_HI 0x201b
+#define mmCP_VGT_IAVERT_COUNT_HI_BASE_IDX 1
+#define mmCP_VGT_IAPRIM_COUNT_LO 0x201c
+#define mmCP_VGT_IAPRIM_COUNT_LO_BASE_IDX 1
+#define mmCP_VGT_IAPRIM_COUNT_HI 0x201d
+#define mmCP_VGT_IAPRIM_COUNT_HI_BASE_IDX 1
+#define mmCP_VGT_GSPRIM_COUNT_LO 0x201e
+#define mmCP_VGT_GSPRIM_COUNT_LO_BASE_IDX 1
+#define mmCP_VGT_GSPRIM_COUNT_HI 0x201f
+#define mmCP_VGT_GSPRIM_COUNT_HI_BASE_IDX 1
+#define mmCP_VGT_VSINVOC_COUNT_LO 0x2020
+#define mmCP_VGT_VSINVOC_COUNT_LO_BASE_IDX 1
+#define mmCP_VGT_VSINVOC_COUNT_HI 0x2021
+#define mmCP_VGT_VSINVOC_COUNT_HI_BASE_IDX 1
+#define mmCP_VGT_GSINVOC_COUNT_LO 0x2022
+#define mmCP_VGT_GSINVOC_COUNT_LO_BASE_IDX 1
+#define mmCP_VGT_GSINVOC_COUNT_HI 0x2023
+#define mmCP_VGT_GSINVOC_COUNT_HI_BASE_IDX 1
+#define mmCP_VGT_HSINVOC_COUNT_LO 0x2024
+#define mmCP_VGT_HSINVOC_COUNT_LO_BASE_IDX 1
+#define mmCP_VGT_HSINVOC_COUNT_HI 0x2025
+#define mmCP_VGT_HSINVOC_COUNT_HI_BASE_IDX 1
+#define mmCP_VGT_DSINVOC_COUNT_LO 0x2026
+#define mmCP_VGT_DSINVOC_COUNT_LO_BASE_IDX 1
+#define mmCP_VGT_DSINVOC_COUNT_HI 0x2027
+#define mmCP_VGT_DSINVOC_COUNT_HI_BASE_IDX 1
+#define mmCP_PA_CINVOC_COUNT_LO 0x2028
+#define mmCP_PA_CINVOC_COUNT_LO_BASE_IDX 1
+#define mmCP_PA_CINVOC_COUNT_HI 0x2029
+#define mmCP_PA_CINVOC_COUNT_HI_BASE_IDX 1
+#define mmCP_PA_CPRIM_COUNT_LO 0x202a
+#define mmCP_PA_CPRIM_COUNT_LO_BASE_IDX 1
+#define mmCP_PA_CPRIM_COUNT_HI 0x202b
+#define mmCP_PA_CPRIM_COUNT_HI_BASE_IDX 1
+#define mmCP_SC_PSINVOC_COUNT0_LO 0x202c
+#define mmCP_SC_PSINVOC_COUNT0_LO_BASE_IDX 1
+#define mmCP_SC_PSINVOC_COUNT0_HI 0x202d
+#define mmCP_SC_PSINVOC_COUNT0_HI_BASE_IDX 1
+#define mmCP_SC_PSINVOC_COUNT1_LO 0x202e
+#define mmCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1
+#define mmCP_SC_PSINVOC_COUNT1_HI 0x202f
+#define mmCP_SC_PSINVOC_COUNT1_HI_BASE_IDX 1
+#define mmCP_VGT_CSINVOC_COUNT_LO 0x2030
+#define mmCP_VGT_CSINVOC_COUNT_LO_BASE_IDX 1
+#define mmCP_VGT_CSINVOC_COUNT_HI 0x2031
+#define mmCP_VGT_CSINVOC_COUNT_HI_BASE_IDX 1
+#define mmCP_PIPE_STATS_CONTROL 0x203d
+#define mmCP_PIPE_STATS_CONTROL_BASE_IDX 1
+#define mmCP_STREAM_OUT_CONTROL 0x203e
+#define mmCP_STREAM_OUT_CONTROL_BASE_IDX 1
+#define mmCP_STRMOUT_CNTL 0x203f
+#define mmCP_STRMOUT_CNTL_BASE_IDX 1
+#define mmSCRATCH_REG0 0x2040
+#define mmSCRATCH_REG0_BASE_IDX 1
+#define mmSCRATCH_REG1 0x2041
+#define mmSCRATCH_REG1_BASE_IDX 1
+#define mmSCRATCH_REG2 0x2042
+#define mmSCRATCH_REG2_BASE_IDX 1
+#define mmSCRATCH_REG3 0x2043
+#define mmSCRATCH_REG3_BASE_IDX 1
+#define mmSCRATCH_REG4 0x2044
+#define mmSCRATCH_REG4_BASE_IDX 1
+#define mmSCRATCH_REG5 0x2045
+#define mmSCRATCH_REG5_BASE_IDX 1
+#define mmSCRATCH_REG6 0x2046
+#define mmSCRATCH_REG6_BASE_IDX 1
+#define mmSCRATCH_REG7 0x2047
+#define mmSCRATCH_REG7_BASE_IDX 1
+#define mmCP_APPEND_DATA_HI 0x204c
+#define mmCP_APPEND_DATA_HI_BASE_IDX 1
+#define mmCP_APPEND_LAST_CS_FENCE_HI 0x204d
+#define mmCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX 1
+#define mmCP_APPEND_LAST_PS_FENCE_HI 0x204e
+#define mmCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX 1
+#define mmSCRATCH_UMSK 0x2050
+#define mmSCRATCH_UMSK_BASE_IDX 1
+#define mmSCRATCH_ADDR 0x2051
+#define mmSCRATCH_ADDR_BASE_IDX 1
+#define mmCP_PFP_ATOMIC_PREOP_LO 0x2052
+#define mmCP_PFP_ATOMIC_PREOP_LO_BASE_IDX 1
+#define mmCP_PFP_ATOMIC_PREOP_HI 0x2053
+#define mmCP_PFP_ATOMIC_PREOP_HI_BASE_IDX 1
+#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0x2054
+#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1
+#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0x2055
+#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1
+#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0x2056
+#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1
+#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0x2057
+#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1
+#define mmCP_APPEND_ADDR_LO 0x2058
+#define mmCP_APPEND_ADDR_LO_BASE_IDX 1
+#define mmCP_APPEND_ADDR_HI 0x2059
+#define mmCP_APPEND_ADDR_HI_BASE_IDX 1
+#define mmCP_APPEND_DATA_LO 0x205a
+#define mmCP_APPEND_DATA_LO_BASE_IDX 1
+#define mmCP_APPEND_LAST_CS_FENCE_LO 0x205b
+#define mmCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX 1
+#define mmCP_APPEND_LAST_PS_FENCE_LO 0x205c
+#define mmCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX 1
+#define mmCP_ATOMIC_PREOP_LO 0x205d
+#define mmCP_ATOMIC_PREOP_LO_BASE_IDX 1
+#define mmCP_ME_ATOMIC_PREOP_LO 0x205d
+#define mmCP_ME_ATOMIC_PREOP_LO_BASE_IDX 1
+#define mmCP_ATOMIC_PREOP_HI 0x205e
+#define mmCP_ATOMIC_PREOP_HI_BASE_IDX 1
+#define mmCP_ME_ATOMIC_PREOP_HI 0x205e
+#define mmCP_ME_ATOMIC_PREOP_HI_BASE_IDX 1
+#define mmCP_GDS_ATOMIC0_PREOP_LO 0x205f
+#define mmCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1
+#define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0x205f
+#define mmCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1
+#define mmCP_GDS_ATOMIC0_PREOP_HI 0x2060
+#define mmCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1
+#define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0x2060
+#define mmCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1
+#define mmCP_GDS_ATOMIC1_PREOP_LO 0x2061
+#define mmCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1
+#define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0x2061
+#define mmCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1
+#define mmCP_GDS_ATOMIC1_PREOP_HI 0x2062
+#define mmCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1
+#define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0x2062
+#define mmCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1
+#define mmCP_ME_MC_WADDR_LO 0x2069
+#define mmCP_ME_MC_WADDR_LO_BASE_IDX 1
+#define mmCP_ME_MC_WADDR_HI 0x206a
+#define mmCP_ME_MC_WADDR_HI_BASE_IDX 1
+#define mmCP_ME_MC_WDATA_LO 0x206b
+#define mmCP_ME_MC_WDATA_LO_BASE_IDX 1
+#define mmCP_ME_MC_WDATA_HI 0x206c
+#define mmCP_ME_MC_WDATA_HI_BASE_IDX 1
+#define mmCP_ME_MC_RADDR_LO 0x206d
+#define mmCP_ME_MC_RADDR_LO_BASE_IDX 1
+#define mmCP_ME_MC_RADDR_HI 0x206e
+#define mmCP_ME_MC_RADDR_HI_BASE_IDX 1
+#define mmCP_SEM_WAIT_TIMER 0x206f
+#define mmCP_SEM_WAIT_TIMER_BASE_IDX 1
+#define mmCP_SIG_SEM_ADDR_LO 0x2070
+#define mmCP_SIG_SEM_ADDR_LO_BASE_IDX 1
+#define mmCP_SIG_SEM_ADDR_HI 0x2071
+#define mmCP_SIG_SEM_ADDR_HI_BASE_IDX 1
+#define mmCP_WAIT_REG_MEM_TIMEOUT 0x2074
+#define mmCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX 1
+#define mmCP_WAIT_SEM_ADDR_LO 0x2075
+#define mmCP_WAIT_SEM_ADDR_LO_BASE_IDX 1
+#define mmCP_WAIT_SEM_ADDR_HI 0x2076
+#define mmCP_WAIT_SEM_ADDR_HI_BASE_IDX 1
+#define mmCP_DMA_PFP_CONTROL 0x2077
+#define mmCP_DMA_PFP_CONTROL_BASE_IDX 1
+#define mmCP_DMA_ME_CONTROL 0x2078
+#define mmCP_DMA_ME_CONTROL_BASE_IDX 1
+#define mmCP_COHER_BASE_HI 0x2079
+#define mmCP_COHER_BASE_HI_BASE_IDX 1
+#define mmCP_COHER_START_DELAY 0x207b
+#define mmCP_COHER_START_DELAY_BASE_IDX 1
+#define mmCP_COHER_CNTL 0x207c
+#define mmCP_COHER_CNTL_BASE_IDX 1
+#define mmCP_COHER_SIZE 0x207d
+#define mmCP_COHER_SIZE_BASE_IDX 1
+#define mmCP_COHER_BASE 0x207e
+#define mmCP_COHER_BASE_BASE_IDX 1
+#define mmCP_COHER_STATUS 0x207f
+#define mmCP_COHER_STATUS_BASE_IDX 1
+#define mmCP_DMA_ME_SRC_ADDR 0x2080
+#define mmCP_DMA_ME_SRC_ADDR_BASE_IDX 1
+#define mmCP_DMA_ME_SRC_ADDR_HI 0x2081
+#define mmCP_DMA_ME_SRC_ADDR_HI_BASE_IDX 1
+#define mmCP_DMA_ME_DST_ADDR 0x2082
+#define mmCP_DMA_ME_DST_ADDR_BASE_IDX 1
+#define mmCP_DMA_ME_DST_ADDR_HI 0x2083
+#define mmCP_DMA_ME_DST_ADDR_HI_BASE_IDX 1
+#define mmCP_DMA_ME_COMMAND 0x2084
+#define mmCP_DMA_ME_COMMAND_BASE_IDX 1
+#define mmCP_DMA_PFP_SRC_ADDR 0x2085
+#define mmCP_DMA_PFP_SRC_ADDR_BASE_IDX 1
+#define mmCP_DMA_PFP_SRC_ADDR_HI 0x2086
+#define mmCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX 1
+#define mmCP_DMA_PFP_DST_ADDR 0x2087
+#define mmCP_DMA_PFP_DST_ADDR_BASE_IDX 1
+#define mmCP_DMA_PFP_DST_ADDR_HI 0x2088
+#define mmCP_DMA_PFP_DST_ADDR_HI_BASE_IDX 1
+#define mmCP_DMA_PFP_COMMAND 0x2089
+#define mmCP_DMA_PFP_COMMAND_BASE_IDX 1
+#define mmCP_DMA_CNTL 0x208a
+#define mmCP_DMA_CNTL_BASE_IDX 1
+#define mmCP_DMA_READ_TAGS 0x208b
+#define mmCP_DMA_READ_TAGS_BASE_IDX 1
+#define mmCP_COHER_SIZE_HI 0x208c
+#define mmCP_COHER_SIZE_HI_BASE_IDX 1
+#define mmCP_PFP_IB_CONTROL 0x208d
+#define mmCP_PFP_IB_CONTROL_BASE_IDX 1
+#define mmCP_PFP_LOAD_CONTROL 0x208e
+#define mmCP_PFP_LOAD_CONTROL_BASE_IDX 1
+#define mmCP_SCRATCH_INDEX 0x208f
+#define mmCP_SCRATCH_INDEX_BASE_IDX 1
+#define mmCP_SCRATCH_DATA 0x2090
+#define mmCP_SCRATCH_DATA_BASE_IDX 1
+#define mmCP_RB_OFFSET 0x2091
+#define mmCP_RB_OFFSET_BASE_IDX 1
+#define mmCP_IB1_OFFSET 0x2092
+#define mmCP_IB1_OFFSET_BASE_IDX 1
+#define mmCP_IB2_OFFSET 0x2093
+#define mmCP_IB2_OFFSET_BASE_IDX 1
+#define mmCP_IB1_PREAMBLE_BEGIN 0x2094
+#define mmCP_IB1_PREAMBLE_BEGIN_BASE_IDX 1
+#define mmCP_IB1_PREAMBLE_END 0x2095
+#define mmCP_IB1_PREAMBLE_END_BASE_IDX 1
+#define mmCP_IB2_PREAMBLE_BEGIN 0x2096
+#define mmCP_IB2_PREAMBLE_BEGIN_BASE_IDX 1
+#define mmCP_IB2_PREAMBLE_END 0x2097
+#define mmCP_IB2_PREAMBLE_END_BASE_IDX 1
+#define mmCP_CE_IB1_OFFSET 0x2098
+#define mmCP_CE_IB1_OFFSET_BASE_IDX 1
+#define mmCP_CE_IB2_OFFSET 0x2099
+#define mmCP_CE_IB2_OFFSET_BASE_IDX 1
+#define mmCP_CE_COUNTER 0x209a
+#define mmCP_CE_COUNTER_BASE_IDX 1
+#define mmCP_CE_RB_OFFSET 0x209b
+#define mmCP_CE_RB_OFFSET_BASE_IDX 1
+#define mmCP_CE_INIT_CMD_BUFSZ 0x20bd
+#define mmCP_CE_INIT_CMD_BUFSZ_BASE_IDX 1
+#define mmCP_CE_IB1_CMD_BUFSZ 0x20be
+#define mmCP_CE_IB1_CMD_BUFSZ_BASE_IDX 1
+#define mmCP_CE_IB2_CMD_BUFSZ 0x20bf
+#define mmCP_CE_IB2_CMD_BUFSZ_BASE_IDX 1
+#define mmCP_IB1_CMD_BUFSZ 0x20c0
+#define mmCP_IB1_CMD_BUFSZ_BASE_IDX 1
+#define mmCP_IB2_CMD_BUFSZ 0x20c1
+#define mmCP_IB2_CMD_BUFSZ_BASE_IDX 1
+#define mmCP_ST_CMD_BUFSZ 0x20c2
+#define mmCP_ST_CMD_BUFSZ_BASE_IDX 1
+#define mmCP_CE_INIT_BASE_LO 0x20c3
+#define mmCP_CE_INIT_BASE_LO_BASE_IDX 1
+#define mmCP_CE_INIT_BASE_HI 0x20c4
+#define mmCP_CE_INIT_BASE_HI_BASE_IDX 1
+#define mmCP_CE_INIT_BUFSZ 0x20c5
+#define mmCP_CE_INIT_BUFSZ_BASE_IDX 1
+#define mmCP_CE_IB1_BASE_LO 0x20c6
+#define mmCP_CE_IB1_BASE_LO_BASE_IDX 1
+#define mmCP_CE_IB1_BASE_HI 0x20c7
+#define mmCP_CE_IB1_BASE_HI_BASE_IDX 1
+#define mmCP_CE_IB1_BUFSZ 0x20c8
+#define mmCP_CE_IB1_BUFSZ_BASE_IDX 1
+#define mmCP_CE_IB2_BASE_LO 0x20c9
+#define mmCP_CE_IB2_BASE_LO_BASE_IDX 1
+#define mmCP_CE_IB2_BASE_HI 0x20ca
+#define mmCP_CE_IB2_BASE_HI_BASE_IDX 1
+#define mmCP_CE_IB2_BUFSZ 0x20cb
+#define mmCP_CE_IB2_BUFSZ_BASE_IDX 1
+#define mmCP_IB1_BASE_LO 0x20cc
+#define mmCP_IB1_BASE_LO_BASE_IDX 1
+#define mmCP_IB1_BASE_HI 0x20cd
+#define mmCP_IB1_BASE_HI_BASE_IDX 1
+#define mmCP_IB1_BUFSZ 0x20ce
+#define mmCP_IB1_BUFSZ_BASE_IDX 1
+#define mmCP_IB2_BASE_LO 0x20cf
+#define mmCP_IB2_BASE_LO_BASE_IDX 1
+#define mmCP_IB2_BASE_HI 0x20d0
+#define mmCP_IB2_BASE_HI_BASE_IDX 1
+#define mmCP_IB2_BUFSZ 0x20d1
+#define mmCP_IB2_BUFSZ_BASE_IDX 1
+#define mmCP_ST_BASE_LO 0x20d2
+#define mmCP_ST_BASE_LO_BASE_IDX 1
+#define mmCP_ST_BASE_HI 0x20d3
+#define mmCP_ST_BASE_HI_BASE_IDX 1
+#define mmCP_ST_BUFSZ 0x20d4
+#define mmCP_ST_BUFSZ_BASE_IDX 1
+#define mmCP_EOP_DONE_EVENT_CNTL 0x20d5
+#define mmCP_EOP_DONE_EVENT_CNTL_BASE_IDX 1
+#define mmCP_EOP_DONE_DATA_CNTL 0x20d6
+#define mmCP_EOP_DONE_DATA_CNTL_BASE_IDX 1
+#define mmCP_EOP_DONE_CNTX_ID 0x20d7
+#define mmCP_EOP_DONE_CNTX_ID_BASE_IDX 1
+#define mmCP_PFP_COMPLETION_STATUS 0x20ec
+#define mmCP_PFP_COMPLETION_STATUS_BASE_IDX 1
+#define mmCP_CE_COMPLETION_STATUS 0x20ed
+#define mmCP_CE_COMPLETION_STATUS_BASE_IDX 1
+#define mmCP_PRED_NOT_VISIBLE 0x20ee
+#define mmCP_PRED_NOT_VISIBLE_BASE_IDX 1
+#define mmCP_PFP_METADATA_BASE_ADDR 0x20f0
+#define mmCP_PFP_METADATA_BASE_ADDR_BASE_IDX 1
+#define mmCP_PFP_METADATA_BASE_ADDR_HI 0x20f1
+#define mmCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX 1
+#define mmCP_CE_METADATA_BASE_ADDR 0x20f2
+#define mmCP_CE_METADATA_BASE_ADDR_BASE_IDX 1
+#define mmCP_CE_METADATA_BASE_ADDR_HI 0x20f3
+#define mmCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX 1
+#define mmCP_DRAW_INDX_INDR_ADDR 0x20f4
+#define mmCP_DRAW_INDX_INDR_ADDR_BASE_IDX 1
+#define mmCP_DRAW_INDX_INDR_ADDR_HI 0x20f5
+#define mmCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX 1
+#define mmCP_DISPATCH_INDR_ADDR 0x20f6
+#define mmCP_DISPATCH_INDR_ADDR_BASE_IDX 1
+#define mmCP_DISPATCH_INDR_ADDR_HI 0x20f7
+#define mmCP_DISPATCH_INDR_ADDR_HI_BASE_IDX 1
+#define mmCP_INDEX_BASE_ADDR 0x20f8
+#define mmCP_INDEX_BASE_ADDR_BASE_IDX 1
+#define mmCP_INDEX_BASE_ADDR_HI 0x20f9
+#define mmCP_INDEX_BASE_ADDR_HI_BASE_IDX 1
+#define mmCP_INDEX_TYPE 0x20fa
+#define mmCP_INDEX_TYPE_BASE_IDX 1
+#define mmCP_GDS_BKUP_ADDR 0x20fb
+#define mmCP_GDS_BKUP_ADDR_BASE_IDX 1
+#define mmCP_GDS_BKUP_ADDR_HI 0x20fc
+#define mmCP_GDS_BKUP_ADDR_HI_BASE_IDX 1
+#define mmCP_SAMPLE_STATUS 0x20fd
+#define mmCP_SAMPLE_STATUS_BASE_IDX 1
+#define mmCP_ME_COHER_CNTL 0x20fe
+#define mmCP_ME_COHER_CNTL_BASE_IDX 1
+#define mmCP_ME_COHER_SIZE 0x20ff
+#define mmCP_ME_COHER_SIZE_BASE_IDX 1
+#define mmCP_ME_COHER_SIZE_HI 0x2100
+#define mmCP_ME_COHER_SIZE_HI_BASE_IDX 1
+#define mmCP_ME_COHER_BASE 0x2101
+#define mmCP_ME_COHER_BASE_BASE_IDX 1
+#define mmCP_ME_COHER_BASE_HI 0x2102
+#define mmCP_ME_COHER_BASE_HI_BASE_IDX 1
+#define mmCP_ME_COHER_STATUS 0x2103
+#define mmCP_ME_COHER_STATUS_BASE_IDX 1
+#define mmRLC_GPM_PERF_COUNT_0 0x2140
+#define mmRLC_GPM_PERF_COUNT_0_BASE_IDX 1
+#define mmRLC_GPM_PERF_COUNT_1 0x2141
+#define mmRLC_GPM_PERF_COUNT_1_BASE_IDX 1
+#define mmGRBM_GFX_INDEX 0x2200
+#define mmGRBM_GFX_INDEX_BASE_IDX 1
+#define mmVGT_GSVS_RING_SIZE 0x2241
+#define mmVGT_GSVS_RING_SIZE_BASE_IDX 1
+#define mmVGT_PRIMITIVE_TYPE 0x2242
+#define mmVGT_PRIMITIVE_TYPE_BASE_IDX 1
+#define mmVGT_INDEX_TYPE 0x2243
+#define mmVGT_INDEX_TYPE_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x2244
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x2245
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x2246
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x2247
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX 1
+#define mmVGT_MAX_VTX_INDX 0x2248
+#define mmVGT_MAX_VTX_INDX_BASE_IDX 1
+#define mmVGT_MIN_VTX_INDX 0x2249
+#define mmVGT_MIN_VTX_INDX_BASE_IDX 1
+#define mmVGT_INDX_OFFSET 0x224a
+#define mmVGT_INDX_OFFSET_BASE_IDX 1
+#define mmVGT_MULTI_PRIM_IB_RESET_EN 0x224b
+#define mmVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1
+#define mmVGT_NUM_INDICES 0x224c
+#define mmVGT_NUM_INDICES_BASE_IDX 1
+#define mmVGT_NUM_INSTANCES 0x224d
+#define mmVGT_NUM_INSTANCES_BASE_IDX 1
+#define mmVGT_TF_RING_SIZE 0x224e
+#define mmVGT_TF_RING_SIZE_BASE_IDX 1
+#define mmVGT_HS_OFFCHIP_PARAM 0x224f
+#define mmVGT_HS_OFFCHIP_PARAM_BASE_IDX 1
+#define mmVGT_TF_MEMORY_BASE 0x2250
+#define mmVGT_TF_MEMORY_BASE_BASE_IDX 1
+#define mmVGT_TF_MEMORY_BASE_HI 0x2251
+#define mmVGT_TF_MEMORY_BASE_HI_BASE_IDX 1
+#define mmWD_POS_BUF_BASE 0x2252
+#define mmWD_POS_BUF_BASE_BASE_IDX 1
+#define mmWD_POS_BUF_BASE_HI 0x2253
+#define mmWD_POS_BUF_BASE_HI_BASE_IDX 1
+#define mmWD_CNTL_SB_BUF_BASE 0x2254
+#define mmWD_CNTL_SB_BUF_BASE_BASE_IDX 1
+#define mmWD_CNTL_SB_BUF_BASE_HI 0x2255
+#define mmWD_CNTL_SB_BUF_BASE_HI_BASE_IDX 1
+#define mmWD_INDEX_BUF_BASE 0x2256
+#define mmWD_INDEX_BUF_BASE_BASE_IDX 1
+#define mmWD_INDEX_BUF_BASE_HI 0x2257
+#define mmWD_INDEX_BUF_BASE_HI_BASE_IDX 1
+#define mmIA_MULTI_VGT_PARAM 0x2258
+#define mmIA_MULTI_VGT_PARAM_BASE_IDX 1
+#define mmVGT_OBJECT_ID 0x2259
+#define mmVGT_OBJECT_ID_BASE_IDX 1
+#define mmVGT_INSTANCE_BASE_ID 0x225a
+#define mmVGT_INSTANCE_BASE_ID_BASE_IDX 1
+#define mmPA_SU_LINE_STIPPLE_VALUE 0x2280
+#define mmPA_SU_LINE_STIPPLE_VALUE_BASE_IDX 1
+#define mmPA_SC_LINE_STIPPLE_STATE 0x2281
+#define mmPA_SC_LINE_STIPPLE_STATE_BASE_IDX 1
+#define mmPA_SC_SCREEN_EXTENT_MIN_0 0x2284
+#define mmPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX 1
+#define mmPA_SC_SCREEN_EXTENT_MAX_0 0x2285
+#define mmPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX 1
+#define mmPA_SC_SCREEN_EXTENT_MIN_1 0x2286
+#define mmPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX 1
+#define mmPA_SC_SCREEN_EXTENT_MAX_1 0x228b
+#define mmPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX 1
+#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0x22a0
+#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX 1
+#define mmPA_SC_P3D_TRAP_SCREEN_H 0x22a1
+#define mmPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX 1
+#define mmPA_SC_P3D_TRAP_SCREEN_V 0x22a2
+#define mmPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX 1
+#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0x22a3
+#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1
+#define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0x22a4
+#define mmPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX 1
+#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0x22a8
+#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX 1
+#define mmPA_SC_HP3D_TRAP_SCREEN_H 0x22a9
+#define mmPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX 1
+#define mmPA_SC_HP3D_TRAP_SCREEN_V 0x22aa
+#define mmPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX 1
+#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0x22ab
+#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1
+#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0x22ac
+#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX 1
+#define mmPA_SC_TRAP_SCREEN_HV_EN 0x22b0
+#define mmPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX 1
+#define mmPA_SC_TRAP_SCREEN_H 0x22b1
+#define mmPA_SC_TRAP_SCREEN_H_BASE_IDX 1
+#define mmPA_SC_TRAP_SCREEN_V 0x22b2
+#define mmPA_SC_TRAP_SCREEN_V_BASE_IDX 1
+#define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0x22b3
+#define mmPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1
+#define mmPA_SC_TRAP_SCREEN_COUNT 0x22b4
+#define mmPA_SC_TRAP_SCREEN_COUNT_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_BASE 0x2330
+#define mmSQ_THREAD_TRACE_BASE_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_SIZE 0x2331
+#define mmSQ_THREAD_TRACE_SIZE_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_MASK 0x2332
+#define mmSQ_THREAD_TRACE_MASK_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_TOKEN_MASK 0x2333
+#define mmSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_PERF_MASK 0x2334
+#define mmSQ_THREAD_TRACE_PERF_MASK_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_CTRL 0x2335
+#define mmSQ_THREAD_TRACE_CTRL_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_MODE 0x2336
+#define mmSQ_THREAD_TRACE_MODE_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_BASE2 0x2337
+#define mmSQ_THREAD_TRACE_BASE2_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_TOKEN_MASK2 0x2338
+#define mmSQ_THREAD_TRACE_TOKEN_MASK2_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_WPTR 0x2339
+#define mmSQ_THREAD_TRACE_WPTR_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_STATUS 0x233a
+#define mmSQ_THREAD_TRACE_STATUS_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_HIWATER 0x233b
+#define mmSQ_THREAD_TRACE_HIWATER_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_CNTR 0x233c
+#define mmSQ_THREAD_TRACE_CNTR_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_USERDATA_0 0x2340
+#define mmSQ_THREAD_TRACE_USERDATA_0_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_USERDATA_1 0x2341
+#define mmSQ_THREAD_TRACE_USERDATA_1_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_USERDATA_2 0x2342
+#define mmSQ_THREAD_TRACE_USERDATA_2_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_USERDATA_3 0x2343
+#define mmSQ_THREAD_TRACE_USERDATA_3_BASE_IDX 1
+#define mmSQC_CACHES 0x2348
+#define mmSQC_CACHES_BASE_IDX 1
+#define mmSQC_WRITEBACK 0x2349
+#define mmSQC_WRITEBACK_BASE_IDX 1
+#define mmTA_CS_BC_BASE_ADDR 0x2380
+#define mmTA_CS_BC_BASE_ADDR_BASE_IDX 1
+#define mmTA_CS_BC_BASE_ADDR_HI 0x2381
+#define mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1
+#define mmTA_GRAD_ADJ_UCONFIG 0x2382
+#define mmTA_GRAD_ADJ_UCONFIG_BASE_IDX 1
+#define mmDB_OCCLUSION_COUNT0_LOW 0x23c0
+#define mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1
+#define mmDB_OCCLUSION_COUNT0_HI 0x23c1
+#define mmDB_OCCLUSION_COUNT0_HI_BASE_IDX 1
+#define mmDB_OCCLUSION_COUNT1_LOW 0x23c2
+#define mmDB_OCCLUSION_COUNT1_LOW_BASE_IDX 1
+#define mmDB_OCCLUSION_COUNT1_HI 0x23c3
+#define mmDB_OCCLUSION_COUNT1_HI_BASE_IDX 1
+#define mmDB_OCCLUSION_COUNT2_LOW 0x23c4
+#define mmDB_OCCLUSION_COUNT2_LOW_BASE_IDX 1
+#define mmDB_OCCLUSION_COUNT2_HI 0x23c5
+#define mmDB_OCCLUSION_COUNT2_HI_BASE_IDX 1
+#define mmDB_OCCLUSION_COUNT3_LOW 0x23c6
+#define mmDB_OCCLUSION_COUNT3_LOW_BASE_IDX 1
+#define mmDB_OCCLUSION_COUNT3_HI 0x23c7
+#define mmDB_OCCLUSION_COUNT3_HI_BASE_IDX 1
+#define mmDB_ZPASS_COUNT_LOW 0x23fe
+#define mmDB_ZPASS_COUNT_LOW_BASE_IDX 1
+#define mmDB_ZPASS_COUNT_HI 0x23ff
+#define mmDB_ZPASS_COUNT_HI_BASE_IDX 1
+#define mmGDS_RD_ADDR 0x2400
+#define mmGDS_RD_ADDR_BASE_IDX 1
+#define mmGDS_RD_DATA 0x2401
+#define mmGDS_RD_DATA_BASE_IDX 1
+#define mmGDS_RD_BURST_ADDR 0x2402
+#define mmGDS_RD_BURST_ADDR_BASE_IDX 1
+#define mmGDS_RD_BURST_COUNT 0x2403
+#define mmGDS_RD_BURST_COUNT_BASE_IDX 1
+#define mmGDS_RD_BURST_DATA 0x2404
+#define mmGDS_RD_BURST_DATA_BASE_IDX 1
+#define mmGDS_WR_ADDR 0x2405
+#define mmGDS_WR_ADDR_BASE_IDX 1
+#define mmGDS_WR_DATA 0x2406
+#define mmGDS_WR_DATA_BASE_IDX 1
+#define mmGDS_WR_BURST_ADDR 0x2407
+#define mmGDS_WR_BURST_ADDR_BASE_IDX 1
+#define mmGDS_WR_BURST_DATA 0x2408
+#define mmGDS_WR_BURST_DATA_BASE_IDX 1
+#define mmGDS_WRITE_COMPLETE 0x2409
+#define mmGDS_WRITE_COMPLETE_BASE_IDX 1
+#define mmGDS_ATOM_CNTL 0x240a
+#define mmGDS_ATOM_CNTL_BASE_IDX 1
+#define mmGDS_ATOM_COMPLETE 0x240b
+#define mmGDS_ATOM_COMPLETE_BASE_IDX 1
+#define mmGDS_ATOM_BASE 0x240c
+#define mmGDS_ATOM_BASE_BASE_IDX 1
+#define mmGDS_ATOM_SIZE 0x240d
+#define mmGDS_ATOM_SIZE_BASE_IDX 1
+#define mmGDS_ATOM_OFFSET0 0x240e
+#define mmGDS_ATOM_OFFSET0_BASE_IDX 1
+#define mmGDS_ATOM_OFFSET1 0x240f
+#define mmGDS_ATOM_OFFSET1_BASE_IDX 1
+#define mmGDS_ATOM_DST 0x2410
+#define mmGDS_ATOM_DST_BASE_IDX 1
+#define mmGDS_ATOM_OP 0x2411
+#define mmGDS_ATOM_OP_BASE_IDX 1
+#define mmGDS_ATOM_SRC0 0x2412
+#define mmGDS_ATOM_SRC0_BASE_IDX 1
+#define mmGDS_ATOM_SRC0_U 0x2413
+#define mmGDS_ATOM_SRC0_U_BASE_IDX 1
+#define mmGDS_ATOM_SRC1 0x2414
+#define mmGDS_ATOM_SRC1_BASE_IDX 1
+#define mmGDS_ATOM_SRC1_U 0x2415
+#define mmGDS_ATOM_SRC1_U_BASE_IDX 1
+#define mmGDS_ATOM_READ0 0x2416
+#define mmGDS_ATOM_READ0_BASE_IDX 1
+#define mmGDS_ATOM_READ0_U 0x2417
+#define mmGDS_ATOM_READ0_U_BASE_IDX 1
+#define mmGDS_ATOM_READ1 0x2418
+#define mmGDS_ATOM_READ1_BASE_IDX 1
+#define mmGDS_ATOM_READ1_U 0x2419
+#define mmGDS_ATOM_READ1_U_BASE_IDX 1
+#define mmGDS_GWS_RESOURCE_CNTL 0x241a
+#define mmGDS_GWS_RESOURCE_CNTL_BASE_IDX 1
+#define mmGDS_GWS_RESOURCE 0x241b
+#define mmGDS_GWS_RESOURCE_BASE_IDX 1
+#define mmGDS_GWS_RESOURCE_CNT 0x241c
+#define mmGDS_GWS_RESOURCE_CNT_BASE_IDX 1
+#define mmGDS_OA_CNTL 0x241d
+#define mmGDS_OA_CNTL_BASE_IDX 1
+#define mmGDS_OA_COUNTER 0x241e
+#define mmGDS_OA_COUNTER_BASE_IDX 1
+#define mmGDS_OA_ADDRESS 0x241f
+#define mmGDS_OA_ADDRESS_BASE_IDX 1
+#define mmGDS_OA_INCDEC 0x2420
+#define mmGDS_OA_INCDEC_BASE_IDX 1
+#define mmGDS_OA_RING_SIZE 0x2421
+#define mmGDS_OA_RING_SIZE_BASE_IDX 1
+#define mmSPI_CONFIG_CNTL 0x2440
+#define mmSPI_CONFIG_CNTL_BASE_IDX 1
+#define mmSPI_CONFIG_CNTL_1 0x2441
+#define mmSPI_CONFIG_CNTL_1_BASE_IDX 1
+#define mmSPI_CONFIG_CNTL_2 0x2442
+#define mmSPI_CONFIG_CNTL_2_BASE_IDX 1
+
+
+// addressBlock: gc_perfddec
+// base address: 0x34000
+#define mmCPG_PERFCOUNTER1_LO 0x3000
+#define mmCPG_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmCPG_PERFCOUNTER1_HI 0x3001
+#define mmCPG_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmCPG_PERFCOUNTER0_LO 0x3002
+#define mmCPG_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmCPG_PERFCOUNTER0_HI 0x3003
+#define mmCPG_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmCPC_PERFCOUNTER1_LO 0x3004
+#define mmCPC_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmCPC_PERFCOUNTER1_HI 0x3005
+#define mmCPC_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmCPC_PERFCOUNTER0_LO 0x3006
+#define mmCPC_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmCPC_PERFCOUNTER0_HI 0x3007
+#define mmCPC_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmCPF_PERFCOUNTER1_LO 0x3008
+#define mmCPF_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmCPF_PERFCOUNTER1_HI 0x3009
+#define mmCPF_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmCPF_PERFCOUNTER0_LO 0x300a
+#define mmCPF_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmCPF_PERFCOUNTER0_HI 0x300b
+#define mmCPF_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmCPF_LATENCY_STATS_DATA 0x300c
+#define mmCPF_LATENCY_STATS_DATA_BASE_IDX 1
+#define mmCPG_LATENCY_STATS_DATA 0x300d
+#define mmCPG_LATENCY_STATS_DATA_BASE_IDX 1
+#define mmCPC_LATENCY_STATS_DATA 0x300e
+#define mmCPC_LATENCY_STATS_DATA_BASE_IDX 1
+#define mmGRBM_PERFCOUNTER0_LO 0x3040
+#define mmGRBM_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmGRBM_PERFCOUNTER0_HI 0x3041
+#define mmGRBM_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmGRBM_PERFCOUNTER1_LO 0x3043
+#define mmGRBM_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmGRBM_PERFCOUNTER1_HI 0x3044
+#define mmGRBM_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmGRBM_SE0_PERFCOUNTER_LO 0x3045
+#define mmGRBM_SE0_PERFCOUNTER_LO_BASE_IDX 1
+#define mmGRBM_SE0_PERFCOUNTER_HI 0x3046
+#define mmGRBM_SE0_PERFCOUNTER_HI_BASE_IDX 1
+#define mmGRBM_SE1_PERFCOUNTER_LO 0x3047
+#define mmGRBM_SE1_PERFCOUNTER_LO_BASE_IDX 1
+#define mmGRBM_SE1_PERFCOUNTER_HI 0x3048
+#define mmGRBM_SE1_PERFCOUNTER_HI_BASE_IDX 1
+#define mmGRBM_SE2_PERFCOUNTER_LO 0x3049
+#define mmGRBM_SE2_PERFCOUNTER_LO_BASE_IDX 1
+#define mmGRBM_SE2_PERFCOUNTER_HI 0x304a
+#define mmGRBM_SE2_PERFCOUNTER_HI_BASE_IDX 1
+#define mmGRBM_SE3_PERFCOUNTER_LO 0x304b
+#define mmGRBM_SE3_PERFCOUNTER_LO_BASE_IDX 1
+#define mmGRBM_SE3_PERFCOUNTER_HI 0x304c
+#define mmGRBM_SE3_PERFCOUNTER_HI_BASE_IDX 1
+#define mmWD_PERFCOUNTER0_LO 0x3080
+#define mmWD_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmWD_PERFCOUNTER0_HI 0x3081
+#define mmWD_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmWD_PERFCOUNTER1_LO 0x3082
+#define mmWD_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmWD_PERFCOUNTER1_HI 0x3083
+#define mmWD_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmWD_PERFCOUNTER2_LO 0x3084
+#define mmWD_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmWD_PERFCOUNTER2_HI 0x3085
+#define mmWD_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmWD_PERFCOUNTER3_LO 0x3086
+#define mmWD_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmWD_PERFCOUNTER3_HI 0x3087
+#define mmWD_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmIA_PERFCOUNTER0_LO 0x3088
+#define mmIA_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmIA_PERFCOUNTER0_HI 0x3089
+#define mmIA_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmIA_PERFCOUNTER1_LO 0x308a
+#define mmIA_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmIA_PERFCOUNTER1_HI 0x308b
+#define mmIA_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmIA_PERFCOUNTER2_LO 0x308c
+#define mmIA_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmIA_PERFCOUNTER2_HI 0x308d
+#define mmIA_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmIA_PERFCOUNTER3_LO 0x308e
+#define mmIA_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmIA_PERFCOUNTER3_HI 0x308f
+#define mmIA_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmVGT_PERFCOUNTER0_LO 0x3090
+#define mmVGT_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmVGT_PERFCOUNTER0_HI 0x3091
+#define mmVGT_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmVGT_PERFCOUNTER1_LO 0x3092
+#define mmVGT_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmVGT_PERFCOUNTER1_HI 0x3093
+#define mmVGT_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmVGT_PERFCOUNTER2_LO 0x3094
+#define mmVGT_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmVGT_PERFCOUNTER2_HI 0x3095
+#define mmVGT_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmVGT_PERFCOUNTER3_LO 0x3096
+#define mmVGT_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmVGT_PERFCOUNTER3_HI 0x3097
+#define mmVGT_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER0_LO 0x3100
+#define mmPA_SU_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER0_HI 0x3101
+#define mmPA_SU_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER1_LO 0x3102
+#define mmPA_SU_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER1_HI 0x3103
+#define mmPA_SU_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER2_LO 0x3104
+#define mmPA_SU_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER2_HI 0x3105
+#define mmPA_SU_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER3_LO 0x3106
+#define mmPA_SU_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER3_HI 0x3107
+#define mmPA_SU_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER0_LO 0x3140
+#define mmPA_SC_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER0_HI 0x3141
+#define mmPA_SC_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER1_LO 0x3142
+#define mmPA_SC_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER1_HI 0x3143
+#define mmPA_SC_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER2_LO 0x3144
+#define mmPA_SC_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER2_HI 0x3145
+#define mmPA_SC_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER3_LO 0x3146
+#define mmPA_SC_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER3_HI 0x3147
+#define mmPA_SC_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER4_LO 0x3148
+#define mmPA_SC_PERFCOUNTER4_LO_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER4_HI 0x3149
+#define mmPA_SC_PERFCOUNTER4_HI_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER5_LO 0x314a
+#define mmPA_SC_PERFCOUNTER5_LO_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER5_HI 0x314b
+#define mmPA_SC_PERFCOUNTER5_HI_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER6_LO 0x314c
+#define mmPA_SC_PERFCOUNTER6_LO_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER6_HI 0x314d
+#define mmPA_SC_PERFCOUNTER6_HI_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER7_LO 0x314e
+#define mmPA_SC_PERFCOUNTER7_LO_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER7_HI 0x314f
+#define mmPA_SC_PERFCOUNTER7_HI_BASE_IDX 1
+#define mmSPI_PERFCOUNTER0_HI 0x3180
+#define mmSPI_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmSPI_PERFCOUNTER0_LO 0x3181
+#define mmSPI_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmSPI_PERFCOUNTER1_HI 0x3182
+#define mmSPI_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmSPI_PERFCOUNTER1_LO 0x3183
+#define mmSPI_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmSPI_PERFCOUNTER2_HI 0x3184
+#define mmSPI_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmSPI_PERFCOUNTER2_LO 0x3185
+#define mmSPI_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmSPI_PERFCOUNTER3_HI 0x3186
+#define mmSPI_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmSPI_PERFCOUNTER3_LO 0x3187
+#define mmSPI_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmSPI_PERFCOUNTER4_HI 0x3188
+#define mmSPI_PERFCOUNTER4_HI_BASE_IDX 1
+#define mmSPI_PERFCOUNTER4_LO 0x3189
+#define mmSPI_PERFCOUNTER4_LO_BASE_IDX 1
+#define mmSPI_PERFCOUNTER5_HI 0x318a
+#define mmSPI_PERFCOUNTER5_HI_BASE_IDX 1
+#define mmSPI_PERFCOUNTER5_LO 0x318b
+#define mmSPI_PERFCOUNTER5_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER0_LO 0x31c0
+#define mmSQ_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER0_HI 0x31c1
+#define mmSQ_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER1_LO 0x31c2
+#define mmSQ_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER1_HI 0x31c3
+#define mmSQ_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER2_LO 0x31c4
+#define mmSQ_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER2_HI 0x31c5
+#define mmSQ_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER3_LO 0x31c6
+#define mmSQ_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER3_HI 0x31c7
+#define mmSQ_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER4_LO 0x31c8
+#define mmSQ_PERFCOUNTER4_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER4_HI 0x31c9
+#define mmSQ_PERFCOUNTER4_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER5_LO 0x31ca
+#define mmSQ_PERFCOUNTER5_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER5_HI 0x31cb
+#define mmSQ_PERFCOUNTER5_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER6_LO 0x31cc
+#define mmSQ_PERFCOUNTER6_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER6_HI 0x31cd
+#define mmSQ_PERFCOUNTER6_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER7_LO 0x31ce
+#define mmSQ_PERFCOUNTER7_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER7_HI 0x31cf
+#define mmSQ_PERFCOUNTER7_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER8_LO 0x31d0
+#define mmSQ_PERFCOUNTER8_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER8_HI 0x31d1
+#define mmSQ_PERFCOUNTER8_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER9_LO 0x31d2
+#define mmSQ_PERFCOUNTER9_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER9_HI 0x31d3
+#define mmSQ_PERFCOUNTER9_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER10_LO 0x31d4
+#define mmSQ_PERFCOUNTER10_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER10_HI 0x31d5
+#define mmSQ_PERFCOUNTER10_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER11_LO 0x31d6
+#define mmSQ_PERFCOUNTER11_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER11_HI 0x31d7
+#define mmSQ_PERFCOUNTER11_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER12_LO 0x31d8
+#define mmSQ_PERFCOUNTER12_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER12_HI 0x31d9
+#define mmSQ_PERFCOUNTER12_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER13_LO 0x31da
+#define mmSQ_PERFCOUNTER13_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER13_HI 0x31db
+#define mmSQ_PERFCOUNTER13_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER14_LO 0x31dc
+#define mmSQ_PERFCOUNTER14_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER14_HI 0x31dd
+#define mmSQ_PERFCOUNTER14_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER15_LO 0x31de
+#define mmSQ_PERFCOUNTER15_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER15_HI 0x31df
+#define mmSQ_PERFCOUNTER15_HI_BASE_IDX 1
+#define mmSX_PERFCOUNTER0_LO 0x3240
+#define mmSX_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmSX_PERFCOUNTER0_HI 0x3241
+#define mmSX_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmSX_PERFCOUNTER1_LO 0x3242
+#define mmSX_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmSX_PERFCOUNTER1_HI 0x3243
+#define mmSX_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmSX_PERFCOUNTER2_LO 0x3244
+#define mmSX_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmSX_PERFCOUNTER2_HI 0x3245
+#define mmSX_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmSX_PERFCOUNTER3_LO 0x3246
+#define mmSX_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmSX_PERFCOUNTER3_HI 0x3247
+#define mmSX_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmGDS_PERFCOUNTER0_LO 0x3280
+#define mmGDS_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmGDS_PERFCOUNTER0_HI 0x3281
+#define mmGDS_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmGDS_PERFCOUNTER1_LO 0x3282
+#define mmGDS_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmGDS_PERFCOUNTER1_HI 0x3283
+#define mmGDS_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmGDS_PERFCOUNTER2_LO 0x3284
+#define mmGDS_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmGDS_PERFCOUNTER2_HI 0x3285
+#define mmGDS_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmGDS_PERFCOUNTER3_LO 0x3286
+#define mmGDS_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmGDS_PERFCOUNTER3_HI 0x3287
+#define mmGDS_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmTA_PERFCOUNTER0_LO 0x32c0
+#define mmTA_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmTA_PERFCOUNTER0_HI 0x32c1
+#define mmTA_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmTA_PERFCOUNTER1_LO 0x32c2
+#define mmTA_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmTA_PERFCOUNTER1_HI 0x32c3
+#define mmTA_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmTD_PERFCOUNTER0_LO 0x3300
+#define mmTD_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmTD_PERFCOUNTER0_HI 0x3301
+#define mmTD_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmTD_PERFCOUNTER1_LO 0x3302
+#define mmTD_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmTD_PERFCOUNTER1_HI 0x3303
+#define mmTD_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmTCP_PERFCOUNTER0_LO 0x3340
+#define mmTCP_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmTCP_PERFCOUNTER0_HI 0x3341
+#define mmTCP_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmTCP_PERFCOUNTER1_LO 0x3342
+#define mmTCP_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmTCP_PERFCOUNTER1_HI 0x3343
+#define mmTCP_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmTCP_PERFCOUNTER2_LO 0x3344
+#define mmTCP_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmTCP_PERFCOUNTER2_HI 0x3345
+#define mmTCP_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmTCP_PERFCOUNTER3_LO 0x3346
+#define mmTCP_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmTCP_PERFCOUNTER3_HI 0x3347
+#define mmTCP_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmTCC_PERFCOUNTER0_LO 0x3380
+#define mmTCC_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmTCC_PERFCOUNTER0_HI 0x3381
+#define mmTCC_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmTCC_PERFCOUNTER1_LO 0x3382
+#define mmTCC_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmTCC_PERFCOUNTER1_HI 0x3383
+#define mmTCC_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmTCC_PERFCOUNTER2_LO 0x3384
+#define mmTCC_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmTCC_PERFCOUNTER2_HI 0x3385
+#define mmTCC_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmTCC_PERFCOUNTER3_LO 0x3386
+#define mmTCC_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmTCC_PERFCOUNTER3_HI 0x3387
+#define mmTCC_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmTCA_PERFCOUNTER0_LO 0x3390
+#define mmTCA_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmTCA_PERFCOUNTER0_HI 0x3391
+#define mmTCA_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmTCA_PERFCOUNTER1_LO 0x3392
+#define mmTCA_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmTCA_PERFCOUNTER1_HI 0x3393
+#define mmTCA_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmTCA_PERFCOUNTER2_LO 0x3394
+#define mmTCA_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmTCA_PERFCOUNTER2_HI 0x3395
+#define mmTCA_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmTCA_PERFCOUNTER3_LO 0x3396
+#define mmTCA_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmTCA_PERFCOUNTER3_HI 0x3397
+#define mmTCA_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmCB_PERFCOUNTER0_LO 0x3406
+#define mmCB_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmCB_PERFCOUNTER0_HI 0x3407
+#define mmCB_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmCB_PERFCOUNTER1_LO 0x3408
+#define mmCB_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmCB_PERFCOUNTER1_HI 0x3409
+#define mmCB_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmCB_PERFCOUNTER2_LO 0x340a
+#define mmCB_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmCB_PERFCOUNTER2_HI 0x340b
+#define mmCB_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmCB_PERFCOUNTER3_LO 0x340c
+#define mmCB_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmCB_PERFCOUNTER3_HI 0x340d
+#define mmCB_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmDB_PERFCOUNTER0_LO 0x3440
+#define mmDB_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmDB_PERFCOUNTER0_HI 0x3441
+#define mmDB_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmDB_PERFCOUNTER1_LO 0x3442
+#define mmDB_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmDB_PERFCOUNTER1_HI 0x3443
+#define mmDB_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmDB_PERFCOUNTER2_LO 0x3444
+#define mmDB_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmDB_PERFCOUNTER2_HI 0x3445
+#define mmDB_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmDB_PERFCOUNTER3_LO 0x3446
+#define mmDB_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmDB_PERFCOUNTER3_HI 0x3447
+#define mmDB_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmRLC_PERFCOUNTER0_LO 0x3480
+#define mmRLC_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmRLC_PERFCOUNTER0_HI 0x3481
+#define mmRLC_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmRLC_PERFCOUNTER1_LO 0x3482
+#define mmRLC_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmRLC_PERFCOUNTER1_HI 0x3483
+#define mmRLC_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmRMI_PERFCOUNTER0_LO 0x34c0
+#define mmRMI_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmRMI_PERFCOUNTER0_HI 0x34c1
+#define mmRMI_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmRMI_PERFCOUNTER1_LO 0x34c2
+#define mmRMI_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmRMI_PERFCOUNTER1_HI 0x34c3
+#define mmRMI_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmRMI_PERFCOUNTER2_LO 0x34c4
+#define mmRMI_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmRMI_PERFCOUNTER2_HI 0x34c5
+#define mmRMI_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmRMI_PERFCOUNTER3_LO 0x34c6
+#define mmRMI_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmRMI_PERFCOUNTER3_HI 0x34c7
+#define mmRMI_PERFCOUNTER3_HI_BASE_IDX 1
+
+
+// addressBlock: gc_utcl2_atcl2pfcntrdec
+// base address: 0x35400
+#define mmATC_L2_PERFCOUNTER_LO 0x3500
+#define mmATC_L2_PERFCOUNTER_LO_BASE_IDX 1
+#define mmATC_L2_PERFCOUNTER_HI 0x3501
+#define mmATC_L2_PERFCOUNTER_HI_BASE_IDX 1
+
+
+// addressBlock: gc_utcl2_vml2prdec
+// base address: 0x35420
+#define mmMC_VM_L2_PERFCOUNTER_LO 0x3508
+#define mmMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1
+#define mmMC_VM_L2_PERFCOUNTER_HI 0x3509
+#define mmMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1
+
+
+// addressBlock: gc_perfsdec
+// base address: 0x36000
+#define mmCPG_PERFCOUNTER1_SELECT 0x3800
+#define mmCPG_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmCPG_PERFCOUNTER0_SELECT1 0x3801
+#define mmCPG_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmCPG_PERFCOUNTER0_SELECT 0x3802
+#define mmCPG_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmCPC_PERFCOUNTER1_SELECT 0x3803
+#define mmCPC_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmCPC_PERFCOUNTER0_SELECT1 0x3804
+#define mmCPC_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmCPF_PERFCOUNTER1_SELECT 0x3805
+#define mmCPF_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmCPF_PERFCOUNTER0_SELECT1 0x3806
+#define mmCPF_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmCPF_PERFCOUNTER0_SELECT 0x3807
+#define mmCPF_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmCP_PERFMON_CNTL 0x3808
+#define mmCP_PERFMON_CNTL_BASE_IDX 1
+#define mmCPC_PERFCOUNTER0_SELECT 0x3809
+#define mmCPC_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT 0x380a
+#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1
+#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT 0x380b
+#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1
+#define mmCPF_LATENCY_STATS_SELECT 0x380c
+#define mmCPF_LATENCY_STATS_SELECT_BASE_IDX 1
+#define mmCPG_LATENCY_STATS_SELECT 0x380d
+#define mmCPG_LATENCY_STATS_SELECT_BASE_IDX 1
+#define mmCPC_LATENCY_STATS_SELECT 0x380e
+#define mmCPC_LATENCY_STATS_SELECT_BASE_IDX 1
+#define mmCP_DRAW_OBJECT 0x3810
+#define mmCP_DRAW_OBJECT_BASE_IDX 1
+#define mmCP_DRAW_OBJECT_COUNTER 0x3811
+#define mmCP_DRAW_OBJECT_COUNTER_BASE_IDX 1
+#define mmCP_DRAW_WINDOW_MASK_HI 0x3812
+#define mmCP_DRAW_WINDOW_MASK_HI_BASE_IDX 1
+#define mmCP_DRAW_WINDOW_HI 0x3813
+#define mmCP_DRAW_WINDOW_HI_BASE_IDX 1
+#define mmCP_DRAW_WINDOW_LO 0x3814
+#define mmCP_DRAW_WINDOW_LO_BASE_IDX 1
+#define mmCP_DRAW_WINDOW_CNTL 0x3815
+#define mmCP_DRAW_WINDOW_CNTL_BASE_IDX 1
+#define mmGRBM_PERFCOUNTER0_SELECT 0x3840
+#define mmGRBM_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmGRBM_PERFCOUNTER1_SELECT 0x3841
+#define mmGRBM_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmGRBM_SE0_PERFCOUNTER_SELECT 0x3842
+#define mmGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX 1
+#define mmGRBM_SE1_PERFCOUNTER_SELECT 0x3843
+#define mmGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX 1
+#define mmGRBM_SE2_PERFCOUNTER_SELECT 0x3844
+#define mmGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX 1
+#define mmGRBM_SE3_PERFCOUNTER_SELECT 0x3845
+#define mmGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX 1
+#define mmWD_PERFCOUNTER0_SELECT 0x3880
+#define mmWD_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmWD_PERFCOUNTER1_SELECT 0x3881
+#define mmWD_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmWD_PERFCOUNTER2_SELECT 0x3882
+#define mmWD_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmWD_PERFCOUNTER3_SELECT 0x3883
+#define mmWD_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmIA_PERFCOUNTER0_SELECT 0x3884
+#define mmIA_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmIA_PERFCOUNTER1_SELECT 0x3885
+#define mmIA_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmIA_PERFCOUNTER2_SELECT 0x3886
+#define mmIA_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmIA_PERFCOUNTER3_SELECT 0x3887
+#define mmIA_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmIA_PERFCOUNTER0_SELECT1 0x3888
+#define mmIA_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmVGT_PERFCOUNTER0_SELECT 0x388c
+#define mmVGT_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmVGT_PERFCOUNTER1_SELECT 0x388d
+#define mmVGT_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmVGT_PERFCOUNTER2_SELECT 0x388e
+#define mmVGT_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmVGT_PERFCOUNTER3_SELECT 0x388f
+#define mmVGT_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmVGT_PERFCOUNTER0_SELECT1 0x3890
+#define mmVGT_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmVGT_PERFCOUNTER1_SELECT1 0x3891
+#define mmVGT_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define mmVGT_PERFCOUNTER_SEID_MASK 0x3894
+#define mmVGT_PERFCOUNTER_SEID_MASK_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER0_SELECT 0x3900
+#define mmPA_SU_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER0_SELECT1 0x3901
+#define mmPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER1_SELECT 0x3902
+#define mmPA_SU_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER1_SELECT1 0x3903
+#define mmPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER2_SELECT 0x3904
+#define mmPA_SU_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER3_SELECT 0x3905
+#define mmPA_SU_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER0_SELECT 0x3940
+#define mmPA_SC_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER0_SELECT1 0x3941
+#define mmPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER1_SELECT 0x3942
+#define mmPA_SC_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER2_SELECT 0x3943
+#define mmPA_SC_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER3_SELECT 0x3944
+#define mmPA_SC_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER4_SELECT 0x3945
+#define mmPA_SC_PERFCOUNTER4_SELECT_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER5_SELECT 0x3946
+#define mmPA_SC_PERFCOUNTER5_SELECT_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER6_SELECT 0x3947
+#define mmPA_SC_PERFCOUNTER6_SELECT_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER7_SELECT 0x3948
+#define mmPA_SC_PERFCOUNTER7_SELECT_BASE_IDX 1
+#define mmSPI_PERFCOUNTER0_SELECT 0x3980
+#define mmSPI_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmSPI_PERFCOUNTER1_SELECT 0x3981
+#define mmSPI_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmSPI_PERFCOUNTER2_SELECT 0x3982
+#define mmSPI_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmSPI_PERFCOUNTER3_SELECT 0x3983
+#define mmSPI_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmSPI_PERFCOUNTER0_SELECT1 0x3984
+#define mmSPI_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmSPI_PERFCOUNTER1_SELECT1 0x3985
+#define mmSPI_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define mmSPI_PERFCOUNTER2_SELECT1 0x3986
+#define mmSPI_PERFCOUNTER2_SELECT1_BASE_IDX 1
+#define mmSPI_PERFCOUNTER3_SELECT1 0x3987
+#define mmSPI_PERFCOUNTER3_SELECT1_BASE_IDX 1
+#define mmSPI_PERFCOUNTER4_SELECT 0x3988
+#define mmSPI_PERFCOUNTER4_SELECT_BASE_IDX 1
+#define mmSPI_PERFCOUNTER5_SELECT 0x3989
+#define mmSPI_PERFCOUNTER5_SELECT_BASE_IDX 1
+#define mmSPI_PERFCOUNTER_BINS 0x398a
+#define mmSPI_PERFCOUNTER_BINS_BASE_IDX 1
+#define mmSQ_PERFCOUNTER0_SELECT 0x39c0
+#define mmSQ_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER1_SELECT 0x39c1
+#define mmSQ_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER2_SELECT 0x39c2
+#define mmSQ_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER3_SELECT 0x39c3
+#define mmSQ_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER4_SELECT 0x39c4
+#define mmSQ_PERFCOUNTER4_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER5_SELECT 0x39c5
+#define mmSQ_PERFCOUNTER5_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER6_SELECT 0x39c6
+#define mmSQ_PERFCOUNTER6_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER7_SELECT 0x39c7
+#define mmSQ_PERFCOUNTER7_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER8_SELECT 0x39c8
+#define mmSQ_PERFCOUNTER8_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER9_SELECT 0x39c9
+#define mmSQ_PERFCOUNTER9_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER10_SELECT 0x39ca
+#define mmSQ_PERFCOUNTER10_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER11_SELECT 0x39cb
+#define mmSQ_PERFCOUNTER11_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER12_SELECT 0x39cc
+#define mmSQ_PERFCOUNTER12_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER13_SELECT 0x39cd
+#define mmSQ_PERFCOUNTER13_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER14_SELECT 0x39ce
+#define mmSQ_PERFCOUNTER14_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER15_SELECT 0x39cf
+#define mmSQ_PERFCOUNTER15_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER_CTRL 0x39e0
+#define mmSQ_PERFCOUNTER_CTRL_BASE_IDX 1
+#define mmSQ_PERFCOUNTER_MASK 0x39e1
+#define mmSQ_PERFCOUNTER_MASK_BASE_IDX 1
+#define mmSQ_PERFCOUNTER_CTRL2 0x39e2
+#define mmSQ_PERFCOUNTER_CTRL2_BASE_IDX 1
+#define mmSX_PERFCOUNTER0_SELECT 0x3a40
+#define mmSX_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmSX_PERFCOUNTER1_SELECT 0x3a41
+#define mmSX_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmSX_PERFCOUNTER2_SELECT 0x3a42
+#define mmSX_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmSX_PERFCOUNTER3_SELECT 0x3a43
+#define mmSX_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmSX_PERFCOUNTER0_SELECT1 0x3a44
+#define mmSX_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmSX_PERFCOUNTER1_SELECT1 0x3a45
+#define mmSX_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define mmGDS_PERFCOUNTER0_SELECT 0x3a80
+#define mmGDS_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmGDS_PERFCOUNTER1_SELECT 0x3a81
+#define mmGDS_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmGDS_PERFCOUNTER2_SELECT 0x3a82
+#define mmGDS_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmGDS_PERFCOUNTER3_SELECT 0x3a83
+#define mmGDS_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmGDS_PERFCOUNTER0_SELECT1 0x3a84
+#define mmGDS_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmTA_PERFCOUNTER0_SELECT 0x3ac0
+#define mmTA_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmTA_PERFCOUNTER0_SELECT1 0x3ac1
+#define mmTA_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmTA_PERFCOUNTER1_SELECT 0x3ac2
+#define mmTA_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmTD_PERFCOUNTER0_SELECT 0x3b00
+#define mmTD_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmTD_PERFCOUNTER0_SELECT1 0x3b01
+#define mmTD_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmTD_PERFCOUNTER1_SELECT 0x3b02
+#define mmTD_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmTCP_PERFCOUNTER0_SELECT 0x3b40
+#define mmTCP_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmTCP_PERFCOUNTER0_SELECT1 0x3b41
+#define mmTCP_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmTCP_PERFCOUNTER1_SELECT 0x3b42
+#define mmTCP_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmTCP_PERFCOUNTER1_SELECT1 0x3b43
+#define mmTCP_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define mmTCP_PERFCOUNTER2_SELECT 0x3b44
+#define mmTCP_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmTCP_PERFCOUNTER3_SELECT 0x3b45
+#define mmTCP_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmTCC_PERFCOUNTER0_SELECT 0x3b80
+#define mmTCC_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmTCC_PERFCOUNTER0_SELECT1 0x3b81
+#define mmTCC_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmTCC_PERFCOUNTER1_SELECT 0x3b82
+#define mmTCC_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmTCC_PERFCOUNTER1_SELECT1 0x3b83
+#define mmTCC_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define mmTCC_PERFCOUNTER2_SELECT 0x3b84
+#define mmTCC_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmTCC_PERFCOUNTER3_SELECT 0x3b85
+#define mmTCC_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmTCA_PERFCOUNTER0_SELECT 0x3b90
+#define mmTCA_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmTCA_PERFCOUNTER0_SELECT1 0x3b91
+#define mmTCA_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmTCA_PERFCOUNTER1_SELECT 0x3b92
+#define mmTCA_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmTCA_PERFCOUNTER1_SELECT1 0x3b93
+#define mmTCA_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define mmTCA_PERFCOUNTER2_SELECT 0x3b94
+#define mmTCA_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmTCA_PERFCOUNTER3_SELECT 0x3b95
+#define mmTCA_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmCB_PERFCOUNTER_FILTER 0x3c00
+#define mmCB_PERFCOUNTER_FILTER_BASE_IDX 1
+#define mmCB_PERFCOUNTER0_SELECT 0x3c01
+#define mmCB_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmCB_PERFCOUNTER0_SELECT1 0x3c02
+#define mmCB_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmCB_PERFCOUNTER1_SELECT 0x3c03
+#define mmCB_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmCB_PERFCOUNTER2_SELECT 0x3c04
+#define mmCB_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmCB_PERFCOUNTER3_SELECT 0x3c05
+#define mmCB_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmDB_PERFCOUNTER0_SELECT 0x3c40
+#define mmDB_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmDB_PERFCOUNTER0_SELECT1 0x3c41
+#define mmDB_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmDB_PERFCOUNTER1_SELECT 0x3c42
+#define mmDB_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmDB_PERFCOUNTER1_SELECT1 0x3c43
+#define mmDB_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define mmDB_PERFCOUNTER2_SELECT 0x3c44
+#define mmDB_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmDB_PERFCOUNTER3_SELECT 0x3c46
+#define mmDB_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmRLC_SPM_PERFMON_CNTL 0x3c80
+#define mmRLC_SPM_PERFMON_CNTL_BASE_IDX 1
+#define mmRLC_SPM_PERFMON_RING_BASE_LO 0x3c81
+#define mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 1
+#define mmRLC_SPM_PERFMON_RING_BASE_HI 0x3c82
+#define mmRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX 1
+#define mmRLC_SPM_PERFMON_RING_SIZE 0x3c83
+#define mmRLC_SPM_PERFMON_RING_SIZE_BASE_IDX 1
+#define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0x3c84
+#define mmRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX 1
+#define mmRLC_SPM_SE_MUXSEL_ADDR 0x3c85
+#define mmRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX 1
+#define mmRLC_SPM_SE_MUXSEL_DATA 0x3c86
+#define mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 1
+#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0x3c87
+#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0x3c88
+#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0x3c89
+#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0x3c8a
+#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0x3c8b
+#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0x3c8c
+#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0x3c8d
+#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0x3c8e
+#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0x3c90
+#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0x3c91
+#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0x3c92
+#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0x3c93
+#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0x3c94
+#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0x3c95
+#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0x3c96
+#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0x3c97
+#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0x3c98
+#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0x3c9a
+#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0x3c9b
+#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX 1
+#define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0x3c9c
+#define mmRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX 1
+#define mmRLC_SPM_RING_RDPTR 0x3c9d
+#define mmRLC_SPM_RING_RDPTR_BASE_IDX 1
+#define mmRLC_SPM_SEGMENT_THRESHOLD 0x3c9e
+#define mmRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX 1
+#define mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY 0x3c9f
+#define mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY 0x3ca0
+#define mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY 0x3ca1
+#define mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY 0x3ca2
+#define mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY 0x3ca3
+#define mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define mmRLC_PERFMON_CLK_CNTL 0x3cbf
+#define mmRLC_PERFMON_CLK_CNTL_BASE_IDX 1
+#define mmRLC_PERFMON_CNTL 0x3cc0
+#define mmRLC_PERFMON_CNTL_BASE_IDX 1
+#define mmRLC_PERFCOUNTER0_SELECT 0x3cc1
+#define mmRLC_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmRLC_PERFCOUNTER1_SELECT 0x3cc2
+#define mmRLC_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmRLC_GPU_IOV_PERF_CNT_CNTL 0x3cc3
+#define mmRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX 1
+#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR 0x3cc4
+#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX 1
+#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA 0x3cc5
+#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX 1
+#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR 0x3cc6
+#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX 1
+#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA 0x3cc7
+#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX 1
+#define mmRMI_PERFCOUNTER0_SELECT 0x3d00
+#define mmRMI_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmRMI_PERFCOUNTER0_SELECT1 0x3d01
+#define mmRMI_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmRMI_PERFCOUNTER1_SELECT 0x3d02
+#define mmRMI_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmRMI_PERFCOUNTER2_SELECT 0x3d03
+#define mmRMI_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmRMI_PERFCOUNTER2_SELECT1 0x3d04
+#define mmRMI_PERFCOUNTER2_SELECT1_BASE_IDX 1
+#define mmRMI_PERFCOUNTER3_SELECT 0x3d05
+#define mmRMI_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmRMI_PERF_COUNTER_CNTL 0x3d06
+#define mmRMI_PERF_COUNTER_CNTL_BASE_IDX 1
+
+
+// addressBlock: gc_utcl2_atcl2pfcntldec
+// base address: 0x37500
+#define mmATC_L2_PERFCOUNTER0_CFG 0x3d40
+#define mmATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1
+#define mmATC_L2_PERFCOUNTER1_CFG 0x3d41
+#define mmATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1
+#define mmATC_L2_PERFCOUNTER_RSLT_CNTL 0x3d42
+#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
+
+
+// addressBlock: gc_utcl2_vml2pldec
+// base address: 0x37530
+#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x3d4c
+#define mmMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1
+#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x3d4d
+#define mmMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1
+#define mmMC_VM_L2_PERFCOUNTER2_CFG 0x3d4e
+#define mmMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1
+#define mmMC_VM_L2_PERFCOUNTER3_CFG 0x3d4f
+#define mmMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1
+#define mmMC_VM_L2_PERFCOUNTER4_CFG 0x3d50
+#define mmMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1
+#define mmMC_VM_L2_PERFCOUNTER5_CFG 0x3d51
+#define mmMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1
+#define mmMC_VM_L2_PERFCOUNTER6_CFG 0x3d52
+#define mmMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1
+#define mmMC_VM_L2_PERFCOUNTER7_CFG 0x3d53
+#define mmMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1
+#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3d54
+#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
+
+
+// addressBlock: gc_rlcpdec
+// base address: 0x3b000
+#define mmRLC_CNTL 0x4c00
+#define mmRLC_CNTL_BASE_IDX 1
+#define mmRLC_STAT 0x4c04
+#define mmRLC_STAT_BASE_IDX 1
+#define mmRLC_SAFE_MODE 0x4c05
+#define mmRLC_SAFE_MODE_BASE_IDX 1
+#define mmRLC_MEM_SLP_CNTL 0x4c06
+#define mmRLC_MEM_SLP_CNTL_BASE_IDX 1
+#define mmSMU_RLC_RESPONSE 0x4c07
+#define mmSMU_RLC_RESPONSE_BASE_IDX 1
+#define mmRLC_RLCV_SAFE_MODE 0x4c08
+#define mmRLC_RLCV_SAFE_MODE_BASE_IDX 1
+#define mmRLC_SMU_SAFE_MODE 0x4c09
+#define mmRLC_SMU_SAFE_MODE_BASE_IDX 1
+#define mmRLC_RLCV_COMMAND 0x4c0a
+#define mmRLC_RLCV_COMMAND_BASE_IDX 1
+#define mmRLC_REFCLOCK_TIMESTAMP_LSB 0x4c0c
+#define mmRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX 1
+#define mmRLC_REFCLOCK_TIMESTAMP_MSB 0x4c0d
+#define mmRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX 1
+#define mmRLC_GPM_TIMER_INT_0 0x4c0e
+#define mmRLC_GPM_TIMER_INT_0_BASE_IDX 1
+#define mmRLC_GPM_TIMER_INT_1 0x4c0f
+#define mmRLC_GPM_TIMER_INT_1_BASE_IDX 1
+#define mmRLC_GPM_TIMER_INT_2 0x4c10
+#define mmRLC_GPM_TIMER_INT_2_BASE_IDX 1
+#define mmRLC_GPM_TIMER_CTRL 0x4c11
+#define mmRLC_GPM_TIMER_CTRL_BASE_IDX 1
+#define mmRLC_LB_CNTR_MAX 0x4c12
+#define mmRLC_LB_CNTR_MAX_BASE_IDX 1
+#define mmRLC_GPM_TIMER_STAT 0x4c13
+#define mmRLC_GPM_TIMER_STAT_BASE_IDX 1
+#define mmRLC_GPM_TIMER_INT_3 0x4c15
+#define mmRLC_GPM_TIMER_INT_3_BASE_IDX 1
+#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_1 0x4c16
+#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_1_BASE_IDX 1
+#define mmRLC_SERDES_NONCU_MASTER_BUSY_1 0x4c17
+#define mmRLC_SERDES_NONCU_MASTER_BUSY_1_BASE_IDX 1
+#define mmRLC_INT_STAT 0x4c18
+#define mmRLC_INT_STAT_BASE_IDX 1
+#define mmRLC_LB_CNTL 0x4c19
+#define mmRLC_LB_CNTL_BASE_IDX 1
+#define mmRLC_MGCG_CTRL 0x4c1a
+#define mmRLC_MGCG_CTRL_BASE_IDX 1
+#define mmRLC_LB_CNTR_INIT 0x4c1b
+#define mmRLC_LB_CNTR_INIT_BASE_IDX 1
+#define mmRLC_LOAD_BALANCE_CNTR 0x4c1c
+#define mmRLC_LOAD_BALANCE_CNTR_BASE_IDX 1
+#define mmRLC_JUMP_TABLE_RESTORE 0x4c1e
+#define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX 1
+#define mmRLC_PG_DELAY_2 0x4c1f
+#define mmRLC_PG_DELAY_2_BASE_IDX 1
+#define mmRLC_GPU_CLOCK_COUNT_LSB 0x4c24
+#define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1
+#define mmRLC_GPU_CLOCK_COUNT_MSB 0x4c25
+#define mmRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX 1
+#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0x4c26
+#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX 1
+#define mmRLC_UCODE_CNTL 0x4c27
+#define mmRLC_UCODE_CNTL_BASE_IDX 1
+#define mmRLC_GPM_THREAD_RESET 0x4c28
+#define mmRLC_GPM_THREAD_RESET_BASE_IDX 1
+#define mmRLC_GPM_CP_DMA_COMPLETE_T0 0x4c29
+#define mmRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX 1
+#define mmRLC_GPM_CP_DMA_COMPLETE_T1 0x4c2a
+#define mmRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX 1
+#define mmRLC_FIREWALL_VIOLATION 0x4c2b
+#define mmRLC_FIREWALL_VIOLATION_BASE_IDX 1
+#define mmRLC_GPM_STAT 0x4c40
+#define mmRLC_GPM_STAT_BASE_IDX 1
+#define mmRLC_GPU_CLOCK_32_RES_SEL 0x4c41
+#define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1
+#define mmRLC_GPU_CLOCK_32 0x4c42
+#define mmRLC_GPU_CLOCK_32_BASE_IDX 1
+#define mmRLC_PG_CNTL 0x4c43
+#define mmRLC_PG_CNTL_BASE_IDX 1
+#define mmRLC_GPM_THREAD_PRIORITY 0x4c44
+#define mmRLC_GPM_THREAD_PRIORITY_BASE_IDX 1
+#define mmRLC_GPM_THREAD_ENABLE 0x4c45
+#define mmRLC_GPM_THREAD_ENABLE_BASE_IDX 1
+#define mmRLC_CGTT_MGCG_OVERRIDE 0x4c48
+#define mmRLC_CGTT_MGCG_OVERRIDE_BASE_IDX 1
+#define mmRLC_CGCG_CGLS_CTRL 0x4c49
+#define mmRLC_CGCG_CGLS_CTRL_BASE_IDX 1
+#define mmRLC_CGCG_RAMP_CTRL 0x4c4a
+#define mmRLC_CGCG_RAMP_CTRL_BASE_IDX 1
+#define mmRLC_DYN_PG_STATUS 0x4c4b
+#define mmRLC_DYN_PG_STATUS_BASE_IDX 1
+#define mmRLC_DYN_PG_REQUEST 0x4c4c
+#define mmRLC_DYN_PG_REQUEST_BASE_IDX 1
+#define mmRLC_PG_DELAY 0x4c4d
+#define mmRLC_PG_DELAY_BASE_IDX 1
+#define mmRLC_CU_STATUS 0x4c4e
+#define mmRLC_CU_STATUS_BASE_IDX 1
+#define mmRLC_LB_INIT_CU_MASK 0x4c4f
+#define mmRLC_LB_INIT_CU_MASK_BASE_IDX 1
+#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x4c50
+#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK_BASE_IDX 1
+#define mmRLC_LB_PARAMS 0x4c51
+#define mmRLC_LB_PARAMS_BASE_IDX 1
+#define mmRLC_THREAD1_DELAY 0x4c52
+#define mmRLC_THREAD1_DELAY_BASE_IDX 1
+#define mmRLC_PG_ALWAYS_ON_CU_MASK 0x4c53
+#define mmRLC_PG_ALWAYS_ON_CU_MASK_BASE_IDX 1
+#define mmRLC_MAX_PG_CU 0x4c54
+#define mmRLC_MAX_PG_CU_BASE_IDX 1
+#define mmRLC_AUTO_PG_CTRL 0x4c55
+#define mmRLC_AUTO_PG_CTRL_BASE_IDX 1
+#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0x4c56
+#define mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX 1
+#define mmRLC_SERDES_RD_MASTER_INDEX 0x4c59
+#define mmRLC_SERDES_RD_MASTER_INDEX_BASE_IDX 1
+#define mmRLC_SERDES_RD_DATA_0 0x4c5a
+#define mmRLC_SERDES_RD_DATA_0_BASE_IDX 1
+#define mmRLC_SERDES_RD_DATA_1 0x4c5b
+#define mmRLC_SERDES_RD_DATA_1_BASE_IDX 1
+#define mmRLC_SERDES_RD_DATA_2 0x4c5c
+#define mmRLC_SERDES_RD_DATA_2_BASE_IDX 1
+#define mmRLC_SERDES_WR_CU_MASTER_MASK 0x4c5d
+#define mmRLC_SERDES_WR_CU_MASTER_MASK_BASE_IDX 1
+#define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0x4c5e
+#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_BASE_IDX 1
+#define mmRLC_SERDES_WR_CTRL 0x4c5f
+#define mmRLC_SERDES_WR_CTRL_BASE_IDX 1
+#define mmRLC_SERDES_WR_DATA 0x4c60
+#define mmRLC_SERDES_WR_DATA_BASE_IDX 1
+#define mmRLC_SERDES_CU_MASTER_BUSY 0x4c61
+#define mmRLC_SERDES_CU_MASTER_BUSY_BASE_IDX 1
+#define mmRLC_SERDES_NONCU_MASTER_BUSY 0x4c62
+#define mmRLC_SERDES_NONCU_MASTER_BUSY_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_0 0x4c63
+#define mmRLC_GPM_GENERAL_0_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_1 0x4c64
+#define mmRLC_GPM_GENERAL_1_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_2 0x4c65
+#define mmRLC_GPM_GENERAL_2_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_3 0x4c66
+#define mmRLC_GPM_GENERAL_3_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_4 0x4c67
+#define mmRLC_GPM_GENERAL_4_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_5 0x4c68
+#define mmRLC_GPM_GENERAL_5_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_6 0x4c69
+#define mmRLC_GPM_GENERAL_6_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_7 0x4c6a
+#define mmRLC_GPM_GENERAL_7_BASE_IDX 1
+#define mmRLC_GPM_SCRATCH_ADDR 0x4c6c
+#define mmRLC_GPM_SCRATCH_ADDR_BASE_IDX 1
+#define mmRLC_GPM_SCRATCH_DATA 0x4c6d
+#define mmRLC_GPM_SCRATCH_DATA_BASE_IDX 1
+#define mmRLC_STATIC_PG_STATUS 0x4c6e
+#define mmRLC_STATIC_PG_STATUS_BASE_IDX 1
+#define mmRLC_SPM_MC_CNTL 0x4c71
+#define mmRLC_SPM_MC_CNTL_BASE_IDX 1
+#define mmRLC_SPM_INT_CNTL 0x4c72
+#define mmRLC_SPM_INT_CNTL_BASE_IDX 1
+#define mmRLC_SPM_INT_STATUS 0x4c73
+#define mmRLC_SPM_INT_STATUS_BASE_IDX 1
+#define mmRLC_SMU_MESSAGE 0x4c76
+#define mmRLC_SMU_MESSAGE_BASE_IDX 1
+#define mmRLC_GPM_LOG_SIZE 0x4c77
+#define mmRLC_GPM_LOG_SIZE_BASE_IDX 1
+#define mmRLC_PG_DELAY_3 0x4c78
+#define mmRLC_PG_DELAY_3_BASE_IDX 1
+#define mmRLC_GPR_REG1 0x4c79
+#define mmRLC_GPR_REG1_BASE_IDX 1
+#define mmRLC_GPR_REG2 0x4c7a
+#define mmRLC_GPR_REG2_BASE_IDX 1
+#define mmRLC_GPM_LOG_CONT 0x4c7b
+#define mmRLC_GPM_LOG_CONT_BASE_IDX 1
+#define mmRLC_GPM_INT_DISABLE_TH0 0x4c7c
+#define mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX 1
+#define mmRLC_GPM_INT_DISABLE_TH1 0x4c7d
+#define mmRLC_GPM_INT_DISABLE_TH1_BASE_IDX 1
+#define mmRLC_GPM_INT_FORCE_TH0 0x4c7e
+#define mmRLC_GPM_INT_FORCE_TH0_BASE_IDX 1
+#define mmRLC_GPM_INT_FORCE_TH1 0x4c7f
+#define mmRLC_GPM_INT_FORCE_TH1_BASE_IDX 1
+#define mmRLC_SRM_CNTL 0x4c80
+#define mmRLC_SRM_CNTL_BASE_IDX 1
+#define mmRLC_SRM_ARAM_ADDR 0x4c83
+#define mmRLC_SRM_ARAM_ADDR_BASE_IDX 1
+#define mmRLC_SRM_ARAM_DATA 0x4c84
+#define mmRLC_SRM_ARAM_DATA_BASE_IDX 1
+#define mmRLC_SRM_DRAM_ADDR 0x4c85
+#define mmRLC_SRM_DRAM_ADDR_BASE_IDX 1
+#define mmRLC_SRM_DRAM_DATA 0x4c86
+#define mmRLC_SRM_DRAM_DATA_BASE_IDX 1
+#define mmRLC_SRM_GPM_COMMAND 0x4c87
+#define mmRLC_SRM_GPM_COMMAND_BASE_IDX 1
+#define mmRLC_SRM_GPM_COMMAND_STATUS 0x4c88
+#define mmRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX 1
+#define mmRLC_SRM_RLCV_COMMAND 0x4c89
+#define mmRLC_SRM_RLCV_COMMAND_BASE_IDX 1
+#define mmRLC_SRM_RLCV_COMMAND_STATUS 0x4c8a
+#define mmRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b
+#define mmRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_ADDR_1 0x4c8c
+#define mmRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_ADDR_2 0x4c8d
+#define mmRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_ADDR_3 0x4c8e
+#define mmRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_ADDR_4 0x4c8f
+#define mmRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_ADDR_5 0x4c90
+#define mmRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_ADDR_6 0x4c91
+#define mmRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_ADDR_7 0x4c92
+#define mmRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_DATA_0 0x4c93
+#define mmRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_DATA_1 0x4c94
+#define mmRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_DATA_2 0x4c95
+#define mmRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_DATA_3 0x4c96
+#define mmRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_DATA_4 0x4c97
+#define mmRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_DATA_5 0x4c98
+#define mmRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_DATA_6 0x4c99
+#define mmRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_DATA_7 0x4c9a
+#define mmRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX 1
+#define mmRLC_SRM_STAT 0x4c9b
+#define mmRLC_SRM_STAT_BASE_IDX 1
+#define mmRLC_SRM_GPM_ABORT 0x4c9c
+#define mmRLC_SRM_GPM_ABORT_BASE_IDX 1
+#define mmRLC_CSIB_ADDR_LO 0x4ca2
+#define mmRLC_CSIB_ADDR_LO_BASE_IDX 1
+#define mmRLC_CSIB_ADDR_HI 0x4ca3
+#define mmRLC_CSIB_ADDR_HI_BASE_IDX 1
+#define mmRLC_CSIB_LENGTH 0x4ca4
+#define mmRLC_CSIB_LENGTH_BASE_IDX 1
+#define mmRLC_SMU_COMMAND 0x4ca9
+#define mmRLC_SMU_COMMAND_BASE_IDX 1
+#define mmRLC_CP_SCHEDULERS 0x4caa
+#define mmRLC_CP_SCHEDULERS_BASE_IDX 1
+#define mmRLC_SMU_ARGUMENT_1 0x4cab
+#define mmRLC_SMU_ARGUMENT_1_BASE_IDX 1
+#define mmRLC_SMU_ARGUMENT_2 0x4cac
+#define mmRLC_SMU_ARGUMENT_2_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_8 0x4cad
+#define mmRLC_GPM_GENERAL_8_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_9 0x4cae
+#define mmRLC_GPM_GENERAL_9_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_10 0x4caf
+#define mmRLC_GPM_GENERAL_10_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_11 0x4cb0
+#define mmRLC_GPM_GENERAL_11_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_12 0x4cb1
+#define mmRLC_GPM_GENERAL_12_BASE_IDX 1
+#define mmRLC_GPM_UTCL1_CNTL_0 0x4cb2
+#define mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX 1
+#define mmRLC_GPM_UTCL1_CNTL_1 0x4cb3
+#define mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1
+#define mmRLC_GPM_UTCL1_CNTL_2 0x4cb4
+#define mmRLC_GPM_UTCL1_CNTL_2_BASE_IDX 1
+#define mmRLC_SPM_UTCL1_CNTL 0x4cb5
+#define mmRLC_SPM_UTCL1_CNTL_BASE_IDX 1
+#define mmRLC_UTCL1_STATUS_2 0x4cb6
+#define mmRLC_UTCL1_STATUS_2_BASE_IDX 1
+#define mmRLC_LB_THR_CONFIG_2 0x4cb8
+#define mmRLC_LB_THR_CONFIG_2_BASE_IDX 1
+#define mmRLC_LB_THR_CONFIG_3 0x4cb9
+#define mmRLC_LB_THR_CONFIG_3_BASE_IDX 1
+#define mmRLC_LB_THR_CONFIG_4 0x4cba
+#define mmRLC_LB_THR_CONFIG_4_BASE_IDX 1
+#define mmRLC_SPM_UTCL1_ERROR_1 0x4cbc
+#define mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX 1
+#define mmRLC_SPM_UTCL1_ERROR_2 0x4cbd
+#define mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX 1
+#define mmRLC_GPM_UTCL1_TH0_ERROR_1 0x4cbe
+#define mmRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX 1
+#define mmRLC_LB_THR_CONFIG_1 0x4cbf
+#define mmRLC_LB_THR_CONFIG_1_BASE_IDX 1
+#define mmRLC_GPM_UTCL1_TH0_ERROR_2 0x4cc0
+#define mmRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX 1
+#define mmRLC_GPM_UTCL1_TH1_ERROR_1 0x4cc1
+#define mmRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX 1
+#define mmRLC_GPM_UTCL1_TH1_ERROR_2 0x4cc2
+#define mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX 1
+#define mmRLC_GPM_UTCL1_TH2_ERROR_1 0x4cc3
+#define mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX 1
+#define mmRLC_GPM_UTCL1_TH2_ERROR_2 0x4cc4
+#define mmRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX 1
+#define mmRLC_CGCG_CGLS_CTRL_3D 0x4cc5
+#define mmRLC_CGCG_CGLS_CTRL_3D_BASE_IDX 1
+#define mmRLC_CGCG_RAMP_CTRL_3D 0x4cc6
+#define mmRLC_CGCG_RAMP_CTRL_3D_BASE_IDX 1
+#define mmRLC_SEMAPHORE_0 0x4cc7
+#define mmRLC_SEMAPHORE_0_BASE_IDX 1
+#define mmRLC_SEMAPHORE_1 0x4cc8
+#define mmRLC_SEMAPHORE_1_BASE_IDX 1
+#define mmRLC_CP_EOF_INT 0x4cca
+#define mmRLC_CP_EOF_INT_BASE_IDX 1
+#define mmRLC_CP_EOF_INT_CNT 0x4ccb
+#define mmRLC_CP_EOF_INT_CNT_BASE_IDX 1
+#define mmRLC_SPARE_INT 0x4ccc
+#define mmRLC_SPARE_INT_BASE_IDX 1
+#define mmRLC_PREWALKER_UTCL1_CNTL 0x4ccd
+#define mmRLC_PREWALKER_UTCL1_CNTL_BASE_IDX 1
+#define mmRLC_PREWALKER_UTCL1_TRIG 0x4cce
+#define mmRLC_PREWALKER_UTCL1_TRIG_BASE_IDX 1
+#define mmRLC_PREWALKER_UTCL1_ADDR_LSB 0x4ccf
+#define mmRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX 1
+#define mmRLC_PREWALKER_UTCL1_ADDR_MSB 0x4cd0
+#define mmRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX 1
+#define mmRLC_PREWALKER_UTCL1_SIZE_LSB 0x4cd1
+#define mmRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX 1
+#define mmRLC_PREWALKER_UTCL1_SIZE_MSB 0x4cd2
+#define mmRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX 1
+#define mmRLC_DSM_TRIG 0x4cd3
+#define mmRLC_DSM_TRIG_BASE_IDX 1
+#define mmRLC_UTCL1_STATUS 0x4cd4
+#define mmRLC_UTCL1_STATUS_BASE_IDX 1
+#define mmRLC_R2I_CNTL_0 0x4cd5
+#define mmRLC_R2I_CNTL_0_BASE_IDX 1
+#define mmRLC_R2I_CNTL_1 0x4cd6
+#define mmRLC_R2I_CNTL_1_BASE_IDX 1
+#define mmRLC_R2I_CNTL_2 0x4cd7
+#define mmRLC_R2I_CNTL_2_BASE_IDX 1
+#define mmRLC_R2I_CNTL_3 0x4cd8
+#define mmRLC_R2I_CNTL_3_BASE_IDX 1
+#define mmRLC_UTCL2_CNTL 0x4cd9
+#define mmRLC_UTCL2_CNTL_BASE_IDX 1
+#define mmRLC_LBPW_CU_STAT 0x4cda
+#define mmRLC_LBPW_CU_STAT_BASE_IDX 1
+#define mmRLC_DS_CNTL 0x4cdb
+#define mmRLC_DS_CNTL_BASE_IDX 1
+#define mmRLC_RLCV_SPARE_INT 0x4f30
+#define mmRLC_RLCV_SPARE_INT_BASE_IDX 1
+
+
+// addressBlock: gc_pwrdec
+// base address: 0x3c000
+#define mmCGTS_SM_CTRL_REG 0x5000
+#define mmCGTS_SM_CTRL_REG_BASE_IDX 1
+#define mmCGTS_RD_CTRL_REG 0x5001
+#define mmCGTS_RD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_RD_REG 0x5002
+#define mmCGTS_RD_REG_BASE_IDX 1
+#define mmCGTS_TCC_DISABLE 0x5003
+#define mmCGTS_TCC_DISABLE_BASE_IDX 1
+#define mmCGTS_USER_TCC_DISABLE 0x5004
+#define mmCGTS_USER_TCC_DISABLE_BASE_IDX 1
+#define mmCGTS_CU0_SP0_CTRL_REG 0x5008
+#define mmCGTS_CU0_SP0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU0_LDS_SQ_CTRL_REG 0x5009
+#define mmCGTS_CU0_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU0_TA_SQC_CTRL_REG 0x500a
+#define mmCGTS_CU0_TA_SQC_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU0_SP1_CTRL_REG 0x500b
+#define mmCGTS_CU0_SP1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU0_TD_TCP_CTRL_REG 0x500c
+#define mmCGTS_CU0_TD_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU1_SP0_CTRL_REG 0x500d
+#define mmCGTS_CU1_SP0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU1_LDS_SQ_CTRL_REG 0x500e
+#define mmCGTS_CU1_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU1_TA_SQC_CTRL_REG 0x500f
+#define mmCGTS_CU1_TA_SQC_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU1_SP1_CTRL_REG 0x5010
+#define mmCGTS_CU1_SP1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU1_TD_TCP_CTRL_REG 0x5011
+#define mmCGTS_CU1_TD_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU2_SP0_CTRL_REG 0x5012
+#define mmCGTS_CU2_SP0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU2_LDS_SQ_CTRL_REG 0x5013
+#define mmCGTS_CU2_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU2_TA_SQC_CTRL_REG 0x5014
+#define mmCGTS_CU2_TA_SQC_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU2_SP1_CTRL_REG 0x5015
+#define mmCGTS_CU2_SP1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU2_TD_TCP_CTRL_REG 0x5016
+#define mmCGTS_CU2_TD_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU3_SP0_CTRL_REG 0x5017
+#define mmCGTS_CU3_SP0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU3_LDS_SQ_CTRL_REG 0x5018
+#define mmCGTS_CU3_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU3_TA_SQC_CTRL_REG 0x5019
+#define mmCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU3_SP1_CTRL_REG 0x501a
+#define mmCGTS_CU3_SP1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU3_TD_TCP_CTRL_REG 0x501b
+#define mmCGTS_CU3_TD_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU4_SP0_CTRL_REG 0x501c
+#define mmCGTS_CU4_SP0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU4_LDS_SQ_CTRL_REG 0x501d
+#define mmCGTS_CU4_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU4_TA_SQC_CTRL_REG 0x501e
+#define mmCGTS_CU4_TA_SQC_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU4_SP1_CTRL_REG 0x501f
+#define mmCGTS_CU4_SP1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU4_TD_TCP_CTRL_REG 0x5020
+#define mmCGTS_CU4_TD_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU5_SP0_CTRL_REG 0x5021
+#define mmCGTS_CU5_SP0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU5_LDS_SQ_CTRL_REG 0x5022
+#define mmCGTS_CU5_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU5_TA_SQC_CTRL_REG 0x5023
+#define mmCGTS_CU5_TA_SQC_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU5_SP1_CTRL_REG 0x5024
+#define mmCGTS_CU5_SP1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU5_TD_TCP_CTRL_REG 0x5025
+#define mmCGTS_CU5_TD_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU6_SP0_CTRL_REG 0x5026
+#define mmCGTS_CU6_SP0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU6_LDS_SQ_CTRL_REG 0x5027
+#define mmCGTS_CU6_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU6_TA_SQC_CTRL_REG 0x5028
+#define mmCGTS_CU6_TA_SQC_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU6_SP1_CTRL_REG 0x5029
+#define mmCGTS_CU6_SP1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU6_TD_TCP_CTRL_REG 0x502a
+#define mmCGTS_CU6_TD_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU7_SP0_CTRL_REG 0x502b
+#define mmCGTS_CU7_SP0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU7_LDS_SQ_CTRL_REG 0x502c
+#define mmCGTS_CU7_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU7_TA_SQC_CTRL_REG 0x502d
+#define mmCGTS_CU7_TA_SQC_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU7_SP1_CTRL_REG 0x502e
+#define mmCGTS_CU7_SP1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU7_TD_TCP_CTRL_REG 0x502f
+#define mmCGTS_CU7_TD_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU8_SP0_CTRL_REG 0x5030
+#define mmCGTS_CU8_SP0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU8_LDS_SQ_CTRL_REG 0x5031
+#define mmCGTS_CU8_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU8_TA_SQC_CTRL_REG 0x5032
+#define mmCGTS_CU8_TA_SQC_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU8_SP1_CTRL_REG 0x5033
+#define mmCGTS_CU8_SP1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU8_TD_TCP_CTRL_REG 0x5034
+#define mmCGTS_CU8_TD_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU9_SP0_CTRL_REG 0x5035
+#define mmCGTS_CU9_SP0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU9_LDS_SQ_CTRL_REG 0x5036
+#define mmCGTS_CU9_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU9_TA_SQC_CTRL_REG 0x5037
+#define mmCGTS_CU9_TA_SQC_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU9_SP1_CTRL_REG 0x5038
+#define mmCGTS_CU9_SP1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU9_TD_TCP_CTRL_REG 0x5039
+#define mmCGTS_CU9_TD_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU10_SP0_CTRL_REG 0x503a
+#define mmCGTS_CU10_SP0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU10_LDS_SQ_CTRL_REG 0x503b
+#define mmCGTS_CU10_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU10_TA_SQC_CTRL_REG 0x503c
+#define mmCGTS_CU10_TA_SQC_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU10_SP1_CTRL_REG 0x503d
+#define mmCGTS_CU10_SP1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU10_TD_TCP_CTRL_REG 0x503e
+#define mmCGTS_CU10_TD_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU11_SP0_CTRL_REG 0x503f
+#define mmCGTS_CU11_SP0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU11_LDS_SQ_CTRL_REG 0x5040
+#define mmCGTS_CU11_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU11_TA_SQC_CTRL_REG 0x5041
+#define mmCGTS_CU11_TA_SQC_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU11_SP1_CTRL_REG 0x5042
+#define mmCGTS_CU11_SP1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU11_TD_TCP_CTRL_REG 0x5043
+#define mmCGTS_CU11_TD_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU12_SP0_CTRL_REG 0x5044
+#define mmCGTS_CU12_SP0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU12_LDS_SQ_CTRL_REG 0x5045
+#define mmCGTS_CU12_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU12_TA_SQC_CTRL_REG 0x5046
+#define mmCGTS_CU12_TA_SQC_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU12_SP1_CTRL_REG 0x5047
+#define mmCGTS_CU12_SP1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU12_TD_TCP_CTRL_REG 0x5048
+#define mmCGTS_CU12_TD_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU13_SP0_CTRL_REG 0x5049
+#define mmCGTS_CU13_SP0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU13_LDS_SQ_CTRL_REG 0x504a
+#define mmCGTS_CU13_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU13_TA_SQC_CTRL_REG 0x504b
+#define mmCGTS_CU13_TA_SQC_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU13_SP1_CTRL_REG 0x504c
+#define mmCGTS_CU13_SP1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU13_TD_TCP_CTRL_REG 0x504d
+#define mmCGTS_CU13_TD_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU14_SP0_CTRL_REG 0x504e
+#define mmCGTS_CU14_SP0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU14_LDS_SQ_CTRL_REG 0x504f
+#define mmCGTS_CU14_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU14_TA_SQC_CTRL_REG 0x5050
+#define mmCGTS_CU14_TA_SQC_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU14_SP1_CTRL_REG 0x5051
+#define mmCGTS_CU14_SP1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU14_TD_TCP_CTRL_REG 0x5052
+#define mmCGTS_CU14_TD_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU15_SP0_CTRL_REG 0x5053
+#define mmCGTS_CU15_SP0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU15_LDS_SQ_CTRL_REG 0x5054
+#define mmCGTS_CU15_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU15_TA_SQC_CTRL_REG 0x5055
+#define mmCGTS_CU15_TA_SQC_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU15_SP1_CTRL_REG 0x5056
+#define mmCGTS_CU15_SP1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU15_TD_TCP_CTRL_REG 0x5057
+#define mmCGTS_CU15_TD_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU0_TCPI_CTRL_REG 0x5058
+#define mmCGTS_CU0_TCPI_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU1_TCPI_CTRL_REG 0x5059
+#define mmCGTS_CU1_TCPI_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU2_TCPI_CTRL_REG 0x505a
+#define mmCGTS_CU2_TCPI_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU3_TCPI_CTRL_REG 0x505b
+#define mmCGTS_CU3_TCPI_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU4_TCPI_CTRL_REG 0x505c
+#define mmCGTS_CU4_TCPI_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU5_TCPI_CTRL_REG 0x505d
+#define mmCGTS_CU5_TCPI_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU6_TCPI_CTRL_REG 0x505e
+#define mmCGTS_CU6_TCPI_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU7_TCPI_CTRL_REG 0x505f
+#define mmCGTS_CU7_TCPI_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU8_TCPI_CTRL_REG 0x5060
+#define mmCGTS_CU8_TCPI_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU9_TCPI_CTRL_REG 0x5061
+#define mmCGTS_CU9_TCPI_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU10_TCPI_CTRL_REG 0x5062
+#define mmCGTS_CU10_TCPI_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU11_TCPI_CTRL_REG 0x5063
+#define mmCGTS_CU11_TCPI_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU12_TCPI_CTRL_REG 0x5064
+#define mmCGTS_CU12_TCPI_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU13_TCPI_CTRL_REG 0x5065
+#define mmCGTS_CU13_TCPI_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU14_TCPI_CTRL_REG 0x5066
+#define mmCGTS_CU14_TCPI_CTRL_REG_BASE_IDX 1
+#define mmCGTS_CU15_TCPI_CTRL_REG 0x5067
+#define mmCGTS_CU15_TCPI_CTRL_REG_BASE_IDX 1
+#define mmCGTT_SPI_CLK_CTRL 0x5080
+#define mmCGTT_SPI_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_PC_CLK_CTRL 0x5081
+#define mmCGTT_PC_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_BCI_CLK_CTRL 0x5082
+#define mmCGTT_BCI_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_VGT_CLK_CTRL 0x5084
+#define mmCGTT_VGT_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_IA_CLK_CTRL 0x5085
+#define mmCGTT_IA_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_WD_CLK_CTRL 0x5086
+#define mmCGTT_WD_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_PA_CLK_CTRL 0x5088
+#define mmCGTT_PA_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_SC_CLK_CTRL0 0x5089
+#define mmCGTT_SC_CLK_CTRL0_BASE_IDX 1
+#define mmCGTT_SC_CLK_CTRL1 0x508a
+#define mmCGTT_SC_CLK_CTRL1_BASE_IDX 1
+#define mmCGTT_SQ_CLK_CTRL 0x508c
+#define mmCGTT_SQ_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_SQG_CLK_CTRL 0x508d
+#define mmCGTT_SQG_CLK_CTRL_BASE_IDX 1
+#define mmSQ_ALU_CLK_CTRL 0x508e
+#define mmSQ_ALU_CLK_CTRL_BASE_IDX 1
+#define mmSQ_TEX_CLK_CTRL 0x508f
+#define mmSQ_TEX_CLK_CTRL_BASE_IDX 1
+#define mmSQ_LDS_CLK_CTRL 0x5090
+#define mmSQ_LDS_CLK_CTRL_BASE_IDX 1
+#define mmSQ_POWER_THROTTLE 0x5091
+#define mmSQ_POWER_THROTTLE_BASE_IDX 1
+#define mmSQ_POWER_THROTTLE2 0x5092
+#define mmSQ_POWER_THROTTLE2_BASE_IDX 1
+#define mmCGTT_SX_CLK_CTRL0 0x5094
+#define mmCGTT_SX_CLK_CTRL0_BASE_IDX 1
+#define mmCGTT_SX_CLK_CTRL1 0x5095
+#define mmCGTT_SX_CLK_CTRL1_BASE_IDX 1
+#define mmCGTT_SX_CLK_CTRL2 0x5096
+#define mmCGTT_SX_CLK_CTRL2_BASE_IDX 1
+#define mmCGTT_SX_CLK_CTRL3 0x5097
+#define mmCGTT_SX_CLK_CTRL3_BASE_IDX 1
+#define mmCGTT_SX_CLK_CTRL4 0x5098
+#define mmCGTT_SX_CLK_CTRL4_BASE_IDX 1
+#define mmTD_CGTT_CTRL 0x509c
+#define mmTD_CGTT_CTRL_BASE_IDX 1
+#define mmTA_CGTT_CTRL 0x509d
+#define mmTA_CGTT_CTRL_BASE_IDX 1
+#define mmCGTT_TCPI_CLK_CTRL 0x509e
+#define mmCGTT_TCPI_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_TCI_CLK_CTRL 0x509f
+#define mmCGTT_TCI_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_GDS_CLK_CTRL 0x50a0
+#define mmCGTT_GDS_CLK_CTRL_BASE_IDX 1
+#define mmDB_CGTT_CLK_CTRL_0 0x50a4
+#define mmDB_CGTT_CLK_CTRL_0_BASE_IDX 1
+#define mmCB_CGTT_SCLK_CTRL 0x50a8
+#define mmCB_CGTT_SCLK_CTRL_BASE_IDX 1
+#define mmTCC_CGTT_SCLK_CTRL 0x50ac
+#define mmTCC_CGTT_SCLK_CTRL_BASE_IDX 1
+#define mmTCA_CGTT_SCLK_CTRL 0x50ad
+#define mmTCA_CGTT_SCLK_CTRL_BASE_IDX 1
+#define mmCGTT_CP_CLK_CTRL 0x50b0
+#define mmCGTT_CP_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_CPF_CLK_CTRL 0x50b1
+#define mmCGTT_CPF_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_CPC_CLK_CTRL 0x50b2
+#define mmCGTT_CPC_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_RLC_CLK_CTRL 0x50b5
+#define mmCGTT_RLC_CLK_CTRL_BASE_IDX 1
+#define mmRLC_GFX_RM_CNTL 0x50b6
+#define mmRLC_GFX_RM_CNTL_BASE_IDX 1
+#define mmRMI_CGTT_SCLK_CTRL 0x50c0
+#define mmRMI_CGTT_SCLK_CTRL_BASE_IDX 1
+#define mmCGTT_TCPF_CLK_CTRL 0x50c1
+#define mmCGTT_TCPF_CLK_CTRL_BASE_IDX 1
+
+
+// addressBlock: gc_ea_pwrdec
+// base address: 0x3c000
+#define mmGCEA_CGTT_CLK_CTRL 0x50c4
+#define mmGCEA_CGTT_CLK_CTRL_BASE_IDX 1
+
+
+// addressBlock: gc_utcl2_vmsharedhvdec
+// base address: 0x3ea00
+#define mmMC_VM_FB_SIZE_OFFSET_VF0 0x5a80
+#define mmMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1
+#define mmMC_VM_FB_SIZE_OFFSET_VF1 0x5a81
+#define mmMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1
+#define mmMC_VM_FB_SIZE_OFFSET_VF2 0x5a82
+#define mmMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1
+#define mmMC_VM_FB_SIZE_OFFSET_VF3 0x5a83
+#define mmMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1
+#define mmMC_VM_FB_SIZE_OFFSET_VF4 0x5a84
+#define mmMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1
+#define mmMC_VM_FB_SIZE_OFFSET_VF5 0x5a85
+#define mmMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1
+#define mmMC_VM_FB_SIZE_OFFSET_VF6 0x5a86
+#define mmMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1
+#define mmMC_VM_FB_SIZE_OFFSET_VF7 0x5a87
+#define mmMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1
+#define mmMC_VM_FB_SIZE_OFFSET_VF8 0x5a88
+#define mmMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1
+#define mmMC_VM_FB_SIZE_OFFSET_VF9 0x5a89
+#define mmMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1
+#define mmMC_VM_FB_SIZE_OFFSET_VF10 0x5a8a
+#define mmMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1
+#define mmMC_VM_FB_SIZE_OFFSET_VF11 0x5a8b
+#define mmMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1
+#define mmMC_VM_FB_SIZE_OFFSET_VF12 0x5a8c
+#define mmMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1
+#define mmMC_VM_FB_SIZE_OFFSET_VF13 0x5a8d
+#define mmMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1
+#define mmMC_VM_FB_SIZE_OFFSET_VF14 0x5a8e
+#define mmMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1
+#define mmMC_VM_FB_SIZE_OFFSET_VF15 0x5a8f
+#define mmMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1
+#define mmVM_IOMMU_MMIO_CNTRL_1 0x5a90
+#define mmVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 1
+#define mmMC_VM_MARC_BASE_LO_0 0x5a91
+#define mmMC_VM_MARC_BASE_LO_0_BASE_IDX 1
+#define mmMC_VM_MARC_BASE_LO_1 0x5a92
+#define mmMC_VM_MARC_BASE_LO_1_BASE_IDX 1
+#define mmMC_VM_MARC_BASE_LO_2 0x5a93
+#define mmMC_VM_MARC_BASE_LO_2_BASE_IDX 1
+#define mmMC_VM_MARC_BASE_LO_3 0x5a94
+#define mmMC_VM_MARC_BASE_LO_3_BASE_IDX 1
+#define mmMC_VM_MARC_BASE_HI_0 0x5a95
+#define mmMC_VM_MARC_BASE_HI_0_BASE_IDX 1
+#define mmMC_VM_MARC_BASE_HI_1 0x5a96
+#define mmMC_VM_MARC_BASE_HI_1_BASE_IDX 1
+#define mmMC_VM_MARC_BASE_HI_2 0x5a97
+#define mmMC_VM_MARC_BASE_HI_2_BASE_IDX 1
+#define mmMC_VM_MARC_BASE_HI_3 0x5a98
+#define mmMC_VM_MARC_BASE_HI_3_BASE_IDX 1
+#define mmMC_VM_MARC_RELOC_LO_0 0x5a99
+#define mmMC_VM_MARC_RELOC_LO_0_BASE_IDX 1
+#define mmMC_VM_MARC_RELOC_LO_1 0x5a9a
+#define mmMC_VM_MARC_RELOC_LO_1_BASE_IDX 1
+#define mmMC_VM_MARC_RELOC_LO_2 0x5a9b
+#define mmMC_VM_MARC_RELOC_LO_2_BASE_IDX 1
+#define mmMC_VM_MARC_RELOC_LO_3 0x5a9c
+#define mmMC_VM_MARC_RELOC_LO_3_BASE_IDX 1
+#define mmMC_VM_MARC_RELOC_HI_0 0x5a9d
+#define mmMC_VM_MARC_RELOC_HI_0_BASE_IDX 1
+#define mmMC_VM_MARC_RELOC_HI_1 0x5a9e
+#define mmMC_VM_MARC_RELOC_HI_1_BASE_IDX 1
+#define mmMC_VM_MARC_RELOC_HI_2 0x5a9f
+#define mmMC_VM_MARC_RELOC_HI_2_BASE_IDX 1
+#define mmMC_VM_MARC_RELOC_HI_3 0x5aa0
+#define mmMC_VM_MARC_RELOC_HI_3_BASE_IDX 1
+#define mmMC_VM_MARC_LEN_LO_0 0x5aa1
+#define mmMC_VM_MARC_LEN_LO_0_BASE_IDX 1
+#define mmMC_VM_MARC_LEN_LO_1 0x5aa2
+#define mmMC_VM_MARC_LEN_LO_1_BASE_IDX 1
+#define mmMC_VM_MARC_LEN_LO_2 0x5aa3
+#define mmMC_VM_MARC_LEN_LO_2_BASE_IDX 1
+#define mmMC_VM_MARC_LEN_LO_3 0x5aa4
+#define mmMC_VM_MARC_LEN_LO_3_BASE_IDX 1
+#define mmMC_VM_MARC_LEN_HI_0 0x5aa5
+#define mmMC_VM_MARC_LEN_HI_0_BASE_IDX 1
+#define mmMC_VM_MARC_LEN_HI_1 0x5aa6
+#define mmMC_VM_MARC_LEN_HI_1_BASE_IDX 1
+#define mmMC_VM_MARC_LEN_HI_2 0x5aa7
+#define mmMC_VM_MARC_LEN_HI_2_BASE_IDX 1
+#define mmMC_VM_MARC_LEN_HI_3 0x5aa8
+#define mmMC_VM_MARC_LEN_HI_3_BASE_IDX 1
+#define mmVM_IOMMU_CONTROL_REGISTER 0x5aa9
+#define mmVM_IOMMU_CONTROL_REGISTER_BASE_IDX 1
+#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x5aaa
+#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1
+#define mmVM_PCIE_ATS_CNTL 0x5aab
+#define mmVM_PCIE_ATS_CNTL_BASE_IDX 1
+#define mmVM_PCIE_ATS_CNTL_VF_0 0x5aac
+#define mmVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1
+#define mmVM_PCIE_ATS_CNTL_VF_1 0x5aad
+#define mmVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1
+#define mmVM_PCIE_ATS_CNTL_VF_2 0x5aae
+#define mmVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1
+#define mmVM_PCIE_ATS_CNTL_VF_3 0x5aaf
+#define mmVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1
+#define mmVM_PCIE_ATS_CNTL_VF_4 0x5ab0
+#define mmVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1
+#define mmVM_PCIE_ATS_CNTL_VF_5 0x5ab1
+#define mmVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1
+#define mmVM_PCIE_ATS_CNTL_VF_6 0x5ab2
+#define mmVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1
+#define mmVM_PCIE_ATS_CNTL_VF_7 0x5ab3
+#define mmVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1
+#define mmVM_PCIE_ATS_CNTL_VF_8 0x5ab4
+#define mmVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1
+#define mmVM_PCIE_ATS_CNTL_VF_9 0x5ab5
+#define mmVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1
+#define mmVM_PCIE_ATS_CNTL_VF_10 0x5ab6
+#define mmVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1
+#define mmVM_PCIE_ATS_CNTL_VF_11 0x5ab7
+#define mmVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1
+#define mmVM_PCIE_ATS_CNTL_VF_12 0x5ab8
+#define mmVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1
+#define mmVM_PCIE_ATS_CNTL_VF_13 0x5ab9
+#define mmVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1
+#define mmVM_PCIE_ATS_CNTL_VF_14 0x5aba
+#define mmVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1
+#define mmVM_PCIE_ATS_CNTL_VF_15 0x5abb
+#define mmVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1
+#define mmUTCL2_CGTT_CLK_CTRL 0x5abc
+#define mmUTCL2_CGTT_CLK_CTRL_BASE_IDX 1
+
+
+// addressBlock: gc_hypdec
+// base address: 0x3e000
+#define mmCP_HYP_PFP_UCODE_ADDR 0x5814
+#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1
+#define mmCP_PFP_UCODE_ADDR 0x5814
+#define mmCP_PFP_UCODE_ADDR_BASE_IDX 1
+#define mmCP_HYP_PFP_UCODE_DATA 0x5815
+#define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1
+#define mmCP_PFP_UCODE_DATA 0x5815
+#define mmCP_PFP_UCODE_DATA_BASE_IDX 1
+#define mmCP_HYP_ME_UCODE_ADDR 0x5816
+#define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1
+#define mmCP_ME_RAM_RADDR 0x5816
+#define mmCP_ME_RAM_RADDR_BASE_IDX 1
+#define mmCP_ME_RAM_WADDR 0x5816
+#define mmCP_ME_RAM_WADDR_BASE_IDX 1
+#define mmCP_HYP_ME_UCODE_DATA 0x5817
+#define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1
+#define mmCP_ME_RAM_DATA 0x5817
+#define mmCP_ME_RAM_DATA_BASE_IDX 1
+#define mmCP_CE_UCODE_ADDR 0x5818
+#define mmCP_CE_UCODE_ADDR_BASE_IDX 1
+#define mmCP_HYP_CE_UCODE_ADDR 0x5818
+#define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1
+#define mmCP_CE_UCODE_DATA 0x5819
+#define mmCP_CE_UCODE_DATA_BASE_IDX 1
+#define mmCP_HYP_CE_UCODE_DATA 0x5819
+#define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1
+#define mmCP_HYP_MEC1_UCODE_ADDR 0x581a
+#define mmCP_HYP_MEC1_UCODE_ADDR_BASE_IDX 1
+#define mmCP_MEC_ME1_UCODE_ADDR 0x581a
+#define mmCP_MEC_ME1_UCODE_ADDR_BASE_IDX 1
+#define mmCP_HYP_MEC1_UCODE_DATA 0x581b
+#define mmCP_HYP_MEC1_UCODE_DATA_BASE_IDX 1
+#define mmCP_MEC_ME1_UCODE_DATA 0x581b
+#define mmCP_MEC_ME1_UCODE_DATA_BASE_IDX 1
+#define mmCP_HYP_MEC2_UCODE_ADDR 0x581c
+#define mmCP_HYP_MEC2_UCODE_ADDR_BASE_IDX 1
+#define mmCP_MEC_ME2_UCODE_ADDR 0x581c
+#define mmCP_MEC_ME2_UCODE_ADDR_BASE_IDX 1
+#define mmCP_HYP_MEC2_UCODE_DATA 0x581d
+#define mmCP_HYP_MEC2_UCODE_DATA_BASE_IDX 1
+#define mmCP_MEC_ME2_UCODE_DATA 0x581d
+#define mmCP_MEC_ME2_UCODE_DATA_BASE_IDX 1
+#define mmRLC_GPM_UCODE_ADDR 0x583c
+#define mmRLC_GPM_UCODE_ADDR_BASE_IDX 1
+#define mmRLC_GPM_UCODE_DATA 0x583d
+#define mmRLC_GPM_UCODE_DATA_BASE_IDX 1
+#define mmGRBM_GFX_INDEX_SR_SELECT 0x5a00
+#define mmGRBM_GFX_INDEX_SR_SELECT_BASE_IDX 1
+#define mmGRBM_GFX_INDEX_SR_DATA 0x5a01
+#define mmGRBM_GFX_INDEX_SR_DATA_BASE_IDX 1
+#define mmGRBM_GFX_CNTL_SR_SELECT 0x5a02
+#define mmGRBM_GFX_CNTL_SR_SELECT_BASE_IDX 1
+#define mmGRBM_GFX_CNTL_SR_DATA 0x5a03
+#define mmGRBM_GFX_CNTL_SR_DATA_BASE_IDX 1
+#define mmGRBM_CAM_INDEX 0x5a04
+#define mmGRBM_CAM_INDEX_BASE_IDX 1
+#define mmGRBM_HYP_CAM_INDEX 0x5a04
+#define mmGRBM_HYP_CAM_INDEX_BASE_IDX 1
+#define mmGRBM_CAM_DATA 0x5a05
+#define mmGRBM_CAM_DATA_BASE_IDX 1
+#define mmGRBM_HYP_CAM_DATA 0x5a05
+#define mmGRBM_HYP_CAM_DATA_BASE_IDX 1
+#define mmRLC_GPU_IOV_VF_ENABLE 0x5b00
+#define mmRLC_GPU_IOV_VF_ENABLE_BASE_IDX 1
+#define mmRLC_GPU_IOV_CFG_REG6 0x5b06
+#define mmRLC_GPU_IOV_CFG_REG6_BASE_IDX 1
+#define mmRLC_GPU_IOV_CFG_REG8 0x5b20
+#define mmRLC_GPU_IOV_CFG_REG8_BASE_IDX 1
+#define mmRLC_RLCV_TIMER_INT_0 0x5b25
+#define mmRLC_RLCV_TIMER_INT_0_BASE_IDX 1
+#define mmRLC_RLCV_TIMER_CTRL 0x5b26
+#define mmRLC_RLCV_TIMER_CTRL_BASE_IDX 1
+#define mmRLC_RLCV_TIMER_STAT 0x5b27
+#define mmRLC_RLCV_TIMER_STAT_BASE_IDX 1
+#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS 0x5b2a
+#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX 1
+#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0x5b2b
+#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX 1
+#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0x5b2c
+#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX 1
+#define mmRLC_GPU_IOV_VF_MASK 0x5b2d
+#define mmRLC_GPU_IOV_VF_MASK_BASE_IDX 1
+#define mmRLC_HYP_SEMAPHORE_2 0x5b2e
+#define mmRLC_HYP_SEMAPHORE_2_BASE_IDX 1
+#define mmRLC_HYP_SEMAPHORE_3 0x5b2f
+#define mmRLC_HYP_SEMAPHORE_3_BASE_IDX 1
+#define mmRLC_CLK_CNTL 0x5b31
+#define mmRLC_CLK_CNTL_BASE_IDX 1
+#define mmRLC_GPU_IOV_SCH_BLOCK 0x5b34
+#define mmRLC_GPU_IOV_SCH_BLOCK_BASE_IDX 1
+#define mmRLC_GPU_IOV_CFG_REG1 0x5b35
+#define mmRLC_GPU_IOV_CFG_REG1_BASE_IDX 1
+#define mmRLC_GPU_IOV_CFG_REG2 0x5b36
+#define mmRLC_GPU_IOV_CFG_REG2_BASE_IDX 1
+#define mmRLC_GPU_IOV_VM_BUSY_STATUS 0x5b37
+#define mmRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX 1
+#define mmRLC_GPU_IOV_SCH_0 0x5b38
+#define mmRLC_GPU_IOV_SCH_0_BASE_IDX 1
+#define mmRLC_GPU_IOV_ACTIVE_FCN_ID 0x5b39
+#define mmRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX 1
+#define mmRLC_GPU_IOV_SCH_3 0x5b3a
+#define mmRLC_GPU_IOV_SCH_3_BASE_IDX 1
+#define mmRLC_GPU_IOV_SCH_1 0x5b3b
+#define mmRLC_GPU_IOV_SCH_1_BASE_IDX 1
+#define mmRLC_GPU_IOV_SCH_2 0x5b3c
+#define mmRLC_GPU_IOV_SCH_2_BASE_IDX 1
+#define mmRLC_GPU_IOV_UCODE_ADDR 0x5b42
+#define mmRLC_GPU_IOV_UCODE_ADDR_BASE_IDX 1
+#define mmRLC_GPU_IOV_UCODE_DATA 0x5b43
+#define mmRLC_GPU_IOV_UCODE_DATA_BASE_IDX 1
+#define mmRLC_GPU_IOV_SCRATCH_ADDR 0x5b44
+#define mmRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX 1
+#define mmRLC_GPU_IOV_SCRATCH_DATA 0x5b45
+#define mmRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX 1
+#define mmRLC_GPU_IOV_F32_CNTL 0x5b46
+#define mmRLC_GPU_IOV_F32_CNTL_BASE_IDX 1
+#define mmRLC_GPU_IOV_F32_RESET 0x5b47
+#define mmRLC_GPU_IOV_F32_RESET_BASE_IDX 1
+#define mmRLC_GPU_IOV_SDMA0_STATUS 0x5b48
+#define mmRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX 1
+#define mmRLC_GPU_IOV_SDMA1_STATUS 0x5b49
+#define mmRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX 1
+#define mmRLC_GPU_IOV_SMU_RESPONSE 0x5b4a
+#define mmRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX 1
+#define mmRLC_GPU_IOV_VIRT_RESET_REQ 0x5b4c
+#define mmRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX 1
+#define mmRLC_GPU_IOV_RLC_RESPONSE 0x5b4d
+#define mmRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX 1
+#define mmRLC_GPU_IOV_INT_DISABLE 0x5b4e
+#define mmRLC_GPU_IOV_INT_DISABLE_BASE_IDX 1
+#define mmRLC_GPU_IOV_INT_FORCE 0x5b4f
+#define mmRLC_GPU_IOV_INT_FORCE_BASE_IDX 1
+#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS 0x5b50
+#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX 1
+#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS 0x5b51
+#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX 1
+
+
+// addressBlock: gccacind
+// base address: 0x0
+#define ixGC_CAC_CNTL 0x0000
+#define ixGC_CAC_OVR_SEL 0x0001
+#define ixGC_CAC_OVR_VAL 0x0002
+#define ixGC_CAC_WEIGHT_BCI_0 0x0003
+#define ixGC_CAC_WEIGHT_CB_0 0x0004
+#define ixGC_CAC_WEIGHT_CB_1 0x0005
+#define ixGC_CAC_WEIGHT_CBR_0 0x0006
+#define ixGC_CAC_WEIGHT_CBR_1 0x0007
+#define ixGC_CAC_WEIGHT_CP_0 0x0008
+#define ixGC_CAC_WEIGHT_CP_1 0x0009
+#define ixGC_CAC_WEIGHT_DB_0 0x000a
+#define ixGC_CAC_WEIGHT_DB_1 0x000b
+#define ixGC_CAC_WEIGHT_DBR_0 0x000c
+#define ixGC_CAC_WEIGHT_DBR_1 0x000d
+#define ixGC_CAC_WEIGHT_GDS_0 0x000e
+#define ixGC_CAC_WEIGHT_GDS_1 0x000f
+#define ixGC_CAC_WEIGHT_IA_0 0x0010
+#define ixGC_CAC_WEIGHT_LDS_0 0x0011
+#define ixGC_CAC_WEIGHT_LDS_1 0x0012
+#define ixGC_CAC_WEIGHT_PA_0 0x0013
+#define ixGC_CAC_WEIGHT_PC_0 0x0014
+#define ixGC_CAC_WEIGHT_SC_0 0x0015
+#define ixGC_CAC_WEIGHT_SPI_0 0x0016
+#define ixGC_CAC_WEIGHT_SPI_1 0x0017
+#define ixGC_CAC_WEIGHT_SPI_2 0x0018
+#define ixGC_CAC_WEIGHT_SQ_0 0x001a
+#define ixGC_CAC_WEIGHT_SQ_1 0x001b
+#define ixGC_CAC_WEIGHT_SQ_2 0x001c
+#define ixGC_CAC_WEIGHT_SQ_3 0x001d
+#define ixGC_CAC_WEIGHT_SQ_4 0x001e
+#define ixGC_CAC_WEIGHT_SX_0 0x001f
+#define ixGC_CAC_WEIGHT_SXRB_0 0x0020
+#define ixGC_CAC_WEIGHT_TA_0 0x0021
+#define ixGC_CAC_WEIGHT_TCC_0 0x0022
+#define ixGC_CAC_WEIGHT_TCC_1 0x0023
+#define ixGC_CAC_WEIGHT_TCC_2 0x0024
+#define ixGC_CAC_WEIGHT_TCP_0 0x0025
+#define ixGC_CAC_WEIGHT_TCP_1 0x0026
+#define ixGC_CAC_WEIGHT_TCP_2 0x0027
+#define ixGC_CAC_WEIGHT_TD_0 0x0028
+#define ixGC_CAC_WEIGHT_TD_1 0x0029
+#define ixGC_CAC_WEIGHT_TD_2 0x002a
+#define ixGC_CAC_WEIGHT_VGT_0 0x002b
+#define ixGC_CAC_WEIGHT_VGT_1 0x002c
+#define ixGC_CAC_WEIGHT_WD_0 0x002d
+#define ixGC_CAC_WEIGHT_CU_0 0x0032
+#define ixGC_CAC_WEIGHT_CU_1 0x0033
+#define ixGC_CAC_WEIGHT_CU_2 0x0034
+#define ixGC_CAC_WEIGHT_CU_3 0x0035
+#define ixGC_CAC_WEIGHT_CU_4 0x0036
+#define ixGC_CAC_WEIGHT_CU_5 0x0037
+#define ixGC_CAC_WEIGHT_CU_6 0x0038
+#define ixGC_CAC_WEIGHT_CU_7 0x0039
+#define ixGC_CAC_ACC_BCI0 0x0042
+#define ixGC_CAC_ACC_CB0 0x0043
+#define ixGC_CAC_ACC_CB1 0x0044
+#define ixGC_CAC_ACC_CB2 0x0045
+#define ixGC_CAC_ACC_CB3 0x0046
+#define ixGC_CAC_ACC_CBR0 0x0047
+#define ixGC_CAC_ACC_CBR1 0x0048
+#define ixGC_CAC_ACC_CBR2 0x0049
+#define ixGC_CAC_ACC_CBR3 0x004a
+#define ixGC_CAC_ACC_CP0 0x004b
+#define ixGC_CAC_ACC_CP1 0x004c
+#define ixGC_CAC_ACC_CP2 0x004d
+#define ixGC_CAC_ACC_DB0 0x004e
+#define ixGC_CAC_ACC_DB1 0x004f
+#define ixGC_CAC_ACC_DB2 0x0050
+#define ixGC_CAC_ACC_DB3 0x0051
+#define ixGC_CAC_ACC_DBR0 0x0052
+#define ixGC_CAC_ACC_DBR1 0x0053
+#define ixGC_CAC_ACC_DBR2 0x0054
+#define ixGC_CAC_ACC_DBR3 0x0055
+#define ixGC_CAC_ACC_GDS0 0x0056
+#define ixGC_CAC_ACC_GDS1 0x0057
+#define ixGC_CAC_ACC_GDS2 0x0058
+#define ixGC_CAC_ACC_GDS3 0x0059
+#define ixGC_CAC_ACC_IA0 0x005a
+#define ixGC_CAC_ACC_LDS0 0x005b
+#define ixGC_CAC_ACC_LDS1 0x005c
+#define ixGC_CAC_ACC_LDS2 0x005d
+#define ixGC_CAC_ACC_LDS3 0x005e
+#define ixGC_CAC_ACC_PA0 0x005f
+#define ixGC_CAC_ACC_PA1 0x0060
+#define ixGC_CAC_ACC_PC0 0x0061
+#define ixGC_CAC_ACC_SC0 0x0062
+#define ixGC_CAC_ACC_SPI0 0x0063
+#define ixGC_CAC_ACC_SPI1 0x0064
+#define ixGC_CAC_ACC_SPI2 0x0065
+#define ixGC_CAC_ACC_SPI3 0x0066
+#define ixGC_CAC_ACC_SPI4 0x0067
+#define ixGC_CAC_ACC_SPI5 0x0068
+#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_0 0x006f
+#define ixGC_CAC_ACC_EA0 0x0070
+#define ixGC_CAC_ACC_EA1 0x0071
+#define ixGC_CAC_ACC_EA2 0x0072
+#define ixGC_CAC_ACC_EA3 0x0073
+#define ixGC_CAC_ACC_UTCL2_ATCL20 0x0074
+#define ixGC_CAC_OVRD_EA 0x0075
+#define ixGC_CAC_OVRD_UTCL2_ATCL2 0x0076
+#define ixGC_CAC_WEIGHT_EA_0 0x0077
+#define ixGC_CAC_WEIGHT_EA_1 0x0078
+#define ixGC_CAC_WEIGHT_RMI_0 0x0079
+#define ixGC_CAC_ACC_RMI0 0x007a
+#define ixGC_CAC_OVRD_RMI 0x007b
+#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_1 0x007c
+#define ixGC_CAC_ACC_UTCL2_ATCL21 0x007d
+#define ixGC_CAC_ACC_UTCL2_ATCL22 0x007e
+#define ixGC_CAC_ACC_UTCL2_ATCL23 0x007f
+#define ixGC_CAC_ACC_EA4 0x0080
+#define ixGC_CAC_ACC_EA5 0x0081
+#define ixGC_CAC_WEIGHT_EA_2 0x0082
+#define ixGC_CAC_ACC_SQ0_LOWER 0x0089
+#define ixGC_CAC_ACC_SQ0_UPPER 0x008a
+#define ixGC_CAC_ACC_SQ1_LOWER 0x008b
+#define ixGC_CAC_ACC_SQ1_UPPER 0x008c
+#define ixGC_CAC_ACC_SQ2_LOWER 0x008d
+#define ixGC_CAC_ACC_SQ2_UPPER 0x008e
+#define ixGC_CAC_ACC_SQ3_LOWER 0x008f
+#define ixGC_CAC_ACC_SQ3_UPPER 0x0090
+#define ixGC_CAC_ACC_SQ4_LOWER 0x0091
+#define ixGC_CAC_ACC_SQ4_UPPER 0x0092
+#define ixGC_CAC_ACC_SQ5_LOWER 0x0093
+#define ixGC_CAC_ACC_SQ5_UPPER 0x0094
+#define ixGC_CAC_ACC_SQ6_LOWER 0x0095
+#define ixGC_CAC_ACC_SQ6_UPPER 0x0096
+#define ixGC_CAC_ACC_SQ7_LOWER 0x0097
+#define ixGC_CAC_ACC_SQ7_UPPER 0x0098
+#define ixGC_CAC_ACC_SQ8_LOWER 0x0099
+#define ixGC_CAC_ACC_SQ8_UPPER 0x009a
+#define ixGC_CAC_ACC_SX0 0x009b
+#define ixGC_CAC_ACC_SXRB0 0x009c
+#define ixGC_CAC_ACC_SXRB1 0x009d
+#define ixGC_CAC_ACC_TA0 0x009e
+#define ixGC_CAC_ACC_TCC0 0x009f
+#define ixGC_CAC_ACC_TCC1 0x00a0
+#define ixGC_CAC_ACC_TCC2 0x00a1
+#define ixGC_CAC_ACC_TCC3 0x00a2
+#define ixGC_CAC_ACC_TCC4 0x00a3
+#define ixGC_CAC_ACC_TCP0 0x00a4
+#define ixGC_CAC_ACC_TCP1 0x00a5
+#define ixGC_CAC_ACC_TCP2 0x00a6
+#define ixGC_CAC_ACC_TCP3 0x00a7
+#define ixGC_CAC_ACC_TCP4 0x00a8
+#define ixGC_CAC_ACC_TD0 0x00a9
+#define ixGC_CAC_ACC_TD1 0x00aa
+#define ixGC_CAC_ACC_TD2 0x00ab
+#define ixGC_CAC_ACC_TD3 0x00ac
+#define ixGC_CAC_ACC_TD4 0x00ad
+#define ixGC_CAC_ACC_TD5 0x00ae
+#define ixGC_CAC_ACC_VGT0 0x00af
+#define ixGC_CAC_ACC_VGT1 0x00b0
+#define ixGC_CAC_ACC_VGT2 0x00b1
+#define ixGC_CAC_ACC_WD0 0x00b2
+#define ixGC_CAC_ACC_CU0 0x00ba
+#define ixGC_CAC_ACC_CU1 0x00bb
+#define ixGC_CAC_ACC_CU2 0x00bc
+#define ixGC_CAC_ACC_CU3 0x00bd
+#define ixGC_CAC_ACC_CU4 0x00be
+#define ixGC_CAC_ACC_CU5 0x00bf
+#define ixGC_CAC_ACC_CU6 0x00c0
+#define ixGC_CAC_ACC_CU7 0x00c1
+#define ixGC_CAC_ACC_CU8 0x00c2
+#define ixGC_CAC_ACC_CU9 0x00c3
+#define ixGC_CAC_ACC_CU10 0x00c4
+#define ixGC_CAC_ACC_CU11 0x00c5
+#define ixGC_CAC_ACC_CU12 0x00c6
+#define ixGC_CAC_ACC_CU13 0x00c7
+#define ixGC_CAC_ACC_CU14 0x00c8
+#define ixGC_CAC_ACC_CU15 0x00c9
+#define ixGC_CAC_OVRD_BCI 0x00da
+#define ixGC_CAC_OVRD_CB 0x00db
+#define ixGC_CAC_OVRD_CBR 0x00dc
+#define ixGC_CAC_OVRD_CP 0x00dd
+#define ixGC_CAC_OVRD_DB 0x00de
+#define ixGC_CAC_OVRD_DBR 0x00df
+#define ixGC_CAC_OVRD_GDS 0x00e0
+#define ixGC_CAC_OVRD_IA 0x00e1
+#define ixGC_CAC_OVRD_LDS 0x00e2
+#define ixGC_CAC_OVRD_PA 0x00e3
+#define ixGC_CAC_OVRD_PC 0x00e4
+#define ixGC_CAC_OVRD_SC 0x00e5
+#define ixGC_CAC_OVRD_SPI 0x00e6
+#define ixGC_CAC_OVRD_CU 0x00e7
+#define ixGC_CAC_OVRD_SQ 0x00e8
+#define ixGC_CAC_OVRD_SX 0x00e9
+#define ixGC_CAC_OVRD_SXRB 0x00ea
+#define ixGC_CAC_OVRD_TA 0x00eb
+#define ixGC_CAC_OVRD_TCC 0x00ec
+#define ixGC_CAC_OVRD_TCP 0x00ed
+#define ixGC_CAC_OVRD_TD 0x00ee
+#define ixGC_CAC_OVRD_VGT 0x00ef
+#define ixGC_CAC_OVRD_WD 0x00f0
+#define ixGC_CAC_ACC_BCI1 0x00ff
+#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_2 0x0100
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_0 0x0101
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_1 0x0102
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_2 0x0103
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_3 0x0104
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_4 0x0105
+#define ixGC_CAC_WEIGHT_UTCL2_VML2_0 0x0106
+#define ixGC_CAC_WEIGHT_UTCL2_VML2_1 0x0107
+#define ixGC_CAC_WEIGHT_UTCL2_VML2_2 0x0108
+#define ixGC_CAC_ACC_UTCL2_ATCL24 0x0109
+#define ixGC_CAC_ACC_UTCL2_ROUTER0 0x010a
+#define ixGC_CAC_ACC_UTCL2_ROUTER1 0x010b
+#define ixGC_CAC_ACC_UTCL2_ROUTER2 0x010c
+#define ixGC_CAC_ACC_UTCL2_ROUTER3 0x010d
+#define ixGC_CAC_ACC_UTCL2_ROUTER4 0x010e
+#define ixGC_CAC_ACC_UTCL2_ROUTER5 0x010f
+#define ixGC_CAC_ACC_UTCL2_ROUTER6 0x0110
+#define ixGC_CAC_ACC_UTCL2_ROUTER7 0x0111
+#define ixGC_CAC_ACC_UTCL2_ROUTER8 0x0112
+#define ixGC_CAC_ACC_UTCL2_ROUTER9 0x0113
+#define ixGC_CAC_ACC_UTCL2_VML20 0x0114
+#define ixGC_CAC_ACC_UTCL2_VML21 0x0115
+#define ixGC_CAC_ACC_UTCL2_VML22 0x0116
+#define ixGC_CAC_ACC_UTCL2_VML23 0x0117
+#define ixGC_CAC_ACC_UTCL2_VML24 0x0118
+#define ixGC_CAC_OVRD_UTCL2_ROUTER 0x0119
+#define ixGC_CAC_OVRD_UTCL2_VML2 0x011a
+#define ixGC_CAC_WEIGHT_UTCL2_WALKER_0 0x011b
+#define ixGC_CAC_WEIGHT_UTCL2_WALKER_1 0x011c
+#define ixGC_CAC_WEIGHT_UTCL2_WALKER_2 0x011d
+#define ixGC_CAC_ACC_UTCL2_WALKER0 0x011e
+#define ixGC_CAC_ACC_UTCL2_WALKER1 0x011f
+#define ixGC_CAC_ACC_UTCL2_WALKER2 0x0120
+#define ixGC_CAC_ACC_UTCL2_WALKER3 0x0121
+#define ixGC_CAC_ACC_UTCL2_WALKER4 0x0122
+#define ixGC_CAC_OVRD_UTCL2_WALKER 0x0123
+
+
+// addressBlock: secacind
+// base address: 0x0
+#define ixSE_CAC_CNTL 0x0000
+#define ixSE_CAC_OVR_SEL 0x0001
+#define ixSE_CAC_OVR_VAL 0x0002
+
+
+// addressBlock: sqind
+// base address: 0x0
+#define ixSQ_WAVE_MODE 0x0011
+#define ixSQ_WAVE_STATUS 0x0012
+#define ixSQ_WAVE_TRAPSTS 0x0013
+#define ixSQ_WAVE_HW_ID 0x0014
+#define ixSQ_WAVE_GPR_ALLOC 0x0015
+#define ixSQ_WAVE_LDS_ALLOC 0x0016
+#define ixSQ_WAVE_IB_STS 0x0017
+#define ixSQ_WAVE_PC_LO 0x0018
+#define ixSQ_WAVE_PC_HI 0x0019
+#define ixSQ_WAVE_INST_DW0 0x001a
+#define ixSQ_WAVE_INST_DW1 0x001b
+#define ixSQ_WAVE_IB_DBG0 0x001c
+#define ixSQ_WAVE_IB_DBG1 0x001d
+#define ixSQ_WAVE_FLUSH_IB 0x001e
+#define ixSQ_WAVE_TTMP0 0x026c
+#define ixSQ_WAVE_TTMP1 0x026d
+#define ixSQ_WAVE_TTMP2 0x026e
+#define ixSQ_WAVE_TTMP3 0x026f
+#define ixSQ_WAVE_TTMP4 0x0270
+#define ixSQ_WAVE_TTMP5 0x0271
+#define ixSQ_WAVE_TTMP6 0x0272
+#define ixSQ_WAVE_TTMP7 0x0273
+#define ixSQ_WAVE_TTMP8 0x0274
+#define ixSQ_WAVE_TTMP9 0x0275
+#define ixSQ_WAVE_TTMP10 0x0276
+#define ixSQ_WAVE_TTMP11 0x0277
+#define ixSQ_WAVE_TTMP12 0x0278
+#define ixSQ_WAVE_TTMP13 0x0279
+#define ixSQ_WAVE_TTMP14 0x027a
+#define ixSQ_WAVE_TTMP15 0x027b
+#define ixSQ_WAVE_M0 0x027c
+#define ixSQ_WAVE_EXEC_LO 0x027e
+#define ixSQ_WAVE_EXEC_HI 0x027f
+#define ixSQ_INTERRUPT_WORD_AUTO_CTXID 0x20c0
+#define ixSQ_INTERRUPT_WORD_AUTO_HI 0x20c0
+#define ixSQ_INTERRUPT_WORD_AUTO_LO 0x20c0
+#define ixSQ_INTERRUPT_WORD_CMN_CTXID 0x20c0
+#define ixSQ_INTERRUPT_WORD_CMN_HI 0x20c0
+#define ixSQ_INTERRUPT_WORD_WAVE_CTXID 0x20c0
+#define ixSQ_INTERRUPT_WORD_WAVE_HI 0x20c0
+#define ixSQ_INTERRUPT_WORD_WAVE_LO 0x20c0
+
+
+// addressBlock: didtind
+// base address: 0x0
+#define ixDIDT_SQ_CTRL0 0x0000
+#define ixDIDT_SQ_CTRL1 0x0001
+#define ixDIDT_SQ_CTRL2 0x0002
+#define ixDIDT_SQ_STALL_CTRL 0x0004
+#define ixDIDT_SQ_TUNING_CTRL 0x0005
+#define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006
+#define ixDIDT_SQ_CTRL3 0x0007
+#define ixDIDT_SQ_STALL_PATTERN_1_2 0x0008
+#define ixDIDT_SQ_STALL_PATTERN_3_4 0x0009
+#define ixDIDT_SQ_STALL_PATTERN_5_6 0x000a
+#define ixDIDT_SQ_STALL_PATTERN_7 0x000b
+#define ixDIDT_SQ_WEIGHT0_3 0x0010
+#define ixDIDT_SQ_WEIGHT4_7 0x0011
+#define ixDIDT_SQ_WEIGHT8_11 0x0012
+#define ixDIDT_SQ_EDC_CTRL 0x0013
+#define ixDIDT_SQ_EDC_THRESHOLD 0x0014
+#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0x0015
+#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4 0x0016
+#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 0x0017
+#define ixDIDT_SQ_EDC_STALL_PATTERN_7 0x0018
+#define ixDIDT_SQ_EDC_STATUS 0x0019
+#define ixDIDT_SQ_EDC_STALL_DELAY_1 0x001a
+#define ixDIDT_SQ_EDC_STALL_DELAY_2 0x001b
+#define ixDIDT_SQ_EDC_STALL_DELAY_3 0x001c
+#define ixDIDT_SQ_EDC_STALL_DELAY_4 0x001d
+#define ixDIDT_SQ_EDC_OVERFLOW 0x001e
+#define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA 0x001f
+#define ixDIDT_DB_CTRL0 0x0020
+#define ixDIDT_DB_CTRL1 0x0021
+#define ixDIDT_DB_CTRL2 0x0022
+#define ixDIDT_DB_STALL_CTRL 0x0024
+#define ixDIDT_DB_TUNING_CTRL 0x0025
+#define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL 0x0026
+#define ixDIDT_DB_CTRL3 0x0027
+#define ixDIDT_DB_STALL_PATTERN_1_2 0x0028
+#define ixDIDT_DB_STALL_PATTERN_3_4 0x0029
+#define ixDIDT_DB_STALL_PATTERN_5_6 0x002a
+#define ixDIDT_DB_STALL_PATTERN_7 0x002b
+#define ixDIDT_DB_WEIGHT0_3 0x0030
+#define ixDIDT_DB_WEIGHT4_7 0x0031
+#define ixDIDT_DB_WEIGHT8_11 0x0032
+#define ixDIDT_DB_EDC_CTRL 0x0033
+#define ixDIDT_DB_EDC_THRESHOLD 0x0034
+#define ixDIDT_DB_EDC_STALL_PATTERN_1_2 0x0035
+#define ixDIDT_DB_EDC_STALL_PATTERN_3_4 0x0036
+#define ixDIDT_DB_EDC_STALL_PATTERN_5_6 0x0037
+#define ixDIDT_DB_EDC_STALL_PATTERN_7 0x0038
+#define ixDIDT_DB_EDC_STATUS 0x0039
+#define ixDIDT_DB_EDC_STALL_DELAY_1 0x003a
+#define ixDIDT_DB_EDC_OVERFLOW 0x003e
+#define ixDIDT_DB_EDC_ROLLING_POWER_DELTA 0x003f
+#define ixDIDT_TD_CTRL0 0x0040
+#define ixDIDT_TD_CTRL1 0x0041
+#define ixDIDT_TD_CTRL2 0x0042
+#define ixDIDT_TD_STALL_CTRL 0x0044
+#define ixDIDT_TD_TUNING_CTRL 0x0045
+#define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL 0x0046
+#define ixDIDT_TD_CTRL3 0x0047
+#define ixDIDT_TD_STALL_PATTERN_1_2 0x0048
+#define ixDIDT_TD_STALL_PATTERN_3_4 0x0049
+#define ixDIDT_TD_STALL_PATTERN_5_6 0x004a
+#define ixDIDT_TD_STALL_PATTERN_7 0x004b
+#define ixDIDT_TD_WEIGHT0_3 0x0050
+#define ixDIDT_TD_WEIGHT4_7 0x0051
+#define ixDIDT_TD_WEIGHT8_11 0x0052
+#define ixDIDT_TD_EDC_CTRL 0x0053
+#define ixDIDT_TD_EDC_THRESHOLD 0x0054
+#define ixDIDT_TD_EDC_STALL_PATTERN_1_2 0x0055
+#define ixDIDT_TD_EDC_STALL_PATTERN_3_4 0x0056
+#define ixDIDT_TD_EDC_STALL_PATTERN_5_6 0x0057
+#define ixDIDT_TD_EDC_STALL_PATTERN_7 0x0058
+#define ixDIDT_TD_EDC_STATUS 0x0059
+#define ixDIDT_TD_EDC_STALL_DELAY_1 0x005a
+#define ixDIDT_TD_EDC_STALL_DELAY_2 0x005b
+#define ixDIDT_TD_EDC_STALL_DELAY_3 0x005c
+#define ixDIDT_TD_EDC_STALL_DELAY_4 0x005d
+#define ixDIDT_TD_EDC_OVERFLOW 0x005e
+#define ixDIDT_TD_EDC_ROLLING_POWER_DELTA 0x005f
+#define ixDIDT_TCP_CTRL0 0x0060
+#define ixDIDT_TCP_CTRL1 0x0061
+#define ixDIDT_TCP_CTRL2 0x0062
+#define ixDIDT_TCP_STALL_CTRL 0x0064
+#define ixDIDT_TCP_TUNING_CTRL 0x0065
+#define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL 0x0066
+#define ixDIDT_TCP_CTRL3 0x0067
+#define ixDIDT_TCP_STALL_PATTERN_1_2 0x0068
+#define ixDIDT_TCP_STALL_PATTERN_3_4 0x0069
+#define ixDIDT_TCP_STALL_PATTERN_5_6 0x006a
+#define ixDIDT_TCP_STALL_PATTERN_7 0x006b
+#define ixDIDT_TCP_WEIGHT0_3 0x0070
+#define ixDIDT_TCP_WEIGHT4_7 0x0071
+#define ixDIDT_TCP_WEIGHT8_11 0x0072
+#define ixDIDT_TCP_EDC_CTRL 0x0073
+#define ixDIDT_TCP_EDC_THRESHOLD 0x0074
+#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2 0x0075
+#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4 0x0076
+#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6 0x0077
+#define ixDIDT_TCP_EDC_STALL_PATTERN_7 0x0078
+#define ixDIDT_TCP_EDC_STATUS 0x0079
+#define ixDIDT_TCP_EDC_STALL_DELAY_1 0x007a
+#define ixDIDT_TCP_EDC_STALL_DELAY_2 0x007b
+#define ixDIDT_TCP_EDC_STALL_DELAY_3 0x007c
+#define ixDIDT_TCP_EDC_STALL_DELAY_4 0x007d
+#define ixDIDT_TCP_EDC_OVERFLOW 0x007e
+#define ixDIDT_TCP_EDC_ROLLING_POWER_DELTA 0x007f
+#define ixDIDT_DBR_CTRL0 0x0080
+#define ixDIDT_DBR_CTRL1 0x0081
+#define ixDIDT_DBR_CTRL2 0x0082
+#define ixDIDT_DBR_STALL_CTRL 0x0084
+#define ixDIDT_DBR_TUNING_CTRL 0x0085
+#define ixDIDT_DBR_STALL_AUTO_RELEASE_CTRL 0x0086
+#define ixDIDT_DBR_CTRL3 0x0087
+#define ixDIDT_DBR_STALL_PATTERN_1_2 0x0088
+#define ixDIDT_DBR_STALL_PATTERN_3_4 0x0089
+#define ixDIDT_DBR_STALL_PATTERN_5_6 0x008a
+#define ixDIDT_DBR_STALL_PATTERN_7 0x008b
+#define ixDIDT_DBR_WEIGHT0_3 0x0090
+#define ixDIDT_DBR_WEIGHT4_7 0x0091
+#define ixDIDT_DBR_WEIGHT8_11 0x0092
+#define ixDIDT_DBR_EDC_CTRL 0x0093
+#define ixDIDT_DBR_EDC_THRESHOLD 0x0094
+#define ixDIDT_DBR_EDC_STALL_PATTERN_1_2 0x0095
+#define ixDIDT_DBR_EDC_STALL_PATTERN_3_4 0x0096
+#define ixDIDT_DBR_EDC_STALL_PATTERN_5_6 0x0097
+#define ixDIDT_DBR_EDC_STALL_PATTERN_7 0x0098
+#define ixDIDT_DBR_EDC_STATUS 0x0099
+#define ixDIDT_DBR_EDC_STALL_DELAY_1 0x009a
+#define ixDIDT_DBR_EDC_OVERFLOW 0x009e
+#define ixDIDT_DBR_EDC_ROLLING_POWER_DELTA 0x009f
+#define ixDIDT_SQ_STALL_EVENT_COUNTER 0x00a0
+#define ixDIDT_DB_STALL_EVENT_COUNTER 0x00a1
+#define ixDIDT_TD_STALL_EVENT_COUNTER 0x00a2
+#define ixDIDT_TCP_STALL_EVENT_COUNTER 0x00a3
+#define ixDIDT_DBR_STALL_EVENT_COUNTER 0x00a4
+
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_sh_mask.h
new file mode 100644
index 000000000000..5c5e9b445432
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_sh_mask.h
@@ -0,0 +1,29868 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _gc_9_0_SH_MASK_HEADER
+#define _gc_9_0_SH_MASK_HEADER
+
+
+// addressBlock: gc_grbmdec
+//GRBM_CNTL
+#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
+#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f
+#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL
+#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L
+//GRBM_SKEW_CNTL
+#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
+#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
+#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL
+#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L
+//GRBM_STATUS2
+#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
+#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
+#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
+#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
+#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
+#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
+#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
+#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
+#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
+#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
+#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
+#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
+#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf
+#define GRBM_STATUS2__EA_BUSY__SHIFT 0x10
+#define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11
+#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12
+#define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13
+#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14
+#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
+#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19
+#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a
+#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
+#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
+#define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f
+#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL
+#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L
+#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L
+#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L
+#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L
+#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L
+#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L
+#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L
+#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L
+#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L
+#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L
+#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L
+#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L
+#define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L
+#define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L
+#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L
+#define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L
+#define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L
+#define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L
+#define GRBM_STATUS2__TC_BUSY_MASK 0x02000000L
+#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x04000000L
+#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L
+#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L
+#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L
+#define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L
+//GRBM_PWR_CNTL
+#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0
+#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2
+#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4
+#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6
+#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe
+#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf
+#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L
+#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL
+#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L
+#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L
+#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L
+#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L
+//GRBM_STATUS
+#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
+#define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x5
+#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
+#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
+#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
+#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
+#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
+#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
+#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
+#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10
+#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11
+#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12
+#define GRBM_STATUS__IA_BUSY__SHIFT 0x13
+#define GRBM_STATUS__SX_BUSY__SHIFT 0x14
+#define GRBM_STATUS__WD_BUSY__SHIFT 0x15
+#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16
+#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17
+#define GRBM_STATUS__SC_BUSY__SHIFT 0x18
+#define GRBM_STATUS__PA_BUSY__SHIFT 0x19
+#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a
+#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c
+#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d
+#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f
+#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL
+#define GRBM_STATUS__RSMU_RQ_PENDING_MASK 0x00000020L
+#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L
+#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L
+#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L
+#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L
+#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L
+#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L
+#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L
+#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L
+#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L
+#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L
+#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L
+#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L
+#define GRBM_STATUS__WD_BUSY_MASK 0x00200000L
+#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L
+#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L
+#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L
+#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L
+#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L
+#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L
+#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L
+#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L
+#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L
+//GRBM_STATUS_SE0
+#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15
+#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17
+#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f
+#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L
+#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L
+#define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L
+#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L
+#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L
+#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L
+#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L
+#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L
+#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L
+#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L
+#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L
+#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L
+//GRBM_STATUS_SE1
+#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15
+#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17
+#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f
+#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L
+#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L
+#define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L
+#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L
+#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L
+#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L
+#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L
+#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L
+#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L
+#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L
+#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L
+#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L
+//GRBM_SOFT_RESET
+#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0
+#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2
+#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
+#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11
+#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12
+#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13
+#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14
+#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT 0x15
+#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16
+#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L
+#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L
+#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L
+#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L
+#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L
+#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L
+#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L
+#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK 0x00200000L
+#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L
+//GRBM_CGTT_CLK_CNTL
+#define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0
+#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000FL
+#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
+//GRBM_GFX_CLKEN_CNTL
+#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL
+#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L
+//GRBM_WAIT_IDLE_CLOCKS
+#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0
+#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL
+//GRBM_STATUS_SE2
+#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15
+#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17
+#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f
+#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L
+#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L
+#define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L
+#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L
+#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L
+#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L
+#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L
+#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L
+#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L
+#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L
+#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L
+#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L
+//GRBM_STATUS_SE3
+#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15
+#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17
+#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f
+#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L
+#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L
+#define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L
+#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L
+#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L
+#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L
+#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L
+#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L
+#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L
+#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L
+#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L
+#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L
+//GRBM_READ_ERROR
+#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
+#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
+#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16
+#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
+#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL
+#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L
+#define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L
+#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L
+//GRBM_READ_ERROR2
+#define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10
+#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT 0x11
+#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12
+#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f
+#define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 0x00020000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L
+//GRBM_INT_CNTL
+#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0
+#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13
+#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L
+#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L
+//GRBM_TRAP_OP
+#define GRBM_TRAP_OP__RW__SHIFT 0x0
+#define GRBM_TRAP_OP__RW_MASK 0x00000001L
+//GRBM_TRAP_ADDR
+#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0
+#define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL
+//GRBM_TRAP_ADDR_MSK
+#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0
+#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL
+//GRBM_TRAP_WD
+#define GRBM_TRAP_WD__DATA__SHIFT 0x0
+#define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL
+//GRBM_TRAP_WD_MSK
+#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0
+#define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL
+//GRBM_DSM_BYPASS
+#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0
+#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2
+#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L
+#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L
+//GRBM_WRITE_ERROR
+#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0
+#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT 0x1
+#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2
+#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5
+#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc
+#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd
+#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14
+#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16
+#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f
+#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L
+#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK 0x00000002L
+#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL
+#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000001E0L
+#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L
+#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L
+#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L
+#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L
+#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L
+//GRBM_IOV_ERROR
+#define GRBM_IOV_ERROR__IOV_ADDR__SHIFT 0x2
+#define GRBM_IOV_ERROR__IOV_VFID__SHIFT 0x14
+#define GRBM_IOV_ERROR__IOV_VF__SHIFT 0x1a
+#define GRBM_IOV_ERROR__IOV_OP__SHIFT 0x1b
+#define GRBM_IOV_ERROR__IOV_ERROR__SHIFT 0x1f
+#define GRBM_IOV_ERROR__IOV_ADDR_MASK 0x000FFFFCL
+#define GRBM_IOV_ERROR__IOV_VFID_MASK 0x03F00000L
+#define GRBM_IOV_ERROR__IOV_VF_MASK 0x04000000L
+#define GRBM_IOV_ERROR__IOV_OP_MASK 0x08000000L
+#define GRBM_IOV_ERROR__IOV_ERROR_MASK 0x80000000L
+//GRBM_CHIP_REVISION
+#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0
+#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL
+//GRBM_GFX_CNTL
+#define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0
+#define GRBM_GFX_CNTL__MEID__SHIFT 0x2
+#define GRBM_GFX_CNTL__VMID__SHIFT 0x4
+#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8
+#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L
+#define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL
+#define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L
+#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L
+//GRBM_RSMU_CFG
+#define GRBM_RSMU_CFG__APERTURE_ID__SHIFT 0x0
+#define GRBM_RSMU_CFG__QOS__SHIFT 0xc
+#define GRBM_RSMU_CFG__POSTED_WR__SHIFT 0x10
+#define GRBM_RSMU_CFG__DEBUG_MASK__SHIFT 0x11
+#define GRBM_RSMU_CFG__APERTURE_ID_MASK 0x00000FFFL
+#define GRBM_RSMU_CFG__QOS_MASK 0x0000F000L
+#define GRBM_RSMU_CFG__POSTED_WR_MASK 0x00010000L
+#define GRBM_RSMU_CFG__DEBUG_MASK_MASK 0x00020000L
+//GRBM_IH_CREDIT
+#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
+#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10
+#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
+#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L
+//GRBM_PWR_CNTL2
+#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10
+#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14
+#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L
+#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L
+//GRBM_UTCL2_INVAL_RANGE_START
+#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0
+#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL
+//GRBM_UTCL2_INVAL_RANGE_END
+#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0
+#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL
+//GRBM_RSMU_READ_ERROR
+#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT 0x2
+#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT 0x14
+#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT 0x15
+#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT 0x1b
+#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT 0x1f
+#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK 0x000FFFFCL
+#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK 0x00100000L
+#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK 0x07E00000L
+#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK 0x08000000L
+#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK 0x80000000L
+//GRBM_CHICKEN_BITS
+#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT 0x0
+#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK 0x00000001L
+//GRBM_NOWHERE
+#define GRBM_NOWHERE__DATA__SHIFT 0x0
+#define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG0
+#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
+#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG1
+#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
+#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG2
+#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
+#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG3
+#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
+#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG4
+#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
+#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG5
+#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
+#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG6
+#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
+#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG7
+#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
+#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_cpdec
+//CP_CPC_STATUS
+#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
+#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
+#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
+#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
+#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
+#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
+#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
+#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
+#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
+#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
+#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
+#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd
+#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe
+#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
+#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
+#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
+#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L
+#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L
+#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L
+#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L
+#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L
+#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L
+#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L
+#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L
+#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L
+#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L
+#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L
+#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L
+#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L
+#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L
+#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L
+#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L
+//CP_CPC_BUSY_STAT
+#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
+#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
+#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
+#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
+#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
+#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
+#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
+#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
+#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
+#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
+#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
+#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
+#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
+#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
+#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
+#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
+#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
+#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
+#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
+#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
+#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
+#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
+#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
+#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
+#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
+#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
+#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
+#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
+#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L
+#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L
+#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L
+#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L
+#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L
+#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L
+#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L
+#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L
+#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L
+#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L
+#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L
+#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L
+#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L
+#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L
+#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L
+#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L
+#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L
+#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L
+#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L
+#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L
+#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L
+#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L
+#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L
+#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L
+#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L
+#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L
+#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L
+#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L
+//CP_CPC_STALLED_STAT1
+#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
+#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
+#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
+#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
+#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
+#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16
+#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17
+#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18
+#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L
+#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L
+#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L
+#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L
+#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L
+#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L
+#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L
+#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L
+//CP_CPF_STATUS
+#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
+#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
+#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
+#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
+#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
+#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
+#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
+#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
+#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
+#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
+#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
+#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
+#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10
+#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11
+#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a
+#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b
+#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c
+#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
+#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
+#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L
+#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L
+#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L
+#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L
+#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L
+#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L
+#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L
+#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L
+#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L
+#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L
+#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L
+#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L
+#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L
+#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L
+#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L
+#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L
+#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L
+#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L
+#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L
+//CP_CPF_BUSY_STAT
+#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
+#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
+#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
+#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
+#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
+#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
+#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
+#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
+#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
+#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
+#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
+#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
+#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
+#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
+#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
+#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
+#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
+#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
+#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
+#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
+#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
+#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
+#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
+#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
+#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
+#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
+#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L
+#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L
+#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L
+#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L
+#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x00000200L
+#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L
+#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L
+#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L
+#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L
+#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L
+#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L
+#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L
+#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L
+#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L
+#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L
+#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L
+#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L
+#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L
+#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L
+#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L
+#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L
+#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L
+#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L
+#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L
+//CP_CPF_STALLED_STAT1
+#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
+#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
+#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
+#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
+#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7
+#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8
+#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9
+#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa
+#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb
+#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L
+#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L
+#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L
+#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L
+#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L
+#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L
+#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L
+#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L
+#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L
+//CP_CPC_GRBM_FREE_COUNT
+#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
+#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL
+//CP_MEC_CNTL
+#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
+#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10
+#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11
+#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12
+#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13
+#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14
+#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15
+#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
+#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
+#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
+#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
+#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L
+#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L
+#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L
+#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L
+#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L
+#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L
+#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L
+#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L
+#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L
+#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L
+#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L
+//CP_MEC_ME1_HEADER_DUMP
+#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
+#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
+//CP_MEC_ME2_HEADER_DUMP
+#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
+#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
+//CP_CPC_SCRATCH_INDEX
+#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
+#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL
+//CP_CPC_SCRATCH_DATA
+#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
+#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL
+//CP_CPF_GRBM_FREE_COUNT
+#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
+#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L
+//CP_CPC_HALT_HYST_COUNT
+#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
+#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL
+//CP_PRT_LOD_STATS_CNTL0
+#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0
+#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xFFFFFFFFL
+//CP_PRT_LOD_STATS_CNTL1
+#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0
+#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xFFFFFFFFL
+//CP_PRT_LOD_STATS_CNTL2
+#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0
+#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x000003FFL
+//CP_PRT_LOD_STATS_CNTL3
+#define CP_PRT_LOD_STATS_CNTL3__INTERVAL__SHIFT 0x2
+#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT__SHIFT 0xa
+#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE__SHIFT 0x12
+#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET__SHIFT 0x13
+#define CP_PRT_LOD_STATS_CNTL3__MC_VMID__SHIFT 0x17
+#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY__SHIFT 0x1c
+#define CP_PRT_LOD_STATS_CNTL3__INTERVAL_MASK 0x000003FCL
+#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT_MASK 0x0003FC00L
+#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE_MASK 0x00040000L
+#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET_MASK 0x00080000L
+#define CP_PRT_LOD_STATS_CNTL3__MC_VMID_MASK 0x07800000L
+#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY_MASK 0x10000000L
+//CP_CE_COMPARE_COUNT
+#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
+#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL
+//CP_CE_DE_COUNT
+#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
+#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
+//CP_DE_CE_COUNT
+#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
+#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL
+//CP_DE_LAST_INVAL_COUNT
+#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
+#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL
+//CP_DE_DE_COUNT
+#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
+#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
+//CP_STALLED_STAT3
+#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
+#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
+#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
+#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
+#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
+#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
+#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
+#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
+#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10
+#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11
+#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12
+#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13
+#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14
+#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L
+#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L
+#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L
+#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L
+#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L
+#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L
+#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L
+#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L
+#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L
+#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L
+#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L
+#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L
+#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L
+//CP_STALLED_STAT1
+#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
+#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
+#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
+#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
+#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
+#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe
+#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
+#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
+#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L
+#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L
+#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L
+#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L
+#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L
+#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L
+#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L
+#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L
+//CP_STALLED_STAT2
+#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
+#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
+#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
+#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
+#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
+#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
+#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
+#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
+#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
+#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
+#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
+#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
+#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
+#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
+#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
+#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
+#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
+#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
+#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
+#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
+#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
+#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
+#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L
+#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L
+#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L
+#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L
+#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L
+#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L
+#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L
+#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L
+#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L
+#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L
+#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L
+#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L
+#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L
+#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L
+#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L
+#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L
+#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L
+#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L
+#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L
+#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L
+//CP_BUSY_STAT
+#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
+#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
+#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
+#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
+#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
+#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
+#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
+#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
+#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
+#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
+#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
+#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
+#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
+#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
+#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
+#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
+#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
+#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L
+#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L
+#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L
+#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L
+#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L
+#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L
+#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L
+#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L
+#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L
+#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L
+#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L
+#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L
+#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L
+#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L
+#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L
+//CP_STAT
+#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
+#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
+#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
+#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
+#define CP_STAT__DC_BUSY__SHIFT 0xd
+#define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe
+#define CP_STAT__PFP_BUSY__SHIFT 0xf
+#define CP_STAT__MEQ_BUSY__SHIFT 0x10
+#define CP_STAT__ME_BUSY__SHIFT 0x11
+#define CP_STAT__QUERY_BUSY__SHIFT 0x12
+#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
+#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
+#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
+#define CP_STAT__DMA_BUSY__SHIFT 0x16
+#define CP_STAT__RCIU_BUSY__SHIFT 0x17
+#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
+#define CP_STAT__CE_BUSY__SHIFT 0x1a
+#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
+#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
+#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
+#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
+#define CP_STAT__CP_BUSY__SHIFT 0x1f
+#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L
+#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L
+#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L
+#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L
+#define CP_STAT__DC_BUSY_MASK 0x00002000L
+#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L
+#define CP_STAT__PFP_BUSY_MASK 0x00008000L
+#define CP_STAT__MEQ_BUSY_MASK 0x00010000L
+#define CP_STAT__ME_BUSY_MASK 0x00020000L
+#define CP_STAT__QUERY_BUSY_MASK 0x00040000L
+#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L
+#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L
+#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L
+#define CP_STAT__DMA_BUSY_MASK 0x00400000L
+#define CP_STAT__RCIU_BUSY_MASK 0x00800000L
+#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L
+#define CP_STAT__CE_BUSY_MASK 0x04000000L
+#define CP_STAT__TCIU_BUSY_MASK 0x08000000L
+#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L
+#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L
+#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L
+#define CP_STAT__CP_BUSY_MASK 0x80000000L
+//CP_ME_HEADER_DUMP
+#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
+#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xFFFFFFFFL
+//CP_PFP_HEADER_DUMP
+#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
+#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xFFFFFFFFL
+//CP_GRBM_FREE_COUNT
+#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L
+//CP_CE_HEADER_DUMP
+#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
+#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xFFFFFFFFL
+//CP_PFP_INSTR_PNTR
+#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
+#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
+//CP_ME_INSTR_PNTR
+#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
+#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
+//CP_CE_INSTR_PNTR
+#define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
+#define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
+//CP_MEC1_INSTR_PNTR
+#define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
+#define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
+//CP_MEC2_INSTR_PNTR
+#define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
+#define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
+//CP_CSF_STAT
+#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
+#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L
+//CP_ME_CNTL
+#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
+#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
+#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
+#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10
+#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11
+#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12
+#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13
+#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14
+#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15
+#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
+#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
+#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
+#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
+#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
+#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
+#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L
+#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L
+#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L
+#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L
+#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L
+#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L
+#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L
+#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L
+#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L
+#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L
+#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L
+#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L
+#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L
+#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L
+#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L
+//CP_CNTX_STAT
+#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
+#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
+#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
+#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
+#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL
+#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L
+#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L
+#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L
+//CP_ME_PREEMPTION
+#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0
+#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L
+//CP_ROQ_THRESHOLDS
+#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
+#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
+#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL
+#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L
+//CP_MEQ_STQ_THRESHOLD
+#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
+#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL
+//CP_RB2_RPTR
+#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL
+//CP_RB1_RPTR
+#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL
+//CP_RB0_RPTR
+#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL
+//CP_RB_RPTR
+#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL
+//CP_RB_WPTR_DELAY
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L
+//CP_RB_WPTR_POLL_CNTL
+#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
+#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL
+#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//CP_ROQ1_THRESHOLDS
+#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
+#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
+#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10
+#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18
+#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000FFL
+#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000FF00L
+#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00FF0000L
+#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xFF000000L
+//CP_ROQ2_THRESHOLDS
+#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0
+#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8
+#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10
+#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18
+#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000FFL
+#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000FF00L
+#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00FF0000L
+#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xFF000000L
+//CP_STQ_THRESHOLDS
+#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
+#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
+#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
+#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL
+#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L
+#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L
+//CP_QUEUE_THRESHOLDS
+#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
+#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
+#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL
+#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L
+//CP_MEQ_THRESHOLDS
+#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
+#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
+#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL
+#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L
+//CP_ROQ_AVAIL
+#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
+#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
+#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007FFL
+#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07FF0000L
+//CP_STQ_AVAIL
+#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
+#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL
+//CP_ROQ2_AVAIL
+#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
+#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007FFL
+//CP_MEQ_AVAIL
+#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
+#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL
+//CP_CMD_INDEX
+#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
+#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
+#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
+#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL
+#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L
+#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L
+//CP_CMD_DATA
+#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
+#define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL
+//CP_ROQ_RB_STAT
+#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
+#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
+#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003FFL
+#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03FF0000L
+//CP_ROQ_IB1_STAT
+#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
+#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
+#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003FFL
+#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03FF0000L
+//CP_ROQ_IB2_STAT
+#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
+#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
+#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003FFL
+#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03FF0000L
+//CP_STQ_STAT
+#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
+#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL
+//CP_STQ_WR_STAT
+#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
+#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL
+//CP_MEQ_STAT
+#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
+#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
+#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL
+#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L
+//CP_CEQ1_AVAIL
+#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
+#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
+#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007FFL
+#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07FF0000L
+//CP_CEQ2_AVAIL
+#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
+#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007FFL
+//CP_CE_ROQ_RB_STAT
+#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
+#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
+#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003FFL
+#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03FF0000L
+//CP_CE_ROQ_IB1_STAT
+#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
+#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
+#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003FFL
+#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03FF0000L
+//CP_CE_ROQ_IB2_STAT
+#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
+#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
+#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003FFL
+#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03FF0000L
+//CP_INT_STAT_DEBUG
+#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb
+#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
+#define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10
+#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
+#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12
+#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13
+#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14
+#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15
+#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
+#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
+#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
+#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
+#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
+#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
+#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
+#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
+#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x00000800L
+#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L
+#define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L
+#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L
+#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x00040000L
+#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x00080000L
+#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x00100000L
+#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x00200000L
+#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L
+#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
+#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L
+#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L
+#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L
+#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L
+#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L
+#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L
+
+
+// addressBlock: gc_padec
+//VGT_VTX_VECT_EJECT_REG
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000007FL
+//VGT_DMA_DATA_FIFO_DEPTH
+#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0
+#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x9
+#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001FFL
+#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x0007FE00L
+//VGT_DMA_REQ_FIFO_DEPTH
+#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0
+#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL
+//VGT_DRAW_INIT_FIFO_DEPTH
+#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0
+#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL
+//VGT_LAST_COPY_STATE
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
+#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
+#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L
+//VGT_CACHE_INVALIDATION
+#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0
+#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4
+#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5
+#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6
+#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9
+#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb
+#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc
+#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd
+#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10
+#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15
+#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16
+#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19
+#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c
+#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d
+#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L
+#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L
+#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L
+#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L
+#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L
+#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L
+#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L
+#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L
+#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L
+#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L
+#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L
+#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L
+#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L
+#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L
+//VGT_RESET_DEBUG
+#define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0
+#define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1
+#define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2
+#define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x00000001L
+#define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x00000002L
+#define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x00000004L
+//VGT_STRMOUT_DELAY
+#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0
+#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8
+#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb
+#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe
+#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11
+#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL
+#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L
+#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L
+#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L
+#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L
+//VGT_FIFO_DEPTHS
+#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0
+#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7
+#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8
+#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16
+#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL
+#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L
+#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L
+#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x0FC00000L
+//VGT_GS_VERTEX_REUSE
+#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0
+#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL
+//VGT_MC_LAT_CNTL
+#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0
+#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL
+//IA_CNTL_STATUS
+#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0
+#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1
+#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2
+#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3
+#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4
+#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L
+#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L
+#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L
+#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L
+#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L
+//VGT_CNTL_STATUS
+#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2
+#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3
+#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4
+#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5
+#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6
+#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7
+#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8
+#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9
+#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa
+#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L
+#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L
+#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L
+#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L
+#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L
+#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L
+#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L
+#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L
+#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L
+//WD_CNTL_STATUS
+#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0
+#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1
+#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2
+#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3
+#define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L
+#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L
+#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L
+#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L
+//CC_GC_PRIM_CONFIG
+#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
+#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
+#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L
+#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L
+//GC_USER_PRIM_CONFIG
+#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
+#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
+#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L
+#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L
+//WD_QOS
+#define WD_QOS__DRAW_STALL__SHIFT 0x0
+#define WD_QOS__DRAW_STALL_MASK 0x00000001L
+//WD_UTCL1_CNTL
+#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
+#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
+#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19
+#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
+#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
+#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
+#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
+#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
+#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L
+#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
+#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
+#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
+//WD_UTCL1_STATUS
+#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
+#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
+#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
+#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
+#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
+#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
+//IA_UTCL1_CNTL
+#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
+#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
+#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19
+#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
+#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
+#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
+#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
+#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
+#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L
+#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
+#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
+#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
+//IA_UTCL1_STATUS
+#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
+#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
+#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
+#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
+#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
+#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
+//VGT_SYS_CONFIG
+#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0
+#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1
+#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7
+#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L
+#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL
+#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L
+//VGT_VS_MAX_WAVE_ID
+#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
+#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
+//VGT_GS_MAX_WAVE_ID
+#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
+#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
+//GFX_PIPE_CONTROL
+#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0
+#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd
+#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10
+#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL
+#define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L
+#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L
+//CC_GC_SHADER_ARRAY_CONFIG
+#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
+#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L
+//GC_USER_SHADER_ARRAY_CONFIG
+#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
+#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L
+//VGT_DMA_PRIMITIVE_TYPE
+#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
+#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL
+//VGT_DMA_CONTROL
+#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0
+#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11
+#define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13
+#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14
+#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT 0x15
+#define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT 0x16
+#define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT 0x17
+#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL
+#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L
+#define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L
+#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L
+#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK 0x00200000L
+#define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK 0x00400000L
+#define VGT_DMA_CONTROL__HW_USE_ONLY_MASK 0x00800000L
+//VGT_DMA_LS_HS_CONFIG
+#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
+#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L
+//WD_BUF_RESOURCE_1
+#define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0
+#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10
+#define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL
+#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L
+//WD_BUF_RESOURCE_2
+#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0
+#define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf
+#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10
+#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL
+#define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L
+#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L
+//PA_CL_CNTL_STATUS
+#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0
+#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1
+#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2
+#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L
+#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L
+#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L
+//PA_CL_ENHANCE
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0
+#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1
+#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3
+#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4
+#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5
+#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6
+#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7
+#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8
+#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9
+#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb
+#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc
+#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe
+#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c
+#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d
+#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e
+#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L
+#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L
+#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L
+#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L
+#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x00000020L
+#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L
+#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L
+#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L
+#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L
+#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L
+#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L
+#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L
+#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L
+#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L
+#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L
+#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L
+//PA_CL_RESET_DEBUG
+#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0
+#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x00000001L
+//PA_SU_CNTL_STATUS
+#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f
+#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L
+//PA_SC_FIFO_DEPTH_CNTL
+#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0
+#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL
+//PA_SC_P3D_TRAP_SCREEN_HV_LOCK
+#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
+//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK
+#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
+//PA_SC_TRAP_SCREEN_HV_LOCK
+#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
+//PA_SC_FORCE_EOV_MAX_CNTS
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L
+//PA_SC_BINNER_EVENT_CNTL_0
+#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0
+#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2
+#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4
+#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6
+#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8
+#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa
+#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc
+#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe
+#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10
+#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12
+#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14
+#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16
+#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18
+#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a
+#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c
+#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e
+#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L
+#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL
+#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L
+#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L
+#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L
+#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L
+#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L
+#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L
+#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L
+#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L
+#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L
+#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L
+#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L
+#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L
+#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L
+#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L
+//PA_SC_BINNER_EVENT_CNTL_1
+#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4
+#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6
+#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8
+#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa
+#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc
+#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe
+#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10
+#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12
+#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14
+#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT 0x1a
+#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c
+#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e
+#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L
+#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L
+#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L
+#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L
+#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L
+#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L
+#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L
+#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L
+#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L
+#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK 0x0C000000L
+#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L
+#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L
+//PA_SC_BINNER_EVENT_CNTL_2
+#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0
+#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2
+#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4
+#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT 0x6
+#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8
+#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa
+#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc
+#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe
+#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT 0x12
+#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c
+#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e
+#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L
+#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL
+#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L
+#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK 0x000000C0L
+#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L
+#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L
+#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L
+#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L
+#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK 0x000C0000L
+#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L
+#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L
+//PA_SC_BINNER_EVENT_CNTL_3
+#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0
+#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2
+#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT 0x4
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT 0xc
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe
+#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10
+#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12
+#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14
+#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16
+#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18
+#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a
+#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c
+#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT 0x1e
+#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L
+#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL
+#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK 0x00000030L
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK 0x00003000L
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L
+#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L
+#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L
+#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L
+#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L
+#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L
+#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L
+#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L
+#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK 0xC0000000L
+//PA_SC_BINNER_TIMEOUT_COUNTER
+#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0
+#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL
+//PA_SC_BINNER_PERF_CNTL_0
+#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0
+#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa
+#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14
+#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17
+#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL
+#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L
+#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L
+#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L
+//PA_SC_BINNER_PERF_CNTL_1
+#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0
+#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5
+#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa
+#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL
+#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L
+#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L
+//PA_SC_BINNER_PERF_CNTL_2
+#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0
+#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb
+#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL
+#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L
+//PA_SC_BINNER_PERF_CNTL_3
+#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0
+#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL
+//PA_SC_FIFO_SIZE
+#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0
+#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6
+#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf
+#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15
+#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL
+#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L
+#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L
+#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L
+//PA_SC_IF_FIFO_SIZE
+#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0
+#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6
+#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc
+#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12
+#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL
+#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L
+#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L
+#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L
+//PA_SC_PKR_WAVE_TABLE_CNTL
+#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0
+#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL
+//PA_UTCL1_CNTL1
+#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
+#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1
+#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
+#define PA_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
+#define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
+#define PA_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
+#define PA_UTCL1_CNTL1__SPARE__SHIFT 0x10
+#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
+#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
+#define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
+#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
+#define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
+#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT 0x19
+#define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
+#define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
+#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
+#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L
+#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
+#define PA_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
+#define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
+#define PA_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
+#define PA_UTCL1_CNTL1__SPARE_MASK 0x00010000L
+#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
+#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
+#define PA_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
+#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
+#define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
+#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK 0x02000000L
+#define PA_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
+#define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
+#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
+#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
+//PA_UTCL1_CNTL2
+#define PA_UTCL1_CNTL2__SPARE1__SHIFT 0x0
+#define PA_UTCL1_CNTL2__SPARE2__SHIFT 0x8
+#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
+#define PA_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
+#define PA_UTCL1_CNTL2__SPARE3__SHIFT 0xb
+#define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
+#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT 0xd
+#define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
+#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
+#define PA_UTCL1_CNTL2__SPARE4__SHIFT 0x10
+#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
+#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
+#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
+#define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
+#define PA_UTCL1_CNTL2__SPARE5__SHIFT 0x19
+#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
+#define PA_UTCL1_CNTL2__RESERVED__SHIFT 0x1b
+#define PA_UTCL1_CNTL2__SPARE1_MASK 0x000000FFL
+#define PA_UTCL1_CNTL2__SPARE2_MASK 0x00000100L
+#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
+#define PA_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
+#define PA_UTCL1_CNTL2__SPARE3_MASK 0x00000800L
+#define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
+#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK 0x00002000L
+#define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
+#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
+#define PA_UTCL1_CNTL2__SPARE4_MASK 0x00030000L
+#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
+#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
+#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
+#define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
+#define PA_UTCL1_CNTL2__SPARE5_MASK 0x02000000L
+#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
+#define PA_UTCL1_CNTL2__RESERVED_MASK 0xF8000000L
+//PA_SIDEBAND_REQUEST_DELAYS
+#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0
+#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10
+#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL
+#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L
+//PA_SC_ENHANCE
+#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0
+#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1
+#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4
+#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5
+#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6
+#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa
+#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb
+#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc
+#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16
+#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17
+#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18
+#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19
+#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a
+#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b
+#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c
+#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d
+#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L
+#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L
+#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L
+#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L
+#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L
+#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L
+#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L
+#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L
+#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L
+#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L
+#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L
+#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L
+#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L
+#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L
+#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L
+#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L
+//PA_SC_ENHANCE_1
+#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0
+#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1
+#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3
+#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4
+#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5
+#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6
+#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7
+#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8
+#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9
+#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa
+#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb
+#define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK__SHIFT 0xc
+#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xd
+#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe
+#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf
+#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10
+#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x11
+#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12
+#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13
+#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14
+#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15
+#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16
+#define PA_SC_ENHANCE_1__RSVD__SHIFT 0x17
+#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L
+#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L
+#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L
+#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L
+#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L
+#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L
+#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L
+#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L
+#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L
+#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L
+#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L
+#define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK_MASK 0x00001000L
+#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00002000L
+#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L
+#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L
+#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L
+#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L
+#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L
+#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L
+#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L
+#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L
+#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L
+#define PA_SC_ENHANCE_1__RSVD_MASK 0xFF800000L
+//PA_SC_DSM_CNTL
+#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0
+#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1
+#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L
+#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L
+//PA_SC_TILE_STEERING_CREST_OVERRIDE
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L
+
+
+// addressBlock: gc_sqdec
+//SQ_CONFIG
+#define SQ_CONFIG__UNUSED__SHIFT 0x0
+#define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT 0x7
+#define SQ_CONFIG__DEBUG_EN__SHIFT 0x8
+#define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT 0x9
+#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT 0xa
+#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0xb
+#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc
+#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd
+#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe
+#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf
+#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10
+#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11
+#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12
+#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13
+#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15
+#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT 0x1c
+#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d
+#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT 0x1e
+#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT 0x1f
+#define SQ_CONFIG__UNUSED_MASK 0x0000007FL
+#define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK 0x00000080L
+#define SQ_CONFIG__DEBUG_EN_MASK 0x00000100L
+#define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK 0x00000200L
+#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK 0x00000400L
+#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L
+#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L
+#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L
+#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L
+#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L
+#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x00010000L
+#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x00020000L
+#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L
+#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L
+#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0FE00000L
+#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK 0x10000000L
+#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L
+#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK 0x40000000L
+#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK 0x80000000L
+//SQC_CONFIG
+#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0
+#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2
+#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4
+#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6
+#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7
+#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8
+#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9
+#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa
+#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb
+#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc
+#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe
+#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf
+#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10
+#define SQC_CONFIG__INST_PRF_COUNT__SHIFT 0x18
+#define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT 0x1a
+#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L
+#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL
+#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L
+#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L
+#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L
+#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L
+#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L
+#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L
+#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L
+#define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L
+#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L
+#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L
+#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L
+#define SQC_CONFIG__INST_PRF_COUNT_MASK 0x03000000L
+#define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK 0x04000000L
+//LDS_CONFIG
+#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0
+#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L
+//SQ_RANDOM_WAVE_PRI
+#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0
+#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7
+#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
+#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL
+#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L
+#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x007FFC00L
+//SQ_REG_CREDITS
+#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0
+#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8
+#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c
+#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d
+#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e
+#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f
+#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003FL
+#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000F00L
+#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L
+#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L
+#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L
+#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L
+//SQ_FIFO_SIZES
+#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0
+#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8
+#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10
+#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12
+#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL
+#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000F00L
+#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L
+#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L
+//SQ_DSM_CNTL
+#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0
+#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1
+#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2
+#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3
+#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8
+#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9
+#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11
+#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14
+#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15
+#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18
+#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19
+#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a
+#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L
+#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L
+#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L
+#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L
+#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L
+#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L
+#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L
+#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L
+#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L
+#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L
+#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L
+#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L
+//SQ_DSM_CNTL2
+#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2
+#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5
+#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8
+#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb
+#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe
+#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14
+#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a
+#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L
+#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L
+#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L
+//SQ_RUNTIME_CONFIG
+#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT 0x0
+#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK 0x00000001L
+//SH_MEM_BASES
+#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0
+#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10
+#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL
+#define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L
+//SH_MEM_CONFIG
+#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0
+#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3
+#define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT 0xc
+#define SH_MEM_CONFIG__PRIVATE_NV__SHIFT 0xd
+#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L
+#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x00000018L
+#define SH_MEM_CONFIG__RETRY_DISABLE_MASK 0x00001000L
+#define SH_MEM_CONFIG__PRIVATE_NV_MASK 0x00002000L
+//CC_GC_SHADER_RATE_CONFIG
+#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
+#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
+#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
+#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L
+#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
+#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L
+//GC_USER_SHADER_RATE_CONFIG
+#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
+#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
+#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
+#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L
+#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
+#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L
+//SQ_INTERRUPT_AUTO_MASK
+#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0
+#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL
+//SQ_INTERRUPT_MSG_CTRL
+#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0
+#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L
+//SQ_UTCL1_CNTL1
+#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
+#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
+#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
+#define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
+#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
+#define SQ_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
+#define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10
+#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
+#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
+#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
+#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
+#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
+#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT 0x19
+#define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
+#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
+#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
+#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
+#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
+#define SQ_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
+#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
+#define SQ_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
+#define SQ_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L
+#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
+#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
+#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
+#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
+#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
+#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK 0x02000000L
+#define SQ_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
+#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
+#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
+#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
+//SQ_UTCL1_CNTL2
+#define SQ_UTCL1_CNTL2__SPARE__SHIFT 0x0
+#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
+#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
+#define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
+#define SQ_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
+#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
+#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
+#define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
+#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
+#define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT 0x10
+#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
+#define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT 0x1c
+#define SQ_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
+#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
+#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
+#define SQ_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
+#define SQ_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
+#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
+#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
+#define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
+#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
+#define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK 0x007F0000L
+#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
+#define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK 0xF0000000L
+//SQ_UTCL1_STATUS
+#define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define SQ_UTCL1_STATUS__RESERVED__SHIFT 0x3
+#define SQ_UTCL1_STATUS__UNUSED__SHIFT 0x10
+#define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define SQ_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+#define SQ_UTCL1_STATUS__RESERVED_MASK 0x0000FFF8L
+#define SQ_UTCL1_STATUS__UNUSED_MASK 0xFFFF0000L
+//SQ_SHADER_TBA_LO
+#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0
+#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL
+//SQ_SHADER_TBA_HI
+#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0
+#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL
+//SQ_SHADER_TMA_LO
+#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0
+#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL
+//SQ_SHADER_TMA_HI
+#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0
+#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL
+//SQC_DSM_CNTL
+#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+//SQC_DSM_CNTLA
+#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15
+#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17
+#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18
+#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a
+#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L
+#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
+#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L
+#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L
+//SQC_DSM_CNTLB
+#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15
+#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17
+#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18
+#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a
+#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L
+#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
+#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L
+#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L
+//SQC_DSM_CNTL2
+#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x2
+#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x5
+#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x8
+#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0xb
+#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xe
+#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x11
+#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x14
+#define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
+#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define SQC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
+//SQC_DSM_CNTL2A
+#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5
+#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
+#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11
+#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14
+#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17
+#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18
+#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a
+#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L
+#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L
+#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L
+//SQC_DSM_CNTL2B
+#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5
+#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
+#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11
+#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14
+#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17
+#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18
+#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a
+#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L
+#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L
+#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L
+//SQC_EDC_FUE_CNTL
+#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0
+#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10
+#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL
+#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L
+//SQC_EDC_CNT2
+#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x0
+#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT 0x2
+#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0x4
+#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT 0x6
+#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x8
+#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT 0xa
+#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0xc
+#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT 0xe
+#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10
+#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x12
+#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT__SHIFT 0x14
+#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x16
+#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18
+#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1a
+#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1c
+#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000003L
+#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK 0x0000000CL
+#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00000030L
+#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK 0x000000C0L
+#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000300L
+#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK 0x00000C00L
+#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00003000L
+#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK 0x0000C000L
+#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L
+#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT_MASK 0x000C0000L
+#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT_MASK 0x00300000L
+#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT_MASK 0x00C00000L
+#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L
+#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK 0x0C000000L
+#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK 0x30000000L
+//SQC_EDC_CNT3
+#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x0
+#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT 0x2
+#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0x4
+#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT 0x6
+#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x8
+#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT 0xa
+#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0xc
+#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT 0xe
+#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10
+#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x12
+#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT__SHIFT 0x14
+#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x16
+#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18
+#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000003L
+#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK 0x0000000CL
+#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00000030L
+#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK 0x000000C0L
+#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000300L
+#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK 0x00000C00L
+#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00003000L
+#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK 0x0000C000L
+#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L
+#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT_MASK 0x000C0000L
+#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT_MASK 0x00300000L
+#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT_MASK 0x00C00000L
+#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L
+//SQ_REG_TIMESTAMP
+#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0
+#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL
+//SQ_CMD_TIMESTAMP
+#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0
+#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL
+//SQ_IND_INDEX
+#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0
+#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4
+#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6
+#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc
+#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd
+#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe
+#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf
+#define SQ_IND_INDEX__INDEX__SHIFT 0x10
+#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000FL
+#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L
+#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000FC0L
+#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L
+#define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L
+#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L
+#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L
+#define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L
+//SQ_IND_DATA
+#define SQ_IND_DATA__DATA__SHIFT 0x0
+#define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL
+//SQ_CMD
+#define SQ_CMD__CMD__SHIFT 0x0
+#define SQ_CMD__MODE__SHIFT 0x4
+#define SQ_CMD__CHECK_VMID__SHIFT 0x7
+#define SQ_CMD__DATA__SHIFT 0x8
+#define SQ_CMD__WAVE_ID__SHIFT 0x10
+#define SQ_CMD__SIMD_ID__SHIFT 0x14
+#define SQ_CMD__QUEUE_ID__SHIFT 0x18
+#define SQ_CMD__VM_ID__SHIFT 0x1c
+#define SQ_CMD__CMD_MASK 0x00000007L
+#define SQ_CMD__MODE_MASK 0x00000070L
+#define SQ_CMD__CHECK_VMID_MASK 0x00000080L
+#define SQ_CMD__DATA_MASK 0x00000F00L
+#define SQ_CMD__WAVE_ID_MASK 0x000F0000L
+#define SQ_CMD__SIMD_ID_MASK 0x00300000L
+#define SQ_CMD__QUEUE_ID_MASK 0x07000000L
+#define SQ_CMD__VM_ID_MASK 0xF0000000L
+//SQ_TIME_HI
+#define SQ_TIME_HI__TIME__SHIFT 0x0
+#define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL
+//SQ_TIME_LO
+#define SQ_TIME_LO__TIME__SHIFT 0x0
+#define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL
+//SQ_DS_0
+#define SQ_DS_0__OFFSET0__SHIFT 0x0
+#define SQ_DS_0__OFFSET1__SHIFT 0x8
+#define SQ_DS_0__GDS__SHIFT 0x10
+#define SQ_DS_0__OP__SHIFT 0x11
+#define SQ_DS_0__ENCODING__SHIFT 0x1a
+#define SQ_DS_0__OFFSET0_MASK 0x000000FFL
+#define SQ_DS_0__OFFSET1_MASK 0x0000FF00L
+#define SQ_DS_0__GDS_MASK 0x00010000L
+#define SQ_DS_0__OP_MASK 0x01FE0000L
+#define SQ_DS_0__ENCODING_MASK 0xFC000000L
+//SQ_DS_1
+#define SQ_DS_1__ADDR__SHIFT 0x0
+#define SQ_DS_1__DATA0__SHIFT 0x8
+#define SQ_DS_1__DATA1__SHIFT 0x10
+#define SQ_DS_1__VDST__SHIFT 0x18
+#define SQ_DS_1__ADDR_MASK 0x000000FFL
+#define SQ_DS_1__DATA0_MASK 0x0000FF00L
+#define SQ_DS_1__DATA1_MASK 0x00FF0000L
+#define SQ_DS_1__VDST_MASK 0xFF000000L
+//SQ_EXP_0
+#define SQ_EXP_0__EN__SHIFT 0x0
+#define SQ_EXP_0__TGT__SHIFT 0x4
+#define SQ_EXP_0__COMPR__SHIFT 0xa
+#define SQ_EXP_0__DONE__SHIFT 0xb
+#define SQ_EXP_0__VM__SHIFT 0xc
+#define SQ_EXP_0__ENCODING__SHIFT 0x1a
+#define SQ_EXP_0__EN_MASK 0x0000000FL
+#define SQ_EXP_0__TGT_MASK 0x000003F0L
+#define SQ_EXP_0__COMPR_MASK 0x00000400L
+#define SQ_EXP_0__DONE_MASK 0x00000800L
+#define SQ_EXP_0__VM_MASK 0x00001000L
+#define SQ_EXP_0__ENCODING_MASK 0xFC000000L
+//SQ_EXP_1
+#define SQ_EXP_1__VSRC0__SHIFT 0x0
+#define SQ_EXP_1__VSRC1__SHIFT 0x8
+#define SQ_EXP_1__VSRC2__SHIFT 0x10
+#define SQ_EXP_1__VSRC3__SHIFT 0x18
+#define SQ_EXP_1__VSRC0_MASK 0x000000FFL
+#define SQ_EXP_1__VSRC1_MASK 0x0000FF00L
+#define SQ_EXP_1__VSRC2_MASK 0x00FF0000L
+#define SQ_EXP_1__VSRC3_MASK 0xFF000000L
+//SQ_FLAT_0
+#define SQ_FLAT_0__OFFSET__SHIFT 0x0
+#define SQ_FLAT_0__LDS__SHIFT 0xd
+#define SQ_FLAT_0__SEG__SHIFT 0xe
+#define SQ_FLAT_0__GLC__SHIFT 0x10
+#define SQ_FLAT_0__SLC__SHIFT 0x11
+#define SQ_FLAT_0__OP__SHIFT 0x12
+#define SQ_FLAT_0__ENCODING__SHIFT 0x1a
+#define SQ_FLAT_0__OFFSET_MASK 0x00000FFFL
+#define SQ_FLAT_0__LDS_MASK 0x00002000L
+#define SQ_FLAT_0__SEG_MASK 0x0000C000L
+#define SQ_FLAT_0__GLC_MASK 0x00010000L
+#define SQ_FLAT_0__SLC_MASK 0x00020000L
+#define SQ_FLAT_0__OP_MASK 0x01FC0000L
+#define SQ_FLAT_0__ENCODING_MASK 0xFC000000L
+//SQ_FLAT_1
+#define SQ_FLAT_1__ADDR__SHIFT 0x0
+#define SQ_FLAT_1__DATA__SHIFT 0x8
+#define SQ_FLAT_1__SADDR__SHIFT 0x10
+#define SQ_FLAT_1__NV__SHIFT 0x17
+#define SQ_FLAT_1__VDST__SHIFT 0x18
+#define SQ_FLAT_1__ADDR_MASK 0x000000FFL
+#define SQ_FLAT_1__DATA_MASK 0x0000FF00L
+#define SQ_FLAT_1__SADDR_MASK 0x007F0000L
+#define SQ_FLAT_1__NV_MASK 0x00800000L
+#define SQ_FLAT_1__VDST_MASK 0xFF000000L
+//SQ_GLBL_0
+#define SQ_GLBL_0__OFFSET__SHIFT 0x0
+#define SQ_GLBL_0__LDS__SHIFT 0xd
+#define SQ_GLBL_0__SEG__SHIFT 0xe
+#define SQ_GLBL_0__GLC__SHIFT 0x10
+#define SQ_GLBL_0__SLC__SHIFT 0x11
+#define SQ_GLBL_0__OP__SHIFT 0x12
+#define SQ_GLBL_0__ENCODING__SHIFT 0x1a
+#define SQ_GLBL_0__OFFSET_MASK 0x00001FFFL
+#define SQ_GLBL_0__LDS_MASK 0x00002000L
+#define SQ_GLBL_0__SEG_MASK 0x0000C000L
+#define SQ_GLBL_0__GLC_MASK 0x00010000L
+#define SQ_GLBL_0__SLC_MASK 0x00020000L
+#define SQ_GLBL_0__OP_MASK 0x01FC0000L
+#define SQ_GLBL_0__ENCODING_MASK 0xFC000000L
+//SQ_GLBL_1
+#define SQ_GLBL_1__ADDR__SHIFT 0x0
+#define SQ_GLBL_1__DATA__SHIFT 0x8
+#define SQ_GLBL_1__SADDR__SHIFT 0x10
+#define SQ_GLBL_1__NV__SHIFT 0x17
+#define SQ_GLBL_1__VDST__SHIFT 0x18
+#define SQ_GLBL_1__ADDR_MASK 0x000000FFL
+#define SQ_GLBL_1__DATA_MASK 0x0000FF00L
+#define SQ_GLBL_1__SADDR_MASK 0x007F0000L
+#define SQ_GLBL_1__NV_MASK 0x00800000L
+#define SQ_GLBL_1__VDST_MASK 0xFF000000L
+//SQ_INST
+#define SQ_INST__ENCODING__SHIFT 0x0
+#define SQ_INST__ENCODING_MASK 0xFFFFFFFFL
+//SQ_MIMG_0
+#define SQ_MIMG_0__OPM__SHIFT 0x0
+#define SQ_MIMG_0__DMASK__SHIFT 0x8
+#define SQ_MIMG_0__UNORM__SHIFT 0xc
+#define SQ_MIMG_0__GLC__SHIFT 0xd
+#define SQ_MIMG_0__DA__SHIFT 0xe
+#define SQ_MIMG_0__A16__SHIFT 0xf
+#define SQ_MIMG_0__TFE__SHIFT 0x10
+#define SQ_MIMG_0__LWE__SHIFT 0x11
+#define SQ_MIMG_0__OP__SHIFT 0x12
+#define SQ_MIMG_0__SLC__SHIFT 0x19
+#define SQ_MIMG_0__ENCODING__SHIFT 0x1a
+#define SQ_MIMG_0__OPM_MASK 0x00000001L
+#define SQ_MIMG_0__DMASK_MASK 0x00000F00L
+#define SQ_MIMG_0__UNORM_MASK 0x00001000L
+#define SQ_MIMG_0__GLC_MASK 0x00002000L
+#define SQ_MIMG_0__DA_MASK 0x00004000L
+#define SQ_MIMG_0__A16_MASK 0x00008000L
+#define SQ_MIMG_0__TFE_MASK 0x00010000L
+#define SQ_MIMG_0__LWE_MASK 0x00020000L
+#define SQ_MIMG_0__OP_MASK 0x01FC0000L
+#define SQ_MIMG_0__SLC_MASK 0x02000000L
+#define SQ_MIMG_0__ENCODING_MASK 0xFC000000L
+//SQ_MIMG_1
+#define SQ_MIMG_1__VADDR__SHIFT 0x0
+#define SQ_MIMG_1__VDATA__SHIFT 0x8
+#define SQ_MIMG_1__SRSRC__SHIFT 0x10
+#define SQ_MIMG_1__SSAMP__SHIFT 0x15
+#define SQ_MIMG_1__D16__SHIFT 0x1f
+#define SQ_MIMG_1__VADDR_MASK 0x000000FFL
+#define SQ_MIMG_1__VDATA_MASK 0x0000FF00L
+#define SQ_MIMG_1__SRSRC_MASK 0x001F0000L
+#define SQ_MIMG_1__SSAMP_MASK 0x03E00000L
+#define SQ_MIMG_1__D16_MASK 0x80000000L
+//SQ_MTBUF_0
+#define SQ_MTBUF_0__OFFSET__SHIFT 0x0
+#define SQ_MTBUF_0__OFFEN__SHIFT 0xc
+#define SQ_MTBUF_0__IDXEN__SHIFT 0xd
+#define SQ_MTBUF_0__GLC__SHIFT 0xe
+#define SQ_MTBUF_0__OP__SHIFT 0xf
+#define SQ_MTBUF_0__DFMT__SHIFT 0x13
+#define SQ_MTBUF_0__NFMT__SHIFT 0x17
+#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a
+#define SQ_MTBUF_0__OFFSET_MASK 0x00000FFFL
+#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L
+#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L
+#define SQ_MTBUF_0__GLC_MASK 0x00004000L
+#define SQ_MTBUF_0__OP_MASK 0x00078000L
+#define SQ_MTBUF_0__DFMT_MASK 0x00780000L
+#define SQ_MTBUF_0__NFMT_MASK 0x03800000L
+#define SQ_MTBUF_0__ENCODING_MASK 0xFC000000L
+//SQ_MTBUF_1
+#define SQ_MTBUF_1__VADDR__SHIFT 0x0
+#define SQ_MTBUF_1__VDATA__SHIFT 0x8
+#define SQ_MTBUF_1__SRSRC__SHIFT 0x10
+#define SQ_MTBUF_1__SLC__SHIFT 0x16
+#define SQ_MTBUF_1__TFE__SHIFT 0x17
+#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18
+#define SQ_MTBUF_1__VADDR_MASK 0x000000FFL
+#define SQ_MTBUF_1__VDATA_MASK 0x0000FF00L
+#define SQ_MTBUF_1__SRSRC_MASK 0x001F0000L
+#define SQ_MTBUF_1__SLC_MASK 0x00400000L
+#define SQ_MTBUF_1__TFE_MASK 0x00800000L
+#define SQ_MTBUF_1__SOFFSET_MASK 0xFF000000L
+//SQ_MUBUF_0
+#define SQ_MUBUF_0__OFFSET__SHIFT 0x0
+#define SQ_MUBUF_0__OFFEN__SHIFT 0xc
+#define SQ_MUBUF_0__IDXEN__SHIFT 0xd
+#define SQ_MUBUF_0__GLC__SHIFT 0xe
+#define SQ_MUBUF_0__LDS__SHIFT 0x10
+#define SQ_MUBUF_0__SLC__SHIFT 0x11
+#define SQ_MUBUF_0__OP__SHIFT 0x12
+#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a
+#define SQ_MUBUF_0__OFFSET_MASK 0x00000FFFL
+#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L
+#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L
+#define SQ_MUBUF_0__GLC_MASK 0x00004000L
+#define SQ_MUBUF_0__LDS_MASK 0x00010000L
+#define SQ_MUBUF_0__SLC_MASK 0x00020000L
+#define SQ_MUBUF_0__OP_MASK 0x01FC0000L
+#define SQ_MUBUF_0__ENCODING_MASK 0xFC000000L
+//SQ_MUBUF_1
+#define SQ_MUBUF_1__VADDR__SHIFT 0x0
+#define SQ_MUBUF_1__VDATA__SHIFT 0x8
+#define SQ_MUBUF_1__SRSRC__SHIFT 0x10
+#define SQ_MUBUF_1__TFE__SHIFT 0x17
+#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18
+#define SQ_MUBUF_1__VADDR_MASK 0x000000FFL
+#define SQ_MUBUF_1__VDATA_MASK 0x0000FF00L
+#define SQ_MUBUF_1__SRSRC_MASK 0x001F0000L
+#define SQ_MUBUF_1__TFE_MASK 0x00800000L
+#define SQ_MUBUF_1__SOFFSET_MASK 0xFF000000L
+//SQ_SCRATCH_0
+#define SQ_SCRATCH_0__OFFSET__SHIFT 0x0
+#define SQ_SCRATCH_0__LDS__SHIFT 0xd
+#define SQ_SCRATCH_0__SEG__SHIFT 0xe
+#define SQ_SCRATCH_0__GLC__SHIFT 0x10
+#define SQ_SCRATCH_0__SLC__SHIFT 0x11
+#define SQ_SCRATCH_0__OP__SHIFT 0x12
+#define SQ_SCRATCH_0__ENCODING__SHIFT 0x1a
+#define SQ_SCRATCH_0__OFFSET_MASK 0x00001FFFL
+#define SQ_SCRATCH_0__LDS_MASK 0x00002000L
+#define SQ_SCRATCH_0__SEG_MASK 0x0000C000L
+#define SQ_SCRATCH_0__GLC_MASK 0x00010000L
+#define SQ_SCRATCH_0__SLC_MASK 0x00020000L
+#define SQ_SCRATCH_0__OP_MASK 0x01FC0000L
+#define SQ_SCRATCH_0__ENCODING_MASK 0xFC000000L
+//SQ_SCRATCH_1
+#define SQ_SCRATCH_1__ADDR__SHIFT 0x0
+#define SQ_SCRATCH_1__DATA__SHIFT 0x8
+#define SQ_SCRATCH_1__SADDR__SHIFT 0x10
+#define SQ_SCRATCH_1__NV__SHIFT 0x17
+#define SQ_SCRATCH_1__VDST__SHIFT 0x18
+#define SQ_SCRATCH_1__ADDR_MASK 0x000000FFL
+#define SQ_SCRATCH_1__DATA_MASK 0x0000FF00L
+#define SQ_SCRATCH_1__SADDR_MASK 0x007F0000L
+#define SQ_SCRATCH_1__NV_MASK 0x00800000L
+#define SQ_SCRATCH_1__VDST_MASK 0xFF000000L
+//SQ_SMEM_0
+#define SQ_SMEM_0__SBASE__SHIFT 0x0
+#define SQ_SMEM_0__SDATA__SHIFT 0x6
+#define SQ_SMEM_0__SOFFSET_EN__SHIFT 0xe
+#define SQ_SMEM_0__NV__SHIFT 0xf
+#define SQ_SMEM_0__GLC__SHIFT 0x10
+#define SQ_SMEM_0__IMM__SHIFT 0x11
+#define SQ_SMEM_0__OP__SHIFT 0x12
+#define SQ_SMEM_0__ENCODING__SHIFT 0x1a
+#define SQ_SMEM_0__SBASE_MASK 0x0000003FL
+#define SQ_SMEM_0__SDATA_MASK 0x00001FC0L
+#define SQ_SMEM_0__SOFFSET_EN_MASK 0x00004000L
+#define SQ_SMEM_0__NV_MASK 0x00008000L
+#define SQ_SMEM_0__GLC_MASK 0x00010000L
+#define SQ_SMEM_0__IMM_MASK 0x00020000L
+#define SQ_SMEM_0__OP_MASK 0x03FC0000L
+#define SQ_SMEM_0__ENCODING_MASK 0xFC000000L
+//SQ_SMEM_1
+#define SQ_SMEM_1__OFFSET__SHIFT 0x0
+#define SQ_SMEM_1__SOFFSET__SHIFT 0x19
+#define SQ_SMEM_1__OFFSET_MASK 0x001FFFFFL
+#define SQ_SMEM_1__SOFFSET_MASK 0xFE000000L
+//SQ_SOP1
+#define SQ_SOP1__SSRC0__SHIFT 0x0
+#define SQ_SOP1__OP__SHIFT 0x8
+#define SQ_SOP1__SDST__SHIFT 0x10
+#define SQ_SOP1__ENCODING__SHIFT 0x17
+#define SQ_SOP1__SSRC0_MASK 0x000000FFL
+#define SQ_SOP1__OP_MASK 0x0000FF00L
+#define SQ_SOP1__SDST_MASK 0x007F0000L
+#define SQ_SOP1__ENCODING_MASK 0xFF800000L
+//SQ_SOP2
+#define SQ_SOP2__SSRC0__SHIFT 0x0
+#define SQ_SOP2__SSRC1__SHIFT 0x8
+#define SQ_SOP2__SDST__SHIFT 0x10
+#define SQ_SOP2__OP__SHIFT 0x17
+#define SQ_SOP2__ENCODING__SHIFT 0x1e
+#define SQ_SOP2__SSRC0_MASK 0x000000FFL
+#define SQ_SOP2__SSRC1_MASK 0x0000FF00L
+#define SQ_SOP2__SDST_MASK 0x007F0000L
+#define SQ_SOP2__OP_MASK 0x3F800000L
+#define SQ_SOP2__ENCODING_MASK 0xC0000000L
+//SQ_SOPC
+#define SQ_SOPC__SSRC0__SHIFT 0x0
+#define SQ_SOPC__SSRC1__SHIFT 0x8
+#define SQ_SOPC__OP__SHIFT 0x10
+#define SQ_SOPC__ENCODING__SHIFT 0x17
+#define SQ_SOPC__SSRC0_MASK 0x000000FFL
+#define SQ_SOPC__SSRC1_MASK 0x0000FF00L
+#define SQ_SOPC__OP_MASK 0x007F0000L
+#define SQ_SOPC__ENCODING_MASK 0xFF800000L
+//SQ_SOPK
+#define SQ_SOPK__SIMM16__SHIFT 0x0
+#define SQ_SOPK__SDST__SHIFT 0x10
+#define SQ_SOPK__OP__SHIFT 0x17
+#define SQ_SOPK__ENCODING__SHIFT 0x1c
+#define SQ_SOPK__SIMM16_MASK 0x0000FFFFL
+#define SQ_SOPK__SDST_MASK 0x007F0000L
+#define SQ_SOPK__OP_MASK 0x0F800000L
+#define SQ_SOPK__ENCODING_MASK 0xF0000000L
+//SQ_SOPP
+#define SQ_SOPP__SIMM16__SHIFT 0x0
+#define SQ_SOPP__OP__SHIFT 0x10
+#define SQ_SOPP__ENCODING__SHIFT 0x17
+#define SQ_SOPP__SIMM16_MASK 0x0000FFFFL
+#define SQ_SOPP__OP_MASK 0x007F0000L
+#define SQ_SOPP__ENCODING_MASK 0xFF800000L
+//SQ_VINTRP
+#define SQ_VINTRP__VSRC__SHIFT 0x0
+#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8
+#define SQ_VINTRP__ATTR__SHIFT 0xa
+#define SQ_VINTRP__OP__SHIFT 0x10
+#define SQ_VINTRP__VDST__SHIFT 0x12
+#define SQ_VINTRP__ENCODING__SHIFT 0x1a
+#define SQ_VINTRP__VSRC_MASK 0x000000FFL
+#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L
+#define SQ_VINTRP__ATTR_MASK 0x0000FC00L
+#define SQ_VINTRP__OP_MASK 0x00030000L
+#define SQ_VINTRP__VDST_MASK 0x03FC0000L
+#define SQ_VINTRP__ENCODING_MASK 0xFC000000L
+//SQ_VOP1
+#define SQ_VOP1__SRC0__SHIFT 0x0
+#define SQ_VOP1__OP__SHIFT 0x9
+#define SQ_VOP1__VDST__SHIFT 0x11
+#define SQ_VOP1__ENCODING__SHIFT 0x19
+#define SQ_VOP1__SRC0_MASK 0x000001FFL
+#define SQ_VOP1__OP_MASK 0x0001FE00L
+#define SQ_VOP1__VDST_MASK 0x01FE0000L
+#define SQ_VOP1__ENCODING_MASK 0xFE000000L
+//SQ_VOP2
+#define SQ_VOP2__SRC0__SHIFT 0x0
+#define SQ_VOP2__VSRC1__SHIFT 0x9
+#define SQ_VOP2__VDST__SHIFT 0x11
+#define SQ_VOP2__OP__SHIFT 0x19
+#define SQ_VOP2__ENCODING__SHIFT 0x1f
+#define SQ_VOP2__SRC0_MASK 0x000001FFL
+#define SQ_VOP2__VSRC1_MASK 0x0001FE00L
+#define SQ_VOP2__VDST_MASK 0x01FE0000L
+#define SQ_VOP2__OP_MASK 0x7E000000L
+#define SQ_VOP2__ENCODING_MASK 0x80000000L
+//SQ_VOP3P_0
+#define SQ_VOP3P_0__VDST__SHIFT 0x0
+#define SQ_VOP3P_0__NEG_HI__SHIFT 0x8
+#define SQ_VOP3P_0__OP_SEL__SHIFT 0xb
+#define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT 0xe
+#define SQ_VOP3P_0__CLAMP__SHIFT 0xf
+#define SQ_VOP3P_0__OP__SHIFT 0x10
+#define SQ_VOP3P_0__ENCODING__SHIFT 0x17
+#define SQ_VOP3P_0__VDST_MASK 0x000000FFL
+#define SQ_VOP3P_0__NEG_HI_MASK 0x00000700L
+#define SQ_VOP3P_0__OP_SEL_MASK 0x00003800L
+#define SQ_VOP3P_0__OP_SEL_HI_2_MASK 0x00004000L
+#define SQ_VOP3P_0__CLAMP_MASK 0x00008000L
+#define SQ_VOP3P_0__OP_MASK 0x007F0000L
+#define SQ_VOP3P_0__ENCODING_MASK 0xFF800000L
+//SQ_VOP3P_1
+#define SQ_VOP3P_1__SRC0__SHIFT 0x0
+#define SQ_VOP3P_1__SRC1__SHIFT 0x9
+#define SQ_VOP3P_1__SRC2__SHIFT 0x12
+#define SQ_VOP3P_1__OP_SEL_HI__SHIFT 0x1b
+#define SQ_VOP3P_1__NEG__SHIFT 0x1d
+#define SQ_VOP3P_1__SRC0_MASK 0x000001FFL
+#define SQ_VOP3P_1__SRC1_MASK 0x0003FE00L
+#define SQ_VOP3P_1__SRC2_MASK 0x07FC0000L
+#define SQ_VOP3P_1__OP_SEL_HI_MASK 0x18000000L
+#define SQ_VOP3P_1__NEG_MASK 0xE0000000L
+//SQ_VOP3_0
+#define SQ_VOP3_0__VDST__SHIFT 0x0
+#define SQ_VOP3_0__ABS__SHIFT 0x8
+#define SQ_VOP3_0__OP_SEL__SHIFT 0xb
+#define SQ_VOP3_0__CLAMP__SHIFT 0xf
+#define SQ_VOP3_0__OP__SHIFT 0x10
+#define SQ_VOP3_0__ENCODING__SHIFT 0x1a
+#define SQ_VOP3_0__VDST_MASK 0x000000FFL
+#define SQ_VOP3_0__ABS_MASK 0x00000700L
+#define SQ_VOP3_0__OP_SEL_MASK 0x00007800L
+#define SQ_VOP3_0__CLAMP_MASK 0x00008000L
+#define SQ_VOP3_0__OP_MASK 0x03FF0000L
+#define SQ_VOP3_0__ENCODING_MASK 0xFC000000L
+//SQ_VOP3_0_SDST_ENC
+#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0
+#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8
+#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf
+#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10
+#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a
+#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000FFL
+#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007F00L
+#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x00008000L
+#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03FF0000L
+#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xFC000000L
+//SQ_VOP3_1
+#define SQ_VOP3_1__SRC0__SHIFT 0x0
+#define SQ_VOP3_1__SRC1__SHIFT 0x9
+#define SQ_VOP3_1__SRC2__SHIFT 0x12
+#define SQ_VOP3_1__OMOD__SHIFT 0x1b
+#define SQ_VOP3_1__NEG__SHIFT 0x1d
+#define SQ_VOP3_1__SRC0_MASK 0x000001FFL
+#define SQ_VOP3_1__SRC1_MASK 0x0003FE00L
+#define SQ_VOP3_1__SRC2_MASK 0x07FC0000L
+#define SQ_VOP3_1__OMOD_MASK 0x18000000L
+#define SQ_VOP3_1__NEG_MASK 0xE0000000L
+//SQ_VOPC
+#define SQ_VOPC__SRC0__SHIFT 0x0
+#define SQ_VOPC__VSRC1__SHIFT 0x9
+#define SQ_VOPC__OP__SHIFT 0x11
+#define SQ_VOPC__ENCODING__SHIFT 0x19
+#define SQ_VOPC__SRC0_MASK 0x000001FFL
+#define SQ_VOPC__VSRC1_MASK 0x0001FE00L
+#define SQ_VOPC__OP_MASK 0x01FE0000L
+#define SQ_VOPC__ENCODING_MASK 0xFE000000L
+//SQ_VOP_DPP
+#define SQ_VOP_DPP__SRC0__SHIFT 0x0
+#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8
+#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13
+#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14
+#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15
+#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16
+#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17
+#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18
+#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c
+#define SQ_VOP_DPP__SRC0_MASK 0x000000FFL
+#define SQ_VOP_DPP__DPP_CTRL_MASK 0x0001FF00L
+#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x00080000L
+#define SQ_VOP_DPP__SRC0_NEG_MASK 0x00100000L
+#define SQ_VOP_DPP__SRC0_ABS_MASK 0x00200000L
+#define SQ_VOP_DPP__SRC1_NEG_MASK 0x00400000L
+#define SQ_VOP_DPP__SRC1_ABS_MASK 0x00800000L
+#define SQ_VOP_DPP__BANK_MASK_MASK 0x0F000000L
+#define SQ_VOP_DPP__ROW_MASK_MASK 0xF0000000L
+//SQ_VOP_SDWA
+#define SQ_VOP_SDWA__SRC0__SHIFT 0x0
+#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8
+#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb
+#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd
+#define SQ_VOP_SDWA__OMOD__SHIFT 0xe
+#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10
+#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13
+#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14
+#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15
+#define SQ_VOP_SDWA__S0__SHIFT 0x17
+#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18
+#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b
+#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c
+#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d
+#define SQ_VOP_SDWA__S1__SHIFT 0x1f
+#define SQ_VOP_SDWA__SRC0_MASK 0x000000FFL
+#define SQ_VOP_SDWA__DST_SEL_MASK 0x00000700L
+#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x00001800L
+#define SQ_VOP_SDWA__CLAMP_MASK 0x00002000L
+#define SQ_VOP_SDWA__OMOD_MASK 0x0000C000L
+#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x00070000L
+#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x00080000L
+#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x00100000L
+#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x00200000L
+#define SQ_VOP_SDWA__S0_MASK 0x00800000L
+#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x07000000L
+#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x08000000L
+#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000L
+#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000L
+#define SQ_VOP_SDWA__S1_MASK 0x80000000L
+//SQ_VOP_SDWA_SDST_ENC
+#define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT 0x0
+#define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT 0x8
+#define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT 0xf
+#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT 0x10
+#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT 0x13
+#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT 0x14
+#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT 0x15
+#define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT 0x17
+#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT 0x18
+#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT 0x1b
+#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT 0x1c
+#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT 0x1d
+#define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT 0x1f
+#define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK 0x000000FFL
+#define SQ_VOP_SDWA_SDST_ENC__SDST_MASK 0x00007F00L
+#define SQ_VOP_SDWA_SDST_ENC__SD_MASK 0x00008000L
+#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK 0x00070000L
+#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK 0x00080000L
+#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK 0x00100000L
+#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK 0x00200000L
+#define SQ_VOP_SDWA_SDST_ENC__S0_MASK 0x00800000L
+#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK 0x07000000L
+#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK 0x08000000L
+#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK 0x10000000L
+#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK 0x20000000L
+#define SQ_VOP_SDWA_SDST_ENC__S1_MASK 0x80000000L
+//SQ_LB_CTR_CTRL
+#define SQ_LB_CTR_CTRL__START__SHIFT 0x0
+#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1
+#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2
+#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L
+#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L
+#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L
+//SQ_LB_DATA0
+#define SQ_LB_DATA0__DATA__SHIFT 0x0
+#define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL
+//SQ_LB_DATA1
+#define SQ_LB_DATA1__DATA__SHIFT 0x0
+#define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL
+//SQ_LB_DATA2
+#define SQ_LB_DATA2__DATA__SHIFT 0x0
+#define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL
+//SQ_LB_DATA3
+#define SQ_LB_DATA3__DATA__SHIFT 0x0
+#define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL
+//SQ_LB_CTR_SEL
+#define SQ_LB_CTR_SEL__SEL0__SHIFT 0x0
+#define SQ_LB_CTR_SEL__SEL1__SHIFT 0x4
+#define SQ_LB_CTR_SEL__SEL2__SHIFT 0x8
+#define SQ_LB_CTR_SEL__SEL3__SHIFT 0xc
+#define SQ_LB_CTR_SEL__SEL0_MASK 0x0000000FL
+#define SQ_LB_CTR_SEL__SEL1_MASK 0x000000F0L
+#define SQ_LB_CTR_SEL__SEL2_MASK 0x00000F00L
+#define SQ_LB_CTR_SEL__SEL3_MASK 0x0000F000L
+//SQ_LB_CTR0_CU
+#define SQ_LB_CTR0_CU__SH0_MASK__SHIFT 0x0
+#define SQ_LB_CTR0_CU__SH1_MASK__SHIFT 0x10
+#define SQ_LB_CTR0_CU__SH0_MASK_MASK 0x0000FFFFL
+#define SQ_LB_CTR0_CU__SH1_MASK_MASK 0xFFFF0000L
+//SQ_LB_CTR1_CU
+#define SQ_LB_CTR1_CU__SH0_MASK__SHIFT 0x0
+#define SQ_LB_CTR1_CU__SH1_MASK__SHIFT 0x10
+#define SQ_LB_CTR1_CU__SH0_MASK_MASK 0x0000FFFFL
+#define SQ_LB_CTR1_CU__SH1_MASK_MASK 0xFFFF0000L
+//SQ_LB_CTR2_CU
+#define SQ_LB_CTR2_CU__SH0_MASK__SHIFT 0x0
+#define SQ_LB_CTR2_CU__SH1_MASK__SHIFT 0x10
+#define SQ_LB_CTR2_CU__SH0_MASK_MASK 0x0000FFFFL
+#define SQ_LB_CTR2_CU__SH1_MASK_MASK 0xFFFF0000L
+//SQ_LB_CTR3_CU
+#define SQ_LB_CTR3_CU__SH0_MASK__SHIFT 0x0
+#define SQ_LB_CTR3_CU__SH1_MASK__SHIFT 0x10
+#define SQ_LB_CTR3_CU__SH0_MASK_MASK 0x0000FFFFL
+#define SQ_LB_CTR3_CU__SH1_MASK_MASK 0xFFFF0000L
+//SQC_EDC_CNT
+#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x0
+#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x2
+#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x4
+#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT 0x6
+#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x8
+#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT 0xa
+#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT 0xc
+#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT 0xe
+#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x10
+#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x12
+#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x14
+#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT 0x16
+#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x18
+#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x1a
+#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1c
+#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1e
+#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000003L
+#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK 0x0000000CL
+#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK 0x00000030L
+#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK 0x000000C0L
+#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000300L
+#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK 0x00000C00L
+#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK 0x00003000L
+#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK 0x0000C000L
+#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00030000L
+#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK 0x000C0000L
+#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK 0x00300000L
+#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK 0x00C00000L
+#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK 0x03000000L
+#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK 0x0C000000L
+#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK 0x30000000L
+#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK 0xC0000000L
+//SQ_EDC_SEC_CNT
+#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0
+#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8
+#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10
+#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0x000000FFL
+#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0x0000FF00L
+#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0x00FF0000L
+//SQ_EDC_DED_CNT
+#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0
+#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8
+#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10
+#define SQ_EDC_DED_CNT__LDS_DED_MASK 0x000000FFL
+#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0x0000FF00L
+#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0x00FF0000L
+//SQ_EDC_INFO
+#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0
+#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4
+#define SQ_EDC_INFO__SOURCE__SHIFT 0x6
+#define SQ_EDC_INFO__VM_ID__SHIFT 0x9
+#define SQ_EDC_INFO__WAVE_ID_MASK 0x0000000FL
+#define SQ_EDC_INFO__SIMD_ID_MASK 0x00000030L
+#define SQ_EDC_INFO__SOURCE_MASK 0x000001C0L
+#define SQ_EDC_INFO__VM_ID_MASK 0x00001E00L
+//SQ_EDC_CNT
+#define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0
+#define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2
+#define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4
+#define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6
+#define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8
+#define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa
+#define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc
+#define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe
+#define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10
+#define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12
+#define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14
+#define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16
+#define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18
+#define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a
+#define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L
+#define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL
+#define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L
+#define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L
+#define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L
+#define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L
+#define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L
+#define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L
+#define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L
+#define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L
+#define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L
+#define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L
+#define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L
+#define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L
+//SQ_EDC_FUE_CNTL
+#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0
+#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10
+#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL
+#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L
+//SQ_THREAD_TRACE_WORD_CMN
+#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x000FL
+#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x0010L
+//SQ_THREAD_TRACE_WORD_EVENT
+#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x000FL
+#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x0010L
+#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x0020L
+#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x01C0L
+#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xFC00L
+//SQ_THREAD_TRACE_WORD_INST
+#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9
+#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb
+#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x000FL
+#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x0010L
+#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x01E0L
+#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x0600L
+#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xF800L
+//SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT 0xf
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001E0L
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK 0x00008000L
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xFFFF0000L
+//SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003C0L
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003C00L
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000C000L
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xFFFF0000L
+//SQ_THREAD_TRACE_WORD_ISSUE
+#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a
+#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000FL
+#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L
+#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000C00L
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000C000L
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000C0000L
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00C00000L
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0C000000L
+//SQ_THREAD_TRACE_WORD_MISC
+#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc
+#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd
+#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x000FL
+#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x0FF0L
+#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000L
+#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xE000L
+//SQ_THREAD_TRACE_WORD_PERF_1_OF_2
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003C0L
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000C00L
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01FFF000L
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xFE000000L
+//SQ_THREAD_TRACE_WORD_REG_1_OF_2
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001C00L
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xFFFF0000L
+//SQ_THREAD_TRACE_WORD_REG_2_OF_2
+#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x00000010L
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x00000060L
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x00000180L
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0x0000FE00L
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xFFFF0000L
+//SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2
+#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0x0000FFFFL
+//SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xFFFF0000L
+//SQ_THREAD_TRACE_WORD_WAVE
+#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x000FL
+#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x0010L
+#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x0020L
+#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x03C0L
+#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3C00L
+#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xC000L
+//SQ_THREAD_TRACE_WORD_WAVE_START
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15
+#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000FL
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L
+#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L
+#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003C0L
+#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003C00L
+#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000C000L
+#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001F0000L
+#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L
+#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1FC00000L
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xE0000000L
+//SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2
+#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00FFFFFFL
+//SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xFFFFL
+//SQ_THREAD_TRACE_WORD_PERF_2_OF_2
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003FL
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007FFC0L
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xFFF80000L
+//SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xFFFFFFFFL
+//SQ_WREXEC_EXEC_HI
+#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0
+#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a
+#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b
+#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c
+#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f
+#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL
+#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L
+#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x08000000L
+#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L
+#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L
+//SQ_WREXEC_EXEC_LO
+#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0
+#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL
+//SQ_BUF_RSRC_WORD0
+#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
+#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL
+//SQ_BUF_RSRC_WORD1
+#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
+#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10
+#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e
+#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f
+#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000FFFFL
+#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3FFF0000L
+#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L
+#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L
+//SQ_BUF_RSRC_WORD2
+#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0
+#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xFFFFFFFFL
+//SQ_BUF_RSRC_WORD3
+#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
+#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
+#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
+#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
+#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc
+#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf
+#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT 0x13
+#define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT 0x14
+#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15
+#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17
+#define SQ_BUF_RSRC_WORD3__NV__SHIFT 0x1b
+#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e
+#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L
+#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L
+#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L
+#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L
+#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L
+#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L
+#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK 0x00080000L
+#define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK 0x00100000L
+#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L
+#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L
+#define SQ_BUF_RSRC_WORD3__NV_MASK 0x08000000L
+#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xC0000000L
+//SQ_IMG_RSRC_WORD0
+#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL
+//SQ_IMG_RSRC_WORD1
+#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8
+#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14
+#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a
+#define SQ_IMG_RSRC_WORD1__NV__SHIFT 0x1e
+#define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT 0x1f
+#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000FFL
+#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000FFF00L
+#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03F00000L
+#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3C000000L
+#define SQ_IMG_RSRC_WORD1__NV_MASK 0x40000000L
+#define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK 0x80000000L
+//SQ_IMG_RSRC_WORD2
+#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe
+#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c
+#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003FFFL
+#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0FFFC000L
+#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L
+//SQ_IMG_RSRC_WORD3
+#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
+#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
+#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
+#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc
+#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10
+#define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT 0x14
+#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c
+#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L
+#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L
+#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L
+#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L
+#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000F000L
+#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000F0000L
+#define SQ_IMG_RSRC_WORD3__SW_MODE_MASK 0x01F00000L
+#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xF0000000L
+//SQ_IMG_RSRC_WORD4
+#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd
+#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT 0x1d
+#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001FFFL
+#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x1FFFE000L
+#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK 0xE0000000L
+//SQ_IMG_RSRC_WORD5
+#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT 0xd
+#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT 0x11
+#define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT 0x19
+#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT 0x1a
+#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT 0x1b
+#define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT 0x1c
+#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001FFFL
+#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK 0x0001E000L
+#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK 0x01FE0000L
+#define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK 0x02000000L
+#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK 0x04000000L
+#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK 0x08000000L
+#define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK 0xF0000000L
+//SQ_IMG_RSRC_WORD6
+#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc
+#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14
+#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15
+#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16
+#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17
+#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18
+#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c
+#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000FFFL
+#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000FF000L
+#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L
+#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x00200000L
+#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x00400000L
+#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x00800000L
+#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0x0F000000L
+#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xF0000000L
+//SQ_IMG_RSRC_WORD7
+#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xFFFFFFFFL
+//SQ_IMG_SAMP_WORD0
+#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3
+#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6
+#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9
+#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc
+#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf
+#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10
+#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13
+#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14
+#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15
+#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b
+#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c
+#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d
+#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f
+#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L
+#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L
+#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001C0L
+#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000E00L
+#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L
+#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L
+#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L
+#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L
+#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L
+#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07E00000L
+#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L
+#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L
+#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L
+#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000L
+//SQ_IMG_SAMP_WORD1
+#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc
+#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18
+#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c
+#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000FFFL
+#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00FFF000L
+#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0F000000L
+#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xF0000000L
+//SQ_IMG_SAMP_WORD2
+#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe
+#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14
+#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16
+#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18
+#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a
+#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c
+#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT 0x1d
+#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e
+#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f
+#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003FFFL
+#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000FC000L
+#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L
+#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00C00000L
+#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L
+#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0C000000L
+#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L
+#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK 0x20000000L
+#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L
+#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000L
+//SQ_IMG_SAMP_WORD3
+#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT 0xc
+#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e
+#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000FFFL
+#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK 0x00001000L
+#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xC0000000L
+//SQ_FLAT_SCRATCH_WORD0
+#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0
+#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x0007FFFFL
+//SQ_FLAT_SCRATCH_WORD1
+#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0
+#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0x00FFFFFFL
+//SQ_M0_GPR_IDX_WORD
+#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0
+#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc
+#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd
+#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe
+#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf
+#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0x000000FFL
+#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x00001000L
+#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x00002000L
+#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x00004000L
+#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x00008000L
+//SQC_ICACHE_UTCL1_CNTL1
+#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
+#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
+#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
+#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
+#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
+#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
+#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
+#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
+#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
+#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
+#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
+#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
+#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
+#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
+#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
+#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
+#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
+#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
+#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
+#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
+#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
+#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
+#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
+#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
+#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
+#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
+#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
+#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
+#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
+#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
+//SQC_ICACHE_UTCL1_CNTL2
+#define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0
+#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
+#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
+#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
+#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
+#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
+#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
+#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
+#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
+#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10
+#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
+#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
+#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
+#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
+#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
+#define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
+#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
+#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
+#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
+#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
+#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
+#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
+#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
+#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
+#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
+#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
+#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
+#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
+#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
+#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
+//SQC_DCACHE_UTCL1_CNTL1
+#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
+#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
+#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
+#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
+#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
+#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
+#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
+#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
+#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
+#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
+#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
+#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
+#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
+#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
+#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
+#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
+#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
+#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
+#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
+#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
+#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
+#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
+#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
+#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
+#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
+#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
+#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
+#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
+#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
+#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
+//SQC_DCACHE_UTCL1_CNTL2
+#define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0
+#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
+#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
+#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
+#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
+#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
+#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
+#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
+#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
+#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10
+#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
+#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
+#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
+#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
+#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
+#define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
+#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
+#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
+#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
+#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
+#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
+#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
+#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
+#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
+#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
+#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
+#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
+#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
+#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
+#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
+//SQC_ICACHE_UTCL1_STATUS
+#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+//SQC_DCACHE_UTCL1_STATUS
+#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+
+
+// addressBlock: gc_shsdec
+//SX_DEBUG_BUSY
+#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x0
+#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x1
+#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x2
+#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x3
+#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x4
+#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x5
+#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x6
+#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x7
+#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x8
+#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x9
+#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0xa
+#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0xb
+#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0xc
+#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0xd
+#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0xe
+#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0xf
+#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x10
+#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x11
+#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x12
+#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x13
+#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x14
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x15
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x16
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x17
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x18
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x19
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x1a
+#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x1b
+#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x1c
+#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d
+#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x1e
+#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x1f
+#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x00000001L
+#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x00000002L
+#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x00000004L
+#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x00000008L
+#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x00000010L
+#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x00000020L
+#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x00000040L
+#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x00000080L
+#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x00000100L
+#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x00000200L
+#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x00000400L
+#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x00000800L
+#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x00001000L
+#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x00002000L
+#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x00004000L
+#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x00008000L
+#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x00010000L
+#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x00020000L
+#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x00040000L
+#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x00080000L
+#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x00100000L
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x00200000L
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x00400000L
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x00800000L
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x01000000L
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x02000000L
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x04000000L
+#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x08000000L
+#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000L
+#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000L
+#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000L
+#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000L
+//SX_DEBUG_BUSY_2
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x0
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x2
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x3
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x4
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x5
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x6
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x7
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x8
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x9
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0xa
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0xb
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0xc
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0xd
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0xe
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0xf
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x10
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0x11
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0x12
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0x13
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0x14
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0x15
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0x16
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x17
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x18
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x19
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x1a
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x1b
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x1c
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x1d
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x1e
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x1f
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x00000001L
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x00000002L
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x00000004L
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x00000008L
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x00000010L
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x00000020L
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x00000040L
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x00000080L
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x00000100L
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x00000200L
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x00000400L
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x00000800L
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x00001000L
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x00002000L
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x00004000L
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x00008000L
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x00010000L
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x00020000L
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x00040000L
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x00080000L
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x00100000L
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x00200000L
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x00400000L
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x00800000L
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x01000000L
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x02000000L
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x04000000L
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x08000000L
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x10000000L
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x20000000L
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x40000000L
+#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x80000000L
+//SX_DEBUG_BUSY_3
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x0
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x2
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x3
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x4
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x5
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x6
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x7
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x8
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x9
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0xa
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0xb
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0xc
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0xd
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0xe
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0xf
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x10
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0x11
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0x12
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0x13
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0x14
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0x15
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0x16
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x17
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x18
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x19
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x1a
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x1b
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x1c
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x1d
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x1e
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x1f
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x00000001L
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x00000002L
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x00000004L
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x00000008L
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x00000010L
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x00000020L
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x00000040L
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x00000080L
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x00000100L
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x00000200L
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x00000400L
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x00000800L
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x00001000L
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x00002000L
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x00004000L
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x00008000L
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x00010000L
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x00020000L
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x00040000L
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x00080000L
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x00100000L
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x00200000L
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x00400000L
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x00800000L
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x01000000L
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x02000000L
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x04000000L
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x08000000L
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x10000000L
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x20000000L
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x40000000L
+#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x80000000L
+//SX_DEBUG_BUSY_4
+#define SX_DEBUG_BUSY_4__COL_SCBD_BUSY__SHIFT 0x0
+#define SX_DEBUG_BUSY_4__COL_REQ3_FREECNT_NE0__SHIFT 0x1
+#define SX_DEBUG_BUSY_4__COL_REQ3_IDLE__SHIFT 0x2
+#define SX_DEBUG_BUSY_4__COL_REQ3_BUSY__SHIFT 0x3
+#define SX_DEBUG_BUSY_4__COL_REQ3_CREDIT_BUSY__SHIFT 0x4
+#define SX_DEBUG_BUSY_4__COL_REQ2_FREECNT_NE0__SHIFT 0x5
+#define SX_DEBUG_BUSY_4__COL_REQ2_IDLE__SHIFT 0x6
+#define SX_DEBUG_BUSY_4__COL_REQ2_BUSY__SHIFT 0x7
+#define SX_DEBUG_BUSY_4__COL_REQ2_CREDIT_BUSY__SHIFT 0x8
+#define SX_DEBUG_BUSY_4__COL_REQ1_FREECNT_NE0__SHIFT 0x9
+#define SX_DEBUG_BUSY_4__COL_REQ1_IDLE__SHIFT 0xa
+#define SX_DEBUG_BUSY_4__COL_REQ1_BUSY__SHIFT 0xb
+#define SX_DEBUG_BUSY_4__COL_REQ1_CREDIT_BUSY__SHIFT 0xc
+#define SX_DEBUG_BUSY_4__COL_REQ0_FREECNT_NE0__SHIFT 0xd
+#define SX_DEBUG_BUSY_4__COL_REQ0_IDLE__SHIFT 0xe
+#define SX_DEBUG_BUSY_4__COL_REQ0_BUSY__SHIFT 0xf
+#define SX_DEBUG_BUSY_4__COL_REQ0_CREDIT_BUSY__SHIFT 0x10
+#define SX_DEBUG_BUSY_4__COL_DBIF3_SENDFREE_BUSY__SHIFT 0x11
+#define SX_DEBUG_BUSY_4__COL_DBIF3_FIFO_BUSY__SHIFT 0x12
+#define SX_DEBUG_BUSY_4__COL_DBIF3_QUAD_FREE__SHIFT 0x13
+#define SX_DEBUG_BUSY_4__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x14
+#define SX_DEBUG_BUSY_4__COL_DBIF2_FIFO_BUSY__SHIFT 0x15
+#define SX_DEBUG_BUSY_4__COL_DBIF2_QUAD_FREE__SHIFT 0x16
+#define SX_DEBUG_BUSY_4__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x17
+#define SX_DEBUG_BUSY_4__COL_DBIF1_FIFO_BUSY__SHIFT 0x18
+#define SX_DEBUG_BUSY_4__COL_DBIF1_QUAD_FREE__SHIFT 0x19
+#define SX_DEBUG_BUSY_4__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x1a
+#define SX_DEBUG_BUSY_4__COL_DBIF0_FIFO_BUSY__SHIFT 0x1b
+#define SX_DEBUG_BUSY_4__COL_DBIF0_QUAD_FREE__SHIFT 0x1c
+#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1__SHIFT 0x1d
+#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1_ADJ__SHIFT 0x1e
+#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ2__SHIFT 0x1f
+#define SX_DEBUG_BUSY_4__COL_SCBD_BUSY_MASK 0x00000001L
+#define SX_DEBUG_BUSY_4__COL_REQ3_FREECNT_NE0_MASK 0x00000002L
+#define SX_DEBUG_BUSY_4__COL_REQ3_IDLE_MASK 0x00000004L
+#define SX_DEBUG_BUSY_4__COL_REQ3_BUSY_MASK 0x00000008L
+#define SX_DEBUG_BUSY_4__COL_REQ3_CREDIT_BUSY_MASK 0x00000010L
+#define SX_DEBUG_BUSY_4__COL_REQ2_FREECNT_NE0_MASK 0x00000020L
+#define SX_DEBUG_BUSY_4__COL_REQ2_IDLE_MASK 0x00000040L
+#define SX_DEBUG_BUSY_4__COL_REQ2_BUSY_MASK 0x00000080L
+#define SX_DEBUG_BUSY_4__COL_REQ2_CREDIT_BUSY_MASK 0x00000100L
+#define SX_DEBUG_BUSY_4__COL_REQ1_FREECNT_NE0_MASK 0x00000200L
+#define SX_DEBUG_BUSY_4__COL_REQ1_IDLE_MASK 0x00000400L
+#define SX_DEBUG_BUSY_4__COL_REQ1_BUSY_MASK 0x00000800L
+#define SX_DEBUG_BUSY_4__COL_REQ1_CREDIT_BUSY_MASK 0x00001000L
+#define SX_DEBUG_BUSY_4__COL_REQ0_FREECNT_NE0_MASK 0x00002000L
+#define SX_DEBUG_BUSY_4__COL_REQ0_IDLE_MASK 0x00004000L
+#define SX_DEBUG_BUSY_4__COL_REQ0_BUSY_MASK 0x00008000L
+#define SX_DEBUG_BUSY_4__COL_REQ0_CREDIT_BUSY_MASK 0x00010000L
+#define SX_DEBUG_BUSY_4__COL_DBIF3_SENDFREE_BUSY_MASK 0x00020000L
+#define SX_DEBUG_BUSY_4__COL_DBIF3_FIFO_BUSY_MASK 0x00040000L
+#define SX_DEBUG_BUSY_4__COL_DBIF3_QUAD_FREE_MASK 0x00080000L
+#define SX_DEBUG_BUSY_4__COL_DBIF2_SENDFREE_BUSY_MASK 0x00100000L
+#define SX_DEBUG_BUSY_4__COL_DBIF2_FIFO_BUSY_MASK 0x00200000L
+#define SX_DEBUG_BUSY_4__COL_DBIF2_QUAD_FREE_MASK 0x00400000L
+#define SX_DEBUG_BUSY_4__COL_DBIF1_SENDFREE_BUSY_MASK 0x00800000L
+#define SX_DEBUG_BUSY_4__COL_DBIF1_FIFO_BUSY_MASK 0x01000000L
+#define SX_DEBUG_BUSY_4__COL_DBIF1_QUAD_FREE_MASK 0x02000000L
+#define SX_DEBUG_BUSY_4__COL_DBIF0_SENDFREE_BUSY_MASK 0x04000000L
+#define SX_DEBUG_BUSY_4__COL_DBIF0_FIFO_BUSY_MASK 0x08000000L
+#define SX_DEBUG_BUSY_4__COL_DBIF0_QUAD_FREE_MASK 0x10000000L
+#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1_MASK 0x20000000L
+#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1_ADJ_MASK 0x40000000L
+#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ2_MASK 0x80000000L
+//SX_DEBUG_BUSY_5
+#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ3__SHIFT 0x0
+#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ4__SHIFT 0x1
+#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ5__SHIFT 0x2
+#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALID_O__SHIFT 0x3
+#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1__SHIFT 0x4
+#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1_ADJ__SHIFT 0x5
+#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ2__SHIFT 0x6
+#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ3__SHIFT 0x7
+#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ4__SHIFT 0x8
+#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ5__SHIFT 0x9
+#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALID_O__SHIFT 0xa
+#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1__SHIFT 0xb
+#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1_ADJ__SHIFT 0xc
+#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ2__SHIFT 0xd
+#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ3__SHIFT 0xe
+#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ4__SHIFT 0xf
+#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ5__SHIFT 0x10
+#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALID_O__SHIFT 0x11
+#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1__SHIFT 0x12
+#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1_ADJ__SHIFT 0x13
+#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ2__SHIFT 0x14
+#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ3__SHIFT 0x15
+#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ4__SHIFT 0x16
+#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ5__SHIFT 0x17
+#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALID_O__SHIFT 0x18
+#define SX_DEBUG_BUSY_5__RESERVED__SHIFT 0x19
+#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ3_MASK 0x00000001L
+#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ4_MASK 0x00000002L
+#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ5_MASK 0x00000004L
+#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALID_O_MASK 0x00000008L
+#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1_MASK 0x00000010L
+#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1_ADJ_MASK 0x00000020L
+#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ2_MASK 0x00000040L
+#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ3_MASK 0x00000080L
+#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ4_MASK 0x00000100L
+#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ5_MASK 0x00000200L
+#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALID_O_MASK 0x00000400L
+#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1_MASK 0x00000800L
+#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1_ADJ_MASK 0x00001000L
+#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ2_MASK 0x00002000L
+#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ3_MASK 0x00004000L
+#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ4_MASK 0x00008000L
+#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ5_MASK 0x00010000L
+#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALID_O_MASK 0x00020000L
+#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1_MASK 0x00040000L
+#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1_ADJ_MASK 0x00080000L
+#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ2_MASK 0x00100000L
+#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ3_MASK 0x00200000L
+#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ4_MASK 0x00400000L
+#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ5_MASK 0x00800000L
+#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALID_O_MASK 0x01000000L
+#define SX_DEBUG_BUSY_5__RESERVED_MASK 0xFE000000L
+//SX_DEBUG_1
+#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0
+#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8
+#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9
+#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa
+#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb
+#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc
+#define SX_DEBUG_1__PC_CFG__SHIFT 0xd
+#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0xe
+#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL
+#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L
+#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L
+#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L
+#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L
+#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L
+#define SX_DEBUG_1__PC_CFG_MASK 0x00002000L
+#define SX_DEBUG_1__DEBUG_DATA_MASK 0xFFFFC000L
+//SPI_PS_MAX_WAVE_ID
+#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
+#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10
+#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
+#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L
+//SPI_START_PHASE
+#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0
+#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2
+#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4
+#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x00000003L
+#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0x0000000CL
+#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x00000030L
+//SPI_GFX_CNTL
+#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0
+#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L
+//SPI_DEBUG_READ
+#define SPI_DEBUG_READ__DATA__SHIFT 0x0
+#define SPI_DEBUG_READ__DATA_MASK 0xFFFFFFFFL
+//SPI_DSM_CNTL
+#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define SPI_DSM_CNTL__UNUSED__SHIFT 0x3
+#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define SPI_DSM_CNTL__UNUSED_MASK 0xFFFFFFF8L
+//SPI_DSM_CNTL2
+#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x4
+#define SPI_DSM_CNTL2__UNUSED__SHIFT 0xa
+#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000003F0L
+#define SPI_DSM_CNTL2__UNUSED_MASK 0xFFFFFC00L
+//SPI_EDC_CNT
+#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT 0x0
+#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK 0x00000003L
+//SPI_DEBUG_BUSY
+#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x0
+#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x1
+#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x2
+#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x3
+#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x4
+#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x5
+#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x6
+#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x7
+#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8
+#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9
+#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa
+#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb
+#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc
+#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd
+#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe
+#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf
+#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x10
+#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x11
+#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x12
+#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x13
+#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x14
+#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x15
+#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x16
+#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x17
+#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x00000001L
+#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x00000002L
+#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x00000004L
+#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x00000008L
+#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x00000010L
+#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x00000020L
+#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x00000040L
+#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x00000080L
+#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x00000100L
+#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x00000200L
+#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x00000400L
+#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x00000800L
+#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x00001000L
+#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x00002000L
+#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x00004000L
+#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x00008000L
+#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x00010000L
+#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x00020000L
+#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x00040000L
+#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x00080000L
+#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x00100000L
+#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x00200000L
+#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x00400000L
+#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x00800000L
+//SPI_CONFIG_PS_CU_EN
+#define SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT 0x0
+#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT 0x1
+#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT 0x10
+#define SPI_CONFIG_PS_CU_EN__ENABLE_MASK 0x00000001L
+#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK 0x0000FFFEL
+#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK 0xFFFF0000L
+//SPI_WF_LIFETIME_CNTL
+#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0
+#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4
+#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL
+#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L
+//SPI_WF_LIFETIME_LIMIT_0
+#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_1
+#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_2
+#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_3
+#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_4
+#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_5
+#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_6
+#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_7
+#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_8
+#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_9
+#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_0
+#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_1
+#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_2
+#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_3
+#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_4
+#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_5
+#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_6
+#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_7
+#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_8
+#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_9
+#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_10
+#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_11
+#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_12
+#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_13
+#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_14
+#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_15
+#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_16
+#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_17
+#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_18
+#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_19
+#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_20
+#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_DEBUG
+#define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0
+#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000L
+//SPI_LB_CTR_CTRL
+#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0
+#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1
+#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3
+#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4
+#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L
+#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L
+#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L
+#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L
+//SPI_LB_CU_MASK
+#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0
+#define SPI_LB_CU_MASK__CU_MASK_MASK 0xFFFFL
+//SPI_LB_DATA_REG
+#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0
+#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL
+//SPI_PG_ENABLE_STATIC_CU_MASK
+#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0
+#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xFFFFL
+//SPI_GDS_CREDITS
+#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0
+#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8
+#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10
+#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL
+#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L
+#define SPI_GDS_CREDITS__UNUSED_MASK 0xFFFF0000L
+//SPI_SX_EXPORT_BUFFER_SIZES
+#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0
+#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10
+#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL
+#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L
+//SPI_SX_SCOREBOARD_BUFFER_SIZES
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L
+//SPI_CSQ_WF_ACTIVE_STATUS
+#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL
+//SPI_CSQ_WF_ACTIVE_COUNT_0
+#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07FF0000L
+//SPI_CSQ_WF_ACTIVE_COUNT_1
+#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07FF0000L
+//SPI_CSQ_WF_ACTIVE_COUNT_2
+#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07FF0000L
+//SPI_CSQ_WF_ACTIVE_COUNT_3
+#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07FF0000L
+//SPI_CSQ_WF_ACTIVE_COUNT_4
+#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000007FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x07FF0000L
+//SPI_CSQ_WF_ACTIVE_COUNT_5
+#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000007FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x07FF0000L
+//SPI_CSQ_WF_ACTIVE_COUNT_6
+#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000007FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x07FF0000L
+//SPI_CSQ_WF_ACTIVE_COUNT_7
+#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000007FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x07FF0000L
+//SPI_LB_DATA_WAVES
+#define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0
+#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10
+#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL
+#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L
+//SPI_LB_DATA_PERCU_WAVE_HSGS
+#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT 0x0
+#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT 0x10
+#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK 0x0000FFFFL
+#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK 0xFFFF0000L
+//SPI_LB_DATA_PERCU_WAVE_VSPS
+#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT 0x0
+#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT 0x10
+#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK 0x0000FFFFL
+#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK 0xFFFF0000L
+//SPI_LB_DATA_PERCU_WAVE_CS
+#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT 0x0
+#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK 0xFFFFL
+//SPIS_DEBUG_READ
+#define SPIS_DEBUG_READ__DATA__SHIFT 0x0
+#define SPIS_DEBUG_READ__DATA_MASK 0xFFFFFFFFL
+//BCI_DEBUG_READ
+#define BCI_DEBUG_READ__DATA__SHIFT 0x0
+#define BCI_DEBUG_READ__DATA_MASK 0xFFFFFFL
+//SPI_P0_TRAP_SCREEN_PSBA_LO
+#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_P0_TRAP_SCREEN_PSBA_HI
+#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL
+//SPI_P0_TRAP_SCREEN_PSMA_LO
+#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_P0_TRAP_SCREEN_PSMA_HI
+#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL
+//SPI_P0_TRAP_SCREEN_GPR_MIN
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L
+//SPI_P1_TRAP_SCREEN_PSBA_LO
+#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_P1_TRAP_SCREEN_PSBA_HI
+#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL
+//SPI_P1_TRAP_SCREEN_PSMA_LO
+#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_P1_TRAP_SCREEN_PSMA_HI
+#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL
+//SPI_P1_TRAP_SCREEN_GPR_MIN
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L
+
+
+// addressBlock: gc_tpdec
+//TD_CNTL
+#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0
+#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4
+#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8
+#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9
+#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb
+#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf
+#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10
+#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12
+#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13
+#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14
+#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15
+#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17
+#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT__SHIFT 0x18
+#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L
+#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L
+#define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L
+#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L
+#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L
+#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x00008000L
+#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L
+#define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L
+#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L
+#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L
+#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x00200000L
+#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x00800000L
+#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT_MASK 0x01000000L
+//TD_STATUS
+#define TD_STATUS__BUSY__SHIFT 0x1f
+#define TD_STATUS__BUSY_MASK 0x80000000L
+//TD_DSM_CNTL
+#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+//TD_DSM_CNTL2
+#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x2
+#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x5
+#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
+#define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x1a
+#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xFC000000L
+//TD_SCRATCH
+#define TD_SCRATCH__SCRATCH__SHIFT 0x0
+#define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
+//TA_CNTL
+#define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0
+#define TA_CNTL__SQ_XNACK_CREDIT__SHIFT 0x9
+#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd
+#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10
+#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16
+#define TA_CNTL__FX_XNACK_CREDIT_MASK 0x0000007FL
+#define TA_CNTL__SQ_XNACK_CREDIT_MASK 0x00001E00L
+#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000E000L
+#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L
+#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L
+//TA_CNTL_AUX
+#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0
+#define TA_CNTL_AUX__RESERVED__SHIFT 0x1
+#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5
+#define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6
+#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7
+#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS__SHIFT 0x9
+#define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa
+#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc
+#define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd
+#define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe
+#define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf
+#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10
+#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11
+#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12
+#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13
+#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14
+#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15
+#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16
+#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17
+#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18
+#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19
+#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a
+#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT 0x1b
+#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c
+#define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d
+#define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e
+#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L
+#define TA_CNTL_AUX__RESERVED_MASK 0x0000000EL
+#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L
+#define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L
+#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L
+#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS_MASK 0x00000200L
+#define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L
+#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L
+#define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L
+#define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L
+#define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L
+#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L
+#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L
+#define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L
+#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x00080000L
+#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L
+#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L
+#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L
+#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L
+#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L
+#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L
+#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L
+#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK 0x08000000L
+#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L
+#define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L
+#define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L
+//TA_RESERVED_010C
+#define TA_RESERVED_010C__Unused__SHIFT 0x0
+#define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL
+//TA_GRAD_ADJ
+#define TA_GRAD_ADJ__GRAD_ADJ_0__SHIFT 0x0
+#define TA_GRAD_ADJ__GRAD_ADJ_1__SHIFT 0x8
+#define TA_GRAD_ADJ__GRAD_ADJ_2__SHIFT 0x10
+#define TA_GRAD_ADJ__GRAD_ADJ_3__SHIFT 0x18
+#define TA_GRAD_ADJ__GRAD_ADJ_0_MASK 0x000000FFL
+#define TA_GRAD_ADJ__GRAD_ADJ_1_MASK 0x0000FF00L
+#define TA_GRAD_ADJ__GRAD_ADJ_2_MASK 0x00FF0000L
+#define TA_GRAD_ADJ__GRAD_ADJ_3_MASK 0xFF000000L
+//TA_STATUS
+#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc
+#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd
+#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe
+#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10
+#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11
+#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12
+#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14
+#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15
+#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16
+#define TA_STATUS__IN_BUSY__SHIFT 0x18
+#define TA_STATUS__FG_BUSY__SHIFT 0x19
+#define TA_STATUS__LA_BUSY__SHIFT 0x1a
+#define TA_STATUS__FL_BUSY__SHIFT 0x1b
+#define TA_STATUS__TA_BUSY__SHIFT 0x1c
+#define TA_STATUS__FA_BUSY__SHIFT 0x1d
+#define TA_STATUS__AL_BUSY__SHIFT 0x1e
+#define TA_STATUS__BUSY__SHIFT 0x1f
+#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L
+#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L
+#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L
+#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L
+#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L
+#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L
+#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L
+#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L
+#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L
+#define TA_STATUS__IN_BUSY_MASK 0x01000000L
+#define TA_STATUS__FG_BUSY_MASK 0x02000000L
+#define TA_STATUS__LA_BUSY_MASK 0x04000000L
+#define TA_STATUS__FL_BUSY_MASK 0x08000000L
+#define TA_STATUS__TA_BUSY_MASK 0x10000000L
+#define TA_STATUS__FA_BUSY_MASK 0x20000000L
+#define TA_STATUS__AL_BUSY_MASK 0x40000000L
+#define TA_STATUS__BUSY_MASK 0x80000000L
+//TA_SCRATCH
+#define TA_SCRATCH__SCRATCH__SHIFT 0x0
+#define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_gdsdec
+//GDS_CONFIG
+#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1
+#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3
+#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5
+#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7
+#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L
+#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L
+#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L
+#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L
+//GDS_CNTL_STATUS
+#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0
+#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1
+#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2
+#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3
+#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4
+#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5
+#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6
+#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7
+#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8
+#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9
+#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa
+#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb
+#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc
+#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd
+#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe
+#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L
+#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L
+#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L
+#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L
+#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L
+#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L
+#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L
+#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L
+#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L
+#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L
+#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L
+#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L
+#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L
+#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L
+#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L
+//GDS_ENHANCE2
+#define GDS_ENHANCE2__MISC__SHIFT 0x0
+#define GDS_ENHANCE2__UNUSED__SHIFT 0x10
+#define GDS_ENHANCE2__MISC_MASK 0x0000FFFFL
+#define GDS_ENHANCE2__UNUSED_MASK 0xFFFF0000L
+//GDS_PROTECTION_FAULT
+#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
+#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
+#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2
+#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3
+#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6
+#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa
+#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc
+#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
+#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L
+#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L
+#define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L
+#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L
+#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003C0L
+#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000C00L
+#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000F000L
+#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L
+//GDS_VM_PROTECTION_FAULT
+#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
+#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
+#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2
+#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3
+#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4
+#define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT 0x5
+#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8
+#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
+#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L
+#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L
+#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L
+#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L
+#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L
+#define GDS_VM_PROTECTION_FAULT__TMZ_MASK 0x00000020L
+#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L
+#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L
+//GDS_EDC_CNT
+#define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0
+#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT 0x2
+#define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4
+#define GDS_EDC_CNT__UNUSED__SHIFT 0x6
+#define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L
+#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK 0x0000000CL
+#define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L
+#define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L
+//GDS_EDC_GRBM_CNT
+#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0
+#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2
+#define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4
+#define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L
+#define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL
+#define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L
+//GDS_EDC_OA_DED
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1
+#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3
+#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4
+#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5
+#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6
+#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7
+#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8
+#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9
+#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa
+#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb
+#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L
+#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L
+#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L
+#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L
+#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L
+#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L
+#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L
+#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L
+#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L
+#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L
+#define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFF000L
+//GDS_DSM_CNTL
+#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0
+#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1
+#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3
+#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4
+#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7
+#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa
+#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd
+#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define GDS_DSM_CNTL__UNUSED__SHIFT 0xf
+#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L
+#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L
+#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L
+#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L
+#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L
+#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L
+//GDS_EDC_OA_PHY_CNT
+#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0
+#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2
+#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4
+#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6
+#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT 0x8
+#define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xa
+#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L
+#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL
+#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L
+#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L
+#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK 0x00000300L
+#define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFFC00L
+//GDS_EDC_OA_PIPE_CNT
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe
+#define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L
+#define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L
+//GDS_DSM_CNTL2
+#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5
+#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf
+#define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a
+#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L
+#define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L
+//GDS_WD_GDS_CSB
+#define GDS_WD_GDS_CSB__COUNTER__SHIFT 0x0
+#define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd
+#define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL
+#define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L
+
+
+// addressBlock: gc_rbdec
+//DB_DEBUG
+#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
+#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
+#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
+#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
+#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
+#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
+#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
+#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
+#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
+#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
+#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
+#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
+#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
+#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
+#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
+#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
+#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
+#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
+#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
+#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
+#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
+#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
+#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L
+#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L
+#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L
+#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L
+#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L
+#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L
+#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L
+#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L
+#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L
+#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L
+#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L
+#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L
+#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L
+#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L
+#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L
+#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L
+#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L
+#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L
+#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L
+#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L
+#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L
+#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L
+//DB_DEBUG2
+#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
+#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
+#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
+#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
+#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
+#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5
+#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6
+#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7
+#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8
+#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
+#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
+#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf
+#define DB_DEBUG2__RESERVED__SHIFT 0x10
+#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
+#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
+#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
+#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c
+#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d
+#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e
+#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f
+#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L
+#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L
+#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L
+#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L
+#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L
+#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L
+#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L
+#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L
+#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L
+#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L
+#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L
+#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L
+#define DB_DEBUG2__RESERVED_MASK 0x00010000L
+#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L
+#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L
+#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L
+#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L
+#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L
+#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L
+#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L
+//DB_DEBUG3
+#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x0
+#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT 0x1
+#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2
+#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3
+#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4
+#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5
+#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6
+#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7
+#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8
+#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9
+#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
+#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb
+#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc
+#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd
+#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe
+#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf
+#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10
+#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11
+#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12
+#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13
+#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
+#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15
+#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16
+#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17
+#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18
+#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19
+#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a
+#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b
+#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c
+#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d
+#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e
+#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f
+#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L
+#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK 0x00000002L
+#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L
+#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L
+#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L
+#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L
+#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L
+#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L
+#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L
+#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000200L
+#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L
+#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L
+#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00001000L
+#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L
+#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L
+#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L
+#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x00010000L
+#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L
+#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00040000L
+#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L
+#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L
+#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L
+#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L
+#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L
+#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L
+#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L
+#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L
+#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L
+#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L
+#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000L
+#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000L
+#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000L
+//DB_DEBUG4
+#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0
+#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1
+#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2
+#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3
+#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT 0x4
+#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0x5
+#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x6
+#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x7
+#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT 0x8
+#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x9
+#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa
+#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0xb
+#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT 0xc
+#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd
+#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0xe
+#define DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT 0xf
+#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0x10
+#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT 0x11
+#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT 0x12
+#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x13
+#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L
+#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L
+#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L
+#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L
+#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK 0x00000010L
+#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00000020L
+#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000040L
+#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000080L
+#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK 0x00000100L
+#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L
+#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L
+#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L
+#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK 0x00001000L
+#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L
+#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L
+#define DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK 0x00008000L
+#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00010000L
+#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK 0x00020000L
+#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK 0x00040000L
+#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xFFF80000L
+//DB_CREDIT_LIMIT
+#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0
+#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5
+#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
+#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18
+#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001FL
+#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L
+#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001C00L
+#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7F000000L
+//DB_WATERMARKS
+#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0
+#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5
+#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb
+#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf
+#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14
+#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e
+#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f
+#define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001FL
+#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007E0L
+#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L
+#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000F8000L
+#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x0FF00000L
+#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L
+#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L
+//DB_SUBTILE_CONTROL
+#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0
+#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2
+#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4
+#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6
+#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8
+#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
+#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc
+#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe
+#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10
+#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12
+#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L
+#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000CL
+#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L
+#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000C0L
+#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L
+#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000C00L
+#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L
+#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000C000L
+#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L
+#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000C0000L
+//DB_FREE_CACHELINES
+#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0
+#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7
+#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe
+#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x14
+#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x18
+#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007FL
+#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003F80L
+#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x000FC000L
+#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x00F00000L
+#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xFF000000L
+//DB_FIFO_DEPTH1
+#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT 0x0
+#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT 0x5
+#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
+#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10
+#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15
+#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK 0x0000001FL
+#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK 0x000003E0L
+#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000FC00L
+#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001F0000L
+#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1FE00000L
+//DB_FIFO_DEPTH2
+#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0
+#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8
+#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf
+#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19
+#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL
+#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007F00L
+#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF8000L
+#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L
+//DB_EXCEPTION_CONTROL
+#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0
+#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1
+#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2
+#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L
+#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L
+#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L
+//DB_RING_CONTROL
+#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0
+#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L
+//DB_MEM_ARB_WATERMARKS
+#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0
+#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8
+#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10
+#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18
+#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L
+#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L
+#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L
+#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L
+//DB_RMI_CACHE_POLICY
+#define DB_RMI_CACHE_POLICY__Z_RD__SHIFT 0x0
+#define DB_RMI_CACHE_POLICY__S_RD__SHIFT 0x1
+#define DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT 0x2
+#define DB_RMI_CACHE_POLICY__Z_WR__SHIFT 0x8
+#define DB_RMI_CACHE_POLICY__S_WR__SHIFT 0x9
+#define DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT 0xa
+#define DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT 0xb
+#define DB_RMI_CACHE_POLICY__CC_RD__SHIFT 0x10
+#define DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT 0x11
+#define DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT 0x12
+#define DB_RMI_CACHE_POLICY__DCC_RD__SHIFT 0x13
+#define DB_RMI_CACHE_POLICY__CC_WR__SHIFT 0x18
+#define DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT 0x19
+#define DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT 0x1a
+#define DB_RMI_CACHE_POLICY__DCC_WR__SHIFT 0x1b
+#define DB_RMI_CACHE_POLICY__Z_RD_MASK 0x00000001L
+#define DB_RMI_CACHE_POLICY__S_RD_MASK 0x00000002L
+#define DB_RMI_CACHE_POLICY__HTILE_RD_MASK 0x00000004L
+#define DB_RMI_CACHE_POLICY__Z_WR_MASK 0x00000100L
+#define DB_RMI_CACHE_POLICY__S_WR_MASK 0x00000200L
+#define DB_RMI_CACHE_POLICY__HTILE_WR_MASK 0x00000400L
+#define DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK 0x00000800L
+#define DB_RMI_CACHE_POLICY__CC_RD_MASK 0x00010000L
+#define DB_RMI_CACHE_POLICY__FMASK_RD_MASK 0x00020000L
+#define DB_RMI_CACHE_POLICY__CMASK_RD_MASK 0x00040000L
+#define DB_RMI_CACHE_POLICY__DCC_RD_MASK 0x00080000L
+#define DB_RMI_CACHE_POLICY__CC_WR_MASK 0x01000000L
+#define DB_RMI_CACHE_POLICY__FMASK_WR_MASK 0x02000000L
+#define DB_RMI_CACHE_POLICY__CMASK_WR_MASK 0x04000000L
+#define DB_RMI_CACHE_POLICY__DCC_WR_MASK 0x08000000L
+//DB_DFSM_CONFIG
+#define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT 0x0
+#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT 0x1
+#define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT 0x2
+#define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT 0x3
+#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT 0x8
+#define DB_DFSM_CONFIG__BYPASS_DFSM_MASK 0x00000001L
+#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK 0x00000002L
+#define DB_DFSM_CONFIG__DISABLE_POPS_MASK 0x00000004L
+#define DB_DFSM_CONFIG__FORCE_FLUSH_MASK 0x00000008L
+#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK 0x00007F00L
+//DB_DFSM_WATERMARK
+#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT 0x0
+#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT 0x10
+#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK 0x0000FFFFL
+#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK 0xFFFF0000L
+//DB_DFSM_TILES_IN_FLIGHT
+#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0
+#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10
+#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL
+#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L
+//DB_DFSM_PRIMS_IN_FLIGHT
+#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0
+#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10
+#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL
+#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L
+//DB_DFSM_WATCHDOG
+#define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT 0x0
+#define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK 0xFFFFFFFFL
+//DB_DFSM_FLUSH_ENABLE
+#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT 0x0
+#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT 0x18
+#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT 0x1c
+#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK 0x000003FFL
+#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK 0x0F000000L
+#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK 0xF0000000L
+//DB_DFSM_FLUSH_AUX_EVENT
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT 0x0
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT 0x8
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT 0x10
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT 0x18
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK 0x000000FFL
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK 0x0000FF00L
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK 0x00FF0000L
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK 0xFF000000L
+//CC_RB_REDUNDANCY
+#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
+#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
+#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L
+#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L
+//CC_RB_BACKEND_DISABLE
+#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
+#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L
+//GB_ADDR_CONFIG
+#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
+#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15
+#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a
+#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define GB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f
+#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
+#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
+#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L
+#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
+#define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L
+#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
+#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
+#define GB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L
+//GB_BACKEND_MAP
+#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0
+#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL
+//GB_GPU_ID
+#define GB_GPU_ID__GPU_ID__SHIFT 0x0
+#define GB_GPU_ID__GPU_ID_MASK 0x0000000FL
+//CC_RB_DAISY_CHAIN
+#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0
+#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4
+#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8
+#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc
+#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10
+#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
+#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18
+#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c
+#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000FL
+#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000F0L
+#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000F00L
+#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000F000L
+#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000F0000L
+#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00F00000L
+#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0F000000L
+#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xF0000000L
+//GB_ADDR_CONFIG_READ
+#define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
+#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6
+#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
+#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
+#define GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT 0x15
+#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a
+#define GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT 0x1c
+#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT 0x1e
+#define GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT 0x1f
+#define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
+#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
+#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
+#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
+#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
+#define GB_ADDR_CONFIG_READ__NUM_GPUS_MASK 0x00E00000L
+#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
+#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L
+#define GB_ADDR_CONFIG_READ__ROW_SIZE_MASK 0x30000000L
+#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK 0x40000000L
+#define GB_ADDR_CONFIG_READ__SE_ENABLE_MASK 0x80000000L
+//GB_TILE_MODE0
+#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE1
+#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE2
+#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE3
+#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE4
+#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE5
+#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE6
+#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE7
+#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE8
+#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE9
+#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE10
+#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE11
+#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE12
+#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE13
+#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE14
+#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE15
+#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE16
+#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE17
+#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE18
+#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE19
+#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE20
+#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE21
+#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE22
+#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE23
+#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE24
+#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE25
+#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE26
+#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE27
+#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE28
+#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE29
+#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE30
+#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE31
+#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_MACROTILE_MODE0
+#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE1
+#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE2
+#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE3
+#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE4
+#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE5
+#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE6
+#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE7
+#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE8
+#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE9
+#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE10
+#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE11
+#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE12
+#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE13
+#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE14
+#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE15
+#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0x000000C0L
+//CB_HW_CONTROL
+#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
+#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
+#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
+#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
+#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
+#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
+#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
+#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
+#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
+#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
+#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
+#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
+#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
+#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000FL
+#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003C0L
+#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000F000L
+#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L
+#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L
+#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L
+#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L
+#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L
+#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L
+#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L
+#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L
+#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L
+#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L
+//CB_HW_CONTROL_1
+#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
+#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
+#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
+#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
+#define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT 0x1a
+#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001FL
+#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007E0L
+#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001F800L
+#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03FE0000L
+#define CB_HW_CONTROL_1__RMI_CREDITS_MASK 0xFC000000L
+//CB_HW_CONTROL_2
+#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
+#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
+#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
+#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18
+#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c
+#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000FFL
+#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007F00L
+#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007F8000L
+#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x0F000000L
+#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xF0000000L
+//CB_HW_CONTROL_3
+#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
+#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1
+#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2
+#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3
+#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7
+#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8
+#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9
+#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa
+#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb
+#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc
+#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd
+#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT 0xe
+#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0xf
+#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0x10
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0x11
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT 0x12
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0x13
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT 0x14
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0x15
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT 0x16
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x17
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT 0x18
+#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT 0x19
+#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT 0x1a
+#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT 0x1b
+#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS__SHIFT 0x1c
+#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L
+#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L
+#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x00000004L
+#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x00000008L
+#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x00000010L
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000020L
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x00000040L
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000080L
+#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x00000100L
+#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000200L
+#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000400L
+#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x00000800L
+#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x00001000L
+#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x00002000L
+#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK 0x00004000L
+#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00008000L
+#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00010000L
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00020000L
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK 0x00040000L
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00080000L
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK 0x00100000L
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00200000L
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK 0x00400000L
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00800000L
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK 0x01000000L
+#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK 0x02000000L
+#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK 0x04000000L
+#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK 0x08000000L
+#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS_MASK 0x30000000L
+//CB_HW_MEM_ARBITER_RD
+#define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x0
+#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x2
+#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x6
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT 0xc
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT 0xe
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0x10
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0x12
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x14
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x16
+#define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x17
+#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x1a
+#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d
+#define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L
+#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003CL
+#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003C0L
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000C00L
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK 0x00003000L
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK 0x0000C000L
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00030000L
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x000C0000L
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00300000L
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00400000L
+#define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x03800000L
+#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x1C000000L
+#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L
+//CB_HW_MEM_ARBITER_WR
+#define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x0
+#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x2
+#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x6
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT 0xc
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT 0xe
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0x10
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0x12
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x14
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x16
+#define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x17
+#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x1a
+#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d
+#define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L
+#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003CL
+#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003C0L
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000C00L
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK 0x00003000L
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK 0x0000C000L
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00030000L
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x000C0000L
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00300000L
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00400000L
+#define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x03800000L
+#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x1C000000L
+#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L
+//CB_DCC_CONFIG
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6
+#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8
+#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10
+#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18
+#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x0000001FL
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x00000020L
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x00000040L
+#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0x0000FF00L
+#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x007F0000L
+#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0x0F000000L
+#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xF0000000L
+//GC_USER_RB_REDUNDANCY
+#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
+#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
+#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L
+#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L
+//GC_USER_RB_BACKEND_DISABLE
+#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
+#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L
+
+
+// addressBlock: gc_rmi_rmidec
+//RMI_GENERAL_CNTL
+#define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0
+#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1
+#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT 0x11
+#define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13
+#define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT 0x14
+#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15
+#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT 0x19
+#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT 0x1a
+#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT 0x1b
+#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT 0x1c
+#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT 0x1d
+#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT 0x1e
+#define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L
+#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL
+#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK 0x00060000L
+#define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L
+#define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK 0x00100000L
+#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L
+#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK 0x02000000L
+#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK 0x04000000L
+#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK 0x08000000L
+#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK 0x10000000L
+#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK 0x20000000L
+#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK 0x40000000L
+//RMI_GENERAL_CNTL1
+#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0
+#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4
+#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6
+#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8
+#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9
+#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xa
+#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT 0xb
+#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT 0xc
+#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL
+#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L
+#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L
+#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L
+#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000200L
+#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000400L
+#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK 0x00000800L
+#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK 0x00001000L
+//RMI_GENERAL_STATUS
+#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0
+#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1
+#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2
+#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3
+#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4
+#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5
+#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT 0x6
+#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7
+#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8
+#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9
+#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa
+#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb
+#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc
+#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd
+#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe
+#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf
+#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x10
+#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x11
+#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT 0x12
+#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT 0x13
+#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT 0x14
+#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT 0x15
+#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT 0x1d
+#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT 0x1e
+#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f
+#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L
+#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L
+#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L
+#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L
+#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L
+#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L
+#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK 0x00000040L
+#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L
+#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L
+#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L
+#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L
+#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L
+#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L
+#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L
+#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L
+#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L
+#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00010000L
+#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00020000L
+#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK 0x00040000L
+#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK 0x00080000L
+#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK 0x00100000L
+#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK 0x1FE00000L
+#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK 0x20000000L
+#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK 0x40000000L
+#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L
+//RMI_SUBBLOCK_STATUS0
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11
+#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L
+#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L
+//RMI_SUBBLOCK_STATUS1
+#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0
+#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa
+#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14
+#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL
+#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L
+#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L
+//RMI_SUBBLOCK_STATUS2
+#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0
+#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9
+#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL
+#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L
+//RMI_SUBBLOCK_STATUS3
+#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0
+#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa
+#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL
+#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L
+//RMI_XBAR_CONFIG
+#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0
+#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2
+#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6
+#define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT 0xe
+#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L
+#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL
+#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L
+#define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK 0x00004000L
+//RMI_PROBE_POP_LOGIC_CNTL
+#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0
+#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7
+#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8
+#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa
+#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11
+#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL
+#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L
+#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L
+#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L
+#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L
+//RMI_UTC_XNACK_N_MISC_CNTL
+#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0
+#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8
+#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc
+#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd
+#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL
+#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L
+#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L
+#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L
+//RMI_DEMUX_CNTL
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT 0x0
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x1
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x4
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT 0x10
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x11
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x14
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK 0x00000001L
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000002L
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK 0x00000030L
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK 0x00010000L
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00020000L
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00300000L
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L
+//RMI_UTCL1_CNTL1
+#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
+#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
+#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
+#define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
+#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
+#define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
+#define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10
+#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
+#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
+#define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
+#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
+#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
+#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
+#define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
+#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
+#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
+#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
+#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
+#define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
+#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
+#define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
+#define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L
+#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
+#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
+#define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
+#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
+#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
+#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
+#define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
+#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
+#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
+#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
+//RMI_UTCL1_CNTL2
+#define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0
+#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
+#define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
+#define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
+#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
+#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
+#define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
+#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
+#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10
+#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
+#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13
+#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14
+#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15
+#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19
+#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
+#define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL
+#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
+#define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
+#define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
+#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
+#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
+#define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
+#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
+#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L
+#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
+#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L
+#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
+#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L
+#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L
+#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
+//RMI_UTC_UNIT_CONFIG
+//RMI_TCIW_FORMATTER0_CNTL
+#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT 0x0
+#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT 0x1
+#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9
+#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT 0x13
+#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b
+#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT 0x1c
+#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d
+#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT 0x1e
+#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f
+#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK 0x00000001L
+#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK 0x000001FEL
+#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L
+#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK 0x07F80000L
+#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L
+#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK 0x10000000L
+#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L
+#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK 0x40000000L
+#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L
+//RMI_TCIW_FORMATTER1_CNTL
+#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0
+#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1
+#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9
+#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT 0x13
+#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b
+#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT 0x1c
+#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d
+#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e
+#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f
+#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L
+#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL
+#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L
+#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK 0x07F80000L
+#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L
+#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK 0x10000000L
+#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L
+#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L
+#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L
+//RMI_SCOREBOARD_CNTL
+#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0
+#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1
+#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2
+#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3
+#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT 0x4
+#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5
+#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6
+#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT 0x7
+#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT 0x8
+#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9
+#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L
+#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L
+#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L
+#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L
+#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK 0x00000010L
+#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L
+#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L
+#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK 0x00000080L
+#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK 0x00000100L
+#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L
+//RMI_SCOREBOARD_STATUS0
+#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14
+#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15
+#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L
+#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L
+//RMI_SCOREBOARD_STATUS1
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd
+#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c
+#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d
+#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L
+#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L
+#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L
+#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L
+//RMI_SCOREBOARD_STATUS2
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19
+#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a
+#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L
+#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L
+#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L
+//RMI_XBAR_ARBITER_CONFIG
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L
+//RMI_XBAR_ARBITER_CONFIG_1
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT 0x10
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT 0x18
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK 0x00FF0000L
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK 0xFF000000L
+//RMI_CLOCK_CNTRL
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0
+#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa
+#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT 0x14
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT 0x19
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL
+#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L
+#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK 0x01F00000L
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK 0x3E000000L
+//RMI_UTCL1_STATUS
+#define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+//RMI_XNACK_DEBUG
+#define RMI_XNACK_DEBUG__XNACK_PER_VMID__SHIFT 0x0
+#define RMI_XNACK_DEBUG__XNACK_PER_VMID_MASK 0x0000FFFFL
+//RMI_SPARE
+#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT 0x0
+#define RMI_SPARE__SPARE_BIT_1__SHIFT 0x1
+#define RMI_SPARE__SPARE_BIT_2__SHIFT 0x2
+#define RMI_SPARE__SPARE_BIT_3__SHIFT 0x3
+#define RMI_SPARE__SPARE_BIT_4__SHIFT 0x4
+#define RMI_SPARE__SPARE_BIT_5__SHIFT 0x5
+#define RMI_SPARE__SPARE_BIT_6__SHIFT 0x6
+#define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7
+#define RMI_SPARE__SPARE_BIT_8_0__SHIFT 0x8
+#define RMI_SPARE__SPARE_BIT_16_0__SHIFT 0x10
+#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK 0x00000001L
+#define RMI_SPARE__SPARE_BIT_1_MASK 0x00000002L
+#define RMI_SPARE__SPARE_BIT_2_MASK 0x00000004L
+#define RMI_SPARE__SPARE_BIT_3_MASK 0x00000008L
+#define RMI_SPARE__SPARE_BIT_4_MASK 0x00000010L
+#define RMI_SPARE__SPARE_BIT_5_MASK 0x00000020L
+#define RMI_SPARE__SPARE_BIT_6_MASK 0x00000040L
+#define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L
+#define RMI_SPARE__SPARE_BIT_8_0_MASK 0x0000FF00L
+#define RMI_SPARE__SPARE_BIT_16_0_MASK 0xFFFF0000L
+//RMI_SPARE_1
+#define RMI_SPARE_1__SPARE_BIT_8__SHIFT 0x0
+#define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1
+#define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2
+#define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3
+#define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4
+#define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5
+#define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6
+#define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7
+#define RMI_SPARE_1__SPARE_BIT_8_1__SHIFT 0x8
+#define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10
+#define RMI_SPARE_1__SPARE_BIT_8_MASK 0x00000001L
+#define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L
+#define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L
+#define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L
+#define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L
+#define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L
+#define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L
+#define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L
+#define RMI_SPARE_1__SPARE_BIT_8_1_MASK 0x0000FF00L
+#define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L
+//RMI_SPARE_2
+#define RMI_SPARE_2__SPARE_BIT_16__SHIFT 0x0
+#define RMI_SPARE_2__SPARE_BIT_17__SHIFT 0x1
+#define RMI_SPARE_2__SPARE_BIT_18__SHIFT 0x2
+#define RMI_SPARE_2__SPARE_BIT_19__SHIFT 0x3
+#define RMI_SPARE_2__SPARE_BIT_20__SHIFT 0x4
+#define RMI_SPARE_2__SPARE_BIT_21__SHIFT 0x5
+#define RMI_SPARE_2__SPARE_BIT_22__SHIFT 0x6
+#define RMI_SPARE_2__SPARE_BIT_23__SHIFT 0x7
+#define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT 0x8
+#define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT 0xc
+#define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10
+#define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18
+#define RMI_SPARE_2__SPARE_BIT_16_MASK 0x00000001L
+#define RMI_SPARE_2__SPARE_BIT_17_MASK 0x00000002L
+#define RMI_SPARE_2__SPARE_BIT_18_MASK 0x00000004L
+#define RMI_SPARE_2__SPARE_BIT_19_MASK 0x00000008L
+#define RMI_SPARE_2__SPARE_BIT_20_MASK 0x00000010L
+#define RMI_SPARE_2__SPARE_BIT_21_MASK 0x00000020L
+#define RMI_SPARE_2__SPARE_BIT_22_MASK 0x00000040L
+#define RMI_SPARE_2__SPARE_BIT_23_MASK 0x00000080L
+#define RMI_SPARE_2__SPARE_BIT_4_0_MASK 0x00000F00L
+#define RMI_SPARE_2__SPARE_BIT_4_1_MASK 0x0000F000L
+#define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L
+#define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L
+
+
+// addressBlock: gc_utcl2_atcl2dec
+//ATC_L2_CNTL
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7
+#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8
+#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L
+#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L
+#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
+//ATC_L2_CNTL2
+#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
+#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
+#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
+#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
+#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
+#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L
+#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L
+#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L
+//ATC_L2_CACHE_DATA0
+#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0
+#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1
+#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2
+#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17
+#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L
+#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L
+#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL
+#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L
+//ATC_L2_CACHE_DATA1
+#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0
+#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL
+//ATC_L2_CACHE_DATA2
+#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0
+#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL
+//ATC_L2_CNTL3
+#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0
+#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3
+#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L
+#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L
+//ATC_L2_STATUS
+#define ATC_L2_STATUS__BUSY__SHIFT 0x0
+#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1
+#define ATC_L2_STATUS__BUSY_MASK 0x00000001L
+#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL
+//ATC_L2_STATUS2
+#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0
+#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8
+#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL
+#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L
+//ATC_L2_MISC_CG
+#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6
+#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12
+#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L
+#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L
+#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L
+//ATC_L2_MEM_POWER_LS
+#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
+#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
+#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
+#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
+//ATC_L2_CGTT_CLK_CTRL
+#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
+#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
+#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
+#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
+
+
+// addressBlock: gc_utcl2_vml2pfdec
+//VM_L2_CNTL
+#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
+#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
+#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
+#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
+#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
+#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
+#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
+#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
+#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
+#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
+#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
+#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
+#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
+#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a
+#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L
+#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L
+#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL
+#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L
+#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L
+#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L
+#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L
+#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
+#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L
+#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L
+#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L
+#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L
+#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L
+#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L
+//VM_L2_CNTL2
+#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
+#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
+#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
+#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
+#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17
+#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
+#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
+#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L
+#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L
+#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L
+#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L
+#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L
+#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L
+#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L
+//VM_L2_CNTL3
+#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
+#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
+#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
+#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
+#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
+#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
+#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f
+#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L
+#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L
+#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L
+#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L
+#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L
+#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L
+#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L
+//VM_L2_STATUS
+#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0
+#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
+#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11
+#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12
+#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13
+#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14
+#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15
+#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L
+#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL
+#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L
+#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L
+#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L
+#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L
+#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L
+//VM_DUMMY_PAGE_FAULT_CNTL
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL
+//VM_DUMMY_PAGE_FAULT_ADDR_LO32
+#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0
+#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//VM_DUMMY_PAGE_FAULT_ADDR_HI32
+#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0
+#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL
+//VM_L2_PROTECTION_FAULT_CNTL
+#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1
+#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5
+#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6
+#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
+#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8
+#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9
+#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb
+#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd
+#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d
+#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e
+#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f
+#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L
+#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L
+#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L
+#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L
+#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L
+#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L
+#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L
+#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L
+#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L
+#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L
+#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L
+#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L
+//VM_L2_PROTECTION_FAULT_CNTL2
+#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10
+#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11
+#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12
+#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13
+#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL
+#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L
+#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L
+#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L
+#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L
+//VM_L2_PROTECTION_FAULT_MM_CNTL3
+#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
+//VM_L2_PROTECTION_FAULT_MM_CNTL4
+#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
+//VM_L2_PROTECTION_FAULT_STATUS
+#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1
+#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4
+#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8
+#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9
+#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12
+#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13
+#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14
+#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18
+#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19
+#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L
+#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL
+#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L
+#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L
+#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L
+#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L
+#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L
+#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L
+#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L
+#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L
+//VM_L2_PROTECTION_FAULT_ADDR_LO32
+#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//VM_L2_PROTECTION_FAULT_ADDR_HI32
+#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
+//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
+#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
+#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
+//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL
+//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL
+//VM_L2_CNTL4
+#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0
+#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6
+#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7
+#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8
+#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12
+#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c
+#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL
+#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L
+#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L
+#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L
+#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L
+#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L
+//VM_L2_MM_GROUP_RT_CLASSES
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L
+//VM_L2_BANK_SELECT_RESERVED_CID
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
+#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
+#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
+//VM_L2_BANK_SELECT_RESERVED_CID2
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
+#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
+#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
+//VM_L2_CACHE_PARITY_CNTL
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L
+//VM_L2_CGTT_CLK_CTRL
+#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
+#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
+#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
+#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
+
+
+// addressBlock: gc_utcl2_vml2vcdec
+//VM_CONTEXT0_CNTL
+#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT1_CNTL
+#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT2_CNTL
+#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT3_CNTL
+#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT4_CNTL
+#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT5_CNTL
+#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT6_CNTL
+#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT7_CNTL
+#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT8_CNTL
+#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT9_CNTL
+#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT10_CNTL
+#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT11_CNTL
+#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT12_CNTL
+#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT13_CNTL
+#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT14_CNTL
+#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT15_CNTL
+#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXTS_DISABLE
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L
+//VM_INVALIDATE_ENG0_SEM
+#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG1_SEM
+#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG2_SEM
+#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG3_SEM
+#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG4_SEM
+#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG5_SEM
+#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG6_SEM
+#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG7_SEM
+#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG8_SEM
+#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG9_SEM
+#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG10_SEM
+#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG11_SEM
+#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG12_SEM
+#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG13_SEM
+#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG14_SEM
+#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG15_SEM
+#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG16_SEM
+#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG17_SEM
+#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG0_REQ
+#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG1_REQ
+#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG2_REQ
+#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG3_REQ
+#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG4_REQ
+#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG5_REQ
+#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG6_REQ
+#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG7_REQ
+#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG8_REQ
+#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG9_REQ
+#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG10_REQ
+#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG11_REQ
+#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG12_REQ
+#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG13_REQ
+#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG14_REQ
+#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG15_REQ
+#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG16_REQ
+#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG17_REQ
+#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG0_ACK
+#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG1_ACK
+#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG2_ACK
+#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG3_ACK
+#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG4_ACK
+#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG5_ACK
+#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG6_ACK
+#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG7_ACK
+#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG8_ACK
+#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG9_ACK
+#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG10_ACK
+#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG11_ACK
+#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG12_ACK
+#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG13_ACK
+#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG14_ACK
+#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG15_ACK
+#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG16_ACK
+#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG17_ACK
+#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+
+
+// addressBlock: gc_utcl2_vmsharedpfdec
+//MC_VM_NB_MMIOBASE
+#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0
+#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL
+//MC_VM_NB_MMIOLIMIT
+#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0
+#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL
+//MC_VM_NB_PCI_CTRL
+#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17
+#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L
+//MC_VM_NB_PCI_ARB
+#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3
+#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L
+//MC_VM_NB_TOP_OF_DRAM_SLOT1
+#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17
+#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L
+//MC_VM_NB_LOWER_TOP_OF_DRAM2
+#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0
+#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17
+#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L
+#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L
+//MC_VM_NB_UPPER_TOP_OF_DRAM2
+#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0
+#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL
+//MC_VM_FB_OFFSET
+#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
+#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL
+//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL
+//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL
+//MC_VM_STEERING
+#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
+#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L
+//MC_SHARED_VIRT_RESET_REQ
+#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
+#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L
+//MC_MEM_POWER_LS
+#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
+#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
+#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
+#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
+//MC_VM_CACHEABLE_DRAM_ADDRESS_START
+#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0
+#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
+//MC_VM_CACHEABLE_DRAM_ADDRESS_END
+#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0
+#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
+//MC_VM_APT_CNTL
+#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0
+#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1
+#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L
+#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L
+//MC_VM_LOCAL_HBM_ADDRESS_START
+#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0
+#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
+//MC_VM_LOCAL_HBM_ADDRESS_END
+#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0
+#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
+//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
+#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0
+#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L
+
+
+// addressBlock: gc_utcl2_vmsharedvcdec
+//MC_VM_FB_LOCATION_BASE
+#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0
+#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL
+//MC_VM_FB_LOCATION_TOP
+#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0
+#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL
+//MC_VM_AGP_TOP
+#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
+#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL
+//MC_VM_AGP_BOT
+#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
+#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL
+//MC_VM_AGP_BASE
+#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
+#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL
+//MC_VM_SYSTEM_APERTURE_LOW_ADDR
+#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
+//MC_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
+//MC_VM_MX_L1_TLB_CNTL
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
+#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
+#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb
+#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L
+#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L
+#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L
+#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L
+
+
+// addressBlock: gc_tcdec
+//TCP_INVALIDATE
+#define TCP_INVALIDATE__START__SHIFT 0x0
+#define TCP_INVALIDATE__START_MASK 0x00000001L
+//TCP_STATUS
+#define TCP_STATUS__TCP_BUSY__SHIFT 0x0
+#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1
+#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2
+#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3
+#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4
+#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5
+#define TCP_STATUS__READ_BUSY__SHIFT 0x6
+#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7
+#define TCP_STATUS__VM_BUSY__SHIFT 0x8
+#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L
+#define TCP_STATUS__INPUT_BUSY_MASK 0x00000002L
+#define TCP_STATUS__ADRS_BUSY_MASK 0x00000004L
+#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000008L
+#define TCP_STATUS__CNTRL_BUSY_MASK 0x00000010L
+#define TCP_STATUS__LFIFO_BUSY_MASK 0x00000020L
+#define TCP_STATUS__READ_BUSY_MASK 0x00000040L
+#define TCP_STATUS__FORMAT_BUSY_MASK 0x00000080L
+#define TCP_STATUS__VM_BUSY_MASK 0x00000100L
+//TCP_CNTL
+#define TCP_CNTL__FORCE_HIT__SHIFT 0x0
+#define TCP_CNTL__FORCE_MISS__SHIFT 0x1
+#define TCP_CNTL__L1_SIZE__SHIFT 0x2
+#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4
+#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5
+#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf
+#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16
+#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c
+#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d
+#define TCP_CNTL__ASTC_VE_MSB_TOLERANT__SHIFT 0x1e
+#define TCP_CNTL__FORCE_HIT_MASK 0x00000001L
+#define TCP_CNTL__FORCE_MISS_MASK 0x00000002L
+#define TCP_CNTL__L1_SIZE_MASK 0x0000000CL
+#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x00000010L
+#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x00000020L
+#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001F8000L
+#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0x0FC00000L
+#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L
+#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000L
+#define TCP_CNTL__ASTC_VE_MSB_TOLERANT_MASK 0x40000000L
+//TCP_CHAN_STEER_LO
+#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0
+#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4
+#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8
+#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc
+#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10
+#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14
+#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18
+#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c
+#define TCP_CHAN_STEER_LO__CHAN0_MASK 0x0000000FL
+#define TCP_CHAN_STEER_LO__CHAN1_MASK 0x000000F0L
+#define TCP_CHAN_STEER_LO__CHAN2_MASK 0x00000F00L
+#define TCP_CHAN_STEER_LO__CHAN3_MASK 0x0000F000L
+#define TCP_CHAN_STEER_LO__CHAN4_MASK 0x000F0000L
+#define TCP_CHAN_STEER_LO__CHAN5_MASK 0x00F00000L
+#define TCP_CHAN_STEER_LO__CHAN6_MASK 0x0F000000L
+#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xF0000000L
+//TCP_CHAN_STEER_HI
+#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0
+#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4
+#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8
+#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc
+#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10
+#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14
+#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18
+#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c
+#define TCP_CHAN_STEER_HI__CHAN8_MASK 0x0000000FL
+#define TCP_CHAN_STEER_HI__CHAN9_MASK 0x000000F0L
+#define TCP_CHAN_STEER_HI__CHANA_MASK 0x00000F00L
+#define TCP_CHAN_STEER_HI__CHANB_MASK 0x0000F000L
+#define TCP_CHAN_STEER_HI__CHANC_MASK 0x000F0000L
+#define TCP_CHAN_STEER_HI__CHAND_MASK 0x00F00000L
+#define TCP_CHAN_STEER_HI__CHANE_MASK 0x0F000000L
+#define TCP_CHAN_STEER_HI__CHANF_MASK 0xF0000000L
+//TCP_ADDR_CONFIG
+#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0
+#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4
+#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6
+#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9
+#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000000FL
+#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x00000030L
+#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x000001C0L
+#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x00000200L
+//TCP_CREDIT
+#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0
+#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10
+#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d
+#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x000003FFL
+#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007F0000L
+#define TCP_CREDIT__TD_CREDIT_MASK 0xE0000000L
+//TCP_BUFFER_ADDR_HASH_CNTL
+#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0
+#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8
+#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10
+#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18
+#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x00000007L
+#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x00000700L
+#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x00070000L
+#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x07000000L
+//TCP_EDC_CNT
+#define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0
+#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8
+#define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10
+#define TCP_EDC_CNT__SEC_COUNT_MASK 0x000000FFL
+#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0x0000FF00L
+#define TCP_EDC_CNT__DED_COUNT_MASK 0x00FF0000L
+//TC_CFG_L1_LOAD_POLICY0
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x00000003L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x00000030L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x00000300L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x00003000L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x00030000L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x00300000L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x03000000L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L
+//TC_CFG_L1_LOAD_POLICY1
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x00000003L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x00000030L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x00000300L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x00003000L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x00030000L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x00300000L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x03000000L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L
+//TC_CFG_L1_STORE_POLICY
+#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0
+#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1
+#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2
+#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3
+#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4
+#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5
+#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6
+#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7
+#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8
+#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9
+#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa
+#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb
+#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc
+#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd
+#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe
+#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf
+#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10
+#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11
+#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12
+#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13
+#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14
+#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15
+#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16
+#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17
+#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18
+#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19
+#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a
+#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b
+#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c
+#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d
+#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e
+#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f
+#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x00000001L
+#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x00000002L
+#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x00000004L
+#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x00000008L
+#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x00000010L
+#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x00000020L
+#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x00000040L
+#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x00000080L
+#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x00000100L
+#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x00000200L
+#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x00000400L
+#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x00000800L
+#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x00001000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x00002000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x00004000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x00008000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x00010000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x00020000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x00040000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x00080000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x00100000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x00200000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x00400000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x00800000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x01000000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x02000000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x04000000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x08000000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000L
+//TC_CFG_L2_LOAD_POLICY0
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x00000003L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x00000030L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x00000300L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x00003000L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x00030000L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x00300000L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x03000000L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L
+//TC_CFG_L2_LOAD_POLICY1
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x00000003L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x00000030L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x00000300L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x00003000L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x00030000L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x00300000L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x03000000L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L
+//TC_CFG_L2_STORE_POLICY0
+#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0
+#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2
+#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4
+#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6
+#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8
+#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa
+#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc
+#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe
+#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10
+#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12
+#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14
+#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16
+#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18
+#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a
+#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c
+#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e
+#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x00000003L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0x0000000CL
+#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x00000030L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0x000000C0L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x00000300L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0x00000C00L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x00003000L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0x0000C000L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x00030000L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0x000C0000L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x00300000L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0x00C00000L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x03000000L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0x0C000000L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xC0000000L
+//TC_CFG_L2_STORE_POLICY1
+#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0
+#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2
+#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4
+#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6
+#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8
+#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa
+#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc
+#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe
+#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10
+#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12
+#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14
+#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16
+#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18
+#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a
+#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c
+#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e
+#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x00000003L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0x0000000CL
+#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x00000030L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0x000000C0L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x00000300L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0x00000C00L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x00003000L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0x0000C000L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x00030000L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0x000C0000L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x00300000L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0x00C00000L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x03000000L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0x0C000000L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xC0000000L
+//TC_CFG_L2_ATOMIC_POLICY
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x00000003L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0x0000000CL
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x00000030L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0x000000C0L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x00000300L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0x00000C00L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x00003000L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0x0000C000L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x00030000L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0x000C0000L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x00300000L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0x00C00000L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x03000000L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0x0C000000L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xC0000000L
+//TC_CFG_L1_VOLATILE
+#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0
+#define TC_CFG_L1_VOLATILE__VOL_MASK 0x0000000FL
+//TC_CFG_L2_VOLATILE
+#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0
+#define TC_CFG_L2_VOLATILE__VOL_MASK 0x0000000FL
+//TCI_STATUS
+#define TCI_STATUS__TCI_BUSY__SHIFT 0x0
+#define TCI_STATUS__TCI_BUSY_MASK 0x00000001L
+//TCI_CNTL_1
+#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0
+#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10
+#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18
+#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000FFFFL
+#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00FF0000L
+#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xFF000000L
+//TCI_CNTL_2
+#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0
+#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1
+#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L
+#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001FEL
+//TCC_CTRL
+#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0
+#define TCC_CTRL__RATE__SHIFT 0x2
+#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4
+#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8
+#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc
+#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10
+#define TCC_CTRL__LINEAR_SET_HASH__SHIFT 0x15
+#define TCC_CTRL__MDC_SIZE__SHIFT 0x18
+#define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT 0x1a
+#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c
+#define TCC_CTRL__CACHE_SIZE_MASK 0x00000003L
+#define TCC_CTRL__RATE_MASK 0x0000000CL
+#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0x000000F0L
+#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0x00000F00L
+#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0x0000F000L
+#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0x000F0000L
+#define TCC_CTRL__LINEAR_SET_HASH_MASK 0x00200000L
+#define TCC_CTRL__MDC_SIZE_MASK 0x03000000L
+#define TCC_CTRL__MDC_SECTOR_SIZE_MASK 0x0C000000L
+#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xF0000000L
+//TCC_CTRL2
+#define TCC_CTRL2__PROBE_FIFO_SIZE__SHIFT 0x0
+#define TCC_CTRL2__PROBE_FIFO_SIZE_MASK 0x0000000FL
+//TCC_EDC_CNT
+#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT__SHIFT 0x0
+#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT__SHIFT 0x2
+#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT__SHIFT 0x4
+#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT__SHIFT 0x6
+#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT__SHIFT 0x8
+#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT__SHIFT 0xa
+#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT__SHIFT 0xc
+#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT__SHIFT 0xe
+#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT 0x10
+#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT__SHIFT 0x12
+#define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT__SHIFT 0x14
+#define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT__SHIFT 0x16
+#define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT__SHIFT 0x18
+#define TCC_EDC_CNT__RETURN_DATA_SED_COUNT__SHIFT 0x1a
+#define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT__SHIFT 0x1c
+#define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT__SHIFT 0x1e
+#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT_MASK 0x00000003L
+#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT_MASK 0x0000000CL
+#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT_MASK 0x00000030L
+#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT_MASK 0x000000C0L
+#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT_MASK 0x00000300L
+#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT_MASK 0x00000C00L
+#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT_MASK 0x00003000L
+#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT_MASK 0x0000C000L
+#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT_MASK 0x00030000L
+#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT_MASK 0x000C0000L
+#define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT_MASK 0x00300000L
+#define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT_MASK 0x00C00000L
+#define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT_MASK 0x03000000L
+#define TCC_EDC_CNT__RETURN_DATA_SED_COUNT_MASK 0x0C000000L
+#define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT_MASK 0x30000000L
+#define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT_MASK 0xC0000000L
+//TCC_EDC_CNT2
+#define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT__SHIFT 0x0
+#define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT__SHIFT 0x2
+#define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x4
+#define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x6
+#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT__SHIFT 0x8
+#define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT_MASK 0x00000003L
+#define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT_MASK 0x0000000CL
+#define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT_MASK 0x00000030L
+#define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT_MASK 0x000000C0L
+#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT_MASK 0x00000300L
+//TCC_REDUNDANCY
+#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0
+#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1
+#define TCC_REDUNDANCY__MC_SEL0_MASK 0x00000001L
+#define TCC_REDUNDANCY__MC_SEL1_MASK 0x00000002L
+//TCC_EXE_DISABLE
+#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1
+#define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x00000002L
+//TCC_DSM_CNTL
+#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL__SHIFT 0x0
+#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL__SHIFT 0x3
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL__SHIFT 0x6
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE__SHIFT 0x8
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL__SHIFT 0x9
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE__SHIFT 0xb
+#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL__SHIFT 0xc
+#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE__SHIFT 0xe
+#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL__SHIFT 0xf
+#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x11
+#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x12
+#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x14
+#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x15
+#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x17
+#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL__SHIFT 0x18
+#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a
+#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL__SHIFT 0x1b
+#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d
+#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL_MASK 0x00000003L
+#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL_MASK 0x00000018L
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL_MASK 0x000000C0L
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL_MASK 0x00000600L
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L
+#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL_MASK 0x00003000L
+#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L
+#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL_MASK 0x00018000L
+#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L
+#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x000C0000L
+#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L
+#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x00600000L
+#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L
+#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL_MASK 0x03000000L
+#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L
+#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL_MASK 0x18000000L
+#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L
+//TCC_DSM_CNTLA
+#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x0
+#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
+#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x3
+#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
+#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL__SHIFT 0x6
+#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT 0x8
+#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL__SHIFT 0x9
+#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE__SHIFT 0xb
+#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc
+#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe
+#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xf
+#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x11
+#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x12
+#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x14
+#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x15
+#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x17
+#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL__SHIFT 0x18
+#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a
+#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL__SHIFT 0x1b
+#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d
+#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000003L
+#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
+#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000018L
+#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
+#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL_MASK 0x000000C0L
+#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L
+#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL_MASK 0x00000600L
+#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L
+#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L
+#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L
+#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00018000L
+#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L
+#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL_MASK 0x000C0000L
+#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L
+#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL_MASK 0x00600000L
+#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L
+#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL_MASK 0x03000000L
+#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L
+#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL_MASK 0x18000000L
+#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L
+//TCC_DSM_CNTL2
+#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY__SHIFT 0x2
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY__SHIFT 0x5
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY__SHIFT 0x8
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY__SHIFT 0xb
+#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY__SHIFT 0xe
+#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY__SHIFT 0x11
+#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x14
+#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x17
+#define TCC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
+#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00800000L
+#define TCC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
+//TCC_DSM_CNTL2A
+#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY__SHIFT 0x2
+#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY__SHIFT 0x5
+#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY__SHIFT 0x8
+#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY__SHIFT 0xb
+#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY__SHIFT 0xe
+#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY__SHIFT 0x11
+#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY__SHIFT 0x14
+#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY__SHIFT 0x17
+#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18
+#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a
+#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x1b
+#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY__SHIFT 0x1d
+#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY_MASK 0x00800000L
+#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L
+#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L
+#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT_MASK 0x18000000L
+#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY_MASK 0x20000000L
+//TCC_DSM_CNTL2B
+#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY__SHIFT 0x2
+#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L
+//TCC_WBINVL2
+#define TCC_WBINVL2__DONE__SHIFT 0x4
+#define TCC_WBINVL2__DONE_MASK 0x00000010L
+//TCC_SOFT_RESET
+#define TCC_SOFT_RESET__HALT_FOR_RESET__SHIFT 0x0
+#define TCC_SOFT_RESET__HALT_FOR_RESET_MASK 0x00000001L
+//TCA_CTRL
+#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0
+#define TCA_CTRL__RB_STILL_4_PHASE__SHIFT 0x4
+#define TCA_CTRL__RB_AS_TCI__SHIFT 0x5
+#define TCA_CTRL__DISABLE_UTCL2_PRIORITY__SHIFT 0x6
+#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER__SHIFT 0x7
+#define TCA_CTRL__HOLE_TIMEOUT_MASK 0x0000000FL
+#define TCA_CTRL__RB_STILL_4_PHASE_MASK 0x00000010L
+#define TCA_CTRL__RB_AS_TCI_MASK 0x00000020L
+#define TCA_CTRL__DISABLE_UTCL2_PRIORITY_MASK 0x00000040L
+#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER_MASK 0x00000080L
+//TCA_BURST_MASK
+#define TCA_BURST_MASK__ADDR_MASK__SHIFT 0x0
+#define TCA_BURST_MASK__ADDR_MASK_MASK 0xFFFFFFFFL
+//TCA_BURST_CTRL
+#define TCA_BURST_CTRL__MAX_BURST__SHIFT 0x0
+#define TCA_BURST_CTRL__RB_DISABLE__SHIFT 0x3
+#define TCA_BURST_CTRL__TCP_DISABLE__SHIFT 0x4
+#define TCA_BURST_CTRL__SQC_DISABLE__SHIFT 0x5
+#define TCA_BURST_CTRL__CPF_DISABLE__SHIFT 0x6
+#define TCA_BURST_CTRL__CPG_DISABLE__SHIFT 0x7
+#define TCA_BURST_CTRL__IA_DISABLE__SHIFT 0x8
+#define TCA_BURST_CTRL__WD_DISABLE__SHIFT 0x9
+#define TCA_BURST_CTRL__SQG_DISABLE__SHIFT 0xa
+#define TCA_BURST_CTRL__UTCL2_DISABLE__SHIFT 0xb
+#define TCA_BURST_CTRL__TPI_DISABLE__SHIFT 0xc
+#define TCA_BURST_CTRL__RLC_DISABLE__SHIFT 0xd
+#define TCA_BURST_CTRL__PA_DISABLE__SHIFT 0xe
+#define TCA_BURST_CTRL__MAX_BURST_MASK 0x00000007L
+#define TCA_BURST_CTRL__RB_DISABLE_MASK 0x00000008L
+#define TCA_BURST_CTRL__TCP_DISABLE_MASK 0x00000010L
+#define TCA_BURST_CTRL__SQC_DISABLE_MASK 0x00000020L
+#define TCA_BURST_CTRL__CPF_DISABLE_MASK 0x00000040L
+#define TCA_BURST_CTRL__CPG_DISABLE_MASK 0x00000080L
+#define TCA_BURST_CTRL__IA_DISABLE_MASK 0x00000100L
+#define TCA_BURST_CTRL__WD_DISABLE_MASK 0x00000200L
+#define TCA_BURST_CTRL__SQG_DISABLE_MASK 0x00000400L
+#define TCA_BURST_CTRL__UTCL2_DISABLE_MASK 0x00000800L
+#define TCA_BURST_CTRL__TPI_DISABLE_MASK 0x00001000L
+#define TCA_BURST_CTRL__RLC_DISABLE_MASK 0x00002000L
+#define TCA_BURST_CTRL__PA_DISABLE_MASK 0x00004000L
+//TCA_DSM_CNTL
+#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x0
+#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
+#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x3
+#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
+#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000003L
+#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
+#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000018L
+#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
+//TCA_DSM_CNTL2
+#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x2
+#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x5
+#define TCA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
+#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define TCA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
+//TCA_EDC_CNT
+#define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT__SHIFT 0x0
+#define TCA_EDC_CNT__REQ_FIFO_SED_COUNT__SHIFT 0x2
+#define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT_MASK 0x00000003L
+#define TCA_EDC_CNT__REQ_FIFO_SED_COUNT_MASK 0x0000000CL
+
+
+// addressBlock: gc_shdec
+//SPI_SHADER_PGM_RSRC3_PS
+#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000FFFFL
+#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x003F0000L
+#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
+#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE_MASK 0x3C000000L
+//SPI_SHADER_PGM_LO_PS
+#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_HI_PS
+#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xFFL
+//SPI_SHADER_PGM_RSRC1_PS
+#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x1d
+#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003FL
+#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003C0L
+#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000C00L
+#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000FF000L
+#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L
+#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L
+#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x00400000L
+#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L
+#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L
+#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000L
+#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L
+//SPI_SHADER_PGM_RSRC2_PS
+#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x19
+#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L
+#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000FF00L
+#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01FF0000L
+#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L
+#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L
+#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0_MASK 0x08000000L
+#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x10000000L
+//SPI_SHADER_USER_DATA_PS_0
+#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_1
+#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_2
+#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_3
+#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_4
+#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_5
+#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_6
+#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_7
+#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_8
+#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_9
+#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_10
+#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_11
+#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_12
+#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_13
+#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_14
+#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_15
+#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_16
+#define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_17
+#define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_18
+#define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_19
+#define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_20
+#define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_21
+#define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_22
+#define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_23
+#define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_24
+#define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_25
+#define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_26
+#define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_27
+#define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_28
+#define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_29
+#define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_30
+#define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_31
+#define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_RSRC3_VS
+#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0x0000FFFFL
+#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x003F0000L
+#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
+#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE_MASK 0x3C000000L
+//SPI_SHADER_LATE_ALLOC_VS
+#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0
+#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x0000003FL
+//SPI_SHADER_PGM_LO_VS
+#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_HI_VS
+#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xFFL
+//SPI_SHADER_PGM_RSRC1_VS
+#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x1e
+#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT 0x1f
+#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003FL
+#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003C0L
+#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000C00L
+#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000FF000L
+#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L
+#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L
+#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x00400000L
+#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L
+#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L
+#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L
+#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000L
+#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK 0x80000000L
+//SPI_SHADER_PGM_RSRC2_VS
+#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb
+#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd
+#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L
+#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L
+#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x003FE000L
+#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK 0x00400000L
+#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x01000000L
+#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0_MASK 0x08000000L
+#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK 0x10000000L
+//SPI_SHADER_USER_DATA_VS_0
+#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_1
+#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_2
+#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_3
+#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_4
+#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_5
+#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_6
+#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_7
+#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_8
+#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_9
+#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_10
+#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_11
+#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_12
+#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_13
+#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_14
+#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_15
+#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_16
+#define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_16__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_17
+#define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_17__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_18
+#define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_18__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_19
+#define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_19__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_20
+#define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_20__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_21
+#define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_21__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_22
+#define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_22__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_23
+#define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_23__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_24
+#define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_24__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_25
+#define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_25__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_26
+#define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_26__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_27
+#define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_27__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_28
+#define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_28__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_29
+#define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_29__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_30
+#define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_30__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_31
+#define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_31__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_RSRC2_GS_VS
+#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT 0x12
+#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT 0x13
+#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK 0x0000FF80L
+#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK 0x00030000L
+#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK 0x00040000L
+#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK 0x07F80000L
+#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK 0x08000000L
+#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK 0x10000000L
+//SPI_SHADER_PGM_RSRC4_GS
+#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH_MASK 0x0000007FL
+#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x00003F80L
+//SPI_SHADER_USER_DATA_ADDR_LO_GS
+#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ADDR_HI_GS
+#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_LO_ES
+#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_HI_ES
+#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xFFL
+//SPI_SHADER_PGM_RSRC3_GS
+#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0x0000FFFFL
+#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x003F0000L
+#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
+#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE_MASK 0x3C000000L
+//SPI_SHADER_PGM_LO_GS
+#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_HI_GS
+#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xFFL
+//SPI_SHADER_PGM_RSRC1_GS
+#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x1d
+#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x1f
+#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003FL
+#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003C0L
+#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000C00L
+#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000FF000L
+#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L
+#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L
+#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x00400000L
+#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L
+#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L
+#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000L
+#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L
+#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L
+//SPI_SHADER_PGM_RSRC2_GS
+#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x12
+#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x13
+#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000FF80L
+#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L
+#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L
+#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07F80000L
+#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0_MASK 0x08000000L
+#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x10000000L
+//SPI_SHADER_USER_DATA_ES_0
+#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_1
+#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_2
+#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_3
+#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_4
+#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_5
+#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_6
+#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_7
+#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_8
+#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_9
+#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_10
+#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_11
+#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_12
+#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_13
+#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_14
+#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_15
+#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_16
+#define SPI_SHADER_USER_DATA_ES_16__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_16__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_17
+#define SPI_SHADER_USER_DATA_ES_17__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_17__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_18
+#define SPI_SHADER_USER_DATA_ES_18__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_18__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_19
+#define SPI_SHADER_USER_DATA_ES_19__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_19__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_20
+#define SPI_SHADER_USER_DATA_ES_20__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_20__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_21
+#define SPI_SHADER_USER_DATA_ES_21__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_21__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_22
+#define SPI_SHADER_USER_DATA_ES_22__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_22__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_23
+#define SPI_SHADER_USER_DATA_ES_23__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_23__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_24
+#define SPI_SHADER_USER_DATA_ES_24__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_24__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_25
+#define SPI_SHADER_USER_DATA_ES_25__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_25__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_26
+#define SPI_SHADER_USER_DATA_ES_26__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_26__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_27
+#define SPI_SHADER_USER_DATA_ES_27__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_27__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_28
+#define SPI_SHADER_USER_DATA_ES_28__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_28__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_29
+#define SPI_SHADER_USER_DATA_ES_29__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_29__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_30
+#define SPI_SHADER_USER_DATA_ES_30__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_30__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_31
+#define SPI_SHADER_USER_DATA_ES_31__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_31__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_RSRC4_HS
+#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH_MASK 0x0000007FL
+//SPI_SHADER_USER_DATA_ADDR_LO_HS
+#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ADDR_HI_HS
+#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_LO_LS
+#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_HI_LS
+#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xFFL
+//SPI_SHADER_PGM_RSRC3_HS
+#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x0000003FL
+#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x000003C0L
+#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE_MASK 0x00003C00L
+#define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xFFFF0000L
+//SPI_SHADER_PGM_LO_HS
+#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_HI_HS
+#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xFFL
+//SPI_SHADER_PGM_RSRC1_HS
+#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x1e
+#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003FL
+#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003C0L
+#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000C00L
+#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000FF000L
+#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L
+#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L
+#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x00400000L
+#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L
+#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x08000000L
+#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L
+#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L
+//SPI_SHADER_PGM_RSRC2_HS
+#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0000FF80L
+#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x01FF0000L
+#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0_MASK 0x08000000L
+#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x10000000L
+//SPI_SHADER_USER_DATA_LS_0
+#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_1
+#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_2
+#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_3
+#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_4
+#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_5
+#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_6
+#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_7
+#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_8
+#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_9
+#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_10
+#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_11
+#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_12
+#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_13
+#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_14
+#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_15
+#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_16
+#define SPI_SHADER_USER_DATA_LS_16__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_16__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_17
+#define SPI_SHADER_USER_DATA_LS_17__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_17__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_18
+#define SPI_SHADER_USER_DATA_LS_18__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_18__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_19
+#define SPI_SHADER_USER_DATA_LS_19__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_19__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_20
+#define SPI_SHADER_USER_DATA_LS_20__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_20__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_21
+#define SPI_SHADER_USER_DATA_LS_21__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_21__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_22
+#define SPI_SHADER_USER_DATA_LS_22__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_22__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_23
+#define SPI_SHADER_USER_DATA_LS_23__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_23__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_24
+#define SPI_SHADER_USER_DATA_LS_24__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_24__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_25
+#define SPI_SHADER_USER_DATA_LS_25__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_25__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_26
+#define SPI_SHADER_USER_DATA_LS_26__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_26__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_27
+#define SPI_SHADER_USER_DATA_LS_27__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_27__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_28
+#define SPI_SHADER_USER_DATA_LS_28__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_28__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_29
+#define SPI_SHADER_USER_DATA_LS_29__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_29__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_30
+#define SPI_SHADER_USER_DATA_LS_30__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_30__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_31
+#define SPI_SHADER_USER_DATA_LS_31__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_31__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_0
+#define SPI_SHADER_USER_DATA_COMMON_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_0__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_1
+#define SPI_SHADER_USER_DATA_COMMON_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_1__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_2
+#define SPI_SHADER_USER_DATA_COMMON_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_2__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_3
+#define SPI_SHADER_USER_DATA_COMMON_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_3__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_4
+#define SPI_SHADER_USER_DATA_COMMON_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_4__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_5
+#define SPI_SHADER_USER_DATA_COMMON_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_5__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_6
+#define SPI_SHADER_USER_DATA_COMMON_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_6__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_7
+#define SPI_SHADER_USER_DATA_COMMON_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_7__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_8
+#define SPI_SHADER_USER_DATA_COMMON_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_8__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_9
+#define SPI_SHADER_USER_DATA_COMMON_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_9__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_10
+#define SPI_SHADER_USER_DATA_COMMON_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_10__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_11
+#define SPI_SHADER_USER_DATA_COMMON_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_11__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_12
+#define SPI_SHADER_USER_DATA_COMMON_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_12__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_13
+#define SPI_SHADER_USER_DATA_COMMON_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_13__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_14
+#define SPI_SHADER_USER_DATA_COMMON_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_14__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_15
+#define SPI_SHADER_USER_DATA_COMMON_15__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_15__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_16
+#define SPI_SHADER_USER_DATA_COMMON_16__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_16__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_17
+#define SPI_SHADER_USER_DATA_COMMON_17__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_17__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_18
+#define SPI_SHADER_USER_DATA_COMMON_18__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_18__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_19
+#define SPI_SHADER_USER_DATA_COMMON_19__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_19__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_20
+#define SPI_SHADER_USER_DATA_COMMON_20__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_20__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_21
+#define SPI_SHADER_USER_DATA_COMMON_21__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_21__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_22
+#define SPI_SHADER_USER_DATA_COMMON_22__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_22__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_23
+#define SPI_SHADER_USER_DATA_COMMON_23__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_23__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_24
+#define SPI_SHADER_USER_DATA_COMMON_24__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_24__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_25
+#define SPI_SHADER_USER_DATA_COMMON_25__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_25__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_26
+#define SPI_SHADER_USER_DATA_COMMON_26__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_26__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_27
+#define SPI_SHADER_USER_DATA_COMMON_27__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_27__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_28
+#define SPI_SHADER_USER_DATA_COMMON_28__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_28__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_29
+#define SPI_SHADER_USER_DATA_COMMON_29__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_29__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_30
+#define SPI_SHADER_USER_DATA_COMMON_30__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_30__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_31
+#define SPI_SHADER_USER_DATA_COMMON_31__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_31__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_DISPATCH_INITIATOR
+#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0
+#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1
+#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4
+#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5
+#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6
+#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
+#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb
+#define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT 0xc
+#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe
+#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L
+#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L
+#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L
+#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L
+#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L
+#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L
+#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L
+#define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK 0x00001000L
+#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L
+//COMPUTE_DIM_X
+#define COMPUTE_DIM_X__SIZE__SHIFT 0x0
+#define COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL
+//COMPUTE_DIM_Y
+#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0
+#define COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL
+//COMPUTE_DIM_Z
+#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0
+#define COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL
+//COMPUTE_START_X
+#define COMPUTE_START_X__START__SHIFT 0x0
+#define COMPUTE_START_X__START_MASK 0xFFFFFFFFL
+//COMPUTE_START_Y
+#define COMPUTE_START_Y__START__SHIFT 0x0
+#define COMPUTE_START_Y__START_MASK 0xFFFFFFFFL
+//COMPUTE_START_Z
+#define COMPUTE_START_Z__START__SHIFT 0x0
+#define COMPUTE_START_Z__START_MASK 0xFFFFFFFFL
+//COMPUTE_NUM_THREAD_X
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000FFFFL
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L
+//COMPUTE_NUM_THREAD_Y
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000FFFFL
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L
+//COMPUTE_NUM_THREAD_Z
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L
+//COMPUTE_PIPELINESTAT_ENABLE
+#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0
+#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L
+//COMPUTE_PERFCOUNT_ENABLE
+#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0
+#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L
+//COMPUTE_PGM_LO
+#define COMPUTE_PGM_LO__DATA__SHIFT 0x0
+#define COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_PGM_HI
+#define COMPUTE_PGM_HI__DATA__SHIFT 0x0
+#define COMPUTE_PGM_HI__DATA_MASK 0x000000FFL
+//COMPUTE_DISPATCH_PKT_ADDR_LO
+#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0
+#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_DISPATCH_PKT_ADDR_HI
+#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0
+#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL
+//COMPUTE_DISPATCH_SCRATCH_BASE_LO
+#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0
+#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_DISPATCH_SCRATCH_BASE_HI
+#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0
+#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL
+//COMPUTE_PGM_RSRC1
+#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0
+#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6
+#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
+#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc
+#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14
+#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15
+#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16
+#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17
+#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18
+#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19
+#define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a
+#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL
+#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L
+#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L
+#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L
+#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L
+#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L
+#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x00400000L
+#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L
+#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L
+#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x02000000L
+#define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L
+//COMPUTE_PGM_RSRC2
+#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0
+#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1
+#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6
+#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7
+#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8
+#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9
+#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
+#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb
+#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd
+#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf
+#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18
+#define COMPUTE_PGM_RSRC2__SKIP_USGPR0__SHIFT 0x1f
+#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L
+#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003EL
+#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L
+#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L
+#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L
+#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L
+#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L
+#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L
+#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L
+#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L
+#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L
+#define COMPUTE_PGM_RSRC2__SKIP_USGPR0_MASK 0x80000000L
+//COMPUTE_VMID
+#define COMPUTE_VMID__DATA__SHIFT 0x0
+#define COMPUTE_VMID__DATA_MASK 0x0000000FL
+//COMPUTE_RESOURCE_LIMITS
+#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0
+#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc
+#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10
+#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16
+#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17
+#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18
+#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE__SHIFT 0x1b
+#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL
+#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L
+#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L
+#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L
+#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L
+#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L
+#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE_MASK 0x78000000L
+//COMPUTE_STATIC_THREAD_MGMT_SE0
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000FFFFL
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xFFFF0000L
+//COMPUTE_STATIC_THREAD_MGMT_SE1
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000FFFFL
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xFFFF0000L
+//COMPUTE_TMPRING_SIZE
+#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0
+#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
+#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL
+#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L
+//COMPUTE_STATIC_THREAD_MGMT_SE2
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0x0000FFFFL
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xFFFF0000L
+//COMPUTE_STATIC_THREAD_MGMT_SE3
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0x0000FFFFL
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xFFFF0000L
+//COMPUTE_RESTART_X
+#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0
+#define COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL
+//COMPUTE_RESTART_Y
+#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0
+#define COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL
+//COMPUTE_RESTART_Z
+#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0
+#define COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL
+//COMPUTE_THREAD_TRACE_ENABLE
+#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0
+#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L
+//COMPUTE_MISC_RESERVED
+#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0
+#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2
+#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3
+#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4
+#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5
+#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x00000003L
+#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x00000004L
+#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x00000008L
+#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x00000010L
+#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L
+//COMPUTE_DISPATCH_ID
+#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0
+#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL
+//COMPUTE_THREADGROUP_ID
+#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0
+#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL
+//COMPUTE_RELAUNCH
+#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0
+#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e
+#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f
+#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL
+#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L
+#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L
+//COMPUTE_WAVE_RESTORE_ADDR_LO
+#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0
+#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL
+//COMPUTE_WAVE_RESTORE_ADDR_HI
+#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0
+#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xFFFFL
+//COMPUTE_USER_DATA_0
+#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_1
+#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_2
+#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_3
+#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_4
+#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_5
+#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_6
+#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_7
+#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_8
+#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_9
+#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_10
+#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_11
+#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_12
+#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_13
+#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_14
+#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_15
+#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_NOWHERE
+#define COMPUTE_NOWHERE__DATA__SHIFT 0x0
+#define COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_cppdec
+//CP_DFY_CNTL
+#define CP_DFY_CNTL__POLICY__SHIFT 0x0
+#define CP_DFY_CNTL__MTYPE__SHIFT 0x2
+#define CP_DFY_CNTL__TPI_SDP_SEL__SHIFT 0x1a
+#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c
+#define CP_DFY_CNTL__MODE__SHIFT 0x1d
+#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f
+#define CP_DFY_CNTL__POLICY_MASK 0x00000001L
+#define CP_DFY_CNTL__MTYPE_MASK 0x0000000CL
+#define CP_DFY_CNTL__TPI_SDP_SEL_MASK 0x04000000L
+#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000L
+#define CP_DFY_CNTL__MODE_MASK 0x60000000L
+#define CP_DFY_CNTL__ENABLE_MASK 0x80000000L
+//CP_DFY_STAT
+#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0
+#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10
+#define CP_DFY_STAT__BUSY__SHIFT 0x1f
+#define CP_DFY_STAT__BURST_COUNT_MASK 0x0000FFFFL
+#define CP_DFY_STAT__TAGS_PENDING_MASK 0x07FF0000L
+#define CP_DFY_STAT__BUSY_MASK 0x80000000L
+//CP_DFY_ADDR_HI
+#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL
+//CP_DFY_ADDR_LO
+#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5
+#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xFFFFFFE0L
+//CP_DFY_DATA_0
+#define CP_DFY_DATA_0__DATA__SHIFT 0x0
+#define CP_DFY_DATA_0__DATA_MASK 0xFFFFFFFFL
+//CP_DFY_DATA_1
+#define CP_DFY_DATA_1__DATA__SHIFT 0x0
+#define CP_DFY_DATA_1__DATA_MASK 0xFFFFFFFFL
+//CP_DFY_DATA_2
+#define CP_DFY_DATA_2__DATA__SHIFT 0x0
+#define CP_DFY_DATA_2__DATA_MASK 0xFFFFFFFFL
+//CP_DFY_DATA_3
+#define CP_DFY_DATA_3__DATA__SHIFT 0x0
+#define CP_DFY_DATA_3__DATA_MASK 0xFFFFFFFFL
+//CP_DFY_DATA_4
+#define CP_DFY_DATA_4__DATA__SHIFT 0x0
+#define CP_DFY_DATA_4__DATA_MASK 0xFFFFFFFFL
+//CP_DFY_DATA_5
+#define CP_DFY_DATA_5__DATA__SHIFT 0x0
+#define CP_DFY_DATA_5__DATA_MASK 0xFFFFFFFFL
+//CP_DFY_DATA_6
+#define CP_DFY_DATA_6__DATA__SHIFT 0x0
+#define CP_DFY_DATA_6__DATA_MASK 0xFFFFFFFFL
+//CP_DFY_DATA_7
+#define CP_DFY_DATA_7__DATA__SHIFT 0x0
+#define CP_DFY_DATA_7__DATA_MASK 0xFFFFFFFFL
+//CP_DFY_DATA_8
+#define CP_DFY_DATA_8__DATA__SHIFT 0x0
+#define CP_DFY_DATA_8__DATA_MASK 0xFFFFFFFFL
+//CP_DFY_DATA_9
+#define CP_DFY_DATA_9__DATA__SHIFT 0x0
+#define CP_DFY_DATA_9__DATA_MASK 0xFFFFFFFFL
+//CP_DFY_DATA_10
+#define CP_DFY_DATA_10__DATA__SHIFT 0x0
+#define CP_DFY_DATA_10__DATA_MASK 0xFFFFFFFFL
+//CP_DFY_DATA_11
+#define CP_DFY_DATA_11__DATA__SHIFT 0x0
+#define CP_DFY_DATA_11__DATA_MASK 0xFFFFFFFFL
+//CP_DFY_DATA_12
+#define CP_DFY_DATA_12__DATA__SHIFT 0x0
+#define CP_DFY_DATA_12__DATA_MASK 0xFFFFFFFFL
+//CP_DFY_DATA_13
+#define CP_DFY_DATA_13__DATA__SHIFT 0x0
+#define CP_DFY_DATA_13__DATA_MASK 0xFFFFFFFFL
+//CP_DFY_DATA_14
+#define CP_DFY_DATA_14__DATA__SHIFT 0x0
+#define CP_DFY_DATA_14__DATA_MASK 0xFFFFFFFFL
+//CP_DFY_DATA_15
+#define CP_DFY_DATA_15__DATA__SHIFT 0x0
+#define CP_DFY_DATA_15__DATA_MASK 0xFFFFFFFFL
+//CP_DFY_CMD
+#define CP_DFY_CMD__OFFSET__SHIFT 0x0
+#define CP_DFY_CMD__SIZE__SHIFT 0x10
+#define CP_DFY_CMD__OFFSET_MASK 0x000001FFL
+#define CP_DFY_CMD__SIZE_MASK 0xFFFF0000L
+//CP_EOPQ_WAIT_TIME
+#define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x0
+#define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa
+#define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003FFL
+#define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003FC00L
+//CP_CPC_MGCG_SYNC_CNTL
+#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0
+#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8
+#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL
+#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L
+//CPC_INT_INFO
+#define CPC_INT_INFO__ADDR_HI__SHIFT 0x0
+#define CPC_INT_INFO__TYPE__SHIFT 0x10
+#define CPC_INT_INFO__VMID__SHIFT 0x14
+#define CPC_INT_INFO__QUEUE_ID__SHIFT 0x1c
+#define CPC_INT_INFO__ADDR_HI_MASK 0x0000FFFFL
+#define CPC_INT_INFO__TYPE_MASK 0x00010000L
+#define CPC_INT_INFO__VMID_MASK 0x00F00000L
+#define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L
+//CP_VIRT_STATUS
+#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0
+#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xFFFFFFFFL
+//CPC_INT_ADDR
+#define CPC_INT_ADDR__ADDR__SHIFT 0x0
+#define CPC_INT_ADDR__ADDR_MASK 0xFFFFFFFFL
+//CPC_INT_PASID
+#define CPC_INT_PASID__PASID__SHIFT 0x0
+#define CPC_INT_PASID__PASID_MASK 0x0000FFFFL
+//CP_GFX_ERROR
+#define CP_GFX_ERROR__EDC_ERROR_ID__SHIFT 0x0
+#define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x4
+#define CP_GFX_ERROR__RSVD1_ERROR__SHIFT 0x5
+#define CP_GFX_ERROR__RSVD2_ERROR__SHIFT 0x6
+#define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT 0x7
+#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT 0x8
+#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x9
+#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa
+#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0xb
+#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0xc
+#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0xd
+#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0xe
+#define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0xf
+#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT 0x10
+#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT 0x11
+#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x12
+#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x13
+#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x14
+#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x15
+#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT 0x16
+#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x17
+#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x18
+#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x19
+#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x1a
+#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x1b
+#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT 0x1c
+#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT 0x1d
+#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x1e
+#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT 0x1f
+#define CP_GFX_ERROR__EDC_ERROR_ID_MASK 0x0000000FL
+#define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L
+#define CP_GFX_ERROR__RSVD1_ERROR_MASK 0x00000020L
+#define CP_GFX_ERROR__RSVD2_ERROR_MASK 0x00000040L
+#define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK 0x00000080L
+#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK 0x00000100L
+#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L
+#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L
+#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L
+#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L
+#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L
+#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L
+#define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L
+#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK 0x00010000L
+#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK 0x00020000L
+#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L
+#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L
+#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L
+#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L
+#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK 0x00400000L
+#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L
+#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L
+#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L
+#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L
+#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L
+#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK 0x10000000L
+#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK 0x20000000L
+#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L
+#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK 0x80000000L
+//CPG_UTCL1_CNTL
+#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
+#define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
+#define CPG_UTCL1_CNTL__BYPASS__SHIFT 0x19
+#define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
+#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
+#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
+#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e
+#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
+#define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
+#define CPG_UTCL1_CNTL__BYPASS_MASK 0x02000000L
+#define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
+#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
+#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
+#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L
+//CPC_UTCL1_CNTL
+#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
+#define CPC_UTCL1_CNTL__BYPASS__SHIFT 0x19
+#define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
+#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
+#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
+#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e
+#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
+#define CPC_UTCL1_CNTL__BYPASS_MASK 0x02000000L
+#define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
+#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
+#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
+#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L
+//CPF_UTCL1_CNTL
+#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
+#define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
+#define CPF_UTCL1_CNTL__BYPASS__SHIFT 0x19
+#define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
+#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
+#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
+#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e
+#define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x1f
+#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
+#define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
+#define CPF_UTCL1_CNTL__BYPASS_MASK 0x02000000L
+#define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
+#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
+#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
+#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L
+#define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L
+//CP_AQL_SMM_STATUS
+#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x0
+#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xFFFFFFFFL
+//CP_RB0_BASE
+#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB0_BASE__RB_BASE_MASK 0xFFFFFFFFL
+//CP_RB_BASE
+#define CP_RB_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB_BASE__RB_BASE_MASK 0xFFFFFFFFL
+//CP_RB0_CNTL
+#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11
+#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003FL
+#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003F00L
+#define CP_RB0_CNTL__BUF_SWAP_MASK 0x00060000L
+#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L
+#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
+#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x01000000L
+#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L
+#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
+//CP_RB_CNTL
+#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003FL
+#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003F00L
+#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L
+#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
+#define CP_RB_CNTL__CACHE_POLICY_MASK 0x01000000L
+#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L
+#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
+//CP_RB_RPTR_WR
+#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
+#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL
+//CP_RB0_RPTR_ADDR
+#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
+//CP_RB_RPTR_ADDR
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
+//CP_RB0_RPTR_ADDR_HI
+#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
+//CP_RB_RPTR_ADDR_HI
+#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
+//CP_RB0_BUFSZ_MASK
+#define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x0
+#define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000FFFFFL
+//CP_RB_BUFSZ_MASK
+#define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x0
+#define CP_RB_BUFSZ_MASK__DATA_MASK 0x000FFFFFL
+//CP_RB_WPTR_POLL_ADDR_LO
+#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2
+#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL
+//CP_RB_WPTR_POLL_ADDR_HI
+#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0
+#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL
+//GC_PRIV_MODE
+//CP_INT_CNTL
+#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
+#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12
+#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15
+#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
+#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
+#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
+#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
+#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
+#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
+#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_INT_STATUS
+#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
+#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x10
+#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12
+#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15
+#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
+#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
+#define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L
+#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
+#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L
+#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L
+#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
+#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L
+#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L
+#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L
+#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
+#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
+#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L
+#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L
+#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L
+//CP_DEVICE_ID
+#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000FFL
+//CP_ME0_PIPE_PRIORITY_CNTS
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
+//CP_RING_PRIORITY_CNTS
+#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
+#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
+#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
+#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
+//CP_ME0_PIPE0_PRIORITY
+#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_RING0_PRIORITY
+#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME0_PIPE1_PRIORITY
+#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_RING1_PRIORITY
+#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME0_PIPE2_PRIORITY
+#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_RING2_PRIORITY
+#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_FATAL_ERROR
+#define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x0
+#define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x1
+#define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x2
+#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x3
+#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x4
+#define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L
+#define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L
+#define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L
+#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L
+#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L
+//CP_RB_VMID
+#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
+#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
+#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
+#define CP_RB_VMID__RB0_VMID_MASK 0x0000000FL
+#define CP_RB_VMID__RB1_VMID_MASK 0x00000F00L
+#define CP_RB_VMID__RB2_VMID_MASK 0x000F0000L
+//CP_ME0_PIPE0_VMID
+#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
+#define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000FL
+//CP_ME0_PIPE1_VMID
+#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
+#define CP_ME0_PIPE1_VMID__VMID_MASK 0x0000000FL
+//CP_RB0_WPTR
+#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB0_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_RB_WPTR
+#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_RB0_WPTR_HI
+#define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x0
+#define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_RB_WPTR_HI
+#define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x0
+#define CP_RB_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_RB1_WPTR
+#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB1_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_RB1_WPTR_HI
+#define CP_RB1_WPTR_HI__RB_WPTR__SHIFT 0x0
+#define CP_RB1_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_RB2_WPTR
+#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB2_WPTR__RB_WPTR_MASK 0x000FFFFFL
+//CP_RB_DOORBELL_CONTROL
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L
+//CP_RB_DOORBELL_RANGE_LOWER
+#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
+#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL
+//CP_RB_DOORBELL_RANGE_UPPER
+#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
+#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL
+//CP_MEC_DOORBELL_RANGE_LOWER
+#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
+#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL
+//CP_MEC_DOORBELL_RANGE_UPPER
+#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
+#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL
+//CPG_UTCL1_ERROR
+#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0
+#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L
+//CPC_UTCL1_ERROR
+#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0
+#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L
+//CP_RB1_BASE
+#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB1_BASE__RB_BASE_MASK 0xFFFFFFFFL
+//CP_RB1_CNTL
+#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003FL
+#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003F00L
+#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L
+#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
+#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x01000000L
+#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L
+#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
+//CP_RB1_RPTR_ADDR
+#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
+//CP_RB1_RPTR_ADDR_HI
+#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
+//CP_RB2_BASE
+#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB2_BASE__RB_BASE_MASK 0xFFFFFFFFL
+//CP_RB2_CNTL
+#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003FL
+#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003F00L
+#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L
+#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
+#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x01000000L
+#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L
+#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
+//CP_RB2_RPTR_ADDR
+#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
+//CP_RB2_RPTR_ADDR_HI
+#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
+//CP_RB0_ACTIVE
+#define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x0
+#define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L
+//CP_RB_ACTIVE
+#define CP_RB_ACTIVE__ACTIVE__SHIFT 0x0
+#define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L
+//CP_INT_CNTL_RING0
+#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
+#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12
+#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15
+#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
+#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
+#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
+#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
+#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
+#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
+#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_INT_CNTL_RING1
+#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
+#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12
+#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15
+#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
+#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
+#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
+#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
+#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
+#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
+#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_INT_CNTL_RING2
+#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
+#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12
+#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15
+#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
+#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
+#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
+#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
+#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
+#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
+#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_INT_STATUS_RING0
+#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
+#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x10
+#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12
+#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15
+#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
+#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
+#define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L
+#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
+#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L
+#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L
+#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
+#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L
+#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L
+#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L
+#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
+#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L
+#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
+#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L
+#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L
+#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L
+//CP_INT_STATUS_RING1
+#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
+#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT 0x10
+#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12
+#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15
+#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
+#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
+#define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK 0x00010000L
+#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
+#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x00040000L
+#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L
+#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
+#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x00200000L
+#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L
+#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L
+#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
+#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L
+#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
+#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L
+#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L
+#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L
+//CP_INT_STATUS_RING2
+#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
+#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT 0x10
+#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12
+#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15
+#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
+#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
+#define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK 0x00010000L
+#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
+#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x00040000L
+#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L
+#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
+#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x00200000L
+#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L
+#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L
+#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
+#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L
+#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
+#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L
+#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L
+#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L
+#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
+#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L
+#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L
+#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L
+//CP_PWR_CNTL
+#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0
+#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13
+#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L
+#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L
+//CP_MEM_SLP_CNTL
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
+#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
+#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
+#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
+#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L
+#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L
+#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL
+#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000FF00L
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00FF0000L
+#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L
+//CP_ECC_FIRSTOCCURRENCE
+#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4
+#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8
+#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa
+#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc
+#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
+#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L
+#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000F0L
+#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L
+#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000C00L
+#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x00007000L
+#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000F0000L
+//CP_ECC_FIRSTOCCURRENCE_RING0
+#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xFFFFFFFFL
+//CP_ECC_FIRSTOCCURRENCE_RING1
+#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xFFFFFFFFL
+//CP_ECC_FIRSTOCCURRENCE_RING2
+#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xFFFFFFFFL
+//GB_EDC_MODE
+#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf
+#define GB_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
+#define GB_EDC_MODE__GATE_FUE__SHIFT 0x11
+#define GB_EDC_MODE__DED_MODE__SHIFT 0x14
+#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d
+#define GB_EDC_MODE__BYPASS__SHIFT 0x1f
+#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L
+#define GB_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
+#define GB_EDC_MODE__GATE_FUE_MASK 0x00020000L
+#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L
+#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L
+#define GB_EDC_MODE__BYPASS_MASK 0x80000000L
+//CP_CPF_DEBUG
+//CP_PQ_WPTR_POLL_CNTL
+#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
+#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x1d
+#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
+#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
+#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000FFL
+#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L
+#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L
+#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L
+//CP_PQ_WPTR_POLL_CNTL1
+#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
+#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xFFFFFFFFL
+//CP_ME1_PIPE0_INT_CNTL
+#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME1_PIPE1_INT_CNTL
+#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME1_PIPE2_INT_CNTL
+#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME1_PIPE3_INT_CNTL
+#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME2_PIPE0_INT_CNTL
+#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME2_PIPE1_INT_CNTL
+#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME2_PIPE2_INT_CNTL
+#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME2_PIPE3_INT_CNTL
+#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME1_PIPE0_INT_STATUS
+#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME1_PIPE1_INT_STATUS
+#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME1_PIPE2_INT_STATUS
+#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME1_PIPE3_INT_STATUS
+#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME2_PIPE0_INT_STATUS
+#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME2_PIPE1_INT_STATUS
+#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME2_PIPE2_INT_STATUS
+#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME2_PIPE3_INT_STATUS
+#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME1_INT_STAT_DEBUG
+#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
+#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
+#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
+#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10
+#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
+#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
+#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
+#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
+#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
+#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
+#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
+#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
+#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x00001000L
+#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x00002000L
+#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L
+#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L
+#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L
+#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
+#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L
+#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L
+#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L
+#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L
+#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L
+#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L
+//CP_ME2_INT_STAT_DEBUG
+#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
+#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
+#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
+#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10
+#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
+#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
+#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
+#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
+#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
+#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
+#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
+#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
+#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x00001000L
+#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x00002000L
+#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L
+#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L
+#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L
+#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
+#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L
+#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L
+#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L
+#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L
+#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L
+#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L
+//CC_GC_EDC_CONFIG
+#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
+//CP_ME1_PIPE_PRIORITY_CNTS
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
+//CP_ME1_PIPE0_PRIORITY
+#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME1_PIPE1_PRIORITY
+#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME1_PIPE2_PRIORITY
+#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME1_PIPE3_PRIORITY
+#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME2_PIPE_PRIORITY_CNTS
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
+//CP_ME2_PIPE0_PRIORITY
+#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME2_PIPE1_PRIORITY
+#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME2_PIPE2_PRIORITY
+#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME2_PIPE3_PRIORITY
+#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_CE_PRGRM_CNTR_START
+#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x000007FFL
+//CP_PFP_PRGRM_CNTR_START
+#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x00001FFFL
+//CP_ME_PRGRM_CNTR_START
+#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x00000FFFL
+//CP_MEC1_PRGRM_CNTR_START
+#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL
+//CP_MEC2_PRGRM_CNTR_START
+#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL
+//CP_CE_INTR_ROUTINE_START
+#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x000007FFL
+//CP_PFP_INTR_ROUTINE_START
+#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x00001FFFL
+//CP_ME_INTR_ROUTINE_START
+#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x00000FFFL
+//CP_MEC1_INTR_ROUTINE_START
+#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL
+//CP_MEC2_INTR_ROUTINE_START
+#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL
+//CP_CONTEXT_CNTL
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x00000007L
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x00000070L
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x00070000L
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00700000L
+//CP_MAX_CONTEXT
+#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
+#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L
+//CP_IQ_WAIT_TIME1
+#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
+#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
+#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
+#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
+#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL
+#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L
+#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L
+#define CP_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L
+//CP_IQ_WAIT_TIME2
+#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
+#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
+#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
+#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
+#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL
+#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L
+#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0x00FF0000L
+#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L
+//CP_RB0_BASE_HI
+#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000FFL
+//CP_RB1_BASE_HI
+#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000FFL
+//CP_VMID_RESET
+#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
+#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000FFFFL
+//CPC_INT_CNTL
+#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CPC_INT_STATUS
+#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_VMID_PREEMPT
+#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
+#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10
+#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000FFFFL
+#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000F0000L
+//CPC_INT_CNTX_ID
+#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
+#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL
+//CP_PQ_STATUS
+#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
+#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
+#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L
+#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L
+//CP_CPC_IC_BASE_LO
+#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
+#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L
+//CP_CPC_IC_BASE_HI
+#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
+#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL
+//CP_CPC_IC_BASE_CNTL
+#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0
+#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000FL
+#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x01000000L
+//CP_CPC_IC_OP_CNTL
+#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
+#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
+#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
+#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L
+#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L
+#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L
+//CP_MEC1_F32_INT_DIS
+#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
+#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
+#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
+#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
+#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
+#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
+#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
+#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
+#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
+#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
+#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb
+#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc
+#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd
+#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe
+#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf
+#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L
+#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L
+#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L
+#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L
+#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L
+#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L
+#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L
+#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L
+#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L
+#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L
+#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L
+#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L
+#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L
+#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L
+#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L
+#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L
+//CP_MEC2_F32_INT_DIS
+#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
+#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
+#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
+#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
+#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
+#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
+#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
+#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
+#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
+#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
+#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb
+#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc
+#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd
+#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe
+#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf
+#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L
+#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L
+#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L
+#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L
+#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L
+#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L
+#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L
+#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L
+#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L
+#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L
+#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L
+#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L
+#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L
+#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L
+#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L
+#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L
+//CP_VMID_STATUS
+#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0
+#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10
+#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL
+#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L
+
+
+// addressBlock: gc_cppdec2
+//CP_RB_DOORBELL_CONTROL_SCH_0
+#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN__SHIFT 0x1e
+#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT__SHIFT 0x1f
+#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN_MASK 0x40000000L
+#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT_MASK 0x80000000L
+//CP_RB_DOORBELL_CONTROL_SCH_1
+#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN__SHIFT 0x1e
+#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT__SHIFT 0x1f
+#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN_MASK 0x40000000L
+#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT_MASK 0x80000000L
+//CP_RB_DOORBELL_CONTROL_SCH_2
+#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN__SHIFT 0x1e
+#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT__SHIFT 0x1f
+#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN_MASK 0x40000000L
+#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT_MASK 0x80000000L
+//CP_RB_DOORBELL_CONTROL_SCH_3
+#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN__SHIFT 0x1e
+#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT__SHIFT 0x1f
+#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN_MASK 0x40000000L
+#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT_MASK 0x80000000L
+//CP_RB_DOORBELL_CONTROL_SCH_4
+#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN__SHIFT 0x1e
+#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT__SHIFT 0x1f
+#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN_MASK 0x40000000L
+#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT_MASK 0x80000000L
+//CP_RB_DOORBELL_CONTROL_SCH_5
+#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN__SHIFT 0x1e
+#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT__SHIFT 0x1f
+#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN_MASK 0x40000000L
+#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT_MASK 0x80000000L
+//CP_RB_DOORBELL_CONTROL_SCH_6
+#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN__SHIFT 0x1e
+#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT__SHIFT 0x1f
+#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN_MASK 0x40000000L
+#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT_MASK 0x80000000L
+//CP_RB_DOORBELL_CONTROL_SCH_7
+#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN__SHIFT 0x1e
+#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT__SHIFT 0x1f
+#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN_MASK 0x40000000L
+#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT_MASK 0x80000000L
+//CP_RB_DOORBELL_CLEAR
+#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x0
+#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x8
+#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x9
+#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa
+#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0xb
+#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0xc
+#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0xd
+#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L
+#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L
+#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L
+#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L
+#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L
+#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L
+#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L
+//CP_GFX_MQD_CONTROL
+#define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x0
+#define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17
+#define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
+#define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000FL
+#define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L
+#define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L
+//CP_GFX_MQD_BASE_ADDR
+#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
+#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL
+//CP_GFX_MQD_BASE_ADDR_HI
+#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
+#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL
+//CP_RB_STATUS
+#define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x0
+#define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x1
+#define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L
+#define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L
+//CPG_UTCL1_STATUS
+#define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
+#define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
+#define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
+#define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+#define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
+#define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
+#define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
+//CPC_UTCL1_STATUS
+#define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
+#define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
+#define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
+#define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+#define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
+#define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
+#define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
+//CPF_UTCL1_STATUS
+#define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
+#define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
+#define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
+#define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+#define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
+#define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
+#define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
+//CP_SD_CNTL
+#define CP_SD_CNTL__CPF_EN__SHIFT 0x0
+#define CP_SD_CNTL__CPG_EN__SHIFT 0x1
+#define CP_SD_CNTL__CPC_EN__SHIFT 0x2
+#define CP_SD_CNTL__RLC_EN__SHIFT 0x3
+#define CP_SD_CNTL__SPI_EN__SHIFT 0x4
+#define CP_SD_CNTL__WD_EN__SHIFT 0x5
+#define CP_SD_CNTL__IA_EN__SHIFT 0x6
+#define CP_SD_CNTL__PA_EN__SHIFT 0x7
+#define CP_SD_CNTL__RMI_EN__SHIFT 0x8
+#define CP_SD_CNTL__EA_EN__SHIFT 0x9
+#define CP_SD_CNTL__CPF_EN_MASK 0x00000001L
+#define CP_SD_CNTL__CPG_EN_MASK 0x00000002L
+#define CP_SD_CNTL__CPC_EN_MASK 0x00000004L
+#define CP_SD_CNTL__RLC_EN_MASK 0x00000008L
+#define CP_SD_CNTL__SPI_EN_MASK 0x00000010L
+#define CP_SD_CNTL__WD_EN_MASK 0x00000020L
+#define CP_SD_CNTL__IA_EN_MASK 0x00000040L
+#define CP_SD_CNTL__PA_EN_MASK 0x00000080L
+#define CP_SD_CNTL__RMI_EN_MASK 0x00000100L
+#define CP_SD_CNTL__EA_EN_MASK 0x00000200L
+//CP_SOFT_RESET_CNTL
+#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x0
+#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x1
+#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x2
+#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x3
+#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x4
+#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x5
+#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x6
+#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L
+#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L
+#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L
+#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L
+#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L
+#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L
+#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L
+//CP_CPC_GFX_CNTL
+#define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x0
+#define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x3
+#define CP_CPC_GFX_CNTL__MEID__SHIFT 0x5
+#define CP_CPC_GFX_CNTL__VALID__SHIFT 0x7
+#define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L
+#define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L
+#define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L
+#define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L
+
+
+// addressBlock: gc_spipdec
+//SPI_ARB_PRIORITY
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9
+#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc
+#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe
+#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10
+#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001C0L
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000E00L
+#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L
+#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000C000L
+#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L
+#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000C0000L
+//SPI_ARB_CYCLES_0
+#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0
+#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10
+#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000FFFFL
+#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xFFFF0000L
+//SPI_ARB_CYCLES_1
+#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0
+#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10
+#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000FFFFL
+#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xFFFF0000L
+//SPI_CDBG_SYS_GFX
+#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0
+#define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1
+#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2
+#define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3
+#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4
+#define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5
+#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6
+#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x0001L
+#define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x0002L
+#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x0004L
+#define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x0008L
+#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x0010L
+#define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x0020L
+#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x0040L
+//SPI_CDBG_SYS_HP3D
+#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0
+#define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1
+#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2
+#define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3
+#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4
+#define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5
+#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x0001L
+#define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x0002L
+#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x0004L
+#define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x0008L
+#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x0010L
+#define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x0020L
+//SPI_CDBG_SYS_CS0
+#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0
+#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8
+#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10
+#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18
+#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0x000000FFL
+#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0x0000FF00L
+#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0x00FF0000L
+#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xFF000000L
+//SPI_CDBG_SYS_CS1
+#define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0
+#define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8
+#define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10
+#define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18
+#define SPI_CDBG_SYS_CS1__PIPE0_MASK 0x000000FFL
+#define SPI_CDBG_SYS_CS1__PIPE1_MASK 0x0000FF00L
+#define SPI_CDBG_SYS_CS1__PIPE2_MASK 0x00FF0000L
+#define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xFF000000L
+//SPI_WCL_PIPE_PERCENT_GFX
+#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7
+#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc
+#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11
+#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16
+#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007FL
+#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0x00000F80L
+#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001F000L
+#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x003E0000L
+#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07C00000L
+//SPI_WCL_PIPE_PERCENT_HP3D
+#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc
+#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16
+#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007FL
+#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001F000L
+#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07C00000L
+//SPI_WCL_PIPE_PERCENT_CS0
+#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7FL
+//SPI_WCL_PIPE_PERCENT_CS1
+#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7FL
+//SPI_WCL_PIPE_PERCENT_CS2
+#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7FL
+//SPI_WCL_PIPE_PERCENT_CS3
+#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7FL
+//SPI_WCL_PIPE_PERCENT_CS4
+#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7FL
+//SPI_WCL_PIPE_PERCENT_CS5
+#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7FL
+//SPI_WCL_PIPE_PERCENT_CS6
+#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7FL
+//SPI_WCL_PIPE_PERCENT_CS7
+#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7FL
+//SPI_GDBG_WAVE_CNTL
+#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0
+#define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1
+#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x00000001L
+#define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x0001FFFEL
+//SPI_GDBG_TRAP_CONFIG
+#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0
+#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2
+#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4
+#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7
+#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8
+#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9
+#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf
+#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10
+#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x00000003L
+#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0x0000000CL
+#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x00000070L
+#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x00000080L
+#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x00000100L
+#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x00000200L
+#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x00008000L
+#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xFFFF0000L
+//SPI_GDBG_TRAP_MASK
+#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0
+#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9
+#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x01FFL
+#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x0200L
+//SPI_GDBG_WAVE_CNTL2
+#define SPI_GDBG_WAVE_CNTL2__VMID_MASK__SHIFT 0x0
+#define SPI_GDBG_WAVE_CNTL2__MODE__SHIFT 0x10
+#define SPI_GDBG_WAVE_CNTL2__VMID_MASK_MASK 0x0000FFFFL
+#define SPI_GDBG_WAVE_CNTL2__MODE_MASK 0x00030000L
+//SPI_GDBG_WAVE_CNTL3
+#define SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT 0x0
+#define SPI_GDBG_WAVE_CNTL3__STALL_VS__SHIFT 0x1
+#define SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT 0x2
+#define SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT 0x3
+#define SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT 0x4
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT 0x5
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT 0x6
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT 0x7
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT 0x8
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT 0x9
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT 0xa
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT 0xb
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT 0xc
+#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT 0xd
+#define SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT 0x1c
+#define SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK 0x00000001L
+#define SPI_GDBG_WAVE_CNTL3__STALL_VS_MASK 0x00000002L
+#define SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK 0x00000004L
+#define SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK 0x00000008L
+#define SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK 0x00000010L
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK 0x00000020L
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK 0x00000040L
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK 0x00000080L
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK 0x00000100L
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK 0x00000200L
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK 0x00000400L
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK 0x00000800L
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK 0x00001000L
+#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK 0x0FFFE000L
+#define SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK 0x10000000L
+//SPI_GDBG_TRAP_DATA0
+#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0
+#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xFFFFFFFFL
+//SPI_GDBG_TRAP_DATA1
+#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0
+#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xFFFFFFFFL
+//SPI_RESET_DEBUG
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x01L
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x02L
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x04L
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x08L
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x10L
+//SPI_COMPUTE_QUEUE_RESET
+#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0
+#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L
+//SPI_RESOURCE_RESERVE_CU_0
+#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_1
+#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_2
+#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_3
+#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_4
+#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_5
+#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_6
+#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_7
+#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_8
+#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_9
+#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_EN_CU_0
+#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_1
+#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_2
+#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_3
+#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_4
+#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_5
+#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_6
+#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_7
+#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_8
+#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_9
+#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_CU_10
+#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_11
+#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_EN_CU_10
+#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_11
+#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_CU_12
+#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_13
+#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_14
+#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_15
+#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_EN_CU_12
+#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_13
+#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_14
+#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_15
+#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_COMPUTE_WF_CTX_SAVE
+#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0
+#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1
+#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2
+#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e
+#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f
+#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L
+#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x00000002L
+#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L
+#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000L
+#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L
+//SPI_ARB_CNTL_0
+#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x0
+#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x4
+#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x8
+#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000FL
+#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000F0L
+#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000F00L
+
+
+// addressBlock: gc_cpphqddec
+//CP_HQD_GFX_CONTROL
+#define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x0
+#define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x4
+#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0xf
+#define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000FL
+#define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007FF0L
+#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L
+//CP_HQD_GFX_STATUS
+#define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x0
+#define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000FFFFL
+//CP_HPD_ROQ_OFFSETS
+#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0
+#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8
+#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
+#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L
+#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L
+#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x003F0000L
+//CP_HPD_STATUS0
+#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0
+#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5
+#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8
+#define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x10
+#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x11
+#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x12
+#define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14
+#define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f
+#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL
+#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L
+#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L
+#define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L
+#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L
+#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L
+#define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L
+#define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L
+//CP_HPD_UTCL1_CNTL
+#define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x0
+#define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000FL
+//CP_HPD_UTCL1_ERROR
+#define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x0
+#define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x10
+#define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x14
+#define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x0000FFFFL
+#define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x00010000L
+#define CP_HPD_UTCL1_ERROR__VMID_MASK 0x00F00000L
+//CP_HPD_UTCL1_ERROR_ADDR
+#define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0xc
+#define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xFFFFF000L
+//CP_MQD_BASE_ADDR
+#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
+#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL
+//CP_MQD_BASE_ADDR_HI
+#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
+#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL
+//CP_HQD_ACTIVE
+#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0
+#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1
+#define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L
+#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L
+//CP_HQD_VMID
+#define CP_HQD_VMID__VMID__SHIFT 0x0
+#define CP_HQD_VMID__IB_VMID__SHIFT 0x8
+#define CP_HQD_VMID__VQID__SHIFT 0x10
+#define CP_HQD_VMID__VMID_MASK 0x0000000FL
+#define CP_HQD_VMID__IB_VMID_MASK 0x00000F00L
+#define CP_HQD_VMID__VQID_MASK 0x03FF0000L
+//CP_HQD_PERSISTENT_STATE
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8
+#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x15
+#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16
+#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x17
+#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x18
+#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x19
+#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x1a
+#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x1b
+#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c
+#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d
+#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e
+#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003FF00L
+#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L
+#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L
+#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L
+#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L
+#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L
+#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L
+#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L
+#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L
+#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L
+#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L
+#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L
+//CP_HQD_PIPE_PRIORITY
+#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0
+#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L
+//CP_HQD_QUEUE_PRIORITY
+#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0
+#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL
+//CP_HQD_QUANTUM
+#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0
+#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4
+#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8
+#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f
+#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L
+#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L
+#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003F00L
+#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L
+//CP_HQD_PQ_BASE
+#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0
+#define CP_HQD_PQ_BASE__ADDR_MASK 0xFFFFFFFFL
+//CP_HQD_PQ_BASE_HI
+#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0
+#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x000000FFL
+//CP_HQD_PQ_RPTR
+#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0
+#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xFFFFFFFFL
+//CP_HQD_PQ_RPTR_REPORT_ADDR
+#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2
+#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xFFFFFFFCL
+//CP_HQD_PQ_RPTR_REPORT_ADDR_HI
+#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0
+#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x0000FFFFL
+//CP_HQD_PQ_WPTR_POLL_ADDR
+#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x3
+#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xFFFFFFF8L
+//CP_HQD_PQ_WPTR_POLL_ADDR_HI
+#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0
+#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL
+//CP_HQD_PQ_DOORBELL_CONTROL
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L
+//CP_HQD_PQ_CONTROL
+#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0
+#define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x6
+#define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x7
+#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8
+#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0xe
+#define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0xf
+#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT 0x10
+#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11
+#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14
+#define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x17
+#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19
+#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b
+#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c
+#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d
+#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
+#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f
+#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL
+#define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L
+#define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L
+#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L
+#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L
+#define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L
+#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN_MASK 0x00010000L
+#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00060000L
+#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L
+#define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L
+#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x01000000L
+#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x06000000L
+#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L
+#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L
+#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000L
+#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L
+#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L
+//CP_HQD_IB_BASE_ADDR
+#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2
+#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xFFFFFFFCL
+//CP_HQD_IB_BASE_ADDR_HI
+#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0
+#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x0000FFFFL
+//CP_HQD_IB_RPTR
+#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0
+#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000FFFFFL
+//CP_HQD_IB_CONTROL
+#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0
+#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14
+#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x17
+#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f
+#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000FFFFFL
+#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L
+#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L
+#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x01000000L
+#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L
+//CP_HQD_IQ_TIMER
+#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0
+#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8
+#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb
+#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc
+#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe
+#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10
+#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16
+#define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x17
+#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x19
+#define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c
+#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d
+#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e
+#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f
+#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL
+#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L
+#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L
+#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L
+#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L
+#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003F0000L
+#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L
+#define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L
+#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x01000000L
+#define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x02000000L
+#define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L
+#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L
+#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L
+#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L
+//CP_HQD_IQ_RPTR
+#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0
+#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003FL
+//CP_HQD_DEQUEUE_REQUEST
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000007L
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L
+//CP_HQD_DMA_OFFLOAD
+#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
+#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L
+//CP_HQD_OFFLOAD
+#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
+#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1
+#define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2
+#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3
+#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4
+#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5
+#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L
+#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L
+#define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L
+#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L
+#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L
+#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L
+//CP_HQD_SEMA_CMD
+#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0
+#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1
+#define CP_HQD_SEMA_CMD__RETRY_MASK 0x00000001L
+#define CP_HQD_SEMA_CMD__RESULT_MASK 0x00000006L
+//CP_HQD_MSG_TYPE
+#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0
+#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4
+#define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L
+#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L
+//CP_HQD_ATOMIC0_PREOP_LO
+#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_HQD_ATOMIC0_PREOP_HI
+#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_HQD_ATOMIC1_PREOP_LO
+#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_HQD_ATOMIC1_PREOP_HI
+#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_HQD_HQ_SCHEDULER0
+#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0
+#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xFFFFFFFFL
+//CP_HQD_HQ_STATUS0
+#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0
+#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2
+#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4
+#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7
+#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8
+#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9
+#define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT 0xa
+#define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e
+#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x1f
+#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000003L
+#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0x0000000CL
+#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x00000070L
+#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L
+#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L
+#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x00000200L
+#define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK 0x3FFFFC00L
+#define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L
+#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L
+//CP_HQD_HQ_CONTROL0
+#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0
+#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xFFFFFFFFL
+//CP_HQD_HQ_SCHEDULER1
+#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0
+#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xFFFFFFFFL
+//CP_MQD_CONTROL
+#define CP_MQD_CONTROL__VMID__SHIFT 0x0
+#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8
+#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc
+#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd
+#define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17
+#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
+#define CP_MQD_CONTROL__VMID_MASK 0x0000000FL
+#define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L
+#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L
+#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L
+#define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L
+#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L
+//CP_HQD_HQ_STATUS1
+#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0
+#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xFFFFFFFFL
+//CP_HQD_HQ_CONTROL1
+#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0
+#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xFFFFFFFFL
+//CP_HQD_EOP_BASE_ADDR
+#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//CP_HQD_EOP_BASE_ADDR_HI
+#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
+#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x000000FFL
+//CP_HQD_EOP_CONTROL
+#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0
+#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8
+#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc
+#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd
+#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe
+#define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x15
+#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x16
+#define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x17
+#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d
+#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f
+#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003FL
+#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L
+#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L
+#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L
+#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L
+#define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L
+#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L
+#define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L
+#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x01000000L
+#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000L
+#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000L
+//CP_HQD_EOP_RPTR
+#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0
+#define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x1c
+#define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x1d
+#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e
+#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f
+#define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001FFFL
+#define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L
+#define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L
+#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L
+#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L
+//CP_HQD_EOP_WPTR
+#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0
+#define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0xf
+#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10
+#define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001FFFL
+#define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L
+#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1FFF0000L
+//CP_HQD_EOP_EVENTS
+#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0
+#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10
+#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000FFFL
+#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L
+//CP_HQD_CTX_SAVE_BASE_ADDR_LO
+#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc
+#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L
+//CP_HQD_CTX_SAVE_BASE_ADDR_HI
+#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_HQD_CTX_SAVE_CONTROL
+#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3
+#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17
+#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000008L
+#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L
+//CP_HQD_CNTL_STACK_OFFSET
+#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2
+#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x00007FFCL
+//CP_HQD_CNTL_STACK_SIZE
+#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc
+#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x00007000L
+//CP_HQD_WG_STATE_OFFSET
+#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2
+#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x01FFFFFCL
+//CP_HQD_CTX_SAVE_SIZE
+#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc
+#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x01FFF000L
+//CP_HQD_GDS_RESOURCE_STATE
+#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0
+#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1
+#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4
+#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc
+#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L
+#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L
+#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003F0L
+#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003F000L
+//CP_HQD_ERROR
+#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0
+#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4
+#define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x5
+#define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x8
+#define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x9
+#define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa
+#define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0xb
+#define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0xc
+#define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0xd
+#define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT 0xe
+#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0xf
+#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x10
+#define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x11
+#define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x12
+#define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x13
+#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0x0000000FL
+#define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L
+#define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L
+#define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L
+#define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L
+#define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L
+#define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L
+#define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L
+#define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L
+#define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK 0x00004000L
+#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L
+#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L
+#define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L
+#define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L
+#define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L
+//CP_HQD_EOP_WPTR_MEM
+#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0
+#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001FFFL
+//CP_HQD_AQL_CONTROL
+#define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x0
+#define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0xf
+#define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x10
+#define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x1f
+#define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007FFFL
+#define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L
+#define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7FFF0000L
+#define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L
+//CP_HQD_PQ_WPTR_LO
+#define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x0
+#define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xFFFFFFFFL
+//CP_HQD_PQ_WPTR_HI
+#define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x0
+#define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_didtdec
+//DIDT_IND_INDEX
+#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0
+#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xFFFFFFFFL
+//DIDT_IND_DATA
+#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0
+#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_gccacdec
+//GC_CAC_CTRL_1
+#define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0
+#define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x18
+#define GC_CAC_CTRL_1__CAC_WINDOW_MASK 0x00FFFFFFL
+#define GC_CAC_CTRL_1__TDP_WINDOW_MASK 0xFF000000L
+//GC_CAC_CTRL_2
+#define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0
+#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT 0x1
+#define GC_CAC_CTRL_2__UNUSED_0__SHIFT 0x2
+#define GC_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L
+#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK 0x00000002L
+#define GC_CAC_CTRL_2__UNUSED_0_MASK 0xFFFFFFFCL
+//GC_CAC_CGTT_CLK_CTRL
+#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
+#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
+//GC_CAC_AGGR_LOWER
+#define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT 0x0
+#define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_AGGR_UPPER
+#define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT 0x0
+#define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK 0xFFFFFFFFL
+//GC_CAC_SOFT_CTRL
+#define GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT 0x0
+#define GC_CAC_SOFT_CTRL__UNUSED__SHIFT 0x1
+#define GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK 0x00000001L
+#define GC_CAC_SOFT_CTRL__UNUSED_MASK 0xFFFFFFFEL
+//GC_DIDT_CTRL0
+#define GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT 0x1
+#define GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT 0x3
+#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
+#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x5
+#define GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
+#define GC_DIDT_CTRL0__PHASE_OFFSET_MASK 0x00000006L
+#define GC_DIDT_CTRL0__DIDT_SW_RST_MASK 0x00000008L
+#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
+#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001E0L
+//GC_DIDT_CTRL1
+#define GC_DIDT_CTRL1__MIN_POWER__SHIFT 0x0
+#define GC_DIDT_CTRL1__MAX_POWER__SHIFT 0x10
+#define GC_DIDT_CTRL1__MIN_POWER_MASK 0x0000FFFFL
+#define GC_DIDT_CTRL1__MAX_POWER_MASK 0xFFFF0000L
+//GC_DIDT_CTRL2
+#define GC_DIDT_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define GC_DIDT_CTRL2__UNUSED_0__SHIFT 0xe
+#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define GC_DIDT_CTRL2__UNUSED_1__SHIFT 0x1a
+#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define GC_DIDT_CTRL2__UNUSED_2__SHIFT 0x1f
+#define GC_DIDT_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
+#define GC_DIDT_CTRL2__UNUSED_0_MASK 0x0000C000L
+#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
+#define GC_DIDT_CTRL2__UNUSED_1_MASK 0x04000000L
+#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
+#define GC_DIDT_CTRL2__UNUSED_2_MASK 0x80000000L
+//GC_DIDT_WEIGHT
+#define GC_DIDT_WEIGHT__SQ_WEIGHT__SHIFT 0x0
+#define GC_DIDT_WEIGHT__DB_WEIGHT__SHIFT 0x8
+#define GC_DIDT_WEIGHT__TD_WEIGHT__SHIFT 0x10
+#define GC_DIDT_WEIGHT__TCP_WEIGHT__SHIFT 0x18
+#define GC_DIDT_WEIGHT__SQ_WEIGHT_MASK 0x000000FFL
+#define GC_DIDT_WEIGHT__DB_WEIGHT_MASK 0x0000FF00L
+#define GC_DIDT_WEIGHT__TD_WEIGHT_MASK 0x00FF0000L
+#define GC_DIDT_WEIGHT__TCP_WEIGHT_MASK 0xFF000000L
+//GC_DIDT_WEIGHT_1
+#define GC_DIDT_WEIGHT_1__DBR_WEIGHT__SHIFT 0x0
+#define GC_DIDT_WEIGHT_1__DBR_WEIGHT_MASK 0x000000FFL
+//GC_EDC_CTRL
+#define GC_EDC_CTRL__EDC_EN__SHIFT 0x0
+#define GC_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
+#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
+#define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
+#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x9
+#define GC_EDC_CTRL__UNUSED_0__SHIFT 0xa
+#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L
+#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
+#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
+#define GC_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
+#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L
+#define GC_EDC_CTRL__UNUSED_0_MASK 0xFFFFFC00L
+//GC_EDC_THRESHOLD
+#define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
+#define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
+//GC_EDC_STATUS
+#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x0
+#define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA__SHIFT 0x3
+#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x00000007L
+#define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA_MASK 0x03FFFFF8L
+//GC_EDC_OVERFLOW
+#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
+#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
+#define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW__SHIFT 0x11
+#define GC_EDC_OVERFLOW__PSM_COUNTER__SHIFT 0x12
+#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
+#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
+#define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW_MASK 0x00020000L
+#define GC_EDC_OVERFLOW__PSM_COUNTER_MASK 0xFFFC0000L
+//GC_EDC_ROLLING_POWER_DELTA
+#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
+#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
+//GC_DIDT_DROOP_CTRL
+#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT 0x0
+#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT 0x1
+#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT 0xf
+#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT 0x13
+#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT 0x1f
+#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK 0x00000001L
+#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK 0x00007FFEL
+#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK 0x00078000L
+#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK 0x00080000L
+#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK 0x80000000L
+//GC_EDC_DROOP_CTRL
+#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT 0x0
+#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT 0x1
+#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT 0xf
+#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT 0x14
+#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT 0x15
+#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK 0x00000001L
+#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK 0x00007FFEL
+#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK 0x000F8000L
+#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK 0x00100000L
+#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK 0x00200000L
+//GC_CAC_IND_INDEX
+#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT 0x0
+#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK 0xFFFFFFFFL
+//GC_CAC_IND_DATA
+#define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT 0x0
+#define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK 0xFFFFFFFFL
+//SE_CAC_CGTT_CLK_CTRL
+#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
+#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
+//SE_CAC_IND_INDEX
+#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT 0x0
+#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK 0xFFFFFFFFL
+//SE_CAC_IND_DATA
+#define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT 0x0
+#define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_tcpdec
+//TCP_WATCH0_ADDR_H
+#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL
+//TCP_WATCH0_ADDR_L
+#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6
+#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFFC0L
+//TCP_WATCH0_CNTL
+#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH0_CNTL__ATC__SHIFT 0x1c
+#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f
+#define TCP_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL
+#define TCP_WATCH0_CNTL__VMID_MASK 0x0F000000L
+#define TCP_WATCH0_CNTL__ATC_MASK 0x10000000L
+#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L
+#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L
+//TCP_WATCH1_ADDR_H
+#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL
+//TCP_WATCH1_ADDR_L
+#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6
+#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFFC0L
+//TCP_WATCH1_CNTL
+#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH1_CNTL__ATC__SHIFT 0x1c
+#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f
+#define TCP_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL
+#define TCP_WATCH1_CNTL__VMID_MASK 0x0F000000L
+#define TCP_WATCH1_CNTL__ATC_MASK 0x10000000L
+#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L
+#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L
+//TCP_WATCH2_ADDR_H
+#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL
+//TCP_WATCH2_ADDR_L
+#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6
+#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFFC0L
+//TCP_WATCH2_CNTL
+#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH2_CNTL__ATC__SHIFT 0x1c
+#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f
+#define TCP_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL
+#define TCP_WATCH2_CNTL__VMID_MASK 0x0F000000L
+#define TCP_WATCH2_CNTL__ATC_MASK 0x10000000L
+#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L
+#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L
+//TCP_WATCH3_ADDR_H
+#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL
+//TCP_WATCH3_ADDR_L
+#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6
+#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFFC0L
+//TCP_WATCH3_CNTL
+#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH3_CNTL__ATC__SHIFT 0x1c
+#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f
+#define TCP_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL
+#define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L
+#define TCP_WATCH3_CNTL__ATC_MASK 0x10000000L
+#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L
+#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L
+//TCP_GATCL1_CNTL
+#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19
+#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a
+#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b
+#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x02000000L
+#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x04000000L
+#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x08000000L
+#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
+#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
+//TCP_ATC_EDC_GATCL1_CNT
+#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0
+#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0x000000FFL
+//TCP_GATCL1_DSM_CNTL
+#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0
+#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1
+#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2
+#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x00000001L
+#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x00000002L
+#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x00000004L
+//TCP_CNTL2
+#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0
+#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0x000000FFL
+//TCP_UTCL1_CNTL1
+#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
+#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1
+#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
+#define TCP_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
+#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
+#define TCP_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
+#define TCP_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
+#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
+#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
+#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
+#define TCP_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
+#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
+#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L
+#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
+#define TCP_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
+#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
+#define TCP_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
+#define TCP_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
+#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
+#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
+#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
+#define TCP_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
+#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
+#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
+//TCP_UTCL1_CNTL2
+#define TCP_UTCL1_CNTL2__SPARE__SHIFT 0x0
+#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
+#define TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT 0xa
+#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
+#define TCP_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
+#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
+#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
+#define TCP_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
+#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
+#define TCP_UTCL1_CNTL2__ANY_LINE_VALID_MASK 0x00000400L
+#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
+#define TCP_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
+#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
+#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
+//TCP_UTCL1_STATUS
+#define TCP_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define TCP_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define TCP_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define TCP_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define TCP_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define TCP_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+//TCP_PERFCOUNTER_FILTER
+#define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0
+#define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1
+#define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x2
+#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x5
+#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0xb
+#define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0xf
+#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x14
+#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x16
+#define TCP_PERFCOUNTER_FILTER__GLC__SHIFT 0x19
+#define TCP_PERFCOUNTER_FILTER__SLC__SHIFT 0x1a
+#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0x1b
+#define TCP_PERFCOUNTER_FILTER__ADDR_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L
+#define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L
+#define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001CL
+#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x000007E0L
+#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x00007800L
+#define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x000F8000L
+#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00300000L
+#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x01C00000L
+#define TCP_PERFCOUNTER_FILTER__GLC_MASK 0x02000000L
+#define TCP_PERFCOUNTER_FILTER__SLC_MASK 0x04000000L
+#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x08000000L
+#define TCP_PERFCOUNTER_FILTER__ADDR_MODE_MASK 0x70000000L
+//TCP_PERFCOUNTER_FILTER_EN
+#define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x0
+#define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x1
+#define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x2
+#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x3
+#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x4
+#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x5
+#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x6
+#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x7
+#define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0x8
+#define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT 0x9
+#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xa
+#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE__SHIFT 0xb
+#define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L
+#define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L
+#define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L
+#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L
+#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L
+#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L
+#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L
+#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L
+#define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK 0x00000100L
+#define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK 0x00000200L
+#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000400L
+#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE_MASK 0x00000800L
+
+
+// addressBlock: gc_gdspdec
+//GDS_VMID0_BASE
+#define GDS_VMID0_BASE__BASE__SHIFT 0x0
+#define GDS_VMID0_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID0_SIZE
+#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID0_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID1_BASE
+#define GDS_VMID1_BASE__BASE__SHIFT 0x0
+#define GDS_VMID1_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID1_SIZE
+#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID1_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID2_BASE
+#define GDS_VMID2_BASE__BASE__SHIFT 0x0
+#define GDS_VMID2_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID2_SIZE
+#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID2_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID3_BASE
+#define GDS_VMID3_BASE__BASE__SHIFT 0x0
+#define GDS_VMID3_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID3_SIZE
+#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID3_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID4_BASE
+#define GDS_VMID4_BASE__BASE__SHIFT 0x0
+#define GDS_VMID4_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID4_SIZE
+#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID4_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID5_BASE
+#define GDS_VMID5_BASE__BASE__SHIFT 0x0
+#define GDS_VMID5_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID5_SIZE
+#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID5_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID6_BASE
+#define GDS_VMID6_BASE__BASE__SHIFT 0x0
+#define GDS_VMID6_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID6_SIZE
+#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID6_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID7_BASE
+#define GDS_VMID7_BASE__BASE__SHIFT 0x0
+#define GDS_VMID7_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID7_SIZE
+#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID7_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID8_BASE
+#define GDS_VMID8_BASE__BASE__SHIFT 0x0
+#define GDS_VMID8_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID8_SIZE
+#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID8_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID9_BASE
+#define GDS_VMID9_BASE__BASE__SHIFT 0x0
+#define GDS_VMID9_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID9_SIZE
+#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID9_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID10_BASE
+#define GDS_VMID10_BASE__BASE__SHIFT 0x0
+#define GDS_VMID10_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID10_SIZE
+#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID10_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID11_BASE
+#define GDS_VMID11_BASE__BASE__SHIFT 0x0
+#define GDS_VMID11_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID11_SIZE
+#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID11_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID12_BASE
+#define GDS_VMID12_BASE__BASE__SHIFT 0x0
+#define GDS_VMID12_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID12_SIZE
+#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID12_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID13_BASE
+#define GDS_VMID13_BASE__BASE__SHIFT 0x0
+#define GDS_VMID13_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID13_SIZE
+#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID13_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID14_BASE
+#define GDS_VMID14_BASE__BASE__SHIFT 0x0
+#define GDS_VMID14_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID14_SIZE
+#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID14_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID15_BASE
+#define GDS_VMID15_BASE__BASE__SHIFT 0x0
+#define GDS_VMID15_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID15_SIZE
+#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID15_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_GWS_VMID0
+#define GDS_GWS_VMID0__BASE__SHIFT 0x0
+#define GDS_GWS_VMID0__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID0__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID0__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID1
+#define GDS_GWS_VMID1__BASE__SHIFT 0x0
+#define GDS_GWS_VMID1__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID1__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID1__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID2
+#define GDS_GWS_VMID2__BASE__SHIFT 0x0
+#define GDS_GWS_VMID2__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID2__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID2__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID3
+#define GDS_GWS_VMID3__BASE__SHIFT 0x0
+#define GDS_GWS_VMID3__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID3__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID3__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID4
+#define GDS_GWS_VMID4__BASE__SHIFT 0x0
+#define GDS_GWS_VMID4__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID4__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID4__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID5
+#define GDS_GWS_VMID5__BASE__SHIFT 0x0
+#define GDS_GWS_VMID5__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID5__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID5__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID6
+#define GDS_GWS_VMID6__BASE__SHIFT 0x0
+#define GDS_GWS_VMID6__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID6__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID6__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID7
+#define GDS_GWS_VMID7__BASE__SHIFT 0x0
+#define GDS_GWS_VMID7__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID7__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID7__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID8
+#define GDS_GWS_VMID8__BASE__SHIFT 0x0
+#define GDS_GWS_VMID8__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID8__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID8__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID9
+#define GDS_GWS_VMID9__BASE__SHIFT 0x0
+#define GDS_GWS_VMID9__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID9__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID9__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID10
+#define GDS_GWS_VMID10__BASE__SHIFT 0x0
+#define GDS_GWS_VMID10__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID10__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID10__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID11
+#define GDS_GWS_VMID11__BASE__SHIFT 0x0
+#define GDS_GWS_VMID11__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID11__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID11__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID12
+#define GDS_GWS_VMID12__BASE__SHIFT 0x0
+#define GDS_GWS_VMID12__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID12__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID12__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID13
+#define GDS_GWS_VMID13__BASE__SHIFT 0x0
+#define GDS_GWS_VMID13__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID13__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID13__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID14
+#define GDS_GWS_VMID14__BASE__SHIFT 0x0
+#define GDS_GWS_VMID14__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID14__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID14__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID15
+#define GDS_GWS_VMID15__BASE__SHIFT 0x0
+#define GDS_GWS_VMID15__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID15__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID15__SIZE_MASK 0x007F0000L
+//GDS_OA_VMID0
+#define GDS_OA_VMID0__MASK__SHIFT 0x0
+#define GDS_OA_VMID0__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID0__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID0__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID1
+#define GDS_OA_VMID1__MASK__SHIFT 0x0
+#define GDS_OA_VMID1__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID1__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID1__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID2
+#define GDS_OA_VMID2__MASK__SHIFT 0x0
+#define GDS_OA_VMID2__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID2__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID2__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID3
+#define GDS_OA_VMID3__MASK__SHIFT 0x0
+#define GDS_OA_VMID3__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID3__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID3__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID4
+#define GDS_OA_VMID4__MASK__SHIFT 0x0
+#define GDS_OA_VMID4__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID4__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID4__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID5
+#define GDS_OA_VMID5__MASK__SHIFT 0x0
+#define GDS_OA_VMID5__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID5__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID5__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID6
+#define GDS_OA_VMID6__MASK__SHIFT 0x0
+#define GDS_OA_VMID6__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID6__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID6__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID7
+#define GDS_OA_VMID7__MASK__SHIFT 0x0
+#define GDS_OA_VMID7__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID7__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID7__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID8
+#define GDS_OA_VMID8__MASK__SHIFT 0x0
+#define GDS_OA_VMID8__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID8__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID8__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID9
+#define GDS_OA_VMID9__MASK__SHIFT 0x0
+#define GDS_OA_VMID9__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID9__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID9__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID10
+#define GDS_OA_VMID10__MASK__SHIFT 0x0
+#define GDS_OA_VMID10__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID10__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID10__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID11
+#define GDS_OA_VMID11__MASK__SHIFT 0x0
+#define GDS_OA_VMID11__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID11__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID11__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID12
+#define GDS_OA_VMID12__MASK__SHIFT 0x0
+#define GDS_OA_VMID12__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID12__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID12__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID13
+#define GDS_OA_VMID13__MASK__SHIFT 0x0
+#define GDS_OA_VMID13__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID13__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID13__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID14
+#define GDS_OA_VMID14__MASK__SHIFT 0x0
+#define GDS_OA_VMID14__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID14__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID14__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID15
+#define GDS_OA_VMID15__MASK__SHIFT 0x0
+#define GDS_OA_VMID15__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID15__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID15__UNUSED_MASK 0xFFFF0000L
+//GDS_GWS_RESET0
+#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0
+#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1
+#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2
+#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3
+#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4
+#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5
+#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6
+#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7
+#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8
+#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9
+#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa
+#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb
+#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc
+#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd
+#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe
+#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf
+#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10
+#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11
+#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12
+#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13
+#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14
+#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15
+#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16
+#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17
+#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18
+#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19
+#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a
+#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b
+#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c
+#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d
+#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e
+#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f
+#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x00000001L
+#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x00000002L
+#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x00000004L
+#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x00000008L
+#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x00000010L
+#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x00000020L
+#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x00000040L
+#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x00000080L
+#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x00000100L
+#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x00000200L
+#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x00000400L
+#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x00000800L
+#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x00001000L
+#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x00002000L
+#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x00004000L
+#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x00008000L
+#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x00010000L
+#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x00020000L
+#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x00040000L
+#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x00080000L
+#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x00100000L
+#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x00200000L
+#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x00400000L
+#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x00800000L
+#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x01000000L
+#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x02000000L
+#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x04000000L
+#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x08000000L
+#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000L
+#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000L
+#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000L
+#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000L
+//GDS_GWS_RESET1
+#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0
+#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1
+#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2
+#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3
+#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4
+#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5
+#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6
+#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7
+#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8
+#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9
+#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa
+#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb
+#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc
+#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd
+#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe
+#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf
+#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10
+#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11
+#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12
+#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13
+#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14
+#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15
+#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16
+#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17
+#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18
+#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19
+#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a
+#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b
+#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c
+#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d
+#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e
+#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f
+#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x00000001L
+#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x00000002L
+#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x00000004L
+#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x00000008L
+#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x00000010L
+#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x00000020L
+#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x00000040L
+#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x00000080L
+#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x00000100L
+#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x00000200L
+#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x00000400L
+#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x00000800L
+#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x00001000L
+#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x00002000L
+#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x00004000L
+#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x00008000L
+#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x00010000L
+#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x00020000L
+#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x00040000L
+#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x00080000L
+#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x00100000L
+#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x00200000L
+#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x00400000L
+#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x00800000L
+#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x01000000L
+#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x02000000L
+#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x04000000L
+#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x08000000L
+#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000L
+#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000L
+#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000L
+#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000L
+//GDS_GWS_RESOURCE_RESET
+#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0
+#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8
+#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L
+#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000FF00L
+//GDS_COMPUTE_MAX_WAVE_ID
+#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
+#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
+//GDS_OA_RESET_MASK
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1
+#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT 0x3
+#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4
+#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5
+#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6
+#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7
+#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8
+#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9
+#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa
+#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb
+#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x00000001L
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x00000002L
+#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x00000004L
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK 0x00000008L
+#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x00000010L
+#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x00000020L
+#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x00000040L
+#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x00000080L
+#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x00000100L
+#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x00000200L
+#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x00000400L
+#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x00000800L
+#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xFFFFF000L
+//GDS_OA_RESET
+#define GDS_OA_RESET__RESET__SHIFT 0x0
+#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8
+#define GDS_OA_RESET__RESET_MASK 0x00000001L
+#define GDS_OA_RESET__PIPE_ID_MASK 0x0000FF00L
+//GDS_ENHANCE
+#define GDS_ENHANCE__MISC__SHIFT 0x0
+#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10
+#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11
+#define GDS_ENHANCE__RD_BUF_TAG_MISS__SHIFT 0x12
+#define GDS_ENHANCE__GDSA_PC_CGTS_DIS__SHIFT 0x13
+#define GDS_ENHANCE__GDSO_PC_CGTS_DIS__SHIFT 0x14
+#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE__SHIFT 0x15
+#define GDS_ENHANCE__UNUSED__SHIFT 0x16
+#define GDS_ENHANCE__MISC_MASK 0x0000FFFFL
+#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L
+#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x00020000L
+#define GDS_ENHANCE__RD_BUF_TAG_MISS_MASK 0x00040000L
+#define GDS_ENHANCE__GDSA_PC_CGTS_DIS_MASK 0x00080000L
+#define GDS_ENHANCE__GDSO_PC_CGTS_DIS_MASK 0x00100000L
+#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE_MASK 0x00200000L
+#define GDS_ENHANCE__UNUSED_MASK 0xFFC00000L
+//GDS_OA_CGPG_RESTORE
+#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0
+#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8
+#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc
+#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10
+#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14
+#define GDS_OA_CGPG_RESTORE__VMID_MASK 0x000000FFL
+#define GDS_OA_CGPG_RESTORE__MEID_MASK 0x00000F00L
+#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0x0000F000L
+#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0x000F0000L
+#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xFFF00000L
+//GDS_CS_CTXSW_STATUS
+#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0
+#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1
+#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2
+#define GDS_CS_CTXSW_STATUS__R_MASK 0x00000001L
+#define GDS_CS_CTXSW_STATUS__W_MASK 0x00000002L
+#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL
+//GDS_CS_CTXSW_CNT0
+#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_CS_CTXSW_CNT1
+#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_CS_CTXSW_CNT2
+#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_CS_CTXSW_CNT3
+#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_GFX_CTXSW_STATUS
+#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0
+#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1
+#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2
+#define GDS_GFX_CTXSW_STATUS__R_MASK 0x00000001L
+#define GDS_GFX_CTXSW_STATUS__W_MASK 0x00000002L
+#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL
+//GDS_VS_CTXSW_CNT0
+#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_VS_CTXSW_CNT1
+#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_VS_CTXSW_CNT2
+#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_VS_CTXSW_CNT3
+#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_PS0_CTXSW_CNT0
+#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_PS0_CTXSW_CNT1
+#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_PS0_CTXSW_CNT2
+#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_PS0_CTXSW_CNT3
+#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_PS1_CTXSW_CNT0
+#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_PS1_CTXSW_CNT1
+#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_PS1_CTXSW_CNT2
+#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_PS1_CTXSW_CNT3
+#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_PS2_CTXSW_CNT0
+#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_PS2_CTXSW_CNT1
+#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_PS2_CTXSW_CNT2
+#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_PS2_CTXSW_CNT3
+#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_PS3_CTXSW_CNT0
+#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_PS3_CTXSW_CNT1
+#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_PS3_CTXSW_CNT2
+#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_PS3_CTXSW_CNT3
+#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_PS4_CTXSW_CNT0
+#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_PS4_CTXSW_CNT1
+#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_PS4_CTXSW_CNT2
+#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_PS4_CTXSW_CNT3
+#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_PS5_CTXSW_CNT0
+#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_PS5_CTXSW_CNT1
+#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_PS5_CTXSW_CNT2
+#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_PS5_CTXSW_CNT3
+#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_PS6_CTXSW_CNT0
+#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_PS6_CTXSW_CNT1
+#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_PS6_CTXSW_CNT2
+#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_PS6_CTXSW_CNT3
+#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_PS7_CTXSW_CNT0
+#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_PS7_CTXSW_CNT1
+#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_PS7_CTXSW_CNT2
+#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_PS7_CTXSW_CNT3
+#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_GS_CTXSW_CNT0
+#define GDS_GS_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_GS_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_GS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_GS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_GS_CTXSW_CNT1
+#define GDS_GS_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_GS_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_GS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_GS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_GS_CTXSW_CNT2
+#define GDS_GS_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_GS_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_GS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_GS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_GS_CTXSW_CNT3
+#define GDS_GS_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_GS_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_GS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_GS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+
+
+// addressBlock: gc_rasdec
+//RAS_SIGNATURE_CONTROL
+#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0
+#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x00000001L
+//RAS_SIGNATURE_MASK
+#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0
+#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xFFFFFFFFL
+//RAS_SX_SIGNATURE0
+#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_SX_SIGNATURE1
+#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_SX_SIGNATURE2
+#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0
+#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_SX_SIGNATURE3
+#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0
+#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_DB_SIGNATURE0
+#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_PA_SIGNATURE0
+#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_VGT_SIGNATURE0
+#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_SQ_SIGNATURE0
+#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_SC_SIGNATURE0
+#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_SC_SIGNATURE1
+#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_SC_SIGNATURE2
+#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_SC_SIGNATURE3
+#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_SC_SIGNATURE4
+#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_SC_SIGNATURE5
+#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_SC_SIGNATURE6
+#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_SC_SIGNATURE7
+#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_IA_SIGNATURE0
+#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_IA_SIGNATURE1
+#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_SPI_SIGNATURE0
+#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_SPI_SIGNATURE1
+#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_TA_SIGNATURE0
+#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_TD_SIGNATURE0
+#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_CB_SIGNATURE0
+#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_BCI_SIGNATURE0
+#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_BCI_SIGNATURE1
+#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
+//RAS_TA_SIGNATURE1
+#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_gfxdec0
+//DB_RENDER_CONTROL
+#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0
+#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1
+#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2
+#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3
+#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4
+#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5
+#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6
+#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7
+#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8
+#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc
+#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L
+#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L
+#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L
+#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L
+#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L
+#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L
+#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L
+#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L
+#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000F00L
+#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L
+//DB_COUNT_CONTROL
+#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0
+#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1
+#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4
+#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
+#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc
+#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10
+#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14
+#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18
+#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c
+#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L
+#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L
+#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L
+#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000F00L
+#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000F000L
+#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000F0000L
+#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00F00000L
+#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0F000000L
+#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xF0000000L
+//DB_DEPTH_VIEW
+#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0
+#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd
+#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18
+#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19
+#define DB_DEPTH_VIEW__MIPID__SHIFT 0x1a
+#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007FFL
+#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00FFE000L
+#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L
+#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L
+#define DB_DEPTH_VIEW__MIPID_MASK 0x3C000000L
+//DB_RENDER_OVERRIDE
+#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4
+#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6
+#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7
+#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8
+#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9
+#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
+#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc
+#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd
+#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf
+#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10
+#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11
+#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12
+#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13
+#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15
+#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a
+#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c
+#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e
+#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f
+#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000CL
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L
+#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L
+#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L
+#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L
+#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L
+#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L
+#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L
+#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L
+#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L
+#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L
+#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L
+#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L
+#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L
+#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03E00000L
+#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L
+#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L
+#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L
+#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L
+//DB_RENDER_OVERRIDE2
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2
+#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5
+#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6
+#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7
+#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8
+#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9
+#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
+#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb
+#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12
+#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15
+#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16
+#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17
+#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL
+#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L
+#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L
+#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L
+#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L
+#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L
+#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L
+#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L
+#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001C0000L
+#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L
+#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L
+#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L
+#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L
+//DB_HTILE_DATA_BASE
+#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0
+#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//DB_HTILE_DATA_BASE_HI
+#define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT 0x0
+#define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK 0x000000FFL
+//DB_DEPTH_SIZE
+#define DB_DEPTH_SIZE__X_MAX__SHIFT 0x0
+#define DB_DEPTH_SIZE__Y_MAX__SHIFT 0x10
+#define DB_DEPTH_SIZE__X_MAX_MASK 0x00003FFFL
+#define DB_DEPTH_SIZE__Y_MAX_MASK 0x3FFF0000L
+//DB_DEPTH_BOUNDS_MIN
+#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0
+#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xFFFFFFFFL
+//DB_DEPTH_BOUNDS_MAX
+#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0
+#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xFFFFFFFFL
+//DB_STENCIL_CLEAR
+#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0
+#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000FFL
+//DB_DEPTH_CLEAR
+#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0
+#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xFFFFFFFFL
+//PA_SC_SCREEN_SCISSOR_TL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000FFFFL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L
+//PA_SC_SCREEN_SCISSOR_BR
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000FFFFL
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L
+//DB_Z_INFO
+#define DB_Z_INFO__FORMAT__SHIFT 0x0
+#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2
+#define DB_Z_INFO__SW_MODE__SHIFT 0x4
+#define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT 0xc
+#define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT 0xd
+#define DB_Z_INFO__ITERATE_FLUSH__SHIFT 0xf
+#define DB_Z_INFO__MAXMIP__SHIFT 0x10
+#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17
+#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
+#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c
+#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d
+#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
+#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f
+#define DB_Z_INFO__FORMAT_MASK 0x00000003L
+#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000CL
+#define DB_Z_INFO__SW_MODE_MASK 0x000001F0L
+#define DB_Z_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L
+#define DB_Z_INFO__FAULT_BEHAVIOR_MASK 0x00006000L
+#define DB_Z_INFO__ITERATE_FLUSH_MASK 0x00008000L
+#define DB_Z_INFO__MAXMIP_MASK 0x000F0000L
+#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L
+#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L
+#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L
+#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L
+#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000L
+#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L
+//DB_STENCIL_INFO
+#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0
+#define DB_STENCIL_INFO__SW_MODE__SHIFT 0x4
+#define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT 0xc
+#define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT 0xd
+#define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT 0xf
+#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
+#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d
+#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
+#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L
+#define DB_STENCIL_INFO__SW_MODE_MASK 0x000001F0L
+#define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L
+#define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK 0x00006000L
+#define DB_STENCIL_INFO__ITERATE_FLUSH_MASK 0x00008000L
+#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L
+#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L
+#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000L
+//DB_Z_READ_BASE
+#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0
+#define DB_Z_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//DB_Z_READ_BASE_HI
+#define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0
+#define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL
+//DB_STENCIL_READ_BASE
+#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0
+#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//DB_STENCIL_READ_BASE_HI
+#define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x0
+#define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000FFL
+//DB_Z_WRITE_BASE
+#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0
+#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//DB_Z_WRITE_BASE_HI
+#define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x0
+#define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL
+//DB_STENCIL_WRITE_BASE
+#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0
+#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//DB_STENCIL_WRITE_BASE_HI
+#define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x0
+#define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL
+//DB_DFSM_CONTROL
+#define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT 0x0
+#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT 0x2
+#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT 0x3
+#define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L
+#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L
+#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L
+//DB_RENDER_FILTER
+#define DB_RENDER_FILTER__PS_INVOKE_MASK__SHIFT 0x0
+#define DB_RENDER_FILTER__PS_INVOKE_MASK_MASK 0x0000FFFFL
+//DB_Z_INFO2
+#define DB_Z_INFO2__EPITCH__SHIFT 0x0
+#define DB_Z_INFO2__EPITCH_MASK 0x0000FFFFL
+//DB_STENCIL_INFO2
+#define DB_STENCIL_INFO2__EPITCH__SHIFT 0x0
+#define DB_STENCIL_INFO2__EPITCH_MASK 0x0000FFFFL
+//TA_BC_BASE_ADDR
+#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
+#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL
+//TA_BC_BASE_ADDR_HI
+#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
+#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL
+//COHER_DEST_BASE_HI_0
+#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000FFL
+//COHER_DEST_BASE_HI_1
+#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000FFL
+//COHER_DEST_BASE_HI_2
+#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000FFL
+//COHER_DEST_BASE_HI_3
+#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000FFL
+//COHER_DEST_BASE_2
+#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xFFFFFFFFL
+//COHER_DEST_BASE_3
+#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xFFFFFFFFL
+//PA_SC_WINDOW_OFFSET
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000FFFFL
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xFFFF0000L
+//PA_SC_WINDOW_SCISSOR_TL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_WINDOW_SCISSOR_BR
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_RULE
+#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0
+#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000FFFFL
+//PA_SC_CLIPRECT_0_TL
+#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_0_BR
+#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_1_TL
+#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_1_BR
+#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_2_TL
+#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_2_BR
+#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_3_TL
+#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_3_BR
+#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_EDGERULE
+#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0
+#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4
+#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8
+#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc
+#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12
+#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18
+#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c
+#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000FL
+#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000F0L
+#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000F00L
+#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003F000L
+#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00FC0000L
+#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0F000000L
+#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xF0000000L
+//PA_SU_HARDWARE_SCREEN_OFFSET
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001FFL
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01FF0000L
+//CB_TARGET_MASK
+#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
+#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
+#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
+#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
+#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
+#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
+#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
+#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
+#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000FL
+#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000F0L
+#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000F00L
+#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000F000L
+#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000F0000L
+#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00F00000L
+#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0F000000L
+#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xF0000000L
+//CB_SHADER_MASK
+#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
+#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
+#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
+#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
+#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
+#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
+#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
+#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
+#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000FL
+#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000F0L
+#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000F00L
+#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000F000L
+#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000F0000L
+#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00F00000L
+#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0F000000L
+#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xF0000000L
+//PA_SC_GENERIC_SCISSOR_TL
+#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0
+#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10
+#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_GENERIC_SCISSOR_BR
+#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0
+#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10
+#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L
+//COHER_DEST_BASE_0
+#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xFFFFFFFFL
+//COHER_DEST_BASE_1
+#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_SCISSOR_0_TL
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_0_BR
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_1_TL
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_1_BR
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_2_TL
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_2_BR
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_3_TL
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_3_BR
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_4_TL
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_4_BR
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_5_TL
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_5_BR
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_6_TL
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_6_BR
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_7_TL
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_7_BR
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_8_TL
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_8_BR
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_9_TL
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_9_BR
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_10_TL
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_10_BR
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_11_TL
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_11_BR
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_12_TL
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_12_BR
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_13_TL
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_13_BR
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_14_TL
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_14_BR
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_15_TL
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_15_BR
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_ZMIN_0
+#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_0
+#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_1
+#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_1
+#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_2
+#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_2
+#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_3
+#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_3
+#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_4
+#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_4
+#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_5
+#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_5
+#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_6
+#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_6
+#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_7
+#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_7
+#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_8
+#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_8
+#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_9
+#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_9
+#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_10
+#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_10
+#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_11
+#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_11
+#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_12
+#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_12
+#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_13
+#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_13
+#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_14
+#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_14
+#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_15
+#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_15
+#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_RASTER_CONFIG
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2
+#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4
+#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6
+#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7
+#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8
+#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
+#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc
+#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe
+#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10
+#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12
+#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14
+#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18
+#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a
+#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1d
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000CL
+#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L
+#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L
+#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L
+#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L
+#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000C00L
+#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L
+#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000C000L
+#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L
+#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000C0000L
+#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L
+#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L
+#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x1C000000L
+#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0xE0000000L
+//PA_SC_RASTER_CONFIG_1
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x5
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000001CL
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x000000E0L
+//PA_SC_SCREEN_EXTENT_CONTROL
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000CL
+//PA_SC_TILE_STEERING_OVERRIDE
+#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0
+#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1
+#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5
+#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT 0x8
+#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L
+#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L
+#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L
+#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK 0x00000100L
+//CP_PERFMON_CNTX_CNTL
+#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
+#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L
+//CP_PIPEID
+#define CP_PIPEID__PIPE_ID__SHIFT 0x0
+#define CP_PIPEID__PIPE_ID_MASK 0x00000003L
+//CP_RINGID
+#define CP_RINGID__RINGID__SHIFT 0x0
+#define CP_RINGID__RINGID_MASK 0x00000003L
+//CP_VMID
+#define CP_VMID__VMID__SHIFT 0x0
+#define CP_VMID__VMID_MASK 0x0000000FL
+//PA_SC_RIGHT_VERT_GRID
+#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT 0x0
+#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT 0x8
+#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT 0x10
+#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT 0x18
+#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL
+#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L
+#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L
+#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L
+//PA_SC_LEFT_VERT_GRID
+#define PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT 0x0
+#define PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT 0x8
+#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT 0x10
+#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT 0x18
+#define PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL
+#define PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L
+#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L
+#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L
+//PA_SC_HORIZ_GRID
+#define PA_SC_HORIZ_GRID__TOP_QTR__SHIFT 0x0
+#define PA_SC_HORIZ_GRID__TOP_HALF__SHIFT 0x8
+#define PA_SC_HORIZ_GRID__BOT_HALF__SHIFT 0x10
+#define PA_SC_HORIZ_GRID__BOT_QTR__SHIFT 0x18
+#define PA_SC_HORIZ_GRID__TOP_QTR_MASK 0x000000FFL
+#define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000FF00L
+#define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00FF0000L
+#define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xFF000000L
+//PA_SC_FOV_WINDOW_LR
+#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_LEFT__SHIFT 0x0
+#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_RIGHT__SHIFT 0x8
+#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_LEFT__SHIFT 0x10
+#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_RIGHT__SHIFT 0x18
+#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_LEFT_MASK 0x000000FFL
+#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_RIGHT_MASK 0x0000FF00L
+#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_LEFT_MASK 0x00FF0000L
+#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_RIGHT_MASK 0xFF000000L
+//PA_SC_FOV_WINDOW_TB
+#define PA_SC_FOV_WINDOW_TB__FOV_TOP__SHIFT 0x0
+#define PA_SC_FOV_WINDOW_TB__FOV_BOT__SHIFT 0x8
+#define PA_SC_FOV_WINDOW_TB__FOV_TOP_MASK 0x000000FFL
+#define PA_SC_FOV_WINDOW_TB__FOV_BOT_MASK 0x0000FF00L
+//VGT_MULTI_PRIM_IB_RESET_INDX
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL
+//CB_BLEND_RED
+#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
+#define CB_BLEND_RED__BLEND_RED_MASK 0xFFFFFFFFL
+//CB_BLEND_GREEN
+#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
+#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xFFFFFFFFL
+//CB_BLEND_BLUE
+#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
+#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xFFFFFFFFL
+//CB_BLEND_ALPHA
+#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
+#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xFFFFFFFFL
+//CB_DCC_CONTROL
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x00000002L
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x0000007CL
+//DB_STENCIL_CONTROL
+#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0
+#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4
+#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8
+#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc
+#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10
+#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14
+#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000FL
+#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000F0L
+#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000F00L
+#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000F000L
+#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000F0000L
+#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00F00000L
+//DB_STENCILREFMASK
+#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0
+#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8
+#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10
+#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18
+#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000FFL
+#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000FF00L
+#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00FF0000L
+#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xFF000000L
+//DB_STENCILREFMASK_BF
+#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0
+#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8
+#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10
+#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18
+#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000FFL
+#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000FF00L
+#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00FF0000L
+#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xFF000000L
+//PA_CL_VPORT_XSCALE
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_1
+#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_1
+#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_1
+#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_1
+#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_1
+#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_1
+#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_2
+#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_2
+#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_2
+#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_2
+#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_2
+#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_2
+#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_3
+#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_3
+#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_3
+#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_3
+#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_3
+#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_3
+#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_4
+#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_4
+#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_4
+#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_4
+#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_4
+#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_4
+#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_5
+#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_5
+#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_5
+#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_5
+#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_5
+#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_5
+#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_6
+#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_6
+#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_6
+#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_6
+#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_6
+#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_6
+#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_7
+#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_7
+#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_7
+#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_7
+#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_7
+#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_7
+#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_8
+#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_8
+#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_8
+#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_8
+#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_8
+#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_8
+#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_9
+#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_9
+#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_9
+#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_9
+#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_9
+#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_9
+#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_10
+#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_10
+#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_10
+#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_10
+#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_10
+#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_10
+#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_11
+#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_11
+#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_11
+#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_11
+#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_11
+#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_11
+#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_12
+#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_12
+#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_12
+#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_12
+#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_12
+#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_12
+#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_13
+#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_13
+#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_13
+#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_13
+#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_13
+#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_13
+#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_14
+#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_14
+#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_14
+#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_14
+#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_14
+#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_14
+#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_15
+#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_15
+#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_15
+#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_15
+#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_15
+#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_15
+#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_UCP_0_X
+#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_0_Y
+#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_0_Z
+#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_0_W
+#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_1_X
+#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_1_Y
+#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_1_Z
+#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_1_W
+#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_2_X
+#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_2_Y
+#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_2_Z
+#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_2_W
+#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_3_X
+#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_3_Y
+#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_3_Z
+#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_3_W
+#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_4_X
+#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_4_Y
+#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_4_Z
+#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_4_W
+#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_5_X
+#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_5_Y
+#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_5_Z
+#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_5_W
+#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xFFFFFFFFL
+//SPI_PS_INPUT_CNTL_0
+#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_1
+#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_2
+#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_3
+#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_4
+#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_5
+#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_6
+#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_7
+#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_8
+#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_9
+#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_10
+#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_11
+#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_12
+#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_13
+#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_14
+#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_15
+#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_16
+#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_17
+#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_18
+#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_19
+#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_20
+#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_21
+#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_22
+#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_23
+#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_24
+#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_25
+#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_26
+#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_27
+#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_28
+#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_29
+#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_30
+#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_31
+#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L
+//SPI_VS_OUT_CONFIG
+#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1
+#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6
+#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003EL
+#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L
+//SPI_PS_INPUT_ENA
+#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0
+#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1
+#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2
+#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3
+#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4
+#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5
+#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6
+#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
+#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8
+#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9
+#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
+#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb
+#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc
+#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd
+#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe
+#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf
+#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L
+#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L
+#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L
+#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L
+#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L
+#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L
+#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L
+#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L
+#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L
+#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L
+#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L
+#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L
+#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L
+#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L
+#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L
+#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L
+//SPI_PS_INPUT_ADDR
+#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0
+#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1
+#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2
+#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3
+#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6
+#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
+#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8
+#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9
+#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
+#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb
+#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc
+#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd
+#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe
+#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf
+#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L
+#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L
+#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L
+#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L
+#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L
+#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L
+#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L
+#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L
+#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L
+#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L
+#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L
+#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L
+#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L
+#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L
+//SPI_INTERP_CONTROL_0
+#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe
+#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001CL
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000E0L
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L
+//SPI_PS_IN_CONTROL
+#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0
+#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6
+#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT 0x7
+#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT 0x8
+#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe
+#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003FL
+#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L
+#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK 0x00000080L
+#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK 0x00000100L
+#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L
+//SPI_BARYC_CNTL
+#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0
+#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4
+#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8
+#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc
+#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10
+#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14
+#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18
+#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L
+#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L
+#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L
+#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L
+#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L
+#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L
+#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L
+//SPI_TMPRING_SIZE
+#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0
+#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
+#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000FFFL
+#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L
+//SPI_SHADER_POS_FORMAT
+#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0
+#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4
+#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8
+#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc
+#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000FL
+#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000F0L
+#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000F00L
+#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000F000L
+//SPI_SHADER_Z_FORMAT
+#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0
+#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000FL
+//SPI_SHADER_COL_FORMAT
+#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0
+#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4
+#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8
+#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc
+#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10
+#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14
+#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18
+#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c
+#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000FL
+#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000F0L
+#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000F00L
+#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000F000L
+#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000F0000L
+#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00F00000L
+#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0F000000L
+#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xF0000000L
+//SX_PS_DOWNCONVERT
+#define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0
+#define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4
+#define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8
+#define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc
+#define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10
+#define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14
+#define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18
+#define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c
+#define SX_PS_DOWNCONVERT__MRT0_MASK 0x0000000FL
+#define SX_PS_DOWNCONVERT__MRT1_MASK 0x000000F0L
+#define SX_PS_DOWNCONVERT__MRT2_MASK 0x00000F00L
+#define SX_PS_DOWNCONVERT__MRT3_MASK 0x0000F000L
+#define SX_PS_DOWNCONVERT__MRT4_MASK 0x000F0000L
+#define SX_PS_DOWNCONVERT__MRT5_MASK 0x00F00000L
+#define SX_PS_DOWNCONVERT__MRT6_MASK 0x0F000000L
+#define SX_PS_DOWNCONVERT__MRT7_MASK 0xF0000000L
+//SX_BLEND_OPT_EPSILON
+#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0
+#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4
+#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8
+#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc
+#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10
+#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14
+#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18
+#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c
+#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0x0000000FL
+#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0x000000F0L
+#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0x00000F00L
+#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0x0000F000L
+#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0x000F0000L
+#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0x00F00000L
+#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0x0F000000L
+#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xF0000000L
+//SX_BLEND_OPT_CONTROL
+#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0
+#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1
+#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4
+#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5
+#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8
+#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9
+#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc
+#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd
+#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10
+#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11
+#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14
+#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15
+#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18
+#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19
+#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c
+#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d
+#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f
+#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x00000001L
+#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x00000002L
+#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x00000010L
+#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x00000020L
+#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x00000100L
+#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x00000200L
+#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x00001000L
+#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x00002000L
+#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x00010000L
+#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x00020000L
+#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x00100000L
+#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x00200000L
+#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x01000000L
+#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x02000000L
+#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000L
+#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000L
+#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000L
+//SX_MRT0_BLEND_OPT
+#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//SX_MRT1_BLEND_OPT
+#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//SX_MRT2_BLEND_OPT
+#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//SX_MRT3_BLEND_OPT
+#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//SX_MRT4_BLEND_OPT
+#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//SX_MRT5_BLEND_OPT
+#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//SX_MRT6_BLEND_OPT
+#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//SX_MRT7_BLEND_OPT
+#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//CB_BLEND0_CONTROL
+#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_BLEND1_CONTROL
+#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_BLEND2_CONTROL
+#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_BLEND3_CONTROL
+#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_BLEND4_CONTROL
+#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_BLEND5_CONTROL
+#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_BLEND6_CONTROL
+#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_BLEND7_CONTROL
+#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_MRT0_EPITCH
+#define CB_MRT0_EPITCH__EPITCH__SHIFT 0x0
+#define CB_MRT0_EPITCH__EPITCH_MASK 0x0000FFFFL
+//CB_MRT1_EPITCH
+#define CB_MRT1_EPITCH__EPITCH__SHIFT 0x0
+#define CB_MRT1_EPITCH__EPITCH_MASK 0x0000FFFFL
+//CB_MRT2_EPITCH
+#define CB_MRT2_EPITCH__EPITCH__SHIFT 0x0
+#define CB_MRT2_EPITCH__EPITCH_MASK 0x0000FFFFL
+//CB_MRT3_EPITCH
+#define CB_MRT3_EPITCH__EPITCH__SHIFT 0x0
+#define CB_MRT3_EPITCH__EPITCH_MASK 0x0000FFFFL
+//CB_MRT4_EPITCH
+#define CB_MRT4_EPITCH__EPITCH__SHIFT 0x0
+#define CB_MRT4_EPITCH__EPITCH_MASK 0x0000FFFFL
+//CB_MRT5_EPITCH
+#define CB_MRT5_EPITCH__EPITCH__SHIFT 0x0
+#define CB_MRT5_EPITCH__EPITCH_MASK 0x0000FFFFL
+//CB_MRT6_EPITCH
+#define CB_MRT6_EPITCH__EPITCH__SHIFT 0x0
+#define CB_MRT6_EPITCH__EPITCH_MASK 0x0000FFFFL
+//CB_MRT7_EPITCH
+#define CB_MRT7_EPITCH__EPITCH__SHIFT 0x0
+#define CB_MRT7_EPITCH__EPITCH_MASK 0x0000FFFFL
+//CS_COPY_STATE
+#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
+#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
+//GFX_COPY_STATE
+#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
+#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
+//PA_CL_POINT_X_RAD
+#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_POINT_Y_RAD
+#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_POINT_SIZE
+#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_POINT_CULL_RAD
+#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL
+//VGT_DMA_BASE_HI
+#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0
+#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000FFFFL
+//VGT_DMA_BASE
+#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0
+#define VGT_DMA_BASE__BASE_ADDR_MASK 0xFFFFFFFFL
+//VGT_DRAW_INITIATOR
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0
+#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2
+#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4
+#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5
+#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6
+#define VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT 0x7
+#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT 0x8
+#define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x1d
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L
+#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000CL
+#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L
+#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L
+#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L
+#define VGT_DRAW_INITIATOR__UNROLLED_INST_MASK 0x00000080L
+#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK 0x00000100L
+#define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xE0000000L
+//VGT_IMMED_DATA
+#define VGT_IMMED_DATA__DATA__SHIFT 0x0
+#define VGT_IMMED_DATA__DATA_MASK 0xFFFFFFFFL
+//VGT_EVENT_ADDRESS_REG
+#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0
+#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0FFFFFFFL
+//DB_DEPTH_CONTROL
+#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0
+#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1
+#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2
+#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3
+#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4
+#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7
+#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8
+#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14
+#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e
+#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f
+#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L
+#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L
+#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L
+#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L
+#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L
+#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L
+#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L
+#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L
+#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L
+#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L
+//DB_EQAA
+#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0
+#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4
+#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8
+#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc
+#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10
+#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11
+#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12
+#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13
+#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14
+#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15
+#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18
+#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b
+#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L
+#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L
+#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L
+#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L
+#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L
+#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L
+#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L
+#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L
+#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L
+#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L
+#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L
+#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L
+//CB_COLOR_CONTROL
+#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0
+#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
+#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
+#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
+#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L
+#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L
+#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L
+#define CB_COLOR_CONTROL__ROP3_MASK 0x00FF0000L
+//DB_SHADER_CONTROL
+#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0
+#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1
+#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2
+#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4
+#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6
+#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7
+#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8
+#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9
+#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
+#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb
+#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc
+#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd
+#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf
+#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x10
+#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT 0x11
+#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT 0x14
+#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L
+#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L
+#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L
+#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L
+#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L
+#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L
+#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L
+#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L
+#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L
+#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L
+#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L
+#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L
+#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L
+#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L
+#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK 0x00020000L
+#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK 0x00700000L
+//PA_CL_CLIP_CNTL
+#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0
+#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1
+#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2
+#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3
+#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4
+#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5
+#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd
+#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10
+#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15
+#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16
+#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18
+#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19
+#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a
+#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b
+#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L
+#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L
+#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L
+#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L
+#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L
+#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L
+#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L
+#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000C000L
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L
+#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L
+#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L
+#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L
+#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L
+#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L
+#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L
+//PA_SU_SC_MODE_CNTL
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0
+#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1
+#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2
+#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15
+#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x16
+#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x17
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L
+#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L
+#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L
+#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000E0L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L
+#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L
+#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L
+//PA_CL_VTE_CNTL
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5
+#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8
+#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9
+#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L
+#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L
+#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L
+#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L
+//PA_CL_VS_OUT_CNTL
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf
+#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10
+#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11
+#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12
+#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13
+#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18
+#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19
+#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a
+#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT 0x1b
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x04000000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK 0x08000000L
+//PA_CL_NANINF_CNTL
+#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0
+#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1
+#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2
+#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3
+#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4
+#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5
+#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6
+#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7
+#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8
+#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9
+#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
+#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb
+#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc
+#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd
+#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe
+#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14
+#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L
+#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L
+#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L
+#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L
+#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L
+#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L
+#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L
+#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L
+#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L
+#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L
+#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L
+#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L
+#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L
+#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L
+#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L
+#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L
+//PA_SU_LINE_STIPPLE_CNTL
+#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0
+#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2
+#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3
+#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4
+#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L
+#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L
+#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L
+#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L
+//PA_SU_LINE_STIPPLE_SCALE
+#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0
+#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xFFFFFFFFL
+//PA_SU_PRIM_FILTER_CNTL
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0
+#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1
+#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4
+#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5
+#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7
+#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8
+#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e
+#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L
+#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L
+#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L
+#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L
+#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L
+#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000FF00L
+#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L
+#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L
+//PA_SU_SMALL_PRIM_FILTER_CNTL
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x0
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x1
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE__SHIFT 0x5
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE_MASK 0x00000020L
+//PA_CL_OBJPRIM_ID_CNTL
+#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x0
+#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x1
+#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID__SHIFT 0x2
+#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK 0x00000001L
+#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK 0x00000002L
+#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID_MASK 0x00000004L
+//PA_CL_NGG_CNTL
+#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x0
+#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x1
+#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L
+#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L
+//PA_SU_OVER_RASTERIZATION_CNTL
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x0
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x1
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x2
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x3
+#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x4
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L
+#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L
+//PA_SU_POINT_SIZE
+#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0
+#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10
+#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000FFFFL
+#define PA_SU_POINT_SIZE__WIDTH_MASK 0xFFFF0000L
+//PA_SU_POINT_MINMAX
+#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0
+#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10
+#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000FFFFL
+#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xFFFF0000L
+//PA_SU_LINE_CNTL
+#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0
+#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000FFFFL
+//PA_SC_LINE_STIPPLE
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000FFFFL
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00FF0000L
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L
+//VGT_OUTPUT_PATH_CNTL
+#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0
+#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L
+//VGT_HOS_CNTL
+#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0
+#define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L
+//VGT_HOS_MAX_TESS_LEVEL
+#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0
+#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xFFFFFFFFL
+//VGT_HOS_MIN_TESS_LEVEL
+#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0
+#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xFFFFFFFFL
+//VGT_HOS_REUSE_DEPTH
+#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0
+#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000FFL
+//VGT_GROUP_PRIM_TYPE
+#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0
+#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe
+#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf
+#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10
+#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001FL
+#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L
+#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L
+#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L
+//VGT_GROUP_FIRST_DECR
+#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0
+#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000FL
+//VGT_GROUP_DECR
+#define VGT_GROUP_DECR__DECR__SHIFT 0x0
+#define VGT_GROUP_DECR__DECR_MASK 0x0000000FL
+//VGT_GROUP_VECT_0_CNTL
+#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0
+#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1
+#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2
+#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3
+#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8
+#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10
+#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L
+#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L
+#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L
+#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L
+#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000FF00L
+#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00FF0000L
+//VGT_GROUP_VECT_1_CNTL
+#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0
+#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1
+#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2
+#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3
+#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8
+#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10
+#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L
+#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L
+#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L
+#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L
+#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000FF00L
+#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00FF0000L
+//VGT_GROUP_VECT_0_FMT_CNTL
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000FL
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000F0L
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000F00L
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000F0000L
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0F000000L
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xF0000000L
+//VGT_GROUP_VECT_1_FMT_CNTL
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000FL
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000F0L
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000F00L
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000F0000L
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0F000000L
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xF0000000L
+//VGT_GS_MODE
+#define VGT_GS_MODE__MODE__SHIFT 0x0
+#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3
+#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4
+#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6
+#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb
+#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc
+#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd
+#define VGT_GS_MODE__RESERVED_3__SHIFT 0xe
+#define VGT_GS_MODE__RESERVED_4__SHIFT 0xf
+#define VGT_GS_MODE__RESERVED_5__SHIFT 0x10
+#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11
+#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12
+#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13
+#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14
+#define VGT_GS_MODE__ONCHIP__SHIFT 0x15
+#define VGT_GS_MODE__MODE_MASK 0x00000007L
+#define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L
+#define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L
+#define VGT_GS_MODE__RESERVED_1_MASK 0x000007C0L
+#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L
+#define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L
+#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L
+#define VGT_GS_MODE__RESERVED_3_MASK 0x00004000L
+#define VGT_GS_MODE__RESERVED_4_MASK 0x00008000L
+#define VGT_GS_MODE__RESERVED_5_MASK 0x00010000L
+#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L
+#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L
+#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L
+#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L
+#define VGT_GS_MODE__ONCHIP_MASK 0x00600000L
+//VGT_GS_ONCHIP_CNTL
+#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0
+#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb
+#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT 0x16
+#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x000007FFL
+#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x003FF800L
+#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK 0xFFC00000L
+//PA_SC_MODE_CNTL_0
+#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0
+#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1
+#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2
+#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3
+#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT 0x4
+#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x5
+#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x6
+#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L
+#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L
+#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L
+#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L
+#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK 0x00000010L
+#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L
+#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L
+//PA_SC_MODE_CNTL_1
+#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0
+#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1
+#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4
+#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7
+#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8
+#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9
+#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc
+#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf
+#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10
+#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c
+#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L
+#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L
+#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L
+#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L
+#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L
+#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L
+#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L
+#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L
+#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L
+#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00F00000L
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L
+//VGT_ENHANCE
+#define VGT_ENHANCE__MISC__SHIFT 0x0
+#define VGT_ENHANCE__MISC_MASK 0xFFFFFFFFL
+//VGT_GS_PER_ES
+#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0
+#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007FFL
+//VGT_ES_PER_GS
+#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0
+#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007FFL
+//VGT_GS_PER_VS
+#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0
+#define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000FL
+//VGT_GSVS_RING_OFFSET_1
+#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0
+#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007FFFL
+//VGT_GSVS_RING_OFFSET_2
+#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0
+#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007FFFL
+//VGT_GSVS_RING_OFFSET_3
+#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0
+#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007FFFL
+//VGT_GS_OUT_PRIM_TYPE
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16
+#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003FL
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003F00L
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003F0000L
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0FC00000L
+#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L
+//IA_ENHANCE
+#define IA_ENHANCE__MISC__SHIFT 0x0
+#define IA_ENHANCE__MISC_MASK 0xFFFFFFFFL
+//VGT_DMA_SIZE
+#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0
+#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xFFFFFFFFL
+//VGT_DMA_MAX_SIZE
+#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0
+#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xFFFFFFFFL
+//VGT_DMA_INDEX_TYPE
+#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
+#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2
+#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4
+#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6
+#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8
+#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9
+#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa
+#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
+#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000CL
+#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L
+#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x00000040L
+#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L
+#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L
+#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L
+//WD_ENHANCE
+#define WD_ENHANCE__MISC__SHIFT 0x0
+#define WD_ENHANCE__MISC_MASK 0xFFFFFFFFL
+//VGT_PRIMITIVEID_EN
+#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0
+#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1
+#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x2
+#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L
+#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L
+#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L
+//VGT_DMA_NUM_INSTANCES
+#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
+#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL
+//VGT_PRIMITIVEID_RESET
+#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0
+#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xFFFFFFFFL
+//VGT_EVENT_INITIATOR
+#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
+#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa
+#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
+#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL
+#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L
+#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L
+//VGT_GS_MAX_PRIMS_PER_SUBGROUP
+#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP__SHIFT 0x0
+#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP_MASK 0x0000FFFFL
+//VGT_DRAW_PAYLOAD_CNTL
+#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT 0x0
+#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x1
+#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID__SHIFT 0x2
+#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT 0x3
+#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK 0x00000001L
+#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L
+#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK 0x00000004L
+#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000008L
+//VGT_INDEX_PAYLOAD_CNTL
+#define VGT_INDEX_PAYLOAD_CNTL__COMPOUND_INDEX_EN__SHIFT 0x0
+#define VGT_INDEX_PAYLOAD_CNTL__COMPOUND_INDEX_EN_MASK 0x00000001L
+//VGT_INSTANCE_STEP_RATE_0
+#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0
+#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL
+//VGT_INSTANCE_STEP_RATE_1
+#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0
+#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xFFFFFFFFL
+//VGT_ESGS_RING_ITEMSIZE
+#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
+#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL
+//VGT_GSVS_RING_ITEMSIZE
+#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
+#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL
+//VGT_REUSE_OFF
+#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0
+#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L
+//VGT_VTX_CNT_EN
+#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0
+#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L
+//DB_HTILE_SURFACE
+#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1
+#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2
+#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3
+#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4
+#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa
+#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10
+#define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT 0x12
+#define DB_HTILE_SURFACE__RB_ALIGNED__SHIFT 0x13
+#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L
+#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x00000004L
+#define DB_HTILE_SURFACE__PRELOAD_MASK 0x00000008L
+#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x000003F0L
+#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0x0000FC00L
+#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L
+#define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK 0x00040000L
+#define DB_HTILE_SURFACE__RB_ALIGNED_MASK 0x00080000L
+//DB_SRESULTS_COMPARE_STATE0
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc
+#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000FF0L
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000FF000L
+#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L
+//DB_SRESULTS_COMPARE_STATE1
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc
+#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000FF0L
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000FF000L
+#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L
+//DB_PRELOAD_CONTROL
+#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0
+#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8
+#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10
+#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18
+#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000FFL
+#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000FF00L
+#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00FF0000L
+#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xFF000000L
+//VGT_STRMOUT_BUFFER_SIZE_0
+#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_VTX_STRIDE_0
+#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003FFL
+//VGT_STRMOUT_BUFFER_OFFSET_0
+#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_BUFFER_SIZE_1
+#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_VTX_STRIDE_1
+#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003FFL
+//VGT_STRMOUT_BUFFER_OFFSET_1
+#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_BUFFER_SIZE_2
+#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_VTX_STRIDE_2
+#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003FFL
+//VGT_STRMOUT_BUFFER_OFFSET_2
+#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_BUFFER_SIZE_3
+#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_VTX_STRIDE_3
+#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003FFL
+//VGT_STRMOUT_BUFFER_OFFSET_3
+#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_DRAW_OPAQUE_OFFSET
+#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
+#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
+#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001FFL
+//VGT_GS_MAX_VERT_OUT
+#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0
+#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007FFL
+//VGT_TESS_DISTRIBUTION
+#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0
+#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8
+#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10
+#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18
+#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x1d
+#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000FFL
+#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000FF00L
+#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00FF0000L
+#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1F000000L
+#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xE0000000L
+//VGT_SHADER_STAGES_EN
+#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0
+#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2
+#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3
+#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5
+#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6
+#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9
+#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa
+#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb
+#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc
+#define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT 0xd
+#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT 0xe
+#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT 0xf
+#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x13
+#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L
+#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L
+#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L
+#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L
+#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000C0L
+#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x00000200L
+#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x00000400L
+#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x00000800L
+#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x00001000L
+#define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK 0x00002000L
+#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK 0x00004000L
+#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK 0x00078000L
+#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00080000L
+//VGT_LS_HS_CONFIG
+#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0
+#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
+#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe
+#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000FFL
+#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L
+#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000FC000L
+//VGT_GS_VERT_ITEMSIZE
+#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL
+//VGT_GS_VERT_ITEMSIZE_1
+#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007FFFL
+//VGT_GS_VERT_ITEMSIZE_2
+#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007FFFL
+//VGT_GS_VERT_ITEMSIZE_3
+#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007FFFL
+//VGT_TF_PARAM
+#define VGT_TF_PARAM__TYPE__SHIFT 0x0
+#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2
+#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5
+#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8
+#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9
+#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe
+#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf
+#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11
+#define VGT_TF_PARAM__TYPE_MASK 0x00000003L
+#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001CL
+#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000E0L
+#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x00000100L
+#define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L
+#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L
+#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00008000L
+#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L
+//DB_ALPHA_TO_MASK
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe
+#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000C00L
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000C000L
+#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L
+//VGT_DISPATCH_DRAW_INDEX
+#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0
+#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xFFFFFFFFL
+//PA_SU_POLY_OFFSET_DB_FMT_CNTL
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000FFL
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L
+//PA_SU_POLY_OFFSET_CLAMP
+#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xFFFFFFFFL
+//PA_SU_POLY_OFFSET_FRONT_SCALE
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xFFFFFFFFL
+//PA_SU_POLY_OFFSET_FRONT_OFFSET
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xFFFFFFFFL
+//PA_SU_POLY_OFFSET_BACK_SCALE
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xFFFFFFFFL
+//PA_SU_POLY_OFFSET_BACK_OFFSET
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xFFFFFFFFL
+//VGT_GS_INSTANCE_CNT
+#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0
+#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2
+#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L
+#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001FCL
+//VGT_STRMOUT_CONFIG
+#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0
+#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1
+#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2
+#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3
+#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4
+#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT 0x7
+#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8
+#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f
+#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L
+#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L
+#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L
+#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L
+#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L
+#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK 0x00000080L
+#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000F00L
+#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L
+//VGT_STRMOUT_BUFFER_CONFIG
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000FL
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000F0L
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000F00L
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000F000L
+//VGT_DMA_EVENT_INITIATOR
+#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
+#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa
+#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
+#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL
+#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L
+#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L
+//PA_SC_CENTROID_PRIORITY_0
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000FL
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000F0L
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000F00L
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000F000L
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000F0000L
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00F00000L
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0F000000L
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xF0000000L
+//PA_SC_CENTROID_PRIORITY_1
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000FL
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000F0L
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000F00L
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000F000L
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000F0000L
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00F00000L
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0F000000L
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xF0000000L
+//PA_SC_LINE_CNTL
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9
+#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
+#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb
+#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L
+#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L
+#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L
+#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L
+//PA_SC_AA_CONFIG
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0
+#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd
+#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14
+#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18
+#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT 0x1a
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L
+#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001E000L
+#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L
+#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L
+#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK 0x0C000000L
+//PA_SU_VTX_CNTL
+#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0
+#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1
+#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3
+#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L
+#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L
+#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L
+//PA_CL_GB_VERT_CLIP_ADJ
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_GB_VERT_DISC_ADJ
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_GB_HORZ_CLIP_ADJ
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_GB_HORZ_DISC_ADJ
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xF0000000L
+//PA_SC_AA_MASK_X0Y0_X1Y0
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000FFFFL
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xFFFF0000L
+//PA_SC_AA_MASK_X0Y1_X1Y1
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000FFFFL
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xFFFF0000L
+//PA_SC_SHADER_CONTROL
+#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0
+#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x2
+#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x3
+#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L
+#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L
+#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L
+//PA_SC_BINNER_CNTL_0
+#define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x0
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x2
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x3
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x4
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x7
+#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa
+#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0xd
+#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x12
+#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x13
+#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x1b
+#define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L
+#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L
+#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L
+#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L
+#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07F80000L
+#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L
+//PA_SC_BINNER_CNTL_1
+#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x0
+#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x10
+#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000FFFFL
+#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xFFFF0000L
+//PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x0
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x1
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x5
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x6
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0xb
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0xc
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0xd
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0xe
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT 0xf
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x10
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x12
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x13
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x14
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x15
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x16
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x17
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x18
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001EL
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003C0L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK 0x00008000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L
+//PA_SC_NGG_MODE_CNTL
+#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0
+#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL
+//VGT_VERTEX_REUSE_BLOCK_CNTL
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000FFL
+//VGT_OUT_DEALLOC_CNTL
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007FL
+//CB_COLOR0_BASE
+#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR0_BASE_EXT
+#define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR0_ATTRIB2
+#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR0_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR0_VIEW
+#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT 0x18
+#define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007FFL
+#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00FFE000L
+#define CB_COLOR0_VIEW__MIP_LEVEL_MASK 0x0F000000L
+//CB_COLOR0_INFO
+#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+//CB_COLOR0_ATTRIB
+#define CB_COLOR0_ATTRIB__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR0_ATTRIB__META_LINEAR__SHIFT 0xb
+#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR0_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
+#define CB_COLOR0_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
+#define CB_COLOR0_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
+#define CB_COLOR0_ATTRIB__RB_ALIGNED__SHIFT 0x1e
+#define CB_COLOR0_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
+#define CB_COLOR0_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
+#define CB_COLOR0_ATTRIB__META_LINEAR_MASK 0x00000800L
+#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR0_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
+#define CB_COLOR0_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
+#define CB_COLOR0_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
+#define CB_COLOR0_ATTRIB__RB_ALIGNED_MASK 0x40000000L
+#define CB_COLOR0_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
+//CB_COLOR0_DCC_CONTROL
+#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
+#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+//CB_COLOR0_CMASK
+#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR0_CMASK_BASE_EXT
+#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR0_FMASK
+#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR0_FMASK_BASE_EXT
+#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR0_CLEAR_WORD0
+#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR0_CLEAR_WORD1
+#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR0_DCC_BASE
+#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR0_DCC_BASE_EXT
+#define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR1_BASE
+#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR1_BASE_EXT
+#define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR1_ATTRIB2
+#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR1_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR1_VIEW
+#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT 0x18
+#define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007FFL
+#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00FFE000L
+#define CB_COLOR1_VIEW__MIP_LEVEL_MASK 0x0F000000L
+//CB_COLOR1_INFO
+#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+//CB_COLOR1_ATTRIB
+#define CB_COLOR1_ATTRIB__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR1_ATTRIB__META_LINEAR__SHIFT 0xb
+#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR1_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
+#define CB_COLOR1_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
+#define CB_COLOR1_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
+#define CB_COLOR1_ATTRIB__RB_ALIGNED__SHIFT 0x1e
+#define CB_COLOR1_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
+#define CB_COLOR1_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
+#define CB_COLOR1_ATTRIB__META_LINEAR_MASK 0x00000800L
+#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR1_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
+#define CB_COLOR1_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
+#define CB_COLOR1_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
+#define CB_COLOR1_ATTRIB__RB_ALIGNED_MASK 0x40000000L
+#define CB_COLOR1_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
+//CB_COLOR1_DCC_CONTROL
+#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
+#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+//CB_COLOR1_CMASK
+#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR1_CMASK_BASE_EXT
+#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR1_FMASK
+#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR1_FMASK_BASE_EXT
+#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR1_CLEAR_WORD0
+#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR1_CLEAR_WORD1
+#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR1_DCC_BASE
+#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR1_DCC_BASE_EXT
+#define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR2_BASE
+#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR2_BASE_EXT
+#define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR2_ATTRIB2
+#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR2_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR2_VIEW
+#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT 0x18
+#define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007FFL
+#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00FFE000L
+#define CB_COLOR2_VIEW__MIP_LEVEL_MASK 0x0F000000L
+//CB_COLOR2_INFO
+#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+//CB_COLOR2_ATTRIB
+#define CB_COLOR2_ATTRIB__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR2_ATTRIB__META_LINEAR__SHIFT 0xb
+#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR2_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
+#define CB_COLOR2_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
+#define CB_COLOR2_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
+#define CB_COLOR2_ATTRIB__RB_ALIGNED__SHIFT 0x1e
+#define CB_COLOR2_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
+#define CB_COLOR2_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
+#define CB_COLOR2_ATTRIB__META_LINEAR_MASK 0x00000800L
+#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR2_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
+#define CB_COLOR2_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
+#define CB_COLOR2_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
+#define CB_COLOR2_ATTRIB__RB_ALIGNED_MASK 0x40000000L
+#define CB_COLOR2_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
+//CB_COLOR2_DCC_CONTROL
+#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
+#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+//CB_COLOR2_CMASK
+#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR2_CMASK_BASE_EXT
+#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR2_FMASK
+#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR2_FMASK_BASE_EXT
+#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR2_CLEAR_WORD0
+#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR2_CLEAR_WORD1
+#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR2_DCC_BASE
+#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR2_DCC_BASE_EXT
+#define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR3_BASE
+#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR3_BASE_EXT
+#define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR3_ATTRIB2
+#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR3_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR3_VIEW
+#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT 0x18
+#define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007FFL
+#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00FFE000L
+#define CB_COLOR3_VIEW__MIP_LEVEL_MASK 0x0F000000L
+//CB_COLOR3_INFO
+#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+//CB_COLOR3_ATTRIB
+#define CB_COLOR3_ATTRIB__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR3_ATTRIB__META_LINEAR__SHIFT 0xb
+#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR3_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
+#define CB_COLOR3_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
+#define CB_COLOR3_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
+#define CB_COLOR3_ATTRIB__RB_ALIGNED__SHIFT 0x1e
+#define CB_COLOR3_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
+#define CB_COLOR3_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
+#define CB_COLOR3_ATTRIB__META_LINEAR_MASK 0x00000800L
+#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR3_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
+#define CB_COLOR3_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
+#define CB_COLOR3_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
+#define CB_COLOR3_ATTRIB__RB_ALIGNED_MASK 0x40000000L
+#define CB_COLOR3_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
+//CB_COLOR3_DCC_CONTROL
+#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
+#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+//CB_COLOR3_CMASK
+#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR3_CMASK_BASE_EXT
+#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR3_FMASK
+#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR3_FMASK_BASE_EXT
+#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR3_CLEAR_WORD0
+#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR3_CLEAR_WORD1
+#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR3_DCC_BASE
+#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR3_DCC_BASE_EXT
+#define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR4_BASE
+#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR4_BASE_EXT
+#define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR4_ATTRIB2
+#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR4_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR4_VIEW
+#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT 0x18
+#define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007FFL
+#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00FFE000L
+#define CB_COLOR4_VIEW__MIP_LEVEL_MASK 0x0F000000L
+//CB_COLOR4_INFO
+#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+//CB_COLOR4_ATTRIB
+#define CB_COLOR4_ATTRIB__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR4_ATTRIB__META_LINEAR__SHIFT 0xb
+#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR4_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
+#define CB_COLOR4_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
+#define CB_COLOR4_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
+#define CB_COLOR4_ATTRIB__RB_ALIGNED__SHIFT 0x1e
+#define CB_COLOR4_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
+#define CB_COLOR4_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
+#define CB_COLOR4_ATTRIB__META_LINEAR_MASK 0x00000800L
+#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR4_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
+#define CB_COLOR4_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
+#define CB_COLOR4_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
+#define CB_COLOR4_ATTRIB__RB_ALIGNED_MASK 0x40000000L
+#define CB_COLOR4_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
+//CB_COLOR4_DCC_CONTROL
+#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
+#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+//CB_COLOR4_CMASK
+#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR4_CMASK_BASE_EXT
+#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR4_FMASK
+#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR4_FMASK_BASE_EXT
+#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR4_CLEAR_WORD0
+#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR4_CLEAR_WORD1
+#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR4_DCC_BASE
+#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR4_DCC_BASE_EXT
+#define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR5_BASE
+#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR5_BASE_EXT
+#define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR5_ATTRIB2
+#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR5_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR5_VIEW
+#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT 0x18
+#define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007FFL
+#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00FFE000L
+#define CB_COLOR5_VIEW__MIP_LEVEL_MASK 0x0F000000L
+//CB_COLOR5_INFO
+#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+//CB_COLOR5_ATTRIB
+#define CB_COLOR5_ATTRIB__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR5_ATTRIB__META_LINEAR__SHIFT 0xb
+#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR5_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
+#define CB_COLOR5_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
+#define CB_COLOR5_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
+#define CB_COLOR5_ATTRIB__RB_ALIGNED__SHIFT 0x1e
+#define CB_COLOR5_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
+#define CB_COLOR5_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
+#define CB_COLOR5_ATTRIB__META_LINEAR_MASK 0x00000800L
+#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR5_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
+#define CB_COLOR5_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
+#define CB_COLOR5_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
+#define CB_COLOR5_ATTRIB__RB_ALIGNED_MASK 0x40000000L
+#define CB_COLOR5_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
+//CB_COLOR5_DCC_CONTROL
+#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
+#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+//CB_COLOR5_CMASK
+#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR5_CMASK_BASE_EXT
+#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR5_FMASK
+#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR5_FMASK_BASE_EXT
+#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR5_CLEAR_WORD0
+#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR5_CLEAR_WORD1
+#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR5_DCC_BASE
+#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR5_DCC_BASE_EXT
+#define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR6_BASE
+#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR6_BASE_EXT
+#define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR6_ATTRIB2
+#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR6_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR6_VIEW
+#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT 0x18
+#define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007FFL
+#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00FFE000L
+#define CB_COLOR6_VIEW__MIP_LEVEL_MASK 0x0F000000L
+//CB_COLOR6_INFO
+#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+//CB_COLOR6_ATTRIB
+#define CB_COLOR6_ATTRIB__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR6_ATTRIB__META_LINEAR__SHIFT 0xb
+#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR6_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
+#define CB_COLOR6_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
+#define CB_COLOR6_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
+#define CB_COLOR6_ATTRIB__RB_ALIGNED__SHIFT 0x1e
+#define CB_COLOR6_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
+#define CB_COLOR6_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
+#define CB_COLOR6_ATTRIB__META_LINEAR_MASK 0x00000800L
+#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR6_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
+#define CB_COLOR6_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
+#define CB_COLOR6_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
+#define CB_COLOR6_ATTRIB__RB_ALIGNED_MASK 0x40000000L
+#define CB_COLOR6_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
+//CB_COLOR6_DCC_CONTROL
+#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
+#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+//CB_COLOR6_CMASK
+#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR6_CMASK_BASE_EXT
+#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR6_FMASK
+#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR6_FMASK_BASE_EXT
+#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR6_CLEAR_WORD0
+#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR6_CLEAR_WORD1
+#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR6_DCC_BASE
+#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR6_DCC_BASE_EXT
+#define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR7_BASE
+#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR7_BASE_EXT
+#define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR7_ATTRIB2
+#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR7_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR7_VIEW
+#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT 0x18
+#define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007FFL
+#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00FFE000L
+#define CB_COLOR7_VIEW__MIP_LEVEL_MASK 0x0F000000L
+//CB_COLOR7_INFO
+#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+//CB_COLOR7_ATTRIB
+#define CB_COLOR7_ATTRIB__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR7_ATTRIB__META_LINEAR__SHIFT 0xb
+#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR7_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
+#define CB_COLOR7_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
+#define CB_COLOR7_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
+#define CB_COLOR7_ATTRIB__RB_ALIGNED__SHIFT 0x1e
+#define CB_COLOR7_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
+#define CB_COLOR7_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
+#define CB_COLOR7_ATTRIB__META_LINEAR_MASK 0x00000800L
+#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR7_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
+#define CB_COLOR7_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
+#define CB_COLOR7_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
+#define CB_COLOR7_ATTRIB__RB_ALIGNED_MASK 0x40000000L
+#define CB_COLOR7_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
+//CB_COLOR7_DCC_CONTROL
+#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
+#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+//CB_COLOR7_CMASK
+#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR7_CMASK_BASE_EXT
+#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR7_FMASK
+#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR7_FMASK_BASE_EXT
+#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR7_CLEAR_WORD0
+#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR7_CLEAR_WORD1
+#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR7_DCC_BASE
+#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR7_DCC_BASE_EXT
+#define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+
+
+// addressBlock: gc_gfxudec
+//CP_EOP_DONE_ADDR_LO
+#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
+#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL
+//CP_EOP_DONE_ADDR_HI
+#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_EOP_DONE_DATA_LO
+#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
+#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL
+//CP_EOP_DONE_DATA_HI
+#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
+#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL
+//CP_EOP_LAST_FENCE_LO
+#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
+#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xFFFFFFFFL
+//CP_EOP_LAST_FENCE_HI
+#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
+#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xFFFFFFFFL
+//CP_STREAM_OUT_ADDR_LO
+#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
+#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xFFFFFFFCL
+//CP_STREAM_OUT_ADDR_HI
+#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
+#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0x0000FFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT0_LO
+#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT0_HI
+#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT0_LO
+#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT0_HI
+#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT1_LO
+#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT1_HI
+#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT1_LO
+#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT1_HI
+#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT2_LO
+#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT2_HI
+#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT2_LO
+#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT2_HI
+#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT3_LO
+#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT3_HI
+#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT3_LO
+#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT3_HI
+#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xFFFFFFFFL
+//CP_PIPE_STATS_ADDR_LO
+#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2
+#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xFFFFFFFCL
+//CP_PIPE_STATS_ADDR_HI
+#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0
+#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000FFFFL
+//CP_VGT_IAVERT_COUNT_LO
+#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0
+#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_IAVERT_COUNT_HI
+#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0
+#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_VGT_IAPRIM_COUNT_LO
+#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0
+#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_IAPRIM_COUNT_HI
+#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0
+#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_VGT_GSPRIM_COUNT_LO
+#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0
+#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_GSPRIM_COUNT_HI
+#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0
+#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_VGT_VSINVOC_COUNT_LO
+#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_VSINVOC_COUNT_HI
+#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_VGT_GSINVOC_COUNT_LO
+#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_GSINVOC_COUNT_HI
+#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_VGT_HSINVOC_COUNT_LO
+#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_HSINVOC_COUNT_HI
+#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_VGT_DSINVOC_COUNT_LO
+#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_DSINVOC_COUNT_HI
+#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_PA_CINVOC_COUNT_LO
+#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0
+#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_PA_CINVOC_COUNT_HI
+#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0
+#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_PA_CPRIM_COUNT_LO
+#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0
+#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_PA_CPRIM_COUNT_HI
+#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0
+#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_SC_PSINVOC_COUNT0_LO
+#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xFFFFFFFFL
+//CP_SC_PSINVOC_COUNT0_HI
+#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xFFFFFFFFL
+//CP_SC_PSINVOC_COUNT1_LO
+#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xFFFFFFFFL
+//CP_SC_PSINVOC_COUNT1_HI
+#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xFFFFFFFFL
+//CP_VGT_CSINVOC_COUNT_LO
+#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_CSINVOC_COUNT_HI
+#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_PIPE_STATS_CONTROL
+#define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x19
+#define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x02000000L
+//CP_STREAM_OUT_CONTROL
+#define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT 0x19
+#define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK 0x02000000L
+//CP_STRMOUT_CNTL
+#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0
+#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L
+//SCRATCH_REG0
+#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
+#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL
+//SCRATCH_REG1
+#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
+#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL
+//SCRATCH_REG2
+#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
+#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL
+//SCRATCH_REG3
+#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
+#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL
+//SCRATCH_REG4
+#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
+#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL
+//SCRATCH_REG5
+#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
+#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL
+//SCRATCH_REG6
+#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
+#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL
+//SCRATCH_REG7
+#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
+#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL
+//CP_APPEND_DATA_HI
+#define CP_APPEND_DATA_HI__DATA__SHIFT 0x0
+#define CP_APPEND_DATA_HI__DATA_MASK 0xFFFFFFFFL
+//CP_APPEND_LAST_CS_FENCE_HI
+#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x0
+#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL
+//CP_APPEND_LAST_PS_FENCE_HI
+#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x0
+#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL
+//SCRATCH_UMSK
+#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0
+#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10
+#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000FFL
+#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L
+//SCRATCH_ADDR
+#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0
+#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xFFFFFFFFL
+//CP_PFP_ATOMIC_PREOP_LO
+#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
+#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_PFP_ATOMIC_PREOP_HI
+#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
+#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_PFP_GDS_ATOMIC0_PREOP_LO
+#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_PFP_GDS_ATOMIC0_PREOP_HI
+#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_PFP_GDS_ATOMIC1_PREOP_LO
+#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_PFP_GDS_ATOMIC1_PREOP_HI
+#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_APPEND_ADDR_LO
+#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2
+#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xFFFFFFFCL
+//CP_APPEND_ADDR_HI
+#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0
+#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10
+#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19
+#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d
+#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000FFFFL
+#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00010000L
+#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x02000000L
+#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xE0000000L
+//CP_APPEND_DATA_LO
+#define CP_APPEND_DATA_LO__DATA__SHIFT 0x0
+#define CP_APPEND_DATA_LO__DATA_MASK 0xFFFFFFFFL
+//CP_APPEND_LAST_CS_FENCE_LO
+#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x0
+#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL
+//CP_APPEND_LAST_PS_FENCE_LO
+#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x0
+#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL
+//CP_ATOMIC_PREOP_LO
+#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
+#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_ME_ATOMIC_PREOP_LO
+#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
+#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_ATOMIC_PREOP_HI
+#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
+#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_ME_ATOMIC_PREOP_HI
+#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
+#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_GDS_ATOMIC0_PREOP_LO
+#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_ME_GDS_ATOMIC0_PREOP_LO
+#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_GDS_ATOMIC0_PREOP_HI
+#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_ME_GDS_ATOMIC0_PREOP_HI
+#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_GDS_ATOMIC1_PREOP_LO
+#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_ME_GDS_ATOMIC1_PREOP_LO
+#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_GDS_ATOMIC1_PREOP_HI
+#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_ME_GDS_ATOMIC1_PREOP_HI
+#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_ME_MC_WADDR_LO
+#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2
+#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xFFFFFFFCL
+//CP_ME_MC_WADDR_HI
+#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0
+#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16
+#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000FFFFL
+#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00400000L
+//CP_ME_MC_WDATA_LO
+#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0
+#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xFFFFFFFFL
+//CP_ME_MC_WDATA_HI
+#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0
+#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xFFFFFFFFL
+//CP_ME_MC_RADDR_LO
+#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2
+#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xFFFFFFFCL
+//CP_ME_MC_RADDR_HI
+#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0
+#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16
+#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000FFFFL
+#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00400000L
+//CP_SEM_WAIT_TIMER
+#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0
+#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xFFFFFFFFL
+//CP_SIG_SEM_ADDR_LO
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L
+//CP_SIG_SEM_ADDR_HI
+#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
+#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
+#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
+#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
+#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
+#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL
+#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L
+#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L
+#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L
+#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L
+//CP_WAIT_REG_MEM_TIMEOUT
+#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0
+#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xFFFFFFFFL
+//CP_WAIT_SEM_ADDR_LO
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L
+//CP_WAIT_SEM_ADDR_HI
+#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
+#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
+#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
+#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
+#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
+#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL
+#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L
+#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L
+#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L
+#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L
+//CP_DMA_PFP_CONTROL
+#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
+#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
+#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
+#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
+#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d
+#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L
+#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L
+#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L
+#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L
+#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L
+//CP_DMA_ME_CONTROL
+#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
+#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
+#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
+#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
+#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d
+#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L
+#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L
+#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L
+#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L
+#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L
+//CP_COHER_BASE_HI
+#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
+#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL
+//CP_COHER_START_DELAY
+#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0
+#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003FL
+//CP_COHER_CNTL
+#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3
+#define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT 0x4
+#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT 0x5
+#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf
+#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
+#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16
+#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17
+#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19
+#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a
+#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b
+#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c
+#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d
+#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e
+#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x00000008L
+#define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK 0x00000010L
+#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK 0x00000020L
+#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L
+#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L
+#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L
+#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L
+#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L
+#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L
+#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L
+#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L
+#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L
+#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000L
+//CP_COHER_SIZE
+#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
+#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL
+//CP_COHER_BASE
+#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
+#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL
+//CP_COHER_STATUS
+#define CP_COHER_STATUS__MEID__SHIFT 0x18
+#define CP_COHER_STATUS__STATUS__SHIFT 0x1f
+#define CP_COHER_STATUS__MEID_MASK 0x03000000L
+#define CP_COHER_STATUS__STATUS_MASK 0x80000000L
+//CP_DMA_ME_SRC_ADDR
+#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0
+#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL
+//CP_DMA_ME_SRC_ADDR_HI
+#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
+#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL
+//CP_DMA_ME_DST_ADDR
+#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0
+#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL
+//CP_DMA_ME_DST_ADDR_HI
+#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
+#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL
+//CP_DMA_ME_COMMAND
+#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0
+#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a
+#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b
+#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c
+#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d
+#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e
+#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x1f
+#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL
+#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L
+#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L
+#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L
+#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L
+#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L
+#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L
+//CP_DMA_PFP_SRC_ADDR
+#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0
+#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL
+//CP_DMA_PFP_SRC_ADDR_HI
+#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
+#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL
+//CP_DMA_PFP_DST_ADDR
+#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0
+#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL
+//CP_DMA_PFP_DST_ADDR_HI
+#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
+#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL
+//CP_DMA_PFP_COMMAND
+#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0
+#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a
+#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b
+#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c
+#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d
+#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e
+#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x1f
+#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL
+#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L
+#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L
+#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L
+#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L
+#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L
+#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L
+//CP_DMA_CNTL
+#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x0
+#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4
+#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10
+#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c
+#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d
+#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e
+#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L
+#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L
+#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000F0000L
+#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L
+#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L
+#define CP_DMA_CNTL__PIO_COUNT_MASK 0xC0000000L
+//CP_DMA_READ_TAGS
+#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0
+#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c
+#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03FFFFFFL
+#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L
+//CP_COHER_SIZE_HI
+#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
+#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL
+//CP_PFP_IB_CONTROL
+#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0
+#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000FFL
+//CP_PFP_LOAD_CONTROL
+#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0
+#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1
+#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10
+#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18
+#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L
+#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L
+#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L
+#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L
+//CP_SCRATCH_INDEX
+#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
+#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000FFL
+//CP_SCRATCH_DATA
+#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
+#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL
+//CP_RB_OFFSET
+#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0
+#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL
+//CP_IB1_OFFSET
+#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
+#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL
+//CP_IB2_OFFSET
+#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
+#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL
+//CP_IB1_PREAMBLE_BEGIN
+#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0
+#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000FFFFFL
+//CP_IB1_PREAMBLE_END
+#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0
+#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000FFFFFL
+//CP_IB2_PREAMBLE_BEGIN
+#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0
+#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000FFFFFL
+//CP_IB2_PREAMBLE_END
+#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0
+#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000FFFFFL
+//CP_CE_IB1_OFFSET
+#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
+#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL
+//CP_CE_IB2_OFFSET
+#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
+#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL
+//CP_CE_COUNTER
+#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0
+#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL
+//CP_CE_RB_OFFSET
+#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0
+#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL
+//CP_CE_INIT_CMD_BUFSZ
+#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT 0x0
+#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK 0x00000FFFL
+//CP_CE_IB1_CMD_BUFSZ
+#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0
+#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL
+//CP_CE_IB2_CMD_BUFSZ
+#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0
+#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL
+//CP_IB1_CMD_BUFSZ
+#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0
+#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL
+//CP_IB2_CMD_BUFSZ
+#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0
+#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL
+//CP_ST_CMD_BUFSZ
+#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x0
+#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000FFFFFL
+//CP_CE_INIT_BASE_LO
+#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5
+#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xFFFFFFE0L
+//CP_CE_INIT_BASE_HI
+#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0
+#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x0000FFFFL
+//CP_CE_INIT_BUFSZ
+#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0
+#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000FFFL
+//CP_CE_IB1_BASE_LO
+#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
+#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL
+//CP_CE_IB1_BASE_HI
+#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
+#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL
+//CP_CE_IB1_BUFSZ
+#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
+#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL
+//CP_CE_IB2_BASE_LO
+#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
+#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL
+//CP_CE_IB2_BASE_HI
+#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
+#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL
+//CP_CE_IB2_BUFSZ
+#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
+#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL
+//CP_IB1_BASE_LO
+#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
+#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL
+//CP_IB1_BASE_HI
+#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
+#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL
+//CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
+#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL
+//CP_IB2_BASE_LO
+#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
+#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL
+//CP_IB2_BASE_HI
+#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
+#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL
+//CP_IB2_BUFSZ
+#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
+#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL
+//CP_ST_BASE_LO
+#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2
+#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xFFFFFFFCL
+//CP_ST_BASE_HI
+#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0
+#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000FFFFL
+//CP_ST_BUFSZ
+#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0
+#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000FFFFFL
+//CP_EOP_DONE_EVENT_CNTL
+#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0
+#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc
+#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x19
+#define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x1c
+#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x0000007FL
+#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x0003F000L
+#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x02000000L
+#define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L
+//CP_EOP_DONE_DATA_CNTL
+#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
+#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
+#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
+#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L
+#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L
+#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xE0000000L
+//CP_EOP_DONE_CNTX_ID
+#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0
+#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL
+//CP_PFP_COMPLETION_STATUS
+#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0
+#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L
+//CP_CE_COMPLETION_STATUS
+#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0
+#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x00000003L
+//CP_PRED_NOT_VISIBLE
+#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0
+#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L
+//CP_PFP_METADATA_BASE_ADDR
+#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
+//CP_PFP_METADATA_BASE_ADDR_HI
+#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_CE_METADATA_BASE_ADDR
+#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
+//CP_CE_METADATA_BASE_ADDR_HI
+#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_DRAW_INDX_INDR_ADDR
+#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
+//CP_DRAW_INDX_INDR_ADDR_HI
+#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_DISPATCH_INDR_ADDR
+#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
+//CP_DISPATCH_INDR_ADDR_HI
+#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_INDEX_BASE_ADDR
+#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
+//CP_INDEX_BASE_ADDR_HI
+#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_INDEX_TYPE
+#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
+#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
+//CP_GDS_BKUP_ADDR
+#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
+//CP_GDS_BKUP_ADDR_HI
+#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_SAMPLE_STATUS
+#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0
+#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1
+#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2
+#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3
+#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4
+#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5
+#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6
+#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7
+#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L
+#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L
+#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L
+#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L
+#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L
+#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L
+#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L
+#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L
+//CP_ME_COHER_CNTL
+#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0
+#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1
+#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6
+#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7
+#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8
+#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9
+#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
+#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb
+#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc
+#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd
+#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe
+#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13
+#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15
+#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L
+#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L
+#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L
+#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L
+#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L
+#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L
+#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L
+#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L
+#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L
+#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L
+#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L
+#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L
+#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L
+//CP_ME_COHER_SIZE
+#define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
+#define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL
+//CP_ME_COHER_SIZE_HI
+#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
+#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL
+//CP_ME_COHER_BASE
+#define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
+#define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL
+//CP_ME_COHER_BASE_HI
+#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
+#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL
+//CP_ME_COHER_STATUS
+#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0
+#define CP_ME_COHER_STATUS__STATUS__SHIFT 0x1f
+#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000FFL
+#define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L
+//RLC_GPM_PERF_COUNT_0
+#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0
+#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4
+#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8
+#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc
+#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10
+#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12
+#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14
+#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15
+#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000FL
+#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000F0L
+#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0x00000F00L
+#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0x0000F000L
+#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L
+#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000C0000L
+#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L
+#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xFFE00000L
+//RLC_GPM_PERF_COUNT_1
+#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0
+#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4
+#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8
+#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc
+#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10
+#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12
+#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14
+#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15
+#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000FL
+#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000F0L
+#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0x00000F00L
+#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0x0000F000L
+#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L
+#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000C0000L
+#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L
+#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xFFE00000L
+//GRBM_GFX_INDEX
+#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0
+#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8
+#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10
+#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d
+#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
+#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f
+#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000FFL
+#define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000FF00L
+#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00FF0000L
+#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L
+#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L
+#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L
+//VGT_GSVS_RING_SIZE
+#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0
+#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL
+//VGT_PRIMITIVE_TYPE
+#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
+#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL
+//VGT_INDEX_TYPE
+#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
+#define VGT_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8
+#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
+#define VGT_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L
+//VGT_STRMOUT_BUFFER_FILLED_SIZE_0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_BUFFER_FILLED_SIZE_1
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_BUFFER_FILLED_SIZE_2
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_BUFFER_FILLED_SIZE_3
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xFFFFFFFFL
+//VGT_MAX_VTX_INDX
+#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0
+#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL
+//VGT_MIN_VTX_INDX
+#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0
+#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL
+//VGT_INDX_OFFSET
+#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0
+#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL
+//VGT_MULTI_PRIM_IB_RESET_EN
+#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0
+#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1
+#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L
+#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L
+//VGT_NUM_INDICES
+#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0
+#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xFFFFFFFFL
+//VGT_NUM_INSTANCES
+#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
+#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL
+//VGT_TF_RING_SIZE
+#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0
+#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL
+//VGT_HS_OFFCHIP_PARAM
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000001FFL
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L
+//VGT_TF_MEMORY_BASE
+#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0
+#define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL
+//VGT_TF_MEMORY_BASE_HI
+#define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0
+#define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL
+//WD_POS_BUF_BASE
+#define WD_POS_BUF_BASE__BASE__SHIFT 0x0
+#define WD_POS_BUF_BASE__BASE_MASK 0xFFFFFFFFL
+//WD_POS_BUF_BASE_HI
+#define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT 0x0
+#define WD_POS_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL
+//WD_CNTL_SB_BUF_BASE
+#define WD_CNTL_SB_BUF_BASE__BASE__SHIFT 0x0
+#define WD_CNTL_SB_BUF_BASE__BASE_MASK 0xFFFFFFFFL
+//WD_CNTL_SB_BUF_BASE_HI
+#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT 0x0
+#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL
+//WD_INDEX_BUF_BASE
+#define WD_INDEX_BUF_BASE__BASE__SHIFT 0x0
+#define WD_INDEX_BUF_BASE__BASE_MASK 0xFFFFFFFFL
+//WD_INDEX_BUF_BASE_HI
+#define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT 0x0
+#define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL
+//IA_MULTI_VGT_PARAM
+#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0
+#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11
+#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13
+#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14
+#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC__SHIFT 0x15
+#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV__SHIFT 0x16
+#define IA_MULTI_VGT_PARAM__HW_USE_ONLY__SHIFT 0x17
+#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000FFFFL
+#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L
+#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L
+#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L
+#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK 0x00200000L
+#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK 0x00400000L
+#define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK 0x00800000L
+//VGT_OBJECT_ID
+#define VGT_OBJECT_ID__REG_OBJ_ID__SHIFT 0x0
+#define VGT_OBJECT_ID__REG_OBJ_ID_MASK 0xFFFFFFFFL
+//VGT_INSTANCE_BASE_ID
+#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0
+#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL
+//PA_SU_LINE_STIPPLE_VALUE
+#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0
+#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00FFFFFFL
+//PA_SC_LINE_STIPPLE_STATE
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000FL
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000FF00L
+//PA_SC_SCREEN_EXTENT_MIN_0
+#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10
+#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000FFFFL
+#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xFFFF0000L
+//PA_SC_SCREEN_EXTENT_MAX_0
+#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10
+#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000FFFFL
+#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xFFFF0000L
+//PA_SC_SCREEN_EXTENT_MIN_1
+#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10
+#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000FFFFL
+#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xFFFF0000L
+//PA_SC_SCREEN_EXTENT_MAX_1
+#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10
+#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000FFFFL
+#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xFFFF0000L
+//PA_SC_P3D_TRAP_SCREEN_HV_EN
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L
+//PA_SC_P3D_TRAP_SCREEN_H
+#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL
+//PA_SC_P3D_TRAP_SCREEN_V
+#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL
+//PA_SC_P3D_TRAP_SCREEN_OCCURRENCE
+#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL
+//PA_SC_P3D_TRAP_SCREEN_COUNT
+#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL
+//PA_SC_HP3D_TRAP_SCREEN_HV_EN
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L
+//PA_SC_HP3D_TRAP_SCREEN_H
+#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL
+//PA_SC_HP3D_TRAP_SCREEN_V
+#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL
+//PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE
+#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL
+//PA_SC_HP3D_TRAP_SCREEN_COUNT
+#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL
+//PA_SC_TRAP_SCREEN_HV_EN
+#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
+#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L
+#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L
+//PA_SC_TRAP_SCREEN_H
+#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL
+//PA_SC_TRAP_SCREEN_V
+#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL
+//PA_SC_TRAP_SCREEN_OCCURRENCE
+#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL
+//PA_SC_TRAP_SCREEN_COUNT
+#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL
+//SQ_THREAD_TRACE_BASE
+#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0
+#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_SIZE
+#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0
+#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x003FFFFFL
+//SQ_THREAD_TRACE_MASK
+#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0
+#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5
+#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7
+#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8
+#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc
+#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe
+#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf
+#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x0000001FL
+#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x00000020L
+#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x00000080L
+#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0x00000F00L
+#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x00003000L
+#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x00004000L
+#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x00008000L
+//SQ_THREAD_TRACE_TOKEN_MASK
+#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18
+#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0x0000FFFFL
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0x00FF0000L
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x01000000L
+//SQ_THREAD_TRACE_PERF_MASK
+#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0
+#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10
+#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0x0000FFFFL
+#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xFFFF0000L
+//SQ_THREAD_TRACE_CTRL
+#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f
+#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000L
+//SQ_THREAD_TRACE_MODE
+#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0
+#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3
+#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6
+#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9
+#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc
+#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf
+#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12
+#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15
+#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17
+#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19
+#define SQ_THREAD_TRACE_MODE__TC_PERF_EN__SHIFT 0x1a
+#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b
+#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d
+#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e
+#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f
+#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x00000007L
+#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x00000038L
+#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x000001C0L
+#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0x00000E00L
+#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x00007000L
+#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x00038000L
+#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x001C0000L
+#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x00600000L
+#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x01800000L
+#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x02000000L
+#define SQ_THREAD_TRACE_MODE__TC_PERF_EN_MASK 0x04000000L
+#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000L
+#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000L
+#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000L
+#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000L
+//SQ_THREAD_TRACE_BASE2
+#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0x0000000FL
+//SQ_THREAD_TRACE_TOKEN_MASK2
+#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0
+#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_WPTR
+#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0
+#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e
+#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3FFFFFFFL
+#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xC0000000L
+//SQ_THREAD_TRACE_STATUS
+#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0
+#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10
+#define SQ_THREAD_TRACE_STATUS__UTC_ERROR__SHIFT 0x1c
+#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d
+#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e
+#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f
+#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x000003FFL
+#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x03FF0000L
+#define SQ_THREAD_TRACE_STATUS__UTC_ERROR_MASK 0x10000000L
+#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000L
+#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000L
+#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000L
+//SQ_THREAD_TRACE_HIWATER
+#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0
+#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x00000007L
+//SQ_THREAD_TRACE_CNTR
+#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0
+#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_USERDATA_0
+#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_USERDATA_1
+#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_USERDATA_2
+#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_USERDATA_3
+#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xFFFFFFFFL
+//SQC_CACHES
+#define SQC_CACHES__TARGET_INST__SHIFT 0x0
+#define SQC_CACHES__TARGET_DATA__SHIFT 0x1
+#define SQC_CACHES__INVALIDATE__SHIFT 0x2
+#define SQC_CACHES__WRITEBACK__SHIFT 0x3
+#define SQC_CACHES__VOL__SHIFT 0x4
+#define SQC_CACHES__COMPLETE__SHIFT 0x10
+#define SQC_CACHES__TARGET_INST_MASK 0x00000001L
+#define SQC_CACHES__TARGET_DATA_MASK 0x00000002L
+#define SQC_CACHES__INVALIDATE_MASK 0x00000004L
+#define SQC_CACHES__WRITEBACK_MASK 0x00000008L
+#define SQC_CACHES__VOL_MASK 0x00000010L
+#define SQC_CACHES__COMPLETE_MASK 0x00010000L
+//SQC_WRITEBACK
+#define SQC_WRITEBACK__DWB__SHIFT 0x0
+#define SQC_WRITEBACK__DIRTY__SHIFT 0x1
+#define SQC_WRITEBACK__DWB_MASK 0x00000001L
+#define SQC_WRITEBACK__DIRTY_MASK 0x00000002L
+//TA_CS_BC_BASE_ADDR
+#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
+#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL
+//TA_CS_BC_BASE_ADDR_HI
+#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
+#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL
+//TA_GRAD_ADJ_UCONFIG
+#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_0__SHIFT 0x0
+#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_1__SHIFT 0x8
+#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_2__SHIFT 0x10
+#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_3__SHIFT 0x18
+#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_0_MASK 0x000000FFL
+#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_1_MASK 0x0000FF00L
+#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_2_MASK 0x00FF0000L
+#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_3_MASK 0xFF000000L
+//DB_OCCLUSION_COUNT0_LOW
+#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
+//DB_OCCLUSION_COUNT0_HI
+#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0
+#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7FFFFFFFL
+//DB_OCCLUSION_COUNT1_LOW
+#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
+//DB_OCCLUSION_COUNT1_HI
+#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0
+#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7FFFFFFFL
+//DB_OCCLUSION_COUNT2_LOW
+#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
+//DB_OCCLUSION_COUNT2_HI
+#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0
+#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7FFFFFFFL
+//DB_OCCLUSION_COUNT3_LOW
+#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
+//DB_OCCLUSION_COUNT3_HI
+#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0
+#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7FFFFFFFL
+//DB_ZPASS_COUNT_LOW
+#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
+//DB_ZPASS_COUNT_HI
+#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0
+#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7FFFFFFFL
+//GDS_RD_ADDR
+#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0
+#define GDS_RD_ADDR__READ_ADDR_MASK 0xFFFFFFFFL
+//GDS_RD_DATA
+#define GDS_RD_DATA__READ_DATA__SHIFT 0x0
+#define GDS_RD_DATA__READ_DATA_MASK 0xFFFFFFFFL
+//GDS_RD_BURST_ADDR
+#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0
+#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xFFFFFFFFL
+//GDS_RD_BURST_COUNT
+#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0
+#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xFFFFFFFFL
+//GDS_RD_BURST_DATA
+#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0
+#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xFFFFFFFFL
+//GDS_WR_ADDR
+#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0
+#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL
+//GDS_WR_DATA
+#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0
+#define GDS_WR_DATA__WRITE_DATA_MASK 0xFFFFFFFFL
+//GDS_WR_BURST_ADDR
+#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0
+#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL
+//GDS_WR_BURST_DATA
+#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0
+#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xFFFFFFFFL
+//GDS_WRITE_COMPLETE
+#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0
+#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xFFFFFFFFL
+//GDS_ATOM_CNTL
+#define GDS_ATOM_CNTL__AINC__SHIFT 0x0
+#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6
+#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8
+#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa
+#define GDS_ATOM_CNTL__AINC_MASK 0x0000003FL
+#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000C0L
+#define GDS_ATOM_CNTL__DMODE_MASK 0x00000300L
+#define GDS_ATOM_CNTL__UNUSED2_MASK 0xFFFFFC00L
+//GDS_ATOM_COMPLETE
+#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0
+#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1
+#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L
+#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xFFFFFFFEL
+//GDS_ATOM_BASE
+#define GDS_ATOM_BASE__BASE__SHIFT 0x0
+#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10
+#define GDS_ATOM_BASE__BASE_MASK 0x0000FFFFL
+#define GDS_ATOM_BASE__UNUSED_MASK 0xFFFF0000L
+//GDS_ATOM_SIZE
+#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0
+#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10
+#define GDS_ATOM_SIZE__SIZE_MASK 0x0000FFFFL
+#define GDS_ATOM_SIZE__UNUSED_MASK 0xFFFF0000L
+//GDS_ATOM_OFFSET0
+#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0
+#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8
+#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000FFL
+#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xFFFFFF00L
+//GDS_ATOM_OFFSET1
+#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0
+#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8
+#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000FFL
+#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xFFFFFF00L
+//GDS_ATOM_DST
+#define GDS_ATOM_DST__DST__SHIFT 0x0
+#define GDS_ATOM_DST__DST_MASK 0xFFFFFFFFL
+//GDS_ATOM_OP
+#define GDS_ATOM_OP__OP__SHIFT 0x0
+#define GDS_ATOM_OP__UNUSED__SHIFT 0x8
+#define GDS_ATOM_OP__OP_MASK 0x000000FFL
+#define GDS_ATOM_OP__UNUSED_MASK 0xFFFFFF00L
+//GDS_ATOM_SRC0
+#define GDS_ATOM_SRC0__DATA__SHIFT 0x0
+#define GDS_ATOM_SRC0__DATA_MASK 0xFFFFFFFFL
+//GDS_ATOM_SRC0_U
+#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0
+#define GDS_ATOM_SRC0_U__DATA_MASK 0xFFFFFFFFL
+//GDS_ATOM_SRC1
+#define GDS_ATOM_SRC1__DATA__SHIFT 0x0
+#define GDS_ATOM_SRC1__DATA_MASK 0xFFFFFFFFL
+//GDS_ATOM_SRC1_U
+#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0
+#define GDS_ATOM_SRC1_U__DATA_MASK 0xFFFFFFFFL
+//GDS_ATOM_READ0
+#define GDS_ATOM_READ0__DATA__SHIFT 0x0
+#define GDS_ATOM_READ0__DATA_MASK 0xFFFFFFFFL
+//GDS_ATOM_READ0_U
+#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0
+#define GDS_ATOM_READ0_U__DATA_MASK 0xFFFFFFFFL
+//GDS_ATOM_READ1
+#define GDS_ATOM_READ1__DATA__SHIFT 0x0
+#define GDS_ATOM_READ1__DATA_MASK 0xFFFFFFFFL
+//GDS_ATOM_READ1_U
+#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0
+#define GDS_ATOM_READ1_U__DATA_MASK 0xFFFFFFFFL
+//GDS_GWS_RESOURCE_CNTL
+#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0
+#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6
+#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003FL
+#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xFFFFFFC0L
+//GDS_GWS_RESOURCE
+#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0
+#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1
+#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd
+#define GDS_GWS_RESOURCE__DED__SHIFT 0xe
+#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf
+#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10
+#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1c
+#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1d
+#define GDS_GWS_RESOURCE__HALTED__SHIFT 0x1e
+#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1f
+#define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L
+#define GDS_GWS_RESOURCE__COUNTER_MASK 0x00001FFEL
+#define GDS_GWS_RESOURCE__TYPE_MASK 0x00002000L
+#define GDS_GWS_RESOURCE__DED_MASK 0x00004000L
+#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00008000L
+#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x0FFF0000L
+#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x10000000L
+#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x20000000L
+#define GDS_GWS_RESOURCE__HALTED_MASK 0x40000000L
+#define GDS_GWS_RESOURCE__UNUSED1_MASK 0x80000000L
+//GDS_GWS_RESOURCE_CNT
+#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0
+#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10
+#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000FFFFL
+#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_CNTL
+#define GDS_OA_CNTL__INDEX__SHIFT 0x0
+#define GDS_OA_CNTL__UNUSED__SHIFT 0x4
+#define GDS_OA_CNTL__INDEX_MASK 0x0000000FL
+#define GDS_OA_CNTL__UNUSED_MASK 0xFFFFFFF0L
+//GDS_OA_COUNTER
+#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0
+#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xFFFFFFFFL
+//GDS_OA_ADDRESS
+#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0
+#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10
+#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14
+#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16
+#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e
+#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f
+#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0x0000FFFFL
+#define GDS_OA_ADDRESS__CRAWLER_MASK 0x000F0000L
+#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x00300000L
+#define GDS_OA_ADDRESS__UNUSED_MASK 0x3FC00000L
+#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000L
+#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000L
+//GDS_OA_INCDEC
+#define GDS_OA_INCDEC__VALUE__SHIFT 0x0
+#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f
+#define GDS_OA_INCDEC__VALUE_MASK 0x7FFFFFFFL
+#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000L
+//GDS_OA_RING_SIZE
+#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0
+#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xFFFFFFFFL
+//SPI_CONFIG_CNTL
+#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0
+#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15
+#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18
+#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19
+#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a
+#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b
+#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c
+#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d
+#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e
+#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL
+#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L
+#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L
+#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L
+#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L
+#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L
+#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L
+#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L
+#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L
+//SPI_CONFIG_CNTL_1
+#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0
+#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4
+#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE__SHIFT 0x5
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7
+#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa
+#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe
+#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10
+#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL
+#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L
+#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE_MASK 0x00000020L
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L
+#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L
+#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L
+#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xFFFF0000L
+//SPI_CONFIG_CNTL_2
+#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0
+#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4
+#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL
+#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L
+
+
+// addressBlock: gc_perfddec
+//CPG_PERFCOUNTER1_LO
+#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CPG_PERFCOUNTER1_HI
+#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CPG_PERFCOUNTER0_LO
+#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CPG_PERFCOUNTER0_HI
+#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CPC_PERFCOUNTER1_LO
+#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CPC_PERFCOUNTER1_HI
+#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CPC_PERFCOUNTER0_LO
+#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CPC_PERFCOUNTER0_HI
+#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CPF_PERFCOUNTER1_LO
+#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CPF_PERFCOUNTER1_HI
+#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CPF_PERFCOUNTER0_LO
+#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CPF_PERFCOUNTER0_HI
+#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CPF_LATENCY_STATS_DATA
+#define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x0
+#define CPF_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL
+//CPG_LATENCY_STATS_DATA
+#define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x0
+#define CPG_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL
+//CPC_LATENCY_STATS_DATA
+#define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x0
+#define CPC_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL
+//GRBM_PERFCOUNTER0_LO
+#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GRBM_PERFCOUNTER0_HI
+#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GRBM_PERFCOUNTER1_LO
+#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GRBM_PERFCOUNTER1_HI
+#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GRBM_SE0_PERFCOUNTER_LO
+#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GRBM_SE0_PERFCOUNTER_HI
+#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GRBM_SE1_PERFCOUNTER_LO
+#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GRBM_SE1_PERFCOUNTER_HI
+#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GRBM_SE2_PERFCOUNTER_LO
+#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GRBM_SE2_PERFCOUNTER_HI
+#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GRBM_SE3_PERFCOUNTER_LO
+#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GRBM_SE3_PERFCOUNTER_HI
+#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//WD_PERFCOUNTER0_LO
+#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//WD_PERFCOUNTER0_HI
+#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//WD_PERFCOUNTER1_LO
+#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//WD_PERFCOUNTER1_HI
+#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//WD_PERFCOUNTER2_LO
+#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//WD_PERFCOUNTER2_HI
+#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//WD_PERFCOUNTER3_LO
+#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//WD_PERFCOUNTER3_HI
+#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//IA_PERFCOUNTER0_LO
+#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//IA_PERFCOUNTER0_HI
+#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//IA_PERFCOUNTER1_LO
+#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//IA_PERFCOUNTER1_HI
+#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//IA_PERFCOUNTER2_LO
+#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//IA_PERFCOUNTER2_HI
+#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//IA_PERFCOUNTER3_LO
+#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//IA_PERFCOUNTER3_HI
+#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//VGT_PERFCOUNTER0_LO
+#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//VGT_PERFCOUNTER0_HI
+#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//VGT_PERFCOUNTER1_LO
+#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//VGT_PERFCOUNTER1_HI
+#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//VGT_PERFCOUNTER2_LO
+#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//VGT_PERFCOUNTER2_HI
+#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//VGT_PERFCOUNTER3_LO
+#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//VGT_PERFCOUNTER3_HI
+#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SU_PERFCOUNTER0_LO
+#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SU_PERFCOUNTER0_HI
+#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
+//PA_SU_PERFCOUNTER1_LO
+#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SU_PERFCOUNTER1_HI
+#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
+//PA_SU_PERFCOUNTER2_LO
+#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SU_PERFCOUNTER2_HI
+#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
+//PA_SU_PERFCOUNTER3_LO
+#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SU_PERFCOUNTER3_HI
+#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
+//PA_SC_PERFCOUNTER0_LO
+#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER0_HI
+#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER1_LO
+#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER1_HI
+#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER2_LO
+#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER2_HI
+#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER3_LO
+#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER3_HI
+#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER4_LO
+#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER4_HI
+#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER5_LO
+#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER5_HI
+#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER6_LO
+#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER6_HI
+#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER7_LO
+#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER7_HI
+#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER0_HI
+#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER0_LO
+#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER1_HI
+#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER1_LO
+#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER2_HI
+#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER2_LO
+#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER3_HI
+#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER3_LO
+#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER4_HI
+#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER4_LO
+#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER5_HI
+#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER5_LO
+#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER0_LO
+#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER0_HI
+#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER1_LO
+#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER1_HI
+#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER2_LO
+#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER2_HI
+#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER3_LO
+#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER3_HI
+#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER4_LO
+#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER4_HI
+#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER5_LO
+#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER5_HI
+#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER6_LO
+#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER6_HI
+#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER7_LO
+#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER7_HI
+#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER8_LO
+#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER8_HI
+#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER9_LO
+#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER9_HI
+#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER10_LO
+#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER10_HI
+#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER11_LO
+#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER11_HI
+#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER12_LO
+#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER12_HI
+#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER13_LO
+#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER13_HI
+#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER14_LO
+#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER14_HI
+#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER15_LO
+#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER15_HI
+#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER0_LO
+#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER0_HI
+#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER1_LO
+#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER1_HI
+#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER2_LO
+#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER2_HI
+#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER3_LO
+#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER3_HI
+#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER0_LO
+#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER0_HI
+#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER1_LO
+#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER1_HI
+#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER2_LO
+#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER2_HI
+#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER3_LO
+#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER3_HI
+#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TA_PERFCOUNTER0_LO
+#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TA_PERFCOUNTER0_HI
+#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TA_PERFCOUNTER1_LO
+#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TA_PERFCOUNTER1_HI
+#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TD_PERFCOUNTER0_LO
+#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TD_PERFCOUNTER0_HI
+#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TD_PERFCOUNTER1_LO
+#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TD_PERFCOUNTER1_HI
+#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER0_LO
+#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER0_HI
+#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER1_LO
+#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER1_HI
+#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER2_LO
+#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER2_HI
+#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER3_LO
+#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER3_HI
+#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCC_PERFCOUNTER0_LO
+#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCC_PERFCOUNTER0_HI
+#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCC_PERFCOUNTER1_LO
+#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCC_PERFCOUNTER1_HI
+#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCC_PERFCOUNTER2_LO
+#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCC_PERFCOUNTER2_HI
+#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCC_PERFCOUNTER3_LO
+#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCC_PERFCOUNTER3_HI
+#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCA_PERFCOUNTER0_LO
+#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCA_PERFCOUNTER0_HI
+#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCA_PERFCOUNTER1_LO
+#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCA_PERFCOUNTER1_HI
+#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCA_PERFCOUNTER2_LO
+#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCA_PERFCOUNTER2_HI
+#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCA_PERFCOUNTER3_LO
+#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCA_PERFCOUNTER3_HI
+#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER0_LO
+#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER0_HI
+#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER1_LO
+#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER1_HI
+#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER2_LO
+#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER2_HI
+#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER3_LO
+#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER3_HI
+#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER0_LO
+#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER0_HI
+#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER1_LO
+#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER1_HI
+#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER2_LO
+#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER2_HI
+#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER3_LO
+#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER3_HI
+#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//RLC_PERFCOUNTER0_LO
+#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//RLC_PERFCOUNTER0_HI
+#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//RLC_PERFCOUNTER1_LO
+#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//RLC_PERFCOUNTER1_HI
+#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER0_LO
+#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER0_HI
+#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER1_LO
+#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER1_HI
+#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER2_LO
+#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER2_HI
+#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER3_LO
+#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER3_HI
+#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_utcl2_atcl2pfcntrdec
+//ATC_L2_PERFCOUNTER_LO
+#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//ATC_L2_PERFCOUNTER_HI
+#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+
+
+// addressBlock: gc_utcl2_vml2prdec
+//MC_VM_L2_PERFCOUNTER_LO
+#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MC_VM_L2_PERFCOUNTER_HI
+#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+
+
+// addressBlock: gc_perfsdec
+//CPG_PERFCOUNTER1_SELECT
+#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0
+#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
+#define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
+#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18
+#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c
+#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL
+#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L
+#define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
+#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L
+#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L
+//CPG_PERFCOUNTER0_SELECT1
+#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0
+#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
+#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18
+#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c
+#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL
+#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L
+#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L
+#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L
+//CPG_PERFCOUNTER0_SELECT
+#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0
+#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
+#define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
+#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18
+#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c
+#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL
+#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L
+#define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
+#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L
+#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L
+//CPC_PERFCOUNTER1_SELECT
+#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0
+#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
+#define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
+#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18
+#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c
+#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL
+#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L
+#define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
+#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L
+#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L
+//CPC_PERFCOUNTER0_SELECT1
+#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0
+#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
+#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18
+#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c
+#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL
+#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L
+#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L
+#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L
+//CPF_PERFCOUNTER1_SELECT
+#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0
+#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
+#define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
+#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18
+#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c
+#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL
+#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L
+#define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
+#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L
+#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L
+//CPF_PERFCOUNTER0_SELECT1
+#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0
+#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
+#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18
+#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c
+#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL
+#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L
+#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L
+#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L
+//CPF_PERFCOUNTER0_SELECT
+#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0
+#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
+#define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
+#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18
+#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c
+#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL
+#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L
+#define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
+#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L
+#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L
+//CP_PERFMON_CNTL
+#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
+#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
+#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL
+#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L
+#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
+//CPC_PERFCOUNTER0_SELECT
+#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0
+#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
+#define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
+#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18
+#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c
+#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL
+#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L
+#define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
+#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L
+#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L
+//CPF_TC_PERF_COUNTER_WINDOW_SELECT
+#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0
+#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e
+#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f
+#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L
+#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L
+#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L
+//CPG_TC_PERF_COUNTER_WINDOW_SELECT
+#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0
+#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e
+#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f
+#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL
+#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L
+#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L
+//CPF_LATENCY_STATS_SELECT
+#define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0
+#define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e
+#define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f
+#define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL
+#define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L
+#define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L
+//CPG_LATENCY_STATS_SELECT
+#define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0
+#define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e
+#define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f
+#define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL
+#define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L
+#define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L
+//CPC_LATENCY_STATS_SELECT
+#define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0
+#define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e
+#define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f
+#define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x00000007L
+#define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L
+#define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L
+//CP_DRAW_OBJECT
+#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
+#define CP_DRAW_OBJECT__OBJECT_MASK 0xFFFFFFFFL
+//CP_DRAW_OBJECT_COUNTER
+#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
+#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000FFFFL
+//CP_DRAW_WINDOW_MASK_HI
+#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
+#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xFFFFFFFFL
+//CP_DRAW_WINDOW_HI
+#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
+#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xFFFFFFFFL
+//CP_DRAW_WINDOW_LO
+#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
+#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
+#define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000FFFFL
+#define CP_DRAW_WINDOW_LO__MAX_MASK 0xFFFF0000L
+//CP_DRAW_WINDOW_CNTL
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
+#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L
+#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L
+//GRBM_PERFCOUNTER0_SELECT
+#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
+#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
+#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
+#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
+#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
+#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
+#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
+#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d
+#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e
+#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f
+#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL
+#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
+#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
+#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
+#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
+#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L
+#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
+#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
+#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
+#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
+#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
+#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
+#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
+#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L
+#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
+#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
+#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L
+#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L
+#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L
+#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L
+#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L
+#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L
+//GRBM_PERFCOUNTER1_SELECT
+#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
+#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
+#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
+#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
+#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
+#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
+#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
+#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d
+#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e
+#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f
+#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL
+#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
+#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
+#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
+#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
+#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L
+#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
+#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
+#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
+#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
+#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
+#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
+#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
+#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L
+#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
+#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
+#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L
+#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L
+#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L
+#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L
+#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L
+#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L
+//GRBM_SE0_PERFCOUNTER_SELECT
+#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
+#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
+//GRBM_SE1_PERFCOUNTER_SELECT
+#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
+#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
+//GRBM_SE2_PERFCOUNTER_SELECT
+#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
+#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
+//GRBM_SE3_PERFCOUNTER_SELECT
+#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
+#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
+//WD_PERFCOUNTER0_SELECT
+#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL
+#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//WD_PERFCOUNTER1_SELECT
+#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
+#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//WD_PERFCOUNTER2_SELECT
+#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL
+#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//WD_PERFCOUNTER3_SELECT
+#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL
+#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//IA_PERFCOUNTER0_SELECT
+#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//IA_PERFCOUNTER1_SELECT
+#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
+#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//IA_PERFCOUNTER2_SELECT
+#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL
+#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//IA_PERFCOUNTER3_SELECT
+#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL
+#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//IA_PERFCOUNTER0_SELECT1
+#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//VGT_PERFCOUNTER0_SELECT
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//VGT_PERFCOUNTER1_SELECT
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//VGT_PERFCOUNTER2_SELECT
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL
+#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//VGT_PERFCOUNTER3_SELECT
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL
+#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//VGT_PERFCOUNTER0_SELECT1
+#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//VGT_PERFCOUNTER1_SELECT1
+#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//VGT_PERFCOUNTER_SEID_MASK
+#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0
+#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0x000000FFL
+//PA_SU_PERFCOUNTER0_SELECT
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+//PA_SU_PERFCOUNTER0_SELECT1
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+//PA_SU_PERFCOUNTER1_SELECT
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+//PA_SU_PERFCOUNTER1_SELECT1
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+//PA_SU_PERFCOUNTER2_SELECT
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+//PA_SU_PERFCOUNTER3_SELECT
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+//PA_SC_PERFCOUNTER0_SELECT
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+//PA_SC_PERFCOUNTER0_SELECT1
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+//PA_SC_PERFCOUNTER1_SELECT
+#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_SC_PERFCOUNTER2_SELECT
+#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_SC_PERFCOUNTER3_SELECT
+#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_SC_PERFCOUNTER4_SELECT
+#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_SC_PERFCOUNTER5_SELECT
+#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_SC_PERFCOUNTER6_SELECT
+#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_SC_PERFCOUNTER7_SELECT
+#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL
+//SPI_PERFCOUNTER0_SELECT
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//SPI_PERFCOUNTER1_SELECT
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//SPI_PERFCOUNTER2_SELECT
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
+#define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//SPI_PERFCOUNTER3_SELECT
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
+#define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//SPI_PERFCOUNTER0_SELECT1
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//SPI_PERFCOUNTER1_SELECT1
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//SPI_PERFCOUNTER2_SELECT1
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18
+#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//SPI_PERFCOUNTER3_SELECT1
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18
+#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//SPI_PERFCOUNTER4_SELECT
+#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000000FFL
+//SPI_PERFCOUNTER5_SELECT
+#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000000FFL
+//SPI_PERFCOUNTER_BINS
+#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0
+#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4
+#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8
+#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc
+#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10
+#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14
+#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18
+#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c
+#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000FL
+#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000F0L
+#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000F00L
+#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000F000L
+#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000F0000L
+#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00F00000L
+#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0F000000L
+#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xF0000000L
+//SQ_PERFCOUNTER0_SELECT
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER1_SELECT
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER2_SELECT
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER3_SELECT
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER4_SELECT
+#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER5_SELECT
+#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER6_SELECT
+#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER7_SELECT
+#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER8_SELECT
+#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER9_SELECT
+#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER10_SELECT
+#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER11_SELECT
+#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER12_SELECT
+#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER13_SELECT
+#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER14_SELECT
+#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER15_SELECT
+#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER_CTRL
+#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0
+#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1
+#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2
+#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3
+#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4
+#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5
+#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6
+#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8
+#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd
+#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L
+#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L
+#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L
+#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L
+#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L
+#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L
+#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L
+#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00001F00L
+#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L
+//SQ_PERFCOUNTER_MASK
+#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0
+#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0x0000FFFFL
+#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xFFFF0000L
+//SQ_PERFCOUNTER_CTRL2
+#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0
+#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L
+//SX_PERFCOUNTER0_SELECT
+#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
+#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
+#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+//SX_PERFCOUNTER1_SELECT
+#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
+#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
+#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+//SX_PERFCOUNTER2_SELECT
+#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
+#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
+#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+//SX_PERFCOUNTER3_SELECT
+#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
+#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
+#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+//SX_PERFCOUNTER0_SELECT1
+#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
+#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
+#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL
+#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L
+//SX_PERFCOUNTER1_SELECT1
+#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
+#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
+#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL
+#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L
+//GDS_PERFCOUNTER0_SELECT
+#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
+#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
+#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+//GDS_PERFCOUNTER1_SELECT
+#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
+#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
+#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+//GDS_PERFCOUNTER2_SELECT
+#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
+#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
+#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+//GDS_PERFCOUNTER3_SELECT
+#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
+#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
+#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+//GDS_PERFCOUNTER0_SELECT1
+#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
+#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
+#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL
+#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L
+//TA_PERFCOUNTER0_SELECT
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L
+#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//TA_PERFCOUNTER0_SELECT1
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//TA_PERFCOUNTER1_SELECT
+#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
+#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003FC00L
+#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//TD_PERFCOUNTER0_SELECT
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L
+#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//TD_PERFCOUNTER0_SELECT1
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//TD_PERFCOUNTER1_SELECT
+#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
+#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003FC00L
+#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCP_PERFCOUNTER0_SELECT
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCP_PERFCOUNTER0_SELECT1
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//TCP_PERFCOUNTER1_SELECT
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCP_PERFCOUNTER1_SELECT1
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//TCP_PERFCOUNTER2_SELECT
+#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCP_PERFCOUNTER3_SELECT
+#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCC_PERFCOUNTER0_SELECT
+#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCC_PERFCOUNTER0_SELECT1
+#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
+#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L
+#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L
+//TCC_PERFCOUNTER1_SELECT
+#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCC_PERFCOUNTER1_SELECT1
+#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
+#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L
+#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L
+//TCC_PERFCOUNTER2_SELECT
+#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCC_PERFCOUNTER3_SELECT
+#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCA_PERFCOUNTER0_SELECT
+#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCA_PERFCOUNTER0_SELECT1
+#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
+#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L
+#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L
+//TCA_PERFCOUNTER1_SELECT
+#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCA_PERFCOUNTER1_SELECT1
+#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
+#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L
+#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L
+//TCA_PERFCOUNTER2_SELECT
+#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCA_PERFCOUNTER3_SELECT
+#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//CB_PERFCOUNTER_FILTER
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000EL
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003E0L
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000E000L
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001C0000L
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00C00000L
+//CB_PERFCOUNTER0_SELECT
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L
+#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//CB_PERFCOUNTER0_SELECT1
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//CB_PERFCOUNTER1_SELECT
+#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
+#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//CB_PERFCOUNTER2_SELECT
+#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL
+#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//CB_PERFCOUNTER3_SELECT
+#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL
+#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//DB_PERFCOUNTER0_SELECT
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//DB_PERFCOUNTER0_SELECT1
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//DB_PERFCOUNTER1_SELECT
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//DB_PERFCOUNTER1_SELECT1
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//DB_PERFCOUNTER2_SELECT
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//DB_PERFCOUNTER3_SELECT
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//RLC_SPM_PERFMON_CNTL
+#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0
+#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc
+#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe
+#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10
+#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0x00000FFFL
+#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L
+#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x0000C000L
+#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xFFFF0000L
+//RLC_SPM_PERFMON_RING_BASE_LO
+#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0
+#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xFFFFFFFFL
+//RLC_SPM_PERFMON_RING_BASE_HI
+#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0
+#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10
+#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x0000FFFFL
+#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xFFFF0000L
+//RLC_SPM_PERFMON_RING_SIZE
+#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0
+#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xFFFFFFFFL
+//RLC_SPM_PERFMON_SEGMENT_SIZE
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x00000700L
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000F800L
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x001F0000L
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x03E00000L
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7C000000L
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000L
+//RLC_SPM_SE_MUXSEL_ADDR
+#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
+#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL
+//RLC_SPM_SE_MUXSEL_DATA
+#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
+#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL
+//RLC_SPM_CPG_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_CPC_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_CPF_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_CB_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_DB_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_PA_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_GDS_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_IA_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_SC_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_TCC_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_TCA_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_TCP_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_TA_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_TD_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_VGT_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_SPI_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_SQG_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_SX_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_GLOBAL_MUXSEL_ADDR
+#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
+#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL
+//RLC_SPM_GLOBAL_MUXSEL_DATA
+#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
+#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL
+//RLC_SPM_RING_RDPTR
+#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0
+#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xFFFFFFFFL
+//RLC_SPM_SEGMENT_THRESHOLD
+#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0
+#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xFFFFFFFFL
+//RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_RMI_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_PERFMON_CLK_CNTL
+#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0
+#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x00000001L
+//RLC_PERFMON_CNTL
+#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
+#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L
+#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
+//RLC_PERFCOUNTER0_SELECT
+#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL
+//RLC_PERFCOUNTER1_SELECT
+#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL
+//RLC_GPU_IOV_PERF_CNT_CNTL
+#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x0
+#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x1
+#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x2
+#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x3
+#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L
+#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L
+#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L
+#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xFFFFFFF8L
+//RLC_GPU_IOV_PERF_CNT_WR_ADDR
+#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x0
+#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x4
+#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x6
+#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000000FL
+#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000030L
+#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xFFFFFFC0L
+//RLC_GPU_IOV_PERF_CNT_WR_DATA
+#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0x0000000FL
+//RLC_GPU_IOV_PERF_CNT_RD_ADDR
+#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x0
+#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x4
+#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x6
+#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000000FL
+#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000030L
+#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xFFFFFFC0L
+//RLC_GPU_IOV_PERF_CNT_RD_DATA
+#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0x0000000FL
+//RMI_PERFCOUNTER0_SELECT
+#define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
+#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L
+#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//RMI_PERFCOUNTER0_SELECT1
+#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL
+#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L
+#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//RMI_PERFCOUNTER1_SELECT
+#define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
+#define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//RMI_PERFCOUNTER2_SELECT
+#define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
+#define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL
+#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x0007FC00L
+#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//RMI_PERFCOUNTER2_SELECT1
+#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
+#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
+#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18
+#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000001FFL
+#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x0007FC00L
+#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//RMI_PERFCOUNTER3_SELECT
+#define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL
+#define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//RMI_PERF_COUNTER_CNTL
+#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x0
+#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x2
+#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x4
+#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x6
+#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x8
+#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa
+#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0xe
+#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x13
+#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x19
+#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x1a
+#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L
+#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000CL
+#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L
+#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000C0L
+#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L
+#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003C00L
+#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007C000L
+#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01F80000L
+#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L
+#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L
+
+
+// addressBlock: gc_utcl2_atcl2pfcntldec
+//ATC_L2_PERFCOUNTER0_CFG
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//ATC_L2_PERFCOUNTER1_CFG
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//ATC_L2_PERFCOUNTER_RSLT_CNTL
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+
+// addressBlock: gc_utcl2_vml2pldec
+//MC_VM_L2_PERFCOUNTER0_CFG
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER1_CFG
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER2_CFG
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER3_CFG
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER4_CFG
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER5_CFG
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER6_CFG
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER7_CFG
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER_RSLT_CNTL
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+
+// addressBlock: gc_rlcpdec
+//RLC_CNTL
+#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0
+#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1
+#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2
+#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3
+#define RLC_CNTL__RESERVED__SHIFT 0x4
+#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L
+#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L
+#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L
+#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L
+#define RLC_CNTL__RESERVED_MASK 0xFFFFFFF0L
+//RLC_STAT
+#define RLC_STAT__RLC_BUSY__SHIFT 0x0
+#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1
+#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2
+#define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x3
+#define RLC_STAT__MC_BUSY__SHIFT 0x4
+#define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x5
+#define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x6
+#define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x7
+#define RLC_STAT__RESERVED__SHIFT 0x8
+#define RLC_STAT__RLC_BUSY_MASK 0x00000001L
+#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000002L
+#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000004L
+#define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000008L
+#define RLC_STAT__MC_BUSY_MASK 0x00000010L
+#define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L
+#define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L
+#define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L
+#define RLC_STAT__RESERVED_MASK 0xFFFFFF00L
+//RLC_SAFE_MODE
+#define RLC_SAFE_MODE__CMD__SHIFT 0x0
+#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1
+#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5
+#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8
+#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc
+#define RLC_SAFE_MODE__CMD_MASK 0x00000001L
+#define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001EL
+#define RLC_SAFE_MODE__RESERVED1_MASK 0x000000E0L
+#define RLC_SAFE_MODE__RESPONSE_MASK 0x00000F00L
+#define RLC_SAFE_MODE__RESERVED_MASK 0xFFFFF000L
+//RLC_MEM_SLP_CNTL
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0
+#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1
+#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
+#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10
+#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L
+#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L
+#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL
+#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000FF00L
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00FF0000L
+#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L
+//SMU_RLC_RESPONSE
+#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0
+#define SMU_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL
+//RLC_RLCV_SAFE_MODE
+#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0
+#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1
+#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5
+#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8
+#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc
+#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L
+#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001EL
+#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000E0L
+#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000F00L
+#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xFFFFF000L
+//RLC_SMU_SAFE_MODE
+#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0
+#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1
+#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5
+#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8
+#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc
+#define RLC_SMU_SAFE_MODE__CMD_MASK 0x00000001L
+#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x0000001EL
+#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0x000000E0L
+#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0x00000F00L
+#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xFFFFF000L
+//RLC_RLCV_COMMAND
+#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0
+#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4
+#define RLC_RLCV_COMMAND__CMD_MASK 0x0000000FL
+#define RLC_RLCV_COMMAND__RESERVED_MASK 0xFFFFFFF0L
+//RLC_REFCLOCK_TIMESTAMP_LSB
+#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x0
+#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xFFFFFFFFL
+//RLC_REFCLOCK_TIMESTAMP_MSB
+#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x0
+#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xFFFFFFFFL
+//RLC_GPM_TIMER_INT_0
+#define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x0
+#define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL
+//RLC_GPM_TIMER_INT_1
+#define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x0
+#define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL
+//RLC_GPM_TIMER_INT_2
+#define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x0
+#define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xFFFFFFFFL
+//RLC_GPM_TIMER_CTRL
+#define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0
+#define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1
+#define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x2
+#define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x3
+#define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0x4
+#define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L
+#define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L
+#define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L
+#define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L
+#define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xFFFFFFF0L
+//RLC_LB_CNTR_MAX
+#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0
+#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xFFFFFFFFL
+//RLC_GPM_TIMER_STAT
+#define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0
+#define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1
+#define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x2
+#define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x3
+#define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0x4
+#define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L
+#define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L
+#define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L
+#define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L
+#define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xFFFFFFF0L
+//RLC_GPM_TIMER_INT_3
+#define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x0
+#define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xFFFFFFFFL
+//RLC_SERDES_WR_NONCU_MASTER_MASK_1
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1__SHIFT 0x0
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1__SHIFT 0x10
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1__SHIFT 0x11
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK__SHIFT 0x12
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1__SHIFT 0x13
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK__SHIFT 0x14
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK__SHIFT 0x15
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK__SHIFT 0x16
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK__SHIFT 0x17
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK__SHIFT 0x18
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED__SHIFT 0x19
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1_MASK 0x0000FFFFL
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1_MASK 0x00010000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1_MASK 0x00020000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK_MASK 0x00040000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1_MASK 0x00080000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK_MASK 0x00100000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK_MASK 0x00200000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK_MASK 0x00400000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK_MASK 0x00800000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK_MASK 0x01000000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_MASK 0xFE000000L
+//RLC_SERDES_NONCU_MASTER_BUSY_1
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1__SHIFT 0x0
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1__SHIFT 0x10
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1__SHIFT 0x11
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1__SHIFT 0x12
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1__SHIFT 0x13
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY__SHIFT 0x14
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY__SHIFT 0x15
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY__SHIFT 0x16
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY__SHIFT 0x17
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY__SHIFT 0x18
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED__SHIFT 0x19
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1_MASK 0x0000FFFFL
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1_MASK 0x00010000L
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1_MASK 0x00020000L
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1_MASK 0x00040000L
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1_MASK 0x00080000L
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY_MASK 0x00100000L
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY_MASK 0x00200000L
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY_MASK 0x00400000L
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY_MASK 0x00800000L
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY_MASK 0x01000000L
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_MASK 0xFE000000L
+//RLC_INT_STAT
+#define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x0
+#define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x8
+#define RLC_INT_STAT__RESERVED__SHIFT 0x9
+#define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000FFL
+#define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L
+#define RLC_INT_STAT__RESERVED_MASK 0xFFFFFE00L
+//RLC_LB_CNTL
+#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0
+#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1
+#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2
+#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3
+#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4
+#define RLC_LB_CNTL__RESERVED__SHIFT 0xc
+#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L
+#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L
+#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L
+#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L
+#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0x00000FF0L
+#define RLC_LB_CNTL__RESERVED_MASK 0xFFFFF000L
+//RLC_MGCG_CTRL
+#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0
+#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1
+#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2
+#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3
+#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7
+#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0xf
+#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x10
+#define RLC_MGCG_CTRL__SPARE__SHIFT 0x11
+#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L
+#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L
+#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L
+#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L
+#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007F80L
+#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x00008000L
+#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x00010000L
+#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L
+//RLC_LB_CNTR_INIT
+#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0
+#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xFFFFFFFFL
+//RLC_LOAD_BALANCE_CNTR
+#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0
+#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xFFFFFFFFL
+//RLC_JUMP_TABLE_RESTORE
+#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0
+#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xFFFFFFFFL
+//RLC_PG_DELAY_2
+#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0
+#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8
+#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10
+#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000FFL
+#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000FF00L
+#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xFFFF0000L
+//RLC_GPU_CLOCK_COUNT_LSB
+#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0
+#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL
+//RLC_GPU_CLOCK_COUNT_MSB
+#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0
+#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL
+//RLC_CAPTURE_GPU_CLOCK_COUNT
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xFFFFFFFEL
+//RLC_UCODE_CNTL
+#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0
+#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xFFFFFFFFL
+//RLC_GPM_THREAD_RESET
+#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0
+#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1
+#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2
+#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3
+#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4
+#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L
+#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L
+#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L
+#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L
+#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xFFFFFFF0L
+//RLC_GPM_CP_DMA_COMPLETE_T0
+#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x0
+#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x1
+#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L
+#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xFFFFFFFEL
+//RLC_GPM_CP_DMA_COMPLETE_T1
+#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x0
+#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x1
+#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L
+#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xFFFFFFFEL
+//RLC_FIREWALL_VIOLATION
+#define RLC_FIREWALL_VIOLATION__ADDR__SHIFT 0x0
+#define RLC_FIREWALL_VIOLATION__ADDR_MASK 0xFFFFFFFFL
+//RLC_GPM_STAT
+#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0
+#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1
+#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2
+#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3
+#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4
+#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5
+#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6
+#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7
+#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8
+#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9
+#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa
+#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb
+#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc
+#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd
+#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe
+#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf
+#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10
+#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11
+#define RLC_GPM_STAT__CMP_power_status__SHIFT 0x12
+#define RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT 0x13
+#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT 0x14
+#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15
+#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16
+#define RLC_GPM_STAT__RESERVED__SHIFT 0x17
+#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18
+#define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L
+#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L
+#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L
+#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L
+#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L
+#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L
+#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L
+#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L
+#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L
+#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L
+#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L
+#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L
+#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L
+#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x00002000L
+#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x00004000L
+#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x00008000L
+#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x00010000L
+#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L
+#define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L
+#define RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK 0x00080000L
+#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK 0x00100000L
+#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L
+#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L
+#define RLC_GPM_STAT__RESERVED_MASK 0x00800000L
+#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L
+//RLC_GPU_CLOCK_32_RES_SEL
+#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0
+#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6
+#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003FL
+#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xFFFFFFC0L
+//RLC_GPU_CLOCK_32
+#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0
+#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xFFFFFFFFL
+//RLC_PG_CNTL
+#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0
+#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1
+#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2
+#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3
+#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4
+#define RLC_PG_CNTL__RESERVED__SHIFT 0x5
+#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe
+#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf
+#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10
+#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11
+#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12
+#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13
+#define RLC_PG_CNTL__RESERVED1__SHIFT 0x14
+#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L
+#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L
+#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L
+#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x00000008L
+#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L
+#define RLC_PG_CNTL__RESERVED_MASK 0x00003FE0L
+#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L
+#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L
+#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L
+#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L
+#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L
+#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x00080000L
+#define RLC_PG_CNTL__RESERVED1_MASK 0x00F00000L
+//RLC_GPM_THREAD_PRIORITY
+#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0
+#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8
+#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10
+#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18
+#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000FFL
+#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000FF00L
+#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00FF0000L
+#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xFF000000L
+//RLC_GPM_THREAD_ENABLE
+#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0
+#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1
+#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2
+#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3
+#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4
+#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L
+#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L
+#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L
+#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L
+#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xFFFFFFF0L
+//RLC_CGTT_MGCG_OVERRIDE
+#define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE__SHIFT 0x0
+#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x1
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x2
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x3
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x4
+#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x5
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x6
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x7
+#define RLC_CGTT_MGCG_OVERRIDE__RESERVED__SHIFT 0x8
+#define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK 0x00000001L
+#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L
+#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L
+#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_MASK 0xFFFFFF00L
+//RLC_CGCG_CGLS_CTRL
+#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0
+#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1
+#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
+#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
+#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b
+#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c
+#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d
+#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f
+#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L
+#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L
+#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL
+#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L
+#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L
+#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L
+#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L
+#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L
+//RLC_CGCG_RAMP_CTRL
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000FL
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000F00L
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000F000L
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0FFF0000L
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xF0000000L
+//RLC_DYN_PG_STATUS
+#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
+#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL
+//RLC_DYN_PG_REQUEST
+#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0
+#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xFFFFFFFFL
+//RLC_PG_DELAY
+#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0
+#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8
+#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10
+#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18
+#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000FFL
+#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000FF00L
+#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00FF0000L
+#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xFF000000L
+//RLC_CU_STATUS
+#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0
+#define RLC_CU_STATUS__WORK_PENDING_MASK 0xFFFFFFFFL
+//RLC_LB_INIT_CU_MASK
+#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0
+#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xFFFFFFFFL
+//RLC_LB_ALWAYS_ACTIVE_CU_MASK
+#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0
+#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xFFFFFFFFL
+//RLC_LB_PARAMS
+#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0
+#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10
+#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L
+#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000FEL
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000FF00L
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xFFFF0000L
+//RLC_THREAD1_DELAY
+#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0
+#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8
+#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10
+#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18
+#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0x000000FFL
+#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000FF00L
+#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00FF0000L
+#define RLC_THREAD1_DELAY__SPARE_MASK 0xFF000000L
+//RLC_PG_ALWAYS_ON_CU_MASK
+#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0
+#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xFFFFFFFFL
+//RLC_MAX_PG_CU
+#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0
+#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8
+#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0x000000FFL
+#define RLC_MAX_PG_CU__SPARE_MASK 0xFFFFFF00L
+//RLC_AUTO_PG_CTRL
+#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0
+#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1
+#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2
+#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3
+#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13
+#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L
+#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L
+#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L
+#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007FFF8L
+#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L
+//RLC_SMU_GRBM_REG_SAVE_CTRL
+#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0
+#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1
+#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x00000001L
+#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xFFFFFFFEL
+//RLC_SERDES_RD_MASTER_INDEX
+#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0
+#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4
+#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6
+#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9
+#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xc
+#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xd
+#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0x11
+#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x13
+#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0x0000000FL
+#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x00000030L
+#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x000001C0L
+#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x00000E00L
+#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x00001000L
+#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x0001E000L
+#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x00060000L
+#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xFFF80000L
+//RLC_SERDES_RD_DATA_0
+#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0
+#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xFFFFFFFFL
+//RLC_SERDES_RD_DATA_1
+#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0
+#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xFFFFFFFFL
+//RLC_SERDES_RD_DATA_2
+#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0
+#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xFFFFFFFFL
+//RLC_SERDES_WR_CU_MASTER_MASK
+#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0
+#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xFFFFFFFFL
+//RLC_SERDES_WR_NONCU_MASTER_MASK
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK__SHIFT 0x18
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK__SHIFT 0x19
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x1a
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0x0000FFFFL
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x00010000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x00020000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x00040000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x00080000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x00100000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x00200000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x00400000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x00800000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK_MASK 0x01000000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK_MASK 0x02000000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xFC000000L
+//RLC_SERDES_WR_CTRL
+#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0
+#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8
+#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9
+#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa
+#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb
+#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc
+#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd
+#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe
+#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf
+#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10
+#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a
+#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b
+#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c
+#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0x000000FFL
+#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x00000100L
+#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x00000200L
+#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x00000400L
+#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x00000800L
+#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x00001000L
+#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x00002000L
+#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x00004000L
+#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x00008000L
+#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x03FF0000L
+#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x04000000L
+#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x08000000L
+#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xF0000000L
+//RLC_SERDES_WR_DATA
+#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0
+#define RLC_SERDES_WR_DATA__DATA_MASK 0xFFFFFFFFL
+//RLC_SERDES_CU_MASTER_BUSY
+#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0
+#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xFFFFFFFFL
+//RLC_SERDES_NONCU_MASTER_BUSY
+#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0
+#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10
+#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17
+#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY__SHIFT 0x18
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY__SHIFT 0x19
+#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x1a
+#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0x0000FFFFL
+#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x00010000L
+#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x00020000L
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x00040000L
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x00080000L
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x00100000L
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x00200000L
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x00400000L
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x00800000L
+#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY_MASK 0x01000000L
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY_MASK 0x02000000L
+#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xFC000000L
+//RLC_GPM_GENERAL_0
+#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_0__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_1
+#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_1__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_2
+#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_2__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_3
+#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_3__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_4
+#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_4__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_5
+#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_5__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_6
+#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_6__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_7
+#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_7__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_SCRATCH_ADDR
+#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0
+#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9
+#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x000001FFL
+#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L
+//RLC_GPM_SCRATCH_DATA
+#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0
+#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL
+//RLC_STATIC_PG_STATUS
+#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
+#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL
+//RLC_SPM_MC_CNTL
+#define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x0
+#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT 0x4
+#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x5
+#define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x6
+#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x7
+#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x8
+#define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0xa
+#define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000FL
+#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK 0x00000010L
+#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000020L
+#define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000040L
+#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00000080L
+#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00000300L
+#define RLC_SPM_MC_CNTL__RESERVED_MASK 0xFFFFFC00L
+//RLC_SPM_INT_CNTL
+#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0
+#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1
+#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L
+#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xFFFFFFFEL
+//RLC_SPM_INT_STATUS
+#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0
+#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1
+#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L
+#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xFFFFFFFEL
+//RLC_SMU_MESSAGE
+#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0
+#define RLC_SMU_MESSAGE__CMD_MASK 0xFFFFFFFFL
+//RLC_GPM_LOG_SIZE
+#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0
+#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xFFFFFFFFL
+//RLC_PG_DELAY_3
+#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0
+#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8
+#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0x000000FFL
+#define RLC_PG_DELAY_3__RESERVED_MASK 0xFFFFFF00L
+//RLC_GPR_REG1
+#define RLC_GPR_REG1__DATA__SHIFT 0x0
+#define RLC_GPR_REG1__DATA_MASK 0xFFFFFFFFL
+//RLC_GPR_REG2
+#define RLC_GPR_REG2__DATA__SHIFT 0x0
+#define RLC_GPR_REG2__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_LOG_CONT
+#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0
+#define RLC_GPM_LOG_CONT__CONT_MASK 0xFFFFFFFFL
+//RLC_GPM_INT_DISABLE_TH0
+#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0
+#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xFFFFFFFFL
+//RLC_GPM_INT_DISABLE_TH1
+#define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT 0x0
+#define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xFFFFFFFFL
+//RLC_GPM_INT_FORCE_TH0
+#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0
+#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xFFFFFFFFL
+//RLC_GPM_INT_FORCE_TH1
+#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0
+#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xFFFFFFFFL
+//RLC_SRM_CNTL
+#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0
+#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1
+#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2
+#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L
+#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L
+#define RLC_SRM_CNTL__RESERVED_MASK 0xFFFFFFFCL
+//RLC_SRM_ARAM_ADDR
+#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0
+#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xc
+#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x00000FFFL
+#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xFFFFF000L
+//RLC_SRM_ARAM_DATA
+#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0
+#define RLC_SRM_ARAM_DATA__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_DRAM_ADDR
+#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0
+#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xc
+#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x00000FFFL
+#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xFFFFF000L
+//RLC_SRM_DRAM_DATA
+#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0
+#define RLC_SRM_DRAM_DATA__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_GPM_COMMAND
+#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0
+#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1
+#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2
+#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5
+#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11
+#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d
+#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f
+#define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L
+#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L
+#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL
+#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0001FFE0L
+#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1FFE0000L
+#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000L
+#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000L
+//RLC_SRM_GPM_COMMAND_STATUS
+#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
+#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
+#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2
+#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L
+#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L
+#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL
+//RLC_SRM_RLCV_COMMAND
+#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0
+#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1
+#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4
+#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10
+#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c
+#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f
+#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x00000001L
+#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0x0000000EL
+#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0x0000FFF0L
+#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0x0FFF0000L
+#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000L
+#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000L
+//RLC_SRM_RLCV_COMMAND_STATUS
+#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
+#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
+#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2
+#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L
+#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L
+#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL
+//RLC_SRM_INDEX_CNTL_ADDR_0
+#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_ADDR_1
+#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_ADDR_2
+#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_ADDR_3
+#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_ADDR_4
+#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_ADDR_5
+#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_ADDR_6
+#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_ADDR_7
+#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_DATA_0
+#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_INDEX_CNTL_DATA_1
+#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_INDEX_CNTL_DATA_2
+#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_INDEX_CNTL_DATA_3
+#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_INDEX_CNTL_DATA_4
+#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_INDEX_CNTL_DATA_5
+#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_INDEX_CNTL_DATA_6
+#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_INDEX_CNTL_DATA_7
+#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_STAT
+#define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x0
+#define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT 0x1
+#define RLC_SRM_STAT__RESERVED__SHIFT 0x2
+#define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L
+#define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK 0x00000002L
+#define RLC_SRM_STAT__RESERVED_MASK 0xFFFFFFFCL
+//RLC_SRM_GPM_ABORT
+#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0
+#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1
+#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L
+#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xFFFFFFFEL
+//RLC_CSIB_ADDR_LO
+#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0
+#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xFFFFFFFFL
+//RLC_CSIB_ADDR_HI
+#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0
+#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x0000FFFFL
+//RLC_CSIB_LENGTH
+#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0
+#define RLC_CSIB_LENGTH__LENGTH_MASK 0xFFFFFFFFL
+//RLC_SMU_COMMAND
+#define RLC_SMU_COMMAND__CMD__SHIFT 0x0
+#define RLC_SMU_COMMAND__CMD_MASK 0xFFFFFFFFL
+//RLC_CP_SCHEDULERS
+#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0
+#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8
+#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10
+#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18
+#define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000FFL
+#define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000FF00L
+#define RLC_CP_SCHEDULERS__scheduler2_MASK 0x00FF0000L
+#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xFF000000L
+//RLC_SMU_ARGUMENT_1
+#define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0
+#define RLC_SMU_ARGUMENT_1__ARG_MASK 0xFFFFFFFFL
+//RLC_SMU_ARGUMENT_2
+#define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0
+#define RLC_SMU_ARGUMENT_2__ARG_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_8
+#define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_8__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_9
+#define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_9__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_10
+#define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_10__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_11
+#define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_11__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_12
+#define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_12__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_UTCL1_CNTL_0
+#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x18
+#define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT 0x19
+#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x1a
+#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x1c
+#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
+#define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x1e
+#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L
+#define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK 0x02000000L
+#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L
+#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L
+#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
+#define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0xC0000000L
+//RLC_GPM_UTCL1_CNTL_1
+#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT 0x18
+#define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT 0x19
+#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT 0x1a
+#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT 0x1c
+#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
+#define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT 0x1e
+#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK 0x01000000L
+#define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK 0x02000000L
+#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK 0x04000000L
+#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK 0x10000000L
+#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
+#define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK 0xC0000000L
+//RLC_GPM_UTCL1_CNTL_2
+#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT 0x18
+#define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT 0x19
+#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT 0x1a
+#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT 0x1c
+#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
+#define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT 0x1e
+#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK 0x01000000L
+#define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK 0x02000000L
+#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK 0x04000000L
+#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK 0x10000000L
+#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
+#define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK 0xC0000000L
+//RLC_SPM_UTCL1_CNTL
+#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
+#define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT 0x19
+#define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
+#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
+#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
+#define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x1e
+#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
+#define RLC_SPM_UTCL1_CNTL__BYPASS_MASK 0x02000000L
+#define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
+#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
+#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
+#define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0xC0000000L
+//RLC_UTCL1_STATUS_2
+#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x0
+#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x1
+#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x2
+#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x3
+#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT 0x4
+#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x5
+#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x6
+#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0x7
+#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0x8
+#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT 0x9
+#define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0xa
+#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L
+#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L
+#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L
+#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L
+#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK 0x00000010L
+#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000020L
+#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000040L
+#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000080L
+#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000100L
+#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK 0x00000200L
+#define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xFFFFFC00L
+//RLC_LB_THR_CONFIG_2
+#define RLC_LB_THR_CONFIG_2__DATA__SHIFT 0x0
+#define RLC_LB_THR_CONFIG_2__DATA_MASK 0xFFFFFFFFL
+//RLC_LB_THR_CONFIG_3
+#define RLC_LB_THR_CONFIG_3__DATA__SHIFT 0x0
+#define RLC_LB_THR_CONFIG_3__DATA_MASK 0xFFFFFFFFL
+//RLC_LB_THR_CONFIG_4
+#define RLC_LB_THR_CONFIG_4__DATA__SHIFT 0x0
+#define RLC_LB_THR_CONFIG_4__DATA_MASK 0xFFFFFFFFL
+//RLC_SPM_UTCL1_ERROR_1
+#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0
+#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
+#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
+#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L
+#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
+#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
+//RLC_SPM_UTCL1_ERROR_2
+#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
+#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
+//RLC_GPM_UTCL1_TH0_ERROR_1
+#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x0
+#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
+#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
+#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L
+#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
+#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
+//RLC_LB_THR_CONFIG_1
+#define RLC_LB_THR_CONFIG_1__DATA__SHIFT 0x0
+#define RLC_LB_THR_CONFIG_1__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_UTCL1_TH0_ERROR_2
+#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
+#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
+//RLC_GPM_UTCL1_TH1_ERROR_1
+#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT 0x0
+#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
+#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
+#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK 0x00000003L
+#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
+#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
+//RLC_GPM_UTCL1_TH1_ERROR_2
+#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
+#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
+//RLC_GPM_UTCL1_TH2_ERROR_1
+#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT 0x0
+#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
+#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
+#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK 0x00000003L
+#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
+#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
+//RLC_GPM_UTCL1_TH2_ERROR_2
+#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
+#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
+//RLC_CGCG_CGLS_CTRL_3D
+#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT 0x0
+#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT 0x1
+#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
+#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
+#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT 0x1b
+#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT 0x1c
+#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT 0x1d
+#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT 0x1f
+#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK 0x00000001L
+#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK 0x00000002L
+#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL
+#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L
+#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK 0x08000000L
+#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK 0x10000000L
+#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK 0x60000000L
+#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK 0x80000000L
+//RLC_CGCG_RAMP_CTRL_3D
+#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT 0x0
+#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT 0x4
+#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT 0x8
+#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT 0xc
+#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT 0x10
+#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT 0x1c
+#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK 0x0000000FL
+#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L
+#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK 0x00000F00L
+#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK 0x0000F000L
+#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK 0x0FFF0000L
+#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK 0xF0000000L
+//RLC_SEMAPHORE_0
+#define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0
+#define RLC_SEMAPHORE_0__RESERVED__SHIFT 0x5
+#define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL
+#define RLC_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L
+//RLC_SEMAPHORE_1
+#define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0
+#define RLC_SEMAPHORE_1__RESERVED__SHIFT 0x5
+#define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL
+#define RLC_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L
+//RLC_CP_EOF_INT
+#define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x0
+#define RLC_CP_EOF_INT__RESERVED__SHIFT 0x1
+#define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L
+#define RLC_CP_EOF_INT__RESERVED_MASK 0xFFFFFFFEL
+//RLC_CP_EOF_INT_CNT
+#define RLC_CP_EOF_INT_CNT__CNT__SHIFT 0x0
+#define RLC_CP_EOF_INT_CNT__CNT_MASK 0xFFFFFFFFL
+//RLC_SPARE_INT
+#define RLC_SPARE_INT__INTERRUPT__SHIFT 0x0
+#define RLC_SPARE_INT__RESERVED__SHIFT 0x1
+#define RLC_SPARE_INT__INTERRUPT_MASK 0x00000001L
+#define RLC_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL
+//RLC_PREWALKER_UTCL1_CNTL
+#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
+#define RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT 0x19
+#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
+#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
+#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
+#define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT 0x1e
+#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
+#define RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK 0x02000000L
+#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
+#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
+#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
+#define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK 0xC0000000L
+//RLC_PREWALKER_UTCL1_TRIG
+#define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT 0x0
+#define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT 0x1
+#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT 0x5
+#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT 0x6
+#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT 0x7
+#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT 0x8
+#define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT 0x9
+#define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT 0x1f
+#define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK 0x00000001L
+#define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK 0x0000001EL
+#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK 0x00000020L
+#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK 0x00000040L
+#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK 0x00000080L
+#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK 0x00000100L
+#define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK 0x7FFFFE00L
+#define RLC_PREWALKER_UTCL1_TRIG__READY_MASK 0x80000000L
+//RLC_PREWALKER_UTCL1_ADDR_LSB
+#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT 0x0
+#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK 0xFFFFFFFFL
+//RLC_PREWALKER_UTCL1_ADDR_MSB
+#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT 0x0
+#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK 0x0000FFFFL
+//RLC_PREWALKER_UTCL1_SIZE_LSB
+#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT 0x0
+#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK 0xFFFFFFFFL
+//RLC_PREWALKER_UTCL1_SIZE_MSB
+#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT 0x0
+#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK 0x00000003L
+//RLC_DSM_TRIG
+//RLC_UTCL1_STATUS
+#define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x3
+#define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
+#define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0xe
+#define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
+#define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x16
+#define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
+#define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x1e
+#define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+#define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000F8L
+#define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
+#define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000C000L
+#define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
+#define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00C00000L
+#define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
+#define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xC0000000L
+//RLC_R2I_CNTL_0
+#define RLC_R2I_CNTL_0__Data__SHIFT 0x0
+#define RLC_R2I_CNTL_0__Data_MASK 0xFFFFFFFFL
+//RLC_R2I_CNTL_1
+#define RLC_R2I_CNTL_1__Data__SHIFT 0x0
+#define RLC_R2I_CNTL_1__Data_MASK 0xFFFFFFFFL
+//RLC_R2I_CNTL_2
+#define RLC_R2I_CNTL_2__Data__SHIFT 0x0
+#define RLC_R2I_CNTL_2__Data_MASK 0xFFFFFFFFL
+//RLC_R2I_CNTL_3
+#define RLC_R2I_CNTL_3__Data__SHIFT 0x0
+#define RLC_R2I_CNTL_3__Data_MASK 0xFFFFFFFFL
+//RLC_UTCL2_CNTL
+#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0
+#define RLC_UTCL2_CNTL__RESERVED__SHIFT 0x1
+#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L
+#define RLC_UTCL2_CNTL__RESERVED_MASK 0xFFFFFFFEL
+//RLC_LBPW_CU_STAT
+#define RLC_LBPW_CU_STAT__MAX_CU__SHIFT 0x0
+#define RLC_LBPW_CU_STAT__ON_CU__SHIFT 0x10
+#define RLC_LBPW_CU_STAT__MAX_CU_MASK 0x0000FFFFL
+#define RLC_LBPW_CU_STAT__ON_CU_MASK 0xFFFF0000L
+//RLC_DS_CNTL
+#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x0
+#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x1
+#define RLC_DS_CNTL__RESRVED__SHIFT 0x2
+#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x10
+#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x11
+#define RLC_DS_CNTL__RESRVED_1__SHIFT 0x12
+#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000001L
+#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000002L
+#define RLC_DS_CNTL__RESRVED_MASK 0x0000FFFCL
+#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00010000L
+#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00020000L
+#define RLC_DS_CNTL__RESRVED_1_MASK 0xFFFC0000L
+//RLC_RLCV_SPARE_INT
+#define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0
+#define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1
+#define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L
+#define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL
+
+
+// addressBlock: gc_pwrdec
+//CGTS_SM_CTRL_REG
+#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0
+#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4
+#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc
+#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10
+#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11
+#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14
+#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15
+#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16
+#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17
+#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18
+#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL
+#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L
+#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L
+#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L
+#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L
+#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L
+#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L
+#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L
+#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L
+#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xFF000000L
+//CGTS_RD_CTRL_REG
+#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0
+#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8
+#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001FL
+#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001F00L
+//CGTS_RD_REG
+#define CGTS_RD_REG__READ_DATA__SHIFT 0x0
+#define CGTS_RD_REG__READ_DATA_MASK 0x00003FFFL
+//CGTS_TCC_DISABLE
+#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
+#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L
+//CGTS_USER_TCC_DISABLE
+#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
+#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L
+//CGTS_CU0_SP0_CTRL_REG
+#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU0_LDS_SQ_CTRL_REG
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU0_TA_SQC_CTRL_REG
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU0_SP1_CTRL_REG
+#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU0_TD_TCP_CTRL_REG
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU1_SP0_CTRL_REG
+#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU1_LDS_SQ_CTRL_REG
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU1_TA_SQC_CTRL_REG
+#define CGTS_CU1_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+//CGTS_CU1_SP1_CTRL_REG
+#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU1_TD_TCP_CTRL_REG
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU2_SP0_CTRL_REG
+#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU2_LDS_SQ_CTRL_REG
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU2_TA_SQC_CTRL_REG
+#define CGTS_CU2_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+//CGTS_CU2_SP1_CTRL_REG
+#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU2_TD_TCP_CTRL_REG
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU3_SP0_CTRL_REG
+#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU3_LDS_SQ_CTRL_REG
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU3_TA_SQC_CTRL_REG
+#define CGTS_CU3_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU3_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
+#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU3_SP1_CTRL_REG
+#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU3_TD_TCP_CTRL_REG
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU4_SP0_CTRL_REG
+#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU4_LDS_SQ_CTRL_REG
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU4_TA_SQC_CTRL_REG
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+//CGTS_CU4_SP1_CTRL_REG
+#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU4_TD_TCP_CTRL_REG
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU5_SP0_CTRL_REG
+#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU5_LDS_SQ_CTRL_REG
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU5_TA_SQC_CTRL_REG
+#define CGTS_CU5_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+//CGTS_CU5_SP1_CTRL_REG
+#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU5_TD_TCP_CTRL_REG
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU6_SP0_CTRL_REG
+#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU6_LDS_SQ_CTRL_REG
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU6_TA_SQC_CTRL_REG
+#define CGTS_CU6_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU6_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
+#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU6_SP1_CTRL_REG
+#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU6_TD_TCP_CTRL_REG
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU7_SP0_CTRL_REG
+#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU7_LDS_SQ_CTRL_REG
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU7_TA_SQC_CTRL_REG
+#define CGTS_CU7_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+//CGTS_CU7_SP1_CTRL_REG
+#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU7_TD_TCP_CTRL_REG
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU8_SP0_CTRL_REG
+#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU8_LDS_SQ_CTRL_REG
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU8_TA_SQC_CTRL_REG
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+//CGTS_CU8_SP1_CTRL_REG
+#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU8_TD_TCP_CTRL_REG
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU9_SP0_CTRL_REG
+#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU9_LDS_SQ_CTRL_REG
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU9_TA_SQC_CTRL_REG
+#define CGTS_CU9_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU9_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
+#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU9_SP1_CTRL_REG
+#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU9_TD_TCP_CTRL_REG
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU10_SP0_CTRL_REG
+#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU10_LDS_SQ_CTRL_REG
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU10_TA_SQC_CTRL_REG
+#define CGTS_CU10_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+//CGTS_CU10_SP1_CTRL_REG
+#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU10_TD_TCP_CTRL_REG
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU11_SP0_CTRL_REG
+#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU11_LDS_SQ_CTRL_REG
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU11_TA_SQC_CTRL_REG
+#define CGTS_CU11_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+//CGTS_CU11_SP1_CTRL_REG
+#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU11_TD_TCP_CTRL_REG
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU12_SP0_CTRL_REG
+#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU12_LDS_SQ_CTRL_REG
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU12_TA_SQC_CTRL_REG
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU12_SP1_CTRL_REG
+#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU12_TD_TCP_CTRL_REG
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU13_SP0_CTRL_REG
+#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU13_LDS_SQ_CTRL_REG
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU13_TA_SQC_CTRL_REG
+#define CGTS_CU13_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+//CGTS_CU13_SP1_CTRL_REG
+#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU13_TD_TCP_CTRL_REG
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU14_SP0_CTRL_REG
+#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU14_LDS_SQ_CTRL_REG
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU14_TA_SQC_CTRL_REG
+#define CGTS_CU14_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+//CGTS_CU14_SP1_CTRL_REG
+#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU14_TD_TCP_CTRL_REG
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU15_SP0_CTRL_REG
+#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU15_LDS_SQ_CTRL_REG
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU15_TA_SQC_CTRL_REG
+#define CGTS_CU15_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU15_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
+#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU15_SP1_CTRL_REG
+#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU15_TD_TCP_CTRL_REG
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU0_TCPI_CTRL_REG
+#define CGTS_CU0_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU0_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU0_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU1_TCPI_CTRL_REG
+#define CGTS_CU1_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU1_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU1_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU2_TCPI_CTRL_REG
+#define CGTS_CU2_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU2_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU2_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU3_TCPI_CTRL_REG
+#define CGTS_CU3_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU3_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU3_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU4_TCPI_CTRL_REG
+#define CGTS_CU4_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU4_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU4_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU5_TCPI_CTRL_REG
+#define CGTS_CU5_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU5_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU5_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU6_TCPI_CTRL_REG
+#define CGTS_CU6_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU6_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU6_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU7_TCPI_CTRL_REG
+#define CGTS_CU7_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU7_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU7_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU8_TCPI_CTRL_REG
+#define CGTS_CU8_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU8_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU8_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU9_TCPI_CTRL_REG
+#define CGTS_CU9_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU9_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU9_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU10_TCPI_CTRL_REG
+#define CGTS_CU10_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU10_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU10_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU11_TCPI_CTRL_REG
+#define CGTS_CU11_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU11_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU11_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU12_TCPI_CTRL_REG
+#define CGTS_CU12_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU12_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU12_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU13_TCPI_CTRL_REG
+#define CGTS_CU13_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU13_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU13_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU14_TCPI_CTRL_REG
+#define CGTS_CU14_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU14_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU14_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU15_TCPI_CTRL_REG
+#define CGTS_CU15_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU15_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU15_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTT_SPI_CLK_CTRL
+#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
+#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
+#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a
+#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b
+#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
+#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
+#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
+#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L
+#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L
+#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x04000000L
+#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L
+#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L
+#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L
+#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L
+#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//CGTT_PC_CLK_CTRL
+#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
+#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT 0x19
+#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT 0x1a
+#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
+#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
+#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
+#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
+#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L
+#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK 0x02000000L
+#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK 0x04000000L
+#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L
+#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L
+#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L
+#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L
+#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//CGTT_BCI_CLK_CTRL
+#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18
+#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19
+#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a
+#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
+#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
+#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
+#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
+#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x0000F000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L
+#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L
+#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L
+#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L
+#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L
+#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L
+#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L
+#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//CGTT_VGT_CLK_CTRL
+#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0xf
+#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x10
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9__SHIFT 0x18
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a
+#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b
+#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c
+#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d
+#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
+#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L
+#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9_MASK 0x01000000L
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L
+#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L
+#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L
+#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000L
+#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
+#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//CGTT_IA_CLK_CTRL
+#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
+#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
+#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L
+#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x04000000L
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
+#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//CGTT_WD_CLK_CTRL
+#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0xf
+#define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x10
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19
+#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a
+#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b
+#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c
+#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d
+#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e
+#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L
+#define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L
+#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L
+#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L
+#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L
+#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L
+#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L
+#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//CGTT_PA_CLK_CTRL
+#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_PA_CLK_CTRL__DEBUG_BUS_EN__SHIFT 0x17
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d
+#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e
+#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f
+#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_PA_CLK_CTRL__DEBUG_BUS_EN_MASK 0x00800000L
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L
+#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L
+#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L
+//CGTT_SC_CLK_CTRL0
+#define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT 0x0
+#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT 0x10
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x11
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x12
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x13
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x14
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x15
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x16
+#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x17
+#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT 0x18
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x19
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1a
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1b
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1c
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1d
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1e
+#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f
+#define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK 0x00010000L
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00020000L
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00040000L
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00080000L
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00100000L
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00200000L
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00400000L
+#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L
+#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK 0x01000000L
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x02000000L
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x04000000L
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x08000000L
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x10000000L
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x20000000L
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x40000000L
+#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L
+//CGTT_SC_CLK_CTRL1
+#define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT 0x0
+#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x11
+#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x12
+#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT 0x13
+#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT 0x14
+#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x15
+#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x16
+#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x19
+#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x1a
+#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT 0x1b
+#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x1c
+#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x1d
+#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT 0x1e
+#define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L
+#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L
+#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK 0x00080000L
+#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK 0x00100000L
+#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L
+#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L
+#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L
+#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L
+#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK 0x08000000L
+#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L
+#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L
+#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK 0x40000000L
+//CGTT_SQ_CLK_CTRL
+#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
+#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
+#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L
+#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
+#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//CGTT_SQG_CLK_CTRL
+#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c
+#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
+#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
+#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L
+#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L
+#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
+#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//SQ_ALU_CLK_CTRL
+#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
+#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
+#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL
+#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L
+//SQ_TEX_CLK_CTRL
+#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
+#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
+#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL
+#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L
+//SQ_LDS_CLK_CTRL
+#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
+#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
+#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL
+#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L
+//SQ_POWER_THROTTLE
+#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0
+#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10
+#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e
+#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x00003FFFL
+#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3FFF0000L
+#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xC0000000L
+//SQ_POWER_THROTTLE2
+#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0
+#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f
+#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x00003FFFL
+#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
+#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
+#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000L
+//CGTT_SX_CLK_CTRL0
+#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x0000F000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_SX_CLK_CTRL1
+#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_SX_CLK_CTRL1__DBG_EN__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x0000F000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_SX_CLK_CTRL1__DBG_EN_MASK 0x01000000L
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_SX_CLK_CTRL2
+#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xd
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_SX_CLK_CTRL2__DBG_EN__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x0000E000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_SX_CLK_CTRL2__DBG_EN_MASK 0x01000000L
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_SX_CLK_CTRL3
+#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xd
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_SX_CLK_CTRL3__DBG_EN__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x0000E000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_SX_CLK_CTRL3__DBG_EN_MASK 0x01000000L
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_SX_CLK_CTRL4
+#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_SX_CLK_CTRL4__DBG_EN__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x0000F000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_SX_CLK_CTRL4__DBG_EN_MASK 0x01000000L
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L
+//TD_CGTT_CTRL
+#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0
+#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL
+#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//TA_CGTT_CTRL
+#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0
+#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL
+#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_TCPI_CLK_CTRL
+#define CGTT_TCPI_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_TCPI_CLK_CTRL__SPARE__SHIFT 0xc
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_TCPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_TCPI_CLK_CTRL__SPARE_MASK 0x0000F000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_TCI_CLK_CTRL
+#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_GDS_CLK_CTRL
+#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//DB_CGTT_CLK_CTRL_0
+#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0
+#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4
+#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000FL
+#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x0000F000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L
+//CB_CGTT_SCLK_CTRL
+#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//TCC_CGTT_SCLK_CTRL
+#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
+#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//TCA_CGTT_SCLK_CTRL
+#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
+#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_CP_CLK_CTRL
+#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
+//CGTT_CPF_CLK_CTRL
+#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
+//CGTT_CPC_CLK_CTRL
+#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
+//CGTT_RLC_CLK_CTRL
+#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
+//RLC_GFX_RM_CNTL
+#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT 0x0
+#define RLC_GFX_RM_CNTL__RESERVED__SHIFT 0x1
+#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK 0x00000001L
+#define RLC_GFX_RM_CNTL__RESERVED_MASK 0xFFFFFFFEL
+//RMI_CGTT_SCLK_CTRL
+#define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
+#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_TCPF_CLK_CTRL
+#define CGTT_TCPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_TCPF_CLK_CTRL__SPARE__SHIFT 0xc
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_TCPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_TCPF_CLK_CTRL__SPARE_MASK 0x0000F000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+
+
+// addressBlock: gc_ea_pwrdec
+//GCEA_CGTT_CLK_CTRL
+#define GCEA_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e
+#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f
+#define GCEA_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L
+#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L
+
+
+// addressBlock: gc_utcl2_vmsharedhvdec
+//MC_VM_FB_SIZE_OFFSET_VF0
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF1
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF2
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF3
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF4
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF5
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF6
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF7
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF8
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF9
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF10
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF11
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF12
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF13
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF14
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF15
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L
+//VM_IOMMU_MMIO_CNTRL_1
+#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8
+#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L
+//MC_VM_MARC_BASE_LO_0
+#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L
+//MC_VM_MARC_BASE_LO_1
+#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L
+//MC_VM_MARC_BASE_LO_2
+#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L
+//MC_VM_MARC_BASE_LO_3
+#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L
+//MC_VM_MARC_BASE_HI_0
+#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL
+//MC_VM_MARC_BASE_HI_1
+#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL
+//MC_VM_MARC_BASE_HI_2
+#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL
+//MC_VM_MARC_BASE_HI_3
+#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL
+//MC_VM_MARC_RELOC_LO_0
+#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L
+#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L
+#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L
+//MC_VM_MARC_RELOC_LO_1
+#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L
+#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L
+#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L
+//MC_VM_MARC_RELOC_LO_2
+#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L
+#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L
+#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L
+//MC_VM_MARC_RELOC_LO_3
+#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L
+#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L
+#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L
+//MC_VM_MARC_RELOC_HI_0
+#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL
+//MC_VM_MARC_RELOC_HI_1
+#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL
+//MC_VM_MARC_RELOC_HI_2
+#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL
+//MC_VM_MARC_RELOC_HI_3
+#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL
+//MC_VM_MARC_LEN_LO_0
+#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L
+//MC_VM_MARC_LEN_LO_1
+#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L
+//MC_VM_MARC_LEN_LO_2
+#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L
+//MC_VM_MARC_LEN_LO_3
+#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L
+//MC_VM_MARC_LEN_HI_0
+#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL
+//MC_VM_MARC_LEN_HI_1
+#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL
+//MC_VM_MARC_LEN_HI_2
+#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL
+//MC_VM_MARC_LEN_HI_3
+#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL
+//VM_IOMMU_CONTROL_REGISTER
+#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0
+#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L
+//VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
+#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd
+#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L
+//VM_PCIE_ATS_CNTL
+#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10
+#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L
+#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_0
+#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_1
+#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_2
+#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_3
+#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_4
+#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_5
+#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_6
+#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_7
+#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_8
+#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_9
+#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_10
+#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_11
+#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_12
+#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_13
+#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_14
+#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_15
+#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L
+//UTCL2_CGTT_CLK_CTRL
+#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc
+#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
+#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
+#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L
+#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
+#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
+
+
+// addressBlock: gc_hypdec
+//CP_HYP_PFP_UCODE_ADDR
+#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL
+//CP_PFP_UCODE_ADDR
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL
+//CP_HYP_PFP_UCODE_DATA
+#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//CP_PFP_UCODE_DATA
+#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//CP_HYP_ME_UCODE_ADDR
+#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK 0x00001FFFL
+//CP_ME_RAM_RADDR
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x00001FFFL
+//CP_ME_RAM_WADDR
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x00001FFFL
+//CP_HYP_ME_UCODE_DATA
+#define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//CP_ME_RAM_DATA
+#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
+#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xFFFFFFFFL
+//CP_CE_UCODE_ADDR
+#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL
+//CP_HYP_CE_UCODE_ADDR
+#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL
+//CP_CE_UCODE_DATA
+#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//CP_HYP_CE_UCODE_DATA
+#define CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//CP_HYP_MEC1_UCODE_ADDR
+#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
+//CP_MEC_ME1_UCODE_ADDR
+#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
+//CP_HYP_MEC1_UCODE_DATA
+#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//CP_MEC_ME1_UCODE_DATA
+#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//CP_HYP_MEC2_UCODE_ADDR
+#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
+//CP_MEC_ME2_UCODE_ADDR
+#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
+//CP_HYP_MEC2_UCODE_DATA
+#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//CP_MEC_ME2_UCODE_DATA
+#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_UCODE_ADDR
+#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xe
+#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL
+#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xFFFFC000L
+//RLC_GPM_UCODE_DATA
+#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//GRBM_GFX_INDEX_SR_SELECT
+#define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x0
+#define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L
+//GRBM_GFX_INDEX_SR_DATA
+#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x0
+#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX__SHIFT 0x8
+#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x10
+#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d
+#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
+#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f
+#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x000000FFL
+#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX_MASK 0x0000FF00L
+#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x00FF0000L
+#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES_MASK 0x20000000L
+#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L
+#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L
+//GRBM_GFX_CNTL_SR_SELECT
+#define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x0
+#define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L
+//GRBM_GFX_CNTL_SR_DATA
+#define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x0
+#define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x2
+#define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x4
+#define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x8
+#define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L
+#define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000CL
+#define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000F0L
+#define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L
+//GRBM_CAM_INDEX
+#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
+#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L
+//GRBM_HYP_CAM_INDEX
+#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0
+#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x00000007L
+//GRBM_CAM_DATA
+#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
+#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
+#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL
+#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L
+//GRBM_HYP_CAM_DATA
+#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0
+#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
+#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL
+#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L
+//RLC_GPU_IOV_VF_ENABLE
+#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10
+#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
+#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000FFFEL
+#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xFFFF0000L
+//RLC_GPU_IOV_CFG_REG6
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7
+#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007FL
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L
+#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xFFFFFC00L
+//RLC_GPU_IOV_CFG_REG8
+#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
+//RLC_RLCV_TIMER_INT_0
+#define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT 0x0
+#define RLC_RLCV_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL
+//RLC_RLCV_TIMER_CTRL
+#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0
+#define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT 0x1
+#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L
+#define RLC_RLCV_TIMER_CTRL__RESERVED_MASK 0xFFFFFFFEL
+//RLC_RLCV_TIMER_STAT
+#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0
+#define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT 0x1
+#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L
+#define RLC_RLCV_TIMER_STAT__RESERVED_MASK 0xFFFFFFFEL
+//RLC_GPU_IOV_VF_DOORBELL_STATUS
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED__SHIFT 0x10
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x1f
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x0000FFFFL
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED_MASK 0x7FFF0000L
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L
+//RLC_GPU_IOV_VF_DOORBELL_STATUS_SET
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x0
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED__SHIFT 0x10
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x1f
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x0000FFFFL
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED_MASK 0x7FFF0000L
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L
+//RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x0
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED__SHIFT 0x10
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x1f
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x0000FFFFL
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED_MASK 0x7FFF0000L
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L
+//RLC_GPU_IOV_VF_MASK
+#define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x0
+#define RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT 0x10
+#define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x0000FFFFL
+#define RLC_GPU_IOV_VF_MASK__RESERVED_MASK 0xFFFF0000L
+//RLC_HYP_SEMAPHORE_2
+#define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0
+#define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT 0x5
+#define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL
+#define RLC_HYP_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L
+//RLC_HYP_SEMAPHORE_3
+#define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0
+#define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT 0x5
+#define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL
+#define RLC_HYP_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L
+//RLC_CLK_CNTL
+#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x0
+#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x1
+#define RLC_CLK_CNTL__RESERVED__SHIFT 0x2
+#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x00000001L
+#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x00000002L
+#define RLC_CLK_CNTL__RESERVED_MASK 0xFFFFFFFCL
+//RLC_GPU_IOV_SCH_BLOCK
+#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x4
+#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x8
+#define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x10
+#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000FL
+#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000F0L
+#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x00007F00L
+#define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0x7FFF0000L
+//RLC_GPU_IOV_CFG_REG1
+#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4
+#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5
+#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6
+#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8
+#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10
+#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18
+#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000FL
+#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L
+#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L
+#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000C0L
+#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x0000FF00L
+#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00FF0000L
+#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xFF000000L
+//RLC_GPU_IOV_CFG_REG2
+#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4
+#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0x0000000FL
+#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xFFFFFFF0L
+//RLC_GPU_IOV_VM_BUSY_STATUS
+#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SCH_0
+#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_ACTIVE_FCN_ID
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L
+//RLC_GPU_IOV_SCH_3
+#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SCH_1
+#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SCH_2
+#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_UCODE_ADDR
+#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc
+#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL
+#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L
+//RLC_GPU_IOV_UCODE_DATA
+#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SCRATCH_ADDR
+#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0
+#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9
+#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x000001FFL
+#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L
+//RLC_GPU_IOV_SCRATCH_DATA
+#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_F32_CNTL
+#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0
+#define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x00000001L
+#define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xFFFFFFFEL
+//RLC_GPU_IOV_F32_RESET
+#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0
+#define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x00000001L
+#define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xFFFFFFFEL
+//RLC_GPU_IOV_SDMA0_STATUS
+#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9
+#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd
+#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x00000001L
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0x000000FEL
+#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x00000100L
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0x00000E00L
+#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x00001000L
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xFFFFE000L
+//RLC_GPU_IOV_SDMA1_STATUS
+#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9
+#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd
+#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x00000001L
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0x000000FEL
+#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x00000100L
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0x00000E00L
+#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x00001000L
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xFFFFE000L
+//RLC_GPU_IOV_SMU_RESPONSE
+#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0
+#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_VIRT_RESET_REQ
+#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0
+#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10
+#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f
+#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0x0000FFFFL
+#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7FFF0000L
+#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000L
+//RLC_GPU_IOV_RLC_RESPONSE
+#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0
+#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_INT_DISABLE
+#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0
+#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_INT_FORCE
+#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0
+#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SDMA0_BUSY_STATUS
+#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SDMA1_BUSY_STATUS
+#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gccacind
+//GC_CAC_CNTL
+#define GC_CAC_CNTL__CAC_ENABLE__SHIFT 0x0
+#define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1
+#define GC_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11
+#define GC_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17
+#define GC_CAC_CNTL__UNUSED_0__SHIFT 0x1f
+#define GC_CAC_CNTL__CAC_ENABLE_MASK 0x00000001L
+#define GC_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL
+#define GC_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L
+#define GC_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L
+#define GC_CAC_CNTL__UNUSED_0_MASK 0x80000000L
+//GC_CAC_OVR_SEL
+#define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0
+#define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL
+//GC_CAC_OVR_VAL
+#define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0
+#define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL
+//GC_CAC_WEIGHT_BCI_0
+#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CB_0
+#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CB_1
+#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CBR_0
+#define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CBR_1
+#define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CP_0
+#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CP_1
+#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_CP_1__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CP_1__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_DB_0
+#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_DB_1
+#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_DBR_0
+#define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_DBR_1
+#define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_GDS_0
+#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_GDS_1
+#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_IA_0
+#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_IA_0__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_IA_0__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_LDS_0
+#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_LDS_1
+#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_PA_0
+#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_PC_0
+#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_PC_0__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_PC_0__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SC_0
+#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_SC_0__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SC_0__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SPI_0
+#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SPI_1
+#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SPI_2
+#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT 0x10
+#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SQ_0
+#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SQ_1
+#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SQ_2
+#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT 0x10
+#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SQ_3
+#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6__SHIFT 0x0
+#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7__SHIFT 0x10
+#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SQ_4
+#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8__SHIFT 0x0
+#define GC_CAC_WEIGHT_SQ_4__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SQ_4__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SX_0
+#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_SX_0__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SX_0__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SXRB_0
+#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TA_0
+#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_TA_0__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TA_0__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TCC_0
+#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TCC_1
+#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TCC_2
+#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_TCC_2__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TCC_2__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TCP_0
+#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TCP_1
+#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TCP_2
+#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_TCP_2__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TCP_2__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TD_0
+#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TD_1
+#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TD_2
+#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT 0x10
+#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_VGT_0
+#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_VGT_1
+#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_VGT_1__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_VGT_1__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_WD_0
+#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_WD_0__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_WD_0__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CU_0
+#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CU_1
+#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CU_2
+#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5__SHIFT 0x10
+#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CU_3
+#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6__SHIFT 0x0
+#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7__SHIFT 0x10
+#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CU_4
+#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8__SHIFT 0x0
+#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9__SHIFT 0x10
+#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CU_5
+#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10__SHIFT 0x0
+#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11__SHIFT 0x10
+#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CU_6
+#define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG12__SHIFT 0x0
+#define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG13__SHIFT 0x10
+#define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG12_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG13_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CU_7
+#define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG14__SHIFT 0x0
+#define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG15__SHIFT 0x10
+#define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG14_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG15_MASK 0xFFFF0000L
+//GC_CAC_ACC_BCI0
+#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CB0
+#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CB1
+#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CB2
+#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CB3
+#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CBR0
+#define GC_CAC_ACC_CBR0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CBR0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CBR1
+#define GC_CAC_ACC_CBR1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CBR1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CBR2
+#define GC_CAC_ACC_CBR2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CBR2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CBR3
+#define GC_CAC_ACC_CBR3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CBR3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CP0
+#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CP1
+#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CP2
+#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_DB0
+#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_DB1
+#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_DB2
+#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_DB3
+#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_DBR0
+#define GC_CAC_ACC_DBR0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_DBR0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_DBR1
+#define GC_CAC_ACC_DBR1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_DBR1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_DBR2
+#define GC_CAC_ACC_DBR2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_DBR2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_DBR3
+#define GC_CAC_ACC_DBR3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_DBR3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_GDS0
+#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_GDS1
+#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_GDS2
+#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_GDS3
+#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_IA0
+#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_LDS0
+#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_LDS1
+#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_LDS2
+#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_LDS3
+#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_PA0
+#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_PA1
+#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_PC0
+#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SC0
+#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SPI0
+#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SPI1
+#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SPI2
+#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SPI3
+#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SPI4
+#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SPI5
+#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_WEIGHT_UTCL2_ATCL2_0
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK 0xFFFF0000L
+//GC_CAC_ACC_EA0
+#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_EA1
+#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_EA2
+#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_EA3
+#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ATCL20
+#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_OVRD_EA
+#define GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT 0x6
+#define GC_CAC_OVRD_EA__OVRRD_SELECT_MASK 0x0000003FL
+#define GC_CAC_OVRD_EA__OVRRD_VALUE_MASK 0x00000FC0L
+//GC_CAC_OVRD_UTCL2_ATCL2
+#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT 0x5
+#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK 0x0000001FL
+#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK 0x000003E0L
+//GC_CAC_WEIGHT_EA_0
+#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_EA_1
+#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_RMI_0
+#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_RMI_0__UNUSED__SHIFT 0x10
+#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_RMI_0__UNUSED_MASK 0xFFFF0000L
+//GC_CAC_ACC_RMI0
+#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_OVRD_RMI
+#define GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_WEIGHT_UTCL2_ATCL2_1
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK 0xFFFF0000L
+//GC_CAC_ACC_UTCL2_ATCL21
+#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ATCL22
+#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ATCL23
+#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_EA4
+#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_EA5
+#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_WEIGHT_EA_2
+#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT 0x10
+#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK 0xFFFF0000L
+//GC_CAC_ACC_SQ0_LOWER
+#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ0_UPPER
+#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0__SHIFT 0x8
+#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0_MASK 0xFFFFFF00L
+//GC_CAC_ACC_SQ1_LOWER
+#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ1_UPPER
+#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0__SHIFT 0x8
+#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0_MASK 0xFFFFFF00L
+//GC_CAC_ACC_SQ2_LOWER
+#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ2_UPPER
+#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0__SHIFT 0x8
+#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0_MASK 0xFFFFFF00L
+//GC_CAC_ACC_SQ3_LOWER
+#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ3_UPPER
+#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0__SHIFT 0x8
+#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0_MASK 0xFFFFFF00L
+//GC_CAC_ACC_SQ4_LOWER
+#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ4_UPPER
+#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0__SHIFT 0x8
+#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0_MASK 0xFFFFFF00L
+//GC_CAC_ACC_SQ5_LOWER
+#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ5_UPPER
+#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0__SHIFT 0x8
+#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0_MASK 0xFFFFFF00L
+//GC_CAC_ACC_SQ6_LOWER
+#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ6_UPPER
+#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0__SHIFT 0x8
+#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0_MASK 0xFFFFFF00L
+//GC_CAC_ACC_SQ7_LOWER
+#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ7_UPPER
+#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0__SHIFT 0x8
+#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0_MASK 0xFFFFFF00L
+//GC_CAC_ACC_SQ8_LOWER
+#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ8_UPPER
+#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0__SHIFT 0x8
+#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0_MASK 0xFFFFFF00L
+//GC_CAC_ACC_SX0
+#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SXRB0
+#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SXRB1
+#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TA0
+#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCC0
+#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCC1
+#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCC2
+#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCC3
+#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCC4
+#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCP0
+#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCP1
+#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCP2
+#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCP3
+#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCP4
+#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD0
+#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD1
+#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD2
+#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD3
+#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD4
+#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD5
+#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_VGT0
+#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_VGT1
+#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_VGT2
+#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_WD0
+#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU0
+#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU1
+#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU2
+#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU3
+#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU4
+#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU5
+#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU6
+#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU7
+#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU8
+#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU9
+#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU10
+#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU11
+#define GC_CAC_ACC_CU11__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU11__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU12
+#define GC_CAC_ACC_CU12__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU12__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU13
+#define GC_CAC_ACC_CU13__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU13__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU14
+#define GC_CAC_ACC_CU14__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU14__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU15
+#define GC_CAC_ACC_CU15__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU15__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_OVRD_BCI
+#define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT 0x2
+#define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK 0x00000003L
+#define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK 0x0000000CL
+//GC_CAC_OVRD_CB
+#define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT 0x4
+#define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK 0x0000000FL
+#define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK 0x000000F0L
+//GC_CAC_OVRD_CBR
+#define GC_CAC_OVRD_CBR__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_CBR__OVRRD_VALUE__SHIFT 0x4
+#define GC_CAC_OVRD_CBR__OVRRD_SELECT_MASK 0x0000000FL
+#define GC_CAC_OVRD_CBR__OVRRD_VALUE_MASK 0x000000F0L
+//GC_CAC_OVRD_CP
+#define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT 0x3
+#define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK 0x00000007L
+#define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK 0x00000038L
+//GC_CAC_OVRD_DB
+#define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT 0x4
+#define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK 0x0000000FL
+#define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK 0x000000F0L
+//GC_CAC_OVRD_DBR
+#define GC_CAC_OVRD_DBR__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_DBR__OVRRD_VALUE__SHIFT 0x4
+#define GC_CAC_OVRD_DBR__OVRRD_SELECT_MASK 0x0000000FL
+#define GC_CAC_OVRD_DBR__OVRRD_VALUE_MASK 0x000000F0L
+//GC_CAC_OVRD_GDS
+#define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT 0x4
+#define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK 0x0000000FL
+#define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK 0x000000F0L
+//GC_CAC_OVRD_IA
+#define GC_CAC_OVRD_IA__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_IA__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_IA__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_IA__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_LDS
+#define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT 0x4
+#define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK 0x0000000FL
+#define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK 0x000000F0L
+//GC_CAC_OVRD_PA
+#define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT 0x2
+#define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK 0x00000003L
+#define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK 0x0000000CL
+//GC_CAC_OVRD_PC
+#define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_SC
+#define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_SPI
+#define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT 0x6
+#define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK 0x0000003FL
+#define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK 0x00000FC0L
+//GC_CAC_OVRD_CU
+#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_SQ
+#define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT 0x9
+#define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK 0x000001FFL
+#define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK 0x0003FE00L
+//GC_CAC_OVRD_SX
+#define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_SXRB
+#define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_TA
+#define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_TCC
+#define GC_CAC_OVRD_TCC__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_TCC__OVRRD_VALUE__SHIFT 0x5
+#define GC_CAC_OVRD_TCC__OVRRD_SELECT_MASK 0x0000001FL
+#define GC_CAC_OVRD_TCC__OVRRD_VALUE_MASK 0x000003E0L
+//GC_CAC_OVRD_TCP
+#define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT 0x5
+#define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK 0x0000001FL
+#define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK 0x000003E0L
+//GC_CAC_OVRD_TD
+#define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT 0x6
+#define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK 0x0000003FL
+#define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK 0x00000FC0L
+//GC_CAC_OVRD_VGT
+#define GC_CAC_OVRD_VGT__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_VGT__OVRRD_VALUE__SHIFT 0x3
+#define GC_CAC_OVRD_VGT__OVRRD_SELECT_MASK 0x00000007L
+#define GC_CAC_OVRD_VGT__OVRRD_VALUE_MASK 0x00000038L
+//GC_CAC_OVRD_WD
+#define GC_CAC_OVRD_WD__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_WD__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_WD__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_WD__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_ACC_BCI1
+#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_WEIGHT_UTCL2_ATCL2_2
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_ROUTER_0
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_ROUTER_1
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_ROUTER_2
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_ROUTER_3
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_ROUTER_4
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_VML2_0
+#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_VML2_1
+#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_VML2_2
+#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5_MASK 0xFFFF0000L
+//GC_CAC_ACC_UTCL2_ATCL24
+#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER0
+#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER1
+#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER2
+#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER3
+#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER4
+#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER5
+#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER6
+#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER7
+#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER8
+#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER9
+#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_VML20
+#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_VML21
+#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_VML22
+#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_VML23
+#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_VML24
+#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_OVRD_UTCL2_ROUTER
+#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT 0xa
+#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK 0x000003FFL
+#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK 0x000FFC00L
+//GC_CAC_OVRD_UTCL2_VML2
+#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT 0x5
+#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK 0x0000001FL
+#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK 0x000003E0L
+//GC_CAC_WEIGHT_UTCL2_WALKER_0
+#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_WALKER_1
+#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_WALKER_2
+#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5_MASK 0xFFFF0000L
+//GC_CAC_ACC_UTCL2_WALKER0
+#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_WALKER1
+#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_WALKER2
+#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_WALKER3
+#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_WALKER4
+#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_OVRD_UTCL2_WALKER
+#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT 0x5
+#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK 0x0000001FL
+#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK 0x000003E0L
+
+
+// addressBlock: secacind
+//SE_CAC_CNTL
+#define SE_CAC_CNTL__CAC_ENABLE__SHIFT 0x0
+#define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1
+#define SE_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11
+#define SE_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17
+#define SE_CAC_CNTL__UNUSED_0__SHIFT 0x1f
+#define SE_CAC_CNTL__CAC_ENABLE_MASK 0x00000001L
+#define SE_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL
+#define SE_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L
+#define SE_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L
+#define SE_CAC_CNTL__UNUSED_0_MASK 0x80000000L
+//SE_CAC_OVR_SEL
+#define SE_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0
+#define SE_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL
+//SE_CAC_OVR_VAL
+#define SE_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0
+#define SE_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL
+
+
+// addressBlock: sqind
+//SQ_WAVE_MODE
+#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0
+#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4
+#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8
+#define SQ_WAVE_MODE__IEEE__SHIFT 0x9
+#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa
+#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0xb
+#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc
+#define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x17
+#define SQ_WAVE_MODE__POPS_PACKER0__SHIFT 0x18
+#define SQ_WAVE_MODE__POPS_PACKER1__SHIFT 0x19
+#define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x1a
+#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b
+#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c
+#define SQ_WAVE_MODE__CSP__SHIFT 0x1d
+#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000FL
+#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000F0L
+#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L
+#define SQ_WAVE_MODE__IEEE_MASK 0x00000200L
+#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L
+#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x00000800L
+#define SQ_WAVE_MODE__EXCP_EN_MASK 0x001FF000L
+#define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L
+#define SQ_WAVE_MODE__POPS_PACKER0_MASK 0x01000000L
+#define SQ_WAVE_MODE__POPS_PACKER1_MASK 0x02000000L
+#define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x04000000L
+#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x08000000L
+#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L
+#define SQ_WAVE_MODE__CSP_MASK 0xE0000000L
+//SQ_WAVE_STATUS
+#define SQ_WAVE_STATUS__SCC__SHIFT 0x0
+#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1
+#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3
+#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5
+#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6
+#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7
+#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8
+#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9
+#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa
+#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb
+#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc
+#define SQ_WAVE_STATUS__HALT__SHIFT 0xd
+#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe
+#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf
+#define SQ_WAVE_STATUS__VALID__SHIFT 0x10
+#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11
+#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12
+#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13
+#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14
+#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x15
+#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16
+#define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x17
+#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b
+#define SQ_WAVE_STATUS__SCC_MASK 0x00000001L
+#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L
+#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x00000018L
+#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L
+#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L
+#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L
+#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L
+#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L
+#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L
+#define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L
+#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L
+#define SQ_WAVE_STATUS__HALT_MASK 0x00002000L
+#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L
+#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x00008000L
+#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L
+#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L
+#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L
+#define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L
+#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x00100000L
+#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x00200000L
+#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x00400000L
+#define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L
+#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L
+//SQ_WAVE_TRAPSTS
+#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0
+#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa
+#define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT 0xb
+#define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT 0xc
+#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10
+#define SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT 0x1c
+#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d
+#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x000001FFL
+#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x00000400L
+#define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK 0x00000800L
+#define SQ_WAVE_TRAPSTS__EXCP_HI_MASK 0x00007000L
+#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x003F0000L
+#define SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK 0x10000000L
+#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xE0000000L
+//SQ_WAVE_HW_ID
+#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0
+#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4
+#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6
+#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8
+#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc
+#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd
+#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10
+#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14
+#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18
+#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b
+#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e
+#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0x0000000FL
+#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x00000030L
+#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0x000000C0L
+#define SQ_WAVE_HW_ID__CU_ID_MASK 0x00000F00L
+#define SQ_WAVE_HW_ID__SH_ID_MASK 0x00001000L
+#define SQ_WAVE_HW_ID__SE_ID_MASK 0x00006000L
+#define SQ_WAVE_HW_ID__TG_ID_MASK 0x000F0000L
+#define SQ_WAVE_HW_ID__VM_ID_MASK 0x00F00000L
+#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x07000000L
+#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000L
+#define SQ_WAVE_HW_ID__ME_ID_MASK 0xC0000000L
+//SQ_WAVE_GPR_ALLOC
+#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0
+#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8
+#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10
+#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18
+#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x0000003FL
+#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x00003F00L
+#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x003F0000L
+#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0F000000L
+//SQ_WAVE_LDS_ALLOC
+#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0
+#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc
+#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000000FFL
+#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001FF000L
+//SQ_WAVE_IB_STS
+#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0
+#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4
+#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8
+#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc
+#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf
+#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10
+#define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT 0x16
+#define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000FL
+#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L
+#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00000F00L
+#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x00007000L
+#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x00008000L
+#define SQ_WAVE_IB_STS__RCNT_MASK 0x001F0000L
+#define SQ_WAVE_IB_STS__VM_CNT_HI_MASK 0x00C00000L
+//SQ_WAVE_PC_LO
+#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0
+#define SQ_WAVE_PC_LO__PC_LO_MASK 0xFFFFFFFFL
+//SQ_WAVE_PC_HI
+#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0
+#define SQ_WAVE_PC_HI__PC_HI_MASK 0x0000FFFFL
+//SQ_WAVE_INST_DW0
+#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0
+#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xFFFFFFFFL
+//SQ_WAVE_INST_DW1
+#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0
+#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xFFFFFFFFL
+//SQ_WAVE_IB_DBG0
+#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0
+#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3
+#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4
+#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5
+#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8
+#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa
+#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10
+#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18
+#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a
+#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b
+#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d
+#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e
+#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI__SHIFT 0x1f
+#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x00000007L
+#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x00000008L
+#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x00000010L
+#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0x000000E0L
+#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x00000300L
+#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0x00000C00L
+#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x000F0000L
+#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x03000000L
+#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x04000000L
+#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000L
+#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000L
+#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000L
+#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI_MASK 0x80000000L
+//SQ_WAVE_IB_DBG1
+#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0
+#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1
+#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2
+#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4
+#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0xb
+#define SQ_WAVE_IB_DBG1__RCNT__SHIFT 0x12
+#define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x19
+#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x00000001L
+#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x00000002L
+#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x00000004L
+#define SQ_WAVE_IB_DBG1__XCNT_MASK 0x000001F0L
+#define SQ_WAVE_IB_DBG1__QCNT_MASK 0x0000F800L
+#define SQ_WAVE_IB_DBG1__RCNT_MASK 0x007C0000L
+#define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xFE000000L
+//SQ_WAVE_FLUSH_IB
+#define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x0
+#define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP0
+#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP0__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP1
+#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP1__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP2
+#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP2__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP3
+#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP3__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP4
+#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP4__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP5
+#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP5__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP6
+#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP6__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP7
+#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP7__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP8
+#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP8__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP9
+#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP9__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP10
+#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP10__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP11
+#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP11__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP12
+#define SQ_WAVE_TTMP12__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP12__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP13
+#define SQ_WAVE_TTMP13__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP13__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP14
+#define SQ_WAVE_TTMP14__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP14__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP15
+#define SQ_WAVE_TTMP15__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP15__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_M0
+#define SQ_WAVE_M0__M0__SHIFT 0x0
+#define SQ_WAVE_M0__M0_MASK 0xFFFFFFFFL
+//SQ_WAVE_EXEC_LO
+#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0
+#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xFFFFFFFFL
+//SQ_WAVE_EXEC_HI
+#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0
+#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xFFFFFFFFL
+//SQ_INTERRUPT_WORD_AUTO_CTXID
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0x0
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 0x1
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 0x2
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 0x3
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 0x4
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 0x5
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 0x6
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 0x7
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 0x8
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 0x18
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 0x1a
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x0000001L
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x0000002L
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x0000004L
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x0000008L
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x0000010L
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x0000020L
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x0000040L
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x0000080L
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x0000100L
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x3000000L
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0xC000000L
+//SQ_INTERRUPT_WORD_AUTO_HI
+#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID__SHIFT 0x8
+#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT 0xa
+#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID_MASK 0x300L
+#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING_MASK 0xC00L
+//SQ_INTERRUPT_WORD_AUTO_LO
+#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE__SHIFT 0x0
+#define SQ_INTERRUPT_WORD_AUTO_LO__WLT__SHIFT 0x1
+#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL__SHIFT 0x2
+#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP__SHIFT 0x3
+#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP__SHIFT 0x4
+#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW__SHIFT 0x5
+#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW__SHIFT 0x6
+#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW__SHIFT 0x7
+#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR__SHIFT 0x8
+#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_MASK 0x001L
+#define SQ_INTERRUPT_WORD_AUTO_LO__WLT_MASK 0x002L
+#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL_MASK 0x004L
+#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP_MASK 0x008L
+#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP_MASK 0x010L
+#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW_MASK 0x020L
+#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW_MASK 0x040L
+#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW_MASK 0x080L
+#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR_MASK 0x100L
+//SQ_INTERRUPT_WORD_CMN_CTXID
+#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID__SHIFT 0x18
+#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING__SHIFT 0x1a
+#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID_MASK 0x3000000L
+#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING_MASK 0xC000000L
+//SQ_INTERRUPT_WORD_CMN_HI
+#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID__SHIFT 0x8
+#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT 0xa
+#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID_MASK 0x300L
+#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING_MASK 0xC00L
+//SQ_INTERRUPT_WORD_WAVE_CTXID
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0x0
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 0xc
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 0xd
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 0xe
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 0x12
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 0x14
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 0x18
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 0x1a
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x0000FFFL
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x0001000L
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x0002000L
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x003C000L
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x00C0000L
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x0F00000L
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x3000000L
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0xC000000L
+//SQ_INTERRUPT_WORD_WAVE_HI
+#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID__SHIFT 0x0
+#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID__SHIFT 0x4
+#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID__SHIFT 0x8
+#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT 0xa
+#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID_MASK 0x00FL
+#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID_MASK 0x0F0L
+#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID_MASK 0x300L
+#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING_MASK 0xC00L
+//SQ_INTERRUPT_WORD_WAVE_LO
+#define SQ_INTERRUPT_WORD_WAVE_LO__DATA__SHIFT 0x0
+#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID__SHIFT 0x18
+#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV__SHIFT 0x19
+#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID__SHIFT 0x1a
+#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID__SHIFT 0x1e
+#define SQ_INTERRUPT_WORD_WAVE_LO__DATA_MASK 0x00FFFFFFL
+#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID_MASK 0x01000000L
+#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV_MASK 0x02000000L
+#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID_MASK 0x3C000000L
+#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID_MASK 0xC0000000L
+
+
+// addressBlock: didtind
+//DIDT_SQ_CTRL0
+#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1
+#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
+#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
+#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
+#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
+#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
+#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
+#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
+#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
+#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
+#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x1b
+#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
+#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0x00000006L
+#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
+#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
+#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
+#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
+#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
+#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
+#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
+#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
+#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
+#define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xF8000000L
+//DIDT_SQ_CTRL1
+#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0x0000FFFFL
+#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xFFFF0000L
+//DIDT_SQ_CTRL2
+#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_SQ_CTRL2__UNUSED_0__SHIFT 0xe
+#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_SQ_CTRL2__UNUSED_1__SHIFT 0x1a
+#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_SQ_CTRL2__UNUSED_2__SHIFT 0x1f
+#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
+#define DIDT_SQ_CTRL2__UNUSED_0_MASK 0x0000C000L
+#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
+#define DIDT_SQ_CTRL2__UNUSED_1_MASK 0x04000000L
+#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
+#define DIDT_SQ_CTRL2__UNUSED_2_MASK 0x80000000L
+//DIDT_SQ_STALL_CTRL
+#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
+#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
+#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
+#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
+#define DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT 0x18
+#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
+#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
+#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
+#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
+#define DIDT_SQ_STALL_CTRL__UNUSED_0_MASK 0xFF000000L
+//DIDT_SQ_TUNING_CTRL
+#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
+#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
+#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
+#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
+//DIDT_SQ_STALL_AUTO_RELEASE_CTRL
+#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
+#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
+//DIDT_SQ_CTRL3
+#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
+#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
+#define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT 0x2
+#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
+#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
+#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
+#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
+#define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
+#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
+#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
+#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
+#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
+#define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
+#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
+#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
+#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
+#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
+#define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
+#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
+#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
+//DIDT_SQ_STALL_PATTERN_1_2
+#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
+#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
+#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
+#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
+#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
+//DIDT_SQ_STALL_PATTERN_3_4
+#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
+#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
+#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
+#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
+#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
+//DIDT_SQ_STALL_PATTERN_5_6
+#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
+#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
+#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
+#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
+#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
+//DIDT_SQ_STALL_PATTERN_7
+#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_SQ_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
+#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
+#define DIDT_SQ_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
+//DIDT_SQ_WEIGHT0_3
+#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
+#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
+#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
+#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
+//DIDT_SQ_WEIGHT4_7
+#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
+#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
+#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
+#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
+//DIDT_SQ_WEIGHT8_11
+#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
+#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
+#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
+#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
+//DIDT_SQ_EDC_CTRL
+#define DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT 0x0
+#define DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
+#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
+#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
+#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
+#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
+#define DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
+#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
+#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
+#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_SQ_EDC_CTRL__UNUSED_0__SHIFT 0x17
+#define DIDT_SQ_EDC_CTRL__EDC_EN_MASK 0x00000001L
+#define DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
+#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
+#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
+#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
+#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
+#define DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
+#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
+#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
+#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_SQ_EDC_CTRL__UNUSED_0_MASK 0xFF800000L
+//DIDT_SQ_EDC_THRESHOLD
+#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
+#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
+//DIDT_SQ_EDC_STALL_PATTERN_1_2
+#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
+#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
+#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
+#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
+#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
+//DIDT_SQ_EDC_STALL_PATTERN_3_4
+#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
+#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
+#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
+#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
+#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
+//DIDT_SQ_EDC_STALL_PATTERN_5_6
+#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
+#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
+#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
+#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
+#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
+//DIDT_SQ_EDC_STALL_PATTERN_7
+#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
+#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
+#define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
+//DIDT_SQ_EDC_STATUS
+#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
+#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
+#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
+#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
+//DIDT_SQ_EDC_STALL_DELAY_1
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT 0x8
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT 0x10
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT 0x18
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK 0x000000FFL
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK 0x0000FF00L
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK 0x00FF0000L
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK 0xFF000000L
+//DIDT_SQ_EDC_STALL_DELAY_2
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT 0x8
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT 0x10
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT 0x18
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK 0x000000FFL
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK 0x0000FF00L
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK 0x00FF0000L
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK 0xFF000000L
+//DIDT_SQ_EDC_STALL_DELAY_3
+#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT 0x8
+#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT 0x10
+#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11__SHIFT 0x18
+#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK 0x000000FFL
+#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK 0x0000FF00L
+#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK 0x00FF0000L
+#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11_MASK 0xFF000000L
+//DIDT_SQ_EDC_STALL_DELAY_4
+#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13__SHIFT 0x8
+#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14__SHIFT 0x10
+#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15__SHIFT 0x18
+#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK 0x000000FFL
+#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13_MASK 0x0000FF00L
+#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14_MASK 0x00FF0000L
+#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15_MASK 0xFF000000L
+//DIDT_SQ_EDC_OVERFLOW
+#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
+#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
+#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
+#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
+//DIDT_SQ_EDC_ROLLING_POWER_DELTA
+#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
+#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
+//DIDT_DB_CTRL0
+#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1
+#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
+#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
+#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
+#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
+#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
+#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
+#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
+#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
+#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
+#define DIDT_DB_CTRL0__UNUSED_0__SHIFT 0x1b
+#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
+#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0x00000006L
+#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
+#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
+#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
+#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
+#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
+#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
+#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
+#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
+#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
+#define DIDT_DB_CTRL0__UNUSED_0_MASK 0xF8000000L
+//DIDT_DB_CTRL1
+#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_DB_CTRL1__MIN_POWER_MASK 0x0000FFFFL
+#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xFFFF0000L
+//DIDT_DB_CTRL2
+#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_DB_CTRL2__UNUSED_0__SHIFT 0xe
+#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_DB_CTRL2__UNUSED_1__SHIFT 0x1a
+#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_DB_CTRL2__UNUSED_2__SHIFT 0x1f
+#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
+#define DIDT_DB_CTRL2__UNUSED_0_MASK 0x0000C000L
+#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
+#define DIDT_DB_CTRL2__UNUSED_1_MASK 0x04000000L
+#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
+#define DIDT_DB_CTRL2__UNUSED_2_MASK 0x80000000L
+//DIDT_DB_STALL_CTRL
+#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
+#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
+#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
+#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
+#define DIDT_DB_STALL_CTRL__UNUSED_0__SHIFT 0x18
+#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
+#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
+#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
+#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
+#define DIDT_DB_STALL_CTRL__UNUSED_0_MASK 0xFF000000L
+//DIDT_DB_TUNING_CTRL
+#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
+#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
+#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
+#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
+//DIDT_DB_STALL_AUTO_RELEASE_CTRL
+#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
+#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
+//DIDT_DB_CTRL3
+#define DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
+#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
+#define DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT 0x2
+#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
+#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
+#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
+#define DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
+#define DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
+#define DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
+#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
+#define DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
+#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
+#define DIDT_DB_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
+#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
+#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
+#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
+#define DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
+#define DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
+#define DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
+#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
+//DIDT_DB_STALL_PATTERN_1_2
+#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
+#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
+#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
+#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
+#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
+//DIDT_DB_STALL_PATTERN_3_4
+#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
+#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
+#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
+#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
+#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
+//DIDT_DB_STALL_PATTERN_5_6
+#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
+#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
+#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
+#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
+#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
+//DIDT_DB_STALL_PATTERN_7
+#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_DB_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
+#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
+#define DIDT_DB_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
+//DIDT_DB_WEIGHT0_3
+#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
+#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
+#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
+#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
+//DIDT_DB_WEIGHT4_7
+#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
+#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
+#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
+#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
+//DIDT_DB_WEIGHT8_11
+#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
+#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
+#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
+#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
+//DIDT_DB_EDC_CTRL
+#define DIDT_DB_EDC_CTRL__EDC_EN__SHIFT 0x0
+#define DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
+#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
+#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
+#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
+#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
+#define DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
+#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
+#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
+#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_DB_EDC_CTRL__UNUSED_0__SHIFT 0x17
+#define DIDT_DB_EDC_CTRL__EDC_EN_MASK 0x00000001L
+#define DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
+#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
+#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
+#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
+#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
+#define DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
+#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
+#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
+#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_DB_EDC_CTRL__UNUSED_0_MASK 0xFF800000L
+//DIDT_DB_EDC_THRESHOLD
+#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
+#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
+//DIDT_DB_EDC_STALL_PATTERN_1_2
+#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
+#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
+#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
+#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
+#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
+//DIDT_DB_EDC_STALL_PATTERN_3_4
+#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
+#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
+#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
+#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
+#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
+//DIDT_DB_EDC_STALL_PATTERN_5_6
+#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
+#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
+#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
+#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
+#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
+//DIDT_DB_EDC_STALL_PATTERN_7
+#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
+#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
+#define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
+//DIDT_DB_EDC_STATUS
+#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
+#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
+#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
+#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
+//DIDT_DB_EDC_STALL_DELAY_1
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT 0x0
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT 0x6
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2__SHIFT 0xc
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3__SHIFT 0x12
+#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK 0x0000003FL
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK 0x00000FC0L
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2_MASK 0x0003F000L
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3_MASK 0x00FC0000L
+#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L
+//DIDT_DB_EDC_OVERFLOW
+#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
+#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
+#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
+#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
+//DIDT_DB_EDC_ROLLING_POWER_DELTA
+#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
+#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
+//DIDT_TD_CTRL0
+#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1
+#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
+#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
+#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
+#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
+#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
+#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
+#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
+#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
+#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
+#define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x1b
+#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
+#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0x00000006L
+#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
+#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
+#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
+#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
+#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
+#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
+#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
+#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
+#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
+#define DIDT_TD_CTRL0__UNUSED_0_MASK 0xF8000000L
+//DIDT_TD_CTRL1
+#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_TD_CTRL1__MIN_POWER_MASK 0x0000FFFFL
+#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xFFFF0000L
+//DIDT_TD_CTRL2
+#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_TD_CTRL2__UNUSED_0__SHIFT 0xe
+#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_TD_CTRL2__UNUSED_1__SHIFT 0x1a
+#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_TD_CTRL2__UNUSED_2__SHIFT 0x1f
+#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
+#define DIDT_TD_CTRL2__UNUSED_0_MASK 0x0000C000L
+#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
+#define DIDT_TD_CTRL2__UNUSED_1_MASK 0x04000000L
+#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
+#define DIDT_TD_CTRL2__UNUSED_2_MASK 0x80000000L
+//DIDT_TD_STALL_CTRL
+#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
+#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
+#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
+#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
+#define DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT 0x18
+#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
+#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
+#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
+#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
+#define DIDT_TD_STALL_CTRL__UNUSED_0_MASK 0xFF000000L
+//DIDT_TD_TUNING_CTRL
+#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
+#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
+#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
+#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
+//DIDT_TD_STALL_AUTO_RELEASE_CTRL
+#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
+#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
+//DIDT_TD_CTRL3
+#define DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
+#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
+#define DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT 0x2
+#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
+#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
+#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
+#define DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
+#define DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
+#define DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
+#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
+#define DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
+#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
+#define DIDT_TD_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
+#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
+#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
+#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
+#define DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
+#define DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
+#define DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
+#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
+//DIDT_TD_STALL_PATTERN_1_2
+#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
+#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
+#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
+#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
+#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
+//DIDT_TD_STALL_PATTERN_3_4
+#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
+#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
+#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
+#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
+#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
+//DIDT_TD_STALL_PATTERN_5_6
+#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
+#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
+#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
+#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
+#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
+//DIDT_TD_STALL_PATTERN_7
+#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_TD_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
+#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
+#define DIDT_TD_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
+//DIDT_TD_WEIGHT0_3
+#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
+#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
+#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
+#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
+//DIDT_TD_WEIGHT4_7
+#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
+#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
+#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
+#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
+//DIDT_TD_WEIGHT8_11
+#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
+#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
+#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
+#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
+//DIDT_TD_EDC_CTRL
+#define DIDT_TD_EDC_CTRL__EDC_EN__SHIFT 0x0
+#define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
+#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
+#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
+#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
+#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
+#define DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
+#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
+#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
+#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_TD_EDC_CTRL__UNUSED_0__SHIFT 0x17
+#define DIDT_TD_EDC_CTRL__EDC_EN_MASK 0x00000001L
+#define DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
+#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
+#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
+#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
+#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
+#define DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
+#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
+#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
+#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_TD_EDC_CTRL__UNUSED_0_MASK 0xFF800000L
+//DIDT_TD_EDC_THRESHOLD
+#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
+#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
+//DIDT_TD_EDC_STALL_PATTERN_1_2
+#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
+#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
+#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
+#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
+#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
+//DIDT_TD_EDC_STALL_PATTERN_3_4
+#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
+#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
+#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
+#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
+#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
+//DIDT_TD_EDC_STALL_PATTERN_5_6
+#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
+#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
+#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
+#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
+#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
+//DIDT_TD_EDC_STALL_PATTERN_7
+#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
+#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
+#define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
+//DIDT_TD_EDC_STATUS
+#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
+#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
+#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
+#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
+//DIDT_TD_EDC_STALL_DELAY_1
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT 0x8
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT 0x10
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT 0x18
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK 0x000000FFL
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK 0x0000FF00L
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK 0x00FF0000L
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK 0xFF000000L
+//DIDT_TD_EDC_STALL_DELAY_2
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5__SHIFT 0x8
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6__SHIFT 0x10
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7__SHIFT 0x18
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK 0x000000FFL
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5_MASK 0x0000FF00L
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6_MASK 0x00FF0000L
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7_MASK 0xFF000000L
+//DIDT_TD_EDC_STALL_DELAY_3
+#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9__SHIFT 0x8
+#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10__SHIFT 0x10
+#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD11__SHIFT 0x18
+#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8_MASK 0x000000FFL
+#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9_MASK 0x0000FF00L
+#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10_MASK 0x00FF0000L
+#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD11_MASK 0xFF000000L
+//DIDT_TD_EDC_STALL_DELAY_4
+#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD12__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD13__SHIFT 0x8
+#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD14__SHIFT 0x10
+#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD15__SHIFT 0x18
+#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD12_MASK 0x000000FFL
+#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD13_MASK 0x0000FF00L
+#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD14_MASK 0x00FF0000L
+#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD15_MASK 0xFF000000L
+//DIDT_TD_EDC_OVERFLOW
+#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
+#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
+#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
+#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
+//DIDT_TD_EDC_ROLLING_POWER_DELTA
+#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
+#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
+//DIDT_TCP_CTRL0
+#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1
+#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
+#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
+#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
+#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
+#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
+#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
+#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
+#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
+#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
+#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x1b
+#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
+#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0x00000006L
+#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
+#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
+#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
+#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
+#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
+#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
+#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
+#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
+#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
+#define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xF8000000L
+//DIDT_TCP_CTRL1
+#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0x0000FFFFL
+#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xFFFF0000L
+//DIDT_TCP_CTRL2
+#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_TCP_CTRL2__UNUSED_0__SHIFT 0xe
+#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_TCP_CTRL2__UNUSED_1__SHIFT 0x1a
+#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_TCP_CTRL2__UNUSED_2__SHIFT 0x1f
+#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
+#define DIDT_TCP_CTRL2__UNUSED_0_MASK 0x0000C000L
+#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
+#define DIDT_TCP_CTRL2__UNUSED_1_MASK 0x04000000L
+#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
+#define DIDT_TCP_CTRL2__UNUSED_2_MASK 0x80000000L
+//DIDT_TCP_STALL_CTRL
+#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
+#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
+#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
+#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
+#define DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT 0x18
+#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
+#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
+#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
+#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
+#define DIDT_TCP_STALL_CTRL__UNUSED_0_MASK 0xFF000000L
+//DIDT_TCP_TUNING_CTRL
+#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
+#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
+#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
+#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
+//DIDT_TCP_STALL_AUTO_RELEASE_CTRL
+#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
+#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
+//DIDT_TCP_CTRL3
+#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
+#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
+#define DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT 0x2
+#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
+#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
+#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
+#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
+#define DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
+#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
+#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
+#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
+#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
+#define DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
+#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
+#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
+#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
+#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
+#define DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
+#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
+#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
+//DIDT_TCP_STALL_PATTERN_1_2
+#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
+#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
+#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
+#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
+#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
+//DIDT_TCP_STALL_PATTERN_3_4
+#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
+#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
+#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
+#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
+#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
+//DIDT_TCP_STALL_PATTERN_5_6
+#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
+#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
+#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
+#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
+#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
+//DIDT_TCP_STALL_PATTERN_7
+#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_TCP_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
+#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
+#define DIDT_TCP_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
+//DIDT_TCP_WEIGHT0_3
+#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
+#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
+#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
+#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
+//DIDT_TCP_WEIGHT4_7
+#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
+#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
+#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
+#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
+//DIDT_TCP_WEIGHT8_11
+#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
+#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
+#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
+#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
+//DIDT_TCP_EDC_CTRL
+#define DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT 0x0
+#define DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
+#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
+#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
+#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
+#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
+#define DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
+#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
+#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
+#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_TCP_EDC_CTRL__UNUSED_0__SHIFT 0x17
+#define DIDT_TCP_EDC_CTRL__EDC_EN_MASK 0x00000001L
+#define DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
+#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
+#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
+#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
+#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
+#define DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
+#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
+#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
+#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_TCP_EDC_CTRL__UNUSED_0_MASK 0xFF800000L
+//DIDT_TCP_EDC_THRESHOLD
+#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
+#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
+//DIDT_TCP_EDC_STALL_PATTERN_1_2
+#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
+#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
+#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
+#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
+#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
+//DIDT_TCP_EDC_STALL_PATTERN_3_4
+#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
+#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
+#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
+#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
+#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
+//DIDT_TCP_EDC_STALL_PATTERN_5_6
+#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
+#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
+#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
+#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
+#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
+//DIDT_TCP_EDC_STALL_PATTERN_7
+#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
+#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
+#define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
+//DIDT_TCP_EDC_STATUS
+#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
+#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
+#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
+#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
+//DIDT_TCP_EDC_STALL_DELAY_1
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT 0x8
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT 0x10
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT 0x18
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK 0x000000FFL
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK 0x0000FF00L
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK 0x00FF0000L
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK 0xFF000000L
+//DIDT_TCP_EDC_STALL_DELAY_2
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5__SHIFT 0x8
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6__SHIFT 0x10
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7__SHIFT 0x18
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK 0x000000FFL
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5_MASK 0x0000FF00L
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6_MASK 0x00FF0000L
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7_MASK 0xFF000000L
+//DIDT_TCP_EDC_STALL_DELAY_3
+#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9__SHIFT 0x8
+#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10__SHIFT 0x10
+#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP11__SHIFT 0x18
+#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8_MASK 0x000000FFL
+#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9_MASK 0x0000FF00L
+#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10_MASK 0x00FF0000L
+#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP11_MASK 0xFF000000L
+//DIDT_TCP_EDC_STALL_DELAY_4
+#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP12__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP13__SHIFT 0x8
+#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP14__SHIFT 0x10
+#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP15__SHIFT 0x18
+#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP12_MASK 0x000000FFL
+#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP13_MASK 0x0000FF00L
+#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP14_MASK 0x00FF0000L
+#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP15_MASK 0xFF000000L
+//DIDT_TCP_EDC_OVERFLOW
+#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
+#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
+#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
+#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
+//DIDT_TCP_EDC_ROLLING_POWER_DELTA
+#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
+#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
+//DIDT_DBR_CTRL0
+#define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT 0x1
+#define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
+#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
+#define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
+#define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
+#define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
+#define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
+#define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
+#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
+#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
+#define DIDT_DBR_CTRL0__UNUSED_0__SHIFT 0x1b
+#define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
+#define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK 0x00000006L
+#define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
+#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
+#define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
+#define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
+#define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
+#define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
+#define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
+#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
+#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
+#define DIDT_DBR_CTRL0__UNUSED_0_MASK 0xF8000000L
+//DIDT_DBR_CTRL1
+#define DIDT_DBR_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_DBR_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_DBR_CTRL1__MIN_POWER_MASK 0x0000FFFFL
+#define DIDT_DBR_CTRL1__MAX_POWER_MASK 0xFFFF0000L
+//DIDT_DBR_CTRL2
+#define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_DBR_CTRL2__UNUSED_0__SHIFT 0xe
+#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_DBR_CTRL2__UNUSED_1__SHIFT 0x1a
+#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_DBR_CTRL2__UNUSED_2__SHIFT 0x1f
+#define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
+#define DIDT_DBR_CTRL2__UNUSED_0_MASK 0x0000C000L
+#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
+#define DIDT_DBR_CTRL2__UNUSED_1_MASK 0x04000000L
+#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
+#define DIDT_DBR_CTRL2__UNUSED_2_MASK 0x80000000L
+//DIDT_DBR_STALL_CTRL
+#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
+#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
+#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
+#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
+#define DIDT_DBR_STALL_CTRL__UNUSED_0__SHIFT 0x18
+#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
+#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
+#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
+#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
+#define DIDT_DBR_STALL_CTRL__UNUSED_0_MASK 0xFF000000L
+//DIDT_DBR_TUNING_CTRL
+#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
+#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
+#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
+#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
+//DIDT_DBR_STALL_AUTO_RELEASE_CTRL
+#define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
+#define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
+//DIDT_DBR_CTRL3
+#define DIDT_DBR_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
+#define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
+#define DIDT_DBR_CTRL3__THROTTLE_POLICY__SHIFT 0x2
+#define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
+#define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
+#define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
+#define DIDT_DBR_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
+#define DIDT_DBR_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
+#define DIDT_DBR_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
+#define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
+#define DIDT_DBR_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
+#define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
+#define DIDT_DBR_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
+#define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
+#define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
+#define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
+#define DIDT_DBR_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
+#define DIDT_DBR_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
+#define DIDT_DBR_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
+#define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
+//DIDT_DBR_STALL_PATTERN_1_2
+#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
+#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
+#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
+#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
+#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
+//DIDT_DBR_STALL_PATTERN_3_4
+#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
+#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
+#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
+#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
+#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
+//DIDT_DBR_STALL_PATTERN_5_6
+#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
+#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
+#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
+#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
+#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
+//DIDT_DBR_STALL_PATTERN_7
+#define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_DBR_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
+#define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
+#define DIDT_DBR_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
+//DIDT_DBR_WEIGHT0_3
+#define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
+#define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
+#define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
+#define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
+//DIDT_DBR_WEIGHT4_7
+#define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
+#define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
+#define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
+#define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
+//DIDT_DBR_WEIGHT8_11
+#define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
+#define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
+#define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
+#define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
+//DIDT_DBR_EDC_CTRL
+#define DIDT_DBR_EDC_CTRL__EDC_EN__SHIFT 0x0
+#define DIDT_DBR_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
+#define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
+#define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
+#define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
+#define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
+#define DIDT_DBR_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
+#define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
+#define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
+#define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_DBR_EDC_CTRL__UNUSED_0__SHIFT 0x17
+#define DIDT_DBR_EDC_CTRL__EDC_EN_MASK 0x00000001L
+#define DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
+#define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
+#define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
+#define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
+#define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
+#define DIDT_DBR_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
+#define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
+#define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
+#define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_DBR_EDC_CTRL__UNUSED_0_MASK 0xFF800000L
+//DIDT_DBR_EDC_THRESHOLD
+#define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
+#define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
+//DIDT_DBR_EDC_STALL_PATTERN_1_2
+#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
+#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
+#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
+#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
+#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
+//DIDT_DBR_EDC_STALL_PATTERN_3_4
+#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
+#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
+#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
+#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
+#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
+//DIDT_DBR_EDC_STALL_PATTERN_5_6
+#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
+#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
+#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
+#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
+#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
+//DIDT_DBR_EDC_STALL_PATTERN_7
+#define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
+#define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
+#define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
+//DIDT_DBR_EDC_STATUS
+#define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
+#define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
+#define DIDT_DBR_EDC_STATUS__UNUSED_0__SHIFT 0x4
+#define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
+#define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
+#define DIDT_DBR_EDC_STATUS__UNUSED_0_MASK 0xFFFFFFF0L
+//DIDT_DBR_EDC_STALL_DELAY_1
+#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0__SHIFT 0x0
+#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR1__SHIFT 0x3
+#define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x6
+#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0_MASK 0x00000007L
+#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR1_MASK 0x00000038L
+#define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED_MASK 0xFFFFFFC0L
+//DIDT_DBR_EDC_OVERFLOW
+#define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
+#define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
+#define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
+#define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
+//DIDT_DBR_EDC_ROLLING_POWER_DELTA
+#define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
+#define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
+//DIDT_SQ_STALL_EVENT_COUNTER
+#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
+#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
+//DIDT_DB_STALL_EVENT_COUNTER
+#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
+#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
+//DIDT_TD_STALL_EVENT_COUNTER
+#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
+#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
+//DIDT_TCP_STALL_EVENT_COUNTER
+#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
+#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
+//DIDT_DBR_STALL_EVENT_COUNTER
+#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
+#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
+
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h
new file mode 100644
index 000000000000..864690cc910a
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _hdp_4_0_DEFAULT_HEADER
+#define _hdp_4_0_DEFAULT_HEADER
+
+
+// addressBlock: hdp_hdpdec
+#define mmHDP_MMHUB_TLVL_DEFAULT 0x00006666
+#define mmHDP_MMHUB_UNITID_DEFAULT 0x00000000
+#define mmHDP_NONSURFACE_BASE_DEFAULT 0x00000000
+#define mmHDP_NONSURFACE_INFO_DEFAULT 0x00000000
+#define mmHDP_NONSURFACE_BASE_HI_DEFAULT 0x00000000
+#define mmHDP_NONSURF_FLAGS_DEFAULT 0x00000000
+#define mmHDP_NONSURF_FLAGS_CLR_DEFAULT 0x00000000
+#define mmHDP_HOST_PATH_CNTL_DEFAULT 0x00680000
+#define mmHDP_SW_SEMAPHORE_DEFAULT 0x00000000
+#define mmHDP_DEBUG0_DEFAULT 0x00000000
+#define mmHDP_LAST_SURFACE_HIT_DEFAULT 0x00000003
+#define mmHDP_READ_CACHE_INVALIDATE_DEFAULT 0x00000000
+#define mmHDP_OUTSTANDING_REQ_DEFAULT 0x00000000
+#define mmHDP_MISC_CNTL_DEFAULT 0x2d200861
+#define mmHDP_MEM_POWER_LS_DEFAULT 0x00000901
+#define mmHDP_MMHUB_CNTL_DEFAULT 0x00000000
+#define mmHDP_EDC_CNT_DEFAULT 0x00000000
+#define mmHDP_VERSION_DEFAULT 0x00000400
+#define mmHDP_CLK_CNTL_DEFAULT 0x0000000f
+#define mmHDP_MEMIO_CNTL_DEFAULT 0x00000000
+#define mmHDP_MEMIO_ADDR_DEFAULT 0x00000000
+#define mmHDP_MEMIO_STATUS_DEFAULT 0x00000000
+#define mmHDP_MEMIO_WR_DATA_DEFAULT 0x00000000
+#define mmHDP_MEMIO_RD_DATA_DEFAULT 0xdeadbeef
+#define mmHDP_XDP_DIRECT2HDP_FIRST_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_FLUSH_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_BAR_UPDATE_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_3_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_4_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_5_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_6_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_7_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_8_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_9_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_10_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_11_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_12_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_13_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_14_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_15_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_16_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_17_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_18_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_19_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_20_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_21_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_22_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_23_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_24_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_25_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_26_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_27_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_28_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_29_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_30_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_31_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_32_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_33_DEFAULT 0x00000000
+#define mmHDP_XDP_D2H_RSVD_34_DEFAULT 0x00000000
+#define mmHDP_XDP_DIRECT2HDP_LAST_DEFAULT 0x00000000
+#define mmHDP_XDP_P2P_BAR_CFG_DEFAULT 0x0000000f
+#define mmHDP_XDP_P2P_MBX_OFFSET_DEFAULT 0x000011bc
+#define mmHDP_XDP_P2P_MBX_ADDR0_DEFAULT 0x00000000
+#define mmHDP_XDP_P2P_MBX_ADDR1_DEFAULT 0x00000000
+#define mmHDP_XDP_P2P_MBX_ADDR2_DEFAULT 0x00000000
+#define mmHDP_XDP_P2P_MBX_ADDR3_DEFAULT 0x00000000
+#define mmHDP_XDP_P2P_MBX_ADDR4_DEFAULT 0x00000000
+#define mmHDP_XDP_P2P_MBX_ADDR5_DEFAULT 0x00000000
+#define mmHDP_XDP_P2P_MBX_ADDR6_DEFAULT 0x00000000
+#define mmHDP_XDP_HDP_MBX_MC_CFG_DEFAULT 0x00000000
+#define mmHDP_XDP_HDP_MC_CFG_DEFAULT 0x00020000
+#define mmHDP_XDP_HST_CFG_DEFAULT 0x0000001b
+#define mmHDP_XDP_HDP_IPH_CFG_DEFAULT 0x00000000
+#define mmHDP_XDP_P2P_BAR0_DEFAULT 0x00000000
+#define mmHDP_XDP_P2P_BAR1_DEFAULT 0x00000000
+#define mmHDP_XDP_P2P_BAR2_DEFAULT 0x00000000
+#define mmHDP_XDP_P2P_BAR3_DEFAULT 0x00000000
+#define mmHDP_XDP_P2P_BAR4_DEFAULT 0x00000000
+#define mmHDP_XDP_P2P_BAR5_DEFAULT 0x00000000
+#define mmHDP_XDP_P2P_BAR6_DEFAULT 0x00000000
+#define mmHDP_XDP_P2P_BAR7_DEFAULT 0x00000000
+#define mmHDP_XDP_FLUSH_ARMED_STS_DEFAULT 0x00000000
+#define mmHDP_XDP_FLUSH_CNTR0_STS_DEFAULT 0x00000000
+#define mmHDP_XDP_BUSY_STS_DEFAULT 0x00000000
+#define mmHDP_XDP_STICKY_DEFAULT 0x00000000
+#define mmHDP_XDP_CHKN_DEFAULT 0x48584450
+#define mmHDP_XDP_BARS_ADDR_39_36_DEFAULT 0x00000000
+#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000
+#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000
+#define mmHDP_XDP_MMHUB_ERROR_DEFAULT 0x00000000
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h
new file mode 100644
index 000000000000..fbad771a569e
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h
@@ -0,0 +1,209 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _hdp_4_0_OFFSET_HEADER
+#define _hdp_4_0_OFFSET_HEADER
+
+
+
+// addressBlock: hdp_hdpdec
+// base address: 0x3c80
+#define mmHDP_MMHUB_TLVL 0x0000
+#define mmHDP_MMHUB_TLVL_BASE_IDX 0
+#define mmHDP_MMHUB_UNITID 0x0001
+#define mmHDP_MMHUB_UNITID_BASE_IDX 0
+#define mmHDP_NONSURFACE_BASE 0x0040
+#define mmHDP_NONSURFACE_BASE_BASE_IDX 0
+#define mmHDP_NONSURFACE_INFO 0x0041
+#define mmHDP_NONSURFACE_INFO_BASE_IDX 0
+#define mmHDP_NONSURFACE_BASE_HI 0x0042
+#define mmHDP_NONSURFACE_BASE_HI_BASE_IDX 0
+#define mmHDP_NONSURF_FLAGS 0x00c8
+#define mmHDP_NONSURF_FLAGS_BASE_IDX 0
+#define mmHDP_NONSURF_FLAGS_CLR 0x00c9
+#define mmHDP_NONSURF_FLAGS_CLR_BASE_IDX 0
+#define mmHDP_HOST_PATH_CNTL 0x00cc
+#define mmHDP_HOST_PATH_CNTL_BASE_IDX 0
+#define mmHDP_SW_SEMAPHORE 0x00cd
+#define mmHDP_SW_SEMAPHORE_BASE_IDX 0
+#define mmHDP_DEBUG0 0x00ce
+#define mmHDP_DEBUG0_BASE_IDX 0
+#define mmHDP_LAST_SURFACE_HIT 0x00d0
+#define mmHDP_LAST_SURFACE_HIT_BASE_IDX 0
+#define mmHDP_READ_CACHE_INVALIDATE 0x00d1
+#define mmHDP_READ_CACHE_INVALIDATE_BASE_IDX 0
+#define mmHDP_OUTSTANDING_REQ 0x00d2
+#define mmHDP_OUTSTANDING_REQ_BASE_IDX 0
+#define mmHDP_MISC_CNTL 0x00d3
+#define mmHDP_MISC_CNTL_BASE_IDX 0
+#define mmHDP_MEM_POWER_LS 0x00d4
+#define mmHDP_MEM_POWER_LS_BASE_IDX 0
+#define mmHDP_MMHUB_CNTL 0x00d5
+#define mmHDP_MMHUB_CNTL_BASE_IDX 0
+#define mmHDP_EDC_CNT 0x00d6
+#define mmHDP_EDC_CNT_BASE_IDX 0
+#define mmHDP_VERSION 0x00d7
+#define mmHDP_VERSION_BASE_IDX 0
+#define mmHDP_CLK_CNTL 0x00d8
+#define mmHDP_CLK_CNTL_BASE_IDX 0
+#define mmHDP_MEMIO_CNTL 0x00f6
+#define mmHDP_MEMIO_CNTL_BASE_IDX 0
+#define mmHDP_MEMIO_ADDR 0x00f7
+#define mmHDP_MEMIO_ADDR_BASE_IDX 0
+#define mmHDP_MEMIO_STATUS 0x00f8
+#define mmHDP_MEMIO_STATUS_BASE_IDX 0
+#define mmHDP_MEMIO_WR_DATA 0x00f9
+#define mmHDP_MEMIO_WR_DATA_BASE_IDX 0
+#define mmHDP_MEMIO_RD_DATA 0x00fa
+#define mmHDP_MEMIO_RD_DATA_BASE_IDX 0
+#define mmHDP_XDP_DIRECT2HDP_FIRST 0x0100
+#define mmHDP_XDP_DIRECT2HDP_FIRST_BASE_IDX 0
+#define mmHDP_XDP_D2H_FLUSH 0x0101
+#define mmHDP_XDP_D2H_FLUSH_BASE_IDX 0
+#define mmHDP_XDP_D2H_BAR_UPDATE 0x0102
+#define mmHDP_XDP_D2H_BAR_UPDATE_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_3 0x0103
+#define mmHDP_XDP_D2H_RSVD_3_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_4 0x0104
+#define mmHDP_XDP_D2H_RSVD_4_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_5 0x0105
+#define mmHDP_XDP_D2H_RSVD_5_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_6 0x0106
+#define mmHDP_XDP_D2H_RSVD_6_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_7 0x0107
+#define mmHDP_XDP_D2H_RSVD_7_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_8 0x0108
+#define mmHDP_XDP_D2H_RSVD_8_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_9 0x0109
+#define mmHDP_XDP_D2H_RSVD_9_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_10 0x010a
+#define mmHDP_XDP_D2H_RSVD_10_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_11 0x010b
+#define mmHDP_XDP_D2H_RSVD_11_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_12 0x010c
+#define mmHDP_XDP_D2H_RSVD_12_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_13 0x010d
+#define mmHDP_XDP_D2H_RSVD_13_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_14 0x010e
+#define mmHDP_XDP_D2H_RSVD_14_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_15 0x010f
+#define mmHDP_XDP_D2H_RSVD_15_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_16 0x0110
+#define mmHDP_XDP_D2H_RSVD_16_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_17 0x0111
+#define mmHDP_XDP_D2H_RSVD_17_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_18 0x0112
+#define mmHDP_XDP_D2H_RSVD_18_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_19 0x0113
+#define mmHDP_XDP_D2H_RSVD_19_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_20 0x0114
+#define mmHDP_XDP_D2H_RSVD_20_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_21 0x0115
+#define mmHDP_XDP_D2H_RSVD_21_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_22 0x0116
+#define mmHDP_XDP_D2H_RSVD_22_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_23 0x0117
+#define mmHDP_XDP_D2H_RSVD_23_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_24 0x0118
+#define mmHDP_XDP_D2H_RSVD_24_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_25 0x0119
+#define mmHDP_XDP_D2H_RSVD_25_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_26 0x011a
+#define mmHDP_XDP_D2H_RSVD_26_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_27 0x011b
+#define mmHDP_XDP_D2H_RSVD_27_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_28 0x011c
+#define mmHDP_XDP_D2H_RSVD_28_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_29 0x011d
+#define mmHDP_XDP_D2H_RSVD_29_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_30 0x011e
+#define mmHDP_XDP_D2H_RSVD_30_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_31 0x011f
+#define mmHDP_XDP_D2H_RSVD_31_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_32 0x0120
+#define mmHDP_XDP_D2H_RSVD_32_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_33 0x0121
+#define mmHDP_XDP_D2H_RSVD_33_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_34 0x0122
+#define mmHDP_XDP_D2H_RSVD_34_BASE_IDX 0
+#define mmHDP_XDP_DIRECT2HDP_LAST 0x0123
+#define mmHDP_XDP_DIRECT2HDP_LAST_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR_CFG 0x0124
+#define mmHDP_XDP_P2P_BAR_CFG_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_OFFSET 0x0125
+#define mmHDP_XDP_P2P_MBX_OFFSET_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_ADDR0 0x0126
+#define mmHDP_XDP_P2P_MBX_ADDR0_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_ADDR1 0x0127
+#define mmHDP_XDP_P2P_MBX_ADDR1_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_ADDR2 0x0128
+#define mmHDP_XDP_P2P_MBX_ADDR2_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_ADDR3 0x0129
+#define mmHDP_XDP_P2P_MBX_ADDR3_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_ADDR4 0x012a
+#define mmHDP_XDP_P2P_MBX_ADDR4_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_ADDR5 0x012b
+#define mmHDP_XDP_P2P_MBX_ADDR5_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_ADDR6 0x012c
+#define mmHDP_XDP_P2P_MBX_ADDR6_BASE_IDX 0
+#define mmHDP_XDP_HDP_MBX_MC_CFG 0x012d
+#define mmHDP_XDP_HDP_MBX_MC_CFG_BASE_IDX 0
+#define mmHDP_XDP_HDP_MC_CFG 0x012e
+#define mmHDP_XDP_HDP_MC_CFG_BASE_IDX 0
+#define mmHDP_XDP_HST_CFG 0x012f
+#define mmHDP_XDP_HST_CFG_BASE_IDX 0
+#define mmHDP_XDP_HDP_IPH_CFG 0x0131
+#define mmHDP_XDP_HDP_IPH_CFG_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR0 0x0134
+#define mmHDP_XDP_P2P_BAR0_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR1 0x0135
+#define mmHDP_XDP_P2P_BAR1_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR2 0x0136
+#define mmHDP_XDP_P2P_BAR2_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR3 0x0137
+#define mmHDP_XDP_P2P_BAR3_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR4 0x0138
+#define mmHDP_XDP_P2P_BAR4_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR5 0x0139
+#define mmHDP_XDP_P2P_BAR5_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR6 0x013a
+#define mmHDP_XDP_P2P_BAR6_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR7 0x013b
+#define mmHDP_XDP_P2P_BAR7_BASE_IDX 0
+#define mmHDP_XDP_FLUSH_ARMED_STS 0x013c
+#define mmHDP_XDP_FLUSH_ARMED_STS_BASE_IDX 0
+#define mmHDP_XDP_FLUSH_CNTR0_STS 0x013d
+#define mmHDP_XDP_FLUSH_CNTR0_STS_BASE_IDX 0
+#define mmHDP_XDP_BUSY_STS 0x013e
+#define mmHDP_XDP_BUSY_STS_BASE_IDX 0
+#define mmHDP_XDP_STICKY 0x013f
+#define mmHDP_XDP_STICKY_BASE_IDX 0
+#define mmHDP_XDP_CHKN 0x0140
+#define mmHDP_XDP_CHKN_BASE_IDX 0
+#define mmHDP_XDP_BARS_ADDR_39_36 0x0144
+#define mmHDP_XDP_BARS_ADDR_39_36_BASE_IDX 0
+#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE 0x0145
+#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE_BASE_IDX 0
+#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG 0x0148
+#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
+#define mmHDP_XDP_MMHUB_ERROR 0x0149
+#define mmHDP_XDP_MMHUB_ERROR_BASE_IDX 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h
new file mode 100644
index 000000000000..586187576d70
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h
@@ -0,0 +1,601 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _hdp_4_0_SH_MASK_HEADER
+#define _hdp_4_0_SH_MASK_HEADER
+
+
+// addressBlock: hdp_hdpdec
+//HDP_MMHUB_TLVL
+#define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT 0x0
+#define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT 0x4
+#define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT 0x8
+#define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT 0xc
+#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10
+#define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK 0x00000007L
+#define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK 0x00000070L
+#define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK 0x00000700L
+#define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK 0x00007000L
+#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK 0x00070000L
+//HDP_MMHUB_UNITID
+#define HDP_MMHUB_UNITID__HDP_UNITID__SHIFT 0x0
+#define HDP_MMHUB_UNITID__XDP_UNITID__SHIFT 0x8
+#define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT 0x10
+#define HDP_MMHUB_UNITID__HDP_UNITID_MASK 0x0000003FL
+#define HDP_MMHUB_UNITID__XDP_UNITID_MASK 0x00003F00L
+#define HDP_MMHUB_UNITID__XDP_MBX_UNITID_MASK 0x003F0000L
+//HDP_NONSURFACE_BASE
+#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT 0x0
+#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK 0xFFFFFFFFL
+//HDP_NONSURFACE_INFO
+#define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT 0x4
+#define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT 0x8
+#define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK 0x00000030L
+#define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK 0x00000F00L
+//HDP_NONSURFACE_BASE_HI
+#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT 0x0
+#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK 0x000000FFL
+//HDP_NONSURF_FLAGS
+#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0
+#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1
+#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L
+#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L
+//HDP_NONSURF_FLAGS_CLR
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L
+//HDP_HOST_PATH_CNTL
+#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9
+#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x12
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT 0x16
+#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d
+#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e
+#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f
+#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L
+#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00040000L
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK 0x00400000L
+#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L
+#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000L
+#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000L
+//HDP_SW_SEMAPHORE
+#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0
+#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xFFFFFFFFL
+//HDP_DEBUG0
+#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0
+#define HDP_DEBUG0__HDP_DEBUG_MASK 0xFFFFFFFFL
+//HDP_LAST_SURFACE_HIT
+#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0
+#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x00000003L
+//HDP_READ_CACHE_INVALIDATE
+#define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE__SHIFT 0x0
+#define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE_MASK 0x00000001L
+//HDP_OUTSTANDING_REQ
+#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0
+#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8
+#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000FFL
+#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000FF00L
+//HDP_MISC_CNTL
+#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0
+#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT 0x2
+#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5
+#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6
+#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb
+#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15
+#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT 0x17
+#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18
+#define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID__SHIFT 0x19
+#define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1a
+#define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1b
+#define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE__SHIFT 0x1c
+#define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE__SHIFT 0x1d
+#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT 0x1e
+#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x00000001L
+#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK 0x0000000CL
+#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L
+#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L
+#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L
+#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L
+#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x00800000L
+#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L
+#define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID_MASK 0x02000000L
+#define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x04000000L
+#define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x08000000L
+#define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE_MASK 0x10000000L
+#define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE_MASK 0x20000000L
+#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK 0x40000000L
+//HDP_MEM_POWER_LS
+#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0
+#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7
+#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x00000001L
+#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x00001F80L
+//HDP_MMHUB_CNTL
+#define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT 0x0
+#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT 0x1
+#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT 0x2
+#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK 0x00000001L
+#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK 0x00000002L
+#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK 0x00000004L
+//HDP_EDC_CNT
+#define HDP_EDC_CNT__MEM0_SED_COUNT__SHIFT 0x0
+#define HDP_EDC_CNT__MEM1_SED_COUNT__SHIFT 0x2
+#define HDP_EDC_CNT__MEM0_SED_COUNT_MASK 0x00000003L
+#define HDP_EDC_CNT__MEM1_SED_COUNT_MASK 0x0000000CL
+//HDP_VERSION
+#define HDP_VERSION__MINVER__SHIFT 0x0
+#define HDP_VERSION__MAJVER__SHIFT 0x8
+#define HDP_VERSION__REV__SHIFT 0x10
+#define HDP_VERSION__MINVER_MASK 0x000000FFL
+#define HDP_VERSION__MAJVER_MASK 0x0000FF00L
+#define HDP_VERSION__REV_MASK 0x00FF0000L
+//HDP_CLK_CNTL
+#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x0
+#define HDP_CLK_CNTL__REG_WAKE_DYN_CLK__SHIFT 0x4
+#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT 0x1c
+#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1d
+#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1e
+#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f
+#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0000000FL
+#define HDP_CLK_CNTL__REG_WAKE_DYN_CLK_MASK 0x00000010L
+#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK 0x10000000L
+#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK 0x20000000L
+#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK 0x40000000L
+#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L
+//HDP_MEMIO_CNTL
+#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0
+#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1
+#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2
+#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6
+#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7
+#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8
+#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe
+#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf
+#define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10
+#define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11
+#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L
+#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L
+#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003CL
+#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L
+#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L
+#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003F00L
+#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L
+#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L
+#define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x00010000L
+#define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x003E0000L
+//HDP_MEMIO_ADDR
+#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0
+#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xFFFFFFFFL
+//HDP_MEMIO_STATUS
+#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0
+#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1
+#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2
+#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3
+#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L
+#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L
+#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L
+#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L
+//HDP_MEMIO_WR_DATA
+#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0
+#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xFFFFFFFFL
+//HDP_MEMIO_RD_DATA
+#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0
+#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xFFFFFFFFL
+//HDP_XDP_DIRECT2HDP_FIRST
+#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0
+#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_FLUSH
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000FL
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000F0L
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000F800L
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L
+//HDP_XDP_D2H_BAR_UPDATE
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000F0000L
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L
+//HDP_XDP_D2H_RSVD_3
+#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_4
+#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_5
+#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_6
+#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_7
+#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_8
+#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_9
+#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_10
+#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_11
+#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_12
+#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_13
+#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_14
+#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_15
+#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_16
+#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_17
+#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_18
+#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_19
+#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_20
+#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_21
+#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_22
+#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_23
+#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_24
+#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_25
+#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_26
+#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_27
+#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_28
+#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_29
+#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_30
+#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_31
+#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_32
+#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_33
+#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_34
+#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_DIRECT2HDP_LAST
+#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0
+#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_P2P_BAR_CFG
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000FL
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L
+//HDP_XDP_P2P_MBX_OFFSET
+#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x0001FFFFL
+//HDP_XDP_P2P_MBX_ADDR0
+#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT 0x3
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT 0x18
+#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK 0x000FFFF8L
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK 0xFF000000L
+//HDP_XDP_P2P_MBX_ADDR1
+#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT 0x3
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT 0x18
+#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK 0x000FFFF8L
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK 0xFF000000L
+//HDP_XDP_P2P_MBX_ADDR2
+#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT 0x3
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT 0x18
+#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK 0x000FFFF8L
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK 0xFF000000L
+//HDP_XDP_P2P_MBX_ADDR3
+#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT 0x3
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT 0x18
+#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK 0x000FFFF8L
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK 0xFF000000L
+//HDP_XDP_P2P_MBX_ADDR4
+#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT 0x3
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT 0x18
+#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK 0x000FFFF8L
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK 0xFF000000L
+//HDP_XDP_P2P_MBX_ADDR5
+#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT 0x3
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT 0x18
+#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK 0x000FFFF8L
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK 0xFF000000L
+//HDP_XDP_P2P_MBX_ADDR6
+#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT 0x3
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT 0x18
+#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK 0x000FFFF8L
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK 0xFF000000L
+//HDP_XDP_HDP_MBX_MC_CFG
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT 0x0
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x4
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x8
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT 0xc
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT 0xd
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT 0xe
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK 0x0000000FL
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000030L
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x00000F00L
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK 0x00001000L
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK 0x00002000L
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK 0x00004000L
+//HDP_XDP_HDP_MC_CFG
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT 0x3
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT 0x4
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT 0x8
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT 0xc
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT 0xd
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK 0x00000008L
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK 0x00000030L
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK 0x00000F00L
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK 0x00001000L
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK 0x00002000L
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000FC000L
+//HDP_XDP_HST_CFG
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1
+#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT 0x3
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT 0x4
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x5
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L
+#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK 0x00000008L
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK 0x00000010L
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00000020L
+//HDP_XDP_HDP_IPH_CFG
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x0000003FL
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0x00000FC0L
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L
+//HDP_XDP_P2P_BAR0
+#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L
+//HDP_XDP_P2P_BAR1
+#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L
+//HDP_XDP_P2P_BAR2
+#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L
+//HDP_XDP_P2P_BAR3
+#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L
+//HDP_XDP_P2P_BAR4
+#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L
+//HDP_XDP_P2P_BAR5
+#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L
+//HDP_XDP_P2P_BAR6
+#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L
+//HDP_XDP_P2P_BAR7
+#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L
+//HDP_XDP_FLUSH_ARMED_STS
+#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0
+#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xFFFFFFFFL
+//HDP_XDP_FLUSH_CNTR0_STS
+#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0
+#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03FFFFFFL
+//HDP_XDP_BUSY_STS
+#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0
+#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x0003FFFFL
+//HDP_XDP_STICKY
+#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0
+#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10
+#define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000FFFFL
+#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xFFFF0000L
+//HDP_XDP_CHKN
+#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0
+#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8
+#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10
+#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18
+#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000FFL
+#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000FF00L
+#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00FF0000L
+#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xFF000000L
+//HDP_XDP_BARS_ADDR_39_36
+#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0
+#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4
+#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8
+#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc
+#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10
+#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18
+#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c
+#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000FL
+#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000F0L
+#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000F00L
+#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000F000L
+#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000F0000L
+#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0F000000L
+#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xF0000000L
+//HDP_XDP_MC_VM_FB_LOCATION_BASE
+#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0
+#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x03FFFFFFL
+//HDP_XDP_GPU_IOV_VIOLATION_LOG
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L
+//HDP_XDP_MMHUB_ERROR
+#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT 0x1
+#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT 0x2
+#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT 0x3
+#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT 0x5
+#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT 0x6
+#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT 0x7
+#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT 0x9
+#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT 0xa
+#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT 0xb
+#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT 0xd
+#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT 0xe
+#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT 0xf
+#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT 0x11
+#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT 0x12
+#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT 0x13
+#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT 0x15
+#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT 0x16
+#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT 0x17
+#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK 0x00000002L
+#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK 0x00000004L
+#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK 0x00000008L
+#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK 0x00000020L
+#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK 0x00000040L
+#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK 0x00000080L
+#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK 0x00000200L
+#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK 0x00000400L
+#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK 0x00000800L
+#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK 0x00002000L
+#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK 0x00004000L
+#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK 0x00008000L
+#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK 0x00020000L
+#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK 0x00040000L
+#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK 0x00080000L
+#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK 0x00200000L
+#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK 0x00400000L
+#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK 0x00800000L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_default.h
new file mode 100644
index 000000000000..02989fe9f7bd
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_default.h
@@ -0,0 +1,1011 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _mmhub_1_0_DEFAULT_HEADER
+#define _mmhub_1_0_DEFAULT_HEADER
+
+
+// addressBlock: mmhub_dagbdec
+#define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI10_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI11_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI12_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI13_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI14_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI15_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RD_CNTL_DEFAULT 0x03527df8
+#define mmDAGB0_RD_GMI_CNTL_DEFAULT 0x0000304f
+#define mmDAGB0_RD_ADDR_DAGB_DEFAULT 0x00000039
+#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888
+#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111
+#define mmDAGB0_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111
+#define mmDAGB0_RD_VC0_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_RD_VC1_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_RD_VC2_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_RD_VC3_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_RD_VC4_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_RD_VC5_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_RD_VC6_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_RD_VC7_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_RD_CNTL_MISC_DEFAULT 0x01a10408
+#define mmDAGB0_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7
+#define mmDAGB0_RDCLI_ASK_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_RDCLI_GO_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_RDCLI_TLB_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_RDCLI_OARB_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_RDCLI_OSD_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_WRCLI0_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI1_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI2_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI3_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI4_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI5_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI6_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI7_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI8_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI9_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI10_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI11_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI12_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI13_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI14_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI15_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WR_CNTL_DEFAULT 0x03527df8
+#define mmDAGB0_WR_GMI_CNTL_DEFAULT 0x0000304f
+#define mmDAGB0_WR_ADDR_DAGB_DEFAULT 0x00000039
+#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888
+#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111
+#define mmDAGB0_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111
+#define mmDAGB0_WR_DATA_DAGB_DEFAULT 0x00000001
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000
+#define mmDAGB0_WR_VC0_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_WR_VC1_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_WR_VC2_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_WR_VC3_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_WR_VC4_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_WR_VC5_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_WR_VC6_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_WR_VC7_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_WR_CNTL_MISC_DEFAULT 0x01a10408
+#define mmDAGB0_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7
+#define mmDAGB0_WR_DATA_CREDIT_DEFAULT 0x5c626870
+#define mmDAGB0_WR_MISC_CREDIT_DEFAULT 0x0078dc88
+#define mmDAGB0_WRCLI_ASK_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_WRCLI_GO_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_WRCLI_TLB_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_WRCLI_OARB_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_WRCLI_OSD_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_DAGB_DLY_DEFAULT 0x00000000
+#define mmDAGB0_CNTL_MISC_DEFAULT 0xcf7c1ffa
+#define mmDAGB0_CNTL_MISC2_DEFAULT 0x00000000
+#define mmDAGB0_FIFO_EMPTY_DEFAULT 0x00ffffff
+#define mmDAGB0_FIFO_FULL_DEFAULT 0x00000000
+#define mmDAGB0_WR_CREDITS_FULL_DEFAULT 0x0007ffff
+#define mmDAGB0_RD_CREDITS_FULL_DEFAULT 0x0003ffff
+#define mmDAGB0_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmDAGB0_PERFCOUNTER_HI_DEFAULT 0x00000000
+#define mmDAGB0_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmDAGB0_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmDAGB0_PERFCOUNTER2_CFG_DEFAULT 0x00000000
+#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+#define mmDAGB0_RESERVE0_DEFAULT 0x00000000
+#define mmDAGB0_RESERVE1_DEFAULT 0x00000000
+#define mmDAGB0_RESERVE2_DEFAULT 0x00000000
+#define mmDAGB0_RESERVE3_DEFAULT 0x00000000
+#define mmDAGB0_RESERVE4_DEFAULT 0x00000000
+#define mmDAGB0_RESERVE5_DEFAULT 0x00000000
+#define mmDAGB0_RESERVE6_DEFAULT 0x00000000
+#define mmDAGB0_RESERVE7_DEFAULT 0x00000000
+#define mmDAGB0_RESERVE8_DEFAULT 0x00000000
+#define mmDAGB0_RESERVE9_DEFAULT 0x00000000
+#define mmDAGB0_RESERVE10_DEFAULT 0x00000000
+#define mmDAGB0_RESERVE11_DEFAULT 0x00000000
+#define mmDAGB0_RESERVE12_DEFAULT 0x00000000
+#define mmDAGB0_RESERVE13_DEFAULT 0x00000000
+#define mmDAGB0_RESERVE14_DEFAULT 0x00000000
+#define mmDAGB0_RESERVE15_DEFAULT 0x00000000
+#define mmDAGB0_RESERVE16_DEFAULT 0x00000000
+#define mmDAGB0_RESERVE17_DEFAULT 0x00000000
+#define mmDAGB1_RDCLI0_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_RDCLI1_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_RDCLI2_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_RDCLI3_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_RDCLI4_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_RDCLI5_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_RDCLI6_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_RDCLI7_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_RDCLI8_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_RDCLI9_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_RDCLI10_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_RDCLI11_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_RDCLI12_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_RDCLI13_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_RDCLI14_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_RDCLI15_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_RD_CNTL_DEFAULT 0x03527df8
+#define mmDAGB1_RD_GMI_CNTL_DEFAULT 0x0000304f
+#define mmDAGB1_RD_ADDR_DAGB_DEFAULT 0x00000039
+#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888
+#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111
+#define mmDAGB1_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888
+#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111
+#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888
+#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111
+#define mmDAGB1_RD_VC0_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB1_RD_VC1_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB1_RD_VC2_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB1_RD_VC3_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB1_RD_VC4_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB1_RD_VC5_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB1_RD_VC6_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB1_RD_VC7_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB1_RD_CNTL_MISC_DEFAULT 0x01a10408
+#define mmDAGB1_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7
+#define mmDAGB1_RDCLI_ASK_PENDING_DEFAULT 0x00000000
+#define mmDAGB1_RDCLI_GO_PENDING_DEFAULT 0x00000000
+#define mmDAGB1_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000
+#define mmDAGB1_RDCLI_TLB_PENDING_DEFAULT 0x00000000
+#define mmDAGB1_RDCLI_OARB_PENDING_DEFAULT 0x00000000
+#define mmDAGB1_RDCLI_OSD_PENDING_DEFAULT 0x00000000
+#define mmDAGB1_WRCLI0_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_WRCLI1_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_WRCLI2_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_WRCLI3_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_WRCLI4_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_WRCLI5_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_WRCLI6_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_WRCLI7_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_WRCLI8_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_WRCLI9_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_WRCLI10_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_WRCLI11_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_WRCLI12_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_WRCLI13_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_WRCLI14_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_WRCLI15_DEFAULT 0xfe5fe0f9
+#define mmDAGB1_WR_CNTL_DEFAULT 0x03527df8
+#define mmDAGB1_WR_GMI_CNTL_DEFAULT 0x0000304f
+#define mmDAGB1_WR_ADDR_DAGB_DEFAULT 0x00000039
+#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888
+#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111
+#define mmDAGB1_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888
+#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111
+#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888
+#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111
+#define mmDAGB1_WR_DATA_DAGB_DEFAULT 0x00000001
+#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111
+#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000
+#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111
+#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000
+#define mmDAGB1_WR_VC0_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB1_WR_VC1_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB1_WR_VC2_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB1_WR_VC3_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB1_WR_VC4_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB1_WR_VC5_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB1_WR_VC6_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB1_WR_VC7_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB1_WR_CNTL_MISC_DEFAULT 0x01a10408
+#define mmDAGB1_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7
+#define mmDAGB1_WR_DATA_CREDIT_DEFAULT 0x5c626870
+#define mmDAGB1_WR_MISC_CREDIT_DEFAULT 0x0078dc88
+#define mmDAGB1_WRCLI_ASK_PENDING_DEFAULT 0x00000000
+#define mmDAGB1_WRCLI_GO_PENDING_DEFAULT 0x00000000
+#define mmDAGB1_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000
+#define mmDAGB1_WRCLI_TLB_PENDING_DEFAULT 0x00000000
+#define mmDAGB1_WRCLI_OARB_PENDING_DEFAULT 0x00000000
+#define mmDAGB1_WRCLI_OSD_PENDING_DEFAULT 0x00000000
+#define mmDAGB1_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000
+#define mmDAGB1_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000
+#define mmDAGB1_DAGB_DLY_DEFAULT 0x00000000
+#define mmDAGB1_CNTL_MISC_DEFAULT 0xcf7c1ffa
+#define mmDAGB1_CNTL_MISC2_DEFAULT 0x00000000
+#define mmDAGB1_FIFO_EMPTY_DEFAULT 0x00ffffff
+#define mmDAGB1_FIFO_FULL_DEFAULT 0x00000000
+#define mmDAGB1_WR_CREDITS_FULL_DEFAULT 0x0007ffff
+#define mmDAGB1_RD_CREDITS_FULL_DEFAULT 0x0003ffff
+#define mmDAGB1_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmDAGB1_PERFCOUNTER_HI_DEFAULT 0x00000000
+#define mmDAGB1_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmDAGB1_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmDAGB1_PERFCOUNTER2_CFG_DEFAULT 0x00000000
+#define mmDAGB1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+#define mmDAGB1_RESERVE0_DEFAULT 0x00000000
+#define mmDAGB1_RESERVE1_DEFAULT 0x00000000
+#define mmDAGB1_RESERVE2_DEFAULT 0x00000000
+#define mmDAGB1_RESERVE3_DEFAULT 0x00000000
+#define mmDAGB1_RESERVE4_DEFAULT 0x00000000
+#define mmDAGB1_RESERVE5_DEFAULT 0x00000000
+#define mmDAGB1_RESERVE6_DEFAULT 0x00000000
+#define mmDAGB1_RESERVE7_DEFAULT 0x00000000
+#define mmDAGB1_RESERVE8_DEFAULT 0x00000000
+#define mmDAGB1_RESERVE9_DEFAULT 0x00000000
+#define mmDAGB1_RESERVE10_DEFAULT 0x00000000
+#define mmDAGB1_RESERVE11_DEFAULT 0x00000000
+#define mmDAGB1_RESERVE12_DEFAULT 0x00000000
+#define mmDAGB1_RESERVE13_DEFAULT 0x00000000
+#define mmDAGB1_RESERVE14_DEFAULT 0x00000000
+#define mmDAGB1_RESERVE15_DEFAULT 0x00000000
+#define mmDAGB1_RESERVE16_DEFAULT 0x00000000
+#define mmDAGB1_RESERVE17_DEFAULT 0x00000000
+
+
+// addressBlock: mmhub_ea_mmeadec
+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555
+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555
+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555
+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555
+#define mmMMEA0_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25
+#define mmMMEA0_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25
+#define mmMMEA0_DRAM_RD_LAZY_DEFAULT 0x00000924
+#define mmMMEA0_DRAM_WR_LAZY_DEFAULT 0x00000924
+#define mmMMEA0_DRAM_RD_CAM_CNTL_DEFAULT 0x06db3333
+#define mmMMEA0_DRAM_WR_CAM_CNTL_DEFAULT 0x06db3333
+#define mmMMEA0_DRAM_PAGE_BURST_DEFAULT 0x20002000
+#define mmMMEA0_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249
+#define mmMMEA0_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249
+#define mmMMEA0_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6
+#define mmMMEA0_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6
+#define mmMMEA0_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924
+#define mmMMEA0_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924
+#define mmMMEA0_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6
+#define mmMMEA0_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff
+#define mmMMEA0_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000
+#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000
+#define mmMMEA0_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000
+#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000
+#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000
+#define mmMMEA0_ADDRNORM_HOLE_CNTL_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef
+#define mmMMEA0_ADDRDEC_MISC_CFG_DEFAULT 0x3ffff000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000
+#define mmMMEA0_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4
+#define mmMMEA0_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4
+#define mmMMEA0_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4
+#define mmMMEA0_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4
+#define mmMMEA0_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777
+#define mmMMEA0_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777
+#define mmMMEA0_IO_GROUP_BURST_DEFAULT 0x1f031f03
+#define mmMMEA0_IO_RD_PRI_AGE_DEFAULT 0x00db6249
+#define mmMMEA0_IO_WR_PRI_AGE_DEFAULT 0x00db6249
+#define mmMMEA0_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6
+#define mmMMEA0_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6
+#define mmMMEA0_IO_RD_PRI_FIXED_DEFAULT 0x00000924
+#define mmMMEA0_IO_WR_PRI_FIXED_DEFAULT 0x00000924
+#define mmMMEA0_IO_RD_PRI_URGENCY_DEFAULT 0x00000492
+#define mmMMEA0_IO_WR_PRI_URGENCY_DEFAULT 0x00000492
+#define mmMMEA0_IO_RD_PRI_URGENCY_MASK_DEFAULT 0xffffffff
+#define mmMMEA0_IO_WR_PRI_URGENCY_MASK_DEFAULT 0xffffffff
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff
+#define mmMMEA0_SDP_ARB_DRAM_DEFAULT 0x00102040
+#define mmMMEA0_SDP_ARB_FINAL_DEFAULT 0x00007fff
+#define mmMMEA0_SDP_DRAM_PRIORITY_DEFAULT 0x00000000
+#define mmMMEA0_SDP_IO_PRIORITY_DEFAULT 0x00000000
+#define mmMMEA0_SDP_CREDITS_DEFAULT 0x000100bf
+#define mmMMEA0_SDP_TAG_RESERVE0_DEFAULT 0x00000000
+#define mmMMEA0_SDP_TAG_RESERVE1_DEFAULT 0x00000000
+#define mmMMEA0_SDP_VCC_RESERVE0_DEFAULT 0x00000000
+#define mmMMEA0_SDP_VCC_RESERVE1_DEFAULT 0x00000000
+#define mmMMEA0_SDP_VCD_RESERVE0_DEFAULT 0x00000000
+#define mmMMEA0_SDP_VCD_RESERVE1_DEFAULT 0x00000000
+#define mmMMEA0_SDP_REQ_CNTL_DEFAULT 0x0000000f
+#define mmMMEA0_MISC_DEFAULT 0x00180130
+#define mmMMEA0_LATENCY_SAMPLING_DEFAULT 0x00000000
+#define mmMMEA0_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmMMEA0_PERFCOUNTER_HI_DEFAULT 0x00000000
+#define mmMMEA0_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmMMEA0_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+#define mmMMEA0_EDC_CNT_DEFAULT 0x00000000
+#define mmMMEA0_EDC_CNT2_DEFAULT 0x00000000
+#define mmMMEA0_DSM_CNTL_DEFAULT 0x00000000
+#define mmMMEA0_DSM_CNTLA_DEFAULT 0x00000000
+#define mmMMEA0_DSM_CNTLB_DEFAULT 0x00000000
+#define mmMMEA0_DSM_CNTL2_DEFAULT 0x00000000
+#define mmMMEA0_DSM_CNTL2A_DEFAULT 0x00000000
+#define mmMMEA0_DSM_CNTL2B_DEFAULT 0x00000000
+#define mmMMEA0_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmMMEA0_EDC_MODE_DEFAULT 0x00000000
+#define mmMMEA0_ERR_STATUS_DEFAULT 0x00000000
+#define mmMMEA0_MISC2_DEFAULT 0x00000000
+#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555
+#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555
+#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555
+#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555
+#define mmMMEA1_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25
+#define mmMMEA1_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25
+#define mmMMEA1_DRAM_RD_LAZY_DEFAULT 0x00000924
+#define mmMMEA1_DRAM_WR_LAZY_DEFAULT 0x00000924
+#define mmMMEA1_DRAM_RD_CAM_CNTL_DEFAULT 0x06db3333
+#define mmMMEA1_DRAM_WR_CAM_CNTL_DEFAULT 0x06db3333
+#define mmMMEA1_DRAM_PAGE_BURST_DEFAULT 0x20002000
+#define mmMMEA1_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249
+#define mmMMEA1_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249
+#define mmMMEA1_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6
+#define mmMMEA1_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6
+#define mmMMEA1_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924
+#define mmMMEA1_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924
+#define mmMMEA1_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6
+#define mmMMEA1_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6
+#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
+#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
+#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff
+#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
+#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
+#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff
+#define mmMMEA1_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000
+#define mmMMEA1_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000
+#define mmMMEA1_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000
+#define mmMMEA1_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000
+#define mmMMEA1_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000
+#define mmMMEA1_ADDRNORM_HOLE_CNTL_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef
+#define mmMMEA1_ADDRDEC_MISC_CFG_DEFAULT 0x3ffff000
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe
+#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe
+#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe
+#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe
+#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408
+#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408
+#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543
+#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543
+#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321
+#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321
+#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543
+#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543
+#define mmMMEA1_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe
+#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe
+#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe
+#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe
+#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408
+#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408
+#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543
+#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543
+#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321
+#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321
+#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543
+#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543
+#define mmMMEA1_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000
+#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000
+#define mmMMEA1_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4
+#define mmMMEA1_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4
+#define mmMMEA1_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4
+#define mmMMEA1_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4
+#define mmMMEA1_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777
+#define mmMMEA1_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777
+#define mmMMEA1_IO_GROUP_BURST_DEFAULT 0x1f031f03
+#define mmMMEA1_IO_RD_PRI_AGE_DEFAULT 0x00db6249
+#define mmMMEA1_IO_WR_PRI_AGE_DEFAULT 0x00db6249
+#define mmMMEA1_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6
+#define mmMMEA1_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6
+#define mmMMEA1_IO_RD_PRI_FIXED_DEFAULT 0x00000924
+#define mmMMEA1_IO_WR_PRI_FIXED_DEFAULT 0x00000924
+#define mmMMEA1_IO_RD_PRI_URGENCY_DEFAULT 0x00000492
+#define mmMMEA1_IO_WR_PRI_URGENCY_DEFAULT 0x00000492
+#define mmMMEA1_IO_RD_PRI_URGENCY_MASK_DEFAULT 0xffffffff
+#define mmMMEA1_IO_WR_PRI_URGENCY_MASK_DEFAULT 0xffffffff
+#define mmMMEA1_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
+#define mmMMEA1_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
+#define mmMMEA1_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff
+#define mmMMEA1_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
+#define mmMMEA1_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
+#define mmMMEA1_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff
+#define mmMMEA1_SDP_ARB_DRAM_DEFAULT 0x00102040
+#define mmMMEA1_SDP_ARB_FINAL_DEFAULT 0x00007fff
+#define mmMMEA1_SDP_DRAM_PRIORITY_DEFAULT 0x00000000
+#define mmMMEA1_SDP_IO_PRIORITY_DEFAULT 0x00000000
+#define mmMMEA1_SDP_CREDITS_DEFAULT 0x000100bf
+#define mmMMEA1_SDP_TAG_RESERVE0_DEFAULT 0x00000000
+#define mmMMEA1_SDP_TAG_RESERVE1_DEFAULT 0x00000000
+#define mmMMEA1_SDP_VCC_RESERVE0_DEFAULT 0x00000000
+#define mmMMEA1_SDP_VCC_RESERVE1_DEFAULT 0x00000000
+#define mmMMEA1_SDP_VCD_RESERVE0_DEFAULT 0x00000000
+#define mmMMEA1_SDP_VCD_RESERVE1_DEFAULT 0x00000000
+#define mmMMEA1_SDP_REQ_CNTL_DEFAULT 0x0000000f
+#define mmMMEA1_MISC_DEFAULT 0x00180130
+#define mmMMEA1_LATENCY_SAMPLING_DEFAULT 0x00000000
+#define mmMMEA1_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmMMEA1_PERFCOUNTER_HI_DEFAULT 0x00000000
+#define mmMMEA1_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmMMEA1_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmMMEA1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+#define mmMMEA1_EDC_CNT_DEFAULT 0x00000000
+#define mmMMEA1_EDC_CNT2_DEFAULT 0x00000000
+#define mmMMEA1_DSM_CNTL_DEFAULT 0x00000000
+#define mmMMEA1_DSM_CNTLA_DEFAULT 0x00000000
+#define mmMMEA1_DSM_CNTLB_DEFAULT 0x00000000
+#define mmMMEA1_DSM_CNTL2_DEFAULT 0x00000000
+#define mmMMEA1_DSM_CNTL2A_DEFAULT 0x00000000
+#define mmMMEA1_DSM_CNTL2B_DEFAULT 0x00000000
+#define mmMMEA1_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmMMEA1_EDC_MODE_DEFAULT 0x00000000
+#define mmMMEA1_ERR_STATUS_DEFAULT 0x00000000
+#define mmMMEA1_MISC2_DEFAULT 0x00000000
+
+
+// addressBlock: mmhub_pctldec
+#define mmPCTL_MISC_DEFAULT 0x00000889
+#define mmPCTL_MMHUB_DEEPSLEEP_DEFAULT 0x00000000
+#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_DEFAULT 0x00000000
+#define mmPCTL_PG_IGNORE_DEEPSLEEP_DEFAULT 0x00000000
+#define mmPCTL_PG_DAGB_DEFAULT 0x00000000
+#define mmPCTL0_RENG_RAM_INDEX_DEFAULT 0x00000000
+#define mmPCTL0_RENG_RAM_DATA_DEFAULT 0x00000000
+#define mmPCTL0_RENG_EXECUTE_DEFAULT 0x00000000
+#define mmPCTL0_MISC_DEFAULT 0x00001000
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000
+#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff
+#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff
+#define mmPCTL1_RENG_RAM_INDEX_DEFAULT 0x00000000
+#define mmPCTL1_RENG_RAM_DATA_DEFAULT 0x00000000
+#define mmPCTL1_RENG_EXECUTE_DEFAULT 0x00000000
+#define mmPCTL1_MISC_DEFAULT 0x00000800
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x061f05a0
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08590800
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000
+#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff
+#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff
+#define mmPCTL2_RENG_RAM_INDEX_DEFAULT 0x00000000
+#define mmPCTL2_RENG_RAM_DATA_DEFAULT 0x00000000
+#define mmPCTL2_RENG_EXECUTE_DEFAULT 0x00000000
+#define mmPCTL2_MISC_DEFAULT 0x00000800
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x069f0620
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08b3085a
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000
+#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff
+#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff
+
+
+// addressBlock: mmhub_l1tlb_vml1dec
+#define mmMC_VM_MX_L1_TLB0_STATUS_DEFAULT 0x00000000
+#define mmMC_VM_MX_L1_TLB1_STATUS_DEFAULT 0x00000000
+#define mmMC_VM_MX_L1_TLB2_STATUS_DEFAULT 0x00000000
+#define mmMC_VM_MX_L1_TLB3_STATUS_DEFAULT 0x00000000
+#define mmMC_VM_MX_L1_TLB4_STATUS_DEFAULT 0x00000000
+#define mmMC_VM_MX_L1_TLB5_STATUS_DEFAULT 0x00000000
+#define mmMC_VM_MX_L1_TLB6_STATUS_DEFAULT 0x00000000
+#define mmMC_VM_MX_L1_TLB7_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: mmhub_l1tlb_vml1pldec
+#define mmMC_VM_MX_L1_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmMC_VM_MX_L1_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmMC_VM_MX_L1_PERFCOUNTER2_CFG_DEFAULT 0x00000000
+#define mmMC_VM_MX_L1_PERFCOUNTER3_CFG_DEFAULT 0x00000000
+#define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+
+
+// addressBlock: mmhub_l1tlb_vml1prdec
+#define mmMC_VM_MX_L1_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmMC_VM_MX_L1_PERFCOUNTER_HI_DEFAULT 0x00000000
+
+
+// addressBlock: mmhub_utcl2_atcl2dec
+#define mmATC_L2_CNTL_DEFAULT 0x000001c9
+#define mmATC_L2_CNTL2_DEFAULT 0x00000100
+#define mmATC_L2_CACHE_DATA0_DEFAULT 0x00000000
+#define mmATC_L2_CACHE_DATA1_DEFAULT 0x00000000
+#define mmATC_L2_CACHE_DATA2_DEFAULT 0x00000000
+#define mmATC_L2_CNTL3_DEFAULT 0x000001f8
+#define mmATC_L2_STATUS_DEFAULT 0x00000000
+#define mmATC_L2_STATUS2_DEFAULT 0x00000000
+#define mmATC_L2_MISC_CG_DEFAULT 0x00000200
+#define mmATC_L2_MEM_POWER_LS_DEFAULT 0x00000208
+#define mmATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080
+
+
+// addressBlock: mmhub_utcl2_vml2pfdec
+#define mmVM_L2_CNTL_DEFAULT 0x00080602
+#define mmVM_L2_CNTL2_DEFAULT 0x00000000
+#define mmVM_L2_CNTL3_DEFAULT 0x80100007
+#define mmVM_L2_STATUS_DEFAULT 0x00000000
+#define mmVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090
+#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc
+#define mmVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000
+#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff
+#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff
+#define mmVM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000
+#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000
+#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000
+#define mmVM_L2_CNTL4_DEFAULT 0x000000c1
+#define mmVM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000
+#define mmVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000
+#define mmVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000
+#define mmVM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000
+#define mmVM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080
+
+
+// addressBlock: mmhub_utcl2_vml2vcdec
+#define mmVM_CONTEXT0_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT1_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT2_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT3_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT4_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT5_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT6_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT7_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT8_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT9_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT10_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT11_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT12_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT13_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT14_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXT15_CNTL_DEFAULT 0x007ffe80
+#define mmVM_CONTEXTS_DISABLE_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG0_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG1_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG2_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG3_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG4_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG5_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG6_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG7_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG8_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG9_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG10_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG11_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG12_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG13_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG14_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG15_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG16_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG17_REQ_DEFAULT 0x017c0000
+#define mmVM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+
+
+// addressBlock: mmhub_utcl2_vml2pldec
+#define mmMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000
+#define mmMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000
+#define mmMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000
+#define mmMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000
+#define mmMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000
+#define mmMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000
+#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+
+
+// addressBlock: mmhub_utcl2_vml2prdec
+#define mmMC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmMC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000
+
+
+// addressBlock: mmhub_utcl2_vmsharedhvdec
+#define mmMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000
+#define mmMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000
+#define mmVM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100
+#define mmMC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000
+#define mmMC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000
+#define mmMC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000
+#define mmMC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000
+#define mmMC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000
+#define mmMC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000
+#define mmMC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000
+#define mmMC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000
+#define mmMC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000
+#define mmMC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000
+#define mmMC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000
+#define mmMC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000
+#define mmMC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000
+#define mmMC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000
+#define mmMC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000
+#define mmMC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000
+#define mmMC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000
+#define mmMC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000
+#define mmMC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000
+#define mmMC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000
+#define mmMC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000
+#define mmMC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000
+#define mmMC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000
+#define mmMC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000
+#define mmVM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000
+#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000
+#define mmVM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000
+#define mmUTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080
+
+
+// addressBlock: mmhub_utcl2_vmsharedpfdec
+#define mmMC_VM_NB_MMIOBASE_DEFAULT 0x00000000
+#define mmMC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000
+#define mmMC_VM_NB_PCI_CTRL_DEFAULT 0x00000000
+#define mmMC_VM_NB_PCI_ARB_DEFAULT 0x00000008
+#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000
+#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000
+#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000
+#define mmMC_VM_FB_OFFSET_DEFAULT 0x00000000
+#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000
+#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000
+#define mmMC_VM_STEERING_DEFAULT 0x00000001
+#define mmMC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000
+#define mmMC_MEM_POWER_LS_DEFAULT 0x00000208
+#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000
+#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000
+#define mmMC_VM_APT_CNTL_DEFAULT 0x00000000
+#define mmMC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000
+#define mmMC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff
+#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: mmhub_utcl2_vmsharedvcdec
+#define mmMC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000
+#define mmMC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000
+#define mmMC_VM_AGP_TOP_DEFAULT 0x00000000
+#define mmMC_VM_AGP_BOT_DEFAULT 0x00000000
+#define mmMC_VM_AGP_BASE_DEFAULT 0x00000000
+#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000
+#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000
+#define mmMC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00002501
+
+
+// addressBlock: mmhub_utcl2_atcl2pfcntrdec
+#define mmATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000
+
+
+// addressBlock: mmhub_utcl2_atcl2pfcntldec
+#define mmATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_offset.h
new file mode 100644
index 000000000000..352ffae7a7ca
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_offset.h
@@ -0,0 +1,1967 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _mmhub_1_0_OFFSET_HEADER
+#define _mmhub_1_0_OFFSET_HEADER
+
+
+
+// addressBlock: mmhub_dagbdec
+// base address: 0x68000
+#define mmDAGB0_RDCLI0 0x0000
+#define mmDAGB0_RDCLI0_BASE_IDX 0
+#define mmDAGB0_RDCLI1 0x0001
+#define mmDAGB0_RDCLI1_BASE_IDX 0
+#define mmDAGB0_RDCLI2 0x0002
+#define mmDAGB0_RDCLI2_BASE_IDX 0
+#define mmDAGB0_RDCLI3 0x0003
+#define mmDAGB0_RDCLI3_BASE_IDX 0
+#define mmDAGB0_RDCLI4 0x0004
+#define mmDAGB0_RDCLI4_BASE_IDX 0
+#define mmDAGB0_RDCLI5 0x0005
+#define mmDAGB0_RDCLI5_BASE_IDX 0
+#define mmDAGB0_RDCLI6 0x0006
+#define mmDAGB0_RDCLI6_BASE_IDX 0
+#define mmDAGB0_RDCLI7 0x0007
+#define mmDAGB0_RDCLI7_BASE_IDX 0
+#define mmDAGB0_RDCLI8 0x0008
+#define mmDAGB0_RDCLI8_BASE_IDX 0
+#define mmDAGB0_RDCLI9 0x0009
+#define mmDAGB0_RDCLI9_BASE_IDX 0
+#define mmDAGB0_RDCLI10 0x000a
+#define mmDAGB0_RDCLI10_BASE_IDX 0
+#define mmDAGB0_RDCLI11 0x000b
+#define mmDAGB0_RDCLI11_BASE_IDX 0
+#define mmDAGB0_RDCLI12 0x000c
+#define mmDAGB0_RDCLI12_BASE_IDX 0
+#define mmDAGB0_RDCLI13 0x000d
+#define mmDAGB0_RDCLI13_BASE_IDX 0
+#define mmDAGB0_RDCLI14 0x000e
+#define mmDAGB0_RDCLI14_BASE_IDX 0
+#define mmDAGB0_RDCLI15 0x000f
+#define mmDAGB0_RDCLI15_BASE_IDX 0
+#define mmDAGB0_RD_CNTL 0x0010
+#define mmDAGB0_RD_CNTL_BASE_IDX 0
+#define mmDAGB0_RD_GMI_CNTL 0x0011
+#define mmDAGB0_RD_GMI_CNTL_BASE_IDX 0
+#define mmDAGB0_RD_ADDR_DAGB 0x0012
+#define mmDAGB0_RD_ADDR_DAGB_BASE_IDX 0
+#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0013
+#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0014
+#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define mmDAGB0_RD_CGTT_CLK_CTRL 0x0015
+#define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0016
+#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x0017
+#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0018
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0019
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001a
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001b
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define mmDAGB0_RD_VC0_CNTL 0x001c
+#define mmDAGB0_RD_VC0_CNTL_BASE_IDX 0
+#define mmDAGB0_RD_VC1_CNTL 0x001d
+#define mmDAGB0_RD_VC1_CNTL_BASE_IDX 0
+#define mmDAGB0_RD_VC2_CNTL 0x001e
+#define mmDAGB0_RD_VC2_CNTL_BASE_IDX 0
+#define mmDAGB0_RD_VC3_CNTL 0x001f
+#define mmDAGB0_RD_VC3_CNTL_BASE_IDX 0
+#define mmDAGB0_RD_VC4_CNTL 0x0020
+#define mmDAGB0_RD_VC4_CNTL_BASE_IDX 0
+#define mmDAGB0_RD_VC5_CNTL 0x0021
+#define mmDAGB0_RD_VC5_CNTL_BASE_IDX 0
+#define mmDAGB0_RD_VC6_CNTL 0x0022
+#define mmDAGB0_RD_VC6_CNTL_BASE_IDX 0
+#define mmDAGB0_RD_VC7_CNTL 0x0023
+#define mmDAGB0_RD_VC7_CNTL_BASE_IDX 0
+#define mmDAGB0_RD_CNTL_MISC 0x0024
+#define mmDAGB0_RD_CNTL_MISC_BASE_IDX 0
+#define mmDAGB0_RD_TLB_CREDIT 0x0025
+#define mmDAGB0_RD_TLB_CREDIT_BASE_IDX 0
+#define mmDAGB0_RDCLI_ASK_PENDING 0x0026
+#define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0
+#define mmDAGB0_RDCLI_GO_PENDING 0x0027
+#define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX 0
+#define mmDAGB0_RDCLI_GBLSEND_PENDING 0x0028
+#define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0
+#define mmDAGB0_RDCLI_TLB_PENDING 0x0029
+#define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0
+#define mmDAGB0_RDCLI_OARB_PENDING 0x002a
+#define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0
+#define mmDAGB0_RDCLI_OSD_PENDING 0x002b
+#define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0
+#define mmDAGB0_WRCLI0 0x002c
+#define mmDAGB0_WRCLI0_BASE_IDX 0
+#define mmDAGB0_WRCLI1 0x002d
+#define mmDAGB0_WRCLI1_BASE_IDX 0
+#define mmDAGB0_WRCLI2 0x002e
+#define mmDAGB0_WRCLI2_BASE_IDX 0
+#define mmDAGB0_WRCLI3 0x002f
+#define mmDAGB0_WRCLI3_BASE_IDX 0
+#define mmDAGB0_WRCLI4 0x0030
+#define mmDAGB0_WRCLI4_BASE_IDX 0
+#define mmDAGB0_WRCLI5 0x0031
+#define mmDAGB0_WRCLI5_BASE_IDX 0
+#define mmDAGB0_WRCLI6 0x0032
+#define mmDAGB0_WRCLI6_BASE_IDX 0
+#define mmDAGB0_WRCLI7 0x0033
+#define mmDAGB0_WRCLI7_BASE_IDX 0
+#define mmDAGB0_WRCLI8 0x0034
+#define mmDAGB0_WRCLI8_BASE_IDX 0
+#define mmDAGB0_WRCLI9 0x0035
+#define mmDAGB0_WRCLI9_BASE_IDX 0
+#define mmDAGB0_WRCLI10 0x0036
+#define mmDAGB0_WRCLI10_BASE_IDX 0
+#define mmDAGB0_WRCLI11 0x0037
+#define mmDAGB0_WRCLI11_BASE_IDX 0
+#define mmDAGB0_WRCLI12 0x0038
+#define mmDAGB0_WRCLI12_BASE_IDX 0
+#define mmDAGB0_WRCLI13 0x0039
+#define mmDAGB0_WRCLI13_BASE_IDX 0
+#define mmDAGB0_WRCLI14 0x003a
+#define mmDAGB0_WRCLI14_BASE_IDX 0
+#define mmDAGB0_WRCLI15 0x003b
+#define mmDAGB0_WRCLI15_BASE_IDX 0
+#define mmDAGB0_WR_CNTL 0x003c
+#define mmDAGB0_WR_CNTL_BASE_IDX 0
+#define mmDAGB0_WR_GMI_CNTL 0x003d
+#define mmDAGB0_WR_GMI_CNTL_BASE_IDX 0
+#define mmDAGB0_WR_ADDR_DAGB 0x003e
+#define mmDAGB0_WR_ADDR_DAGB_BASE_IDX 0
+#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x003f
+#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0040
+#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define mmDAGB0_WR_CGTT_CLK_CTRL 0x0041
+#define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0042
+#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x0043
+#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0044
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0045
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0046
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x0047
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define mmDAGB0_WR_DATA_DAGB 0x0048
+#define mmDAGB0_WR_DATA_DAGB_BASE_IDX 0
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0049
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x004a
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1 0x004b
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x004c
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define mmDAGB0_WR_VC0_CNTL 0x004d
+#define mmDAGB0_WR_VC0_CNTL_BASE_IDX 0
+#define mmDAGB0_WR_VC1_CNTL 0x004e
+#define mmDAGB0_WR_VC1_CNTL_BASE_IDX 0
+#define mmDAGB0_WR_VC2_CNTL 0x004f
+#define mmDAGB0_WR_VC2_CNTL_BASE_IDX 0
+#define mmDAGB0_WR_VC3_CNTL 0x0050
+#define mmDAGB0_WR_VC3_CNTL_BASE_IDX 0
+#define mmDAGB0_WR_VC4_CNTL 0x0051
+#define mmDAGB0_WR_VC4_CNTL_BASE_IDX 0
+#define mmDAGB0_WR_VC5_CNTL 0x0052
+#define mmDAGB0_WR_VC5_CNTL_BASE_IDX 0
+#define mmDAGB0_WR_VC6_CNTL 0x0053
+#define mmDAGB0_WR_VC6_CNTL_BASE_IDX 0
+#define mmDAGB0_WR_VC7_CNTL 0x0054
+#define mmDAGB0_WR_VC7_CNTL_BASE_IDX 0
+#define mmDAGB0_WR_CNTL_MISC 0x0055
+#define mmDAGB0_WR_CNTL_MISC_BASE_IDX 0
+#define mmDAGB0_WR_TLB_CREDIT 0x0056
+#define mmDAGB0_WR_TLB_CREDIT_BASE_IDX 0
+#define mmDAGB0_WR_DATA_CREDIT 0x0057
+#define mmDAGB0_WR_DATA_CREDIT_BASE_IDX 0
+#define mmDAGB0_WR_MISC_CREDIT 0x0058
+#define mmDAGB0_WR_MISC_CREDIT_BASE_IDX 0
+#define mmDAGB0_WRCLI_ASK_PENDING 0x0059
+#define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0
+#define mmDAGB0_WRCLI_GO_PENDING 0x005a
+#define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX 0
+#define mmDAGB0_WRCLI_GBLSEND_PENDING 0x005b
+#define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0
+#define mmDAGB0_WRCLI_TLB_PENDING 0x005c
+#define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0
+#define mmDAGB0_WRCLI_OARB_PENDING 0x005d
+#define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0
+#define mmDAGB0_WRCLI_OSD_PENDING 0x005e
+#define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0
+#define mmDAGB0_WRCLI_DBUS_ASK_PENDING 0x005f
+#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
+#define mmDAGB0_WRCLI_DBUS_GO_PENDING 0x0060
+#define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
+#define mmDAGB0_DAGB_DLY 0x0061
+#define mmDAGB0_DAGB_DLY_BASE_IDX 0
+#define mmDAGB0_CNTL_MISC 0x0062
+#define mmDAGB0_CNTL_MISC_BASE_IDX 0
+#define mmDAGB0_CNTL_MISC2 0x0063
+#define mmDAGB0_CNTL_MISC2_BASE_IDX 0
+#define mmDAGB0_FIFO_EMPTY 0x0064
+#define mmDAGB0_FIFO_EMPTY_BASE_IDX 0
+#define mmDAGB0_FIFO_FULL 0x0065
+#define mmDAGB0_FIFO_FULL_BASE_IDX 0
+#define mmDAGB0_WR_CREDITS_FULL 0x0066
+#define mmDAGB0_WR_CREDITS_FULL_BASE_IDX 0
+#define mmDAGB0_RD_CREDITS_FULL 0x0067
+#define mmDAGB0_RD_CREDITS_FULL_BASE_IDX 0
+#define mmDAGB0_PERFCOUNTER_LO 0x0068
+#define mmDAGB0_PERFCOUNTER_LO_BASE_IDX 0
+#define mmDAGB0_PERFCOUNTER_HI 0x0069
+#define mmDAGB0_PERFCOUNTER_HI_BASE_IDX 0
+#define mmDAGB0_PERFCOUNTER0_CFG 0x006a
+#define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0
+#define mmDAGB0_PERFCOUNTER1_CFG 0x006b
+#define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0
+#define mmDAGB0_PERFCOUNTER2_CFG 0x006c
+#define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0
+#define mmDAGB0_PERFCOUNTER_RSLT_CNTL 0x006d
+#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define mmDAGB0_RESERVE0 0x006e
+#define mmDAGB0_RESERVE0_BASE_IDX 0
+#define mmDAGB0_RESERVE1 0x006f
+#define mmDAGB0_RESERVE1_BASE_IDX 0
+#define mmDAGB0_RESERVE2 0x0070
+#define mmDAGB0_RESERVE2_BASE_IDX 0
+#define mmDAGB0_RESERVE3 0x0071
+#define mmDAGB0_RESERVE3_BASE_IDX 0
+#define mmDAGB0_RESERVE4 0x0072
+#define mmDAGB0_RESERVE4_BASE_IDX 0
+#define mmDAGB0_RESERVE5 0x0073
+#define mmDAGB0_RESERVE5_BASE_IDX 0
+#define mmDAGB0_RESERVE6 0x0074
+#define mmDAGB0_RESERVE6_BASE_IDX 0
+#define mmDAGB0_RESERVE7 0x0075
+#define mmDAGB0_RESERVE7_BASE_IDX 0
+#define mmDAGB0_RESERVE8 0x0076
+#define mmDAGB0_RESERVE8_BASE_IDX 0
+#define mmDAGB0_RESERVE9 0x0077
+#define mmDAGB0_RESERVE9_BASE_IDX 0
+#define mmDAGB0_RESERVE10 0x0078
+#define mmDAGB0_RESERVE10_BASE_IDX 0
+#define mmDAGB0_RESERVE11 0x0079
+#define mmDAGB0_RESERVE11_BASE_IDX 0
+#define mmDAGB0_RESERVE12 0x007a
+#define mmDAGB0_RESERVE12_BASE_IDX 0
+#define mmDAGB0_RESERVE13 0x007b
+#define mmDAGB0_RESERVE13_BASE_IDX 0
+#define mmDAGB0_RESERVE14 0x007c
+#define mmDAGB0_RESERVE14_BASE_IDX 0
+#define mmDAGB0_RESERVE15 0x007d
+#define mmDAGB0_RESERVE15_BASE_IDX 0
+#define mmDAGB0_RESERVE16 0x007e
+#define mmDAGB0_RESERVE16_BASE_IDX 0
+#define mmDAGB0_RESERVE17 0x007f
+#define mmDAGB0_RESERVE17_BASE_IDX 0
+#define mmDAGB1_RDCLI0 0x0080
+#define mmDAGB1_RDCLI0_BASE_IDX 0
+#define mmDAGB1_RDCLI1 0x0081
+#define mmDAGB1_RDCLI1_BASE_IDX 0
+#define mmDAGB1_RDCLI2 0x0082
+#define mmDAGB1_RDCLI2_BASE_IDX 0
+#define mmDAGB1_RDCLI3 0x0083
+#define mmDAGB1_RDCLI3_BASE_IDX 0
+#define mmDAGB1_RDCLI4 0x0084
+#define mmDAGB1_RDCLI4_BASE_IDX 0
+#define mmDAGB1_RDCLI5 0x0085
+#define mmDAGB1_RDCLI5_BASE_IDX 0
+#define mmDAGB1_RDCLI6 0x0086
+#define mmDAGB1_RDCLI6_BASE_IDX 0
+#define mmDAGB1_RDCLI7 0x0087
+#define mmDAGB1_RDCLI7_BASE_IDX 0
+#define mmDAGB1_RDCLI8 0x0088
+#define mmDAGB1_RDCLI8_BASE_IDX 0
+#define mmDAGB1_RDCLI9 0x0089
+#define mmDAGB1_RDCLI9_BASE_IDX 0
+#define mmDAGB1_RDCLI10 0x008a
+#define mmDAGB1_RDCLI10_BASE_IDX 0
+#define mmDAGB1_RDCLI11 0x008b
+#define mmDAGB1_RDCLI11_BASE_IDX 0
+#define mmDAGB1_RDCLI12 0x008c
+#define mmDAGB1_RDCLI12_BASE_IDX 0
+#define mmDAGB1_RDCLI13 0x008d
+#define mmDAGB1_RDCLI13_BASE_IDX 0
+#define mmDAGB1_RDCLI14 0x008e
+#define mmDAGB1_RDCLI14_BASE_IDX 0
+#define mmDAGB1_RDCLI15 0x008f
+#define mmDAGB1_RDCLI15_BASE_IDX 0
+#define mmDAGB1_RD_CNTL 0x0090
+#define mmDAGB1_RD_CNTL_BASE_IDX 0
+#define mmDAGB1_RD_GMI_CNTL 0x0091
+#define mmDAGB1_RD_GMI_CNTL_BASE_IDX 0
+#define mmDAGB1_RD_ADDR_DAGB 0x0092
+#define mmDAGB1_RD_ADDR_DAGB_BASE_IDX 0
+#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST 0x0093
+#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 0x0094
+#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define mmDAGB1_RD_CGTT_CLK_CTRL 0x0095
+#define mmDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x0096
+#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL 0x0097
+#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x0098
+#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x0099
+#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x009a
+#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x009b
+#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define mmDAGB1_RD_VC0_CNTL 0x009c
+#define mmDAGB1_RD_VC0_CNTL_BASE_IDX 0
+#define mmDAGB1_RD_VC1_CNTL 0x009d
+#define mmDAGB1_RD_VC1_CNTL_BASE_IDX 0
+#define mmDAGB1_RD_VC2_CNTL 0x009e
+#define mmDAGB1_RD_VC2_CNTL_BASE_IDX 0
+#define mmDAGB1_RD_VC3_CNTL 0x009f
+#define mmDAGB1_RD_VC3_CNTL_BASE_IDX 0
+#define mmDAGB1_RD_VC4_CNTL 0x00a0
+#define mmDAGB1_RD_VC4_CNTL_BASE_IDX 0
+#define mmDAGB1_RD_VC5_CNTL 0x00a1
+#define mmDAGB1_RD_VC5_CNTL_BASE_IDX 0
+#define mmDAGB1_RD_VC6_CNTL 0x00a2
+#define mmDAGB1_RD_VC6_CNTL_BASE_IDX 0
+#define mmDAGB1_RD_VC7_CNTL 0x00a3
+#define mmDAGB1_RD_VC7_CNTL_BASE_IDX 0
+#define mmDAGB1_RD_CNTL_MISC 0x00a4
+#define mmDAGB1_RD_CNTL_MISC_BASE_IDX 0
+#define mmDAGB1_RD_TLB_CREDIT 0x00a5
+#define mmDAGB1_RD_TLB_CREDIT_BASE_IDX 0
+#define mmDAGB1_RDCLI_ASK_PENDING 0x00a6
+#define mmDAGB1_RDCLI_ASK_PENDING_BASE_IDX 0
+#define mmDAGB1_RDCLI_GO_PENDING 0x00a7
+#define mmDAGB1_RDCLI_GO_PENDING_BASE_IDX 0
+#define mmDAGB1_RDCLI_GBLSEND_PENDING 0x00a8
+#define mmDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 0
+#define mmDAGB1_RDCLI_TLB_PENDING 0x00a9
+#define mmDAGB1_RDCLI_TLB_PENDING_BASE_IDX 0
+#define mmDAGB1_RDCLI_OARB_PENDING 0x00aa
+#define mmDAGB1_RDCLI_OARB_PENDING_BASE_IDX 0
+#define mmDAGB1_RDCLI_OSD_PENDING 0x00ab
+#define mmDAGB1_RDCLI_OSD_PENDING_BASE_IDX 0
+#define mmDAGB1_WRCLI0 0x00ac
+#define mmDAGB1_WRCLI0_BASE_IDX 0
+#define mmDAGB1_WRCLI1 0x00ad
+#define mmDAGB1_WRCLI1_BASE_IDX 0
+#define mmDAGB1_WRCLI2 0x00ae
+#define mmDAGB1_WRCLI2_BASE_IDX 0
+#define mmDAGB1_WRCLI3 0x00af
+#define mmDAGB1_WRCLI3_BASE_IDX 0
+#define mmDAGB1_WRCLI4 0x00b0
+#define mmDAGB1_WRCLI4_BASE_IDX 0
+#define mmDAGB1_WRCLI5 0x00b1
+#define mmDAGB1_WRCLI5_BASE_IDX 0
+#define mmDAGB1_WRCLI6 0x00b2
+#define mmDAGB1_WRCLI6_BASE_IDX 0
+#define mmDAGB1_WRCLI7 0x00b3
+#define mmDAGB1_WRCLI7_BASE_IDX 0
+#define mmDAGB1_WRCLI8 0x00b4
+#define mmDAGB1_WRCLI8_BASE_IDX 0
+#define mmDAGB1_WRCLI9 0x00b5
+#define mmDAGB1_WRCLI9_BASE_IDX 0
+#define mmDAGB1_WRCLI10 0x00b6
+#define mmDAGB1_WRCLI10_BASE_IDX 0
+#define mmDAGB1_WRCLI11 0x00b7
+#define mmDAGB1_WRCLI11_BASE_IDX 0
+#define mmDAGB1_WRCLI12 0x00b8
+#define mmDAGB1_WRCLI12_BASE_IDX 0
+#define mmDAGB1_WRCLI13 0x00b9
+#define mmDAGB1_WRCLI13_BASE_IDX 0
+#define mmDAGB1_WRCLI14 0x00ba
+#define mmDAGB1_WRCLI14_BASE_IDX 0
+#define mmDAGB1_WRCLI15 0x00bb
+#define mmDAGB1_WRCLI15_BASE_IDX 0
+#define mmDAGB1_WR_CNTL 0x00bc
+#define mmDAGB1_WR_CNTL_BASE_IDX 0
+#define mmDAGB1_WR_GMI_CNTL 0x00bd
+#define mmDAGB1_WR_GMI_CNTL_BASE_IDX 0
+#define mmDAGB1_WR_ADDR_DAGB 0x00be
+#define mmDAGB1_WR_ADDR_DAGB_BASE_IDX 0
+#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST 0x00bf
+#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 0x00c0
+#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define mmDAGB1_WR_CGTT_CLK_CTRL 0x00c1
+#define mmDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0x00c2
+#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL 0x00c3
+#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0 0x00c4
+#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0x00c5
+#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1 0x00c6
+#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 0x00c7
+#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define mmDAGB1_WR_DATA_DAGB 0x00c8
+#define mmDAGB1_WR_DATA_DAGB_BASE_IDX 0
+#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0 0x00c9
+#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
+#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0 0x00ca
+#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1 0x00cb
+#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
+#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1 0x00cc
+#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define mmDAGB1_WR_VC0_CNTL 0x00cd
+#define mmDAGB1_WR_VC0_CNTL_BASE_IDX 0
+#define mmDAGB1_WR_VC1_CNTL 0x00ce
+#define mmDAGB1_WR_VC1_CNTL_BASE_IDX 0
+#define mmDAGB1_WR_VC2_CNTL 0x00cf
+#define mmDAGB1_WR_VC2_CNTL_BASE_IDX 0
+#define mmDAGB1_WR_VC3_CNTL 0x00d0
+#define mmDAGB1_WR_VC3_CNTL_BASE_IDX 0
+#define mmDAGB1_WR_VC4_CNTL 0x00d1
+#define mmDAGB1_WR_VC4_CNTL_BASE_IDX 0
+#define mmDAGB1_WR_VC5_CNTL 0x00d2
+#define mmDAGB1_WR_VC5_CNTL_BASE_IDX 0
+#define mmDAGB1_WR_VC6_CNTL 0x00d3
+#define mmDAGB1_WR_VC6_CNTL_BASE_IDX 0
+#define mmDAGB1_WR_VC7_CNTL 0x00d4
+#define mmDAGB1_WR_VC7_CNTL_BASE_IDX 0
+#define mmDAGB1_WR_CNTL_MISC 0x00d5
+#define mmDAGB1_WR_CNTL_MISC_BASE_IDX 0
+#define mmDAGB1_WR_TLB_CREDIT 0x00d6
+#define mmDAGB1_WR_TLB_CREDIT_BASE_IDX 0
+#define mmDAGB1_WR_DATA_CREDIT 0x00d7
+#define mmDAGB1_WR_DATA_CREDIT_BASE_IDX 0
+#define mmDAGB1_WR_MISC_CREDIT 0x00d8
+#define mmDAGB1_WR_MISC_CREDIT_BASE_IDX 0
+#define mmDAGB1_WRCLI_ASK_PENDING 0x00d9
+#define mmDAGB1_WRCLI_ASK_PENDING_BASE_IDX 0
+#define mmDAGB1_WRCLI_GO_PENDING 0x00da
+#define mmDAGB1_WRCLI_GO_PENDING_BASE_IDX 0
+#define mmDAGB1_WRCLI_GBLSEND_PENDING 0x00db
+#define mmDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX 0
+#define mmDAGB1_WRCLI_TLB_PENDING 0x00dc
+#define mmDAGB1_WRCLI_TLB_PENDING_BASE_IDX 0
+#define mmDAGB1_WRCLI_OARB_PENDING 0x00dd
+#define mmDAGB1_WRCLI_OARB_PENDING_BASE_IDX 0
+#define mmDAGB1_WRCLI_OSD_PENDING 0x00de
+#define mmDAGB1_WRCLI_OSD_PENDING_BASE_IDX 0
+#define mmDAGB1_WRCLI_DBUS_ASK_PENDING 0x00df
+#define mmDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
+#define mmDAGB1_WRCLI_DBUS_GO_PENDING 0x00e0
+#define mmDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
+#define mmDAGB1_DAGB_DLY 0x00e1
+#define mmDAGB1_DAGB_DLY_BASE_IDX 0
+#define mmDAGB1_CNTL_MISC 0x00e2
+#define mmDAGB1_CNTL_MISC_BASE_IDX 0
+#define mmDAGB1_CNTL_MISC2 0x00e3
+#define mmDAGB1_CNTL_MISC2_BASE_IDX 0
+#define mmDAGB1_FIFO_EMPTY 0x00e4
+#define mmDAGB1_FIFO_EMPTY_BASE_IDX 0
+#define mmDAGB1_FIFO_FULL 0x00e5
+#define mmDAGB1_FIFO_FULL_BASE_IDX 0
+#define mmDAGB1_WR_CREDITS_FULL 0x00e6
+#define mmDAGB1_WR_CREDITS_FULL_BASE_IDX 0
+#define mmDAGB1_RD_CREDITS_FULL 0x00e7
+#define mmDAGB1_RD_CREDITS_FULL_BASE_IDX 0
+#define mmDAGB1_PERFCOUNTER_LO 0x00e8
+#define mmDAGB1_PERFCOUNTER_LO_BASE_IDX 0
+#define mmDAGB1_PERFCOUNTER_HI 0x00e9
+#define mmDAGB1_PERFCOUNTER_HI_BASE_IDX 0
+#define mmDAGB1_PERFCOUNTER0_CFG 0x00ea
+#define mmDAGB1_PERFCOUNTER0_CFG_BASE_IDX 0
+#define mmDAGB1_PERFCOUNTER1_CFG 0x00eb
+#define mmDAGB1_PERFCOUNTER1_CFG_BASE_IDX 0
+#define mmDAGB1_PERFCOUNTER2_CFG 0x00ec
+#define mmDAGB1_PERFCOUNTER2_CFG_BASE_IDX 0
+#define mmDAGB1_PERFCOUNTER_RSLT_CNTL 0x00ed
+#define mmDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define mmDAGB1_RESERVE0 0x00ee
+#define mmDAGB1_RESERVE0_BASE_IDX 0
+#define mmDAGB1_RESERVE1 0x00ef
+#define mmDAGB1_RESERVE1_BASE_IDX 0
+#define mmDAGB1_RESERVE2 0x00f0
+#define mmDAGB1_RESERVE2_BASE_IDX 0
+#define mmDAGB1_RESERVE3 0x00f1
+#define mmDAGB1_RESERVE3_BASE_IDX 0
+#define mmDAGB1_RESERVE4 0x00f2
+#define mmDAGB1_RESERVE4_BASE_IDX 0
+#define mmDAGB1_RESERVE5 0x00f3
+#define mmDAGB1_RESERVE5_BASE_IDX 0
+#define mmDAGB1_RESERVE6 0x00f4
+#define mmDAGB1_RESERVE6_BASE_IDX 0
+#define mmDAGB1_RESERVE7 0x00f5
+#define mmDAGB1_RESERVE7_BASE_IDX 0
+#define mmDAGB1_RESERVE8 0x00f6
+#define mmDAGB1_RESERVE8_BASE_IDX 0
+#define mmDAGB1_RESERVE9 0x00f7
+#define mmDAGB1_RESERVE9_BASE_IDX 0
+#define mmDAGB1_RESERVE10 0x00f8
+#define mmDAGB1_RESERVE10_BASE_IDX 0
+#define mmDAGB1_RESERVE11 0x00f9
+#define mmDAGB1_RESERVE11_BASE_IDX 0
+#define mmDAGB1_RESERVE12 0x00fa
+#define mmDAGB1_RESERVE12_BASE_IDX 0
+#define mmDAGB1_RESERVE13 0x00fb
+#define mmDAGB1_RESERVE13_BASE_IDX 0
+#define mmDAGB1_RESERVE14 0x00fc
+#define mmDAGB1_RESERVE14_BASE_IDX 0
+#define mmDAGB1_RESERVE15 0x00fd
+#define mmDAGB1_RESERVE15_BASE_IDX 0
+#define mmDAGB1_RESERVE16 0x00fe
+#define mmDAGB1_RESERVE16_BASE_IDX 0
+#define mmDAGB1_RESERVE17 0x00ff
+#define mmDAGB1_RESERVE17_BASE_IDX 0
+
+
+// addressBlock: mmhub_ea_mmeadec
+// base address: 0x68400
+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0100
+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0101
+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0102
+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0103
+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_GRP2VC_MAP 0x0104
+#define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_GRP2VC_MAP 0x0105
+#define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_LAZY 0x0106
+#define mmMMEA0_DRAM_RD_LAZY_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_LAZY 0x0107
+#define mmMMEA0_DRAM_WR_LAZY_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_CAM_CNTL 0x0108
+#define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_CAM_CNTL 0x0109
+#define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 0
+#define mmMMEA0_DRAM_PAGE_BURST 0x010a
+#define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_PRI_AGE 0x010b
+#define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_PRI_AGE 0x010c
+#define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_PRI_QUEUING 0x010d
+#define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_PRI_QUEUING 0x010e
+#define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_PRI_FIXED 0x010f
+#define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_PRI_FIXED 0x0110
+#define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_PRI_URGENCY 0x0111
+#define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_PRI_URGENCY 0x0112
+#define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0113
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0114
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0115
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0116
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0117
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0118
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define mmMMEA0_ADDRNORM_BASE_ADDR0 0x0132
+#define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 0
+#define mmMMEA0_ADDRNORM_LIMIT_ADDR0 0x0133
+#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
+#define mmMMEA0_ADDRNORM_BASE_ADDR1 0x0134
+#define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 0
+#define mmMMEA0_ADDRNORM_LIMIT_ADDR1 0x0135
+#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
+#define mmMMEA0_ADDRNORM_OFFSET_ADDR1 0x0136
+#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
+#define mmMMEA0_ADDRNORM_HOLE_CNTL 0x0141
+#define mmMMEA0_ADDRNORM_HOLE_CNTL_BASE_IDX 0
+#define mmMMEA0_ADDRDEC_BANK_CFG 0x0142
+#define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 0
+#define mmMMEA0_ADDRDEC_MISC_CFG 0x0143
+#define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 0x0144
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 0x0145
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 0x0146
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 0x0147
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 0x0148
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC 0x0149
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 0x014a
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 0x014b
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 0x014c
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x014d
+#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x0158
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x0159
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x015a
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x015b
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x015c
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x015d
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x015e
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x015f
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x0160
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x0161
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x0162
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x0163
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x0164
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x0165
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x0166
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x0167
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x0168
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x0169
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x016a
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x016b
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS01 0x016c
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS23 0x016d
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01 0x016e
+#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23 0x016f
+#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x0170
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x0171
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x0172
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x0173
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x0174
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x0175
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x0176
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x0177
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x0178
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x0179
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x017a
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x017b
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x017c
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x017d
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x017e
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x017f
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x0180
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x0181
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x0182
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x0183
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS01 0x0184
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS23 0x0185
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01 0x0186
+#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23 0x0187
+#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
+#define mmMMEA0_IO_RD_CLI2GRP_MAP0 0x01d0
+#define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define mmMMEA0_IO_RD_CLI2GRP_MAP1 0x01d1
+#define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define mmMMEA0_IO_WR_CLI2GRP_MAP0 0x01d2
+#define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define mmMMEA0_IO_WR_CLI2GRP_MAP1 0x01d3
+#define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define mmMMEA0_IO_RD_COMBINE_FLUSH 0x01d4
+#define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 0
+#define mmMMEA0_IO_WR_COMBINE_FLUSH 0x01d5
+#define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 0
+#define mmMMEA0_IO_GROUP_BURST 0x01d6
+#define mmMMEA0_IO_GROUP_BURST_BASE_IDX 0
+#define mmMMEA0_IO_RD_PRI_AGE 0x01d7
+#define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX 0
+#define mmMMEA0_IO_WR_PRI_AGE 0x01d8
+#define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX 0
+#define mmMMEA0_IO_RD_PRI_QUEUING 0x01d9
+#define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 0
+#define mmMMEA0_IO_WR_PRI_QUEUING 0x01da
+#define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 0
+#define mmMMEA0_IO_RD_PRI_FIXED 0x01db
+#define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX 0
+#define mmMMEA0_IO_WR_PRI_FIXED 0x01dc
+#define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX 0
+#define mmMMEA0_IO_RD_PRI_URGENCY 0x01dd
+#define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 0
+#define mmMMEA0_IO_WR_PRI_URGENCY 0x01de
+#define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 0
+#define mmMMEA0_IO_RD_PRI_URGENCY_MASK 0x01df
+#define mmMMEA0_IO_RD_PRI_URGENCY_MASK_BASE_IDX 0
+#define mmMMEA0_IO_WR_PRI_URGENCY_MASK 0x01e0
+#define mmMMEA0_IO_WR_PRI_URGENCY_MASK_BASE_IDX 0
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI1 0x01e1
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI2 0x01e2
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI3 0x01e3
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI1 0x01e4
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI2 0x01e5
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI3 0x01e6
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define mmMMEA0_SDP_ARB_DRAM 0x01e7
+#define mmMMEA0_SDP_ARB_DRAM_BASE_IDX 0
+#define mmMMEA0_SDP_ARB_FINAL 0x01e9
+#define mmMMEA0_SDP_ARB_FINAL_BASE_IDX 0
+#define mmMMEA0_SDP_DRAM_PRIORITY 0x01ea
+#define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 0
+#define mmMMEA0_SDP_IO_PRIORITY 0x01ec
+#define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX 0
+#define mmMMEA0_SDP_CREDITS 0x01ed
+#define mmMMEA0_SDP_CREDITS_BASE_IDX 0
+#define mmMMEA0_SDP_TAG_RESERVE0 0x01ee
+#define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX 0
+#define mmMMEA0_SDP_TAG_RESERVE1 0x01ef
+#define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX 0
+#define mmMMEA0_SDP_VCC_RESERVE0 0x01f0
+#define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX 0
+#define mmMMEA0_SDP_VCC_RESERVE1 0x01f1
+#define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX 0
+#define mmMMEA0_SDP_VCD_RESERVE0 0x01f2
+#define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX 0
+#define mmMMEA0_SDP_VCD_RESERVE1 0x01f3
+#define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX 0
+#define mmMMEA0_SDP_REQ_CNTL 0x01f4
+#define mmMMEA0_SDP_REQ_CNTL_BASE_IDX 0
+#define mmMMEA0_MISC 0x01f5
+#define mmMMEA0_MISC_BASE_IDX 0
+#define mmMMEA0_LATENCY_SAMPLING 0x01f6
+#define mmMMEA0_LATENCY_SAMPLING_BASE_IDX 0
+#define mmMMEA0_PERFCOUNTER_LO 0x01f7
+#define mmMMEA0_PERFCOUNTER_LO_BASE_IDX 0
+#define mmMMEA0_PERFCOUNTER_HI 0x01f8
+#define mmMMEA0_PERFCOUNTER_HI_BASE_IDX 0
+#define mmMMEA0_PERFCOUNTER0_CFG 0x01f9
+#define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX 0
+#define mmMMEA0_PERFCOUNTER1_CFG 0x01fa
+#define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX 0
+#define mmMMEA0_PERFCOUNTER_RSLT_CNTL 0x01fb
+#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define mmMMEA0_EDC_CNT 0x0201
+#define mmMMEA0_EDC_CNT_BASE_IDX 0
+#define mmMMEA0_EDC_CNT2 0x0202
+#define mmMMEA0_EDC_CNT2_BASE_IDX 0
+#define mmMMEA0_DSM_CNTL 0x0203
+#define mmMMEA0_DSM_CNTL_BASE_IDX 0
+#define mmMMEA0_DSM_CNTLA 0x0204
+#define mmMMEA0_DSM_CNTLA_BASE_IDX 0
+#define mmMMEA0_DSM_CNTLB 0x0205
+#define mmMMEA0_DSM_CNTLB_BASE_IDX 0
+#define mmMMEA0_DSM_CNTL2 0x0206
+#define mmMMEA0_DSM_CNTL2_BASE_IDX 0
+#define mmMMEA0_DSM_CNTL2A 0x0207
+#define mmMMEA0_DSM_CNTL2A_BASE_IDX 0
+#define mmMMEA0_DSM_CNTL2B 0x0208
+#define mmMMEA0_DSM_CNTL2B_BASE_IDX 0
+#define mmMMEA0_CGTT_CLK_CTRL 0x020a
+#define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmMMEA0_EDC_MODE 0x020b
+#define mmMMEA0_EDC_MODE_BASE_IDX 0
+#define mmMMEA0_ERR_STATUS 0x020c
+#define mmMMEA0_ERR_STATUS_BASE_IDX 0
+#define mmMMEA0_MISC2 0x020d
+#define mmMMEA0_MISC2_BASE_IDX 0
+#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0 0x0240
+#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1 0x0241
+#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0 0x0242
+#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1 0x0243
+#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define mmMMEA1_DRAM_RD_GRP2VC_MAP 0x0244
+#define mmMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
+#define mmMMEA1_DRAM_WR_GRP2VC_MAP 0x0245
+#define mmMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
+#define mmMMEA1_DRAM_RD_LAZY 0x0246
+#define mmMMEA1_DRAM_RD_LAZY_BASE_IDX 0
+#define mmMMEA1_DRAM_WR_LAZY 0x0247
+#define mmMMEA1_DRAM_WR_LAZY_BASE_IDX 0
+#define mmMMEA1_DRAM_RD_CAM_CNTL 0x0248
+#define mmMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX 0
+#define mmMMEA1_DRAM_WR_CAM_CNTL 0x0249
+#define mmMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX 0
+#define mmMMEA1_DRAM_PAGE_BURST 0x024a
+#define mmMMEA1_DRAM_PAGE_BURST_BASE_IDX 0
+#define mmMMEA1_DRAM_RD_PRI_AGE 0x024b
+#define mmMMEA1_DRAM_RD_PRI_AGE_BASE_IDX 0
+#define mmMMEA1_DRAM_WR_PRI_AGE 0x024c
+#define mmMMEA1_DRAM_WR_PRI_AGE_BASE_IDX 0
+#define mmMMEA1_DRAM_RD_PRI_QUEUING 0x024d
+#define mmMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX 0
+#define mmMMEA1_DRAM_WR_PRI_QUEUING 0x024e
+#define mmMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX 0
+#define mmMMEA1_DRAM_RD_PRI_FIXED 0x024f
+#define mmMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX 0
+#define mmMMEA1_DRAM_WR_PRI_FIXED 0x0250
+#define mmMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX 0
+#define mmMMEA1_DRAM_RD_PRI_URGENCY 0x0251
+#define mmMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX 0
+#define mmMMEA1_DRAM_WR_PRI_URGENCY 0x0252
+#define mmMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX 0
+#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1 0x0253
+#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2 0x0254
+#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3 0x0255
+#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1 0x0256
+#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2 0x0257
+#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3 0x0258
+#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define mmMMEA1_ADDRNORM_BASE_ADDR0 0x0272
+#define mmMMEA1_ADDRNORM_BASE_ADDR0_BASE_IDX 0
+#define mmMMEA1_ADDRNORM_LIMIT_ADDR0 0x0273
+#define mmMMEA1_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
+#define mmMMEA1_ADDRNORM_BASE_ADDR1 0x0274
+#define mmMMEA1_ADDRNORM_BASE_ADDR1_BASE_IDX 0
+#define mmMMEA1_ADDRNORM_LIMIT_ADDR1 0x0275
+#define mmMMEA1_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
+#define mmMMEA1_ADDRNORM_OFFSET_ADDR1 0x0276
+#define mmMMEA1_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
+#define mmMMEA1_ADDRNORM_HOLE_CNTL 0x0281
+#define mmMMEA1_ADDRNORM_HOLE_CNTL_BASE_IDX 0
+#define mmMMEA1_ADDRDEC_BANK_CFG 0x0282
+#define mmMMEA1_ADDRDEC_BANK_CFG_BASE_IDX 0
+#define mmMMEA1_ADDRDEC_MISC_CFG 0x0283
+#define mmMMEA1_ADDRDEC_MISC_CFG_BASE_IDX 0
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 0x0284
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 0x0285
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 0x0286
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 0x0287
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 0x0288
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC 0x0289
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2 0x028a
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0 0x028b
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1 0x028c
+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0
+#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE 0x028d
+#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0 0x0298
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1 0x0299
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2 0x029a
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3 0x029b
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 0x029c
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 0x029d
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 0x029e
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 0x029f
+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01 0x02a0
+#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23 0x02a1
+#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 0x02a2
+#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 0x02a3
+#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01 0x02a4
+#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23 0x02a5
+#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01 0x02a6
+#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23 0x02a7
+#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01 0x02a8
+#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23 0x02a9
+#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01 0x02aa
+#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23 0x02ab
+#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_RM_SEL_CS01 0x02ac
+#define mmMMEA1_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_RM_SEL_CS23 0x02ad
+#define mmMMEA1_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01 0x02ae
+#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
+#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23 0x02af
+#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0 0x02b0
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1 0x02b1
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2 0x02b2
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3 0x02b3
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 0x02b4
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 0x02b5
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 0x02b6
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 0x02b7
+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01 0x02b8
+#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23 0x02b9
+#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 0x02ba
+#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 0x02bb
+#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01 0x02bc
+#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23 0x02bd
+#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01 0x02be
+#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23 0x02bf
+#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01 0x02c0
+#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23 0x02c1
+#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01 0x02c2
+#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23 0x02c3
+#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_RM_SEL_CS01 0x02c4
+#define mmMMEA1_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_RM_SEL_CS23 0x02c5
+#define mmMMEA1_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01 0x02c6
+#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
+#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23 0x02c7
+#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
+#define mmMMEA1_IO_RD_CLI2GRP_MAP0 0x0310
+#define mmMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define mmMMEA1_IO_RD_CLI2GRP_MAP1 0x0311
+#define mmMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define mmMMEA1_IO_WR_CLI2GRP_MAP0 0x0312
+#define mmMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define mmMMEA1_IO_WR_CLI2GRP_MAP1 0x0313
+#define mmMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define mmMMEA1_IO_RD_COMBINE_FLUSH 0x0314
+#define mmMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX 0
+#define mmMMEA1_IO_WR_COMBINE_FLUSH 0x0315
+#define mmMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX 0
+#define mmMMEA1_IO_GROUP_BURST 0x0316
+#define mmMMEA1_IO_GROUP_BURST_BASE_IDX 0
+#define mmMMEA1_IO_RD_PRI_AGE 0x0317
+#define mmMMEA1_IO_RD_PRI_AGE_BASE_IDX 0
+#define mmMMEA1_IO_WR_PRI_AGE 0x0318
+#define mmMMEA1_IO_WR_PRI_AGE_BASE_IDX 0
+#define mmMMEA1_IO_RD_PRI_QUEUING 0x0319
+#define mmMMEA1_IO_RD_PRI_QUEUING_BASE_IDX 0
+#define mmMMEA1_IO_WR_PRI_QUEUING 0x031a
+#define mmMMEA1_IO_WR_PRI_QUEUING_BASE_IDX 0
+#define mmMMEA1_IO_RD_PRI_FIXED 0x031b
+#define mmMMEA1_IO_RD_PRI_FIXED_BASE_IDX 0
+#define mmMMEA1_IO_WR_PRI_FIXED 0x031c
+#define mmMMEA1_IO_WR_PRI_FIXED_BASE_IDX 0
+#define mmMMEA1_IO_RD_PRI_URGENCY 0x031d
+#define mmMMEA1_IO_RD_PRI_URGENCY_BASE_IDX 0
+#define mmMMEA1_IO_WR_PRI_URGENCY 0x031e
+#define mmMMEA1_IO_WR_PRI_URGENCY_BASE_IDX 0
+#define mmMMEA1_IO_RD_PRI_URGENCY_MASK 0x031f
+#define mmMMEA1_IO_RD_PRI_URGENCY_MASK_BASE_IDX 0
+#define mmMMEA1_IO_WR_PRI_URGENCY_MASK 0x0320
+#define mmMMEA1_IO_WR_PRI_URGENCY_MASK_BASE_IDX 0
+#define mmMMEA1_IO_RD_PRI_QUANT_PRI1 0x0321
+#define mmMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define mmMMEA1_IO_RD_PRI_QUANT_PRI2 0x0322
+#define mmMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define mmMMEA1_IO_RD_PRI_QUANT_PRI3 0x0323
+#define mmMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define mmMMEA1_IO_WR_PRI_QUANT_PRI1 0x0324
+#define mmMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define mmMMEA1_IO_WR_PRI_QUANT_PRI2 0x0325
+#define mmMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define mmMMEA1_IO_WR_PRI_QUANT_PRI3 0x0326
+#define mmMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define mmMMEA1_SDP_ARB_DRAM 0x0327
+#define mmMMEA1_SDP_ARB_DRAM_BASE_IDX 0
+#define mmMMEA1_SDP_ARB_FINAL 0x0329
+#define mmMMEA1_SDP_ARB_FINAL_BASE_IDX 0
+#define mmMMEA1_SDP_DRAM_PRIORITY 0x032a
+#define mmMMEA1_SDP_DRAM_PRIORITY_BASE_IDX 0
+#define mmMMEA1_SDP_IO_PRIORITY 0x032c
+#define mmMMEA1_SDP_IO_PRIORITY_BASE_IDX 0
+#define mmMMEA1_SDP_CREDITS 0x032d
+#define mmMMEA1_SDP_CREDITS_BASE_IDX 0
+#define mmMMEA1_SDP_TAG_RESERVE0 0x032e
+#define mmMMEA1_SDP_TAG_RESERVE0_BASE_IDX 0
+#define mmMMEA1_SDP_TAG_RESERVE1 0x032f
+#define mmMMEA1_SDP_TAG_RESERVE1_BASE_IDX 0
+#define mmMMEA1_SDP_VCC_RESERVE0 0x0330
+#define mmMMEA1_SDP_VCC_RESERVE0_BASE_IDX 0
+#define mmMMEA1_SDP_VCC_RESERVE1 0x0331
+#define mmMMEA1_SDP_VCC_RESERVE1_BASE_IDX 0
+#define mmMMEA1_SDP_VCD_RESERVE0 0x0332
+#define mmMMEA1_SDP_VCD_RESERVE0_BASE_IDX 0
+#define mmMMEA1_SDP_VCD_RESERVE1 0x0333
+#define mmMMEA1_SDP_VCD_RESERVE1_BASE_IDX 0
+#define mmMMEA1_SDP_REQ_CNTL 0x0334
+#define mmMMEA1_SDP_REQ_CNTL_BASE_IDX 0
+#define mmMMEA1_MISC 0x0335
+#define mmMMEA1_MISC_BASE_IDX 0
+#define mmMMEA1_LATENCY_SAMPLING 0x0336
+#define mmMMEA1_LATENCY_SAMPLING_BASE_IDX 0
+#define mmMMEA1_PERFCOUNTER_LO 0x0337
+#define mmMMEA1_PERFCOUNTER_LO_BASE_IDX 0
+#define mmMMEA1_PERFCOUNTER_HI 0x0338
+#define mmMMEA1_PERFCOUNTER_HI_BASE_IDX 0
+#define mmMMEA1_PERFCOUNTER0_CFG 0x0339
+#define mmMMEA1_PERFCOUNTER0_CFG_BASE_IDX 0
+#define mmMMEA1_PERFCOUNTER1_CFG 0x033a
+#define mmMMEA1_PERFCOUNTER1_CFG_BASE_IDX 0
+#define mmMMEA1_PERFCOUNTER_RSLT_CNTL 0x033b
+#define mmMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define mmMMEA1_EDC_CNT 0x0341
+#define mmMMEA1_EDC_CNT_BASE_IDX 0
+#define mmMMEA1_EDC_CNT2 0x0342
+#define mmMMEA1_EDC_CNT2_BASE_IDX 0
+#define mmMMEA1_DSM_CNTL 0x0343
+#define mmMMEA1_DSM_CNTL_BASE_IDX 0
+#define mmMMEA1_DSM_CNTLA 0x0344
+#define mmMMEA1_DSM_CNTLA_BASE_IDX 0
+#define mmMMEA1_DSM_CNTLB 0x0345
+#define mmMMEA1_DSM_CNTLB_BASE_IDX 0
+#define mmMMEA1_DSM_CNTL2 0x0346
+#define mmMMEA1_DSM_CNTL2_BASE_IDX 0
+#define mmMMEA1_DSM_CNTL2A 0x0347
+#define mmMMEA1_DSM_CNTL2A_BASE_IDX 0
+#define mmMMEA1_DSM_CNTL2B 0x0348
+#define mmMMEA1_DSM_CNTL2B_BASE_IDX 0
+#define mmMMEA1_CGTT_CLK_CTRL 0x034a
+#define mmMMEA1_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmMMEA1_EDC_MODE 0x034b
+#define mmMMEA1_EDC_MODE_BASE_IDX 0
+#define mmMMEA1_ERR_STATUS 0x034c
+#define mmMMEA1_ERR_STATUS_BASE_IDX 0
+#define mmMMEA1_MISC2 0x034d
+#define mmMMEA1_MISC2_BASE_IDX 0
+
+
+// addressBlock: mmhub_pctldec
+// base address: 0x68e00
+#define mmPCTL_MISC 0x0380
+#define mmPCTL_MISC_BASE_IDX 0
+#define mmPCTL_MMHUB_DEEPSLEEP 0x0381
+#define mmPCTL_MMHUB_DEEPSLEEP_BASE_IDX 0
+#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0382
+#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 0
+#define mmPCTL_PG_IGNORE_DEEPSLEEP 0x0383
+#define mmPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 0
+#define mmPCTL_PG_DAGB 0x0384
+#define mmPCTL_PG_DAGB_BASE_IDX 0
+#define mmPCTL0_RENG_RAM_INDEX 0x0385
+#define mmPCTL0_RENG_RAM_INDEX_BASE_IDX 0
+#define mmPCTL0_RENG_RAM_DATA 0x0386
+#define mmPCTL0_RENG_RAM_DATA_BASE_IDX 0
+#define mmPCTL0_RENG_EXECUTE 0x0387
+#define mmPCTL0_RENG_EXECUTE_BASE_IDX 0
+#define mmPCTL0_MISC 0x0388
+#define mmPCTL0_MISC_BASE_IDX 0
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0 0x0389
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1 0x038a
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2 0x038b
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0
+#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET 0x038c
+#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0
+#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x038d
+#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0
+#define mmPCTL1_RENG_RAM_INDEX 0x038e
+#define mmPCTL1_RENG_RAM_INDEX_BASE_IDX 0
+#define mmPCTL1_RENG_RAM_DATA 0x038f
+#define mmPCTL1_RENG_RAM_DATA_BASE_IDX 0
+#define mmPCTL1_RENG_EXECUTE 0x0390
+#define mmPCTL1_RENG_EXECUTE_BASE_IDX 0
+#define mmPCTL1_MISC 0x0391
+#define mmPCTL1_MISC_BASE_IDX 0
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0 0x0392
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1 0x0393
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2 0x0394
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0
+#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET 0x0395
+#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0
+#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0396
+#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0
+#define mmPCTL2_RENG_RAM_INDEX 0x0397
+#define mmPCTL2_RENG_RAM_INDEX_BASE_IDX 0
+#define mmPCTL2_RENG_RAM_DATA 0x0398
+#define mmPCTL2_RENG_RAM_DATA_BASE_IDX 0
+#define mmPCTL2_RENG_EXECUTE 0x0399
+#define mmPCTL2_RENG_EXECUTE_BASE_IDX 0
+#define mmPCTL2_MISC 0x039a
+#define mmPCTL2_MISC_BASE_IDX 0
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0 0x039b
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1 0x039c
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2 0x039d
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0
+#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET 0x039e
+#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0
+#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x039f
+#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0
+
+
+// addressBlock: mmhub_l1tlb_vml1dec
+// base address: 0x69600
+#define mmMC_VM_MX_L1_TLB0_STATUS 0x0588
+#define mmMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 0
+#define mmMC_VM_MX_L1_TLB1_STATUS 0x0589
+#define mmMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 0
+#define mmMC_VM_MX_L1_TLB2_STATUS 0x058a
+#define mmMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 0
+#define mmMC_VM_MX_L1_TLB3_STATUS 0x058b
+#define mmMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 0
+#define mmMC_VM_MX_L1_TLB4_STATUS 0x058c
+#define mmMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 0
+#define mmMC_VM_MX_L1_TLB5_STATUS 0x058d
+#define mmMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 0
+#define mmMC_VM_MX_L1_TLB6_STATUS 0x058e
+#define mmMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 0
+#define mmMC_VM_MX_L1_TLB7_STATUS 0x058f
+#define mmMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 0
+
+
+// addressBlock: mmhub_l1tlb_vml1pldec
+// base address: 0x69650
+#define mmMC_VM_MX_L1_PERFCOUNTER0_CFG 0x0594
+#define mmMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 0
+#define mmMC_VM_MX_L1_PERFCOUNTER1_CFG 0x0595
+#define mmMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 0
+#define mmMC_VM_MX_L1_PERFCOUNTER2_CFG 0x0596
+#define mmMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 0
+#define mmMC_VM_MX_L1_PERFCOUNTER3_CFG 0x0597
+#define mmMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 0
+#define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x0598
+#define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+
+
+// addressBlock: mmhub_l1tlb_vml1prdec
+// base address: 0x69670
+#define mmMC_VM_MX_L1_PERFCOUNTER_LO 0x059c
+#define mmMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 0
+#define mmMC_VM_MX_L1_PERFCOUNTER_HI 0x059d
+#define mmMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_atcl2dec
+// base address: 0x69900
+#define mmATC_L2_CNTL 0x0640
+#define mmATC_L2_CNTL_BASE_IDX 0
+#define mmATC_L2_CNTL2 0x0641
+#define mmATC_L2_CNTL2_BASE_IDX 0
+#define mmATC_L2_CACHE_DATA0 0x0644
+#define mmATC_L2_CACHE_DATA0_BASE_IDX 0
+#define mmATC_L2_CACHE_DATA1 0x0645
+#define mmATC_L2_CACHE_DATA1_BASE_IDX 0
+#define mmATC_L2_CACHE_DATA2 0x0646
+#define mmATC_L2_CACHE_DATA2_BASE_IDX 0
+#define mmATC_L2_CNTL3 0x0647
+#define mmATC_L2_CNTL3_BASE_IDX 0
+#define mmATC_L2_STATUS 0x0648
+#define mmATC_L2_STATUS_BASE_IDX 0
+#define mmATC_L2_STATUS2 0x0649
+#define mmATC_L2_STATUS2_BASE_IDX 0
+#define mmATC_L2_MISC_CG 0x064a
+#define mmATC_L2_MISC_CG_BASE_IDX 0
+#define mmATC_L2_MEM_POWER_LS 0x064b
+#define mmATC_L2_MEM_POWER_LS_BASE_IDX 0
+#define mmATC_L2_CGTT_CLK_CTRL 0x064c
+#define mmATC_L2_CGTT_CLK_CTRL_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_vml2pfdec
+// base address: 0x69a00
+#define mmVM_L2_CNTL 0x0680
+#define mmVM_L2_CNTL_BASE_IDX 0
+#define mmVM_L2_CNTL2 0x0681
+#define mmVM_L2_CNTL2_BASE_IDX 0
+#define mmVM_L2_CNTL3 0x0682
+#define mmVM_L2_CNTL3_BASE_IDX 0
+#define mmVM_L2_STATUS 0x0683
+#define mmVM_L2_STATUS_BASE_IDX 0
+#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x0684
+#define mmVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0
+#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0685
+#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0
+#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0686
+#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0
+#define mmVM_L2_PROTECTION_FAULT_CNTL 0x0687
+#define mmVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0
+#define mmVM_L2_PROTECTION_FAULT_CNTL2 0x0688
+#define mmVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0
+#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0689
+#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0
+#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4 0x068a
+#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0
+#define mmVM_L2_PROTECTION_FAULT_STATUS 0x068b
+#define mmVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0
+#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32 0x068c
+#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0
+#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32 0x068d
+#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0
+#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x068e
+#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0
+#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x068f
+#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0691
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0692
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0693
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0694
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0
+#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0695
+#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0
+#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0696
+#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0
+#define mmVM_L2_CNTL4 0x0697
+#define mmVM_L2_CNTL4_BASE_IDX 0
+#define mmVM_L2_MM_GROUP_RT_CLASSES 0x0698
+#define mmVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0
+#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x0699
+#define mmVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0
+#define mmVM_L2_BANK_SELECT_RESERVED_CID2 0x069a
+#define mmVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0
+#define mmVM_L2_CACHE_PARITY_CNTL 0x069b
+#define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0
+#define mmVM_L2_CGTT_CLK_CTRL 0x069e
+#define mmVM_L2_CGTT_CLK_CTRL_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_vml2vcdec
+// base address: 0x69b00
+#define mmVM_CONTEXT0_CNTL 0x06c0
+#define mmVM_CONTEXT0_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT1_CNTL 0x06c1
+#define mmVM_CONTEXT1_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT2_CNTL 0x06c2
+#define mmVM_CONTEXT2_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT3_CNTL 0x06c3
+#define mmVM_CONTEXT3_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT4_CNTL 0x06c4
+#define mmVM_CONTEXT4_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT5_CNTL 0x06c5
+#define mmVM_CONTEXT5_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT6_CNTL 0x06c6
+#define mmVM_CONTEXT6_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT7_CNTL 0x06c7
+#define mmVM_CONTEXT7_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT8_CNTL 0x06c8
+#define mmVM_CONTEXT8_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT9_CNTL 0x06c9
+#define mmVM_CONTEXT9_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT10_CNTL 0x06ca
+#define mmVM_CONTEXT10_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT11_CNTL 0x06cb
+#define mmVM_CONTEXT11_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT12_CNTL 0x06cc
+#define mmVM_CONTEXT12_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT13_CNTL 0x06cd
+#define mmVM_CONTEXT13_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT14_CNTL 0x06ce
+#define mmVM_CONTEXT14_CNTL_BASE_IDX 0
+#define mmVM_CONTEXT15_CNTL 0x06cf
+#define mmVM_CONTEXT15_CNTL_BASE_IDX 0
+#define mmVM_CONTEXTS_DISABLE 0x06d0
+#define mmVM_CONTEXTS_DISABLE_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG0_SEM 0x06d1
+#define mmVM_INVALIDATE_ENG0_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG1_SEM 0x06d2
+#define mmVM_INVALIDATE_ENG1_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG2_SEM 0x06d3
+#define mmVM_INVALIDATE_ENG2_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG3_SEM 0x06d4
+#define mmVM_INVALIDATE_ENG3_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG4_SEM 0x06d5
+#define mmVM_INVALIDATE_ENG4_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG5_SEM 0x06d6
+#define mmVM_INVALIDATE_ENG5_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG6_SEM 0x06d7
+#define mmVM_INVALIDATE_ENG6_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG7_SEM 0x06d8
+#define mmVM_INVALIDATE_ENG7_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG8_SEM 0x06d9
+#define mmVM_INVALIDATE_ENG8_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG9_SEM 0x06da
+#define mmVM_INVALIDATE_ENG9_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG10_SEM 0x06db
+#define mmVM_INVALIDATE_ENG10_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG11_SEM 0x06dc
+#define mmVM_INVALIDATE_ENG11_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG12_SEM 0x06dd
+#define mmVM_INVALIDATE_ENG12_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG13_SEM 0x06de
+#define mmVM_INVALIDATE_ENG13_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG14_SEM 0x06df
+#define mmVM_INVALIDATE_ENG14_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG15_SEM 0x06e0
+#define mmVM_INVALIDATE_ENG15_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG16_SEM 0x06e1
+#define mmVM_INVALIDATE_ENG16_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG17_SEM 0x06e2
+#define mmVM_INVALIDATE_ENG17_SEM_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG0_REQ 0x06e3
+#define mmVM_INVALIDATE_ENG0_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG1_REQ 0x06e4
+#define mmVM_INVALIDATE_ENG1_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG2_REQ 0x06e5
+#define mmVM_INVALIDATE_ENG2_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG3_REQ 0x06e6
+#define mmVM_INVALIDATE_ENG3_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG4_REQ 0x06e7
+#define mmVM_INVALIDATE_ENG4_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG5_REQ 0x06e8
+#define mmVM_INVALIDATE_ENG5_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG6_REQ 0x06e9
+#define mmVM_INVALIDATE_ENG6_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG7_REQ 0x06ea
+#define mmVM_INVALIDATE_ENG7_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG8_REQ 0x06eb
+#define mmVM_INVALIDATE_ENG8_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG9_REQ 0x06ec
+#define mmVM_INVALIDATE_ENG9_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG10_REQ 0x06ed
+#define mmVM_INVALIDATE_ENG10_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG11_REQ 0x06ee
+#define mmVM_INVALIDATE_ENG11_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG12_REQ 0x06ef
+#define mmVM_INVALIDATE_ENG12_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG13_REQ 0x06f0
+#define mmVM_INVALIDATE_ENG13_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG14_REQ 0x06f1
+#define mmVM_INVALIDATE_ENG14_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG15_REQ 0x06f2
+#define mmVM_INVALIDATE_ENG15_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG16_REQ 0x06f3
+#define mmVM_INVALIDATE_ENG16_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG17_REQ 0x06f4
+#define mmVM_INVALIDATE_ENG17_REQ_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG0_ACK 0x06f5
+#define mmVM_INVALIDATE_ENG0_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG1_ACK 0x06f6
+#define mmVM_INVALIDATE_ENG1_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG2_ACK 0x06f7
+#define mmVM_INVALIDATE_ENG2_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG3_ACK 0x06f8
+#define mmVM_INVALIDATE_ENG3_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG4_ACK 0x06f9
+#define mmVM_INVALIDATE_ENG4_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG5_ACK 0x06fa
+#define mmVM_INVALIDATE_ENG5_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG6_ACK 0x06fb
+#define mmVM_INVALIDATE_ENG6_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG7_ACK 0x06fc
+#define mmVM_INVALIDATE_ENG7_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG8_ACK 0x06fd
+#define mmVM_INVALIDATE_ENG8_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG9_ACK 0x06fe
+#define mmVM_INVALIDATE_ENG9_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG10_ACK 0x06ff
+#define mmVM_INVALIDATE_ENG10_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG11_ACK 0x0700
+#define mmVM_INVALIDATE_ENG11_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG12_ACK 0x0701
+#define mmVM_INVALIDATE_ENG12_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG13_ACK 0x0702
+#define mmVM_INVALIDATE_ENG13_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG14_ACK 0x0703
+#define mmVM_INVALIDATE_ENG14_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG15_ACK 0x0704
+#define mmVM_INVALIDATE_ENG15_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG16_ACK 0x0705
+#define mmVM_INVALIDATE_ENG16_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG17_ACK 0x0706
+#define mmVM_INVALIDATE_ENG17_ACK_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0707
+#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0708
+#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0709
+#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x070a
+#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x070b
+#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x070c
+#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x070d
+#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x070e
+#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x070f
+#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0710
+#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0711
+#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0712
+#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0713
+#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0714
+#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0715
+#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0716
+#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0717
+#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0718
+#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0719
+#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x071a
+#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x071b
+#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x071c
+#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x071d
+#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x071e
+#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x071f
+#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0720
+#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0721
+#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0722
+#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0723
+#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0724
+#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0725
+#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0726
+#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0727
+#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0728
+#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0729
+#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x072a
+#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x072b
+#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x072c
+#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x072d
+#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x072e
+#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x072f
+#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0730
+#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0731
+#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0732
+#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0733
+#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0734
+#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0735
+#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0736
+#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0737
+#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0738
+#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0739
+#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x073a
+#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x073b
+#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x073c
+#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x073d
+#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x073e
+#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x073f
+#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0740
+#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0741
+#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0742
+#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0743
+#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0744
+#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0745
+#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0746
+#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0747
+#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0748
+#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0749
+#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x074a
+#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x074b
+#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x074c
+#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x074d
+#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x074e
+#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x074f
+#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0750
+#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0751
+#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0752
+#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0753
+#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0754
+#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0755
+#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0756
+#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0757
+#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0758
+#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0759
+#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x075a
+#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x075b
+#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x075c
+#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x075d
+#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x075e
+#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x075f
+#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0760
+#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0761
+#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0762
+#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0763
+#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0764
+#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0765
+#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0766
+#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0767
+#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0768
+#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0769
+#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x076a
+#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x076b
+#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x076c
+#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x076d
+#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x076e
+#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x076f
+#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0770
+#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0771
+#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0772
+#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0773
+#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0774
+#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0775
+#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0776
+#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0777
+#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0778
+#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0779
+#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x077a
+#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x077b
+#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x077c
+#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x077d
+#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x077e
+#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x077f
+#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0780
+#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0781
+#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0782
+#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0783
+#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0784
+#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0785
+#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0786
+#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0787
+#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0788
+#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0789
+#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x078a
+#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_vml2pldec
+// base address: 0x69e90
+#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x07a4
+#define mmMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 0
+#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x07a5
+#define mmMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 0
+#define mmMC_VM_L2_PERFCOUNTER2_CFG 0x07a6
+#define mmMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 0
+#define mmMC_VM_L2_PERFCOUNTER3_CFG 0x07a7
+#define mmMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 0
+#define mmMC_VM_L2_PERFCOUNTER4_CFG 0x07a8
+#define mmMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 0
+#define mmMC_VM_L2_PERFCOUNTER5_CFG 0x07a9
+#define mmMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0
+#define mmMC_VM_L2_PERFCOUNTER6_CFG 0x07aa
+#define mmMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 0
+#define mmMC_VM_L2_PERFCOUNTER7_CFG 0x07ab
+#define mmMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 0
+#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x07ac
+#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_vml2prdec
+// base address: 0x69ee0
+#define mmMC_VM_L2_PERFCOUNTER_LO 0x07b8
+#define mmMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 0
+#define mmMC_VM_L2_PERFCOUNTER_HI 0x07b9
+#define mmMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_vmsharedhvdec
+// base address: 0x69f30
+#define mmMC_VM_FB_SIZE_OFFSET_VF0 0x07cc
+#define mmMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 0
+#define mmMC_VM_FB_SIZE_OFFSET_VF1 0x07cd
+#define mmMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 0
+#define mmMC_VM_FB_SIZE_OFFSET_VF2 0x07ce
+#define mmMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 0
+#define mmMC_VM_FB_SIZE_OFFSET_VF3 0x07cf
+#define mmMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 0
+#define mmMC_VM_FB_SIZE_OFFSET_VF4 0x07d0
+#define mmMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 0
+#define mmMC_VM_FB_SIZE_OFFSET_VF5 0x07d1
+#define mmMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 0
+#define mmMC_VM_FB_SIZE_OFFSET_VF6 0x07d2
+#define mmMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 0
+#define mmMC_VM_FB_SIZE_OFFSET_VF7 0x07d3
+#define mmMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 0
+#define mmMC_VM_FB_SIZE_OFFSET_VF8 0x07d4
+#define mmMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 0
+#define mmMC_VM_FB_SIZE_OFFSET_VF9 0x07d5
+#define mmMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 0
+#define mmMC_VM_FB_SIZE_OFFSET_VF10 0x07d6
+#define mmMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 0
+#define mmMC_VM_FB_SIZE_OFFSET_VF11 0x07d7
+#define mmMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 0
+#define mmMC_VM_FB_SIZE_OFFSET_VF12 0x07d8
+#define mmMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 0
+#define mmMC_VM_FB_SIZE_OFFSET_VF13 0x07d9
+#define mmMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 0
+#define mmMC_VM_FB_SIZE_OFFSET_VF14 0x07da
+#define mmMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 0
+#define mmMC_VM_FB_SIZE_OFFSET_VF15 0x07db
+#define mmMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 0
+#define mmVM_IOMMU_MMIO_CNTRL_1 0x07dc
+#define mmVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 0
+#define mmMC_VM_MARC_BASE_LO_0 0x07dd
+#define mmMC_VM_MARC_BASE_LO_0_BASE_IDX 0
+#define mmMC_VM_MARC_BASE_LO_1 0x07de
+#define mmMC_VM_MARC_BASE_LO_1_BASE_IDX 0
+#define mmMC_VM_MARC_BASE_LO_2 0x07df
+#define mmMC_VM_MARC_BASE_LO_2_BASE_IDX 0
+#define mmMC_VM_MARC_BASE_LO_3 0x07e0
+#define mmMC_VM_MARC_BASE_LO_3_BASE_IDX 0
+#define mmMC_VM_MARC_BASE_HI_0 0x07e1
+#define mmMC_VM_MARC_BASE_HI_0_BASE_IDX 0
+#define mmMC_VM_MARC_BASE_HI_1 0x07e2
+#define mmMC_VM_MARC_BASE_HI_1_BASE_IDX 0
+#define mmMC_VM_MARC_BASE_HI_2 0x07e3
+#define mmMC_VM_MARC_BASE_HI_2_BASE_IDX 0
+#define mmMC_VM_MARC_BASE_HI_3 0x07e4
+#define mmMC_VM_MARC_BASE_HI_3_BASE_IDX 0
+#define mmMC_VM_MARC_RELOC_LO_0 0x07e5
+#define mmMC_VM_MARC_RELOC_LO_0_BASE_IDX 0
+#define mmMC_VM_MARC_RELOC_LO_1 0x07e6
+#define mmMC_VM_MARC_RELOC_LO_1_BASE_IDX 0
+#define mmMC_VM_MARC_RELOC_LO_2 0x07e7
+#define mmMC_VM_MARC_RELOC_LO_2_BASE_IDX 0
+#define mmMC_VM_MARC_RELOC_LO_3 0x07e8
+#define mmMC_VM_MARC_RELOC_LO_3_BASE_IDX 0
+#define mmMC_VM_MARC_RELOC_HI_0 0x07e9
+#define mmMC_VM_MARC_RELOC_HI_0_BASE_IDX 0
+#define mmMC_VM_MARC_RELOC_HI_1 0x07ea
+#define mmMC_VM_MARC_RELOC_HI_1_BASE_IDX 0
+#define mmMC_VM_MARC_RELOC_HI_2 0x07eb
+#define mmMC_VM_MARC_RELOC_HI_2_BASE_IDX 0
+#define mmMC_VM_MARC_RELOC_HI_3 0x07ec
+#define mmMC_VM_MARC_RELOC_HI_3_BASE_IDX 0
+#define mmMC_VM_MARC_LEN_LO_0 0x07ed
+#define mmMC_VM_MARC_LEN_LO_0_BASE_IDX 0
+#define mmMC_VM_MARC_LEN_LO_1 0x07ee
+#define mmMC_VM_MARC_LEN_LO_1_BASE_IDX 0
+#define mmMC_VM_MARC_LEN_LO_2 0x07ef
+#define mmMC_VM_MARC_LEN_LO_2_BASE_IDX 0
+#define mmMC_VM_MARC_LEN_LO_3 0x07f0
+#define mmMC_VM_MARC_LEN_LO_3_BASE_IDX 0
+#define mmMC_VM_MARC_LEN_HI_0 0x07f1
+#define mmMC_VM_MARC_LEN_HI_0_BASE_IDX 0
+#define mmMC_VM_MARC_LEN_HI_1 0x07f2
+#define mmMC_VM_MARC_LEN_HI_1_BASE_IDX 0
+#define mmMC_VM_MARC_LEN_HI_2 0x07f3
+#define mmMC_VM_MARC_LEN_HI_2_BASE_IDX 0
+#define mmMC_VM_MARC_LEN_HI_3 0x07f4
+#define mmMC_VM_MARC_LEN_HI_3_BASE_IDX 0
+#define mmVM_IOMMU_CONTROL_REGISTER 0x07f5
+#define mmVM_IOMMU_CONTROL_REGISTER_BASE_IDX 0
+#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x07f6
+#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 0
+#define mmVM_PCIE_ATS_CNTL 0x07f7
+#define mmVM_PCIE_ATS_CNTL_BASE_IDX 0
+#define mmVM_PCIE_ATS_CNTL_VF_0 0x07f8
+#define mmVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 0
+#define mmVM_PCIE_ATS_CNTL_VF_1 0x07f9
+#define mmVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 0
+#define mmVM_PCIE_ATS_CNTL_VF_2 0x07fa
+#define mmVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 0
+#define mmVM_PCIE_ATS_CNTL_VF_3 0x07fb
+#define mmVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 0
+#define mmVM_PCIE_ATS_CNTL_VF_4 0x07fc
+#define mmVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 0
+#define mmVM_PCIE_ATS_CNTL_VF_5 0x07fd
+#define mmVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 0
+#define mmVM_PCIE_ATS_CNTL_VF_6 0x07fe
+#define mmVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 0
+#define mmVM_PCIE_ATS_CNTL_VF_7 0x07ff
+#define mmVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 0
+#define mmVM_PCIE_ATS_CNTL_VF_8 0x0800
+#define mmVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 0
+#define mmVM_PCIE_ATS_CNTL_VF_9 0x0801
+#define mmVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 0
+#define mmVM_PCIE_ATS_CNTL_VF_10 0x0802
+#define mmVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 0
+#define mmVM_PCIE_ATS_CNTL_VF_11 0x0803
+#define mmVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 0
+#define mmVM_PCIE_ATS_CNTL_VF_12 0x0804
+#define mmVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 0
+#define mmVM_PCIE_ATS_CNTL_VF_13 0x0805
+#define mmVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 0
+#define mmVM_PCIE_ATS_CNTL_VF_14 0x0806
+#define mmVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 0
+#define mmVM_PCIE_ATS_CNTL_VF_15 0x0807
+#define mmVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 0
+#define mmUTCL2_CGTT_CLK_CTRL 0x0808
+#define mmUTCL2_CGTT_CLK_CTRL_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_vmsharedpfdec
+// base address: 0x6a040
+#define mmMC_VM_NB_MMIOBASE 0x0810
+#define mmMC_VM_NB_MMIOBASE_BASE_IDX 0
+#define mmMC_VM_NB_MMIOLIMIT 0x0811
+#define mmMC_VM_NB_MMIOLIMIT_BASE_IDX 0
+#define mmMC_VM_NB_PCI_CTRL 0x0812
+#define mmMC_VM_NB_PCI_CTRL_BASE_IDX 0
+#define mmMC_VM_NB_PCI_ARB 0x0813
+#define mmMC_VM_NB_PCI_ARB_BASE_IDX 0
+#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0814
+#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0
+#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0815
+#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0
+#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0x0816
+#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0
+#define mmMC_VM_FB_OFFSET 0x0817
+#define mmMC_VM_FB_OFFSET_BASE_IDX 0
+#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0818
+#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0
+#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0819
+#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0
+#define mmMC_VM_STEERING 0x081a
+#define mmMC_VM_STEERING_BASE_IDX 0
+#define mmMC_SHARED_VIRT_RESET_REQ 0x081b
+#define mmMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0
+#define mmMC_MEM_POWER_LS 0x081c
+#define mmMC_MEM_POWER_LS_BASE_IDX 0
+#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x081d
+#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0
+#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x081e
+#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0
+#define mmMC_VM_APT_CNTL 0x081f
+#define mmMC_VM_APT_CNTL_BASE_IDX 0
+#define mmMC_VM_LOCAL_HBM_ADDRESS_START 0x0820
+#define mmMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0
+#define mmMC_VM_LOCAL_HBM_ADDRESS_END 0x0821
+#define mmMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0
+#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0822
+#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_vmsharedvcdec
+// base address: 0x6a0b0
+#define mmMC_VM_FB_LOCATION_BASE 0x082c
+#define mmMC_VM_FB_LOCATION_BASE_BASE_IDX 0
+#define mmMC_VM_FB_LOCATION_TOP 0x082d
+#define mmMC_VM_FB_LOCATION_TOP_BASE_IDX 0
+#define mmMC_VM_AGP_TOP 0x082e
+#define mmMC_VM_AGP_TOP_BASE_IDX 0
+#define mmMC_VM_AGP_BOT 0x082f
+#define mmMC_VM_AGP_BOT_BASE_IDX 0
+#define mmMC_VM_AGP_BASE 0x0830
+#define mmMC_VM_AGP_BASE_BASE_IDX 0
+#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0831
+#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0
+#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0832
+#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0
+#define mmMC_VM_MX_L1_TLB_CNTL 0x0833
+#define mmMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_atcl2pfcntrdec
+// base address: 0x6a100
+#define mmATC_L2_PERFCOUNTER_LO 0x0840
+#define mmATC_L2_PERFCOUNTER_LO_BASE_IDX 0
+#define mmATC_L2_PERFCOUNTER_HI 0x0841
+#define mmATC_L2_PERFCOUNTER_HI_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_atcl2pfcntldec
+// base address: 0x6a120
+#define mmATC_L2_PERFCOUNTER0_CFG 0x0848
+#define mmATC_L2_PERFCOUNTER0_CFG_BASE_IDX 0
+#define mmATC_L2_PERFCOUNTER1_CFG 0x0849
+#define mmATC_L2_PERFCOUNTER1_CFG_BASE_IDX 0
+#define mmATC_L2_PERFCOUNTER_RSLT_CNTL 0x084a
+#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h
new file mode 100644
index 000000000000..34278ef2aa1b
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h
@@ -0,0 +1,10127 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _mmhub_1_0_SH_MASK_HEADER
+#define _mmhub_1_0_SH_MASK_HEADER
+
+
+// addressBlock: mmhub_dagbdec
+//DAGB0_RDCLI0
+#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI1
+#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI2
+#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI3
+#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI4
+#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI5
+#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI6
+#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI7
+#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI8
+#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI9
+#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI10
+#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI11
+#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI12
+#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI13
+#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI14
+#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI15
+#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RD_CNTL
+#define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0
+#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
+#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
+#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
+#define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11
+#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
+#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17
+#define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL
+#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
+#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
+#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
+#define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L
+#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
+#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L
+//DAGB0_RD_GMI_CNTL
+#define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0
+#define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6
+#define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9
+#define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
+#define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
+#define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L
+#define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
+#define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
+//DAGB0_RD_ADDR_DAGB
+#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
+//DAGB0_RD_OUTPUT_DAGB_MAX_BURST
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
+//DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
+//DAGB0_RD_CGTT_CLK_CTRL
+#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB0_L1TLB_RD_CGTT_CLK_CTRL
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB0_ATCVM_RD_CGTT_CLK_CTRL
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB0_RD_ADDR_DAGB_MAX_BURST0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB0_RD_ADDR_DAGB_MAX_BURST1
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB0_RD_VC0_CNTL
+#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC1_CNTL
+#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC2_CNTL
+#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC3_CNTL
+#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC4_CNTL
+#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC5_CNTL
+#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC6_CNTL
+#define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC7_CNTL
+#define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_CNTL_MISC
+#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
+#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
+#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
+#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
+#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
+#define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15
+#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
+#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
+#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
+#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
+#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
+#define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
+//DAGB0_RD_TLB_CREDIT
+#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0
+#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5
+#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa
+#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf
+#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14
+#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19
+#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL
+#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L
+#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L
+#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L
+#define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L
+#define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L
+//DAGB0_RDCLI_ASK_PENDING
+#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_GO_PENDING
+#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_GBLSEND_PENDING
+#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_TLB_PENDING
+#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_OARB_PENDING
+#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_OSD_PENDING
+#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI0
+#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI1
+#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI2
+#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI3
+#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI4
+#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI5
+#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI6
+#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI7
+#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI8
+#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI9
+#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI10
+#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI11
+#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI12
+#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI13
+#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI14
+#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI15
+#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WR_CNTL
+#define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0
+#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
+#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
+#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
+#define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11
+#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
+#define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17
+#define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL
+#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
+#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
+#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
+#define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L
+#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
+#define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L
+//DAGB0_WR_GMI_CNTL
+#define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0
+#define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6
+#define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9
+#define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
+#define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
+#define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L
+#define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
+#define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
+//DAGB0_WR_ADDR_DAGB
+#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
+//DAGB0_WR_OUTPUT_DAGB_MAX_BURST
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
+//DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
+//DAGB0_WR_CGTT_CLK_CTRL
+#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB0_L1TLB_WR_CGTT_CLK_CTRL
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB0_ATCVM_WR_CGTT_CLK_CTRL
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB0_WR_ADDR_DAGB_MAX_BURST0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB0_WR_ADDR_DAGB_MAX_BURST1
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB
+#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L
+//DAGB0_WR_DATA_DAGB_MAX_BURST0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB_LAZY_TIMER0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB_MAX_BURST1
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB_LAZY_TIMER1
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB0_WR_VC0_CNTL
+#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC1_CNTL
+#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC2_CNTL
+#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC3_CNTL
+#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC4_CNTL
+#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC5_CNTL
+#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC6_CNTL
+#define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC7_CNTL
+#define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_CNTL_MISC
+#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
+#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
+#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
+#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
+#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
+#define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15
+#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
+#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
+#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
+#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
+#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
+#define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
+//DAGB0_WR_TLB_CREDIT
+#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0
+#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5
+#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa
+#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf
+#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14
+#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19
+#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL
+#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L
+#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L
+#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L
+#define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L
+#define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L
+//DAGB0_WR_DATA_CREDIT
+#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0
+#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8
+#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10
+#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18
+#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL
+#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L
+#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L
+#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L
+//DAGB0_WR_MISC_CREDIT
+#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0
+#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6
+#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9
+#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10
+#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL
+#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L
+#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L
+#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L
+//DAGB0_WRCLI_ASK_PENDING
+#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_GO_PENDING
+#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_GBLSEND_PENDING
+#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_TLB_PENDING
+#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_OARB_PENDING
+#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_OSD_PENDING
+#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_DBUS_ASK_PENDING
+#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_DBUS_GO_PENDING
+#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_DAGB_DLY
+#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0
+#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8
+#define DAGB0_DAGB_DLY__POS__SHIFT 0x10
+#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL
+#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L
+#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L
+//DAGB0_CNTL_MISC
+#define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0
+#define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3
+#define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6
+#define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9
+#define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc
+#define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf
+#define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12
+#define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15
+#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18
+#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e
+#define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L
+#define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L
+#define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L
+#define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L
+#define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L
+#define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L
+#define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L
+#define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L
+#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L
+#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L
+//DAGB0_CNTL_MISC2
+#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0
+#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1
+#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2
+#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3
+#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4
+#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5
+#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6
+#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7
+#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8
+#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9
+#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa
+#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L
+#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L
+#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L
+#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L
+#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L
+#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L
+#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L
+#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L
+#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L
+#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L
+#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L
+//DAGB0_FIFO_EMPTY
+#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0
+#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL
+//DAGB0_FIFO_FULL
+#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0
+#define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL
+//DAGB0_WR_CREDITS_FULL
+#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0
+#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL
+//DAGB0_RD_CREDITS_FULL
+#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0
+#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL
+//DAGB0_PERFCOUNTER_LO
+#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//DAGB0_PERFCOUNTER_HI
+#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//DAGB0_PERFCOUNTER0_CFG
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//DAGB0_PERFCOUNTER1_CFG
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//DAGB0_PERFCOUNTER2_CFG
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//DAGB0_PERFCOUNTER_RSLT_CNTL
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//DAGB0_RESERVE0
+#define DAGB0_RESERVE0__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE1
+#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE2
+#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE3
+#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE4
+#define DAGB0_RESERVE4__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE5
+#define DAGB0_RESERVE5__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE5__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE6
+#define DAGB0_RESERVE6__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE6__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE7
+#define DAGB0_RESERVE7__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE7__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE8
+#define DAGB0_RESERVE8__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE8__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE9
+#define DAGB0_RESERVE9__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE9__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE10
+#define DAGB0_RESERVE10__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE10__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE11
+#define DAGB0_RESERVE11__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE11__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE12
+#define DAGB0_RESERVE12__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE12__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE13
+#define DAGB0_RESERVE13__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE13__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE14
+#define DAGB0_RESERVE14__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE14__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE15
+#define DAGB0_RESERVE15__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE15__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE16
+#define DAGB0_RESERVE16__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE16__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE17
+#define DAGB0_RESERVE17__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE17__RESERVE_MASK 0xFFFFFFFFL
+//DAGB1_RDCLI0
+#define DAGB1_RDCLI0__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI0__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI0__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI0__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI0__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI0__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI0__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI0__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI0__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI0__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI0__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI0__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI1
+#define DAGB1_RDCLI1__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI1__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI1__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI1__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI1__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI1__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI1__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI1__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI1__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI1__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI1__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI1__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI2
+#define DAGB1_RDCLI2__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI2__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI2__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI2__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI2__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI2__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI2__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI2__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI2__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI2__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI2__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI2__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI3
+#define DAGB1_RDCLI3__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI3__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI3__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI3__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI3__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI3__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI3__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI3__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI3__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI3__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI3__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI3__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI4
+#define DAGB1_RDCLI4__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI4__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI4__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI4__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI4__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI4__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI4__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI4__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI4__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI4__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI4__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI4__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI5
+#define DAGB1_RDCLI5__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI5__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI5__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI5__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI5__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI5__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI5__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI5__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI5__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI5__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI5__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI5__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI6
+#define DAGB1_RDCLI6__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI6__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI6__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI6__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI6__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI6__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI6__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI6__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI6__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI6__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI6__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI6__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI7
+#define DAGB1_RDCLI7__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI7__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI7__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI7__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI7__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI7__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI7__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI7__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI7__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI7__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI7__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI7__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI8
+#define DAGB1_RDCLI8__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI8__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI8__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI8__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI8__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI8__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI8__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI8__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI8__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI8__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI8__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI8__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI9
+#define DAGB1_RDCLI9__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI9__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI9__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI9__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI9__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI9__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI9__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI9__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI9__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI9__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI9__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI9__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI10
+#define DAGB1_RDCLI10__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI10__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI10__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI10__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI10__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI10__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI10__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI10__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI10__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI10__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI10__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI10__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI11
+#define DAGB1_RDCLI11__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI11__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI11__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI11__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI11__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI11__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI11__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI11__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI11__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI11__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI11__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI11__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI12
+#define DAGB1_RDCLI12__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI12__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI12__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI12__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI12__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI12__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI12__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI12__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI12__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI12__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI12__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI12__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI13
+#define DAGB1_RDCLI13__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI13__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI13__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI13__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI13__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI13__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI13__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI13__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI13__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI13__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI13__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI13__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI14
+#define DAGB1_RDCLI14__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI14__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI14__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI14__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI14__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI14__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI14__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI14__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI14__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI14__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI14__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI14__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI15
+#define DAGB1_RDCLI15__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI15__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI15__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI15__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI15__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI15__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI15__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI15__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI15__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI15__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI15__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI15__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RD_CNTL
+#define DAGB1_RD_CNTL__SCLK_FREQ__SHIFT 0x0
+#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
+#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
+#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
+#define DAGB1_RD_CNTL__IO_LEVEL__SHIFT 0x11
+#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
+#define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17
+#define DAGB1_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL
+#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
+#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
+#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
+#define DAGB1_RD_CNTL__IO_LEVEL_MASK 0x000E0000L
+#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
+#define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L
+//DAGB1_RD_GMI_CNTL
+#define DAGB1_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0
+#define DAGB1_RD_GMI_CNTL__LEVEL__SHIFT 0x6
+#define DAGB1_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9
+#define DAGB1_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
+#define DAGB1_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
+#define DAGB1_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L
+#define DAGB1_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
+#define DAGB1_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
+//DAGB1_RD_ADDR_DAGB
+#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
+//DAGB1_RD_OUTPUT_DAGB_MAX_BURST
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
+//DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
+//DAGB1_RD_CGTT_CLK_CTRL
+#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB1_L1TLB_RD_CGTT_CLK_CTRL
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB1_ATCVM_RD_CGTT_CLK_CTRL
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB1_RD_ADDR_DAGB_MAX_BURST0
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB1_RD_ADDR_DAGB_LAZY_TIMER0
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB1_RD_ADDR_DAGB_MAX_BURST1
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB1_RD_ADDR_DAGB_LAZY_TIMER1
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB1_RD_VC0_CNTL
+#define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_RD_VC1_CNTL
+#define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_RD_VC2_CNTL
+#define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_RD_VC3_CNTL
+#define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_RD_VC4_CNTL
+#define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_RD_VC5_CNTL
+#define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_RD_VC6_CNTL
+#define DAGB1_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_RD_VC6_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_RD_VC6_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_RD_VC7_CNTL
+#define DAGB1_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_RD_VC7_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_RD_VC7_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_RD_CNTL_MISC
+#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
+#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
+#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
+#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
+#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
+#define DAGB1_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15
+#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
+#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
+#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
+#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
+#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
+#define DAGB1_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
+//DAGB1_RD_TLB_CREDIT
+#define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT 0x0
+#define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT 0x5
+#define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa
+#define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT 0xf
+#define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT 0x14
+#define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT 0x19
+#define DAGB1_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL
+#define DAGB1_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L
+#define DAGB1_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L
+#define DAGB1_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L
+#define DAGB1_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L
+#define DAGB1_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L
+//DAGB1_RDCLI_ASK_PENDING
+#define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_RDCLI_GO_PENDING
+#define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_RDCLI_GBLSEND_PENDING
+#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_RDCLI_TLB_PENDING
+#define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_RDCLI_OARB_PENDING
+#define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_RDCLI_OSD_PENDING
+#define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_WRCLI0
+#define DAGB1_WRCLI0__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI0__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI0__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI0__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI0__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI0__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI0__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI0__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI0__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI0__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI0__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI0__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI1
+#define DAGB1_WRCLI1__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI1__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI1__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI1__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI1__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI1__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI1__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI1__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI1__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI1__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI1__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI1__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI2
+#define DAGB1_WRCLI2__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI2__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI2__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI2__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI2__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI2__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI2__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI2__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI2__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI2__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI2__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI2__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI3
+#define DAGB1_WRCLI3__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI3__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI3__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI3__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI3__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI3__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI3__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI3__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI3__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI3__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI3__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI3__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI4
+#define DAGB1_WRCLI4__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI4__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI4__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI4__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI4__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI4__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI4__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI4__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI4__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI4__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI4__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI4__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI5
+#define DAGB1_WRCLI5__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI5__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI5__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI5__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI5__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI5__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI5__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI5__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI5__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI5__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI5__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI5__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI6
+#define DAGB1_WRCLI6__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI6__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI6__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI6__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI6__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI6__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI6__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI6__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI6__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI6__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI6__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI6__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI7
+#define DAGB1_WRCLI7__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI7__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI7__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI7__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI7__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI7__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI7__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI7__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI7__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI7__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI7__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI7__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI8
+#define DAGB1_WRCLI8__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI8__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI8__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI8__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI8__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI8__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI8__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI8__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI8__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI8__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI8__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI8__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI9
+#define DAGB1_WRCLI9__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI9__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI9__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI9__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI9__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI9__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI9__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI9__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI9__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI9__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI9__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI9__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI10
+#define DAGB1_WRCLI10__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI10__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI10__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI10__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI10__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI10__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI10__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI10__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI10__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI10__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI10__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI10__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI11
+#define DAGB1_WRCLI11__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI11__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI11__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI11__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI11__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI11__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI11__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI11__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI11__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI11__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI11__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI11__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI12
+#define DAGB1_WRCLI12__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI12__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI12__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI12__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI12__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI12__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI12__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI12__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI12__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI12__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI12__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI12__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI13
+#define DAGB1_WRCLI13__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI13__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI13__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI13__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI13__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI13__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI13__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI13__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI13__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI13__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI13__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI13__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI14
+#define DAGB1_WRCLI14__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI14__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI14__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI14__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI14__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI14__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI14__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI14__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI14__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI14__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI14__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI14__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI15
+#define DAGB1_WRCLI15__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI15__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI15__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI15__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI15__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI15__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI15__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI15__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI15__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI15__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI15__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI15__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WR_CNTL
+#define DAGB1_WR_CNTL__SCLK_FREQ__SHIFT 0x0
+#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
+#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
+#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
+#define DAGB1_WR_CNTL__IO_LEVEL__SHIFT 0x11
+#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
+#define DAGB1_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17
+#define DAGB1_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL
+#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
+#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
+#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
+#define DAGB1_WR_CNTL__IO_LEVEL_MASK 0x000E0000L
+#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
+#define DAGB1_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L
+//DAGB1_WR_GMI_CNTL
+#define DAGB1_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0
+#define DAGB1_WR_GMI_CNTL__LEVEL__SHIFT 0x6
+#define DAGB1_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9
+#define DAGB1_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
+#define DAGB1_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
+#define DAGB1_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L
+#define DAGB1_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
+#define DAGB1_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
+//DAGB1_WR_ADDR_DAGB
+#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB1_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB1_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
+//DAGB1_WR_OUTPUT_DAGB_MAX_BURST
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
+//DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
+//DAGB1_WR_CGTT_CLK_CTRL
+#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB1_L1TLB_WR_CGTT_CLK_CTRL
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB1_ATCVM_WR_CGTT_CLK_CTRL
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB1_WR_ADDR_DAGB_MAX_BURST0
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB1_WR_ADDR_DAGB_LAZY_TIMER0
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB1_WR_ADDR_DAGB_MAX_BURST1
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB1_WR_ADDR_DAGB_LAZY_TIMER1
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB1_WR_DATA_DAGB
+#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB1_WR_DATA_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB1_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L
+//DAGB1_WR_DATA_DAGB_MAX_BURST0
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB1_WR_DATA_DAGB_LAZY_TIMER0
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB1_WR_DATA_DAGB_MAX_BURST1
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB1_WR_DATA_DAGB_LAZY_TIMER1
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB1_WR_VC0_CNTL
+#define DAGB1_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_WR_VC0_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_WR_VC0_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_WR_VC1_CNTL
+#define DAGB1_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_WR_VC1_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_WR_VC1_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_WR_VC2_CNTL
+#define DAGB1_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_WR_VC2_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_WR_VC2_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_WR_VC3_CNTL
+#define DAGB1_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_WR_VC3_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_WR_VC3_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_WR_VC4_CNTL
+#define DAGB1_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_WR_VC4_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_WR_VC4_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_WR_VC5_CNTL
+#define DAGB1_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_WR_VC5_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_WR_VC5_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_WR_VC6_CNTL
+#define DAGB1_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_WR_VC6_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_WR_VC6_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_WR_VC7_CNTL
+#define DAGB1_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_WR_VC7_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_WR_VC7_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_WR_CNTL_MISC
+#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
+#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
+#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
+#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
+#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
+#define DAGB1_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15
+#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
+#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
+#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
+#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
+#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
+#define DAGB1_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
+//DAGB1_WR_TLB_CREDIT
+#define DAGB1_WR_TLB_CREDIT__TLB0__SHIFT 0x0
+#define DAGB1_WR_TLB_CREDIT__TLB1__SHIFT 0x5
+#define DAGB1_WR_TLB_CREDIT__TLB2__SHIFT 0xa
+#define DAGB1_WR_TLB_CREDIT__TLB3__SHIFT 0xf
+#define DAGB1_WR_TLB_CREDIT__TLB4__SHIFT 0x14
+#define DAGB1_WR_TLB_CREDIT__TLB5__SHIFT 0x19
+#define DAGB1_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL
+#define DAGB1_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L
+#define DAGB1_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L
+#define DAGB1_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L
+#define DAGB1_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L
+#define DAGB1_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L
+//DAGB1_WR_DATA_CREDIT
+#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0
+#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8
+#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10
+#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18
+#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL
+#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L
+#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L
+#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L
+//DAGB1_WR_MISC_CREDIT
+#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0
+#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6
+#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9
+#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10
+#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL
+#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L
+#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L
+#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L
+//DAGB1_WRCLI_ASK_PENDING
+#define DAGB1_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_WRCLI_GO_PENDING
+#define DAGB1_WRCLI_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_WRCLI_GBLSEND_PENDING
+#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_WRCLI_TLB_PENDING
+#define DAGB1_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_WRCLI_OARB_PENDING
+#define DAGB1_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_WRCLI_OSD_PENDING
+#define DAGB1_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_WRCLI_DBUS_ASK_PENDING
+#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_WRCLI_DBUS_GO_PENDING
+#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_DAGB_DLY
+#define DAGB1_DAGB_DLY__DLY__SHIFT 0x0
+#define DAGB1_DAGB_DLY__CLI__SHIFT 0x8
+#define DAGB1_DAGB_DLY__POS__SHIFT 0x10
+#define DAGB1_DAGB_DLY__DLY_MASK 0x000000FFL
+#define DAGB1_DAGB_DLY__CLI_MASK 0x0000FF00L
+#define DAGB1_DAGB_DLY__POS_MASK 0x000F0000L
+//DAGB1_CNTL_MISC
+#define DAGB1_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0
+#define DAGB1_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3
+#define DAGB1_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6
+#define DAGB1_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9
+#define DAGB1_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc
+#define DAGB1_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf
+#define DAGB1_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12
+#define DAGB1_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15
+#define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18
+#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e
+#define DAGB1_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L
+#define DAGB1_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L
+#define DAGB1_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L
+#define DAGB1_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L
+#define DAGB1_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L
+#define DAGB1_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L
+#define DAGB1_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L
+#define DAGB1_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L
+#define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L
+#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L
+//DAGB1_CNTL_MISC2
+#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0
+#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1
+#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2
+#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3
+#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4
+#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5
+#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6
+#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7
+#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8
+#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9
+#define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0xa
+#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L
+#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L
+#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L
+#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L
+#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L
+#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L
+#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L
+#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L
+#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L
+#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L
+#define DAGB1_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L
+//DAGB1_FIFO_EMPTY
+#define DAGB1_FIFO_EMPTY__EMPTY__SHIFT 0x0
+#define DAGB1_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL
+//DAGB1_FIFO_FULL
+#define DAGB1_FIFO_FULL__FULL__SHIFT 0x0
+#define DAGB1_FIFO_FULL__FULL_MASK 0x007FFFFFL
+//DAGB1_WR_CREDITS_FULL
+#define DAGB1_WR_CREDITS_FULL__FULL__SHIFT 0x0
+#define DAGB1_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL
+//DAGB1_RD_CREDITS_FULL
+#define DAGB1_RD_CREDITS_FULL__FULL__SHIFT 0x0
+#define DAGB1_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL
+//DAGB1_PERFCOUNTER_LO
+#define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//DAGB1_PERFCOUNTER_HI
+#define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//DAGB1_PERFCOUNTER0_CFG
+#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//DAGB1_PERFCOUNTER1_CFG
+#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//DAGB1_PERFCOUNTER2_CFG
+#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//DAGB1_PERFCOUNTER_RSLT_CNTL
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//DAGB1_RESERVE0
+#define DAGB1_RESERVE0__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE0__RESERVE_MASK 0xFFFFFFFFL
+//DAGB1_RESERVE1
+#define DAGB1_RESERVE1__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE1__RESERVE_MASK 0xFFFFFFFFL
+//DAGB1_RESERVE2
+#define DAGB1_RESERVE2__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE2__RESERVE_MASK 0xFFFFFFFFL
+//DAGB1_RESERVE3
+#define DAGB1_RESERVE3__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE3__RESERVE_MASK 0xFFFFFFFFL
+//DAGB1_RESERVE4
+#define DAGB1_RESERVE4__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE4__RESERVE_MASK 0xFFFFFFFFL
+//DAGB1_RESERVE5
+#define DAGB1_RESERVE5__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE5__RESERVE_MASK 0xFFFFFFFFL
+//DAGB1_RESERVE6
+#define DAGB1_RESERVE6__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE6__RESERVE_MASK 0xFFFFFFFFL
+//DAGB1_RESERVE7
+#define DAGB1_RESERVE7__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE7__RESERVE_MASK 0xFFFFFFFFL
+//DAGB1_RESERVE8
+#define DAGB1_RESERVE8__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE8__RESERVE_MASK 0xFFFFFFFFL
+//DAGB1_RESERVE9
+#define DAGB1_RESERVE9__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE9__RESERVE_MASK 0xFFFFFFFFL
+//DAGB1_RESERVE10
+#define DAGB1_RESERVE10__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE10__RESERVE_MASK 0xFFFFFFFFL
+//DAGB1_RESERVE11
+#define DAGB1_RESERVE11__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE11__RESERVE_MASK 0xFFFFFFFFL
+//DAGB1_RESERVE12
+#define DAGB1_RESERVE12__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE12__RESERVE_MASK 0xFFFFFFFFL
+//DAGB1_RESERVE13
+#define DAGB1_RESERVE13__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE13__RESERVE_MASK 0xFFFFFFFFL
+//DAGB1_RESERVE14
+#define DAGB1_RESERVE14__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE14__RESERVE_MASK 0xFFFFFFFFL
+//DAGB1_RESERVE15
+#define DAGB1_RESERVE15__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE15__RESERVE_MASK 0xFFFFFFFFL
+//DAGB1_RESERVE16
+#define DAGB1_RESERVE16__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE16__RESERVE_MASK 0xFFFFFFFFL
+//DAGB1_RESERVE17
+#define DAGB1_RESERVE17__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE17__RESERVE_MASK 0xFFFFFFFFL
+
+
+// addressBlock: mmhub_ea_mmeadec
+//MMEA0_DRAM_RD_CLI2GRP_MAP0
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA0_DRAM_RD_CLI2GRP_MAP1
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA0_DRAM_WR_CLI2GRP_MAP0
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA0_DRAM_WR_CLI2GRP_MAP1
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA0_DRAM_RD_GRP2VC_MAP
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA0_DRAM_WR_GRP2VC_MAP
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA0_DRAM_RD_LAZY
+#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+//MMEA0_DRAM_WR_LAZY
+#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+//MMEA0_DRAM_RD_CAM_CNTL
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+//MMEA0_DRAM_WR_CAM_CNTL
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+//MMEA0_DRAM_PAGE_BURST
+#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA0_DRAM_RD_PRI_AGE
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA0_DRAM_WR_PRI_AGE
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA0_DRAM_RD_PRI_QUEUING
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_DRAM_WR_PRI_QUEUING
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_DRAM_RD_PRI_FIXED
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_DRAM_WR_PRI_FIXED
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_DRAM_RD_PRI_URGENCY
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA0_DRAM_WR_PRI_URGENCY
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA0_DRAM_RD_PRI_QUANT_PRI1
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_DRAM_RD_PRI_QUANT_PRI2
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_DRAM_RD_PRI_QUANT_PRI3
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_DRAM_WR_PRI_QUANT_PRI1
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_DRAM_WR_PRI_QUANT_PRI2
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_DRAM_WR_PRI_QUANT_PRI3
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_ADDRNORM_BASE_ADDR0
+#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8
+#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc
+#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L
+#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA0_ADDRNORM_LIMIT_ADDR0
+#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa
+#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
+#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL
+#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L
+#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA0_ADDRNORM_BASE_ADDR1
+#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8
+#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc
+#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L
+#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA0_ADDRNORM_LIMIT_ADDR1
+#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa
+#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
+#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL
+#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L
+#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA0_ADDRNORM_OFFSET_ADDR1
+#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0
+#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14
+#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L
+#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L
+//MMEA0_ADDRNORM_HOLE_CNTL
+#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
+#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
+#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
+#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
+//MMEA0_ADDRDEC_BANK_CFG
+#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0
+#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11
+#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL
+#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L
+//MMEA0_ADDRDEC_MISC_CFG
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4
+#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8
+#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9
+#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc
+#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10
+#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14
+#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16
+#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18
+#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L
+#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L
+#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L
+#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L
+#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L
+#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L
+#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L
+#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L
+#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_PC
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_PC2
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL
+//MMEA0_ADDRDECDRAM_ADDR_HASH_CS0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDECDRAM_ADDR_HASH_CS1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDECDRAM_HARVEST_ENABLE
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
+//MMEA0_ADDRDEC0_BASE_ADDR_CS0
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_CS1
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_CS2
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_CS3
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_SECCS0
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_SECCS1
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_SECCS2
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_SECCS3
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_MASK_CS01
+#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_MASK_CS23
+#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_MASK_SECCS01
+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_MASK_SECCS23
+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_CFG_CS01
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+//MMEA0_ADDRDEC0_ADDR_CFG_CS23
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+//MMEA0_ADDRDEC0_ADDR_SEL_CS01
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA0_ADDRDEC0_ADDR_SEL_CS23
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA0_ADDRDEC0_COL_SEL_LO_CS01
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA0_ADDRDEC0_COL_SEL_LO_CS23
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA0_ADDRDEC0_COL_SEL_HI_CS01
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA0_ADDRDEC0_COL_SEL_HI_CS23
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA0_ADDRDEC0_RM_SEL_CS01
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC0_RM_SEL_CS23
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC0_RM_SEL_SECCS01
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC0_RM_SEL_SECCS23
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC1_BASE_ADDR_CS0
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_CS1
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_CS2
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_CS3
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_SECCS0
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_SECCS1
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_SECCS2
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_SECCS3
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_MASK_CS01
+#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_MASK_CS23
+#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_MASK_SECCS01
+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_MASK_SECCS23
+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_CFG_CS01
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+//MMEA0_ADDRDEC1_ADDR_CFG_CS23
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+//MMEA0_ADDRDEC1_ADDR_SEL_CS01
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA0_ADDRDEC1_ADDR_SEL_CS23
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA0_ADDRDEC1_COL_SEL_LO_CS01
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA0_ADDRDEC1_COL_SEL_LO_CS23
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA0_ADDRDEC1_COL_SEL_HI_CS01
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA0_ADDRDEC1_COL_SEL_HI_CS23
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA0_ADDRDEC1_RM_SEL_CS01
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC1_RM_SEL_CS23
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC1_RM_SEL_SECCS01
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC1_RM_SEL_SECCS23
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_IO_RD_CLI2GRP_MAP0
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA0_IO_RD_CLI2GRP_MAP1
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA0_IO_WR_CLI2GRP_MAP0
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA0_IO_WR_CLI2GRP_MAP1
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA0_IO_RD_COMBINE_FLUSH
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+//MMEA0_IO_WR_COMBINE_FLUSH
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+//MMEA0_IO_GROUP_BURST
+#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA0_IO_RD_PRI_AGE
+#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA0_IO_WR_PRI_AGE
+#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA0_IO_RD_PRI_QUEUING
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_IO_WR_PRI_QUEUING
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_IO_RD_PRI_FIXED
+#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_IO_WR_PRI_FIXED
+#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_IO_RD_PRI_URGENCY
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA0_IO_WR_PRI_URGENCY
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA0_IO_RD_PRI_URGENCY_MASK
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L
+//MMEA0_IO_WR_PRI_URGENCY_MASK
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L
+//MMEA0_IO_RD_PRI_QUANT_PRI1
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_IO_RD_PRI_QUANT_PRI2
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_IO_RD_PRI_QUANT_PRI3
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_IO_WR_PRI_QUANT_PRI1
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_IO_WR_PRI_QUANT_PRI2
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_IO_WR_PRI_QUANT_PRI3
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_SDP_ARB_DRAM
+#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0
+#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13
+#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14
+#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL
+#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L
+#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L
+//MMEA0_SDP_ARB_FINAL
+#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0
+#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5
+#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
+#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18
+#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19
+#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a
+#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL
+#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L
+#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L
+#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L
+#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L
+#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L
+//MMEA0_SDP_DRAM_PRIORITY
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA0_SDP_IO_PRIORITY
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA0_SDP_CREDITS
+#define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0
+#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8
+#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10
+#define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL
+#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L
+#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L
+//MMEA0_SDP_TAG_RESERVE0
+#define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0
+#define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8
+#define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10
+#define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18
+#define MMEA0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL
+#define MMEA0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L
+#define MMEA0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L
+#define MMEA0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L
+//MMEA0_SDP_TAG_RESERVE1
+#define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0
+#define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8
+#define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10
+#define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18
+#define MMEA0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL
+#define MMEA0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L
+#define MMEA0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L
+#define MMEA0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L
+//MMEA0_SDP_VCC_RESERVE0
+#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//MMEA0_SDP_VCC_RESERVE1
+#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//MMEA0_SDP_VCD_RESERVE0
+#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//MMEA0_SDP_VCD_RESERVE1
+#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//MMEA0_SDP_REQ_CNTL
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2
+#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3
+#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L
+#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L
+#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L
+//MMEA0_MISC
+#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0
+#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1
+#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2
+#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3
+#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4
+#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5
+#define MMEA0_MISC__RRET_SWAP_MODE__SHIFT 0x6
+#define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x7
+#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x8
+#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xa
+#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xc
+#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xe
+#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x13
+#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x14
+#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x15
+#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x16
+#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x17
+#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x18
+#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L
+#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L
+#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L
+#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L
+#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L
+#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L
+#define MMEA0_MISC__RRET_SWAP_MODE_MASK 0x00000040L
+#define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000080L
+#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000300L
+#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00000C00L
+#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00003000L
+#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x0007C000L
+#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x00080000L
+#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x00100000L
+#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x00200000L
+#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x00400000L
+#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x00800000L
+#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x01000000L
+//MMEA0_LATENCY_SAMPLING
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L
+//MMEA0_PERFCOUNTER_LO
+#define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MMEA0_PERFCOUNTER_HI
+#define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//MMEA0_PERFCOUNTER0_CFG
+#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MMEA0_PERFCOUNTER1_CFG
+#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MMEA0_PERFCOUNTER_RSLT_CNTL
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//MMEA0_EDC_CNT
+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
+#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
+#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
+#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
+#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14
+#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16
+#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18
+#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a
+#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c
+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
+#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
+#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
+#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
+#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L
+#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L
+#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L
+#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L
+#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L
+//MMEA0_EDC_CNT2
+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
+#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
+#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
+//MMEA0_DSM_CNTL
+#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15
+#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17
+#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L
+#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
+//MMEA0_DSM_CNTLA
+#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+//MMEA0_DSM_CNTLB
+//MMEA0_DSM_CNTL2
+#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17
+#define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
+#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L
+#define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
+//MMEA0_DSM_CNTL2A
+#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+//MMEA0_DSM_CNTL2B
+//MMEA0_CGTT_CLK_CTRL
+#define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f
+#define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L
+//MMEA0_EDC_MODE
+#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
+#define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11
+#define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14
+#define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d
+#define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f
+#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
+#define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L
+#define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L
+#define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L
+#define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L
+//MMEA0_ERR_STATUS
+#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
+#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0x8
+#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0x9
+#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xa
+#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
+#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000100L
+#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000200L
+#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00000400L
+//MMEA0_MISC2
+#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0
+#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1
+#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2
+#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7
+#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L
+#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L
+#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL
+#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L
+//MMEA1_DRAM_RD_CLI2GRP_MAP0
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA1_DRAM_RD_CLI2GRP_MAP1
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA1_DRAM_WR_CLI2GRP_MAP0
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA1_DRAM_WR_CLI2GRP_MAP1
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA1_DRAM_RD_GRP2VC_MAP
+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA1_DRAM_WR_GRP2VC_MAP
+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA1_DRAM_RD_LAZY
+#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+//MMEA1_DRAM_WR_LAZY
+#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+//MMEA1_DRAM_RD_CAM_CNTL
+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+//MMEA1_DRAM_WR_CAM_CNTL
+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+//MMEA1_DRAM_PAGE_BURST
+#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA1_DRAM_RD_PRI_AGE
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA1_DRAM_WR_PRI_AGE
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA1_DRAM_RD_PRI_QUEUING
+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA1_DRAM_WR_PRI_QUEUING
+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA1_DRAM_RD_PRI_FIXED
+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA1_DRAM_WR_PRI_FIXED
+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA1_DRAM_RD_PRI_URGENCY
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA1_DRAM_WR_PRI_URGENCY
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA1_DRAM_RD_PRI_QUANT_PRI1
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_DRAM_RD_PRI_QUANT_PRI2
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_DRAM_RD_PRI_QUANT_PRI3
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_DRAM_WR_PRI_QUANT_PRI1
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_DRAM_WR_PRI_QUANT_PRI2
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_DRAM_WR_PRI_QUANT_PRI3
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_ADDRNORM_BASE_ADDR0
+#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4
+#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8
+#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc
+#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L
+#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L
+#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA1_ADDRNORM_LIMIT_ADDR0
+#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa
+#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
+#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL
+#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L
+#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA1_ADDRNORM_BASE_ADDR1
+#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4
+#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8
+#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc
+#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L
+#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L
+#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA1_ADDRNORM_LIMIT_ADDR1
+#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa
+#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
+#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL
+#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L
+#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA1_ADDRNORM_OFFSET_ADDR1
+#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0
+#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14
+#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L
+#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L
+//MMEA1_ADDRNORM_HOLE_CNTL
+#define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
+#define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
+#define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
+#define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
+//MMEA1_ADDRDEC_BANK_CFG
+#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0
+#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5
+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa
+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd
+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10
+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11
+#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL
+#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L
+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L
+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L
+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L
+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L
+//MMEA1_ADDRDEC_MISC_CFG
+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0
+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1
+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2
+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3
+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4
+#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8
+#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9
+#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc
+#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10
+#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14
+#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16
+#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18
+#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b
+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L
+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L
+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L
+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L
+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L
+#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L
+#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L
+#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L
+#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L
+#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L
+#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L
+#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L
+#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L
+//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L
+//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L
+//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L
+//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L
+//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L
+//MMEA1_ADDRDECDRAM_ADDR_HASH_PC
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L
+//MMEA1_ADDRDECDRAM_ADDR_HASH_PC2
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL
+//MMEA1_ADDRDECDRAM_ADDR_HASH_CS0
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDECDRAM_ADDR_HASH_CS1
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDECDRAM_HARVEST_ENABLE
+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
+//MMEA1_ADDRDEC0_BASE_ADDR_CS0
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_BASE_ADDR_CS1
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_BASE_ADDR_CS2
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_BASE_ADDR_CS3
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_BASE_ADDR_SECCS0
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_BASE_ADDR_SECCS1
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_BASE_ADDR_SECCS2
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_BASE_ADDR_SECCS3
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_ADDR_MASK_CS01
+#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_ADDR_MASK_CS23
+#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_ADDR_MASK_SECCS01
+#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_ADDR_MASK_SECCS23
+#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_ADDR_CFG_CS01
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+//MMEA1_ADDRDEC0_ADDR_CFG_CS23
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+//MMEA1_ADDRDEC0_ADDR_SEL_CS01
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA1_ADDRDEC0_ADDR_SEL_CS23
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA1_ADDRDEC0_COL_SEL_LO_CS01
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA1_ADDRDEC0_COL_SEL_LO_CS23
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA1_ADDRDEC0_COL_SEL_HI_CS01
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA1_ADDRDEC0_COL_SEL_HI_CS23
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA1_ADDRDEC0_RM_SEL_CS01
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA1_ADDRDEC0_RM_SEL_CS23
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA1_ADDRDEC0_RM_SEL_SECCS01
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA1_ADDRDEC0_RM_SEL_SECCS23
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA1_ADDRDEC1_BASE_ADDR_CS0
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_BASE_ADDR_CS1
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_BASE_ADDR_CS2
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_BASE_ADDR_CS3
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_BASE_ADDR_SECCS0
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_BASE_ADDR_SECCS1
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_BASE_ADDR_SECCS2
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_BASE_ADDR_SECCS3
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_ADDR_MASK_CS01
+#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_ADDR_MASK_CS23
+#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_ADDR_MASK_SECCS01
+#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_ADDR_MASK_SECCS23
+#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_ADDR_CFG_CS01
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+//MMEA1_ADDRDEC1_ADDR_CFG_CS23
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+//MMEA1_ADDRDEC1_ADDR_SEL_CS01
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA1_ADDRDEC1_ADDR_SEL_CS23
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA1_ADDRDEC1_COL_SEL_LO_CS01
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA1_ADDRDEC1_COL_SEL_LO_CS23
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA1_ADDRDEC1_COL_SEL_HI_CS01
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA1_ADDRDEC1_COL_SEL_HI_CS23
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA1_ADDRDEC1_RM_SEL_CS01
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA1_ADDRDEC1_RM_SEL_CS23
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA1_ADDRDEC1_RM_SEL_SECCS01
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA1_ADDRDEC1_RM_SEL_SECCS23
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA1_IO_RD_CLI2GRP_MAP0
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA1_IO_RD_CLI2GRP_MAP1
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA1_IO_WR_CLI2GRP_MAP0
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA1_IO_WR_CLI2GRP_MAP1
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA1_IO_RD_COMBINE_FLUSH
+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+//MMEA1_IO_WR_COMBINE_FLUSH
+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+//MMEA1_IO_GROUP_BURST
+#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA1_IO_RD_PRI_AGE
+#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA1_IO_WR_PRI_AGE
+#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA1_IO_RD_PRI_QUEUING
+#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA1_IO_WR_PRI_QUEUING
+#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA1_IO_RD_PRI_FIXED
+#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA1_IO_WR_PRI_FIXED
+#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA1_IO_RD_PRI_URGENCY
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA1_IO_WR_PRI_URGENCY
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA1_IO_RD_PRI_URGENCY_MASK
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L
+//MMEA1_IO_WR_PRI_URGENCY_MASK
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L
+//MMEA1_IO_RD_PRI_QUANT_PRI1
+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_IO_RD_PRI_QUANT_PRI2
+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_IO_RD_PRI_QUANT_PRI3
+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_IO_WR_PRI_QUANT_PRI1
+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_IO_WR_PRI_QUANT_PRI2
+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_IO_WR_PRI_QUANT_PRI3
+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_SDP_ARB_DRAM
+#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0
+#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8
+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10
+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11
+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12
+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13
+#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14
+#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL
+#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L
+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L
+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L
+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L
+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L
+#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L
+//MMEA1_SDP_ARB_FINAL
+#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0
+#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5
+#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
+#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18
+#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19
+#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a
+#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL
+#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L
+#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L
+#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L
+#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L
+#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L
+//MMEA1_SDP_DRAM_PRIORITY
+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA1_SDP_IO_PRIORITY
+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA1_SDP_CREDITS
+#define MMEA1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0
+#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8
+#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10
+#define MMEA1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL
+#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L
+#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L
+//MMEA1_SDP_TAG_RESERVE0
+#define MMEA1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0
+#define MMEA1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8
+#define MMEA1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10
+#define MMEA1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18
+#define MMEA1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL
+#define MMEA1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L
+#define MMEA1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L
+#define MMEA1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L
+//MMEA1_SDP_TAG_RESERVE1
+#define MMEA1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0
+#define MMEA1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8
+#define MMEA1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10
+#define MMEA1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18
+#define MMEA1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL
+#define MMEA1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L
+#define MMEA1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L
+#define MMEA1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L
+//MMEA1_SDP_VCC_RESERVE0
+#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//MMEA1_SDP_VCC_RESERVE1
+#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//MMEA1_SDP_VCD_RESERVE0
+#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//MMEA1_SDP_VCD_RESERVE1
+#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//MMEA1_SDP_REQ_CNTL
+#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0
+#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1
+#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2
+#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3
+#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4
+#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L
+#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L
+#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L
+#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L
+#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L
+//MMEA1_MISC
+#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0
+#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1
+#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2
+#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3
+#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4
+#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5
+#define MMEA1_MISC__RRET_SWAP_MODE__SHIFT 0x6
+#define MMEA1_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x7
+#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x8
+#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xa
+#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xc
+#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xe
+#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x13
+#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x14
+#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x15
+#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x16
+#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x17
+#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x18
+#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L
+#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L
+#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L
+#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L
+#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L
+#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L
+#define MMEA1_MISC__RRET_SWAP_MODE_MASK 0x00000040L
+#define MMEA1_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000080L
+#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000300L
+#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00000C00L
+#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00003000L
+#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x0007C000L
+#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x00080000L
+#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x00100000L
+#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x00200000L
+#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x00400000L
+#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x00800000L
+#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x01000000L
+//MMEA1_LATENCY_SAMPLING
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L
+//MMEA1_PERFCOUNTER_LO
+#define MMEA1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MMEA1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MMEA1_PERFCOUNTER_HI
+#define MMEA1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MMEA1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//MMEA1_PERFCOUNTER0_CFG
+#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MMEA1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MMEA1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMEA1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MMEA1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MMEA1_PERFCOUNTER1_CFG
+#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MMEA1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MMEA1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMEA1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MMEA1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MMEA1_PERFCOUNTER_RSLT_CNTL
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//MMEA1_EDC_CNT
+#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
+#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
+#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
+#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
+#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14
+#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16
+#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18
+#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a
+#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c
+#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
+#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
+#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
+#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
+#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L
+#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L
+#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L
+#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L
+#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L
+//MMEA1_EDC_CNT2
+#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
+#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
+#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
+#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
+//MMEA1_DSM_CNTL
+#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15
+#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17
+#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L
+#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
+//MMEA1_DSM_CNTLA
+#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+//MMEA1_DSM_CNTLB
+//MMEA1_DSM_CNTL2
+#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17
+#define MMEA1_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
+#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L
+#define MMEA1_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
+//MMEA1_DSM_CNTL2A
+#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+//MMEA1_DSM_CNTL2B
+//MMEA1_CGTT_CLK_CTRL
+#define MMEA1_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c
+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d
+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e
+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f
+#define MMEA1_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L
+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L
+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L
+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L
+//MMEA1_EDC_MODE
+#define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
+#define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11
+#define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14
+#define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d
+#define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f
+#define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
+#define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L
+#define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L
+#define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L
+#define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L
+//MMEA1_ERR_STATUS
+#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
+#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
+#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0x8
+#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0x9
+#define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xa
+#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
+#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
+#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000100L
+#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000200L
+#define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00000400L
+//MMEA1_MISC2
+#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0
+#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1
+#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2
+#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7
+#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L
+#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L
+#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL
+#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L
+
+
+// addressBlock: mmhub_pctldec
+//PCTL_MISC
+#define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x0
+#define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x3
+#define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0x6
+#define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0xb
+#define PCTL_MISC__IGNORE_EA0_SDP_ACK__SHIFT 0xc
+#define PCTL_MISC__IGNORE_EA1_SDP_ACK__SHIFT 0xd
+#define PCTL_MISC__PGFSM_CMD_STATUS__SHIFT 0xe
+#define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x00000007L
+#define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00000038L
+#define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x000007C0L
+#define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00000800L
+#define PCTL_MISC__IGNORE_EA0_SDP_ACK_MASK 0x00001000L
+#define PCTL_MISC__IGNORE_EA1_SDP_ACK_MASK 0x00002000L
+#define PCTL_MISC__PGFSM_CMD_STATUS_MASK 0x0000C000L
+//PCTL_MMHUB_DEEPSLEEP
+#define PCTL_MMHUB_DEEPSLEEP__DS0__SHIFT 0x0
+#define PCTL_MMHUB_DEEPSLEEP__DS1__SHIFT 0x1
+#define PCTL_MMHUB_DEEPSLEEP__DS2__SHIFT 0x2
+#define PCTL_MMHUB_DEEPSLEEP__DS3__SHIFT 0x3
+#define PCTL_MMHUB_DEEPSLEEP__DS4__SHIFT 0x4
+#define PCTL_MMHUB_DEEPSLEEP__DS5__SHIFT 0x5
+#define PCTL_MMHUB_DEEPSLEEP__DS6__SHIFT 0x6
+#define PCTL_MMHUB_DEEPSLEEP__DS7__SHIFT 0x7
+#define PCTL_MMHUB_DEEPSLEEP__DS8__SHIFT 0x8
+#define PCTL_MMHUB_DEEPSLEEP__DS9__SHIFT 0x9
+#define PCTL_MMHUB_DEEPSLEEP__DS10__SHIFT 0xa
+#define PCTL_MMHUB_DEEPSLEEP__DS11__SHIFT 0xb
+#define PCTL_MMHUB_DEEPSLEEP__DS12__SHIFT 0xc
+#define PCTL_MMHUB_DEEPSLEEP__DS13__SHIFT 0xd
+#define PCTL_MMHUB_DEEPSLEEP__DS14__SHIFT 0xe
+#define PCTL_MMHUB_DEEPSLEEP__DS15__SHIFT 0xf
+#define PCTL_MMHUB_DEEPSLEEP__DS16__SHIFT 0x10
+#define PCTL_MMHUB_DEEPSLEEP__SETCLEAR__SHIFT 0x1f
+#define PCTL_MMHUB_DEEPSLEEP__DS0_MASK 0x00000001L
+#define PCTL_MMHUB_DEEPSLEEP__DS1_MASK 0x00000002L
+#define PCTL_MMHUB_DEEPSLEEP__DS2_MASK 0x00000004L
+#define PCTL_MMHUB_DEEPSLEEP__DS3_MASK 0x00000008L
+#define PCTL_MMHUB_DEEPSLEEP__DS4_MASK 0x00000010L
+#define PCTL_MMHUB_DEEPSLEEP__DS5_MASK 0x00000020L
+#define PCTL_MMHUB_DEEPSLEEP__DS6_MASK 0x00000040L
+#define PCTL_MMHUB_DEEPSLEEP__DS7_MASK 0x00000080L
+#define PCTL_MMHUB_DEEPSLEEP__DS8_MASK 0x00000100L
+#define PCTL_MMHUB_DEEPSLEEP__DS9_MASK 0x00000200L
+#define PCTL_MMHUB_DEEPSLEEP__DS10_MASK 0x00000400L
+#define PCTL_MMHUB_DEEPSLEEP__DS11_MASK 0x00000800L
+#define PCTL_MMHUB_DEEPSLEEP__DS12_MASK 0x00001000L
+#define PCTL_MMHUB_DEEPSLEEP__DS13_MASK 0x00002000L
+#define PCTL_MMHUB_DEEPSLEEP__DS14_MASK 0x00004000L
+#define PCTL_MMHUB_DEEPSLEEP__DS15_MASK 0x00008000L
+#define PCTL_MMHUB_DEEPSLEEP__DS16_MASK 0x00010000L
+#define PCTL_MMHUB_DEEPSLEEP__SETCLEAR_MASK 0x80000000L
+//PCTL_MMHUB_DEEPSLEEP_OVERRIDE
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L
+//PCTL_PG_IGNORE_DEEPSLEEP
+#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x0
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x1
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x2
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x3
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x4
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x5
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x6
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x7
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x8
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x9
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0xa
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xb
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xc
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xd
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xe
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xf
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0x10
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x11
+#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00000001L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000002L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000004L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000008L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000010L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000020L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000040L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000080L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000100L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000200L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000400L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000800L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00001000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00002000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00004000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00008000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00010000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00020000L
+//PCTL_PG_DAGB
+#define PCTL_PG_DAGB__DS0__SHIFT 0x0
+#define PCTL_PG_DAGB__DS1__SHIFT 0x1
+#define PCTL_PG_DAGB__DS2__SHIFT 0x2
+#define PCTL_PG_DAGB__DS3__SHIFT 0x3
+#define PCTL_PG_DAGB__DS4__SHIFT 0x4
+#define PCTL_PG_DAGB__DS5__SHIFT 0x5
+#define PCTL_PG_DAGB__DS6__SHIFT 0x6
+#define PCTL_PG_DAGB__DS7__SHIFT 0x7
+#define PCTL_PG_DAGB__DS8__SHIFT 0x8
+#define PCTL_PG_DAGB__DS9__SHIFT 0x9
+#define PCTL_PG_DAGB__DS10__SHIFT 0xa
+#define PCTL_PG_DAGB__DS11__SHIFT 0xb
+#define PCTL_PG_DAGB__DS12__SHIFT 0xc
+#define PCTL_PG_DAGB__DS13__SHIFT 0xd
+#define PCTL_PG_DAGB__DS14__SHIFT 0xe
+#define PCTL_PG_DAGB__DS15__SHIFT 0xf
+#define PCTL_PG_DAGB__DS16__SHIFT 0x10
+#define PCTL_PG_DAGB__DS0_MASK 0x00000001L
+#define PCTL_PG_DAGB__DS1_MASK 0x00000002L
+#define PCTL_PG_DAGB__DS2_MASK 0x00000004L
+#define PCTL_PG_DAGB__DS3_MASK 0x00000008L
+#define PCTL_PG_DAGB__DS4_MASK 0x00000010L
+#define PCTL_PG_DAGB__DS5_MASK 0x00000020L
+#define PCTL_PG_DAGB__DS6_MASK 0x00000040L
+#define PCTL_PG_DAGB__DS7_MASK 0x00000080L
+#define PCTL_PG_DAGB__DS8_MASK 0x00000100L
+#define PCTL_PG_DAGB__DS9_MASK 0x00000200L
+#define PCTL_PG_DAGB__DS10_MASK 0x00000400L
+#define PCTL_PG_DAGB__DS11_MASK 0x00000800L
+#define PCTL_PG_DAGB__DS12_MASK 0x00001000L
+#define PCTL_PG_DAGB__DS13_MASK 0x00002000L
+#define PCTL_PG_DAGB__DS14_MASK 0x00004000L
+#define PCTL_PG_DAGB__DS15_MASK 0x00008000L
+#define PCTL_PG_DAGB__DS16_MASK 0x00010000L
+//PCTL0_RENG_RAM_INDEX
+#define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
+#define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL
+//PCTL0_RENG_RAM_DATA
+#define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
+#define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL
+//PCTL0_RENG_EXECUTE
+#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0
+#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1
+#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2
+#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3
+#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xe
+#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x19
+#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L
+#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L
+#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L
+#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00003FF8L
+#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x01FFC000L
+#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x02000000L
+//PCTL0_MISC
+#define PCTL0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb
+#define PCTL0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc
+#define PCTL0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf
+#define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10
+#define PCTL0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L
+#define PCTL0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L
+#define PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L
+#define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L
+//PCTL0_STCTRL_REGISTER_SAVE_RANGE0
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL0_STCTRL_REGISTER_SAVE_RANGE1
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL0_STCTRL_REGISTER_SAVE_RANGE2
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET
+#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
+#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
+#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL
+#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L
+//PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1
+#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
+#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
+#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL
+#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L
+//PCTL1_RENG_RAM_INDEX
+#define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
+#define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL
+//PCTL1_RENG_RAM_DATA
+#define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
+#define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL
+//PCTL1_RENG_EXECUTE
+#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0
+#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1
+#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2
+#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3
+#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd
+#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x17
+#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L
+#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L
+#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L
+#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FF8L
+#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x007FE000L
+#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00800000L
+//PCTL1_MISC
+#define PCTL1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa
+#define PCTL1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb
+#define PCTL1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe
+#define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf
+#define PCTL1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10
+#define PCTL1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L
+#define PCTL1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L
+#define PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L
+#define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L
+#define PCTL1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L
+//PCTL1_STCTRL_REGISTER_SAVE_RANGE0
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL1_STCTRL_REGISTER_SAVE_RANGE1
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL1_STCTRL_REGISTER_SAVE_RANGE2
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET
+#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
+#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
+#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL
+#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L
+//PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1
+#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
+#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
+#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL
+#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L
+//PCTL2_RENG_RAM_INDEX
+#define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
+#define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL
+//PCTL2_RENG_RAM_DATA
+#define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
+#define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL
+//PCTL2_RENG_EXECUTE
+#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0
+#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1
+#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2
+#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3
+#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd
+#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x17
+#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L
+#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L
+#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L
+#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FF8L
+#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x007FE000L
+#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00800000L
+//PCTL2_MISC
+#define PCTL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa
+#define PCTL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb
+#define PCTL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe
+#define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf
+#define PCTL2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10
+#define PCTL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L
+#define PCTL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L
+#define PCTL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L
+#define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L
+#define PCTL2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L
+//PCTL2_STCTRL_REGISTER_SAVE_RANGE0
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL2_STCTRL_REGISTER_SAVE_RANGE1
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL2_STCTRL_REGISTER_SAVE_RANGE2
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET
+#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
+#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
+#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL
+#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L
+//PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1
+#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
+#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
+#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL
+#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L
+
+
+// addressBlock: mmhub_l1tlb_vml1dec
+//MC_VM_MX_L1_TLB0_STATUS
+#define MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L
+#define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//MC_VM_MX_L1_TLB1_STATUS
+#define MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L
+#define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//MC_VM_MX_L1_TLB2_STATUS
+#define MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L
+#define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//MC_VM_MX_L1_TLB3_STATUS
+#define MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L
+#define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//MC_VM_MX_L1_TLB4_STATUS
+#define MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L
+#define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//MC_VM_MX_L1_TLB5_STATUS
+#define MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L
+#define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//MC_VM_MX_L1_TLB6_STATUS
+#define MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L
+#define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//MC_VM_MX_L1_TLB7_STATUS
+#define MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L
+#define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+
+
+// addressBlock: mmhub_l1tlb_vml1pldec
+//MC_VM_MX_L1_PERFCOUNTER0_CFG
+#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_MX_L1_PERFCOUNTER1_CFG
+#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_MX_L1_PERFCOUNTER2_CFG
+#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_MX_L1_PERFCOUNTER3_CFG
+#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+
+// addressBlock: mmhub_l1tlb_vml1prdec
+//MC_VM_MX_L1_PERFCOUNTER_LO
+#define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MC_VM_MX_L1_PERFCOUNTER_HI
+#define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+
+
+// addressBlock: mmhub_utcl2_atcl2dec
+//ATC_L2_CNTL
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7
+#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8
+#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L
+#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L
+#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
+//ATC_L2_CNTL2
+#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
+#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
+#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
+#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
+#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
+#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L
+#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L
+#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L
+//ATC_L2_CACHE_DATA0
+#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0
+#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1
+#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2
+#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17
+#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L
+#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L
+#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL
+#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L
+//ATC_L2_CACHE_DATA1
+#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0
+#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL
+//ATC_L2_CACHE_DATA2
+#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0
+#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL
+//ATC_L2_CNTL3
+#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0
+#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3
+#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L
+#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L
+//ATC_L2_STATUS
+#define ATC_L2_STATUS__BUSY__SHIFT 0x0
+#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1
+#define ATC_L2_STATUS__BUSY_MASK 0x00000001L
+#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL
+//ATC_L2_STATUS2
+#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0
+#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8
+#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL
+#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L
+//ATC_L2_MISC_CG
+#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6
+#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12
+#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L
+#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L
+#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L
+//ATC_L2_MEM_POWER_LS
+#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
+#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
+#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
+#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
+//ATC_L2_CGTT_CLK_CTRL
+#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
+#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
+#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
+#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
+
+
+// addressBlock: mmhub_utcl2_vml2pfdec
+//VM_L2_CNTL
+#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
+#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
+#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
+#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
+#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
+#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
+#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
+#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
+#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
+#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
+#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
+#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
+#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
+#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a
+#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L
+#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L
+#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL
+#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L
+#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L
+#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L
+#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L
+#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
+#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L
+#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L
+#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L
+#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L
+#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L
+#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L
+//VM_L2_CNTL2
+#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
+#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
+#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
+#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
+#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17
+#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
+#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
+#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L
+#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L
+#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L
+#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L
+#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L
+#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L
+#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L
+//VM_L2_CNTL3
+#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
+#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
+#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
+#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
+#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
+#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
+#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f
+#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L
+#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L
+#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L
+#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L
+#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L
+#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L
+#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L
+//VM_L2_STATUS
+#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0
+#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
+#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11
+#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12
+#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13
+#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14
+#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15
+#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L
+#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL
+#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L
+#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L
+#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L
+#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L
+#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L
+//VM_DUMMY_PAGE_FAULT_CNTL
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL
+//VM_DUMMY_PAGE_FAULT_ADDR_LO32
+#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0
+#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//VM_DUMMY_PAGE_FAULT_ADDR_HI32
+#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0
+#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL
+//VM_L2_PROTECTION_FAULT_CNTL
+#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1
+#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5
+#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6
+#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
+#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8
+#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9
+#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb
+#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd
+#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d
+#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e
+#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f
+#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L
+#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L
+#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L
+#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L
+#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L
+#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L
+#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L
+#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L
+#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L
+#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L
+#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L
+#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L
+//VM_L2_PROTECTION_FAULT_CNTL2
+#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10
+#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11
+#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12
+#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13
+#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL
+#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L
+#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L
+#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L
+#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L
+//VM_L2_PROTECTION_FAULT_MM_CNTL3
+#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
+//VM_L2_PROTECTION_FAULT_MM_CNTL4
+#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
+//VM_L2_PROTECTION_FAULT_STATUS
+#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1
+#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4
+#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8
+#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9
+#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12
+#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13
+#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14
+#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18
+#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19
+#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L
+#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL
+#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L
+#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L
+#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L
+#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L
+#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L
+#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L
+#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L
+#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L
+//VM_L2_PROTECTION_FAULT_ADDR_LO32
+#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//VM_L2_PROTECTION_FAULT_ADDR_HI32
+#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
+//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
+#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
+#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
+//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL
+//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL
+//VM_L2_CNTL4
+#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0
+#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6
+#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7
+#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8
+#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12
+#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c
+#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL
+#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L
+#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L
+#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L
+#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L
+#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L
+//VM_L2_MM_GROUP_RT_CLASSES
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L
+//VM_L2_BANK_SELECT_RESERVED_CID
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
+#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
+#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
+//VM_L2_BANK_SELECT_RESERVED_CID2
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
+#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
+#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
+//VM_L2_CACHE_PARITY_CNTL
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L
+//VM_L2_CGTT_CLK_CTRL
+#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
+#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
+#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
+#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
+
+
+// addressBlock: mmhub_utcl2_vml2vcdec
+//VM_CONTEXT0_CNTL
+#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT1_CNTL
+#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT2_CNTL
+#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT3_CNTL
+#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT4_CNTL
+#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT5_CNTL
+#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT6_CNTL
+#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT7_CNTL
+#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT8_CNTL
+#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT9_CNTL
+#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT10_CNTL
+#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT11_CNTL
+#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT12_CNTL
+#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT13_CNTL
+#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT14_CNTL
+#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT15_CNTL
+#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXTS_DISABLE
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L
+//VM_INVALIDATE_ENG0_SEM
+#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG1_SEM
+#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG2_SEM
+#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG3_SEM
+#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG4_SEM
+#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG5_SEM
+#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG6_SEM
+#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG7_SEM
+#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG8_SEM
+#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG9_SEM
+#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG10_SEM
+#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG11_SEM
+#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG12_SEM
+#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG13_SEM
+#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG14_SEM
+#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG15_SEM
+#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG16_SEM
+#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG17_SEM
+#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG0_REQ
+#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG1_REQ
+#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG2_REQ
+#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG3_REQ
+#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG4_REQ
+#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG5_REQ
+#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG6_REQ
+#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG7_REQ
+#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG8_REQ
+#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG9_REQ
+#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG10_REQ
+#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG11_REQ
+#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG12_REQ
+#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG13_REQ
+#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG14_REQ
+#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG15_REQ
+#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG16_REQ
+#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG17_REQ
+#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+//VM_INVALIDATE_ENG0_ACK
+#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG1_ACK
+#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG2_ACK
+#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG3_ACK
+#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG4_ACK
+#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG5_ACK
+#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG6_ACK
+#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG7_ACK
+#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG8_ACK
+#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG9_ACK
+#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG10_ACK
+#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG11_ACK
+#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG12_ACK
+#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG13_ACK
+#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG14_ACK
+#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG15_ACK
+#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG16_ACK
+#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG17_ACK
+#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+
+
+// addressBlock: mmhub_utcl2_vml2pldec
+//MC_VM_L2_PERFCOUNTER0_CFG
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER1_CFG
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER2_CFG
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER3_CFG
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER4_CFG
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER5_CFG
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER6_CFG
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER7_CFG
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER_RSLT_CNTL
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+
+// addressBlock: mmhub_utcl2_vml2prdec
+//MC_VM_L2_PERFCOUNTER_LO
+#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MC_VM_L2_PERFCOUNTER_HI
+#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+
+
+// addressBlock: mmhub_utcl2_vmsharedhvdec
+//MC_VM_FB_SIZE_OFFSET_VF0
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF1
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF2
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF3
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF4
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF5
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF6
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF7
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF8
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF9
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF10
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF11
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF12
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF13
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF14
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF15
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L
+//VM_IOMMU_MMIO_CNTRL_1
+#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8
+#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L
+//MC_VM_MARC_BASE_LO_0
+#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L
+//MC_VM_MARC_BASE_LO_1
+#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L
+//MC_VM_MARC_BASE_LO_2
+#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L
+//MC_VM_MARC_BASE_LO_3
+#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L
+//MC_VM_MARC_BASE_HI_0
+#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL
+//MC_VM_MARC_BASE_HI_1
+#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL
+//MC_VM_MARC_BASE_HI_2
+#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL
+//MC_VM_MARC_BASE_HI_3
+#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL
+//MC_VM_MARC_RELOC_LO_0
+#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L
+#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L
+#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L
+//MC_VM_MARC_RELOC_LO_1
+#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L
+#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L
+#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L
+//MC_VM_MARC_RELOC_LO_2
+#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L
+#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L
+#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L
+//MC_VM_MARC_RELOC_LO_3
+#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L
+#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L
+#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L
+//MC_VM_MARC_RELOC_HI_0
+#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL
+//MC_VM_MARC_RELOC_HI_1
+#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL
+//MC_VM_MARC_RELOC_HI_2
+#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL
+//MC_VM_MARC_RELOC_HI_3
+#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL
+//MC_VM_MARC_LEN_LO_0
+#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L
+//MC_VM_MARC_LEN_LO_1
+#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L
+//MC_VM_MARC_LEN_LO_2
+#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L
+//MC_VM_MARC_LEN_LO_3
+#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L
+//MC_VM_MARC_LEN_HI_0
+#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL
+//MC_VM_MARC_LEN_HI_1
+#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL
+//MC_VM_MARC_LEN_HI_2
+#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL
+//MC_VM_MARC_LEN_HI_3
+#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL
+//VM_IOMMU_CONTROL_REGISTER
+#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0
+#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L
+//VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
+#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd
+#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L
+//VM_PCIE_ATS_CNTL
+#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10
+#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L
+#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_0
+#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_1
+#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_2
+#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_3
+#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_4
+#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_5
+#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_6
+#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_7
+#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_8
+#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_9
+#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_10
+#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_11
+#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_12
+#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_13
+#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_14
+#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_15
+#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L
+//UTCL2_CGTT_CLK_CTRL
+#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc
+#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
+#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
+#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L
+#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
+#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
+
+
+// addressBlock: mmhub_utcl2_vmsharedpfdec
+//MC_VM_NB_MMIOBASE
+#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0
+#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL
+//MC_VM_NB_MMIOLIMIT
+#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0
+#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL
+//MC_VM_NB_PCI_CTRL
+#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17
+#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L
+//MC_VM_NB_PCI_ARB
+#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3
+#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L
+//MC_VM_NB_TOP_OF_DRAM_SLOT1
+#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17
+#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L
+//MC_VM_NB_LOWER_TOP_OF_DRAM2
+#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0
+#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17
+#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L
+#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L
+//MC_VM_NB_UPPER_TOP_OF_DRAM2
+#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0
+#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL
+//MC_VM_FB_OFFSET
+#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
+#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL
+//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL
+//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL
+//MC_VM_STEERING
+#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
+#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L
+//MC_SHARED_VIRT_RESET_REQ
+#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
+#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L
+//MC_MEM_POWER_LS
+#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
+#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
+#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
+#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
+//MC_VM_CACHEABLE_DRAM_ADDRESS_START
+#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0
+#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
+//MC_VM_CACHEABLE_DRAM_ADDRESS_END
+#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0
+#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
+//MC_VM_APT_CNTL
+#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0
+#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1
+#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L
+#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L
+//MC_VM_LOCAL_HBM_ADDRESS_START
+#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0
+#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
+//MC_VM_LOCAL_HBM_ADDRESS_END
+#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0
+#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
+//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
+#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0
+#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L
+
+
+// addressBlock: mmhub_utcl2_vmsharedvcdec
+//MC_VM_FB_LOCATION_BASE
+#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0
+#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL
+//MC_VM_FB_LOCATION_TOP
+#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0
+#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL
+//MC_VM_AGP_TOP
+#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
+#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL
+//MC_VM_AGP_BOT
+#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
+#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL
+//MC_VM_AGP_BASE
+#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
+#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL
+//MC_VM_SYSTEM_APERTURE_LOW_ADDR
+#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
+//MC_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
+//MC_VM_MX_L1_TLB_CNTL
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
+#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
+#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb
+#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L
+#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L
+#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L
+#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L
+
+
+// addressBlock: mmhub_utcl2_atcl2pfcntrdec
+//ATC_L2_PERFCOUNTER_LO
+#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//ATC_L2_PERFCOUNTER_HI
+#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+
+
+// addressBlock: mmhub_utcl2_atcl2pfcntldec
+//ATC_L2_PERFCOUNTER0_CFG
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//ATC_L2_PERFCOUNTER1_CFG
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//ATC_L2_PERFCOUNTER_RSLT_CNTL
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h
new file mode 100644
index 000000000000..98ba7d832423
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h
@@ -0,0 +1,342 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _mp_9_0_DEFAULT_HEADER
+#define _mp_9_0_DEFAULT_HEADER
+
+
+// addressBlock: mp_SmuMp0_SmnDec
+#define mmMP0_SMN_C2PMSG_32_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_33_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_34_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_35_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_36_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_37_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_38_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_39_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_40_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_41_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_42_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_43_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_44_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_45_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_46_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_47_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_48_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_49_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_50_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_51_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_52_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_53_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_54_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_55_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_56_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_57_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_58_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_59_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_60_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_61_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_62_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_63_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_64_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_65_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_66_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_67_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_68_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_69_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_70_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_71_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_72_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_73_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_74_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_75_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_76_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_77_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_78_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_79_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_80_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_81_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_82_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_83_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_84_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_85_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_86_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_87_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_88_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_89_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_90_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_91_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_92_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_93_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_94_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_95_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_96_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_97_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_98_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_99_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_100_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_101_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_102_DEFAULT 0x00000000
+#define mmMP0_SMN_C2PMSG_103_DEFAULT 0x00000000
+#define mmMP0_SMN_ACTIVE_FCN_ID_DEFAULT 0x00000000
+#define mmMP0_SMN_IH_CREDIT_DEFAULT 0x00000000
+#define mmMP0_SMN_IH_SW_INT_DEFAULT 0x00000000
+#define mmMP0_SMN_IH_SW_INT_CTRL_DEFAULT 0x00000000
+
+
+// addressBlock: mp_SmuMp1_SmnDec
+#define mmMP1_SMN_ACP2MP_RESP_DEFAULT 0x00000000
+#define mmMP1_SMN_DC2MP_RESP_DEFAULT 0x00000000
+#define mmMP1_SMN_UVD2MP_RESP_DEFAULT 0x00000000
+#define mmMP1_SMN_VCE2MP_RESP_DEFAULT 0x00000000
+#define mmMP1_SMN_RLC2MP_RESP_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_32_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_33_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_34_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_35_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_36_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_37_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_38_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_39_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_40_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_41_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_42_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_43_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_44_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_45_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_46_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_47_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_48_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_49_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_50_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_51_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_52_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_53_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_54_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_55_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_56_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_57_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_58_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_59_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_60_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_61_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_62_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_63_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_64_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_65_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_66_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_67_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_68_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_69_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_70_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_71_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_72_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_73_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_74_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_75_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_76_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_77_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_78_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_79_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_80_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_81_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_82_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_83_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_84_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_85_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_86_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_87_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_88_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_89_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_90_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_91_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_92_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_93_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_94_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_95_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_96_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_97_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_98_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_99_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_100_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_101_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_102_DEFAULT 0x00000000
+#define mmMP1_SMN_C2PMSG_103_DEFAULT 0x00000000
+#define mmMP1_SMN_ACTIVE_FCN_ID_DEFAULT 0x00000000
+#define mmMP1_SMN_IH_CREDIT_DEFAULT 0x00000000
+#define mmMP1_SMN_IH_SW_INT_DEFAULT 0x00000000
+#define mmMP1_SMN_IH_SW_INT_CTRL_DEFAULT 0x00000000
+#define mmMP1_SMN_FPS_CNT_DEFAULT 0x00000000
+#define mmMP1_SMN_EXT_SCRATCH0_DEFAULT 0x00000000
+#define mmMP1_SMN_EXT_SCRATCH1_DEFAULT 0x00000000
+#define mmMP1_SMN_EXT_SCRATCH2_DEFAULT 0x00000000
+#define mmMP1_SMN_EXT_SCRATCH3_DEFAULT 0x00000000
+#define mmMP1_SMN_EXT_SCRATCH4_DEFAULT 0x00000000
+#define mmMP1_SMN_EXT_SCRATCH5_DEFAULT 0x00000000
+#define mmMP1_SMN_EXT_SCRATCH6_DEFAULT 0x00000000
+#define mmMP1_SMN_EXT_SCRATCH7_DEFAULT 0x00000000
+#define mmMP1_SMN_EXT_SCRATCH8_DEFAULT 0x00000000
+
+
+// addressBlock: mp_SmuMp1Pub_CruDec
+#define mmMP1_SMN_PUB_CTRL_DEFAULT 0x00000001
+#define smnMP1_FIRMWARE_FLAGS_DEFAULT 0x00000000
+#define smnMP1_PUB_SCRATCH0_DEFAULT 0x00000000
+#define smnMP1_PUB_SCRATCH1_DEFAULT 0x00000000
+#define smnMP1_PUB_SCRATCH2_DEFAULT 0x00000000
+#define smnMP1_PUB_SCRATCH3_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_0_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_1_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_2_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_3_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_4_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_5_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_6_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_7_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_8_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_9_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_10_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_11_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_12_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_13_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_14_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_15_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_16_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_17_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_18_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_19_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_20_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_21_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_22_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_23_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_24_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_25_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_26_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_27_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_28_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_29_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_30_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_31_DEFAULT 0x00000000
+#define smnMP1_P2CMSG_0_DEFAULT 0x00000000
+#define smnMP1_P2CMSG_1_DEFAULT 0x00000000
+#define smnMP1_P2CMSG_2_DEFAULT 0x00000000
+#define smnMP1_P2CMSG_3_DEFAULT 0x00000000
+#define smnMP1_P2CMSG_INTEN_DEFAULT 0x00000000
+#define smnMP1_P2CMSG_INTSTS_DEFAULT 0x00000000
+#define smnMP1_P2SMSG_0_DEFAULT 0x00000000
+#define smnMP1_P2SMSG_1_DEFAULT 0x00000000
+#define smnMP1_P2SMSG_2_DEFAULT 0x00000000
+#define smnMP1_P2SMSG_3_DEFAULT 0x00000000
+#define smnMP1_P2SMSG_INTSTS_DEFAULT 0x00000000
+#define smnMP1_S2PMSG_0_DEFAULT 0x00000000
+#define smnMP1_ACP2MP_RESP_DEFAULT 0x00000000
+#define smnMP1_DC2MP_RESP_DEFAULT 0x00000000
+#define smnMP1_UVD2MP_RESP_DEFAULT 0x00000000
+#define smnMP1_VCE2MP_RESP_DEFAULT 0x00000000
+#define smnMP1_RLC2MP_RESP_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_32_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_33_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_34_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_35_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_36_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_37_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_38_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_39_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_40_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_41_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_42_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_43_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_44_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_45_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_46_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_47_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_48_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_49_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_50_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_51_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_52_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_53_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_54_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_55_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_56_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_57_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_58_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_59_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_60_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_61_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_62_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_63_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_64_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_65_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_66_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_67_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_68_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_69_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_70_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_71_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_72_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_73_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_74_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_75_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_76_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_77_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_78_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_79_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_80_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_81_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_82_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_83_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_84_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_85_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_86_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_87_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_88_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_89_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_90_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_91_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_92_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_93_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_94_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_95_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_96_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_97_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_98_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_99_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_100_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_101_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_102_DEFAULT 0x00000000
+#define smnMP1_C2PMSG_103_DEFAULT 0x00000000
+#define smnMP1_ACTIVE_FCN_ID_DEFAULT 0x00000000
+#define smnMP1_IH_CREDIT_DEFAULT 0x00000000
+#define smnMP1_IH_SW_INT_DEFAULT 0x00000000
+#define smnMP1_IH_SW_INT_CTRL_DEFAULT 0x00000000
+#define smnMP1_FPS_CNT_DEFAULT 0x00000000
+#define smnMP1_PUB_CTRL_DEFAULT 0x00000001
+#define smnMP1_EXT_SCRATCH0_DEFAULT 0x00000000
+#define smnMP1_EXT_SCRATCH1_DEFAULT 0x00000000
+#define smnMP1_EXT_SCRATCH2_DEFAULT 0x00000000
+#define smnMP1_EXT_SCRATCH3_DEFAULT 0x00000000
+#define smnMP1_EXT_SCRATCH4_DEFAULT 0x00000000
+#define smnMP1_EXT_SCRATCH5_DEFAULT 0x00000000
+#define smnMP1_EXT_SCRATCH6_DEFAULT 0x00000000
+#define smnMP1_EXT_SCRATCH7_DEFAULT 0x00000000
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h
new file mode 100644
index 000000000000..621e8809c867
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h
@@ -0,0 +1,375 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _mp_9_0_OFFSET_HEADER
+#define _mp_9_0_OFFSET_HEADER
+
+
+
+// addressBlock: mp_SmuMp0_SmnDec
+// base address: 0x0
+#define mmMP0_SMN_C2PMSG_32 0x0060
+#define mmMP0_SMN_C2PMSG_32_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_33 0x0061
+#define mmMP0_SMN_C2PMSG_33_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_34 0x0062
+#define mmMP0_SMN_C2PMSG_34_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_35 0x0063
+#define mmMP0_SMN_C2PMSG_35_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_36 0x0064
+#define mmMP0_SMN_C2PMSG_36_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_37 0x0065
+#define mmMP0_SMN_C2PMSG_37_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_38 0x0066
+#define mmMP0_SMN_C2PMSG_38_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_39 0x0067
+#define mmMP0_SMN_C2PMSG_39_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_40 0x0068
+#define mmMP0_SMN_C2PMSG_40_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_41 0x0069
+#define mmMP0_SMN_C2PMSG_41_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_42 0x006a
+#define mmMP0_SMN_C2PMSG_42_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_43 0x006b
+#define mmMP0_SMN_C2PMSG_43_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_44 0x006c
+#define mmMP0_SMN_C2PMSG_44_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_45 0x006d
+#define mmMP0_SMN_C2PMSG_45_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_46 0x006e
+#define mmMP0_SMN_C2PMSG_46_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_47 0x006f
+#define mmMP0_SMN_C2PMSG_47_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_48 0x0070
+#define mmMP0_SMN_C2PMSG_48_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_49 0x0071
+#define mmMP0_SMN_C2PMSG_49_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_50 0x0072
+#define mmMP0_SMN_C2PMSG_50_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_51 0x0073
+#define mmMP0_SMN_C2PMSG_51_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_52 0x0074
+#define mmMP0_SMN_C2PMSG_52_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_53 0x0075
+#define mmMP0_SMN_C2PMSG_53_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_54 0x0076
+#define mmMP0_SMN_C2PMSG_54_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_55 0x0077
+#define mmMP0_SMN_C2PMSG_55_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_56 0x0078
+#define mmMP0_SMN_C2PMSG_56_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_57 0x0079
+#define mmMP0_SMN_C2PMSG_57_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_58 0x007a
+#define mmMP0_SMN_C2PMSG_58_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_59 0x007b
+#define mmMP0_SMN_C2PMSG_59_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_60 0x007c
+#define mmMP0_SMN_C2PMSG_60_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_61 0x007d
+#define mmMP0_SMN_C2PMSG_61_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_62 0x007e
+#define mmMP0_SMN_C2PMSG_62_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_63 0x007f
+#define mmMP0_SMN_C2PMSG_63_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_64 0x0080
+#define mmMP0_SMN_C2PMSG_64_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_65 0x0081
+#define mmMP0_SMN_C2PMSG_65_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_66 0x0082
+#define mmMP0_SMN_C2PMSG_66_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_67 0x0083
+#define mmMP0_SMN_C2PMSG_67_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_68 0x0084
+#define mmMP0_SMN_C2PMSG_68_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_69 0x0085
+#define mmMP0_SMN_C2PMSG_69_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_70 0x0086
+#define mmMP0_SMN_C2PMSG_70_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_71 0x0087
+#define mmMP0_SMN_C2PMSG_71_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_72 0x0088
+#define mmMP0_SMN_C2PMSG_72_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_73 0x0089
+#define mmMP0_SMN_C2PMSG_73_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_74 0x008a
+#define mmMP0_SMN_C2PMSG_74_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_75 0x008b
+#define mmMP0_SMN_C2PMSG_75_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_76 0x008c
+#define mmMP0_SMN_C2PMSG_76_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_77 0x008d
+#define mmMP0_SMN_C2PMSG_77_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_78 0x008e
+#define mmMP0_SMN_C2PMSG_78_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_79 0x008f
+#define mmMP0_SMN_C2PMSG_79_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_80 0x0090
+#define mmMP0_SMN_C2PMSG_80_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_81 0x0091
+#define mmMP0_SMN_C2PMSG_81_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_82 0x0092
+#define mmMP0_SMN_C2PMSG_82_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_83 0x0093
+#define mmMP0_SMN_C2PMSG_83_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_84 0x0094
+#define mmMP0_SMN_C2PMSG_84_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_85 0x0095
+#define mmMP0_SMN_C2PMSG_85_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_86 0x0096
+#define mmMP0_SMN_C2PMSG_86_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_87 0x0097
+#define mmMP0_SMN_C2PMSG_87_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_88 0x0098
+#define mmMP0_SMN_C2PMSG_88_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_89 0x0099
+#define mmMP0_SMN_C2PMSG_89_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_90 0x009a
+#define mmMP0_SMN_C2PMSG_90_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_91 0x009b
+#define mmMP0_SMN_C2PMSG_91_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_92 0x009c
+#define mmMP0_SMN_C2PMSG_92_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_93 0x009d
+#define mmMP0_SMN_C2PMSG_93_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_94 0x009e
+#define mmMP0_SMN_C2PMSG_94_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_95 0x009f
+#define mmMP0_SMN_C2PMSG_95_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_96 0x00a0
+#define mmMP0_SMN_C2PMSG_96_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_97 0x00a1
+#define mmMP0_SMN_C2PMSG_97_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_98 0x00a2
+#define mmMP0_SMN_C2PMSG_98_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_99 0x00a3
+#define mmMP0_SMN_C2PMSG_99_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_100 0x00a4
+#define mmMP0_SMN_C2PMSG_100_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_101 0x00a5
+#define mmMP0_SMN_C2PMSG_101_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_102 0x00a6
+#define mmMP0_SMN_C2PMSG_102_BASE_IDX 0
+#define mmMP0_SMN_C2PMSG_103 0x00a7
+#define mmMP0_SMN_C2PMSG_103_BASE_IDX 0
+#define mmMP0_SMN_ACTIVE_FCN_ID 0x00c0
+#define mmMP0_SMN_ACTIVE_FCN_ID_BASE_IDX 0
+#define mmMP0_SMN_IH_CREDIT 0x00c1
+#define mmMP0_SMN_IH_CREDIT_BASE_IDX 0
+#define mmMP0_SMN_IH_SW_INT 0x00c2
+#define mmMP0_SMN_IH_SW_INT_BASE_IDX 0
+#define mmMP0_SMN_IH_SW_INT_CTRL 0x00c3
+#define mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0
+
+
+// addressBlock: mp_SmuMp1_SmnDec
+// base address: 0x0
+#define mmMP1_SMN_ACP2MP_RESP 0x0240
+#define mmMP1_SMN_ACP2MP_RESP_BASE_IDX 0
+#define mmMP1_SMN_DC2MP_RESP 0x0241
+#define mmMP1_SMN_DC2MP_RESP_BASE_IDX 0
+#define mmMP1_SMN_UVD2MP_RESP 0x0242
+#define mmMP1_SMN_UVD2MP_RESP_BASE_IDX 0
+#define mmMP1_SMN_VCE2MP_RESP 0x0243
+#define mmMP1_SMN_VCE2MP_RESP_BASE_IDX 0
+#define mmMP1_SMN_RLC2MP_RESP 0x0244
+#define mmMP1_SMN_RLC2MP_RESP_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_32 0x0260
+#define mmMP1_SMN_C2PMSG_32_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_33 0x0261
+#define mmMP1_SMN_C2PMSG_33_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_34 0x0262
+#define mmMP1_SMN_C2PMSG_34_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_35 0x0263
+#define mmMP1_SMN_C2PMSG_35_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_36 0x0264
+#define mmMP1_SMN_C2PMSG_36_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_37 0x0265
+#define mmMP1_SMN_C2PMSG_37_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_38 0x0266
+#define mmMP1_SMN_C2PMSG_38_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_39 0x0267
+#define mmMP1_SMN_C2PMSG_39_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_40 0x0268
+#define mmMP1_SMN_C2PMSG_40_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_41 0x0269
+#define mmMP1_SMN_C2PMSG_41_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_42 0x026a
+#define mmMP1_SMN_C2PMSG_42_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_43 0x026b
+#define mmMP1_SMN_C2PMSG_43_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_44 0x026c
+#define mmMP1_SMN_C2PMSG_44_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_45 0x026d
+#define mmMP1_SMN_C2PMSG_45_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_46 0x026e
+#define mmMP1_SMN_C2PMSG_46_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_47 0x026f
+#define mmMP1_SMN_C2PMSG_47_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_48 0x0270
+#define mmMP1_SMN_C2PMSG_48_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_49 0x0271
+#define mmMP1_SMN_C2PMSG_49_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_50 0x0272
+#define mmMP1_SMN_C2PMSG_50_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_51 0x0273
+#define mmMP1_SMN_C2PMSG_51_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_52 0x0274
+#define mmMP1_SMN_C2PMSG_52_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_53 0x0275
+#define mmMP1_SMN_C2PMSG_53_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_54 0x0276
+#define mmMP1_SMN_C2PMSG_54_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_55 0x0277
+#define mmMP1_SMN_C2PMSG_55_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_56 0x0278
+#define mmMP1_SMN_C2PMSG_56_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_57 0x0279
+#define mmMP1_SMN_C2PMSG_57_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_58 0x027a
+#define mmMP1_SMN_C2PMSG_58_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_59 0x027b
+#define mmMP1_SMN_C2PMSG_59_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_60 0x027c
+#define mmMP1_SMN_C2PMSG_60_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_61 0x027d
+#define mmMP1_SMN_C2PMSG_61_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_62 0x027e
+#define mmMP1_SMN_C2PMSG_62_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_63 0x027f
+#define mmMP1_SMN_C2PMSG_63_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_64 0x0280
+#define mmMP1_SMN_C2PMSG_64_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_65 0x0281
+#define mmMP1_SMN_C2PMSG_65_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_66 0x0282
+#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_67 0x0283
+#define mmMP1_SMN_C2PMSG_67_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_68 0x0284
+#define mmMP1_SMN_C2PMSG_68_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_69 0x0285
+#define mmMP1_SMN_C2PMSG_69_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_70 0x0286
+#define mmMP1_SMN_C2PMSG_70_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_71 0x0287
+#define mmMP1_SMN_C2PMSG_71_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_72 0x0288
+#define mmMP1_SMN_C2PMSG_72_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_73 0x0289
+#define mmMP1_SMN_C2PMSG_73_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_74 0x028a
+#define mmMP1_SMN_C2PMSG_74_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_75 0x028b
+#define mmMP1_SMN_C2PMSG_75_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_76 0x028c
+#define mmMP1_SMN_C2PMSG_76_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_77 0x028d
+#define mmMP1_SMN_C2PMSG_77_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_78 0x028e
+#define mmMP1_SMN_C2PMSG_78_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_79 0x028f
+#define mmMP1_SMN_C2PMSG_79_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_80 0x0290
+#define mmMP1_SMN_C2PMSG_80_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_81 0x0291
+#define mmMP1_SMN_C2PMSG_81_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_82 0x0292
+#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_83 0x0293
+#define mmMP1_SMN_C2PMSG_83_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_84 0x0294
+#define mmMP1_SMN_C2PMSG_84_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_85 0x0295
+#define mmMP1_SMN_C2PMSG_85_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_86 0x0296
+#define mmMP1_SMN_C2PMSG_86_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_87 0x0297
+#define mmMP1_SMN_C2PMSG_87_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_88 0x0298
+#define mmMP1_SMN_C2PMSG_88_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_89 0x0299
+#define mmMP1_SMN_C2PMSG_89_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_90 0x029a
+#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_91 0x029b
+#define mmMP1_SMN_C2PMSG_91_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_92 0x029c
+#define mmMP1_SMN_C2PMSG_92_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_93 0x029d
+#define mmMP1_SMN_C2PMSG_93_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_94 0x029e
+#define mmMP1_SMN_C2PMSG_94_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_95 0x029f
+#define mmMP1_SMN_C2PMSG_95_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_96 0x02a0
+#define mmMP1_SMN_C2PMSG_96_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_97 0x02a1
+#define mmMP1_SMN_C2PMSG_97_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_98 0x02a2
+#define mmMP1_SMN_C2PMSG_98_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_99 0x02a3
+#define mmMP1_SMN_C2PMSG_99_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_100 0x02a4
+#define mmMP1_SMN_C2PMSG_100_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_101 0x02a5
+#define mmMP1_SMN_C2PMSG_101_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_102 0x02a6
+#define mmMP1_SMN_C2PMSG_102_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_103 0x02a7
+#define mmMP1_SMN_C2PMSG_103_BASE_IDX 0
+#define mmMP1_SMN_ACTIVE_FCN_ID 0x02c0
+#define mmMP1_SMN_ACTIVE_FCN_ID_BASE_IDX 0
+#define mmMP1_SMN_IH_CREDIT 0x02c1
+#define mmMP1_SMN_IH_CREDIT_BASE_IDX 0
+#define mmMP1_SMN_IH_SW_INT 0x02c2
+#define mmMP1_SMN_IH_SW_INT_BASE_IDX 0
+#define mmMP1_SMN_IH_SW_INT_CTRL 0x02c3
+#define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0
+#define mmMP1_SMN_FPS_CNT 0x02c4
+#define mmMP1_SMN_FPS_CNT_BASE_IDX 0
+#define mmMP1_SMN_EXT_SCRATCH0 0x03c0
+#define mmMP1_SMN_EXT_SCRATCH0_BASE_IDX 0
+#define mmMP1_SMN_EXT_SCRATCH1 0x03c1
+#define mmMP1_SMN_EXT_SCRATCH1_BASE_IDX 0
+#define mmMP1_SMN_EXT_SCRATCH2 0x03c2
+#define mmMP1_SMN_EXT_SCRATCH2_BASE_IDX 0
+#define mmMP1_SMN_EXT_SCRATCH3 0x03c3
+#define mmMP1_SMN_EXT_SCRATCH3_BASE_IDX 0
+#define mmMP1_SMN_EXT_SCRATCH4 0x03c4
+#define mmMP1_SMN_EXT_SCRATCH4_BASE_IDX 0
+#define mmMP1_SMN_EXT_SCRATCH5 0x03c5
+#define mmMP1_SMN_EXT_SCRATCH5_BASE_IDX 0
+#define mmMP1_SMN_EXT_SCRATCH6 0x03c6
+#define mmMP1_SMN_EXT_SCRATCH6_BASE_IDX 0
+#define mmMP1_SMN_EXT_SCRATCH7 0x03c7
+#define mmMP1_SMN_EXT_SCRATCH7_BASE_IDX 0
+#define mmMP1_SMN_EXT_SCRATCH8 0x03c8
+#define mmMP1_SMN_EXT_SCRATCH8_BASE_IDX 0
+
+
+// addressBlock: mp_SmuMp1Pub_CruDec
+// base address: 0x0
+#define mmMP1_SMN_PUB_CTRL 0x02c5
+#define mmMP1_SMN_PUB_CTRL_BASE_IDX 0
+
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h
new file mode 100644
index 000000000000..ae7b51870322
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h
@@ -0,0 +1,1463 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _mp_9_0_SH_MASK_HEADER
+#define _mp_9_0_SH_MASK_HEADER
+
+
+// addressBlock: mp_SmuMp0_SmnDec
+//MP0_SMN_C2PMSG_32
+#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_33
+#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_34
+#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_35
+#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_36
+#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_37
+#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_38
+#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_39
+#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_40
+#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_41
+#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_42
+#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_43
+#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_44
+#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_45
+#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_46
+#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_47
+#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_48
+#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_49
+#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_50
+#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_51
+#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_52
+#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_53
+#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_54
+#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_55
+#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_56
+#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_57
+#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_58
+#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_59
+#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_60
+#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_61
+#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_62
+#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_63
+#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_64
+#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_65
+#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_66
+#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_67
+#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_68
+#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_69
+#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_70
+#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_71
+#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_72
+#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_73
+#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_74
+#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_75
+#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_76
+#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_77
+#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_78
+#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_79
+#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_80
+#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_81
+#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_82
+#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_83
+#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_84
+#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_85
+#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_86
+#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_87
+#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_88
+#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_89
+#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_90
+#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_91
+#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_92
+#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_93
+#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_94
+#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_95
+#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_96
+#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_97
+#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_98
+#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_99
+#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_100
+#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_101
+#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_102
+#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_103
+#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_ACTIVE_FCN_ID
+#define MP0_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define MP0_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define MP0_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
+#define MP0_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//MP0_SMN_IH_CREDIT
+#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
+#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
+#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
+#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
+//MP0_SMN_IH_SW_INT
+#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x0
+#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x1
+#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000001L
+#define MP0_SMN_IH_SW_INT__ID_MASK 0x000001FEL
+//MP0_SMN_IH_SW_INT_CTRL
+#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0
+#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8
+#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L
+#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L
+
+
+// addressBlock: mp_SmuMp1_SmnDec
+//MP1_SMN_ACP2MP_RESP
+#define MP1_SMN_ACP2MP_RESP__CONTENT__SHIFT 0x0
+#define MP1_SMN_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_DC2MP_RESP
+#define MP1_SMN_DC2MP_RESP__CONTENT__SHIFT 0x0
+#define MP1_SMN_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_UVD2MP_RESP
+#define MP1_SMN_UVD2MP_RESP__CONTENT__SHIFT 0x0
+#define MP1_SMN_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_VCE2MP_RESP
+#define MP1_SMN_VCE2MP_RESP__CONTENT__SHIFT 0x0
+#define MP1_SMN_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_RLC2MP_RESP
+#define MP1_SMN_RLC2MP_RESP__CONTENT__SHIFT 0x0
+#define MP1_SMN_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_32
+#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_33
+#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_34
+#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_35
+#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_36
+#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_37
+#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_38
+#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_39
+#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_40
+#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_41
+#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_42
+#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_43
+#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_44
+#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_45
+#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_46
+#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_47
+#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_48
+#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_49
+#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_50
+#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_51
+#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_52
+#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_53
+#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_54
+#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_55
+#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_56
+#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_57
+#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_58
+#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_59
+#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_60
+#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_61
+#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_62
+#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_63
+#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_64
+#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_65
+#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_66
+#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_67
+#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_68
+#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_69
+#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_70
+#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_71
+#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_72
+#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_73
+#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_74
+#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_75
+#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_76
+#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_77
+#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_78
+#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_79
+#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_80
+#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_81
+#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_82
+#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_83
+#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_84
+#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_85
+#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_86
+#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_87
+#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_88
+#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_89
+#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_90
+#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_91
+#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_92
+#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_93
+#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_94
+#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_95
+#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_96
+#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_97
+#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_98
+#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_99
+#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_100
+#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_101
+#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_102
+#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_103
+#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_ACTIVE_FCN_ID
+#define MP1_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define MP1_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define MP1_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
+#define MP1_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//MP1_SMN_IH_CREDIT
+#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
+#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
+#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
+#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
+//MP1_SMN_IH_SW_INT
+#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x0
+#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x1
+#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000001L
+#define MP1_SMN_IH_SW_INT__ID_MASK 0x000001FEL
+//MP1_SMN_IH_SW_INT_CTRL
+#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0
+#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8
+#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L
+#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L
+//MP1_SMN_FPS_CNT
+#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0
+#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH0
+#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH1
+#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH2
+#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH3
+#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH4
+#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH5
+#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH6
+#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH7
+#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH8
+#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL
+
+
+
+
+// addressBlock: mp_SmuMp0Pub_CruDec
+//MP0_SOC_INFO
+#define MP0_SOC_INFO__SOC_DIE_ID__SHIFT 0x0
+#define MP0_SOC_INFO__SOC_PKG_TYPE__SHIFT 0x2
+#define MP0_SOC_INFO__SOC_DIE_ID_MASK 0x00000003L
+#define MP0_SOC_INFO__SOC_PKG_TYPE_MASK 0x0000001CL
+//MP0_PUB_SCRATCH0
+#define MP0_PUB_SCRATCH0__DATA__SHIFT 0x0
+#define MP0_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL
+//MP0_PUB_SCRATCH1
+#define MP0_PUB_SCRATCH1__DATA__SHIFT 0x0
+#define MP0_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL
+//MP0_PUB_SCRATCH2
+#define MP0_PUB_SCRATCH2__DATA__SHIFT 0x0
+#define MP0_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL
+//MP0_PUB_SCRATCH3
+#define MP0_PUB_SCRATCH3__DATA__SHIFT 0x0
+#define MP0_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL
+//MP0_FW_INTF
+#define MP0_FW_INTF__SS_SECURE__SHIFT 0x13
+#define MP0_FW_INTF__SS_SECURE_MASK 0x00080000L
+//MP0_C2PMSG_0
+#define MP0_C2PMSG_0__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_1
+#define MP0_C2PMSG_1__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_2
+#define MP0_C2PMSG_2__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_3
+#define MP0_C2PMSG_3__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_4
+#define MP0_C2PMSG_4__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_5
+#define MP0_C2PMSG_5__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_6
+#define MP0_C2PMSG_6__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_7
+#define MP0_C2PMSG_7__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_8
+#define MP0_C2PMSG_8__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_9
+#define MP0_C2PMSG_9__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_10
+#define MP0_C2PMSG_10__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_11
+#define MP0_C2PMSG_11__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_12
+#define MP0_C2PMSG_12__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_13
+#define MP0_C2PMSG_13__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_14
+#define MP0_C2PMSG_14__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_15
+#define MP0_C2PMSG_15__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_16
+#define MP0_C2PMSG_16__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_17
+#define MP0_C2PMSG_17__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_18
+#define MP0_C2PMSG_18__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_19
+#define MP0_C2PMSG_19__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_20
+#define MP0_C2PMSG_20__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_21
+#define MP0_C2PMSG_21__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_22
+#define MP0_C2PMSG_22__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_23
+#define MP0_C2PMSG_23__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_24
+#define MP0_C2PMSG_24__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_25
+#define MP0_C2PMSG_25__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_26
+#define MP0_C2PMSG_26__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_27
+#define MP0_C2PMSG_27__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_28
+#define MP0_C2PMSG_28__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_29
+#define MP0_C2PMSG_29__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_30
+#define MP0_C2PMSG_30__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_31
+#define MP0_C2PMSG_31__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL
+//MP0_P2CMSG_0
+#define MP0_P2CMSG_0__CONTENT__SHIFT 0x0
+#define MP0_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL
+//MP0_P2CMSG_1
+#define MP0_P2CMSG_1__CONTENT__SHIFT 0x0
+#define MP0_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL
+//MP0_P2CMSG_2
+#define MP0_P2CMSG_2__CONTENT__SHIFT 0x0
+#define MP0_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL
+//MP0_P2CMSG_3
+#define MP0_P2CMSG_3__CONTENT__SHIFT 0x0
+#define MP0_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL
+//MP0_P2CMSG_INTEN
+#define MP0_P2CMSG_INTEN__INTEN__SHIFT 0x0
+#define MP0_P2CMSG_INTEN__INTEN_MASK 0x0000000FL
+//MP0_P2CMSG_INTSTS
+#define MP0_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0
+#define MP0_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1
+#define MP0_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2
+#define MP0_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3
+#define MP0_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L
+#define MP0_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L
+#define MP0_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L
+#define MP0_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L
+//MP0_C2PMSG_ATTR_0
+#define MP0_C2PMSG_ATTR_0__MSG_ATTR__SHIFT 0x0
+#define MP0_C2PMSG_ATTR_0__MSG_ATTR_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_ATTR_1
+#define MP0_C2PMSG_ATTR_1__MSG_ATTR__SHIFT 0x0
+#define MP0_C2PMSG_ATTR_1__MSG_ATTR_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_ATTR_2
+#define MP0_C2PMSG_ATTR_2__MSG_ATTR__SHIFT 0x0
+#define MP0_C2PMSG_ATTR_2__MSG_ATTR_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_ATTR_3
+#define MP0_C2PMSG_ATTR_3__MSG_ATTR__SHIFT 0x0
+#define MP0_C2PMSG_ATTR_3__MSG_ATTR_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_ATTR_4
+#define MP0_C2PMSG_ATTR_4__MSG_ATTR__SHIFT 0x0
+#define MP0_C2PMSG_ATTR_4__MSG_ATTR_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_ATTR_5
+#define MP0_C2PMSG_ATTR_5__MSG_ATTR__SHIFT 0x0
+#define MP0_C2PMSG_ATTR_5__MSG_ATTR_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_ATTR_6
+#define MP0_C2PMSG_ATTR_6__MSG_ATTR__SHIFT 0x0
+#define MP0_C2PMSG_ATTR_6__MSG_ATTR_MASK 0x0000FFFFL
+//MP0_P2CMSG_ATTR
+#define MP0_P2CMSG_ATTR__MSG_ATTR__SHIFT 0x0
+#define MP0_P2CMSG_ATTR__MSG_ATTR_MASK 0x000000FFL
+//MP0_P2SMSG_0
+#define MP0_P2SMSG_0__CONTENT__SHIFT 0x0
+#define MP0_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL
+//MP0_P2SMSG_1
+#define MP0_P2SMSG_1__CONTENT__SHIFT 0x0
+#define MP0_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL
+//MP0_P2SMSG_2
+#define MP0_P2SMSG_2__CONTENT__SHIFT 0x0
+#define MP0_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL
+//MP0_P2SMSG_3
+#define MP0_P2SMSG_3__CONTENT__SHIFT 0x0
+#define MP0_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL
+//MP0_P2SMSG_ATTR
+#define MP0_P2SMSG_ATTR__MSG_ATTR__SHIFT 0x0
+#define MP0_P2SMSG_ATTR__MSG_ATTR_MASK 0x000000FFL
+//MP0_S2PMSG_ATTR
+#define MP0_S2PMSG_ATTR__MSG_ATTR__SHIFT 0x0
+#define MP0_S2PMSG_ATTR__MSG_ATTR_MASK 0x00000003L
+//MP0_P2SMSG_INTSTS
+#define MP0_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0
+#define MP0_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1
+#define MP0_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2
+#define MP0_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3
+#define MP0_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L
+#define MP0_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L
+#define MP0_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L
+#define MP0_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L
+//MP0_S2PMSG_0
+#define MP0_S2PMSG_0__CONTENT__SHIFT 0x0
+#define MP0_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_32
+#define MP0_C2PMSG_32__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_33
+#define MP0_C2PMSG_33__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_34
+#define MP0_C2PMSG_34__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_35
+#define MP0_C2PMSG_35__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_36
+#define MP0_C2PMSG_36__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_37
+#define MP0_C2PMSG_37__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_38
+#define MP0_C2PMSG_38__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_39
+#define MP0_C2PMSG_39__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_40
+#define MP0_C2PMSG_40__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_41
+#define MP0_C2PMSG_41__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_42
+#define MP0_C2PMSG_42__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_43
+#define MP0_C2PMSG_43__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_44
+#define MP0_C2PMSG_44__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_45
+#define MP0_C2PMSG_45__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_46
+#define MP0_C2PMSG_46__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_47
+#define MP0_C2PMSG_47__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_48
+#define MP0_C2PMSG_48__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_49
+#define MP0_C2PMSG_49__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_50
+#define MP0_C2PMSG_50__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_51
+#define MP0_C2PMSG_51__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_52
+#define MP0_C2PMSG_52__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_53
+#define MP0_C2PMSG_53__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_54
+#define MP0_C2PMSG_54__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_55
+#define MP0_C2PMSG_55__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_56
+#define MP0_C2PMSG_56__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_57
+#define MP0_C2PMSG_57__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_58
+#define MP0_C2PMSG_58__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_59
+#define MP0_C2PMSG_59__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_60
+#define MP0_C2PMSG_60__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_61
+#define MP0_C2PMSG_61__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_62
+#define MP0_C2PMSG_62__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_63
+#define MP0_C2PMSG_63__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_64
+#define MP0_C2PMSG_64__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_65
+#define MP0_C2PMSG_65__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_66
+#define MP0_C2PMSG_66__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_67
+#define MP0_C2PMSG_67__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_68
+#define MP0_C2PMSG_68__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_69
+#define MP0_C2PMSG_69__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_70
+#define MP0_C2PMSG_70__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_71
+#define MP0_C2PMSG_71__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_72
+#define MP0_C2PMSG_72__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_73
+#define MP0_C2PMSG_73__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_74
+#define MP0_C2PMSG_74__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_75
+#define MP0_C2PMSG_75__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_76
+#define MP0_C2PMSG_76__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_77
+#define MP0_C2PMSG_77__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_78
+#define MP0_C2PMSG_78__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_79
+#define MP0_C2PMSG_79__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_80
+#define MP0_C2PMSG_80__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_81
+#define MP0_C2PMSG_81__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_82
+#define MP0_C2PMSG_82__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_83
+#define MP0_C2PMSG_83__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_84
+#define MP0_C2PMSG_84__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_85
+#define MP0_C2PMSG_85__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_86
+#define MP0_C2PMSG_86__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_87
+#define MP0_C2PMSG_87__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_88
+#define MP0_C2PMSG_88__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_89
+#define MP0_C2PMSG_89__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_90
+#define MP0_C2PMSG_90__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_91
+#define MP0_C2PMSG_91__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_92
+#define MP0_C2PMSG_92__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_93
+#define MP0_C2PMSG_93__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_94
+#define MP0_C2PMSG_94__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_95
+#define MP0_C2PMSG_95__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_96
+#define MP0_C2PMSG_96__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_97
+#define MP0_C2PMSG_97__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_98
+#define MP0_C2PMSG_98__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_99
+#define MP0_C2PMSG_99__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_100
+#define MP0_C2PMSG_100__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_101
+#define MP0_C2PMSG_101__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_102
+#define MP0_C2PMSG_102__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
+//MP0_C2PMSG_103
+#define MP0_C2PMSG_103__CONTENT__SHIFT 0x0
+#define MP0_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
+//MP0_ACTIVE_FCN_ID
+#define MP0_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define MP0_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define MP0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
+#define MP0_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//MP0_IH_CREDIT
+#define MP0_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
+#define MP0_IH_CREDIT__CLIENT_ID__SHIFT 0x10
+#define MP0_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
+#define MP0_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
+//MP0_IH_SW_INT
+#define MP0_IH_SW_INT__ID__SHIFT 0x0
+#define MP0_IH_SW_INT__VALID__SHIFT 0x8
+#define MP0_IH_SW_INT__ID_MASK 0x000000FFL
+#define MP0_IH_SW_INT__VALID_MASK 0x00000100L
+//MP0_IH_SW_INT_CTRL
+#define MP0_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
+#define MP0_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
+#define MP0_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
+#define MP0_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
+
+
+//CGTT_DRM_CLK_CTRL0
+#define CGTT_DRM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
+#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_DRM_CLK_CTRL0__DIV_ID__SHIFT 0xc
+#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0__SHIFT 0x15
+#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG__SHIFT 0x16
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_DRM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
+#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_DRM_CLK_CTRL0__DIV_ID_MASK 0x00007000L
+#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0_MASK 0x00200000L
+#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG_MASK 0x00400000L
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
+//DRM_LIGHT_SLEEP_CTRL
+#define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN__SHIFT 0x0
+#define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN_MASK 0x00000001L
+
+
+// addressBlock: mp_SmuMp1Pub_CruDec
+//MP1_SMN_PUB_CTRL
+#define MP1_SMN_PUB_CTRL__RESET__SHIFT 0x0
+#define MP1_SMN_PUB_CTRL__RESET_MASK 0x00000001L
+//MP1_FIRMWARE_FLAGS
+#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
+#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
+#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L
+#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL
+//MP1_PUB_SCRATCH0
+#define MP1_PUB_SCRATCH0__DATA__SHIFT 0x0
+#define MP1_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL
+//MP1_PUB_SCRATCH1
+#define MP1_PUB_SCRATCH1__DATA__SHIFT 0x0
+#define MP1_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL
+//MP1_PUB_SCRATCH2
+#define MP1_PUB_SCRATCH2__DATA__SHIFT 0x0
+#define MP1_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL
+//MP1_PUB_SCRATCH3
+#define MP1_PUB_SCRATCH3__DATA__SHIFT 0x0
+#define MP1_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_0
+#define MP1_C2PMSG_0__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_1
+#define MP1_C2PMSG_1__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_2
+#define MP1_C2PMSG_2__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_3
+#define MP1_C2PMSG_3__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_4
+#define MP1_C2PMSG_4__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_5
+#define MP1_C2PMSG_5__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_6
+#define MP1_C2PMSG_6__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_7
+#define MP1_C2PMSG_7__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_8
+#define MP1_C2PMSG_8__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_9
+#define MP1_C2PMSG_9__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_10
+#define MP1_C2PMSG_10__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_11
+#define MP1_C2PMSG_11__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_12
+#define MP1_C2PMSG_12__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_13
+#define MP1_C2PMSG_13__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_14
+#define MP1_C2PMSG_14__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_15
+#define MP1_C2PMSG_15__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_16
+#define MP1_C2PMSG_16__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_17
+#define MP1_C2PMSG_17__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_18
+#define MP1_C2PMSG_18__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_19
+#define MP1_C2PMSG_19__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_20
+#define MP1_C2PMSG_20__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_21
+#define MP1_C2PMSG_21__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_22
+#define MP1_C2PMSG_22__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_23
+#define MP1_C2PMSG_23__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_24
+#define MP1_C2PMSG_24__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_25
+#define MP1_C2PMSG_25__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_26
+#define MP1_C2PMSG_26__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_27
+#define MP1_C2PMSG_27__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_28
+#define MP1_C2PMSG_28__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_29
+#define MP1_C2PMSG_29__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_30
+#define MP1_C2PMSG_30__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_31
+#define MP1_C2PMSG_31__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2CMSG_0
+#define MP1_P2CMSG_0__CONTENT__SHIFT 0x0
+#define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2CMSG_1
+#define MP1_P2CMSG_1__CONTENT__SHIFT 0x0
+#define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2CMSG_2
+#define MP1_P2CMSG_2__CONTENT__SHIFT 0x0
+#define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2CMSG_3
+#define MP1_P2CMSG_3__CONTENT__SHIFT 0x0
+#define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2CMSG_INTEN
+#define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0
+#define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL
+//MP1_P2CMSG_INTSTS
+#define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0
+#define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1
+#define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2
+#define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3
+#define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L
+#define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L
+#define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L
+#define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L
+//MP1_P2SMSG_0
+#define MP1_P2SMSG_0__CONTENT__SHIFT 0x0
+#define MP1_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2SMSG_1
+#define MP1_P2SMSG_1__CONTENT__SHIFT 0x0
+#define MP1_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2SMSG_2
+#define MP1_P2SMSG_2__CONTENT__SHIFT 0x0
+#define MP1_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2SMSG_3
+#define MP1_P2SMSG_3__CONTENT__SHIFT 0x0
+#define MP1_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2SMSG_INTSTS
+#define MP1_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0
+#define MP1_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1
+#define MP1_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2
+#define MP1_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3
+#define MP1_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L
+#define MP1_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L
+#define MP1_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L
+#define MP1_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L
+//MP1_S2PMSG_0
+#define MP1_S2PMSG_0__CONTENT__SHIFT 0x0
+#define MP1_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
+//MP1_ACP2MP_RESP
+#define MP1_ACP2MP_RESP__CONTENT__SHIFT 0x0
+#define MP1_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
+//MP1_DC2MP_RESP
+#define MP1_DC2MP_RESP__CONTENT__SHIFT 0x0
+#define MP1_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
+//MP1_UVD2MP_RESP
+#define MP1_UVD2MP_RESP__CONTENT__SHIFT 0x0
+#define MP1_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
+//MP1_VCE2MP_RESP
+#define MP1_VCE2MP_RESP__CONTENT__SHIFT 0x0
+#define MP1_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
+//MP1_RLC2MP_RESP
+#define MP1_RLC2MP_RESP__CONTENT__SHIFT 0x0
+#define MP1_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_32
+#define MP1_C2PMSG_32__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_33
+#define MP1_C2PMSG_33__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_34
+#define MP1_C2PMSG_34__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_35
+#define MP1_C2PMSG_35__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_36
+#define MP1_C2PMSG_36__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_37
+#define MP1_C2PMSG_37__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_38
+#define MP1_C2PMSG_38__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_39
+#define MP1_C2PMSG_39__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_40
+#define MP1_C2PMSG_40__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_41
+#define MP1_C2PMSG_41__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_42
+#define MP1_C2PMSG_42__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_43
+#define MP1_C2PMSG_43__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_44
+#define MP1_C2PMSG_44__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_45
+#define MP1_C2PMSG_45__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_46
+#define MP1_C2PMSG_46__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_47
+#define MP1_C2PMSG_47__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_48
+#define MP1_C2PMSG_48__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_49
+#define MP1_C2PMSG_49__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_50
+#define MP1_C2PMSG_50__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_51
+#define MP1_C2PMSG_51__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_52
+#define MP1_C2PMSG_52__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_53
+#define MP1_C2PMSG_53__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_54
+#define MP1_C2PMSG_54__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_55
+#define MP1_C2PMSG_55__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_56
+#define MP1_C2PMSG_56__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_57
+#define MP1_C2PMSG_57__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_58
+#define MP1_C2PMSG_58__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_59
+#define MP1_C2PMSG_59__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_60
+#define MP1_C2PMSG_60__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_61
+#define MP1_C2PMSG_61__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_62
+#define MP1_C2PMSG_62__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_63
+#define MP1_C2PMSG_63__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_64
+#define MP1_C2PMSG_64__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_65
+#define MP1_C2PMSG_65__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_66
+#define MP1_C2PMSG_66__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_67
+#define MP1_C2PMSG_67__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_68
+#define MP1_C2PMSG_68__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_69
+#define MP1_C2PMSG_69__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_70
+#define MP1_C2PMSG_70__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_71
+#define MP1_C2PMSG_71__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_72
+#define MP1_C2PMSG_72__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_73
+#define MP1_C2PMSG_73__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_74
+#define MP1_C2PMSG_74__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_75
+#define MP1_C2PMSG_75__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_76
+#define MP1_C2PMSG_76__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_77
+#define MP1_C2PMSG_77__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_78
+#define MP1_C2PMSG_78__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_79
+#define MP1_C2PMSG_79__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_80
+#define MP1_C2PMSG_80__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_81
+#define MP1_C2PMSG_81__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_82
+#define MP1_C2PMSG_82__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_83
+#define MP1_C2PMSG_83__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_84
+#define MP1_C2PMSG_84__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_85
+#define MP1_C2PMSG_85__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_86
+#define MP1_C2PMSG_86__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_87
+#define MP1_C2PMSG_87__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_88
+#define MP1_C2PMSG_88__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_89
+#define MP1_C2PMSG_89__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_90
+#define MP1_C2PMSG_90__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_91
+#define MP1_C2PMSG_91__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_92
+#define MP1_C2PMSG_92__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_93
+#define MP1_C2PMSG_93__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_94
+#define MP1_C2PMSG_94__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_95
+#define MP1_C2PMSG_95__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_96
+#define MP1_C2PMSG_96__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_97
+#define MP1_C2PMSG_97__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_98
+#define MP1_C2PMSG_98__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_99
+#define MP1_C2PMSG_99__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_100
+#define MP1_C2PMSG_100__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_101
+#define MP1_C2PMSG_101__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_102
+#define MP1_C2PMSG_102__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_103
+#define MP1_C2PMSG_103__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
+//MP1_ACTIVE_FCN_ID
+#define MP1_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define MP1_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define MP1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
+#define MP1_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//MP1_IH_CREDIT
+#define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
+#define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10
+#define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
+#define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
+//MP1_IH_SW_INT
+#define MP1_IH_SW_INT__ID__SHIFT 0x0
+#define MP1_IH_SW_INT__VALID__SHIFT 0x8
+#define MP1_IH_SW_INT__ID_MASK 0x000000FFL
+#define MP1_IH_SW_INT__VALID_MASK 0x00000100L
+//MP1_IH_SW_INT_CTRL
+#define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
+#define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
+#define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
+#define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
+//MP1_FPS_CNT
+#define MP1_FPS_CNT__COUNT__SHIFT 0x0
+#define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
+//MP1_PUB_CTRL
+#define MP1_PUB_CTRL__RESET__SHIFT 0x0
+#define MP1_PUB_CTRL__RESET_MASK 0x00000001L
+//MP1_EXT_SCRATCH0
+#define MP1_EXT_SCRATCH0__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
+//MP1_EXT_SCRATCH1
+#define MP1_EXT_SCRATCH1__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
+//MP1_EXT_SCRATCH2
+#define MP1_EXT_SCRATCH2__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
+//MP1_EXT_SCRATCH3
+#define MP1_EXT_SCRATCH3__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
+//MP1_EXT_SCRATCH4
+#define MP1_EXT_SCRATCH4__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
+//MP1_EXT_SCRATCH5
+#define MP1_EXT_SCRATCH5__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
+//MP1_EXT_SCRATCH6
+#define MP1_EXT_SCRATCH6__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
+//MP1_EXT_SCRATCH7
+#define MP1_EXT_SCRATCH7__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h
new file mode 100644
index 000000000000..daa7eaef01b8
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h
@@ -0,0 +1,1271 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _nbif_6_1_DEFAULT_HEADER
+#define _nbif_6_1_DEFAULT_HEADER
+
+
+// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp
+// base address: 0x0
+#define cfgVENDOR_ID_DEFAULT 0x00000000
+#define cfgDEVICE_ID_DEFAULT 0x00000000
+#define cfgCOMMAND_DEFAULT 0x00000000
+#define cfgSTATUS_DEFAULT 0x00000000
+#define cfgREVISION_ID_DEFAULT 0x00000000
+#define cfgPROG_INTERFACE_DEFAULT 0x00000000
+#define cfgSUB_CLASS_DEFAULT 0x00000000
+#define cfgBASE_CLASS_DEFAULT 0x00000000
+#define cfgCACHE_LINE_DEFAULT 0x00000000
+#define cfgLATENCY_DEFAULT 0x00000000
+#define cfgHEADER_DEFAULT 0x00000000
+#define cfgBIST_DEFAULT 0x00000000
+#define cfgBASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBASE_ADDR_6_DEFAULT 0x00000000
+#define cfgADAPTER_ID_DEFAULT 0x00000000
+#define cfgROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgCAP_PTR_DEFAULT 0x00000000
+#define cfgINTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgINTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgMIN_GRANT_DEFAULT 0x00000000
+#define cfgMAX_LATENCY_DEFAULT 0x00000000
+#define cfgVENDOR_CAP_LIST_DEFAULT 0x00000000
+#define cfgADAPTER_ID_W_DEFAULT 0x00000000
+#define cfgPMI_CAP_LIST_DEFAULT 0x00000000
+#define cfgPMI_CAP_DEFAULT 0x00000000
+#define cfgPMI_STATUS_CNTL_DEFAULT 0x00000000
+#define cfgPCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgPCIE_CAP_DEFAULT 0x00000002
+#define cfgDEVICE_CAP_DEFAULT 0x10000000
+#define cfgDEVICE_CNTL_DEFAULT 0x00002810
+#define cfgDEVICE_STATUS_DEFAULT 0x00000000
+#define cfgLINK_CAP_DEFAULT 0x00011c03
+#define cfgLINK_CNTL_DEFAULT 0x00000000
+#define cfgLINK_STATUS_DEFAULT 0x00000001
+#define cfgDEVICE_CAP2_DEFAULT 0x00000000
+#define cfgDEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgDEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgLINK_CAP2_DEFAULT 0x0000000e
+#define cfgLINK_CNTL2_DEFAULT 0x00000003
+#define cfgLINK_STATUS2_DEFAULT 0x00000000
+#define cfgSLOT_CAP2_DEFAULT 0x00000000
+#define cfgSLOT_CNTL2_DEFAULT 0x00000000
+#define cfgSLOT_STATUS2_DEFAULT 0x00000000
+#define cfgMSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgMSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgMSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgMSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgMSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgMSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgMSI_MASK_DEFAULT 0x00000000
+#define cfgMSI_PENDING_DEFAULT 0x00000000
+#define cfgMSI_MASK_64_DEFAULT 0x00000000
+#define cfgMSI_PENDING_64_DEFAULT 0x00000000
+#define cfgMSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgMSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgMSIX_TABLE_DEFAULT 0x00000000
+#define cfgMSIX_PBA_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgPCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
+#define cfgPCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
+#define cfgPCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
+#define cfgPCIE_PORT_VC_CNTL_DEFAULT 0x00000000
+#define cfgPCIE_PORT_VC_STATUS_DEFAULT 0x00000000
+#define cfgPCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgPCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
+#define cfgPCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002
+#define cfgPCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgPCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
+#define cfgPCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002
+#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
+#define cfgPCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
+#define cfgPCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
+#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgPCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgPCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgPCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgPCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgPCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define cfgPCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgPCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgPCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgPCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgPCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgPCIE_ROOT_ERR_CMD_DEFAULT 0x00000000
+#define cfgPCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000
+#define cfgPCIE_ERR_SRC_ID_DEFAULT 0x00000000
+#define cfgPCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgPCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgPCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgPCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgPCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
+#define cfgPCIE_BAR1_CAP_DEFAULT 0x00000000
+#define cfgPCIE_BAR1_CNTL_DEFAULT 0x00000020
+#define cfgPCIE_BAR2_CAP_DEFAULT 0x00000000
+#define cfgPCIE_BAR2_CNTL_DEFAULT 0x00000000
+#define cfgPCIE_BAR3_CAP_DEFAULT 0x00000000
+#define cfgPCIE_BAR3_CNTL_DEFAULT 0x00000000
+#define cfgPCIE_BAR4_CAP_DEFAULT 0x00000000
+#define cfgPCIE_BAR4_CNTL_DEFAULT 0x00000000
+#define cfgPCIE_BAR5_CAP_DEFAULT 0x00000000
+#define cfgPCIE_BAR5_CNTL_DEFAULT 0x00000000
+#define cfgPCIE_BAR6_CAP_DEFAULT 0x00000000
+#define cfgPCIE_BAR6_CNTL_DEFAULT 0x00000000
+#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
+#define cfgPCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
+#define cfgPCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
+#define cfgPCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
+#define cfgPCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
+#define cfgPCIE_DPA_CAP_DEFAULT 0x00000000
+#define cfgPCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
+#define cfgPCIE_DPA_STATUS_DEFAULT 0x00000100
+#define cfgPCIE_DPA_CNTL_DEFAULT 0x00000000
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
+#define cfgPCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019
+#define cfgPCIE_LINK_CNTL3_DEFAULT 0x00000000
+#define cfgPCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
+#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgPCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
+#define cfgPCIE_ACS_CAP_DEFAULT 0x00000000
+#define cfgPCIE_ACS_CNTL_DEFAULT 0x00000000
+#define cfgPCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgPCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgPCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000
+#define cfgPCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
+#define cfgPCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000
+#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000
+#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
+#define cfgPCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000
+#define cfgPCIE_PASID_CAP_DEFAULT 0x00000000
+#define cfgPCIE_PASID_CNTL_DEFAULT 0x00000000
+#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define cfgPCIE_TPH_REQR_CAP_DEFAULT 0x00000000
+#define cfgPCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
+#define cfgPCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
+#define cfgPCIE_MC_CAP_DEFAULT 0x00000000
+#define cfgPCIE_MC_CNTL_DEFAULT 0x00000000
+#define cfgPCIE_MC_ADDR0_DEFAULT 0x00000000
+#define cfgPCIE_MC_ADDR1_DEFAULT 0x00000000
+#define cfgPCIE_MC_RCV0_DEFAULT 0x00000000
+#define cfgPCIE_MC_RCV1_DEFAULT 0x00000000
+#define cfgPCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
+#define cfgPCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
+#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
+#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
+#define cfgPCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
+#define cfgPCIE_LTR_CAP_DEFAULT 0x00000000
+#define cfgPCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgPCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgPCIE_ARI_CNTL_DEFAULT 0x00000000
+#define cfgPCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgPCIE_SRIOV_CAP_DEFAULT 0x00000000
+#define cfgPCIE_SRIOV_CONTROL_DEFAULT 0x00000000
+#define cfgPCIE_SRIOV_STATUS_DEFAULT 0x00000000
+#define cfgPCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000
+#define cfgPCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000
+#define cfgPCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000
+#define cfgPCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000
+#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000
+#define cfgPCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000
+#define cfgPCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000
+#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000
+#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001
+#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000
+#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000
+
+
+// addressBlock: bif_cfg_dev0_swds_bifcfgdecp
+// base address: 0x0
+#define mmSUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
+#define mmIO_BASE_LIMIT_DEFAULT 0x00000000
+#define mmSECONDARY_STATUS_DEFAULT 0x00000000
+#define mmMEM_BASE_LIMIT_DEFAULT 0x00000000
+#define mmPREF_BASE_LIMIT_DEFAULT 0x00000000
+#define mmPREF_BASE_UPPER_DEFAULT 0x00000000
+#define mmPREF_LIMIT_UPPER_DEFAULT 0x00000000
+#define mmIO_BASE_LIMIT_HI_DEFAULT 0x00000000
+#define mmIRQ_BRIDGE_CNTL_DEFAULT 0x00000000
+#define mmSLOT_CAP_DEFAULT 0x00000000
+#define mmSLOT_CNTL_DEFAULT 0x00000000
+#define mmSLOT_STATUS_DEFAULT 0x00000000
+#define mmSSID_CAP_LIST_DEFAULT 0x00000000
+#define mmSSID_CAP_DEFAULT 0x00000000
+
+
+// addressBlock: rcc_shadow_reg_shadowdec
+// base address: 0x0
+#define ixSHADOW_COMMAND_DEFAULT 0x00000000
+#define ixSHADOW_BASE_ADDR_1_DEFAULT 0x00000000
+#define ixSHADOW_BASE_ADDR_2_DEFAULT 0x00000000
+#define ixSHADOW_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
+#define ixSHADOW_IO_BASE_LIMIT_DEFAULT 0x00000000
+#define ixSHADOW_MEM_BASE_LIMIT_DEFAULT 0x00000000
+#define ixSHADOW_PREF_BASE_LIMIT_DEFAULT 0x00000000
+#define ixSHADOW_PREF_BASE_UPPER_DEFAULT 0x00000000
+#define ixSHADOW_PREF_LIMIT_UPPER_DEFAULT 0x00000000
+#define ixSHADOW_IO_BASE_LIMIT_HI_DEFAULT 0x00000000
+#define ixSHADOW_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000
+#define ixSUC_INDEX_DEFAULT 0x00000000
+#define ixSUC_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: bif_bx_pf_SUMDEC
+// base address: 0x0
+#define ixSUM_INDEX_DEFAULT 0x00000000
+#define ixSUM_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: gdc_GDCDEC
+// base address: 0x1400000
+#define mmA2S_CNTL_CL0_DEFAULT 0x00280540
+#define mmA2S_CNTL_CL1_DEFAULT 0x00282540
+#define mmA2S_CNTL_CL2_DEFAULT 0x002825a0
+#define mmA2S_CNTL_CL3_DEFAULT 0x00282550
+#define mmA2S_CNTL_CL4_DEFAULT 0x00282550
+#define mmA2S_CNTL_SW0_DEFAULT 0x08080005
+#define mmA2S_CNTL_SW1_DEFAULT 0x08080205
+#define mmA2S_CNTL_SW2_DEFAULT 0x08080200
+#define mmNGDC_MGCG_CTRL_DEFAULT 0x00000080
+#define mmA2S_MISC_CNTL_DEFAULT 0x00000003
+#define mmNGDC_SDP_PORT_CTRL_DEFAULT 0x0000000f
+#define mmNGDC_RESERVED_0_DEFAULT 0x00000000
+#define mmNGDC_RESERVED_1_DEFAULT 0x00000000
+#define mmBIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000
+#define mmBIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000
+#define mmBIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000
+#define mmBIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000
+#define mmBIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000
+#define mmS2A_MISC_CNTL_DEFAULT 0x00000000
+#define mmA2S_CNTL2_SEC_CL0_DEFAULT 0x00000006
+#define mmA2S_CNTL2_SEC_CL1_DEFAULT 0x00000006
+#define mmA2S_CNTL2_SEC_CL2_DEFAULT 0x00000006
+#define mmA2S_CNTL2_SEC_CL3_DEFAULT 0x00000006
+#define mmA2S_CNTL2_SEC_CL4_DEFAULT 0x00000006
+
+
+// addressBlock: nbif_sion_SIONDEC
+// base address: 0x1400000
+#define ixSION_CL0_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define ixSION_CL0_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define ixSION_CL0_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define ixSION_CL0_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define ixSION_CL0_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define ixSION_CL0_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define ixSION_CL0_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define ixSION_CL0_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define ixSION_CL0_Req_BurstTarget_REG0_DEFAULT 0x00000000
+#define ixSION_CL0_Req_BurstTarget_REG1_DEFAULT 0x00000000
+#define ixSION_CL0_Req_TimeSlot_REG0_DEFAULT 0x00000000
+#define ixSION_CL0_Req_TimeSlot_REG1_DEFAULT 0x00000000
+#define ixSION_CL0_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL0_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL0_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL0_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL0_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL0_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL0_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL0_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL1_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define ixSION_CL1_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define ixSION_CL1_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define ixSION_CL1_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define ixSION_CL1_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define ixSION_CL1_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define ixSION_CL1_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define ixSION_CL1_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define ixSION_CL1_Req_BurstTarget_REG0_DEFAULT 0x00000000
+#define ixSION_CL1_Req_BurstTarget_REG1_DEFAULT 0x00000000
+#define ixSION_CL1_Req_TimeSlot_REG0_DEFAULT 0x00000000
+#define ixSION_CL1_Req_TimeSlot_REG1_DEFAULT 0x00000000
+#define ixSION_CL1_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL1_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL1_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL1_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL1_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL1_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL1_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL1_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL2_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define ixSION_CL2_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define ixSION_CL2_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define ixSION_CL2_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define ixSION_CL2_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define ixSION_CL2_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define ixSION_CL2_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define ixSION_CL2_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define ixSION_CL2_Req_BurstTarget_REG0_DEFAULT 0x00000000
+#define ixSION_CL2_Req_BurstTarget_REG1_DEFAULT 0x00000000
+#define ixSION_CL2_Req_TimeSlot_REG0_DEFAULT 0x00000000
+#define ixSION_CL2_Req_TimeSlot_REG1_DEFAULT 0x00000000
+#define ixSION_CL2_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL2_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL2_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL2_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL2_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL2_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL2_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL2_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL3_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define ixSION_CL3_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define ixSION_CL3_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define ixSION_CL3_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define ixSION_CL3_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define ixSION_CL3_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define ixSION_CL3_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define ixSION_CL3_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define ixSION_CL3_Req_BurstTarget_REG0_DEFAULT 0x00000000
+#define ixSION_CL3_Req_BurstTarget_REG1_DEFAULT 0x00000000
+#define ixSION_CL3_Req_TimeSlot_REG0_DEFAULT 0x00000000
+#define ixSION_CL3_Req_TimeSlot_REG1_DEFAULT 0x00000000
+#define ixSION_CL3_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL3_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL3_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL3_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL3_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL3_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL3_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL3_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL4_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define ixSION_CL4_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define ixSION_CL4_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define ixSION_CL4_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define ixSION_CL4_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define ixSION_CL4_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define ixSION_CL4_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define ixSION_CL4_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define ixSION_CL4_Req_BurstTarget_REG0_DEFAULT 0x00000000
+#define ixSION_CL4_Req_BurstTarget_REG1_DEFAULT 0x00000000
+#define ixSION_CL4_Req_TimeSlot_REG0_DEFAULT 0x00000000
+#define ixSION_CL4_Req_TimeSlot_REG1_DEFAULT 0x00000000
+#define ixSION_CL4_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL4_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL4_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL4_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL4_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL4_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL4_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL4_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL5_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define ixSION_CL5_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define ixSION_CL5_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define ixSION_CL5_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define ixSION_CL5_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define ixSION_CL5_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define ixSION_CL5_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define ixSION_CL5_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define ixSION_CL5_Req_BurstTarget_REG0_DEFAULT 0x00000000
+#define ixSION_CL5_Req_BurstTarget_REG1_DEFAULT 0x00000000
+#define ixSION_CL5_Req_TimeSlot_REG0_DEFAULT 0x00000000
+#define ixSION_CL5_Req_TimeSlot_REG1_DEFAULT 0x00000000
+#define ixSION_CL5_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL5_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL5_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL5_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL5_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL5_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CL5_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define ixSION_CL5_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define ixSION_CNTL_REG0_DEFAULT 0x00000000
+#define ixSION_CNTL_REG1_DEFAULT 0x00000000
+
+
+// addressBlock: syshub_mmreg_direct_syshubdirect
+// base address: 0x1400000
+#define ixSYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000
+#define ixSYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100
+#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000
+#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000
+#define ixDMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
+#define ixDMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
+#define ixDMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000
+#define ixDMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000
+#define ixDMA_CLK0_SW0_CL2_CNTL_DEFAULT 0x20200000
+#define ixDMA_CLK0_SW0_CL3_CNTL_DEFAULT 0x20200000
+#define ixDMA_CLK0_SW0_CL4_CNTL_DEFAULT 0x20200000
+#define ixDMA_CLK0_SW0_CL5_CNTL_DEFAULT 0x20200000
+#define ixDMA_CLK0_SW1_CL0_CNTL_DEFAULT 0x20200000
+#define ixDMA_CLK0_SW2_CL0_CNTL_DEFAULT 0x20200000
+#define ixSYSHUB_CG_CNTL_DEFAULT 0x00082000
+#define ixSYSHUB_TRANS_IDLE_DEFAULT 0x00000000
+#define ixSYSHUB_HP_TIMER_DEFAULT 0x00000100
+#define ixSYSHUB_SCRATCH_DEFAULT 0x00000040
+#define ixSYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000
+#define ixSYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100
+#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000
+#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000
+#define ixDMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
+#define ixDMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
+#define ixDMA_CLK1_SW0_CL0_CNTL_DEFAULT 0x20200000
+#define ixDMA_CLK1_SW0_CL1_CNTL_DEFAULT 0x20200000
+#define ixDMA_CLK1_SW0_CL2_CNTL_DEFAULT 0x20200000
+#define ixDMA_CLK1_SW0_CL3_CNTL_DEFAULT 0x20200000
+#define ixDMA_CLK1_SW0_CL4_CNTL_DEFAULT 0x20200000
+#define ixDMA_CLK1_SW1_CL0_CNTL_DEFAULT 0x20200000
+#define ixDMA_CLK1_SW1_CL1_CNTL_DEFAULT 0x20200000
+#define ixDMA_CLK1_SW1_CL2_CNTL_DEFAULT 0x20200000
+#define ixDMA_CLK1_SW1_CL3_CNTL_DEFAULT 0x20200000
+#define ixDMA_CLK1_SW1_CL4_CNTL_DEFAULT 0x20200000
+
+
+// addressBlock: gdc_ras_gdc_ras_regblk
+// base address: 0x1400000
+#define ixGDC_RAS_LEAF0_CTRL_DEFAULT 0x00000000
+#define ixGDC_RAS_LEAF1_CTRL_DEFAULT 0x00000000
+#define ixGDC_RAS_LEAF2_CTRL_DEFAULT 0x00000000
+#define ixGDC_RAS_LEAF3_CTRL_DEFAULT 0x00000000
+#define ixGDC_RAS_LEAF4_CTRL_DEFAULT 0x00000000
+#define ixGDC_RAS_LEAF5_CTRL_DEFAULT 0x00000000
+
+
+// addressBlock: gdc_rst_GDCRST_DEC
+// base address: 0x1400000
+#define ixSHUB_PF_FLR_RST_DEFAULT 0x00000000
+#define ixSHUB_GFX_DRV_MODE1_RST_DEFAULT 0x00000000
+#define ixSHUB_LINK_RESET_DEFAULT 0x00000000
+#define ixSHUB_PF0_VF_FLR_RST_DEFAULT 0x00000000
+#define ixSHUB_HARD_RST_CTRL_DEFAULT 0x0000001b
+#define ixSHUB_SOFT_RST_CTRL_DEFAULT 0x00000009
+#define ixSHUB_SDP_PORT_RST_DEFAULT 0x00000000
+
+
+// addressBlock: bif_bx_pf_SYSDEC
+// base address: 0x0
+#define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000
+#define mmSBIOS_SCRATCH_1_DEFAULT 0x00000000
+#define mmSBIOS_SCRATCH_2_DEFAULT 0x00000000
+#define mmSBIOS_SCRATCH_3_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_0_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_1_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_2_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_3_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_4_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_5_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_6_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_7_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_8_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_9_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_10_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_11_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_12_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_13_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_14_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_15_DEFAULT 0x00000000
+#define mmBIF_RLC_INTR_CNTL_DEFAULT 0x00000000
+#define mmBIF_VCE_INTR_CNTL_DEFAULT 0x00000000
+#define mmBIF_UVD_INTR_CNTL_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000
+
+
+// addressBlock: bif_bx_pf_SYSPFVFDEC
+// base address: 0x0
+#define mmMM_INDEX_DEFAULT 0x00000000
+#define mmMM_DATA_DEFAULT 0x00000000
+#define mmMM_INDEX_HI_DEFAULT 0x00000000
+#define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000
+#define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000
+#define mmPCIE_INDEX_DEFAULT 0x00000000
+#define mmPCIE_DATA_DEFAULT 0x00000000
+#define mmPCIE_INDEX2_DEFAULT 0x00000000
+#define mmPCIE_DATA2_DEFAULT 0x00000000
+
+
+// addressBlock: rcc_dwn_BIFDEC1
+// base address: 0x0
+#define mmDN_PCIE_RESERVED_DEFAULT 0x00000000
+#define mmDN_PCIE_SCRATCH_DEFAULT 0x00000000
+#define mmDN_PCIE_CNTL_DEFAULT 0x00000000
+#define mmDN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000
+#define mmDN_PCIE_RX_CNTL2_DEFAULT 0x00000000
+#define mmDN_PCIE_BUS_CNTL_DEFAULT 0x00000080
+#define mmDN_PCIE_CFG_CNTL_DEFAULT 0x00000000
+#define mmDN_PCIE_STRAP_F0_DEFAULT 0x00000001
+#define mmDN_PCIE_STRAP_MISC_DEFAULT 0x00000000
+#define mmDN_PCIE_STRAP_MISC2_DEFAULT 0x00000000
+
+
+// addressBlock: rcc_dwnp_BIFDEC1
+// base address: 0x0
+#define mmPCIEP_RESERVED_DEFAULT 0x00000000
+#define mmPCIEP_SCRATCH_DEFAULT 0x00000000
+#define mmPCIE_ERR_CNTL_DEFAULT 0x00000500
+#define mmPCIE_RX_CNTL_DEFAULT 0x00000000
+#define mmPCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
+#define mmPCIE_LC_CNTL2_DEFAULT 0x00000000
+#define mmPCIEP_STRAP_MISC_DEFAULT 0x00000000
+#define mmLTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000
+
+
+// addressBlock: rcc_ep_BIFDEC1
+// base address: 0x0
+#define mmEP_PCIE_SCRATCH_DEFAULT 0x00000000
+#define mmEP_PCIE_CNTL_DEFAULT 0x00000100
+#define mmEP_PCIE_INT_CNTL_DEFAULT 0x00000000
+#define mmEP_PCIE_INT_STATUS_DEFAULT 0x00000000
+#define mmEP_PCIE_RX_CNTL2_DEFAULT 0x00000000
+#define mmEP_PCIE_BUS_CNTL_DEFAULT 0x00000080
+#define mmEP_PCIE_CFG_CNTL_DEFAULT 0x00000000
+#define mmEP_PCIE_OBFF_CNTL_DEFAULT 0x00012774
+#define mmEP_PCIE_TX_LTR_CNTL_DEFAULT 0x00003468
+#define mmEP_PCIE_STRAP_MISC_DEFAULT 0x00000000
+#define mmEP_PCIE_STRAP_MISC2_DEFAULT 0x00000000
+#define mmEP_PCIE_STRAP_PI_DEFAULT 0x00000000
+#define mmEP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000
+#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0
+#define mmEP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a
+#define mmEP_PCIE_PME_CONTROL_DEFAULT 0x00000000
+#define mmEP_PCIEP_RESERVED_DEFAULT 0x00000000
+#define mmEP_PCIE_TX_CNTL_DEFAULT 0x00000000
+#define mmEP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000
+#define mmEP_PCIE_ERR_CNTL_DEFAULT 0x00000500
+#define mmEP_PCIE_RX_CNTL_DEFAULT 0x01000000
+#define mmEP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: bif_bx_pf_BIFDEC1
+// base address: 0x0
+#define mmBIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000
+#define mmBUS_CNTL_DEFAULT 0x00000000
+#define mmBIF_SCRATCH0_DEFAULT 0x00000000
+#define mmBIF_SCRATCH1_DEFAULT 0x00000000
+#define mmBX_RESET_EN_DEFAULT 0x00010003
+#define mmMM_CFGREGS_CNTL_DEFAULT 0x00000000
+#define mmBX_RESET_CNTL_DEFAULT 0x00000000
+#define mmINTERRUPT_CNTL_DEFAULT 0x00000010
+#define mmINTERRUPT_CNTL2_DEFAULT 0x00000000
+#define mmCLKREQB_PAD_CNTL_DEFAULT 0x000008e0
+#define mmCLKREQB_PERF_COUNTER_DEFAULT 0x00000000
+#define mmBIF_CLK_CTRL_DEFAULT 0x00000000
+#define mmBIF_FEATURES_CONTROL_MISC_DEFAULT 0x00000000
+#define mmBIF_DOORBELL_CNTL_DEFAULT 0x00000000
+#define mmBIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_SLVARB_MODE_DEFAULT 0x00000000
+#define mmBIF_FB_EN_DEFAULT 0x00000000
+#define mmBIF_BUSY_DELAY_CNTR_DEFAULT 0x0000003f
+#define mmBIF_PERFMON_CNTL_DEFAULT 0x00000000
+#define mmBIF_PERFCOUNTER0_RESULT_DEFAULT 0x00000000
+#define mmBIF_PERFCOUNTER1_RESULT_DEFAULT 0x00000000
+#define mmBIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000
+#define mmBIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000
+#define mmBACO_CNTL_DEFAULT 0x00000000
+#define mmBIF_BACO_EXIT_TIME0_DEFAULT 0x00000100
+#define mmBIF_BACO_EXIT_TIMER1_DEFAULT 0x00000100
+#define mmBIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300
+#define mmBIF_BACO_EXIT_TIMER3_DEFAULT 0x00000400
+#define mmBIF_BACO_EXIT_TIMER4_DEFAULT 0x00000100
+#define mmMEM_TYPE_CNTL_DEFAULT 0x00000000
+#define mmSMU_BIF_VDDGFX_PWR_STATUS_DEFAULT 0x00000000
+#define mmBIF_VDDGFX_GFX0_LOWER_DEFAULT 0xc0008000
+#define mmBIF_VDDGFX_GFX0_UPPER_DEFAULT 0x0000cffc
+#define mmBIF_VDDGFX_GFX1_LOWER_DEFAULT 0xc0028000
+#define mmBIF_VDDGFX_GFX1_UPPER_DEFAULT 0x00031ffc
+#define mmBIF_VDDGFX_GFX2_LOWER_DEFAULT 0xc0034000
+#define mmBIF_VDDGFX_GFX2_UPPER_DEFAULT 0x00037ffc
+#define mmBIF_VDDGFX_GFX3_LOWER_DEFAULT 0xc003c000
+#define mmBIF_VDDGFX_GFX3_UPPER_DEFAULT 0x0003e1fc
+#define mmBIF_VDDGFX_GFX4_LOWER_DEFAULT 0xc003ec00
+#define mmBIF_VDDGFX_GFX4_UPPER_DEFAULT 0x0003f1fc
+#define mmBIF_VDDGFX_GFX5_LOWER_DEFAULT 0xc003fc00
+#define mmBIF_VDDGFX_GFX5_UPPER_DEFAULT 0x0003fffc
+#define mmBIF_VDDGFX_RSV1_LOWER_DEFAULT 0x00000000
+#define mmBIF_VDDGFX_RSV1_UPPER_DEFAULT 0x00000000
+#define mmBIF_VDDGFX_RSV2_LOWER_DEFAULT 0x00000000
+#define mmBIF_VDDGFX_RSV2_UPPER_DEFAULT 0x00000000
+#define mmBIF_VDDGFX_RSV3_LOWER_DEFAULT 0x00000000
+#define mmBIF_VDDGFX_RSV3_UPPER_DEFAULT 0x00000000
+#define mmBIF_VDDGFX_RSV4_LOWER_DEFAULT 0x00000000
+#define mmBIF_VDDGFX_RSV4_UPPER_DEFAULT 0x00000000
+#define mmBIF_VDDGFX_FB_CMP_DEFAULT 0x00000000
+#define mmBIF_DOORBELL_GBLAPER1_LOWER_DEFAULT 0x80000780
+#define mmBIF_DOORBELL_GBLAPER1_UPPER_DEFAULT 0x000007fc
+#define mmBIF_DOORBELL_GBLAPER2_LOWER_DEFAULT 0x80000800
+#define mmBIF_DOORBELL_GBLAPER2_UPPER_DEFAULT 0x0000087c
+#define mmREMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c
+#define mmREMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858
+#define mmBIF_RB_CNTL_DEFAULT 0x00000000
+#define mmBIF_RB_BASE_DEFAULT 0x00000000
+#define mmBIF_RB_RPTR_DEFAULT 0x00000000
+#define mmBIF_RB_WPTR_DEFAULT 0x00000000
+#define mmBIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmBIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmMAILBOX_INDEX_DEFAULT 0x00000000
+#define mmBIF_GPUIOV_RESET_NOTIFICATION_DEFAULT 0x00000000
+#define mmBIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
+#define mmBIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
+#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
+#define mmBIF_GMI_WRR_WEIGHT_DEFAULT 0x00202020
+#define mmNBIF_STRAP_WRITE_CTRL_DEFAULT 0x00000000
+#define mmBIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0
+#define mmBIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031
+#define mmBIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007
+#define mmBIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100
+
+
+// addressBlock: rcc_pf_0_BIFDEC1
+// base address: 0x0
+#define mmRCC_BACO_CNTL_MISC_DEFAULT 0x00000000
+#define mmRCC_RESET_EN_DEFAULT 0x00008000
+#define mmRCC_VDM_SUPPORT_DEFAULT 0x00000000
+#define mmRCC_PEER_REG_RANGE0_DEFAULT 0xffff0000
+#define mmRCC_PEER_REG_RANGE1_DEFAULT 0xffff0000
+#define mmRCC_BUS_CNTL_DEFAULT 0x00000000
+#define mmRCC_CONFIG_CNTL_DEFAULT 0x00000000
+#define mmRCC_CONFIG_F0_BASE_DEFAULT 0x00000000
+#define mmRCC_CONFIG_APER_SIZE_DEFAULT 0x00000000
+#define mmRCC_CONFIG_REG_APER_SIZE_DEFAULT 0x00000000
+#define mmRCC_XDMA_LO_DEFAULT 0x00000000
+#define mmRCC_XDMA_HI_DEFAULT 0x00000000
+#define mmRCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000
+#define mmRCC_BUSNUM_CNTL1_DEFAULT 0x00000000
+#define mmRCC_BUSNUM_LIST0_DEFAULT 0x00000000
+#define mmRCC_BUSNUM_LIST1_DEFAULT 0x00000000
+#define mmRCC_BUSNUM_CNTL2_DEFAULT 0x00000000
+#define mmRCC_CAPTURE_HOST_BUSNUM_DEFAULT 0x00000000
+#define mmRCC_HOST_BUSNUM_DEFAULT 0x00000000
+#define mmRCC_PEER0_FB_OFFSET_HI_DEFAULT 0x00000000
+#define mmRCC_PEER0_FB_OFFSET_LO_DEFAULT 0x00000000
+#define mmRCC_PEER1_FB_OFFSET_HI_DEFAULT 0x00000000
+#define mmRCC_PEER1_FB_OFFSET_LO_DEFAULT 0x00000000
+#define mmRCC_PEER2_FB_OFFSET_HI_DEFAULT 0x00000000
+#define mmRCC_PEER2_FB_OFFSET_LO_DEFAULT 0x00000000
+#define mmRCC_PEER3_FB_OFFSET_HI_DEFAULT 0x00000000
+#define mmRCC_PEER3_FB_OFFSET_LO_DEFAULT 0x00000000
+#define mmRCC_DEVFUNCNUM_LIST0_DEFAULT 0x00000000
+#define mmRCC_DEVFUNCNUM_LIST1_DEFAULT 0x00000000
+#define mmRCC_DEV0_LINK_CNTL_DEFAULT 0x00000000
+#define mmRCC_CMN_LINK_CNTL_DEFAULT 0x00000000
+#define mmRCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000
+#define mmRCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000
+#define mmRCC_MH_ARB_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: rcc_pf_0_BIFDEC2
+// base address: 0x0
+#define mmGFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmGFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmGFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmGFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmGFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmGFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmGFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmGFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmGFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmGFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmGFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmGFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmGFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: rcc_strap_BIFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_PORT_STRAP0_DEFAULT 0x54228bc0
+#define mmRCC_DEV0_PORT_STRAP1_DEFAULT 0x1022145e
+#define mmRCC_DEV0_PORT_STRAP2_DEFAULT 0x1c65e009
+#define mmRCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849
+#define mmRCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000
+#define mmRCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000
+#define mmRCC_DEV0_PORT_STRAP6_DEFAULT 0x00000002
+#define mmRCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_STRAP0_DEFAULT 0x30000000
+#define mmRCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000
+#define mmRCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_STRAP2_DEFAULT 0x02000000
+#define mmRCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b40001
+#define mmRCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000042
+#define mmRCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001022
+#define mmRCC_DEV0_EPF0_STRAP8_DEFAULT 0xc8c73002
+#define mmRCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF1_STRAP0_DEFAULT 0x30000000
+#define mmRCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF1_STRAP2_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF1_STRAP3_DEFAULT 0x08040001
+#define mmRCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000
+#define mmRCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001022
+#define mmRCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000
+
+
+// addressBlock: bif_bx_pf_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmDOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000000
+#define mmHDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmGPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmGPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmMAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmMAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmMAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmMAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmMAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmMAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmMAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmMAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmMAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmMAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: rcc_pf_0_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: syshub_mmreg_ind_syshubdec
+// base address: 0x0
+#define mmSYSHUB_INDEX_DEFAULT 0x00000000
+#define mmSYSHUB_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: rcc_strap_rcc_strap_internal
+// base address: 0x10100000
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0_DEFAULT 0x54228bc0
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1_DEFAULT 0x1022145e
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2_DEFAULT 0x1c65e009
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6_DEFAULT 0x00000002
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000
+#define mmRCC_DEV1_PORT_STRAP0_DEFAULT 0x00000000
+#define mmRCC_DEV1_PORT_STRAP1_DEFAULT 0x00000000
+#define mmRCC_DEV1_PORT_STRAP2_DEFAULT 0x00000000
+#define mmRCC_DEV1_PORT_STRAP3_DEFAULT 0x00000000
+#define mmRCC_DEV1_PORT_STRAP4_DEFAULT 0x00000000
+#define mmRCC_DEV1_PORT_STRAP5_DEFAULT 0x00000000
+#define mmRCC_DEV1_PORT_STRAP6_DEFAULT 0x00000000
+#define mmRCC_DEV1_PORT_STRAP7_DEFAULT 0x00000000
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x30000000
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2_DEFAULT 0x02000000
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b40001
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000042
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001022
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8_DEFAULT 0xc8c73002
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000000
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0_DEFAULT 0x30000000
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2_DEFAULT 0x00000000
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3_DEFAULT 0x08040001
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001022
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF2_STRAP0_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF2_STRAP2_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF2_STRAP3_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF2_STRAP4_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF2_STRAP5_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF2_STRAP6_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF2_STRAP13_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF3_STRAP0_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF3_STRAP2_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF3_STRAP3_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF3_STRAP4_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF3_STRAP5_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF3_STRAP6_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF3_STRAP13_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF4_STRAP0_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF4_STRAP2_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF4_STRAP3_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF4_STRAP4_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF4_STRAP5_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF4_STRAP6_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF4_STRAP13_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF5_STRAP0_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF5_STRAP2_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF5_STRAP3_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF5_STRAP4_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF5_STRAP5_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF5_STRAP6_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF5_STRAP13_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF6_STRAP0_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF6_STRAP2_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF6_STRAP3_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF6_STRAP4_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF6_STRAP5_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF6_STRAP6_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF6_STRAP13_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF7_STRAP0_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF7_STRAP2_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF7_STRAP3_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF7_STRAP4_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF7_STRAP5_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF7_STRAP6_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF7_STRAP13_DEFAULT 0x00000000
+#define mmRCC_DEV1_EPF0_STRAP0_DEFAULT 0x00000000
+#define mmRCC_DEV1_EPF0_STRAP2_DEFAULT 0x00000000
+#define mmRCC_DEV1_EPF0_STRAP3_DEFAULT 0x00000000
+#define mmRCC_DEV1_EPF0_STRAP4_DEFAULT 0x00000000
+#define mmRCC_DEV1_EPF0_STRAP5_DEFAULT 0x00000000
+#define mmRCC_DEV1_EPF0_STRAP6_DEFAULT 0x00000000
+#define mmRCC_DEV1_EPF0_STRAP13_DEFAULT 0x00000000
+#define mmRCC_DEV1_EPF1_STRAP0_DEFAULT 0x00000000
+#define mmRCC_DEV1_EPF1_STRAP2_DEFAULT 0x00000000
+#define mmRCC_DEV1_EPF1_STRAP3_DEFAULT 0x00000000
+#define mmRCC_DEV1_EPF1_STRAP4_DEFAULT 0x00000000
+#define mmRCC_DEV1_EPF1_STRAP5_DEFAULT 0x00000000
+#define mmRCC_DEV1_EPF1_STRAP6_DEFAULT 0x00000000
+#define mmRCC_DEV1_EPF1_STRAP13_DEFAULT 0x00000000
+#define mmRCC_DEV1_EPF2_STRAP0_DEFAULT 0x00000000
+#define mmRCC_DEV1_EPF2_STRAP2_DEFAULT 0x00000000
+#define mmRCC_DEV1_EPF2_STRAP3_DEFAULT 0x00000000
+#define mmRCC_DEV1_EPF2_STRAP4_DEFAULT 0x00000000
+#define mmRCC_DEV1_EPF2_STRAP5_DEFAULT 0x00000000
+#define mmRCC_DEV1_EPF2_STRAP6_DEFAULT 0x00000000
+#define mmRCC_DEV1_EPF2_STRAP13_DEFAULT 0x00000000
+
+
+// addressBlock: bif_rst_bif_rst_regblk
+// base address: 0x10100000
+#define ixHARD_RST_CTRL_DEFAULT 0xb0000055
+#define ixRSMU_SOFT_RST_CTRL_DEFAULT 0x90000000
+#define ixSELF_SOFT_RST_DEFAULT 0x00000000
+#define ixGFX_DRV_MODE1_RST_CTRL_DEFAULT 0x000000a9
+#define ixBIF_RST_MISC_CTRL_DEFAULT 0x00000644
+#define ixBIF_RST_MISC_CTRL2_DEFAULT 0x00000000
+#define ixBIF_RST_MISC_CTRL3_DEFAULT 0x00004900
+#define ixBIF_RST_GFXVF_FLR_IDLE_DEFAULT 0x00000000
+#define ixDEV0_PF0_FLR_RST_CTRL_DEFAULT 0x0206a9a9
+#define ixDEV0_PF1_FLR_RST_CTRL_DEFAULT 0x02060009
+#define ixDEV0_PF2_FLR_RST_CTRL_DEFAULT 0x02060009
+#define ixDEV0_PF3_FLR_RST_CTRL_DEFAULT 0x02060009
+#define ixDEV0_PF4_FLR_RST_CTRL_DEFAULT 0x02060009
+#define ixDEV0_PF5_FLR_RST_CTRL_DEFAULT 0x02060009
+#define ixDEV0_PF6_FLR_RST_CTRL_DEFAULT 0x02060009
+#define ixDEV0_PF7_FLR_RST_CTRL_DEFAULT 0x02060009
+#define ixBIF_INST_RESET_INTR_STS_DEFAULT 0x00000000
+#define ixBIF_PF_FLR_INTR_STS_DEFAULT 0x00000000
+#define ixBIF_D3HOTD0_INTR_STS_DEFAULT 0x00000000
+#define ixBIF_POWER_INTR_STS_DEFAULT 0x00000000
+#define ixBIF_PF_DSTATE_INTR_STS_DEFAULT 0x00000000
+#define ixBIF_PF0_VF_FLR_INTR_STS_DEFAULT 0x00000000
+#define ixBIF_INST_RESET_INTR_MASK_DEFAULT 0x00000000
+#define ixBIF_PF_FLR_INTR_MASK_DEFAULT 0x00000000
+#define ixBIF_D3HOTD0_INTR_MASK_DEFAULT 0x000000ff
+#define ixBIF_POWER_INTR_MASK_DEFAULT 0x00000000
+#define ixBIF_PF_DSTATE_INTR_MASK_DEFAULT 0x00000000
+#define ixBIF_PF0_VF_FLR_INTR_MASK_DEFAULT 0x00000000
+#define ixBIF_PF_FLR_RST_DEFAULT 0x00000000
+#define ixBIF_PF0_VF_FLR_RST_DEFAULT 0x00000000
+#define ixBIF_DEV0_PF0_DSTATE_VALUE_DEFAULT 0x00000000
+#define ixBIF_DEV0_PF1_DSTATE_VALUE_DEFAULT 0x00000000
+#define ixBIF_DEV0_PF2_DSTATE_VALUE_DEFAULT 0x00000000
+#define ixBIF_DEV0_PF3_DSTATE_VALUE_DEFAULT 0x00000000
+#define ixBIF_DEV0_PF4_DSTATE_VALUE_DEFAULT 0x00000000
+#define ixBIF_DEV0_PF5_DSTATE_VALUE_DEFAULT 0x00000000
+#define ixBIF_DEV0_PF6_DSTATE_VALUE_DEFAULT 0x00000000
+#define ixBIF_DEV0_PF7_DSTATE_VALUE_DEFAULT 0x00000000
+#define ixDEV0_PF0_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define ixDEV0_PF1_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define ixDEV0_PF2_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define ixDEV0_PF3_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define ixDEV0_PF4_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define ixDEV0_PF5_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define ixDEV0_PF6_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define ixDEV0_PF7_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define ixBIF_PORT0_DSTATE_VALUE_DEFAULT 0x00000000
+
+
+// addressBlock: bif_misc_bif_misc_regblk
+// base address: 0x10100000
+#define ixMISC_SCRATCH_DEFAULT 0x00000000
+#define ixINTR_LINE_POLARITY_DEFAULT 0x00000000
+#define ixINTR_LINE_ENABLE_DEFAULT 0x00000000
+#define ixOUTSTANDING_VC_ALLOC_DEFAULT 0x6f06c0cf
+#define ixBIFC_MISC_CTRL0_DEFAULT 0x08000004
+#define ixBIFC_MISC_CTRL1_DEFAULT 0x00008004
+#define ixBIFC_BME_ERR_LOG_DEFAULT 0x00000000
+#define ixBIFC_RCCBIH_BME_ERR_LOG_DEFAULT 0x00000000
+#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_DEFAULT 0x00000000
+#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_DEFAULT 0x00000000
+#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_DEFAULT 0x00000000
+#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_DEFAULT 0x00000000
+#define ixNBIF_VWIRE_CTRL_DEFAULT 0x00000000
+#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000
+#define ixNBIF_SMN_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000
+#define ixNBIF_SMN_VWR_VCHG_TRIG_DEFAULT 0x00000000
+#define ixNBIF_SMN_VWR_WTRIG_CNTL_DEFAULT 0x00000000
+#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL_1_DEFAULT 0x00000000
+#define ixNBIF_MGCG_CTRL_DEFAULT 0x00000080
+#define ixNBIF_DS_CTRL_LCLK_DEFAULT 0x01000000
+#define ixSMN_MST_CNTL0_DEFAULT 0x00000001
+#define ixSMN_MST_EP_CNTL1_DEFAULT 0x00000000
+#define ixSMN_MST_EP_CNTL2_DEFAULT 0x00000000
+#define ixNBIF_SDP_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000
+#define ixNBIF_SDP_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000
+#define ixNBIF_SDP_VWR_VCHG_RST_CTRL1_DEFAULT 0x00000000
+#define ixNBIF_SDP_VWR_VCHG_TRIG_DEFAULT 0x00000000
+#define ixBME_DUMMY_CNTL_0_DEFAULT 0x0000aaaa
+#define ixBIFC_THT_CNTL_DEFAULT 0x00000222
+#define ixBIFC_HSTARB_CNTL_DEFAULT 0x00000000
+#define ixBIFC_GSI_CNTL_DEFAULT 0x000017c0
+#define ixBIFC_PCIEFUNC_CNTL_DEFAULT 0x00000000
+#define ixBIFC_SDP_CNTL_0_DEFAULT 0x003cf3cf
+#define ixBIFC_PERF_CNTL_0_DEFAULT 0x00000000
+#define ixBIFC_PERF_CNTL_1_DEFAULT 0x00000000
+#define ixBIFC_PERF_CNT_MMIO_RD_DEFAULT 0x00000000
+#define ixBIFC_PERF_CNT_MMIO_WR_DEFAULT 0x00000000
+#define ixBIFC_PERF_CNT_DMA_RD_DEFAULT 0x00000000
+#define ixBIFC_PERF_CNT_DMA_WR_DEFAULT 0x00000000
+#define ixNBIF_REGIF_ERRSET_CTRL_DEFAULT 0x00000000
+#define ixSMN_MST_EP_CNTL3_DEFAULT 0x00000000
+#define ixSMN_MST_EP_CNTL4_DEFAULT 0x00000000
+#define ixBIF_SELFRING_BUFFER_VID_DEFAULT 0x0000605f
+#define ixBIF_SELFRING_VECTOR_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: bif_ras_bif_ras_regblk
+// base address: 0x10100000
+#define ixBIF_RAS_LEAF0_CTRL_DEFAULT 0x00000000
+#define ixBIF_RAS_LEAF1_CTRL_DEFAULT 0x00000000
+#define ixBIF_RAS_LEAF2_CTRL_DEFAULT 0x00000000
+#define ixBIF_RAS_MISC_CTRL_DEFAULT 0x00000000
+#define ixBIF_IOHUB_RAS_IH_CNTL_DEFAULT 0x00000000
+#define ixBIF_RAS_VWR_FROM_IOHUB_DEFAULT 0x00000000
+
+
+// addressBlock: rcc_pfc_amdgfx_RCCPFCDEC
+// base address: 0x10134000
+#define ixRCC_PFC_LTR_CNTL_DEFAULT 0x00000000
+#define ixRCC_PFC_PME_RESTORE_DEFAULT 0x00000000
+#define ixRCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000
+#define ixRCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000
+#define ixRCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000
+#define ixRCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000
+#define ixRCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000
+#define ixRCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000
+#define ixRCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC
+// base address: 0x10134200
+#define ixRCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000
+#define ixRCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000
+#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000
+#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000
+#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000
+#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000
+#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000
+#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000
+#define ixRCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: pciemsix_amdgfx_MSIXTDEC
+// base address: 0x10170000
+#define ixPCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000
+#define ixPCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000
+
+
+// addressBlock: pciemsix_amdgfx_MSIXPDEC
+// base address: 0x10171000
+#define ixPCIEMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: syshub_mmreg_ind_syshubind
+// base address: 0x0
+#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000
+#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100
+#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000
+#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000
+#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
+#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
+#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000
+#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000
+#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL_DEFAULT 0x20200000
+#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL_DEFAULT 0x20200000
+#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL_DEFAULT 0x20200000
+#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL_DEFAULT 0x20200000
+#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL_DEFAULT 0x20200000
+#define ixSYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL_DEFAULT 0x20200000
+#define ixSYSHUBMMREGIND_SYSHUB_CG_CNTL_DEFAULT 0x00082000
+#define ixSYSHUBMMREGIND_SYSHUB_TRANS_IDLE_DEFAULT 0x00000000
+#define ixSYSHUBMMREGIND_SYSHUB_HP_TIMER_DEFAULT 0x00000100
+#define ixSYSHUBMMREGIND_SYSHUB_SCRATCH_DEFAULT 0x00000040
+#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000
+#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100
+#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000
+#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL_DEFAULT 0x20200000
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL_DEFAULT 0x20200000
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL_DEFAULT 0x20200000
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL_DEFAULT 0x20200000
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL_DEFAULT 0x20200000
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL_DEFAULT 0x20200000
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL_DEFAULT 0x20200000
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL_DEFAULT 0x20200000
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL_DEFAULT 0x20200000
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL_DEFAULT 0x20200000
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h
new file mode 100644
index 000000000000..68d0ffad28c7
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h
@@ -0,0 +1,1688 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _nbif_6_1_OFFSET_HEADER
+#define _nbif_6_1_OFFSET_HEADER
+
+
+// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp
+// base address: 0x0
+#define cfgVENDOR_ID 0x0000 // duplicate
+#define cfgDEVICE_ID 0x0002 // duplicate
+#define cfgCOMMAND 0x0004 // duplicate
+#define cfgSTATUS 0x0006 // duplicate
+#define cfgREVISION_ID 0x0008 // duplicate
+#define cfgPROG_INTERFACE 0x0009 // duplicate
+#define cfgSUB_CLASS 0x000a // duplicate
+#define cfgBASE_CLASS 0x000b // duplicate
+#define cfgCACHE_LINE 0x000c // duplicate
+#define cfgLATENCY 0x000d // duplicate
+#define cfgHEADER 0x000e // duplicate
+#define cfgBIST 0x000f // duplicate
+#define cfgBASE_ADDR_1 0x0010 // duplicate
+#define cfgBASE_ADDR_2 0x0014 // duplicate
+#define cfgBASE_ADDR_3 0x0018 // duplicate
+#define cfgBASE_ADDR_4 0x001c // duplicate
+#define cfgBASE_ADDR_5 0x0020 // duplicate
+#define cfgBASE_ADDR_6 0x0024 // duplicate
+#define cfgADAPTER_ID 0x002c // duplicate
+#define cfgROM_BASE_ADDR 0x0030 // duplicate
+#define cfgCAP_PTR 0x0034 // duplicate
+#define cfgINTERRUPT_LINE 0x003c // duplicate
+#define cfgINTERRUPT_PIN 0x003d // duplicate
+#define cfgMIN_GRANT 0x003e // duplicate
+#define cfgMAX_LATENCY 0x003f // duplicate
+#define cfgVENDOR_CAP_LIST 0x0048 // duplicate
+#define cfgADAPTER_ID_W 0x004c // duplicate
+#define cfgPMI_CAP_LIST 0x0050 // duplicate
+#define cfgPMI_CAP 0x0052 // duplicate
+#define cfgPMI_STATUS_CNTL 0x0054 // duplicate
+#define cfgPCIE_CAP_LIST 0x0064 // duplicate
+#define cfgPCIE_CAP 0x0066 // duplicate
+#define cfgDEVICE_CAP 0x0068 // duplicate
+#define cfgDEVICE_CNTL 0x006c // duplicate
+#define cfgDEVICE_STATUS 0x006e // duplicate
+#define cfgLINK_CAP 0x0070 // duplicate
+#define cfgLINK_CNTL 0x0074 // duplicate
+#define cfgLINK_STATUS 0x0076 // duplicate
+#define cfgDEVICE_CAP2 0x0088 // duplicate
+#define cfgDEVICE_CNTL2 0x008c // duplicate
+#define cfgDEVICE_STATUS2 0x008e // duplicate
+#define cfgLINK_CAP2 0x0090 // duplicate
+#define cfgLINK_CNTL2 0x0094 // duplicate
+#define cfgLINK_STATUS2 0x0096 // duplicate
+#define cfgSLOT_CAP2 0x0098 // duplicate
+#define cfgSLOT_CNTL2 0x009c // duplicate
+#define cfgSLOT_STATUS2 0x009e // duplicate
+#define cfgMSI_CAP_LIST 0x00a0 // duplicate
+#define cfgMSI_MSG_CNTL 0x00a2 // duplicate
+#define cfgMSI_MSG_ADDR_LO 0x00a4 // duplicate
+#define cfgMSI_MSG_ADDR_HI 0x00a8 // duplicate
+#define cfgMSI_MSG_DATA 0x00a8 // duplicate
+#define cfgMSI_MSG_DATA_64 0x00ac // duplicate
+#define cfgMSI_MASK 0x00ac // duplicate
+#define cfgMSI_PENDING 0x00b0 // duplicate
+#define cfgMSI_MASK_64 0x00b0 // duplicate
+#define cfgMSI_PENDING_64 0x00b4 // duplicate
+#define cfgMSIX_CAP_LIST 0x00c0 // duplicate
+#define cfgMSIX_MSG_CNTL 0x00c2 // duplicate
+#define cfgMSIX_TABLE 0x00c4 // duplicate
+#define cfgMSIX_PBA 0x00c8 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR 0x0104 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC1 0x0108 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC2 0x010c // duplicate
+#define cfgPCIE_VC_ENH_CAP_LIST 0x0110 // duplicate
+#define cfgPCIE_PORT_VC_CAP_REG1 0x0114 // duplicate
+#define cfgPCIE_PORT_VC_CAP_REG2 0x0118 // duplicate
+#define cfgPCIE_PORT_VC_CNTL 0x011c // duplicate
+#define cfgPCIE_PORT_VC_STATUS 0x011e // duplicate
+#define cfgPCIE_VC0_RESOURCE_CAP 0x0120 // duplicate
+#define cfgPCIE_VC0_RESOURCE_CNTL 0x0124 // duplicate
+#define cfgPCIE_VC0_RESOURCE_STATUS 0x012a // duplicate
+#define cfgPCIE_VC1_RESOURCE_CAP 0x012c // duplicate
+#define cfgPCIE_VC1_RESOURCE_CNTL 0x0130 // duplicate
+#define cfgPCIE_VC1_RESOURCE_STATUS 0x0136 // duplicate
+#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 // duplicate
+#define cfgPCIE_DEV_SERIAL_NUM_DW1 0x0144 // duplicate
+#define cfgPCIE_DEV_SERIAL_NUM_DW2 0x0148 // duplicate
+#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 // duplicate
+#define cfgPCIE_UNCORR_ERR_STATUS 0x0154 // duplicate
+#define cfgPCIE_UNCORR_ERR_MASK 0x0158 // duplicate
+#define cfgPCIE_UNCORR_ERR_SEVERITY 0x015c // duplicate
+#define cfgPCIE_CORR_ERR_STATUS 0x0160 // duplicate
+#define cfgPCIE_CORR_ERR_MASK 0x0164 // duplicate
+#define cfgPCIE_ADV_ERR_CAP_CNTL 0x0168 // duplicate
+#define cfgPCIE_HDR_LOG0 0x016c // duplicate
+#define cfgPCIE_HDR_LOG1 0x0170 // duplicate
+#define cfgPCIE_HDR_LOG2 0x0174 // duplicate
+#define cfgPCIE_HDR_LOG3 0x0178 // duplicate
+#define cfgPCIE_ROOT_ERR_CMD 0x017c // duplicate
+#define cfgPCIE_ROOT_ERR_STATUS 0x0180 // duplicate
+#define cfgPCIE_ERR_SRC_ID 0x0184 // duplicate
+#define cfgPCIE_TLP_PREFIX_LOG0 0x0188 // duplicate
+#define cfgPCIE_TLP_PREFIX_LOG1 0x018c // duplicate
+#define cfgPCIE_TLP_PREFIX_LOG2 0x0190 // duplicate
+#define cfgPCIE_TLP_PREFIX_LOG3 0x0194 // duplicate
+#define cfgPCIE_BAR_ENH_CAP_LIST 0x0200 // duplicate
+#define cfgPCIE_BAR1_CAP 0x0204 // duplicate
+#define cfgPCIE_BAR1_CNTL 0x0208 // duplicate
+#define cfgPCIE_BAR2_CAP 0x020c // duplicate
+#define cfgPCIE_BAR2_CNTL 0x0210 // duplicate
+#define cfgPCIE_BAR3_CAP 0x0214 // duplicate
+#define cfgPCIE_BAR3_CNTL 0x0218 // duplicate
+#define cfgPCIE_BAR4_CAP 0x021c // duplicate
+#define cfgPCIE_BAR4_CNTL 0x0220 // duplicate
+#define cfgPCIE_BAR5_CAP 0x0224 // duplicate
+#define cfgPCIE_BAR5_CNTL 0x0228 // duplicate
+#define cfgPCIE_BAR6_CAP 0x022c // duplicate
+#define cfgPCIE_BAR6_CNTL 0x0230 // duplicate
+#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 // duplicate
+#define cfgPCIE_PWR_BUDGET_DATA_SELECT 0x0244 // duplicate
+#define cfgPCIE_PWR_BUDGET_DATA 0x0248 // duplicate
+#define cfgPCIE_PWR_BUDGET_CAP 0x024c // duplicate
+#define cfgPCIE_DPA_ENH_CAP_LIST 0x0250 // duplicate
+#define cfgPCIE_DPA_CAP 0x0254 // duplicate
+#define cfgPCIE_DPA_LATENCY_INDICATOR 0x0258 // duplicate
+#define cfgPCIE_DPA_STATUS 0x025c // duplicate
+#define cfgPCIE_DPA_CNTL 0x025e // duplicate
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 // duplicate
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 // duplicate
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 // duplicate
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 // duplicate
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 // duplicate
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 // duplicate
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 // duplicate
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 // duplicate
+#define cfgPCIE_SECONDARY_ENH_CAP_LIST 0x0270 // duplicate
+#define cfgPCIE_LINK_CNTL3 0x0274 // duplicate
+#define cfgPCIE_LANE_ERROR_STATUS 0x0278 // duplicate
+#define cfgPCIE_LANE_0_EQUALIZATION_CNTL 0x027c // duplicate
+#define cfgPCIE_LANE_1_EQUALIZATION_CNTL 0x027e // duplicate
+#define cfgPCIE_LANE_2_EQUALIZATION_CNTL 0x0280 // duplicate
+#define cfgPCIE_LANE_3_EQUALIZATION_CNTL 0x0282 // duplicate
+#define cfgPCIE_LANE_4_EQUALIZATION_CNTL 0x0284 // duplicate
+#define cfgPCIE_LANE_5_EQUALIZATION_CNTL 0x0286 // duplicate
+#define cfgPCIE_LANE_6_EQUALIZATION_CNTL 0x0288 // duplicate
+#define cfgPCIE_LANE_7_EQUALIZATION_CNTL 0x028a // duplicate
+#define cfgPCIE_LANE_8_EQUALIZATION_CNTL 0x028c // duplicate
+#define cfgPCIE_LANE_9_EQUALIZATION_CNTL 0x028e // duplicate
+#define cfgPCIE_LANE_10_EQUALIZATION_CNTL 0x0290 // duplicate
+#define cfgPCIE_LANE_11_EQUALIZATION_CNTL 0x0292 // duplicate
+#define cfgPCIE_LANE_12_EQUALIZATION_CNTL 0x0294 // duplicate
+#define cfgPCIE_LANE_13_EQUALIZATION_CNTL 0x0296 // duplicate
+#define cfgPCIE_LANE_14_EQUALIZATION_CNTL 0x0298 // duplicate
+#define cfgPCIE_LANE_15_EQUALIZATION_CNTL 0x029a // duplicate
+#define cfgPCIE_ACS_ENH_CAP_LIST 0x02a0 // duplicate
+#define cfgPCIE_ACS_CAP 0x02a4 // duplicate
+#define cfgPCIE_ACS_CNTL 0x02a6 // duplicate
+#define cfgPCIE_ATS_ENH_CAP_LIST 0x02b0 // duplicate
+#define cfgPCIE_ATS_CAP 0x02b4 // duplicate
+#define cfgPCIE_ATS_CNTL 0x02b6 // duplicate
+#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 // duplicate
+#define cfgPCIE_PAGE_REQ_CNTL 0x02c4 // duplicate
+#define cfgPCIE_PAGE_REQ_STATUS 0x02c6 // duplicate
+#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 // duplicate
+#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc // duplicate
+#define cfgPCIE_PASID_ENH_CAP_LIST 0x02d0 // duplicate
+#define cfgPCIE_PASID_CAP 0x02d4 // duplicate
+#define cfgPCIE_PASID_CNTL 0x02d6 // duplicate
+#define cfgPCIE_TPH_REQR_ENH_CAP_LIST 0x02e0 // duplicate
+#define cfgPCIE_TPH_REQR_CAP 0x02e4 // duplicate
+#define cfgPCIE_TPH_REQR_CNTL 0x02e8 // duplicate
+#define cfgPCIE_MC_ENH_CAP_LIST 0x02f0 // duplicate
+#define cfgPCIE_MC_CAP 0x02f4 // duplicate
+#define cfgPCIE_MC_CNTL 0x02f6 // duplicate
+#define cfgPCIE_MC_ADDR0 0x02f8 // duplicate
+#define cfgPCIE_MC_ADDR1 0x02fc // duplicate
+#define cfgPCIE_MC_RCV0 0x0300 // duplicate
+#define cfgPCIE_MC_RCV1 0x0304 // duplicate
+#define cfgPCIE_MC_BLOCK_ALL0 0x0308 // duplicate
+#define cfgPCIE_MC_BLOCK_ALL1 0x030c // duplicate
+#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 // duplicate
+#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 // duplicate
+#define cfgPCIE_LTR_ENH_CAP_LIST 0x0320 // duplicate
+#define cfgPCIE_LTR_CAP 0x0324 // duplicate
+#define cfgPCIE_ARI_ENH_CAP_LIST 0x0328 // duplicate
+#define cfgPCIE_ARI_CAP 0x032c // duplicate
+#define cfgPCIE_ARI_CNTL 0x032e // duplicate
+#define cfgPCIE_SRIOV_ENH_CAP_LIST 0x0330 // duplicate
+#define cfgPCIE_SRIOV_CAP 0x0334 // duplicate
+#define cfgPCIE_SRIOV_CONTROL 0x0338 // duplicate
+#define cfgPCIE_SRIOV_STATUS 0x033a // duplicate
+#define cfgPCIE_SRIOV_INITIAL_VFS 0x033c // duplicate
+#define cfgPCIE_SRIOV_TOTAL_VFS 0x033e // duplicate
+#define cfgPCIE_SRIOV_NUM_VFS 0x0340 // duplicate
+#define cfgPCIE_SRIOV_FUNC_DEP_LINK 0x0342 // duplicate
+#define cfgPCIE_SRIOV_FIRST_VF_OFFSET 0x0344 // duplicate
+#define cfgPCIE_SRIOV_VF_STRIDE 0x0346 // duplicate
+#define cfgPCIE_SRIOV_VF_DEVICE_ID 0x034a // duplicate
+#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c // duplicate
+#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 // duplicate
+#define cfgPCIE_SRIOV_VF_BASE_ADDR_0 0x0354 // duplicate
+#define cfgPCIE_SRIOV_VF_BASE_ADDR_1 0x0358 // duplicate
+#define cfgPCIE_SRIOV_VF_BASE_ADDR_2 0x035c // duplicate
+#define cfgPCIE_SRIOV_VF_BASE_ADDR_3 0x0360 // duplicate
+#define cfgPCIE_SRIOV_VF_BASE_ADDR_4 0x0364 // duplicate
+#define cfgPCIE_SRIOV_VF_BASE_ADDR_5 0x0368 // duplicate
+#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x0490 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x0494 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x0498 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x049c // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04a0 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04a4 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04a8 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04ac // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04b0 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04b4 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04b8 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04bc // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04c0 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04c4 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04c8 // duplicate
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04cc // duplicate
+
+
+// addressBlock: bif_cfg_dev0_swds_bifcfgdecp
+// base address: 0x0
+#define mmSUB_BUS_NUMBER_LATENCY 0x0006 // duplicate
+#define mmSUB_BUS_NUMBER_LATENCY_BASE_IDX 0
+#define mmIO_BASE_LIMIT 0x0007 // duplicate
+#define mmIO_BASE_LIMIT_BASE_IDX 0
+#define mmSECONDARY_STATUS 0x0007 // duplicate
+#define mmSECONDARY_STATUS_BASE_IDX 0
+#define mmMEM_BASE_LIMIT 0x0008 // duplicate
+#define mmMEM_BASE_LIMIT_BASE_IDX 0
+#define mmPREF_BASE_LIMIT 0x0009 // duplicate
+#define mmPREF_BASE_LIMIT_BASE_IDX 0
+#define mmPREF_BASE_UPPER 0x000a // duplicate
+#define mmPREF_BASE_UPPER_BASE_IDX 0
+#define mmPREF_LIMIT_UPPER 0x000b // duplicate
+#define mmPREF_LIMIT_UPPER_BASE_IDX 0
+#define mmIO_BASE_LIMIT_HI 0x000c // duplicate
+#define mmIO_BASE_LIMIT_HI_BASE_IDX 0
+#define mmIRQ_BRIDGE_CNTL 0x000f // duplicate
+#define mmIRQ_BRIDGE_CNTL_BASE_IDX 0
+#define mmSLOT_CAP 0x001b // duplicate
+#define mmSLOT_CAP_BASE_IDX 0
+#define mmSLOT_CNTL 0x001c // duplicate
+#define mmSLOT_CNTL_BASE_IDX 0
+#define mmSLOT_STATUS 0x001c // duplicate
+#define mmSLOT_STATUS_BASE_IDX 0
+#define mmSSID_CAP_LIST 0x0030 // duplicate
+#define mmSSID_CAP_LIST_BASE_IDX 0
+#define mmSSID_CAP 0x0031 // duplicate
+#define mmSSID_CAP_BASE_IDX 0
+
+
+// addressBlock: rcc_shadow_reg_shadowdec
+// base address: 0x0
+#define ixSHADOW_COMMAND 0x0004 // duplicate
+#define ixSHADOW_BASE_ADDR_1 0x0010 // duplicate
+#define ixSHADOW_BASE_ADDR_2 0x0014 // duplicate
+#define ixSHADOW_SUB_BUS_NUMBER_LATENCY 0x0018 // duplicate
+#define ixSHADOW_IO_BASE_LIMIT 0x001c // duplicate
+#define ixSHADOW_MEM_BASE_LIMIT 0x0020 // duplicate
+#define ixSHADOW_PREF_BASE_LIMIT 0x0024 // duplicate
+#define ixSHADOW_PREF_BASE_UPPER 0x0028 // duplicate
+#define ixSHADOW_PREF_LIMIT_UPPER 0x002c // duplicate
+#define ixSHADOW_IO_BASE_LIMIT_HI 0x0030 // duplicate
+#define ixSHADOW_IRQ_BRIDGE_CNTL 0x003e // duplicate
+#define ixSUC_INDEX 0x00e0 // duplicate
+#define ixSUC_DATA 0x00e4 // duplicate
+
+
+// addressBlock: bif_bx_pf_SUMDEC
+// base address: 0x0
+#define ixSUM_INDEX 0x00e0 // duplicate
+#define ixSUM_DATA 0x00e4 // duplicate
+
+
+// addressBlock: gdc_GDCDEC
+// base address: 0x1400000
+#define mmA2S_CNTL_CL0 0x4f0ab0 // duplicate
+#define mmA2S_CNTL_CL0_BASE_IDX 3
+#define mmA2S_CNTL_CL1 0x4f0ab1 // duplicate
+#define mmA2S_CNTL_CL1_BASE_IDX 3
+#define mmA2S_CNTL_CL2 0x4f0ab2 // duplicate
+#define mmA2S_CNTL_CL2_BASE_IDX 3
+#define mmA2S_CNTL_CL3 0x4f0ab3 // duplicate
+#define mmA2S_CNTL_CL3_BASE_IDX 3
+#define mmA2S_CNTL_CL4 0x4f0ab4 // duplicate
+#define mmA2S_CNTL_CL4_BASE_IDX 3
+#define mmA2S_CNTL_SW0 0x4f0ad0 // duplicate
+#define mmA2S_CNTL_SW0_BASE_IDX 3
+#define mmA2S_CNTL_SW1 0x4f0ad1 // duplicate
+#define mmA2S_CNTL_SW1_BASE_IDX 3
+#define mmA2S_CNTL_SW2 0x4f0ad2 // duplicate
+#define mmA2S_CNTL_SW2_BASE_IDX 3
+#define mmNGDC_MGCG_CTRL 0x4f0ae0 // duplicate
+#define mmNGDC_MGCG_CTRL_BASE_IDX 3
+#define mmA2S_MISC_CNTL 0x4f0ae1 // duplicate
+#define mmA2S_MISC_CNTL_BASE_IDX 3
+#define mmNGDC_SDP_PORT_CTRL 0x4f0ae2 // duplicate
+#define mmNGDC_SDP_PORT_CTRL_BASE_IDX 3
+#define mmNGDC_RESERVED_0 0x4f0aeb // duplicate
+#define mmNGDC_RESERVED_0_BASE_IDX 3
+#define mmNGDC_RESERVED_1 0x4f0aec // duplicate
+#define mmNGDC_RESERVED_1_BASE_IDX 3
+#define mmBIF_SDMA0_DOORBELL_RANGE 0x4f0af0 // duplicate
+#define mmBIF_SDMA0_DOORBELL_RANGE_BASE_IDX 3
+#define mmBIF_SDMA1_DOORBELL_RANGE 0x4f0af1 // duplicate
+#define mmBIF_SDMA1_DOORBELL_RANGE_BASE_IDX 3
+#define mmBIF_IH_DOORBELL_RANGE 0x4f0af2 // duplicate
+#define mmBIF_IH_DOORBELL_RANGE_BASE_IDX 3
+#define mmBIF_MMSCH0_DOORBELL_RANGE 0x4f0af3 // duplicate
+#define mmBIF_MMSCH0_DOORBELL_RANGE_BASE_IDX 3
+#define mmBIF_DOORBELL_FENCE_CNTL 0x4f0afe // duplicate
+#define mmBIF_DOORBELL_FENCE_CNTL_BASE_IDX 3
+#define mmS2A_MISC_CNTL 0x4f0aff // duplicate
+#define mmS2A_MISC_CNTL_BASE_IDX 3
+#define mmA2S_CNTL2_SEC_CL0 0x4f0b00 // duplicate
+#define mmA2S_CNTL2_SEC_CL0_BASE_IDX 3
+#define mmA2S_CNTL2_SEC_CL1 0x4f0b01 // duplicate
+#define mmA2S_CNTL2_SEC_CL1_BASE_IDX 3
+#define mmA2S_CNTL2_SEC_CL2 0x4f0b02 // duplicate
+#define mmA2S_CNTL2_SEC_CL2_BASE_IDX 3
+#define mmA2S_CNTL2_SEC_CL3 0x4f0b03 // duplicate
+#define mmA2S_CNTL2_SEC_CL3_BASE_IDX 3
+#define mmA2S_CNTL2_SEC_CL4 0x4f0b04 // duplicate
+#define mmA2S_CNTL2_SEC_CL4_BASE_IDX 3
+
+
+// addressBlock: nbif_sion_SIONDEC
+// base address: 0x1400000
+#define ixSION_CL0_RdRsp_BurstTarget_REG0 0x1e000
+#define ixSION_CL0_RdRsp_BurstTarget_REG1 0x1e004
+#define ixSION_CL0_RdRsp_TimeSlot_REG0 0x1e008
+#define ixSION_CL0_RdRsp_TimeSlot_REG1 0x1e00c
+#define ixSION_CL0_WrRsp_BurstTarget_REG0 0x1e010
+#define ixSION_CL0_WrRsp_BurstTarget_REG1 0x1e014
+#define ixSION_CL0_WrRsp_TimeSlot_REG0 0x1e018
+#define ixSION_CL0_WrRsp_TimeSlot_REG1 0x1e01c
+#define ixSION_CL0_Req_BurstTarget_REG0 0x1e020
+#define ixSION_CL0_Req_BurstTarget_REG1 0x1e024
+#define ixSION_CL0_Req_TimeSlot_REG0 0x1e028
+#define ixSION_CL0_Req_TimeSlot_REG1 0x1e02c
+#define ixSION_CL0_ReqPoolCredit_Alloc_REG0 0x1e030
+#define ixSION_CL0_ReqPoolCredit_Alloc_REG1 0x1e034
+#define ixSION_CL0_DataPoolCredit_Alloc_REG0 0x1e038
+#define ixSION_CL0_DataPoolCredit_Alloc_REG1 0x1e03c
+#define ixSION_CL0_RdRspPoolCredit_Alloc_REG0 0x1e040
+#define ixSION_CL0_RdRspPoolCredit_Alloc_REG1 0x1e044
+#define ixSION_CL0_WrRspPoolCredit_Alloc_REG0 0x1e048
+#define ixSION_CL0_WrRspPoolCredit_Alloc_REG1 0x1e04c
+#define ixSION_CL1_RdRsp_BurstTarget_REG0 0x1e050
+#define ixSION_CL1_RdRsp_BurstTarget_REG1 0x1e054
+#define ixSION_CL1_RdRsp_TimeSlot_REG0 0x1e058
+#define ixSION_CL1_RdRsp_TimeSlot_REG1 0x1e05c
+#define ixSION_CL1_WrRsp_BurstTarget_REG0 0x1e060
+#define ixSION_CL1_WrRsp_BurstTarget_REG1 0x1e064
+#define ixSION_CL1_WrRsp_TimeSlot_REG0 0x1e068
+#define ixSION_CL1_WrRsp_TimeSlot_REG1 0x1e06c
+#define ixSION_CL1_Req_BurstTarget_REG0 0x1e070
+#define ixSION_CL1_Req_BurstTarget_REG1 0x1e074
+#define ixSION_CL1_Req_TimeSlot_REG0 0x1e078
+#define ixSION_CL1_Req_TimeSlot_REG1 0x1e07c
+#define ixSION_CL1_ReqPoolCredit_Alloc_REG0 0x1e080
+#define ixSION_CL1_ReqPoolCredit_Alloc_REG1 0x1e084
+#define ixSION_CL1_DataPoolCredit_Alloc_REG0 0x1e088
+#define ixSION_CL1_DataPoolCredit_Alloc_REG1 0x1e08c
+#define ixSION_CL1_RdRspPoolCredit_Alloc_REG0 0x1e090
+#define ixSION_CL1_RdRspPoolCredit_Alloc_REG1 0x1e094
+#define ixSION_CL1_WrRspPoolCredit_Alloc_REG0 0x1e098
+#define ixSION_CL1_WrRspPoolCredit_Alloc_REG1 0x1e09c
+#define ixSION_CL2_RdRsp_BurstTarget_REG0 0x1e0a0
+#define ixSION_CL2_RdRsp_BurstTarget_REG1 0x1e0a4
+#define ixSION_CL2_RdRsp_TimeSlot_REG0 0x1e0a8
+#define ixSION_CL2_RdRsp_TimeSlot_REG1 0x1e0ac
+#define ixSION_CL2_WrRsp_BurstTarget_REG0 0x1e0b0
+#define ixSION_CL2_WrRsp_BurstTarget_REG1 0x1e0b4
+#define ixSION_CL2_WrRsp_TimeSlot_REG0 0x1e0b8
+#define ixSION_CL2_WrRsp_TimeSlot_REG1 0x1e0bc
+#define ixSION_CL2_Req_BurstTarget_REG0 0x1e0c0
+#define ixSION_CL2_Req_BurstTarget_REG1 0x1e0c4
+#define ixSION_CL2_Req_TimeSlot_REG0 0x1e0c8
+#define ixSION_CL2_Req_TimeSlot_REG1 0x1e0cc
+#define ixSION_CL2_ReqPoolCredit_Alloc_REG0 0x1e0d0
+#define ixSION_CL2_ReqPoolCredit_Alloc_REG1 0x1e0d4
+#define ixSION_CL2_DataPoolCredit_Alloc_REG0 0x1e0d8
+#define ixSION_CL2_DataPoolCredit_Alloc_REG1 0x1e0dc
+#define ixSION_CL2_RdRspPoolCredit_Alloc_REG0 0x1e0e0
+#define ixSION_CL2_RdRspPoolCredit_Alloc_REG1 0x1e0e4
+#define ixSION_CL2_WrRspPoolCredit_Alloc_REG0 0x1e0e8
+#define ixSION_CL2_WrRspPoolCredit_Alloc_REG1 0x1e0ec
+#define ixSION_CL3_RdRsp_BurstTarget_REG0 0x1e0f0
+#define ixSION_CL3_RdRsp_BurstTarget_REG1 0x1e0f4
+#define ixSION_CL3_RdRsp_TimeSlot_REG0 0x1e0f8
+#define ixSION_CL3_RdRsp_TimeSlot_REG1 0x1e0fc
+#define ixSION_CL3_WrRsp_BurstTarget_REG0 0x1e100
+#define ixSION_CL3_WrRsp_BurstTarget_REG1 0x1e104
+#define ixSION_CL3_WrRsp_TimeSlot_REG0 0x1e108
+#define ixSION_CL3_WrRsp_TimeSlot_REG1 0x1e10c
+#define ixSION_CL3_Req_BurstTarget_REG0 0x1e110
+#define ixSION_CL3_Req_BurstTarget_REG1 0x1e114
+#define ixSION_CL3_Req_TimeSlot_REG0 0x1e118
+#define ixSION_CL3_Req_TimeSlot_REG1 0x1e11c
+#define ixSION_CL3_ReqPoolCredit_Alloc_REG0 0x1e120
+#define ixSION_CL3_ReqPoolCredit_Alloc_REG1 0x1e124
+#define ixSION_CL3_DataPoolCredit_Alloc_REG0 0x1e128
+#define ixSION_CL3_DataPoolCredit_Alloc_REG1 0x1e12c
+#define ixSION_CL3_RdRspPoolCredit_Alloc_REG0 0x1e130
+#define ixSION_CL3_RdRspPoolCredit_Alloc_REG1 0x1e134
+#define ixSION_CL3_WrRspPoolCredit_Alloc_REG0 0x1e138
+#define ixSION_CL3_WrRspPoolCredit_Alloc_REG1 0x1e13c
+#define ixSION_CL4_RdRsp_BurstTarget_REG0 0x1e140
+#define ixSION_CL4_RdRsp_BurstTarget_REG1 0x1e144
+#define ixSION_CL4_RdRsp_TimeSlot_REG0 0x1e148
+#define ixSION_CL4_RdRsp_TimeSlot_REG1 0x1e14c
+#define ixSION_CL4_WrRsp_BurstTarget_REG0 0x1e150
+#define ixSION_CL4_WrRsp_BurstTarget_REG1 0x1e154
+#define ixSION_CL4_WrRsp_TimeSlot_REG0 0x1e158
+#define ixSION_CL4_WrRsp_TimeSlot_REG1 0x1e15c
+#define ixSION_CL4_Req_BurstTarget_REG0 0x1e160
+#define ixSION_CL4_Req_BurstTarget_REG1 0x1e164
+#define ixSION_CL4_Req_TimeSlot_REG0 0x1e168
+#define ixSION_CL4_Req_TimeSlot_REG1 0x1e16c
+#define ixSION_CL4_ReqPoolCredit_Alloc_REG0 0x1e170
+#define ixSION_CL4_ReqPoolCredit_Alloc_REG1 0x1e174
+#define ixSION_CL4_DataPoolCredit_Alloc_REG0 0x1e178
+#define ixSION_CL4_DataPoolCredit_Alloc_REG1 0x1e17c
+#define ixSION_CL4_RdRspPoolCredit_Alloc_REG0 0x1e180
+#define ixSION_CL4_RdRspPoolCredit_Alloc_REG1 0x1e184
+#define ixSION_CL4_WrRspPoolCredit_Alloc_REG0 0x1e188
+#define ixSION_CL4_WrRspPoolCredit_Alloc_REG1 0x1e18c
+#define ixSION_CL5_RdRsp_BurstTarget_REG0 0x1e190
+#define ixSION_CL5_RdRsp_BurstTarget_REG1 0x1e194
+#define ixSION_CL5_RdRsp_TimeSlot_REG0 0x1e198
+#define ixSION_CL5_RdRsp_TimeSlot_REG1 0x1e19c
+#define ixSION_CL5_WrRsp_BurstTarget_REG0 0x1e1a0
+#define ixSION_CL5_WrRsp_BurstTarget_REG1 0x1e1a4
+#define ixSION_CL5_WrRsp_TimeSlot_REG0 0x1e1a8
+#define ixSION_CL5_WrRsp_TimeSlot_REG1 0x1e1ac
+#define ixSION_CL5_Req_BurstTarget_REG0 0x1e1b0
+#define ixSION_CL5_Req_BurstTarget_REG1 0x1e1b4
+#define ixSION_CL5_Req_TimeSlot_REG0 0x1e1b8
+#define ixSION_CL5_Req_TimeSlot_REG1 0x1e1bc
+#define ixSION_CL5_ReqPoolCredit_Alloc_REG0 0x1e1c0
+#define ixSION_CL5_ReqPoolCredit_Alloc_REG1 0x1e1c4
+#define ixSION_CL5_DataPoolCredit_Alloc_REG0 0x1e1c8
+#define ixSION_CL5_DataPoolCredit_Alloc_REG1 0x1e1cc
+#define ixSION_CL5_RdRspPoolCredit_Alloc_REG0 0x1e1d0
+#define ixSION_CL5_RdRspPoolCredit_Alloc_REG1 0x1e1d4
+#define ixSION_CL5_WrRspPoolCredit_Alloc_REG0 0x1e1d8
+#define ixSION_CL5_WrRspPoolCredit_Alloc_REG1 0x1e1dc
+#define ixSION_CNTL_REG0 0x1e1e0
+#define ixSION_CNTL_REG1 0x1e1e4
+
+
+// addressBlock: syshub_mmreg_direct_syshubdirect
+// base address: 0x1400000
+#define ixSYSHUB_DS_CTRL_SOCCLK 0x10000 // duplicate
+#define ixSYSHUB_DS_CTRL2_SOCCLK 0x10004 // duplicate
+#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x10008 // duplicate
+#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x1000c // duplicate
+#define ixDMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x10010 // duplicate
+#define ixDMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x10014 // duplicate
+#define ixDMA_CLK0_SW0_CL0_CNTL 0x10018 // duplicate
+#define ixDMA_CLK0_SW0_CL1_CNTL 0x1001c // duplicate
+#define ixDMA_CLK0_SW0_CL2_CNTL 0x10020 // duplicate
+#define ixDMA_CLK0_SW0_CL3_CNTL 0x10024 // duplicate
+#define ixDMA_CLK0_SW0_CL4_CNTL 0x10028 // duplicate
+#define ixDMA_CLK0_SW0_CL5_CNTL 0x1002c // duplicate
+#define ixDMA_CLK0_SW1_CL0_CNTL 0x10030 // duplicate
+#define ixDMA_CLK0_SW2_CL0_CNTL 0x10034 // duplicate
+#define ixSYSHUB_CG_CNTL 0x10300 // duplicate
+#define ixSYSHUB_TRANS_IDLE 0x10308 // duplicate
+#define ixSYSHUB_HP_TIMER 0x1030c // duplicate
+#define ixSYSHUB_SCRATCH 0x10f00 // duplicate
+#define ixSYSHUB_DS_CTRL_SHUBCLK 0x11000 // duplicate
+#define ixSYSHUB_DS_CTRL2_SHUBCLK 0x11004 // duplicate
+#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 0x11008 // duplicate
+#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 0x1100c // duplicate
+#define ixDMA_CLK1_SW0_SYSHUB_QOS_CNTL 0x11010 // duplicate
+#define ixDMA_CLK1_SW1_SYSHUB_QOS_CNTL 0x11014 // duplicate
+#define ixDMA_CLK1_SW0_CL0_CNTL 0x11018 // duplicate
+#define ixDMA_CLK1_SW0_CL1_CNTL 0x1101c // duplicate
+#define ixDMA_CLK1_SW0_CL2_CNTL 0x11020 // duplicate
+#define ixDMA_CLK1_SW0_CL3_CNTL 0x11024 // duplicate
+#define ixDMA_CLK1_SW0_CL4_CNTL 0x11028 // duplicate
+#define ixDMA_CLK1_SW1_CL0_CNTL 0x1102c // duplicate
+#define ixDMA_CLK1_SW1_CL1_CNTL 0x11030 // duplicate
+#define ixDMA_CLK1_SW1_CL2_CNTL 0x11034 // duplicate
+#define ixDMA_CLK1_SW1_CL3_CNTL 0x11038 // duplicate
+#define ixDMA_CLK1_SW1_CL4_CNTL 0x1103c // duplicate
+
+
+// addressBlock: gdc_ras_gdc_ras_regblk
+// base address: 0x1400000
+#define ixGDC_RAS_LEAF0_CTRL 0x1f800
+#define ixGDC_RAS_LEAF1_CTRL 0x1f804
+#define ixGDC_RAS_LEAF2_CTRL 0x1f808
+#define ixGDC_RAS_LEAF3_CTRL 0x1f80c
+#define ixGDC_RAS_LEAF4_CTRL 0x1f810
+#define ixGDC_RAS_LEAF5_CTRL 0x1f814
+
+
+// addressBlock: gdc_rst_GDCRST_DEC
+// base address: 0x1400000
+#define ixSHUB_PF_FLR_RST 0x1f000
+#define ixSHUB_GFX_DRV_MODE1_RST 0x1f004
+#define ixSHUB_LINK_RESET 0x1f008
+#define ixSHUB_PF0_VF_FLR_RST 0x1f020
+#define ixSHUB_HARD_RST_CTRL 0x1f040
+#define ixSHUB_SOFT_RST_CTRL 0x1f044
+#define ixSHUB_SDP_PORT_RST 0x1f048
+
+
+// memoryMap:EP0F0Reg
+
+
+// addressBlock: bif_bx_pf_SYSDEC
+// base address: 0x0
+#define mmSBIOS_SCRATCH_0 0x0048 // duplicate
+#define mmSBIOS_SCRATCH_0_BASE_IDX 0
+#define mmSBIOS_SCRATCH_1 0x0049 // duplicate
+#define mmSBIOS_SCRATCH_1_BASE_IDX 0
+#define mmSBIOS_SCRATCH_2 0x004a // duplicate
+#define mmSBIOS_SCRATCH_2_BASE_IDX 0
+#define mmSBIOS_SCRATCH_3 0x004b // duplicate
+#define mmSBIOS_SCRATCH_3_BASE_IDX 0
+#define mmBIOS_SCRATCH_0 0x004c // duplicate
+#define mmBIOS_SCRATCH_0_BASE_IDX 0
+#define mmBIOS_SCRATCH_1 0x004d // duplicate
+#define mmBIOS_SCRATCH_1_BASE_IDX 0
+#define mmBIOS_SCRATCH_2 0x004e // duplicate
+#define mmBIOS_SCRATCH_2_BASE_IDX 0
+#define mmBIOS_SCRATCH_3 0x004f // duplicate
+#define mmBIOS_SCRATCH_3_BASE_IDX 0
+#define mmBIOS_SCRATCH_4 0x0050 // duplicate
+#define mmBIOS_SCRATCH_4_BASE_IDX 0
+#define mmBIOS_SCRATCH_5 0x0051 // duplicate
+#define mmBIOS_SCRATCH_5_BASE_IDX 0
+#define mmBIOS_SCRATCH_6 0x0052 // duplicate
+#define mmBIOS_SCRATCH_6_BASE_IDX 0
+#define mmBIOS_SCRATCH_7 0x0053 // duplicate
+#define mmBIOS_SCRATCH_7_BASE_IDX 0
+#define mmBIOS_SCRATCH_8 0x0054 // duplicate
+#define mmBIOS_SCRATCH_8_BASE_IDX 0
+#define mmBIOS_SCRATCH_9 0x0055 // duplicate
+#define mmBIOS_SCRATCH_9_BASE_IDX 0
+#define mmBIOS_SCRATCH_10 0x0056 // duplicate
+#define mmBIOS_SCRATCH_10_BASE_IDX 0
+#define mmBIOS_SCRATCH_11 0x0057 // duplicate
+#define mmBIOS_SCRATCH_11_BASE_IDX 0
+#define mmBIOS_SCRATCH_12 0x0058 // duplicate
+#define mmBIOS_SCRATCH_12_BASE_IDX 0
+#define mmBIOS_SCRATCH_13 0x0059 // duplicate
+#define mmBIOS_SCRATCH_13_BASE_IDX 0
+#define mmBIOS_SCRATCH_14 0x005a // duplicate
+#define mmBIOS_SCRATCH_14_BASE_IDX 0
+#define mmBIOS_SCRATCH_15 0x005b // duplicate
+#define mmBIOS_SCRATCH_15_BASE_IDX 0
+#define mmBIF_RLC_INTR_CNTL 0x0060 // duplicate
+#define mmBIF_RLC_INTR_CNTL_BASE_IDX 0
+#define mmBIF_VCE_INTR_CNTL 0x0061 // duplicate
+#define mmBIF_VCE_INTR_CNTL_BASE_IDX 0
+#define mmBIF_UVD_INTR_CNTL 0x0062 // duplicate
+#define mmBIF_UVD_INTR_CNTL_BASE_IDX 0
+#define mmGFX_MMIOREG_CAM_ADDR0 0x0080 // duplicate
+#define mmGFX_MMIOREG_CAM_ADDR0_BASE_IDX 0
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR0 0x0081 // duplicate
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 0
+#define mmGFX_MMIOREG_CAM_ADDR1 0x0082 // duplicate
+#define mmGFX_MMIOREG_CAM_ADDR1_BASE_IDX 0
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR1 0x0083 // duplicate
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 0
+#define mmGFX_MMIOREG_CAM_ADDR2 0x0084 // duplicate
+#define mmGFX_MMIOREG_CAM_ADDR2_BASE_IDX 0
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR2 0x0085 // duplicate
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 0
+#define mmGFX_MMIOREG_CAM_ADDR3 0x0086 // duplicate
+#define mmGFX_MMIOREG_CAM_ADDR3_BASE_IDX 0
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR3 0x0087 // duplicate
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 0
+#define mmGFX_MMIOREG_CAM_ADDR4 0x0088 // duplicate
+#define mmGFX_MMIOREG_CAM_ADDR4_BASE_IDX 0
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR4 0x0089 // duplicate
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 0
+#define mmGFX_MMIOREG_CAM_ADDR5 0x008a // duplicate
+#define mmGFX_MMIOREG_CAM_ADDR5_BASE_IDX 0
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR5 0x008b // duplicate
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 0
+#define mmGFX_MMIOREG_CAM_ADDR6 0x008c // duplicate
+#define mmGFX_MMIOREG_CAM_ADDR6_BASE_IDX 0
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR6 0x008d // duplicate
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 0
+#define mmGFX_MMIOREG_CAM_ADDR7 0x008e // duplicate
+#define mmGFX_MMIOREG_CAM_ADDR7_BASE_IDX 0
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR7 0x008f // duplicate
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 0
+#define mmGFX_MMIOREG_CAM_CNTL 0x0090 // duplicate
+#define mmGFX_MMIOREG_CAM_CNTL_BASE_IDX 0
+#define mmGFX_MMIOREG_CAM_ZERO_CPL 0x0091 // duplicate
+#define mmGFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 0
+#define mmGFX_MMIOREG_CAM_ONE_CPL 0x0092 // duplicate
+#define mmGFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 0
+#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x0093 // duplicate
+#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 0
+
+
+// addressBlock: bif_bx_pf_SYSPFVFDEC
+// base address: 0x0
+#define mmMM_INDEX 0x0000 // duplicate
+#define mmMM_INDEX_BASE_IDX 0
+#define mmMM_DATA 0x0001 // duplicate
+#define mmMM_DATA_BASE_IDX 0
+#define mmMM_INDEX_HI 0x0006 // duplicate
+#define mmMM_INDEX_HI_BASE_IDX 0
+#define mmSYSHUB_INDEX_OVLP 0x0008 // duplicate
+#define mmSYSHUB_INDEX_OVLP_BASE_IDX 0
+#define mmSYSHUB_DATA_OVLP 0x0009 // duplicate
+#define mmSYSHUB_DATA_OVLP_BASE_IDX 0
+#define mmPCIE_INDEX 0x000c // duplicate
+#define mmPCIE_INDEX_BASE_IDX 0
+#define mmPCIE_DATA 0x000d // duplicate
+#define mmPCIE_DATA_BASE_IDX 0
+#define mmPCIE_INDEX2 0x000e // duplicate
+#define mmPCIE_INDEX2_BASE_IDX 0
+#define mmPCIE_DATA2 0x000f // duplicate
+#define mmPCIE_DATA2_BASE_IDX 0
+
+
+// addressBlock: rcc_dwn_BIFDEC1
+// base address: 0x0
+#define mmDN_PCIE_RESERVED 0x0d60 // duplicate
+#define mmDN_PCIE_RESERVED_BASE_IDX 0
+#define mmDN_PCIE_SCRATCH 0x0d61 // duplicate
+#define mmDN_PCIE_SCRATCH_BASE_IDX 0
+#define mmDN_PCIE_CNTL 0x0d63 // duplicate
+#define mmDN_PCIE_CNTL_BASE_IDX 0
+#define mmDN_PCIE_CONFIG_CNTL 0x0d64 // duplicate
+#define mmDN_PCIE_CONFIG_CNTL_BASE_IDX 0
+#define mmDN_PCIE_RX_CNTL2 0x0d65 // duplicate
+#define mmDN_PCIE_RX_CNTL2_BASE_IDX 0
+#define mmDN_PCIE_BUS_CNTL 0x0d66 // duplicate
+#define mmDN_PCIE_BUS_CNTL_BASE_IDX 0
+#define mmDN_PCIE_CFG_CNTL 0x0d67 // duplicate
+#define mmDN_PCIE_CFG_CNTL_BASE_IDX 0
+#define mmDN_PCIE_STRAP_F0 0x0d68 // duplicate
+#define mmDN_PCIE_STRAP_F0_BASE_IDX 0
+#define mmDN_PCIE_STRAP_MISC 0x0d69 // duplicate
+#define mmDN_PCIE_STRAP_MISC_BASE_IDX 0
+#define mmDN_PCIE_STRAP_MISC2 0x0d6a // duplicate
+#define mmDN_PCIE_STRAP_MISC2_BASE_IDX 0
+
+
+// addressBlock: rcc_dwnp_BIFDEC1
+// base address: 0x0
+#define mmPCIEP_RESERVED 0x0d6c // duplicate
+#define mmPCIEP_RESERVED_BASE_IDX 0
+#define mmPCIEP_SCRATCH 0x0d6d // duplicate
+#define mmPCIEP_SCRATCH_BASE_IDX 0
+#define mmPCIE_ERR_CNTL 0x0d6f // duplicate
+#define mmPCIE_ERR_CNTL_BASE_IDX 0
+#define mmPCIE_RX_CNTL 0x0d70 // duplicate
+#define mmPCIE_RX_CNTL_BASE_IDX 0
+#define mmPCIE_LC_SPEED_CNTL 0x0d71 // duplicate
+#define mmPCIE_LC_SPEED_CNTL_BASE_IDX 0
+#define mmPCIE_LC_CNTL2 0x0d72 // duplicate
+#define mmPCIE_LC_CNTL2_BASE_IDX 0
+#define mmPCIEP_STRAP_MISC 0x0d73 // duplicate
+#define mmPCIEP_STRAP_MISC_BASE_IDX 0
+#define mmLTR_MSG_INFO_FROM_EP 0x0d74 // duplicate
+#define mmLTR_MSG_INFO_FROM_EP_BASE_IDX 0
+
+
+// addressBlock: rcc_ep_BIFDEC1
+// base address: 0x0
+#define mmEP_PCIE_SCRATCH 0x0d43 // duplicate
+#define mmEP_PCIE_SCRATCH_BASE_IDX 0
+#define mmEP_PCIE_CNTL 0x0d45 // duplicate
+#define mmEP_PCIE_CNTL_BASE_IDX 0
+#define mmEP_PCIE_INT_CNTL 0x0d46 // duplicate
+#define mmEP_PCIE_INT_CNTL_BASE_IDX 0
+#define mmEP_PCIE_INT_STATUS 0x0d47 // duplicate
+#define mmEP_PCIE_INT_STATUS_BASE_IDX 0
+#define mmEP_PCIE_RX_CNTL2 0x0d48 // duplicate
+#define mmEP_PCIE_RX_CNTL2_BASE_IDX 0
+#define mmEP_PCIE_BUS_CNTL 0x0d49 // duplicate
+#define mmEP_PCIE_BUS_CNTL_BASE_IDX 0
+#define mmEP_PCIE_CFG_CNTL 0x0d4a // duplicate
+#define mmEP_PCIE_CFG_CNTL_BASE_IDX 0
+#define mmEP_PCIE_OBFF_CNTL 0x0d4b // duplicate
+#define mmEP_PCIE_OBFF_CNTL_BASE_IDX 0
+#define mmEP_PCIE_TX_LTR_CNTL 0x0d4c // duplicate
+#define mmEP_PCIE_TX_LTR_CNTL_BASE_IDX 0
+#define mmEP_PCIE_STRAP_MISC 0x0d4f // duplicate
+#define mmEP_PCIE_STRAP_MISC_BASE_IDX 0
+#define mmEP_PCIE_STRAP_MISC2 0x0d50 // duplicate
+#define mmEP_PCIE_STRAP_MISC2_BASE_IDX 0
+#define mmEP_PCIE_STRAP_PI 0x0d51 // duplicate
+#define mmEP_PCIE_STRAP_PI_BASE_IDX 0
+#define mmEP_PCIE_F0_DPA_CAP 0x0d52 // duplicate
+#define mmEP_PCIE_F0_DPA_CAP_BASE_IDX 0
+#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0d53 // duplicate
+#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 0
+#define mmEP_PCIE_F0_DPA_CNTL 0x0d53 // duplicate
+#define mmEP_PCIE_F0_DPA_CNTL_BASE_IDX 0
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0d53 // duplicate
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 0
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0d54 // duplicate
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 0
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0d54 // duplicate
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 0
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0d54 // duplicate
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 0
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0d54 // duplicate
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 0
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0d55 // duplicate
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 0
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0d55 // duplicate
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 0
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0d55 // duplicate
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 0
+#define mmEP_PCIE_PME_CONTROL 0x0d55 // duplicate
+#define mmEP_PCIE_PME_CONTROL_BASE_IDX 0
+#define mmEP_PCIEP_RESERVED 0x0d56 // duplicate
+#define mmEP_PCIEP_RESERVED_BASE_IDX 0
+#define mmEP_PCIE_TX_CNTL 0x0d58 // duplicate
+#define mmEP_PCIE_TX_CNTL_BASE_IDX 0
+#define mmEP_PCIE_TX_REQUESTER_ID 0x0d59 // duplicate
+#define mmEP_PCIE_TX_REQUESTER_ID_BASE_IDX 0
+#define mmEP_PCIE_ERR_CNTL 0x0d5a // duplicate
+#define mmEP_PCIE_ERR_CNTL_BASE_IDX 0
+#define mmEP_PCIE_RX_CNTL 0x0d5b // duplicate
+#define mmEP_PCIE_RX_CNTL_BASE_IDX 0
+#define mmEP_PCIE_LC_SPEED_CNTL 0x0d5c // duplicate
+#define mmEP_PCIE_LC_SPEED_CNTL_BASE_IDX 0
+
+
+// addressBlock: bif_bx_pf_BIFDEC1
+// base address: 0x0
+#define mmBIF_MM_INDACCESS_CNTL 0x0e06 // duplicate
+#define mmBIF_MM_INDACCESS_CNTL_BASE_IDX 0
+#define mmBUS_CNTL 0x0e07 // duplicate
+#define mmBUS_CNTL_BASE_IDX 0
+#define mmBIF_SCRATCH0 0x0e08 // duplicate
+#define mmBIF_SCRATCH0_BASE_IDX 0
+#define mmBIF_SCRATCH1 0x0e09 // duplicate
+#define mmBIF_SCRATCH1_BASE_IDX 0
+#define mmBX_RESET_EN 0x0e0d // duplicate
+#define mmBX_RESET_EN_BASE_IDX 0
+#define mmMM_CFGREGS_CNTL 0x0e0e // duplicate
+#define mmMM_CFGREGS_CNTL_BASE_IDX 0
+#define mmBX_RESET_CNTL 0x0e10 // duplicate
+#define mmBX_RESET_CNTL_BASE_IDX 0
+#define mmINTERRUPT_CNTL 0x0e11 // duplicate
+#define mmINTERRUPT_CNTL_BASE_IDX 0
+#define mmINTERRUPT_CNTL2 0x0e12 // duplicate
+#define mmINTERRUPT_CNTL2_BASE_IDX 0
+#define mmCLKREQB_PAD_CNTL 0x0e18 // duplicate
+#define mmCLKREQB_PAD_CNTL_BASE_IDX 0
+#define mmCLKREQB_PERF_COUNTER 0x0e19 // duplicate
+#define mmCLKREQB_PERF_COUNTER_BASE_IDX 0
+#define mmBIF_CLK_CTRL 0x0e1a // duplicate
+#define mmBIF_CLK_CTRL_BASE_IDX 0
+#define mmBIF_FEATURES_CONTROL_MISC 0x0e1b // duplicate
+#define mmBIF_FEATURES_CONTROL_MISC_BASE_IDX 0
+#define mmBIF_DOORBELL_CNTL 0x0e1c // duplicate
+#define mmBIF_DOORBELL_CNTL_BASE_IDX 0
+#define mmBIF_DOORBELL_INT_CNTL 0x0e1d // duplicate
+#define mmBIF_DOORBELL_INT_CNTL_BASE_IDX 0
+#define mmBIF_SLVARB_MODE 0x0e1e // duplicate
+#define mmBIF_SLVARB_MODE_BASE_IDX 0
+#define mmBIF_FB_EN 0x0e1f // duplicate
+#define mmBIF_FB_EN_BASE_IDX 0
+#define mmBIF_BUSY_DELAY_CNTR 0x0e20 // duplicate
+#define mmBIF_BUSY_DELAY_CNTR_BASE_IDX 0
+#define mmBIF_PERFMON_CNTL 0x0e21 // duplicate
+#define mmBIF_PERFMON_CNTL_BASE_IDX 0
+#define mmBIF_PERFCOUNTER0_RESULT 0x0e22 // duplicate
+#define mmBIF_PERFCOUNTER0_RESULT_BASE_IDX 0
+#define mmBIF_PERFCOUNTER1_RESULT 0x0e23 // duplicate
+#define mmBIF_PERFCOUNTER1_RESULT_BASE_IDX 0
+#define mmBIF_MST_TRANS_PENDING_VF 0x0e29 // duplicate
+#define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX 0
+#define mmBIF_SLV_TRANS_PENDING_VF 0x0e2a // duplicate
+#define mmBIF_SLV_TRANS_PENDING_VF_BASE_IDX 0
+#define mmBACO_CNTL 0x0e2b // duplicate
+#define mmBACO_CNTL_BASE_IDX 0
+#define mmBIF_BACO_EXIT_TIME0 0x0e2c // duplicate
+#define mmBIF_BACO_EXIT_TIME0_BASE_IDX 0
+#define mmBIF_BACO_EXIT_TIMER1 0x0e2d // duplicate
+#define mmBIF_BACO_EXIT_TIMER1_BASE_IDX 0
+#define mmBIF_BACO_EXIT_TIMER2 0x0e2e // duplicate
+#define mmBIF_BACO_EXIT_TIMER2_BASE_IDX 0
+#define mmBIF_BACO_EXIT_TIMER3 0x0e2f // duplicate
+#define mmBIF_BACO_EXIT_TIMER3_BASE_IDX 0
+#define mmBIF_BACO_EXIT_TIMER4 0x0e30 // duplicate
+#define mmBIF_BACO_EXIT_TIMER4_BASE_IDX 0
+#define mmMEM_TYPE_CNTL 0x0e31 // duplicate
+#define mmMEM_TYPE_CNTL_BASE_IDX 0
+#define mmSMU_BIF_VDDGFX_PWR_STATUS 0x0e33 // duplicate
+#define mmSMU_BIF_VDDGFX_PWR_STATUS_BASE_IDX 0
+#define mmBIF_VDDGFX_GFX0_LOWER 0x0e34 // duplicate
+#define mmBIF_VDDGFX_GFX0_LOWER_BASE_IDX 0
+#define mmBIF_VDDGFX_GFX0_UPPER 0x0e35 // duplicate
+#define mmBIF_VDDGFX_GFX0_UPPER_BASE_IDX 0
+#define mmBIF_VDDGFX_GFX1_LOWER 0x0e36 // duplicate
+#define mmBIF_VDDGFX_GFX1_LOWER_BASE_IDX 0
+#define mmBIF_VDDGFX_GFX1_UPPER 0x0e37 // duplicate
+#define mmBIF_VDDGFX_GFX1_UPPER_BASE_IDX 0
+#define mmBIF_VDDGFX_GFX2_LOWER 0x0e38 // duplicate
+#define mmBIF_VDDGFX_GFX2_LOWER_BASE_IDX 0
+#define mmBIF_VDDGFX_GFX2_UPPER 0x0e39 // duplicate
+#define mmBIF_VDDGFX_GFX2_UPPER_BASE_IDX 0
+#define mmBIF_VDDGFX_GFX3_LOWER 0x0e3a // duplicate
+#define mmBIF_VDDGFX_GFX3_LOWER_BASE_IDX 0
+#define mmBIF_VDDGFX_GFX3_UPPER 0x0e3b // duplicate
+#define mmBIF_VDDGFX_GFX3_UPPER_BASE_IDX 0
+#define mmBIF_VDDGFX_GFX4_LOWER 0x0e3c // duplicate
+#define mmBIF_VDDGFX_GFX4_LOWER_BASE_IDX 0
+#define mmBIF_VDDGFX_GFX4_UPPER 0x0e3d // duplicate
+#define mmBIF_VDDGFX_GFX4_UPPER_BASE_IDX 0
+#define mmBIF_VDDGFX_GFX5_LOWER 0x0e3e // duplicate
+#define mmBIF_VDDGFX_GFX5_LOWER_BASE_IDX 0
+#define mmBIF_VDDGFX_GFX5_UPPER 0x0e3f // duplicate
+#define mmBIF_VDDGFX_GFX5_UPPER_BASE_IDX 0
+#define mmBIF_VDDGFX_RSV1_LOWER 0x0e40 // duplicate
+#define mmBIF_VDDGFX_RSV1_LOWER_BASE_IDX 0
+#define mmBIF_VDDGFX_RSV1_UPPER 0x0e41 // duplicate
+#define mmBIF_VDDGFX_RSV1_UPPER_BASE_IDX 0
+#define mmBIF_VDDGFX_RSV2_LOWER 0x0e42 // duplicate
+#define mmBIF_VDDGFX_RSV2_LOWER_BASE_IDX 0
+#define mmBIF_VDDGFX_RSV2_UPPER 0x0e43 // duplicate
+#define mmBIF_VDDGFX_RSV2_UPPER_BASE_IDX 0
+#define mmBIF_VDDGFX_RSV3_LOWER 0x0e44 // duplicate
+#define mmBIF_VDDGFX_RSV3_LOWER_BASE_IDX 0
+#define mmBIF_VDDGFX_RSV3_UPPER 0x0e45 // duplicate
+#define mmBIF_VDDGFX_RSV3_UPPER_BASE_IDX 0
+#define mmBIF_VDDGFX_RSV4_LOWER 0x0e46 // duplicate
+#define mmBIF_VDDGFX_RSV4_LOWER_BASE_IDX 0
+#define mmBIF_VDDGFX_RSV4_UPPER 0x0e47 // duplicate
+#define mmBIF_VDDGFX_RSV4_UPPER_BASE_IDX 0
+#define mmBIF_VDDGFX_FB_CMP 0x0e48 // duplicate
+#define mmBIF_VDDGFX_FB_CMP_BASE_IDX 0
+#define mmBIF_DOORBELL_GBLAPER1_LOWER 0x0e49 // duplicate
+#define mmBIF_DOORBELL_GBLAPER1_LOWER_BASE_IDX 0
+#define mmBIF_DOORBELL_GBLAPER1_UPPER 0x0e4a // duplicate
+#define mmBIF_DOORBELL_GBLAPER1_UPPER_BASE_IDX 0
+#define mmBIF_DOORBELL_GBLAPER2_LOWER 0x0e4b // duplicate
+#define mmBIF_DOORBELL_GBLAPER2_LOWER_BASE_IDX 0
+#define mmBIF_DOORBELL_GBLAPER2_UPPER 0x0e4c // duplicate
+#define mmBIF_DOORBELL_GBLAPER2_UPPER_BASE_IDX 0
+#define mmREMAP_HDP_MEM_FLUSH_CNTL 0x0e4d // duplicate
+#define mmREMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 0
+#define mmREMAP_HDP_REG_FLUSH_CNTL 0x0e4e // duplicate
+#define mmREMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 0
+#define mmBIF_RB_CNTL 0x0e4f // duplicate
+#define mmBIF_RB_CNTL_BASE_IDX 0
+#define mmBIF_RB_BASE 0x0e50 // duplicate
+#define mmBIF_RB_BASE_BASE_IDX 0
+#define mmBIF_RB_RPTR 0x0e51 // duplicate
+#define mmBIF_RB_RPTR_BASE_IDX 0
+#define mmBIF_RB_WPTR 0x0e52 // duplicate
+#define mmBIF_RB_WPTR_BASE_IDX 0
+#define mmBIF_RB_WPTR_ADDR_HI 0x0e53 // duplicate
+#define mmBIF_RB_WPTR_ADDR_HI_BASE_IDX 0
+#define mmBIF_RB_WPTR_ADDR_LO 0x0e54 // duplicate
+#define mmBIF_RB_WPTR_ADDR_LO_BASE_IDX 0
+#define mmMAILBOX_INDEX 0x0e55 // duplicate
+#define mmMAILBOX_INDEX_BASE_IDX 0
+#define mmBIF_GPUIOV_RESET_NOTIFICATION 0x0e62 // duplicate
+#define mmBIF_GPUIOV_RESET_NOTIFICATION_BASE_IDX 0
+#define mmBIF_UVD_GPUIOV_CFG_SIZE 0x0e63 // duplicate
+#define mmBIF_UVD_GPUIOV_CFG_SIZE_BASE_IDX 0
+#define mmBIF_VCE_GPUIOV_CFG_SIZE 0x0e64 // duplicate
+#define mmBIF_VCE_GPUIOV_CFG_SIZE_BASE_IDX 0
+#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x0e65 // duplicate
+#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 0
+#define mmBIF_GMI_WRR_WEIGHT 0x0e66 // duplicate
+#define mmBIF_GMI_WRR_WEIGHT_BASE_IDX 0
+#define mmNBIF_STRAP_WRITE_CTRL 0x0e67 // duplicate
+#define mmNBIF_STRAP_WRITE_CTRL_BASE_IDX 0
+#define mmBIF_PERSTB_PAD_CNTL 0x0e68 // duplicate
+#define mmBIF_PERSTB_PAD_CNTL_BASE_IDX 0
+#define mmBIF_PX_EN_PAD_CNTL 0x0e69 // duplicate
+#define mmBIF_PX_EN_PAD_CNTL_BASE_IDX 0
+#define mmBIF_REFPADKIN_PAD_CNTL 0x0e6a // duplicate
+#define mmBIF_REFPADKIN_PAD_CNTL_BASE_IDX 0
+#define mmBIF_CLKREQB_PAD_CNTL 0x0e6b // duplicate
+#define mmBIF_CLKREQB_PAD_CNTL_BASE_IDX 0
+
+
+// addressBlock: rcc_pf_0_BIFDEC1
+// base address: 0x0
+#define mmRCC_BACO_CNTL_MISC 0x0da7 // duplicate
+#define mmRCC_BACO_CNTL_MISC_BASE_IDX 0
+#define mmRCC_RESET_EN 0x0da8 // duplicate
+#define mmRCC_RESET_EN_BASE_IDX 0
+#define mmRCC_VDM_SUPPORT 0x0da9 // duplicate
+#define mmRCC_VDM_SUPPORT_BASE_IDX 0
+#define mmRCC_PEER_REG_RANGE0 0x0dde // duplicate
+#define mmRCC_PEER_REG_RANGE0_BASE_IDX 0
+#define mmRCC_PEER_REG_RANGE1 0x0ddf // duplicate
+#define mmRCC_PEER_REG_RANGE1_BASE_IDX 0
+#define mmRCC_BUS_CNTL 0x0de1 // duplicate
+#define mmRCC_BUS_CNTL_BASE_IDX 0
+#define mmRCC_CONFIG_CNTL 0x0de2 // duplicate
+#define mmRCC_CONFIG_CNTL_BASE_IDX 0
+#define mmRCC_CONFIG_F0_BASE 0x0de6 // duplicate
+#define mmRCC_CONFIG_F0_BASE_BASE_IDX 0
+#define mmRCC_CONFIG_APER_SIZE 0x0de7 // duplicate
+#define mmRCC_CONFIG_APER_SIZE_BASE_IDX 0
+#define mmRCC_CONFIG_REG_APER_SIZE 0x0de8 // duplicate
+#define mmRCC_CONFIG_REG_APER_SIZE_BASE_IDX 0
+#define mmRCC_XDMA_LO 0x0de9 // duplicate
+#define mmRCC_XDMA_LO_BASE_IDX 0
+#define mmRCC_XDMA_HI 0x0dea // duplicate
+#define mmRCC_XDMA_HI_BASE_IDX 0
+#define mmRCC_FEATURES_CONTROL_MISC 0x0deb // duplicate
+#define mmRCC_FEATURES_CONTROL_MISC_BASE_IDX 0
+#define mmRCC_BUSNUM_CNTL1 0x0dec // duplicate
+#define mmRCC_BUSNUM_CNTL1_BASE_IDX 0
+#define mmRCC_BUSNUM_LIST0 0x0ded // duplicate
+#define mmRCC_BUSNUM_LIST0_BASE_IDX 0
+#define mmRCC_BUSNUM_LIST1 0x0dee // duplicate
+#define mmRCC_BUSNUM_LIST1_BASE_IDX 0
+#define mmRCC_BUSNUM_CNTL2 0x0def // duplicate
+#define mmRCC_BUSNUM_CNTL2_BASE_IDX 0
+#define mmRCC_CAPTURE_HOST_BUSNUM 0x0df0 // duplicate
+#define mmRCC_CAPTURE_HOST_BUSNUM_BASE_IDX 0
+#define mmRCC_HOST_BUSNUM 0x0df1 // duplicate
+#define mmRCC_HOST_BUSNUM_BASE_IDX 0
+#define mmRCC_PEER0_FB_OFFSET_HI 0x0df2 // duplicate
+#define mmRCC_PEER0_FB_OFFSET_HI_BASE_IDX 0
+#define mmRCC_PEER0_FB_OFFSET_LO 0x0df3 // duplicate
+#define mmRCC_PEER0_FB_OFFSET_LO_BASE_IDX 0
+#define mmRCC_PEER1_FB_OFFSET_HI 0x0df4 // duplicate
+#define mmRCC_PEER1_FB_OFFSET_HI_BASE_IDX 0
+#define mmRCC_PEER1_FB_OFFSET_LO 0x0df5 // duplicate
+#define mmRCC_PEER1_FB_OFFSET_LO_BASE_IDX 0
+#define mmRCC_PEER2_FB_OFFSET_HI 0x0df6 // duplicate
+#define mmRCC_PEER2_FB_OFFSET_HI_BASE_IDX 0
+#define mmRCC_PEER2_FB_OFFSET_LO 0x0df7 // duplicate
+#define mmRCC_PEER2_FB_OFFSET_LO_BASE_IDX 0
+#define mmRCC_PEER3_FB_OFFSET_HI 0x0df8 // duplicate
+#define mmRCC_PEER3_FB_OFFSET_HI_BASE_IDX 0
+#define mmRCC_PEER3_FB_OFFSET_LO 0x0df9 // duplicate
+#define mmRCC_PEER3_FB_OFFSET_LO_BASE_IDX 0
+#define mmRCC_DEVFUNCNUM_LIST0 0x0dfa // duplicate
+#define mmRCC_DEVFUNCNUM_LIST0_BASE_IDX 0
+#define mmRCC_DEVFUNCNUM_LIST1 0x0dfb // duplicate
+#define mmRCC_DEVFUNCNUM_LIST1_BASE_IDX 0
+#define mmRCC_DEV0_LINK_CNTL 0x0dfd // duplicate
+#define mmRCC_DEV0_LINK_CNTL_BASE_IDX 0
+#define mmRCC_CMN_LINK_CNTL 0x0dfe // duplicate
+#define mmRCC_CMN_LINK_CNTL_BASE_IDX 0
+#define mmRCC_EP_REQUESTERID_RESTORE 0x0dff // duplicate
+#define mmRCC_EP_REQUESTERID_RESTORE_BASE_IDX 0
+#define mmRCC_LTR_LSWITCH_CNTL 0x0e00 // duplicate
+#define mmRCC_LTR_LSWITCH_CNTL_BASE_IDX 0
+#define mmRCC_MH_ARB_CNTL 0x0e01 // duplicate
+#define mmRCC_MH_ARB_CNTL_BASE_IDX 0
+
+
+// addressBlock: rcc_pf_0_BIFDEC2
+// base address: 0x0
+#define mmGFXMSIX_VECT0_ADDR_LO 0x10800 // duplicate
+#define mmGFXMSIX_VECT0_ADDR_LO_BASE_IDX 0
+#define mmGFXMSIX_VECT0_ADDR_HI 0x10801 // duplicate
+#define mmGFXMSIX_VECT0_ADDR_HI_BASE_IDX 0
+#define mmGFXMSIX_VECT0_MSG_DATA 0x10802 // duplicate
+#define mmGFXMSIX_VECT0_MSG_DATA_BASE_IDX 0
+#define mmGFXMSIX_VECT0_CONTROL 0x10803 // duplicate
+#define mmGFXMSIX_VECT0_CONTROL_BASE_IDX 0
+#define mmGFXMSIX_VECT1_ADDR_LO 0x10804 // duplicate
+#define mmGFXMSIX_VECT1_ADDR_LO_BASE_IDX 0
+#define mmGFXMSIX_VECT1_ADDR_HI 0x10805 // duplicate
+#define mmGFXMSIX_VECT1_ADDR_HI_BASE_IDX 0
+#define mmGFXMSIX_VECT1_MSG_DATA 0x10806 // duplicate
+#define mmGFXMSIX_VECT1_MSG_DATA_BASE_IDX 0
+#define mmGFXMSIX_VECT1_CONTROL 0x10807 // duplicate
+#define mmGFXMSIX_VECT1_CONTROL_BASE_IDX 0
+#define mmGFXMSIX_VECT2_ADDR_LO 0x10808 // duplicate
+#define mmGFXMSIX_VECT2_ADDR_LO_BASE_IDX 0
+#define mmGFXMSIX_VECT2_ADDR_HI 0x10809 // duplicate
+#define mmGFXMSIX_VECT2_ADDR_HI_BASE_IDX 0
+#define mmGFXMSIX_VECT2_MSG_DATA 0x1080a // duplicate
+#define mmGFXMSIX_VECT2_MSG_DATA_BASE_IDX 0
+#define mmGFXMSIX_VECT2_CONTROL 0x1080b // duplicate
+#define mmGFXMSIX_VECT2_CONTROL_BASE_IDX 0
+#define mmGFXMSIX_PBA 0x10c00 // duplicate
+#define mmGFXMSIX_PBA_BASE_IDX 0
+
+
+// addressBlock: rcc_strap_BIFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_PORT_STRAP0 0x0d27 // duplicate
+#define mmRCC_DEV0_PORT_STRAP0_BASE_IDX 0
+#define mmRCC_DEV0_PORT_STRAP1 0x0d28 // duplicate
+#define mmRCC_DEV0_PORT_STRAP1_BASE_IDX 0
+#define mmRCC_DEV0_PORT_STRAP2 0x0d29 // duplicate
+#define mmRCC_DEV0_PORT_STRAP2_BASE_IDX 0
+#define mmRCC_DEV0_PORT_STRAP3 0x0d2a // duplicate
+#define mmRCC_DEV0_PORT_STRAP3_BASE_IDX 0
+#define mmRCC_DEV0_PORT_STRAP4 0x0d2b // duplicate
+#define mmRCC_DEV0_PORT_STRAP4_BASE_IDX 0
+#define mmRCC_DEV0_PORT_STRAP5 0x0d2c // duplicate
+#define mmRCC_DEV0_PORT_STRAP5_BASE_IDX 0
+#define mmRCC_DEV0_PORT_STRAP6 0x0d2d // duplicate
+#define mmRCC_DEV0_PORT_STRAP6_BASE_IDX 0
+#define mmRCC_DEV0_PORT_STRAP7 0x0d2e // duplicate
+#define mmRCC_DEV0_PORT_STRAP7_BASE_IDX 0
+#define mmRCC_DEV0_EPF0_STRAP0 0x0d2f // duplicate
+#define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX 0
+#define mmRCC_DEV0_EPF0_STRAP1 0x0d30 // duplicate
+#define mmRCC_DEV0_EPF0_STRAP1_BASE_IDX 0
+#define mmRCC_DEV0_EPF0_STRAP13 0x0d31 // duplicate
+#define mmRCC_DEV0_EPF0_STRAP13_BASE_IDX 0
+#define mmRCC_DEV0_EPF0_STRAP2 0x0d32 // duplicate
+#define mmRCC_DEV0_EPF0_STRAP2_BASE_IDX 0
+#define mmRCC_DEV0_EPF0_STRAP3 0x0d33 // duplicate
+#define mmRCC_DEV0_EPF0_STRAP3_BASE_IDX 0
+#define mmRCC_DEV0_EPF0_STRAP4 0x0d34 // duplicate
+#define mmRCC_DEV0_EPF0_STRAP4_BASE_IDX 0
+#define mmRCC_DEV0_EPF0_STRAP5 0x0d35 // duplicate
+#define mmRCC_DEV0_EPF0_STRAP5_BASE_IDX 0
+#define mmRCC_DEV0_EPF0_STRAP8 0x0d36 // duplicate
+#define mmRCC_DEV0_EPF0_STRAP8_BASE_IDX 0
+#define mmRCC_DEV0_EPF0_STRAP9 0x0d37 // duplicate
+#define mmRCC_DEV0_EPF0_STRAP9_BASE_IDX 0
+#define mmRCC_DEV0_EPF1_STRAP0 0x0d38 // duplicate
+#define mmRCC_DEV0_EPF1_STRAP0_BASE_IDX 0
+#define mmRCC_DEV0_EPF1_STRAP10 0x0d39 // duplicate
+#define mmRCC_DEV0_EPF1_STRAP10_BASE_IDX 0
+#define mmRCC_DEV0_EPF1_STRAP11 0x0d3a // duplicate
+#define mmRCC_DEV0_EPF1_STRAP11_BASE_IDX 0
+#define mmRCC_DEV0_EPF1_STRAP12 0x0d3b // duplicate
+#define mmRCC_DEV0_EPF1_STRAP12_BASE_IDX 0
+#define mmRCC_DEV0_EPF1_STRAP13 0x0d3c // duplicate
+#define mmRCC_DEV0_EPF1_STRAP13_BASE_IDX 0
+#define mmRCC_DEV0_EPF1_STRAP2 0x0d3d // duplicate
+#define mmRCC_DEV0_EPF1_STRAP2_BASE_IDX 0
+#define mmRCC_DEV0_EPF1_STRAP3 0x0d3e // duplicate
+#define mmRCC_DEV0_EPF1_STRAP3_BASE_IDX 0
+#define mmRCC_DEV0_EPF1_STRAP4 0x0d3f // duplicate
+#define mmRCC_DEV0_EPF1_STRAP4_BASE_IDX 0
+#define mmRCC_DEV0_EPF1_STRAP5 0x0d40 // duplicate
+#define mmRCC_DEV0_EPF1_STRAP5_BASE_IDX 0
+#define mmRCC_DEV0_EPF1_STRAP6 0x0d41 // duplicate
+#define mmRCC_DEV0_EPF1_STRAP6_BASE_IDX 0
+#define mmRCC_DEV0_EPF1_STRAP7 0x0d42 // duplicate
+#define mmRCC_DEV0_EPF1_STRAP7_BASE_IDX 0
+
+
+// addressBlock: bif_bx_pf_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BME_STATUS 0x0e0b // duplicate
+#define mmBIF_BME_STATUS_BASE_IDX 0
+#define mmBIF_ATOMIC_ERR_LOG 0x0e0c // duplicate
+#define mmBIF_ATOMIC_ERR_LOG_BASE_IDX 0
+#define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0e13 // duplicate
+#define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 0
+#define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0e14 // duplicate
+#define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 0
+#define mmDOORBELL_SELFRING_GPA_APER_CNTL 0x0e15 // duplicate
+#define mmDOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 0
+#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x0e16 // duplicate
+#define mmHDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 0
+#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x0e17 // duplicate
+#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 0
+#define mmGPU_HDP_FLUSH_REQ 0x0e26 // duplicate
+#define mmGPU_HDP_FLUSH_REQ_BASE_IDX 0
+#define mmGPU_HDP_FLUSH_DONE 0x0e27 // duplicate
+#define mmGPU_HDP_FLUSH_DONE_BASE_IDX 0
+#define mmBIF_TRANS_PENDING 0x0e28 // duplicate
+#define mmBIF_TRANS_PENDING_BASE_IDX 0
+#define mmMAILBOX_MSGBUF_TRN_DW0 0x0e56 // duplicate
+#define mmMAILBOX_MSGBUF_TRN_DW0_BASE_IDX 0
+#define mmMAILBOX_MSGBUF_TRN_DW1 0x0e57 // duplicate
+#define mmMAILBOX_MSGBUF_TRN_DW1_BASE_IDX 0
+#define mmMAILBOX_MSGBUF_TRN_DW2 0x0e58 // duplicate
+#define mmMAILBOX_MSGBUF_TRN_DW2_BASE_IDX 0
+#define mmMAILBOX_MSGBUF_TRN_DW3 0x0e59 // duplicate
+#define mmMAILBOX_MSGBUF_TRN_DW3_BASE_IDX 0
+#define mmMAILBOX_MSGBUF_RCV_DW0 0x0e5a // duplicate
+#define mmMAILBOX_MSGBUF_RCV_DW0_BASE_IDX 0
+#define mmMAILBOX_MSGBUF_RCV_DW1 0x0e5b // duplicate
+#define mmMAILBOX_MSGBUF_RCV_DW1_BASE_IDX 0
+#define mmMAILBOX_MSGBUF_RCV_DW2 0x0e5c // duplicate
+#define mmMAILBOX_MSGBUF_RCV_DW2_BASE_IDX 0
+#define mmMAILBOX_MSGBUF_RCV_DW3 0x0e5d // duplicate
+#define mmMAILBOX_MSGBUF_RCV_DW3_BASE_IDX 0
+#define mmMAILBOX_CONTROL 0x0e5e // duplicate
+#define mmMAILBOX_CONTROL_BASE_IDX 0
+#define mmMAILBOX_INT_CNTL 0x0e5f // duplicate
+#define mmMAILBOX_INT_CNTL_BASE_IDX 0
+#define mmBIF_VMHV_MAILBOX 0x0e60 // duplicate
+#define mmBIF_VMHV_MAILBOX_BASE_IDX 0
+
+
+// addressBlock: rcc_pf_0_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DOORBELL_APER_EN 0x0de0 // duplicate
+#define mmRCC_DOORBELL_APER_EN_BASE_IDX 0
+#define mmRCC_CONFIG_MEMSIZE 0x0de3 // duplicate
+#define mmRCC_CONFIG_MEMSIZE_BASE_IDX 0
+#define mmRCC_CONFIG_RESERVED 0x0de4 // duplicate
+#define mmRCC_CONFIG_RESERVED_BASE_IDX 0
+#define mmRCC_IOV_FUNC_IDENTIFIER 0x0de5 // duplicate
+#define mmRCC_IOV_FUNC_IDENTIFIER_BASE_IDX 0
+
+
+// addressBlock: syshub_mmreg_ind_syshubdec
+// base address: 0x0
+#define mmSYSHUB_INDEX 0x0008
+#define mmSYSHUB_INDEX_BASE_IDX 0
+#define mmSYSHUB_DATA 0x0009
+#define mmSYSHUB_DATA_BASE_IDX 0
+
+
+// addressBlock: rcc_strap_rcc_strap_internal
+// base address: 0x10100000
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0 0x403c000 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1 0x403c001 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2 0x403c002 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3 0x403c003 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4 0x403c004 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5 0x403c005 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6 0x403c006 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7 0x403c007 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7_BASE_IDX 3
+#define mmRCC_DEV1_PORT_STRAP0 0x403c080
+#define mmRCC_DEV1_PORT_STRAP0_BASE_IDX 3
+#define mmRCC_DEV1_PORT_STRAP1 0x403c081
+#define mmRCC_DEV1_PORT_STRAP1_BASE_IDX 3
+#define mmRCC_DEV1_PORT_STRAP2 0x403c082
+#define mmRCC_DEV1_PORT_STRAP2_BASE_IDX 3
+#define mmRCC_DEV1_PORT_STRAP3 0x403c083
+#define mmRCC_DEV1_PORT_STRAP3_BASE_IDX 3
+#define mmRCC_DEV1_PORT_STRAP4 0x403c084
+#define mmRCC_DEV1_PORT_STRAP4_BASE_IDX 3
+#define mmRCC_DEV1_PORT_STRAP5 0x403c085
+#define mmRCC_DEV1_PORT_STRAP5_BASE_IDX 3
+#define mmRCC_DEV1_PORT_STRAP6 0x403c086
+#define mmRCC_DEV1_PORT_STRAP6_BASE_IDX 3
+#define mmRCC_DEV1_PORT_STRAP7 0x403c087
+#define mmRCC_DEV1_PORT_STRAP7_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0 0x403cc00 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1 0x403cc01 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2 0x403cc02 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3 0x403cc03 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4 0x403cc04 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5 0x403cc05 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8 0x403cc08 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9 0x403cc09 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13 0x403cc0d // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0 0x403cc80 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2 0x403cc82 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3 0x403cc83 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4 0x403cc84 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5 0x403cc85 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6 0x403cc86 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7 0x403cc87 // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10 0x403cc8a // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11 0x403cc8b // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12 0x403cc8c // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12_BASE_IDX 3
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13 0x403cc8d // duplicate
+#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13_BASE_IDX 3
+#define mmRCC_DEV0_EPF2_STRAP0 0x403cd00
+#define mmRCC_DEV0_EPF2_STRAP0_BASE_IDX 3
+#define mmRCC_DEV0_EPF2_STRAP2 0x403cd02
+#define mmRCC_DEV0_EPF2_STRAP2_BASE_IDX 3
+#define mmRCC_DEV0_EPF2_STRAP3 0x403cd03
+#define mmRCC_DEV0_EPF2_STRAP3_BASE_IDX 3
+#define mmRCC_DEV0_EPF2_STRAP4 0x403cd04
+#define mmRCC_DEV0_EPF2_STRAP4_BASE_IDX 3
+#define mmRCC_DEV0_EPF2_STRAP5 0x403cd05
+#define mmRCC_DEV0_EPF2_STRAP5_BASE_IDX 3
+#define mmRCC_DEV0_EPF2_STRAP6 0x403cd06
+#define mmRCC_DEV0_EPF2_STRAP6_BASE_IDX 3
+#define mmRCC_DEV0_EPF2_STRAP13 0x403cd0d
+#define mmRCC_DEV0_EPF2_STRAP13_BASE_IDX 3
+#define mmRCC_DEV0_EPF3_STRAP0 0x403cd80
+#define mmRCC_DEV0_EPF3_STRAP0_BASE_IDX 3
+#define mmRCC_DEV0_EPF3_STRAP2 0x403cd82
+#define mmRCC_DEV0_EPF3_STRAP2_BASE_IDX 3
+#define mmRCC_DEV0_EPF3_STRAP3 0x403cd83
+#define mmRCC_DEV0_EPF3_STRAP3_BASE_IDX 3
+#define mmRCC_DEV0_EPF3_STRAP4 0x403cd84
+#define mmRCC_DEV0_EPF3_STRAP4_BASE_IDX 3
+#define mmRCC_DEV0_EPF3_STRAP5 0x403cd85
+#define mmRCC_DEV0_EPF3_STRAP5_BASE_IDX 3
+#define mmRCC_DEV0_EPF3_STRAP6 0x403cd86
+#define mmRCC_DEV0_EPF3_STRAP6_BASE_IDX 3
+#define mmRCC_DEV0_EPF3_STRAP13 0x403cd8d
+#define mmRCC_DEV0_EPF3_STRAP13_BASE_IDX 3
+#define mmRCC_DEV0_EPF4_STRAP0 0x403ce00
+#define mmRCC_DEV0_EPF4_STRAP0_BASE_IDX 3
+#define mmRCC_DEV0_EPF4_STRAP2 0x403ce02
+#define mmRCC_DEV0_EPF4_STRAP2_BASE_IDX 3
+#define mmRCC_DEV0_EPF4_STRAP3 0x403ce03
+#define mmRCC_DEV0_EPF4_STRAP3_BASE_IDX 3
+#define mmRCC_DEV0_EPF4_STRAP4 0x403ce04
+#define mmRCC_DEV0_EPF4_STRAP4_BASE_IDX 3
+#define mmRCC_DEV0_EPF4_STRAP5 0x403ce05
+#define mmRCC_DEV0_EPF4_STRAP5_BASE_IDX 3
+#define mmRCC_DEV0_EPF4_STRAP6 0x403ce06
+#define mmRCC_DEV0_EPF4_STRAP6_BASE_IDX 3
+#define mmRCC_DEV0_EPF4_STRAP13 0x403ce0d
+#define mmRCC_DEV0_EPF4_STRAP13_BASE_IDX 3
+#define mmRCC_DEV0_EPF5_STRAP0 0x403ce80
+#define mmRCC_DEV0_EPF5_STRAP0_BASE_IDX 3
+#define mmRCC_DEV0_EPF5_STRAP2 0x403ce82
+#define mmRCC_DEV0_EPF5_STRAP2_BASE_IDX 3
+#define mmRCC_DEV0_EPF5_STRAP3 0x403ce83
+#define mmRCC_DEV0_EPF5_STRAP3_BASE_IDX 3
+#define mmRCC_DEV0_EPF5_STRAP4 0x403ce84
+#define mmRCC_DEV0_EPF5_STRAP4_BASE_IDX 3
+#define mmRCC_DEV0_EPF5_STRAP5 0x403ce85
+#define mmRCC_DEV0_EPF5_STRAP5_BASE_IDX 3
+#define mmRCC_DEV0_EPF5_STRAP6 0x403ce86
+#define mmRCC_DEV0_EPF5_STRAP6_BASE_IDX 3
+#define mmRCC_DEV0_EPF5_STRAP13 0x403ce8d
+#define mmRCC_DEV0_EPF5_STRAP13_BASE_IDX 3
+#define mmRCC_DEV0_EPF6_STRAP0 0x403cf00
+#define mmRCC_DEV0_EPF6_STRAP0_BASE_IDX 3
+#define mmRCC_DEV0_EPF6_STRAP2 0x403cf02
+#define mmRCC_DEV0_EPF6_STRAP2_BASE_IDX 3
+#define mmRCC_DEV0_EPF6_STRAP3 0x403cf03
+#define mmRCC_DEV0_EPF6_STRAP3_BASE_IDX 3
+#define mmRCC_DEV0_EPF6_STRAP4 0x403cf04
+#define mmRCC_DEV0_EPF6_STRAP4_BASE_IDX 3
+#define mmRCC_DEV0_EPF6_STRAP5 0x403cf05
+#define mmRCC_DEV0_EPF6_STRAP5_BASE_IDX 3
+#define mmRCC_DEV0_EPF6_STRAP6 0x403cf06
+#define mmRCC_DEV0_EPF6_STRAP6_BASE_IDX 3
+#define mmRCC_DEV0_EPF6_STRAP13 0x403cf0d
+#define mmRCC_DEV0_EPF6_STRAP13_BASE_IDX 3
+#define mmRCC_DEV0_EPF7_STRAP0 0x403cf80
+#define mmRCC_DEV0_EPF7_STRAP0_BASE_IDX 3
+#define mmRCC_DEV0_EPF7_STRAP2 0x403cf82
+#define mmRCC_DEV0_EPF7_STRAP2_BASE_IDX 3
+#define mmRCC_DEV0_EPF7_STRAP3 0x403cf83
+#define mmRCC_DEV0_EPF7_STRAP3_BASE_IDX 3
+#define mmRCC_DEV0_EPF7_STRAP4 0x403cf84
+#define mmRCC_DEV0_EPF7_STRAP4_BASE_IDX 3
+#define mmRCC_DEV0_EPF7_STRAP5 0x403cf85
+#define mmRCC_DEV0_EPF7_STRAP5_BASE_IDX 3
+#define mmRCC_DEV0_EPF7_STRAP6 0x403cf86
+#define mmRCC_DEV0_EPF7_STRAP6_BASE_IDX 3
+#define mmRCC_DEV0_EPF7_STRAP13 0x403cf8d
+#define mmRCC_DEV0_EPF7_STRAP13_BASE_IDX 3
+#define mmRCC_DEV1_EPF0_STRAP0 0x403d000
+#define mmRCC_DEV1_EPF0_STRAP0_BASE_IDX 3
+#define mmRCC_DEV1_EPF0_STRAP2 0x403d002
+#define mmRCC_DEV1_EPF0_STRAP2_BASE_IDX 3
+#define mmRCC_DEV1_EPF0_STRAP3 0x403d003
+#define mmRCC_DEV1_EPF0_STRAP3_BASE_IDX 3
+#define mmRCC_DEV1_EPF0_STRAP4 0x403d004
+#define mmRCC_DEV1_EPF0_STRAP4_BASE_IDX 3
+#define mmRCC_DEV1_EPF0_STRAP5 0x403d005
+#define mmRCC_DEV1_EPF0_STRAP5_BASE_IDX 3
+#define mmRCC_DEV1_EPF0_STRAP6 0x403d006
+#define mmRCC_DEV1_EPF0_STRAP6_BASE_IDX 3
+#define mmRCC_DEV1_EPF0_STRAP13 0x403d00d
+#define mmRCC_DEV1_EPF0_STRAP13_BASE_IDX 3
+#define mmRCC_DEV1_EPF1_STRAP0 0x403d080
+#define mmRCC_DEV1_EPF1_STRAP0_BASE_IDX 3
+#define mmRCC_DEV1_EPF1_STRAP2 0x403d082
+#define mmRCC_DEV1_EPF1_STRAP2_BASE_IDX 3
+#define mmRCC_DEV1_EPF1_STRAP3 0x403d083
+#define mmRCC_DEV1_EPF1_STRAP3_BASE_IDX 3
+#define mmRCC_DEV1_EPF1_STRAP4 0x403d084
+#define mmRCC_DEV1_EPF1_STRAP4_BASE_IDX 3
+#define mmRCC_DEV1_EPF1_STRAP5 0x403d085
+#define mmRCC_DEV1_EPF1_STRAP5_BASE_IDX 3
+#define mmRCC_DEV1_EPF1_STRAP6 0x403d086
+#define mmRCC_DEV1_EPF1_STRAP6_BASE_IDX 3
+#define mmRCC_DEV1_EPF1_STRAP13 0x403d08d
+#define mmRCC_DEV1_EPF1_STRAP13_BASE_IDX 3
+#define mmRCC_DEV1_EPF2_STRAP0 0x403d100
+#define mmRCC_DEV1_EPF2_STRAP0_BASE_IDX 3
+#define mmRCC_DEV1_EPF2_STRAP2 0x403d102
+#define mmRCC_DEV1_EPF2_STRAP2_BASE_IDX 3
+#define mmRCC_DEV1_EPF2_STRAP3 0x403d103
+#define mmRCC_DEV1_EPF2_STRAP3_BASE_IDX 3
+#define mmRCC_DEV1_EPF2_STRAP4 0x403d104
+#define mmRCC_DEV1_EPF2_STRAP4_BASE_IDX 3
+#define mmRCC_DEV1_EPF2_STRAP5 0x403d105
+#define mmRCC_DEV1_EPF2_STRAP5_BASE_IDX 3
+#define mmRCC_DEV1_EPF2_STRAP6 0x403d106
+#define mmRCC_DEV1_EPF2_STRAP6_BASE_IDX 3
+#define mmRCC_DEV1_EPF2_STRAP13 0x403d10d
+#define mmRCC_DEV1_EPF2_STRAP13_BASE_IDX 3
+
+
+// addressBlock: bif_rst_bif_rst_regblk
+// base address: 0x10100000
+#define ixHARD_RST_CTRL 0x38000
+#define ixRSMU_SOFT_RST_CTRL 0x38004
+#define ixSELF_SOFT_RST 0x38008
+#define ixGFX_DRV_MODE1_RST_CTRL 0x3800c
+#define ixBIF_RST_MISC_CTRL 0x38010
+#define ixBIF_RST_MISC_CTRL2 0x38014
+#define ixBIF_RST_MISC_CTRL3 0x38018
+#define ixBIF_RST_GFXVF_FLR_IDLE 0x3801c
+#define ixDEV0_PF0_FLR_RST_CTRL 0x38020
+#define ixDEV0_PF1_FLR_RST_CTRL 0x38024
+#define ixDEV0_PF2_FLR_RST_CTRL 0x38028
+#define ixDEV0_PF3_FLR_RST_CTRL 0x3802c
+#define ixDEV0_PF4_FLR_RST_CTRL 0x38030
+#define ixDEV0_PF5_FLR_RST_CTRL 0x38034
+#define ixDEV0_PF6_FLR_RST_CTRL 0x38038
+#define ixDEV0_PF7_FLR_RST_CTRL 0x3803c
+#define ixBIF_INST_RESET_INTR_STS 0x38040
+#define ixBIF_PF_FLR_INTR_STS 0x38044
+#define ixBIF_D3HOTD0_INTR_STS 0x38048
+#define ixBIF_POWER_INTR_STS 0x38050
+#define ixBIF_PF_DSTATE_INTR_STS 0x38054
+#define ixBIF_PF0_VF_FLR_INTR_STS 0x38060
+#define ixBIF_INST_RESET_INTR_MASK 0x38080
+#define ixBIF_PF_FLR_INTR_MASK 0x38084
+#define ixBIF_D3HOTD0_INTR_MASK 0x38088
+#define ixBIF_POWER_INTR_MASK 0x38090
+#define ixBIF_PF_DSTATE_INTR_MASK 0x38094
+#define ixBIF_PF0_VF_FLR_INTR_MASK 0x380a0
+#define ixBIF_PF_FLR_RST 0x38100
+#define ixBIF_PF0_VF_FLR_RST 0x38120
+#define ixBIF_DEV0_PF0_DSTATE_VALUE 0x38140
+#define ixBIF_DEV0_PF1_DSTATE_VALUE 0x38144
+#define ixBIF_DEV0_PF2_DSTATE_VALUE 0x38148
+#define ixBIF_DEV0_PF3_DSTATE_VALUE 0x3814c
+#define ixBIF_DEV0_PF4_DSTATE_VALUE 0x38150
+#define ixBIF_DEV0_PF5_DSTATE_VALUE 0x38154
+#define ixBIF_DEV0_PF6_DSTATE_VALUE 0x38158
+#define ixBIF_DEV0_PF7_DSTATE_VALUE 0x3815c
+#define ixDEV0_PF0_D3HOTD0_RST_CTRL 0x381e0
+#define ixDEV0_PF1_D3HOTD0_RST_CTRL 0x381e4
+#define ixDEV0_PF2_D3HOTD0_RST_CTRL 0x381e8
+#define ixDEV0_PF3_D3HOTD0_RST_CTRL 0x381ec
+#define ixDEV0_PF4_D3HOTD0_RST_CTRL 0x381f0
+#define ixDEV0_PF5_D3HOTD0_RST_CTRL 0x381f4
+#define ixDEV0_PF6_D3HOTD0_RST_CTRL 0x381f8
+#define ixDEV0_PF7_D3HOTD0_RST_CTRL 0x381fc
+#define ixBIF_PORT0_DSTATE_VALUE 0x388c0
+
+
+// addressBlock: bif_misc_bif_misc_regblk
+// base address: 0x10100000
+#define ixMISC_SCRATCH 0x3a000
+#define ixINTR_LINE_POLARITY 0x3a004
+#define ixINTR_LINE_ENABLE 0x3a008
+#define ixOUTSTANDING_VC_ALLOC 0x3a00c
+#define ixBIFC_MISC_CTRL0 0x3a010
+#define ixBIFC_MISC_CTRL1 0x3a014
+#define ixBIFC_BME_ERR_LOG 0x3a018
+#define ixBIFC_RCCBIH_BME_ERR_LOG 0x3a01c
+#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 0x3a020
+#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 0x3a024
+#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 0x3a028
+#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 0x3a02c
+#define ixNBIF_VWIRE_CTRL 0x3a040
+#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL 0x3a044
+#define ixNBIF_SMN_VWR_VCHG_RST_CTRL0 0x3a048
+#define ixNBIF_SMN_VWR_VCHG_TRIG 0x3a050
+#define ixNBIF_SMN_VWR_WTRIG_CNTL 0x3a054
+#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL_1 0x3a058
+#define ixNBIF_MGCG_CTRL 0x3a05c
+#define ixNBIF_DS_CTRL_LCLK 0x3a060
+#define ixSMN_MST_CNTL0 0x3a064
+#define ixSMN_MST_EP_CNTL1 0x3a068
+#define ixSMN_MST_EP_CNTL2 0x3a06c
+#define ixNBIF_SDP_VWR_VCHG_DIS_CTRL 0x3a070
+#define ixNBIF_SDP_VWR_VCHG_RST_CTRL0 0x3a074
+#define ixNBIF_SDP_VWR_VCHG_RST_CTRL1 0x3a078
+#define ixNBIF_SDP_VWR_VCHG_TRIG 0x3a07c
+#define ixBME_DUMMY_CNTL_0 0x3a098
+#define ixBIFC_THT_CNTL 0x3a09c
+#define ixBIFC_HSTARB_CNTL 0x3a0a0
+#define ixBIFC_GSI_CNTL 0x3a0a4
+#define ixBIFC_PCIEFUNC_CNTL 0x3a0a8
+#define ixBIFC_SDP_CNTL_0 0x3a0b0
+#define ixBIFC_PERF_CNTL_0 0x3a0c0
+#define ixBIFC_PERF_CNTL_1 0x3a0c4
+#define ixBIFC_PERF_CNT_MMIO_RD 0x3a0c8
+#define ixBIFC_PERF_CNT_MMIO_WR 0x3a0cc
+#define ixBIFC_PERF_CNT_DMA_RD 0x3a0d0
+#define ixBIFC_PERF_CNT_DMA_WR 0x3a0d4
+#define ixNBIF_REGIF_ERRSET_CTRL 0x3a0d8
+#define ixSMN_MST_EP_CNTL3 0x3a0f0
+#define ixSMN_MST_EP_CNTL4 0x3a0f4
+#define ixBIF_SELFRING_BUFFER_VID 0x3a100
+#define ixBIF_SELFRING_VECTOR_CNTL 0x3a104
+
+
+// addressBlock: bif_ras_bif_ras_regblk
+// base address: 0x10100000
+#define ixBIF_RAS_LEAF0_CTRL 0x39000
+#define ixBIF_RAS_LEAF1_CTRL 0x39004
+#define ixBIF_RAS_LEAF2_CTRL 0x39008
+#define ixBIF_RAS_MISC_CTRL 0x39100
+#define ixBIF_IOHUB_RAS_IH_CNTL 0x39ff8
+#define ixBIF_RAS_VWR_FROM_IOHUB 0x39ffc
+
+
+// addressBlock: rcc_pfc_amdgfx_RCCPFCDEC
+// base address: 0x10134000
+#define ixRCC_PFC_LTR_CNTL 0x0100 // duplicate
+#define ixRCC_PFC_PME_RESTORE 0x0104 // duplicate
+#define ixRCC_PFC_STICKY_RESTORE_0 0x0108 // duplicate
+#define ixRCC_PFC_STICKY_RESTORE_1 0x010c // duplicate
+#define ixRCC_PFC_STICKY_RESTORE_2 0x0110 // duplicate
+#define ixRCC_PFC_STICKY_RESTORE_3 0x0114 // duplicate
+#define ixRCC_PFC_STICKY_RESTORE_4 0x0118 // duplicate
+#define ixRCC_PFC_STICKY_RESTORE_5 0x011c // duplicate
+#define ixRCC_PFC_AUXPWR_CNTL 0x0120 // duplicate
+
+
+// addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC
+// base address: 0x10134200
+#define ixRCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL 0x0100 // duplicate
+#define ixRCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE 0x0104 // duplicate
+#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0 0x0108 // duplicate
+#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1 0x010c // duplicate
+#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2 0x0110 // duplicate
+#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3 0x0114 // duplicate
+#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4 0x0118 // duplicate
+#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5 0x011c // duplicate
+#define ixRCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL 0x0120 // duplicate
+
+
+// addressBlock: pciemsix_amdgfx_MSIXTDEC
+// base address: 0x10170000
+#define ixPCIEMSIX_VECT0_ADDR_LO 0x0000
+#define ixPCIEMSIX_VECT0_ADDR_HI 0x0004
+#define ixPCIEMSIX_VECT0_MSG_DATA 0x0008
+#define ixPCIEMSIX_VECT0_CONTROL 0x000c
+#define ixPCIEMSIX_VECT1_ADDR_LO 0x0010
+#define ixPCIEMSIX_VECT1_ADDR_HI 0x0014
+#define ixPCIEMSIX_VECT1_MSG_DATA 0x0018
+#define ixPCIEMSIX_VECT1_CONTROL 0x001c
+#define ixPCIEMSIX_VECT2_ADDR_LO 0x0020
+#define ixPCIEMSIX_VECT2_ADDR_HI 0x0024
+#define ixPCIEMSIX_VECT2_MSG_DATA 0x0028
+#define ixPCIEMSIX_VECT2_CONTROL 0x002c
+#define ixPCIEMSIX_VECT3_ADDR_LO 0x0030
+#define ixPCIEMSIX_VECT3_ADDR_HI 0x0034
+#define ixPCIEMSIX_VECT3_MSG_DATA 0x0038
+#define ixPCIEMSIX_VECT3_CONTROL 0x003c
+#define ixPCIEMSIX_VECT4_ADDR_LO 0x0040
+#define ixPCIEMSIX_VECT4_ADDR_HI 0x0044
+#define ixPCIEMSIX_VECT4_MSG_DATA 0x0048
+#define ixPCIEMSIX_VECT4_CONTROL 0x004c
+#define ixPCIEMSIX_VECT5_ADDR_LO 0x0050
+#define ixPCIEMSIX_VECT5_ADDR_HI 0x0054
+#define ixPCIEMSIX_VECT5_MSG_DATA 0x0058
+#define ixPCIEMSIX_VECT5_CONTROL 0x005c
+#define ixPCIEMSIX_VECT6_ADDR_LO 0x0060
+#define ixPCIEMSIX_VECT6_ADDR_HI 0x0064
+#define ixPCIEMSIX_VECT6_MSG_DATA 0x0068
+#define ixPCIEMSIX_VECT6_CONTROL 0x006c
+#define ixPCIEMSIX_VECT7_ADDR_LO 0x0070
+#define ixPCIEMSIX_VECT7_ADDR_HI 0x0074
+#define ixPCIEMSIX_VECT7_MSG_DATA 0x0078
+#define ixPCIEMSIX_VECT7_CONTROL 0x007c
+#define ixPCIEMSIX_VECT8_ADDR_LO 0x0080
+#define ixPCIEMSIX_VECT8_ADDR_HI 0x0084
+#define ixPCIEMSIX_VECT8_MSG_DATA 0x0088
+#define ixPCIEMSIX_VECT8_CONTROL 0x008c
+#define ixPCIEMSIX_VECT9_ADDR_LO 0x0090
+#define ixPCIEMSIX_VECT9_ADDR_HI 0x0094
+#define ixPCIEMSIX_VECT9_MSG_DATA 0x0098
+#define ixPCIEMSIX_VECT9_CONTROL 0x009c
+#define ixPCIEMSIX_VECT10_ADDR_LO 0x00a0
+#define ixPCIEMSIX_VECT10_ADDR_HI 0x00a4
+#define ixPCIEMSIX_VECT10_MSG_DATA 0x00a8
+#define ixPCIEMSIX_VECT10_CONTROL 0x00ac
+#define ixPCIEMSIX_VECT11_ADDR_LO 0x00b0
+#define ixPCIEMSIX_VECT11_ADDR_HI 0x00b4
+#define ixPCIEMSIX_VECT11_MSG_DATA 0x00b8
+#define ixPCIEMSIX_VECT11_CONTROL 0x00bc
+#define ixPCIEMSIX_VECT12_ADDR_LO 0x00c0
+#define ixPCIEMSIX_VECT12_ADDR_HI 0x00c4
+#define ixPCIEMSIX_VECT12_MSG_DATA 0x00c8
+#define ixPCIEMSIX_VECT12_CONTROL 0x00cc
+#define ixPCIEMSIX_VECT13_ADDR_LO 0x00d0
+#define ixPCIEMSIX_VECT13_ADDR_HI 0x00d4
+#define ixPCIEMSIX_VECT13_MSG_DATA 0x00d8
+#define ixPCIEMSIX_VECT13_CONTROL 0x00dc
+#define ixPCIEMSIX_VECT14_ADDR_LO 0x00e0
+#define ixPCIEMSIX_VECT14_ADDR_HI 0x00e4
+#define ixPCIEMSIX_VECT14_MSG_DATA 0x00e8
+#define ixPCIEMSIX_VECT14_CONTROL 0x00ec
+#define ixPCIEMSIX_VECT15_ADDR_LO 0x00f0
+#define ixPCIEMSIX_VECT15_ADDR_HI 0x00f4
+#define ixPCIEMSIX_VECT15_MSG_DATA 0x00f8
+#define ixPCIEMSIX_VECT15_CONTROL 0x00fc
+#define ixPCIEMSIX_VECT16_ADDR_LO 0x0100
+#define ixPCIEMSIX_VECT16_ADDR_HI 0x0104
+#define ixPCIEMSIX_VECT16_MSG_DATA 0x0108
+#define ixPCIEMSIX_VECT16_CONTROL 0x010c
+#define ixPCIEMSIX_VECT17_ADDR_LO 0x0110
+#define ixPCIEMSIX_VECT17_ADDR_HI 0x0114
+#define ixPCIEMSIX_VECT17_MSG_DATA 0x0118
+#define ixPCIEMSIX_VECT17_CONTROL 0x011c
+#define ixPCIEMSIX_VECT18_ADDR_LO 0x0120
+#define ixPCIEMSIX_VECT18_ADDR_HI 0x0124
+#define ixPCIEMSIX_VECT18_MSG_DATA 0x0128
+#define ixPCIEMSIX_VECT18_CONTROL 0x012c
+#define ixPCIEMSIX_VECT19_ADDR_LO 0x0130
+#define ixPCIEMSIX_VECT19_ADDR_HI 0x0134
+#define ixPCIEMSIX_VECT19_MSG_DATA 0x0138
+#define ixPCIEMSIX_VECT19_CONTROL 0x013c
+#define ixPCIEMSIX_VECT20_ADDR_LO 0x0140
+#define ixPCIEMSIX_VECT20_ADDR_HI 0x0144
+#define ixPCIEMSIX_VECT20_MSG_DATA 0x0148
+#define ixPCIEMSIX_VECT20_CONTROL 0x014c
+#define ixPCIEMSIX_VECT21_ADDR_LO 0x0150
+#define ixPCIEMSIX_VECT21_ADDR_HI 0x0154
+#define ixPCIEMSIX_VECT21_MSG_DATA 0x0158
+#define ixPCIEMSIX_VECT21_CONTROL 0x015c
+#define ixPCIEMSIX_VECT22_ADDR_LO 0x0160
+#define ixPCIEMSIX_VECT22_ADDR_HI 0x0164
+#define ixPCIEMSIX_VECT22_MSG_DATA 0x0168
+#define ixPCIEMSIX_VECT22_CONTROL 0x016c
+#define ixPCIEMSIX_VECT23_ADDR_LO 0x0170
+#define ixPCIEMSIX_VECT23_ADDR_HI 0x0174
+#define ixPCIEMSIX_VECT23_MSG_DATA 0x0178
+#define ixPCIEMSIX_VECT23_CONTROL 0x017c
+#define ixPCIEMSIX_VECT24_ADDR_LO 0x0180
+#define ixPCIEMSIX_VECT24_ADDR_HI 0x0184
+#define ixPCIEMSIX_VECT24_MSG_DATA 0x0188
+#define ixPCIEMSIX_VECT24_CONTROL 0x018c
+#define ixPCIEMSIX_VECT25_ADDR_LO 0x0190
+#define ixPCIEMSIX_VECT25_ADDR_HI 0x0194
+#define ixPCIEMSIX_VECT25_MSG_DATA 0x0198
+#define ixPCIEMSIX_VECT25_CONTROL 0x019c
+#define ixPCIEMSIX_VECT26_ADDR_LO 0x01a0
+#define ixPCIEMSIX_VECT26_ADDR_HI 0x01a4
+#define ixPCIEMSIX_VECT26_MSG_DATA 0x01a8
+#define ixPCIEMSIX_VECT26_CONTROL 0x01ac
+#define ixPCIEMSIX_VECT27_ADDR_LO 0x01b0
+#define ixPCIEMSIX_VECT27_ADDR_HI 0x01b4
+#define ixPCIEMSIX_VECT27_MSG_DATA 0x01b8
+#define ixPCIEMSIX_VECT27_CONTROL 0x01bc
+#define ixPCIEMSIX_VECT28_ADDR_LO 0x01c0
+#define ixPCIEMSIX_VECT28_ADDR_HI 0x01c4
+#define ixPCIEMSIX_VECT28_MSG_DATA 0x01c8
+#define ixPCIEMSIX_VECT28_CONTROL 0x01cc
+#define ixPCIEMSIX_VECT29_ADDR_LO 0x01d0
+#define ixPCIEMSIX_VECT29_ADDR_HI 0x01d4
+#define ixPCIEMSIX_VECT29_MSG_DATA 0x01d8
+#define ixPCIEMSIX_VECT29_CONTROL 0x01dc
+#define ixPCIEMSIX_VECT30_ADDR_LO 0x01e0
+#define ixPCIEMSIX_VECT30_ADDR_HI 0x01e4
+#define ixPCIEMSIX_VECT30_MSG_DATA 0x01e8
+#define ixPCIEMSIX_VECT30_CONTROL 0x01ec
+#define ixPCIEMSIX_VECT31_ADDR_LO 0x01f0
+#define ixPCIEMSIX_VECT31_ADDR_HI 0x01f4
+#define ixPCIEMSIX_VECT31_MSG_DATA 0x01f8
+#define ixPCIEMSIX_VECT31_CONTROL 0x01fc
+
+
+// addressBlock: pciemsix_amdgfx_MSIXPDEC
+// base address: 0x10171000
+#define ixPCIEMSIX_PBA 0x0000
+
+
+// addressBlock: syshub_mmreg_ind_syshubind
+// base address: 0x0
+#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK 0x10000 // duplicate
+#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK 0x10004 // duplicate
+#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x10008 // duplicate
+#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x1000c // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x10010 // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x10014 // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL 0x10018 // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL 0x1001c // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL 0x10020 // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL 0x10024 // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL 0x10028 // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL 0x1002c // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL 0x10030 // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL 0x10034 // duplicate
+#define ixSYSHUBMMREGIND_SYSHUB_CG_CNTL 0x10300 // duplicate
+#define ixSYSHUBMMREGIND_SYSHUB_TRANS_IDLE 0x10308 // duplicate
+#define ixSYSHUBMMREGIND_SYSHUB_HP_TIMER 0x1030c // duplicate
+#define ixSYSHUBMMREGIND_SYSHUB_SCRATCH 0x10f00 // duplicate
+#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK 0x11000 // duplicate
+#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK 0x11004 // duplicate
+#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 0x11008 // duplicate
+#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 0x1100c // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL 0x11010 // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL 0x11014 // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL 0x11018 // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL 0x1101c // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL 0x11020 // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL 0x11024 // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL 0x11028 // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL 0x1102c // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL 0x11030 // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL 0x11034 // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL 0x11038 // duplicate
+#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL 0x1103c // duplicate
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h
new file mode 100644
index 000000000000..c7518b84f559
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h
@@ -0,0 +1,10281 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _nbif_6_1_SH_MASK_HEADER
+#define _nbif_6_1_SH_MASK_HEADER
+
+
+// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp
+//VENDOR_ID
+#define VENDOR_ID__VENDOR_ID__SHIFT 0x0
+//DEVICE_ID
+#define DEVICE_ID__DEVICE_ID__SHIFT 0x0
+//COMMAND
+#define COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define COMMAND__AD_STEPPING__SHIFT 0x7
+#define COMMAND__SERR_EN__SHIFT 0x8
+#define COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define COMMAND__INT_DIS__SHIFT 0xa
+//STATUS
+#define STATUS__INT_STATUS__SHIFT 0x3
+#define STATUS__CAP_LIST__SHIFT 0x4
+#define STATUS__PCI_66_EN__SHIFT 0x5
+#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+//REVISION_ID
+#define REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+//PROG_INTERFACE
+#define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+//SUB_CLASS
+#define SUB_CLASS__SUB_CLASS__SHIFT 0x0
+//BASE_CLASS
+#define BASE_CLASS__BASE_CLASS__SHIFT 0x0
+//CACHE_LINE
+#define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+//LATENCY
+#define LATENCY__LATENCY_TIMER__SHIFT 0x0
+//HEADER
+#define HEADER__HEADER_TYPE__SHIFT 0x0
+#define HEADER__DEVICE_TYPE__SHIFT 0x7
+//BIST
+#define BIST__BIST_COMP__SHIFT 0x0
+#define BIST__BIST_STRT__SHIFT 0x6
+#define BIST__BIST_CAP__SHIFT 0x7
+//BASE_ADDR_1
+#define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+//BASE_ADDR_2
+#define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+//BASE_ADDR_3
+#define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+//BASE_ADDR_4
+#define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+//BASE_ADDR_5
+#define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+//BASE_ADDR_6
+#define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+//ADAPTER_ID
+#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+//ROM_BASE_ADDR
+#define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+//CAP_PTR
+#define CAP_PTR__CAP_PTR__SHIFT 0x0
+//INTERRUPT_LINE
+#define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+//INTERRUPT_PIN
+#define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+//MIN_GRANT
+#define MIN_GRANT__MIN_GNT__SHIFT 0x0
+//MAX_LATENCY
+#define MAX_LATENCY__MAX_LAT__SHIFT 0x0
+//VENDOR_CAP_LIST
+#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+//ADAPTER_ID_W
+#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+//PMI_CAP_LIST
+#define PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+//PMI_CAP
+#define PMI_CAP__VERSION__SHIFT 0x0
+#define PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define PMI_CAP__PME_SUPPORT__SHIFT 0xb
+//PMI_STATUS_CNTL
+#define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+//PCIE_CAP_LIST
+#define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+//PCIE_CAP
+#define PCIE_CAP__VERSION__SHIFT 0x0
+#define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+//DEVICE_CAP
+#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+//DEVICE_CNTL
+#define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+//DEVICE_STATUS
+#define DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+//LINK_CAP
+#define LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define LINK_CAP__PORT_NUMBER__SHIFT 0x18
+//LINK_CNTL
+#define LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+//LINK_STATUS
+#define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+//DEVICE_CAP2
+#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+//DEVICE_CNTL2
+#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+//DEVICE_STATUS2
+#define DEVICE_STATUS2__RESERVED__SHIFT 0x0
+//LINK_CAP2
+#define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define LINK_CAP2__RESERVED__SHIFT 0x9
+//LINK_CNTL2
+#define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+//LINK_STATUS2
+#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+//SLOT_CAP2
+#define SLOT_CAP2__RESERVED__SHIFT 0x0
+//SLOT_CNTL2
+#define SLOT_CNTL2__RESERVED__SHIFT 0x0
+//SLOT_STATUS2
+#define SLOT_STATUS2__RESERVED__SHIFT 0x0
+//MSI_CAP_LIST
+#define MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+//MSI_MSG_CNTL
+#define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+//MSI_MSG_ADDR_LO
+#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+//MSI_MSG_ADDR_HI
+#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+//MSI_MSG_DATA
+#define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+//MSI_MSG_DATA_64
+#define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+//MSI_MASK
+#define MSI_MASK__MSI_MASK__SHIFT 0x0
+//MSI_PENDING
+#define MSI_PENDING__MSI_PENDING__SHIFT 0x0
+//MSI_MASK_64
+#define MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+//MSI_PENDING_64
+#define MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+//MSIX_CAP_LIST
+#define MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+//MSIX_MSG_CNTL
+#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+//MSIX_TABLE
+#define MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+//MSIX_PBA
+#define MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+//PCIE_VENDOR_SPECIFIC_HDR
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+//PCIE_VENDOR_SPECIFIC1
+#define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC2
+#define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+//PCIE_VC_ENH_CAP_LIST
+#define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+//PCIE_PORT_VC_CAP_REG1
+#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+//PCIE_PORT_VC_CAP_REG2
+#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+//PCIE_PORT_VC_CNTL
+#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+//PCIE_PORT_VC_STATUS
+#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+//PCIE_VC0_RESOURCE_CAP
+#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+//PCIE_VC0_RESOURCE_CNTL
+#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+//PCIE_VC0_RESOURCE_STATUS
+#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+//PCIE_VC1_RESOURCE_CAP
+#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+//PCIE_VC1_RESOURCE_CNTL
+#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+//PCIE_VC1_RESOURCE_STATUS
+#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+//PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+//PCIE_DEV_SERIAL_NUM_DW1
+#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+//PCIE_DEV_SERIAL_NUM_DW2
+#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+//PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+//PCIE_UNCORR_ERR_STATUS
+#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+//PCIE_UNCORR_ERR_MASK
+#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+//PCIE_UNCORR_ERR_SEVERITY
+#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+//PCIE_CORR_ERR_STATUS
+#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+//PCIE_CORR_ERR_MASK
+#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+//PCIE_ADV_ERR_CAP_CNTL
+#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+//PCIE_HDR_LOG0
+#define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+//PCIE_HDR_LOG1
+#define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+//PCIE_HDR_LOG2
+#define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+//PCIE_HDR_LOG3
+#define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+//PCIE_ROOT_ERR_CMD
+#define PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+//PCIE_ROOT_ERR_STATUS
+#define PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+//PCIE_ERR_SRC_ID
+#define PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+//PCIE_TLP_PREFIX_LOG0
+#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+//PCIE_TLP_PREFIX_LOG1
+#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+//PCIE_TLP_PREFIX_LOG2
+#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+//PCIE_TLP_PREFIX_LOG3
+#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+//PCIE_BAR_ENH_CAP_LIST
+#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+//PCIE_BAR1_CAP
+#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+//PCIE_BAR1_CNTL
+#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+//PCIE_BAR2_CAP
+#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+//PCIE_BAR2_CNTL
+#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+//PCIE_BAR3_CAP
+#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+//PCIE_BAR3_CNTL
+#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+//PCIE_BAR4_CAP
+#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+//PCIE_BAR4_CNTL
+#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+//PCIE_BAR5_CAP
+#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+//PCIE_BAR5_CNTL
+#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+//PCIE_BAR6_CAP
+#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+//PCIE_BAR6_CNTL
+#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+//PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+//PCIE_PWR_BUDGET_DATA_SELECT
+#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+//PCIE_PWR_BUDGET_DATA
+#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+//PCIE_PWR_BUDGET_CAP
+#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+//PCIE_DPA_ENH_CAP_LIST
+#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+//PCIE_DPA_CAP
+#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+//PCIE_DPA_LATENCY_INDICATOR
+#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+//PCIE_DPA_STATUS
+#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+//PCIE_DPA_CNTL
+#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+//PCIE_SECONDARY_ENH_CAP_LIST
+#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+//PCIE_LINK_CNTL3
+#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+//PCIE_LANE_ERROR_STATUS
+#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+//PCIE_LANE_0_EQUALIZATION_CNTL
+#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+//PCIE_LANE_1_EQUALIZATION_CNTL
+#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+//PCIE_LANE_2_EQUALIZATION_CNTL
+#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+//PCIE_LANE_3_EQUALIZATION_CNTL
+#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+//PCIE_LANE_4_EQUALIZATION_CNTL
+#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+//PCIE_LANE_5_EQUALIZATION_CNTL
+#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+//PCIE_LANE_6_EQUALIZATION_CNTL
+#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+//PCIE_LANE_7_EQUALIZATION_CNTL
+#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+//PCIE_LANE_8_EQUALIZATION_CNTL
+#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+//PCIE_LANE_9_EQUALIZATION_CNTL
+#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+//PCIE_LANE_10_EQUALIZATION_CNTL
+#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+//PCIE_LANE_11_EQUALIZATION_CNTL
+#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+//PCIE_LANE_12_EQUALIZATION_CNTL
+#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+//PCIE_LANE_13_EQUALIZATION_CNTL
+#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+//PCIE_LANE_14_EQUALIZATION_CNTL
+#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+//PCIE_LANE_15_EQUALIZATION_CNTL
+#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+//PCIE_ACS_ENH_CAP_LIST
+#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+//PCIE_ACS_CAP
+#define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+//PCIE_ACS_CNTL
+#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+//PCIE_ATS_ENH_CAP_LIST
+#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+//PCIE_ATS_CAP
+#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+//PCIE_ATS_CNTL
+#define PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+//PCIE_PAGE_REQ_ENH_CAP_LIST
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+//PCIE_PAGE_REQ_CNTL
+#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+//PCIE_PAGE_REQ_STATUS
+#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+//PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+//PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+//PCIE_PASID_ENH_CAP_LIST
+#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+//PCIE_PASID_CAP
+#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+//PCIE_PASID_CNTL
+#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+//PCIE_TPH_REQR_ENH_CAP_LIST
+#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+//PCIE_TPH_REQR_CAP
+#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+//PCIE_TPH_REQR_CNTL
+#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+//PCIE_MC_ENH_CAP_LIST
+#define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+//PCIE_MC_CAP
+#define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+//PCIE_MC_CNTL
+#define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+//PCIE_MC_ADDR0
+#define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+//PCIE_MC_ADDR1
+#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+//PCIE_MC_RCV0
+#define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+//PCIE_MC_RCV1
+#define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+//PCIE_MC_BLOCK_ALL0
+#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+//PCIE_MC_BLOCK_ALL1
+#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+//PCIE_MC_BLOCK_UNTRANSLATED_0
+#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+//PCIE_MC_BLOCK_UNTRANSLATED_1
+#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+//PCIE_LTR_ENH_CAP_LIST
+#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+//PCIE_LTR_CAP
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+//PCIE_ARI_ENH_CAP_LIST
+#define PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+//PCIE_ARI_CAP
+#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+//PCIE_ARI_CNTL
+#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+//PCIE_SRIOV_ENH_CAP_LIST
+#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+//PCIE_SRIOV_CAP
+#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+//PCIE_SRIOV_CONTROL
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+//PCIE_SRIOV_STATUS
+#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+//PCIE_SRIOV_INITIAL_VFS
+#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+//PCIE_SRIOV_TOTAL_VFS
+#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+//PCIE_SRIOV_NUM_VFS
+#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+//PCIE_SRIOV_FUNC_DEP_LINK
+#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+//PCIE_SRIOV_FIRST_VF_OFFSET
+#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+//PCIE_SRIOV_VF_STRIDE
+#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+//PCIE_SRIOV_VF_DEVICE_ID
+#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+//PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+//PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+//PCIE_SRIOV_VF_BASE_ADDR_0
+#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+//PCIE_SRIOV_VF_BASE_ADDR_1
+#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+//PCIE_SRIOV_VF_BASE_ADDR_2
+#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+//PCIE_SRIOV_VF_BASE_ADDR_3
+#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+//PCIE_SRIOV_VF_BASE_ADDR_4
+#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+//PCIE_SRIOV_VF_BASE_ADDR_5
+#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+//PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0
+#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+
+
+// addressBlock: bif_cfg_dev0_swds_bifcfgdecp
+//SUB_BUS_NUMBER_LATENCY
+#define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+//IO_BASE_LIMIT
+#define IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+//SECONDARY_STATUS
+#define SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+//MEM_BASE_LIMIT
+#define MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+//PREF_BASE_LIMIT
+#define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+//PREF_BASE_UPPER
+#define PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+//PREF_LIMIT_UPPER
+#define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+//IO_BASE_LIMIT_HI
+#define IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+//IRQ_BRIDGE_CNTL
+#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+//SLOT_CAP
+#define SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+//SLOT_CNTL
+#define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+//SLOT_STATUS
+#define SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+//SSID_CAP_LIST
+#define SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+//SSID_CAP
+#define SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+
+
+// addressBlock: rcc_shadow_reg_shadowdec
+//SHADOW_COMMAND
+#define SHADOW_COMMAND__IOEN_UP__SHIFT 0x0
+#define SHADOW_COMMAND__MEMEN_UP__SHIFT 0x1
+//SHADOW_BASE_ADDR_1
+#define SHADOW_BASE_ADDR_1__BAR1_UP__SHIFT 0x0
+//SHADOW_BASE_ADDR_2
+#define SHADOW_BASE_ADDR_2__BAR2_UP__SHIFT 0x0
+//SHADOW_SUB_BUS_NUMBER_LATENCY
+#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__SHIFT 0x8
+#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__SHIFT 0x10
+//SHADOW_IO_BASE_LIMIT
+#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__SHIFT 0x4
+#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__SHIFT 0xc
+//SHADOW_MEM_BASE_LIMIT
+#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__SHIFT 0x4
+#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__SHIFT 0x14
+//SHADOW_PREF_BASE_LIMIT
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__SHIFT 0x4
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__SHIFT 0x14
+//SHADOW_PREF_BASE_UPPER
+#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__SHIFT 0x0
+//SHADOW_PREF_LIMIT_UPPER
+#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__SHIFT 0x0
+//SHADOW_IO_BASE_LIMIT_HI
+#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__SHIFT 0x0
+#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__SHIFT 0x10
+//SHADOW_IRQ_BRIDGE_CNTL
+#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__SHIFT 0x2
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__SHIFT 0x3
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__SHIFT 0x4
+#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__SHIFT 0x6
+//SUC_INDEX
+#define SUC_INDEX__SUC_INDEX__SHIFT 0x0
+//SUC_DATA
+#define SUC_DATA__SUC_DATA__SHIFT 0x0
+
+
+// addressBlock: bif_bx_pf_SUMDEC
+//SUM_INDEX
+#define SUM_INDEX__SUM_INDEX__SHIFT 0x0
+//SUM_DATA
+#define SUM_DATA__SUM_DATA__SHIFT 0x0
+
+
+// addressBlock: gdc_GDCDEC
+//A2S_CNTL_CL0
+#define A2S_CNTL_CL0__NSNOOP_MAP__SHIFT 0x0
+#define A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT 0x2
+#define A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT 0x4
+#define A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT 0x6
+#define A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8
+#define A2S_CNTL_CL0__BLKLVL_MAP__SHIFT 0xa
+#define A2S_CNTL_CL0__DATERR_MAP__SHIFT 0xc
+#define A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT 0xe
+#define A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT 0x10
+#define A2S_CNTL_CL0__RESP_WR_MAP__SHIFT 0x12
+#define A2S_CNTL_CL0__RESP_RD_MAP__SHIFT 0x14
+//A2S_CNTL_CL1
+#define A2S_CNTL_CL1__NSNOOP_MAP__SHIFT 0x0
+#define A2S_CNTL_CL1__REQPASSPW_VC0_MAP__SHIFT 0x2
+#define A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__SHIFT 0x4
+#define A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__SHIFT 0x6
+#define A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8
+#define A2S_CNTL_CL1__BLKLVL_MAP__SHIFT 0xa
+#define A2S_CNTL_CL1__DATERR_MAP__SHIFT 0xc
+#define A2S_CNTL_CL1__EXOKAY_WR_MAP__SHIFT 0xe
+#define A2S_CNTL_CL1__EXOKAY_RD_MAP__SHIFT 0x10
+#define A2S_CNTL_CL1__RESP_WR_MAP__SHIFT 0x12
+#define A2S_CNTL_CL1__RESP_RD_MAP__SHIFT 0x14
+//A2S_CNTL_CL2
+#define A2S_CNTL_CL2__NSNOOP_MAP__SHIFT 0x0
+#define A2S_CNTL_CL2__REQPASSPW_VC0_MAP__SHIFT 0x2
+#define A2S_CNTL_CL2__REQPASSPW_NVC0_MAP__SHIFT 0x4
+#define A2S_CNTL_CL2__REQRSPPASSPW_VC0_MAP__SHIFT 0x6
+#define A2S_CNTL_CL2__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8
+#define A2S_CNTL_CL2__BLKLVL_MAP__SHIFT 0xa
+#define A2S_CNTL_CL2__DATERR_MAP__SHIFT 0xc
+#define A2S_CNTL_CL2__EXOKAY_WR_MAP__SHIFT 0xe
+#define A2S_CNTL_CL2__EXOKAY_RD_MAP__SHIFT 0x10
+#define A2S_CNTL_CL2__RESP_WR_MAP__SHIFT 0x12
+#define A2S_CNTL_CL2__RESP_RD_MAP__SHIFT 0x14
+//A2S_CNTL_CL3
+#define A2S_CNTL_CL3__NSNOOP_MAP__SHIFT 0x0
+#define A2S_CNTL_CL3__REQPASSPW_VC0_MAP__SHIFT 0x2
+#define A2S_CNTL_CL3__REQPASSPW_NVC0_MAP__SHIFT 0x4
+#define A2S_CNTL_CL3__REQRSPPASSPW_VC0_MAP__SHIFT 0x6
+#define A2S_CNTL_CL3__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8
+#define A2S_CNTL_CL3__BLKLVL_MAP__SHIFT 0xa
+#define A2S_CNTL_CL3__DATERR_MAP__SHIFT 0xc
+#define A2S_CNTL_CL3__EXOKAY_WR_MAP__SHIFT 0xe
+#define A2S_CNTL_CL3__EXOKAY_RD_MAP__SHIFT 0x10
+#define A2S_CNTL_CL3__RESP_WR_MAP__SHIFT 0x12
+#define A2S_CNTL_CL3__RESP_RD_MAP__SHIFT 0x14
+//A2S_CNTL_CL4
+#define A2S_CNTL_CL4__NSNOOP_MAP__SHIFT 0x0
+#define A2S_CNTL_CL4__REQPASSPW_VC0_MAP__SHIFT 0x2
+#define A2S_CNTL_CL4__REQPASSPW_NVC0_MAP__SHIFT 0x4
+#define A2S_CNTL_CL4__REQRSPPASSPW_VC0_MAP__SHIFT 0x6
+#define A2S_CNTL_CL4__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8
+#define A2S_CNTL_CL4__BLKLVL_MAP__SHIFT 0xa
+#define A2S_CNTL_CL4__DATERR_MAP__SHIFT 0xc
+#define A2S_CNTL_CL4__EXOKAY_WR_MAP__SHIFT 0xe
+#define A2S_CNTL_CL4__EXOKAY_RD_MAP__SHIFT 0x10
+#define A2S_CNTL_CL4__RESP_WR_MAP__SHIFT 0x12
+#define A2S_CNTL_CL4__RESP_RD_MAP__SHIFT 0x14
+//A2S_CNTL_SW0
+#define A2S_CNTL_SW0__WR_TAG_SET_MIN__SHIFT 0x0
+#define A2S_CNTL_SW0__RD_TAG_SET_MIN__SHIFT 0x3
+#define A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__SHIFT 0x6
+#define A2S_CNTL_SW0__RSP_REORDER_DIS__SHIFT 0x7
+#define A2S_CNTL_SW0__WRRSP_ACCUM_SEL__SHIFT 0x8
+#define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT 0x9
+#define A2S_CNTL_SW0__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xa
+#define A2S_CNTL_SW0__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xb
+#define A2S_CNTL_SW0__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0xc
+#define A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT 0x10
+#define A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT 0x18
+//A2S_CNTL_SW1
+#define A2S_CNTL_SW1__WR_TAG_SET_MIN__SHIFT 0x0
+#define A2S_CNTL_SW1__RD_TAG_SET_MIN__SHIFT 0x3
+#define A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__SHIFT 0x6
+#define A2S_CNTL_SW1__RSP_REORDER_DIS__SHIFT 0x7
+#define A2S_CNTL_SW1__WRRSP_ACCUM_SEL__SHIFT 0x8
+#define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT 0x9
+#define A2S_CNTL_SW1__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xa
+#define A2S_CNTL_SW1__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xb
+#define A2S_CNTL_SW1__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0xc
+#define A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT 0x10
+#define A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT 0x18
+//A2S_CNTL_SW2
+#define A2S_CNTL_SW2__WR_TAG_SET_MIN__SHIFT 0x0
+#define A2S_CNTL_SW2__RD_TAG_SET_MIN__SHIFT 0x3
+#define A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__SHIFT 0x6
+#define A2S_CNTL_SW2__RSP_REORDER_DIS__SHIFT 0x7
+#define A2S_CNTL_SW2__WRRSP_ACCUM_SEL__SHIFT 0x8
+#define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__SHIFT 0x9
+#define A2S_CNTL_SW2__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xa
+#define A2S_CNTL_SW2__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xb
+#define A2S_CNTL_SW2__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0xc
+#define A2S_CNTL_SW2__WRR_RD_WEIGHT__SHIFT 0x10
+#define A2S_CNTL_SW2__WRR_WR_WEIGHT__SHIFT 0x18
+//NGDC_MGCG_CTRL
+#define NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x0
+#define NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x1
+#define NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x2
+//A2S_MISC_CNTL
+#define A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT 0x0
+#define A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT 0x2
+//NGDC_SDP_PORT_CTRL
+#define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0
+//NGDC_RESERVED_0
+#define NGDC_RESERVED_0__RESERVED__SHIFT 0x0
+//NGDC_RESERVED_1
+#define NGDC_RESERVED_1__RESERVED__SHIFT 0x0
+//BIF_SDMA0_DOORBELL_RANGE
+#define BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10
+//BIF_SDMA1_DOORBELL_RANGE
+#define BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10
+//BIF_IH_DOORBELL_RANGE
+#define BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10
+//BIF_MMSCH0_DOORBELL_RANGE
+#define BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT 0x10
+//BIF_DOORBELL_FENCE_CNTL
+#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT 0x0
+//S2A_MISC_CNTL
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2
+//A2S_CNTL2_SEC_CL0
+#define A2S_CNTL2_SEC_CL0__SECLVL_MAP__SHIFT 0x0
+//A2S_CNTL2_SEC_CL1
+#define A2S_CNTL2_SEC_CL1__SECLVL_MAP__SHIFT 0x0
+//A2S_CNTL2_SEC_CL2
+#define A2S_CNTL2_SEC_CL2__SECLVL_MAP__SHIFT 0x0
+//A2S_CNTL2_SEC_CL3
+#define A2S_CNTL2_SEC_CL3__SECLVL_MAP__SHIFT 0x0
+//A2S_CNTL2_SEC_CL4
+#define A2S_CNTL2_SEC_CL4__SECLVL_MAP__SHIFT 0x0
+
+
+// addressBlock: nbif_sion_SIONDEC
+//SION_CL0_RdRsp_BurstTarget_REG0
+#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+//SION_CL0_RdRsp_BurstTarget_REG1
+#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+//SION_CL0_RdRsp_TimeSlot_REG0
+#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+//SION_CL0_RdRsp_TimeSlot_REG1
+#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+//SION_CL0_WrRsp_BurstTarget_REG0
+#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+//SION_CL0_WrRsp_BurstTarget_REG1
+#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+//SION_CL0_WrRsp_TimeSlot_REG0
+#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+//SION_CL0_WrRsp_TimeSlot_REG1
+#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+//SION_CL0_Req_BurstTarget_REG0
+#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+//SION_CL0_Req_BurstTarget_REG1
+#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+//SION_CL0_Req_TimeSlot_REG0
+#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+//SION_CL0_Req_TimeSlot_REG1
+#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+//SION_CL0_ReqPoolCredit_Alloc_REG0
+#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL0_ReqPoolCredit_Alloc_REG1
+#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL0_DataPoolCredit_Alloc_REG0
+#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL0_DataPoolCredit_Alloc_REG1
+#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL0_RdRspPoolCredit_Alloc_REG0
+#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL0_RdRspPoolCredit_Alloc_REG1
+#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL0_WrRspPoolCredit_Alloc_REG0
+#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL0_WrRspPoolCredit_Alloc_REG1
+#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL1_RdRsp_BurstTarget_REG0
+#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+//SION_CL1_RdRsp_BurstTarget_REG1
+#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+//SION_CL1_RdRsp_TimeSlot_REG0
+#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+//SION_CL1_RdRsp_TimeSlot_REG1
+#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+//SION_CL1_WrRsp_BurstTarget_REG0
+#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+//SION_CL1_WrRsp_BurstTarget_REG1
+#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+//SION_CL1_WrRsp_TimeSlot_REG0
+#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+//SION_CL1_WrRsp_TimeSlot_REG1
+#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+//SION_CL1_Req_BurstTarget_REG0
+#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+//SION_CL1_Req_BurstTarget_REG1
+#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+//SION_CL1_Req_TimeSlot_REG0
+#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+//SION_CL1_Req_TimeSlot_REG1
+#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+//SION_CL1_ReqPoolCredit_Alloc_REG0
+#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL1_ReqPoolCredit_Alloc_REG1
+#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL1_DataPoolCredit_Alloc_REG0
+#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL1_DataPoolCredit_Alloc_REG1
+#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL1_RdRspPoolCredit_Alloc_REG0
+#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL1_RdRspPoolCredit_Alloc_REG1
+#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL1_WrRspPoolCredit_Alloc_REG0
+#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL1_WrRspPoolCredit_Alloc_REG1
+#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL2_RdRsp_BurstTarget_REG0
+#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+//SION_CL2_RdRsp_BurstTarget_REG1
+#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+//SION_CL2_RdRsp_TimeSlot_REG0
+#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+//SION_CL2_RdRsp_TimeSlot_REG1
+#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+//SION_CL2_WrRsp_BurstTarget_REG0
+#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+//SION_CL2_WrRsp_BurstTarget_REG1
+#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+//SION_CL2_WrRsp_TimeSlot_REG0
+#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+//SION_CL2_WrRsp_TimeSlot_REG1
+#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+//SION_CL2_Req_BurstTarget_REG0
+#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+//SION_CL2_Req_BurstTarget_REG1
+#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+//SION_CL2_Req_TimeSlot_REG0
+#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+//SION_CL2_Req_TimeSlot_REG1
+#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+//SION_CL2_ReqPoolCredit_Alloc_REG0
+#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL2_ReqPoolCredit_Alloc_REG1
+#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL2_DataPoolCredit_Alloc_REG0
+#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL2_DataPoolCredit_Alloc_REG1
+#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL2_RdRspPoolCredit_Alloc_REG0
+#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL2_RdRspPoolCredit_Alloc_REG1
+#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL2_WrRspPoolCredit_Alloc_REG0
+#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL2_WrRspPoolCredit_Alloc_REG1
+#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL3_RdRsp_BurstTarget_REG0
+#define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+//SION_CL3_RdRsp_BurstTarget_REG1
+#define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+//SION_CL3_RdRsp_TimeSlot_REG0
+#define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+//SION_CL3_RdRsp_TimeSlot_REG1
+#define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+//SION_CL3_WrRsp_BurstTarget_REG0
+#define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+//SION_CL3_WrRsp_BurstTarget_REG1
+#define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+//SION_CL3_WrRsp_TimeSlot_REG0
+#define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+//SION_CL3_WrRsp_TimeSlot_REG1
+#define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+//SION_CL3_Req_BurstTarget_REG0
+#define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+//SION_CL3_Req_BurstTarget_REG1
+#define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+//SION_CL3_Req_TimeSlot_REG0
+#define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+//SION_CL3_Req_TimeSlot_REG1
+#define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+//SION_CL3_ReqPoolCredit_Alloc_REG0
+#define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL3_ReqPoolCredit_Alloc_REG1
+#define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL3_DataPoolCredit_Alloc_REG0
+#define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL3_DataPoolCredit_Alloc_REG1
+#define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL3_RdRspPoolCredit_Alloc_REG0
+#define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL3_RdRspPoolCredit_Alloc_REG1
+#define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL3_WrRspPoolCredit_Alloc_REG0
+#define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL3_WrRspPoolCredit_Alloc_REG1
+#define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL4_RdRsp_BurstTarget_REG0
+#define SION_CL4_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+//SION_CL4_RdRsp_BurstTarget_REG1
+#define SION_CL4_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+//SION_CL4_RdRsp_TimeSlot_REG0
+#define SION_CL4_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+//SION_CL4_RdRsp_TimeSlot_REG1
+#define SION_CL4_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+//SION_CL4_WrRsp_BurstTarget_REG0
+#define SION_CL4_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+//SION_CL4_WrRsp_BurstTarget_REG1
+#define SION_CL4_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+//SION_CL4_WrRsp_TimeSlot_REG0
+#define SION_CL4_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+//SION_CL4_WrRsp_TimeSlot_REG1
+#define SION_CL4_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+//SION_CL4_Req_BurstTarget_REG0
+#define SION_CL4_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+//SION_CL4_Req_BurstTarget_REG1
+#define SION_CL4_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+//SION_CL4_Req_TimeSlot_REG0
+#define SION_CL4_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+//SION_CL4_Req_TimeSlot_REG1
+#define SION_CL4_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+//SION_CL4_ReqPoolCredit_Alloc_REG0
+#define SION_CL4_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL4_ReqPoolCredit_Alloc_REG1
+#define SION_CL4_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL4_DataPoolCredit_Alloc_REG0
+#define SION_CL4_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL4_DataPoolCredit_Alloc_REG1
+#define SION_CL4_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL4_RdRspPoolCredit_Alloc_REG0
+#define SION_CL4_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL4_RdRspPoolCredit_Alloc_REG1
+#define SION_CL4_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL4_WrRspPoolCredit_Alloc_REG0
+#define SION_CL4_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL4_WrRspPoolCredit_Alloc_REG1
+#define SION_CL4_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL5_RdRsp_BurstTarget_REG0
+#define SION_CL5_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+//SION_CL5_RdRsp_BurstTarget_REG1
+#define SION_CL5_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+//SION_CL5_RdRsp_TimeSlot_REG0
+#define SION_CL5_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+//SION_CL5_RdRsp_TimeSlot_REG1
+#define SION_CL5_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+//SION_CL5_WrRsp_BurstTarget_REG0
+#define SION_CL5_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+//SION_CL5_WrRsp_BurstTarget_REG1
+#define SION_CL5_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+//SION_CL5_WrRsp_TimeSlot_REG0
+#define SION_CL5_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+//SION_CL5_WrRsp_TimeSlot_REG1
+#define SION_CL5_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+//SION_CL5_Req_BurstTarget_REG0
+#define SION_CL5_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+//SION_CL5_Req_BurstTarget_REG1
+#define SION_CL5_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+//SION_CL5_Req_TimeSlot_REG0
+#define SION_CL5_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+//SION_CL5_Req_TimeSlot_REG1
+#define SION_CL5_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+//SION_CL5_ReqPoolCredit_Alloc_REG0
+#define SION_CL5_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL5_ReqPoolCredit_Alloc_REG1
+#define SION_CL5_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL5_DataPoolCredit_Alloc_REG0
+#define SION_CL5_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL5_DataPoolCredit_Alloc_REG1
+#define SION_CL5_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL5_RdRspPoolCredit_Alloc_REG0
+#define SION_CL5_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL5_RdRspPoolCredit_Alloc_REG1
+#define SION_CL5_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CL5_WrRspPoolCredit_Alloc_REG0
+#define SION_CL5_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+//SION_CL5_WrRspPoolCredit_Alloc_REG1
+#define SION_CL5_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+//SION_CNTL_REG0
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13
+//SION_CNTL_REG1
+#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0
+#define SION_CNTL_REG1__CG_OFF_HYSTERESIS__SHIFT 0x8
+
+
+// addressBlock: syshub_mmreg_direct_syshubdirect
+//SYSHUB_DS_CTRL_SOCCLK
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17
+#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c
+#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f
+//SYSHUB_DS_CTRL2_SOCCLK
+#define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0
+//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0xf
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x10
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x11
+//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0xf
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x10
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x11
+//DMA_CLK0_SW0_SYSHUB_QOS_CNTL
+#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+//DMA_CLK0_SW1_SYSHUB_QOS_CNTL
+#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+//DMA_CLK0_SW0_CL0_CNTL
+#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//DMA_CLK0_SW0_CL1_CNTL
+#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//DMA_CLK0_SW0_CL2_CNTL
+#define DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//DMA_CLK0_SW0_CL3_CNTL
+#define DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//DMA_CLK0_SW0_CL4_CNTL
+#define DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//DMA_CLK0_SW0_CL5_CNTL
+#define DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//DMA_CLK0_SW1_CL0_CNTL
+#define DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//DMA_CLK0_SW2_CL0_CNTL
+#define DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//SYSHUB_CG_CNTL
+#define SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT 0x0
+#define SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT 0x8
+#define SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT 0x10
+//SYSHUB_TRANS_IDLE
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT 0x0
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT 0x1
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT 0x2
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT 0x3
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT 0x4
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT 0x5
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT 0x6
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT 0x7
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT 0x8
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT 0x9
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT 0xa
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT 0xb
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT 0xc
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT 0xd
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT 0xe
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT 0xf
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT 0x10
+//SYSHUB_HP_TIMER
+#define SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT 0x0
+//SYSHUB_SCRATCH
+#define SYSHUB_SCRATCH__SCRATCH__SHIFT 0x0
+//SYSHUB_DS_CTRL_SHUBCLK
+#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0
+#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1
+#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2
+#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3
+#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4
+#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5
+#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6
+#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7
+#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10
+#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11
+#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12
+#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13
+#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14
+#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15
+#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16
+#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17
+#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c
+#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f
+//SYSHUB_DS_CTRL2_SHUBCLK
+#define SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0
+//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT 0xf
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT 0x10
+//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT 0xf
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT 0x10
+//DMA_CLK1_SW0_SYSHUB_QOS_CNTL
+#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+//DMA_CLK1_SW1_SYSHUB_QOS_CNTL
+#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+//DMA_CLK1_SW0_CL0_CNTL
+#define DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//DMA_CLK1_SW0_CL1_CNTL
+#define DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//DMA_CLK1_SW0_CL2_CNTL
+#define DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//DMA_CLK1_SW0_CL3_CNTL
+#define DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//DMA_CLK1_SW0_CL4_CNTL
+#define DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//DMA_CLK1_SW1_CL0_CNTL
+#define DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//DMA_CLK1_SW1_CL1_CNTL
+#define DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//DMA_CLK1_SW1_CL2_CNTL
+#define DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//DMA_CLK1_SW1_CL3_CNTL
+#define DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//DMA_CLK1_SW1_CL4_CNTL
+#define DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+
+
+// addressBlock: gdc_ras_gdc_ras_regblk
+//GDC_RAS_LEAF0_CTRL
+#define GDC_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x0
+#define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x15
+//GDC_RAS_LEAF1_CTRL
+#define GDC_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x0
+#define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x15
+//GDC_RAS_LEAF2_CTRL
+#define GDC_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x0
+#define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x15
+//GDC_RAS_LEAF3_CTRL
+#define GDC_RAS_LEAF3_CTRL__POISON_DET_EN__SHIFT 0x0
+#define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED__SHIFT 0x15
+//GDC_RAS_LEAF4_CTRL
+#define GDC_RAS_LEAF4_CTRL__POISON_DET_EN__SHIFT 0x0
+#define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED__SHIFT 0x15
+//GDC_RAS_LEAF5_CTRL
+#define GDC_RAS_LEAF5_CTRL__POISON_DET_EN__SHIFT 0x0
+#define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED__SHIFT 0x15
+
+
+// addressBlock: gdc_rst_GDCRST_DEC
+//SHUB_PF_FLR_RST
+#define SHUB_PF_FLR_RST__PF0_FLR_RST__SHIFT 0x0
+#define SHUB_PF_FLR_RST__PF1_FLR_RST__SHIFT 0x1
+#define SHUB_PF_FLR_RST__PF2_FLR_RST__SHIFT 0x2
+#define SHUB_PF_FLR_RST__PF3_FLR_RST__SHIFT 0x3
+#define SHUB_PF_FLR_RST__PF4_FLR_RST__SHIFT 0x4
+#define SHUB_PF_FLR_RST__PF5_FLR_RST__SHIFT 0x5
+#define SHUB_PF_FLR_RST__PF6_FLR_RST__SHIFT 0x6
+#define SHUB_PF_FLR_RST__PF7_FLR_RST__SHIFT 0x7
+//SHUB_GFX_DRV_MODE1_RST
+#define SHUB_GFX_DRV_MODE1_RST__GFX_DRV_MODE1_RST__SHIFT 0x0
+//SHUB_LINK_RESET
+#define SHUB_LINK_RESET__LINK_RESET__SHIFT 0x0
+//SHUB_PF0_VF_FLR_RST
+#define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x0
+#define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x1
+#define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x2
+#define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x3
+#define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x4
+#define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x5
+#define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x6
+#define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x7
+#define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x8
+#define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x9
+#define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0xa
+#define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0xb
+#define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0xc
+#define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0xd
+#define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0xe
+#define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0xf
+#define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x1f
+//SHUB_HARD_RST_CTRL
+#define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT 0x0
+#define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT 0x1
+#define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT 0x2
+#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3
+#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4
+//SHUB_SOFT_RST_CTRL
+#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT 0x0
+#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT 0x1
+#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT 0x2
+#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3
+#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4
+//SHUB_SDP_PORT_RST
+#define SHUB_SDP_PORT_RST__SDP_PORT_RST__SHIFT 0x0
+
+
+// addressBlock: bif_bx_pf_SYSDEC
+//SBIOS_SCRATCH_0
+#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0
+//SBIOS_SCRATCH_1
+#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0
+//SBIOS_SCRATCH_2
+#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0
+//SBIOS_SCRATCH_3
+#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0
+//BIOS_SCRATCH_0
+#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0
+//BIOS_SCRATCH_1
+#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0
+//BIOS_SCRATCH_2
+#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
+//BIOS_SCRATCH_3
+#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
+//BIOS_SCRATCH_4
+#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0
+//BIOS_SCRATCH_5
+#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0
+//BIOS_SCRATCH_6
+#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
+//BIOS_SCRATCH_7
+#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0
+//BIOS_SCRATCH_8
+#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0
+//BIOS_SCRATCH_9
+#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0
+//BIOS_SCRATCH_10
+#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0
+//BIOS_SCRATCH_11
+#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0
+//BIOS_SCRATCH_12
+#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0
+//BIOS_SCRATCH_13
+#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0
+//BIOS_SCRATCH_14
+#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0
+//BIOS_SCRATCH_15
+#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0
+//BIF_RLC_INTR_CNTL
+#define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0
+#define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3
+//BIF_VCE_INTR_CNTL
+#define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0
+#define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3
+//BIF_UVD_INTR_CNTL
+#define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0
+#define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3
+//GFX_MMIOREG_CAM_ADDR0
+#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0
+//GFX_MMIOREG_CAM_REMAP_ADDR0
+#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0
+//GFX_MMIOREG_CAM_ADDR1
+#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0
+//GFX_MMIOREG_CAM_REMAP_ADDR1
+#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0
+//GFX_MMIOREG_CAM_ADDR2
+#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0
+//GFX_MMIOREG_CAM_REMAP_ADDR2
+#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0
+//GFX_MMIOREG_CAM_ADDR3
+#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0
+//GFX_MMIOREG_CAM_REMAP_ADDR3
+#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0
+//GFX_MMIOREG_CAM_ADDR4
+#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0
+//GFX_MMIOREG_CAM_REMAP_ADDR4
+#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0
+//GFX_MMIOREG_CAM_ADDR5
+#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0
+//GFX_MMIOREG_CAM_REMAP_ADDR5
+#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0
+//GFX_MMIOREG_CAM_ADDR6
+#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0
+//GFX_MMIOREG_CAM_REMAP_ADDR6
+#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0
+//GFX_MMIOREG_CAM_ADDR7
+#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0
+//GFX_MMIOREG_CAM_REMAP_ADDR7
+#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0
+//GFX_MMIOREG_CAM_CNTL
+#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0
+//GFX_MMIOREG_CAM_ZERO_CPL
+#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0
+//GFX_MMIOREG_CAM_ONE_CPL
+#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0
+//GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
+#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0
+
+
+// addressBlock: bif_bx_pf_SYSPFVFDEC
+//MM_INDEX
+#define MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define MM_INDEX__MM_APER__SHIFT 0x1f
+//MM_DATA
+#define MM_DATA__MM_DATA__SHIFT 0x0
+//MM_INDEX_HI
+#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+//SYSHUB_INDEX_OVLP
+#define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0
+//SYSHUB_DATA_OVLP
+#define SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0
+//PCIE_INDEX
+#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
+//PCIE_DATA
+#define PCIE_DATA__PCIE_DATA__SHIFT 0x0
+//PCIE_INDEX2
+#define PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0
+//PCIE_DATA2
+#define PCIE_DATA2__PCIE_DATA2__SHIFT 0x0
+
+
+// addressBlock: rcc_dwn_BIFDEC1
+//DN_PCIE_RESERVED
+#define DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+//DN_PCIE_SCRATCH
+#define DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+//DN_PCIE_CNTL
+#define DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7
+#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+//DN_PCIE_CONFIG_CNTL
+#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+//DN_PCIE_RX_CNTL2
+#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+//DN_PCIE_BUS_CNTL
+#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8
+//DN_PCIE_CFG_CNTL
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+//DN_PCIE_STRAP_F0
+#define DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
+#define DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
+#define DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
+//DN_PCIE_STRAP_MISC
+#define DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
+#define DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+//DN_PCIE_STRAP_MISC2
+#define DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
+
+
+// addressBlock: rcc_dwnp_BIFDEC1
+//PCIEP_RESERVED
+#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+//PCIEP_SCRATCH
+#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+//PCIE_ERR_CNTL
+#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+//PCIE_RX_CNTL
+#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9
+#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15
+#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+//PCIE_LC_SPEED_CNTL
+#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+//PCIE_LC_CNTL2
+#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+//PCIEP_STRAP_MISC
+#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
+//LTR_MSG_INFO_FROM_EP
+#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0
+
+
+// addressBlock: rcc_ep_BIFDEC1
+//EP_PCIE_SCRATCH
+#define EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+//EP_PCIE_CNTL
+#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+//EP_PCIE_INT_CNTL
+#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+//EP_PCIE_INT_STATUS
+#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+//EP_PCIE_RX_CNTL2
+#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+//EP_PCIE_BUS_CNTL
+#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+//EP_PCIE_CFG_CNTL
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+//EP_PCIE_OBFF_CNTL
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x0
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x1
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x3
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x4
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x8
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0xc
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x10
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x11
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x12
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0__SHIFT 0x13
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x14
+//EP_PCIE_TX_LTR_CNTL
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+//EP_PCIE_STRAP_MISC
+#define EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+//EP_PCIE_STRAP_MISC2
+#define EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
+//EP_PCIE_STRAP_PI
+//EP_PCIE_F0_DPA_CAP
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+//EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+//EP_PCIE_F0_DPA_CNTL
+#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+//EP_PCIE_PME_CONTROL
+#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0
+//EP_PCIEP_RESERVED
+#define EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+//EP_PCIE_TX_CNTL
+#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+//EP_PCIE_TX_REQUESTER_ID
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+//EP_PCIE_ERR_CNTL
+#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f
+//EP_PCIE_RX_CNTL
+#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+//EP_PCIE_LC_SPEED_CNTL
+#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+
+
+// addressBlock: bif_bx_pf_BIFDEC1
+//BIF_MM_INDACCESS_CNTL
+#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
+//BUS_CNTL
+#define BUS_CNTL__PMI_INT_DIS_EP__SHIFT 0x3
+#define BUS_CNTL__PMI_INT_DIS_DN__SHIFT 0x4
+#define BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x5
+#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
+#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
+#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa
+#define BUS_CNTL__SET_MC_TC__SHIFT 0xd
+#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
+#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
+#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
+#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x13
+#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x14
+#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x15
+#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x16
+#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x17
+#define BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x18
+//BIF_SCRATCH0
+#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
+//BIF_SCRATCH1
+#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
+//BX_RESET_EN
+#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0
+#define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1
+#define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2
+#define BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8
+#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10
+//MM_CFGREGS_CNTL
+#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
+#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6
+#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f
+//BX_RESET_CNTL
+#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0
+//INTERRUPT_CNTL
+#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
+#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
+#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
+#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
+#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
+#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
+//INTERRUPT_CNTL2
+#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
+//CLKREQB_PAD_CNTL
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd
+#define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER__SHIFT 0x18
+//CLKREQB_PERF_COUNTER
+#define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER__SHIFT 0x0
+//BIF_CLK_CTRL
+#define BIF_CLK_CTRL__BIF_XSTCLK_READY__SHIFT 0x0
+#define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__SHIFT 0x1
+//BIF_FEATURES_CONTROL_MISC
+#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0
+#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
+#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
+#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3
+#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9
+#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa
+#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb
+#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
+#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd
+#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf
+#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11
+#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12
+#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18
+//BIF_DOORBELL_CNTL
+#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0
+#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1
+#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
+#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
+#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b
+//BIF_DOORBELL_INT_CNTL
+#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0
+#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT 0x1
+#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
+#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT 0x11
+//BIF_SLVARB_MODE
+#define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x0
+//BIF_FB_EN
+#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0
+#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
+//BIF_BUSY_DELAY_CNTR
+#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0
+//BIF_PERFMON_CNTL
+#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x0
+#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x1
+#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2
+#define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x8
+#define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd
+//BIF_PERFCOUNTER0_RESULT
+#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0
+//BIF_PERFCOUNTER1_RESULT
+#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0
+//BIF_MST_TRANS_PENDING_VF
+#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0
+//BIF_SLV_TRANS_PENDING_VF
+#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0
+//BACO_CNTL
+#define BACO_CNTL__BACO_EN__SHIFT 0x0
+#define BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x1
+#define BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2
+#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3
+#define BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5
+#define BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6
+#define BACO_CNTL__BACO_MODE__SHIFT 0x8
+#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9
+#define BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f
+//BIF_BACO_EXIT_TIME0
+#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0
+//BIF_BACO_EXIT_TIMER1
+#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0
+#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a
+#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b
+#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c
+#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d
+#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f
+//BIF_BACO_EXIT_TIMER2
+#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0
+//BIF_BACO_EXIT_TIMER3
+#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0
+//BIF_BACO_EXIT_TIMER4
+#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0
+//MEM_TYPE_CNTL
+#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0
+//SMU_BIF_VDDGFX_PWR_STATUS
+#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0
+//BIF_VDDGFX_GFX0_LOWER
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f
+//BIF_VDDGFX_GFX0_UPPER
+#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2
+//BIF_VDDGFX_GFX1_LOWER
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f
+//BIF_VDDGFX_GFX1_UPPER
+#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2
+//BIF_VDDGFX_GFX2_LOWER
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f
+//BIF_VDDGFX_GFX2_UPPER
+#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2
+//BIF_VDDGFX_GFX3_LOWER
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f
+//BIF_VDDGFX_GFX3_UPPER
+#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2
+//BIF_VDDGFX_GFX4_LOWER
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f
+//BIF_VDDGFX_GFX4_UPPER
+#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2
+//BIF_VDDGFX_GFX5_LOWER
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f
+//BIF_VDDGFX_GFX5_UPPER
+#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2
+//BIF_VDDGFX_RSV1_LOWER
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f
+//BIF_VDDGFX_RSV1_UPPER
+#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2
+//BIF_VDDGFX_RSV2_LOWER
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f
+//BIF_VDDGFX_RSV2_UPPER
+#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2
+//BIF_VDDGFX_RSV3_LOWER
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f
+//BIF_VDDGFX_RSV3_UPPER
+#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2
+//BIF_VDDGFX_RSV4_LOWER
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f
+//BIF_VDDGFX_RSV4_UPPER
+#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2
+//BIF_VDDGFX_FB_CMP
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5
+//BIF_DOORBELL_GBLAPER1_LOWER
+#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2
+#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f
+//BIF_DOORBELL_GBLAPER1_UPPER
+#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2
+//BIF_DOORBELL_GBLAPER2_LOWER
+#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2
+#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f
+//BIF_DOORBELL_GBLAPER2_UPPER
+#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2
+//REMAP_HDP_MEM_FLUSH_CNTL
+#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+//REMAP_HDP_REG_FLUSH_CNTL
+#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+//BIF_RB_CNTL
+#define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
+#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
+#define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11
+#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+//BIF_RB_BASE
+#define BIF_RB_BASE__ADDR__SHIFT 0x0
+//BIF_RB_RPTR
+#define BIF_RB_RPTR__OFFSET__SHIFT 0x2
+//BIF_RB_WPTR
+#define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0
+#define BIF_RB_WPTR__OFFSET__SHIFT 0x2
+//BIF_RB_WPTR_ADDR_HI
+#define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
+//BIF_RB_WPTR_ADDR_LO
+#define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
+//MAILBOX_INDEX
+#define MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0
+//BIF_GPUIOV_RESET_NOTIFICATION
+#define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT 0x0
+//BIF_UVD_GPUIOV_CFG_SIZE
+#define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT 0x0
+//BIF_VCE_GPUIOV_CFG_SIZE
+#define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT 0x0
+//BIF_GFX_SDMA_GPUIOV_CFG_SIZE
+#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0
+//BIF_GMI_WRR_WEIGHT
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT__SHIFT 0x0
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT__SHIFT 0x8
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT__SHIFT 0x10
+//NBIF_STRAP_WRITE_CTRL
+#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT 0x0
+//BIF_PERSTB_PAD_CNTL
+#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0
+//BIF_PX_EN_PAD_CNTL
+#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0
+//BIF_REFPADKIN_PAD_CNTL
+#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0
+//BIF_CLKREQB_PAD_CNTL
+#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0
+
+
+// addressBlock: rcc_pf_0_BIFDEC1
+//RCC_BACO_CNTL_MISC
+#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0
+#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1
+//RCC_RESET_EN
+#define RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf
+//RCC_VDM_SUPPORT
+#define RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0
+#define RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1
+#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2
+#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3
+#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4
+//RCC_PEER_REG_RANGE0
+#define RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0
+#define RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10
+//RCC_PEER_REG_RANGE1
+#define RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0
+#define RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10
+//RCC_BUS_CNTL
+#define RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
+#define RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
+#define RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
+#define RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5
+#define RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6
+#define RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7
+#define RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8
+#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc
+#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd
+#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10
+#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11
+#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12
+#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13
+#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14
+#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15
+#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18
+#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19
+#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c
+#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d
+//RCC_CONFIG_CNTL
+#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0
+#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
+#define RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3
+//RCC_CONFIG_F0_BASE
+#define RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0
+//RCC_CONFIG_APER_SIZE
+#define RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0
+//RCC_CONFIG_REG_APER_SIZE
+#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0
+//RCC_XDMA_LO
+#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0
+#define RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f
+//RCC_XDMA_HI
+#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0
+//RCC_FEATURES_CONTROL_MISC
+#define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4
+#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5
+#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6
+#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd
+#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe
+#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf
+#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10
+#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11
+#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12
+//RCC_BUSNUM_CNTL1
+#define RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0
+//RCC_BUSNUM_LIST0
+#define RCC_BUSNUM_LIST0__ID0__SHIFT 0x0
+#define RCC_BUSNUM_LIST0__ID1__SHIFT 0x8
+#define RCC_BUSNUM_LIST0__ID2__SHIFT 0x10
+#define RCC_BUSNUM_LIST0__ID3__SHIFT 0x18
+//RCC_BUSNUM_LIST1
+#define RCC_BUSNUM_LIST1__ID4__SHIFT 0x0
+#define RCC_BUSNUM_LIST1__ID5__SHIFT 0x8
+#define RCC_BUSNUM_LIST1__ID6__SHIFT 0x10
+#define RCC_BUSNUM_LIST1__ID7__SHIFT 0x18
+//RCC_BUSNUM_CNTL2
+#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0
+#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8
+#define RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10
+#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11
+//RCC_CAPTURE_HOST_BUSNUM
+#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0
+//RCC_HOST_BUSNUM
+#define RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0
+//RCC_PEER0_FB_OFFSET_HI
+#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0
+//RCC_PEER0_FB_OFFSET_LO
+#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f
+//RCC_PEER1_FB_OFFSET_HI
+#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0
+//RCC_PEER1_FB_OFFSET_LO
+#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f
+//RCC_PEER2_FB_OFFSET_HI
+#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0
+//RCC_PEER2_FB_OFFSET_LO
+#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f
+//RCC_PEER3_FB_OFFSET_HI
+#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0
+//RCC_PEER3_FB_OFFSET_LO
+#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f
+//RCC_DEVFUNCNUM_LIST0
+#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0
+#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8
+#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10
+#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18
+//RCC_DEVFUNCNUM_LIST1
+#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0
+#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8
+#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10
+#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18
+//RCC_DEV0_LINK_CNTL
+#define RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0
+#define RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8
+//RCC_CMN_LINK_CNTL
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2
+#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3
+//RCC_EP_REQUESTERID_RESTORE
+#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0
+#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8
+//RCC_LTR_LSWITCH_CNTL
+#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0
+//RCC_MH_ARB_CNTL
+#define RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0
+#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1
+
+
+// addressBlock: rcc_pf_0_BIFDEC2
+//GFXMSIX_VECT0_ADDR_LO
+#define GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//GFXMSIX_VECT0_ADDR_HI
+#define GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//GFXMSIX_VECT0_MSG_DATA
+#define GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+//GFXMSIX_VECT0_CONTROL
+#define GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+//GFXMSIX_VECT1_ADDR_LO
+#define GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//GFXMSIX_VECT1_ADDR_HI
+#define GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//GFXMSIX_VECT1_MSG_DATA
+#define GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+//GFXMSIX_VECT1_CONTROL
+#define GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+//GFXMSIX_VECT2_ADDR_LO
+#define GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//GFXMSIX_VECT2_ADDR_HI
+#define GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//GFXMSIX_VECT2_MSG_DATA
+#define GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+//GFXMSIX_VECT2_CONTROL
+#define GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+//GFXMSIX_PBA
+#define GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+
+
+// addressBlock: rcc_strap_BIFDEC1
+//RCC_DEV0_PORT_STRAP0
+#define RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1
+#define RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2
+#define RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3
+#define RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4
+#define RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5
+#define RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15
+#define RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18
+#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19
+#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c
+#define RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f
+//RCC_DEV0_PORT_STRAP1
+#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0
+#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10
+//RCC_DEV0_PORT_STRAP2
+#define RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0
+#define RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1
+#define RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2
+#define RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3
+#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4
+#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5
+#define RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6
+#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7
+#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8
+#define RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9
+#define RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc
+#define RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd
+#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe
+#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf
+#define RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10
+#define RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x11
+#define RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x13
+#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14
+#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17
+#define RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a
+#define RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d
+//RCC_DEV0_PORT_STRAP3
+#define RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0
+#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1
+#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2
+#define RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3
+#define RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6
+#define RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7
+#define RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8
+#define RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9
+#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb
+#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe
+#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12
+#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15
+#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19
+#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b
+#define RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d
+#define RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT 0x1e
+#define RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f
+//RCC_DEV0_PORT_STRAP4
+#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0
+#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8
+#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10
+#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18
+//RCC_DEV0_PORT_STRAP5
+#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0
+#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8
+#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10
+#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11
+#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12
+#define RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13
+#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14
+#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d
+#define RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e
+#define RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f
+//RCC_DEV0_PORT_STRAP6
+#define RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0
+#define RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1
+//RCC_DEV0_PORT_STRAP7
+#define RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0
+#define RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8
+#define RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc
+#define RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10
+#define RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18
+#define RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d
+//RCC_DEV0_EPF0_STRAP0
+#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
+#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
+#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
+#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
+#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
+//RCC_DEV0_EPF0_STRAP1
+#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10
+//RCC_DEV0_EPF0_STRAP13
+#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0
+#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8
+#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10
+//RCC_DEV0_EPF0_STRAP2
+#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0
+#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1
+#define RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6
+#define RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7
+#define RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8
+#define RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9
+#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe
+#define RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf
+#define RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10
+#define RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11
+#define RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12
+#define RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14
+#define RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15
+#define RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16
+#define RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17
+#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18
+#define RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b
+#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d
+#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e
+#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f
+//RCC_DEV0_EPF0_STRAP3
+#define RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0
+#define RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1
+#define RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2
+#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12
+#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13
+#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14
+#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15
+#define RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18
+#define RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT 0x19
+#define RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a
+#define RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b
+//RCC_DEV0_EPF0_STRAP4
+#define RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__SHIFT 0x0
+#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14
+#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15
+#define RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16
+#define RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17
+#define RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c
+#define RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f
+//RCC_DEV0_EPF0_STRAP5
+#define RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0
+//RCC_DEV0_EPF0_STRAP8
+#define RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x0
+#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x1
+#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3
+#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x4
+#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x5
+#define RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7
+#define RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8
+#define RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9
+#define RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xc
+#define RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0xe
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x16
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x18
+#define RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x19
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x1a
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b
+#define RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e
+//RCC_DEV0_EPF0_STRAP9
+//RCC_DEV0_EPF1_STRAP0
+#define RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0
+#define RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10
+#define RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14
+#define RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c
+#define RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d
+#define RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e
+#define RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f
+//RCC_DEV0_EPF1_STRAP10
+#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT 0x0
+#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1
+//RCC_DEV0_EPF1_STRAP11
+#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT 0x0
+#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1
+//RCC_DEV0_EPF1_STRAP12
+#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT 0x0
+#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1
+//RCC_DEV0_EPF1_STRAP13
+#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0
+#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8
+#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10
+//RCC_DEV0_EPF1_STRAP2
+#define RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7
+#define RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8
+#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe
+#define RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10
+#define RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11
+#define RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12
+#define RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14
+#define RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15
+#define RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16
+#define RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17
+#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18
+//RCC_DEV0_EPF1_STRAP3
+#define RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0
+#define RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1
+#define RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2
+#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12
+#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13
+#define RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14
+#define RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18
+#define RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT 0x19
+#define RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a
+#define RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b
+//RCC_DEV0_EPF1_STRAP4
+#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14
+#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15
+#define RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16
+#define RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17
+#define RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c
+#define RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f
+//RCC_DEV0_EPF1_STRAP5
+#define RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0
+//RCC_DEV0_EPF1_STRAP6
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT 0x4
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19
+//RCC_DEV0_EPF1_STRAP7
+#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT 0x0
+#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT 0x1
+
+
+// addressBlock: bif_bx_pf_BIFPFVFDEC1
+//BIF_BME_STATUS
+#define BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+//BIF_ATOMIC_ERR_LOG
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+//DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+//DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+//DOORBELL_SELFRING_GPA_APER_CNTL
+#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+//HDP_REG_COHERENCY_FLUSH_CNTL
+#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+//HDP_MEM_COHERENCY_FLUSH_CNTL
+#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+//GPU_HDP_FLUSH_REQ
+#define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+//GPU_HDP_FLUSH_DONE
+#define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+//BIF_TRANS_PENDING
+#define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+//MAILBOX_MSGBUF_TRN_DW0
+#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+//MAILBOX_MSGBUF_TRN_DW1
+#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+//MAILBOX_MSGBUF_TRN_DW2
+#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+//MAILBOX_MSGBUF_TRN_DW3
+#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+//MAILBOX_MSGBUF_RCV_DW0
+#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+//MAILBOX_MSGBUF_RCV_DW1
+#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+//MAILBOX_MSGBUF_RCV_DW2
+#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+//MAILBOX_MSGBUF_RCV_DW3
+#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+//MAILBOX_CONTROL
+#define MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+//MAILBOX_INT_CNTL
+#define MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+//BIF_VMHV_MAILBOX
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+
+
+// addressBlock: rcc_pf_0_BIFPFVFDEC1
+//RCC_DOORBELL_APER_EN
+#define RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+//RCC_CONFIG_MEMSIZE
+#define RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+//RCC_CONFIG_RESERVED
+#define RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+//RCC_IOV_FUNC_IDENTIFIER
+#define RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+
+
+// addressBlock: syshub_mmreg_ind_syshubdec
+//SYSHUB_INDEX
+#define SYSHUB_INDEX__INDEX__SHIFT 0x0
+//SYSHUB_DATA
+#define SYSHUB_DATA__DATA__SHIFT 0x0
+
+
+// addressBlock: rcc_strap_rcc_strap_internal
+//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f
+//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10
+//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x11
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x13
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d
+//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT 0x1e
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f
+//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18
+//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f
+//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1
+//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d
+//RCC_DEV1_PORT_STRAP0
+#define RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1__SHIFT 0x1
+#define RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1__SHIFT 0x2
+#define RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1__SHIFT 0x3
+#define RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1__SHIFT 0x4
+#define RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1__SHIFT 0x5
+#define RCC_DEV1_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV1__SHIFT 0x15
+#define RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1__SHIFT 0x18
+#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1__SHIFT 0x19
+#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1__SHIFT 0x1c
+#define RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1__SHIFT 0x1f
+//RCC_DEV1_PORT_STRAP1
+#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1__SHIFT 0x10
+//RCC_DEV1_PORT_STRAP2
+#define RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1__SHIFT 0x1
+#define RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1__SHIFT 0x2
+#define RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1__SHIFT 0x3
+#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1__SHIFT 0x4
+#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV1__SHIFT 0x5
+#define RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1__SHIFT 0x6
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1__SHIFT 0x7
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1__SHIFT 0x8
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1__SHIFT 0x9
+#define RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1__SHIFT 0xc
+#define RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1__SHIFT 0xd
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1__SHIFT 0xe
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1__SHIFT 0xf
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1__SHIFT 0x10
+#define RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1__SHIFT 0x11
+#define RCC_DEV1_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV1__SHIFT 0x13
+#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1__SHIFT 0x14
+#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1__SHIFT 0x17
+#define RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1__SHIFT 0x1a
+#define RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1__SHIFT 0x1d
+//RCC_DEV1_PORT_STRAP3
+#define RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1__SHIFT 0x1
+#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1__SHIFT 0x2
+#define RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1__SHIFT 0x3
+#define RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1__SHIFT 0x6
+#define RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1__SHIFT 0x7
+#define RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1__SHIFT 0x8
+#define RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1__SHIFT 0x9
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT 0xb
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1__SHIFT 0xe
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT 0x12
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1__SHIFT 0x15
+#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1__SHIFT 0x19
+#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1__SHIFT 0x1b
+#define RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1__SHIFT 0x1d
+#define RCC_DEV1_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV1__SHIFT 0x1e
+#define RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1__SHIFT 0x1f
+//RCC_DEV1_PORT_STRAP4
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1__SHIFT 0x8
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1__SHIFT 0x10
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1__SHIFT 0x18
+//RCC_DEV1_PORT_STRAP5
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1__SHIFT 0x8
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1__SHIFT 0x10
+#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1__SHIFT 0x11
+#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1__SHIFT 0x12
+#define RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1__SHIFT 0x13
+#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1__SHIFT 0x14
+#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1__SHIFT 0x15
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1__SHIFT 0x17
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1__SHIFT 0x18
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1__SHIFT 0x19
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1__SHIFT 0x1a
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1__SHIFT 0x1b
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1__SHIFT 0x1c
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1__SHIFT 0x1d
+#define RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1__SHIFT 0x1e
+#define RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1__SHIFT 0x1f
+//RCC_DEV1_PORT_STRAP6
+#define RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1__SHIFT 0x1
+//RCC_DEV1_PORT_STRAP7
+#define RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1__SHIFT 0x8
+#define RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1__SHIFT 0xc
+#define RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1__SHIFT 0x10
+#define RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1__SHIFT 0x18
+#define RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1__SHIFT 0x1d
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT 0x19
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x1
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x4
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x5
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xc
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0xe
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x16
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x18
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x19
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x1a
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT 0x19
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT 0x4
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT 0x1
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10
+//RCC_DEV0_EPF2_STRAP0
+#define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__SHIFT 0x10
+#define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__SHIFT 0x14
+#define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__SHIFT 0x1c
+#define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__SHIFT 0x1d
+#define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__SHIFT 0x1e
+#define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__SHIFT 0x1f
+//RCC_DEV0_EPF2_STRAP2
+#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__SHIFT 0x7
+#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__SHIFT 0x8
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__SHIFT 0xe
+#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__SHIFT 0x10
+#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__SHIFT 0x11
+#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__SHIFT 0x14
+#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__SHIFT 0x15
+#define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__SHIFT 0x17
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__SHIFT 0x18
+//RCC_DEV0_EPF2_STRAP3
+#define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__SHIFT 0x1
+#define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__SHIFT 0x2
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__SHIFT 0x12
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__SHIFT 0x13
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__SHIFT 0x14
+#define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__SHIFT 0x18
+#define RCC_DEV0_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F2__SHIFT 0x19
+#define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__SHIFT 0x1a
+#define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__SHIFT 0x1b
+//RCC_DEV0_EPF2_STRAP4
+#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__SHIFT 0x14
+#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__SHIFT 0x15
+#define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__SHIFT 0x16
+#define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__SHIFT 0x17
+#define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__SHIFT 0x1c
+#define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__SHIFT 0x1f
+//RCC_DEV0_EPF2_STRAP5
+#define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP5__STRAP_SATAIDP_EN_DEV0_F2__SHIFT 0x18
+//RCC_DEV0_EPF2_STRAP6
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2__SHIFT 0x1
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F2__SHIFT 0x4
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2__SHIFT 0x8
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F2__SHIFT 0x9
+//RCC_DEV0_EPF2_STRAP13
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__SHIFT 0x8
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__SHIFT 0x10
+//RCC_DEV0_EPF3_STRAP0
+#define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__SHIFT 0x10
+#define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__SHIFT 0x14
+#define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__SHIFT 0x1c
+#define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__SHIFT 0x1d
+#define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__SHIFT 0x1e
+#define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__SHIFT 0x1f
+//RCC_DEV0_EPF3_STRAP2
+#define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__SHIFT 0x7
+#define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__SHIFT 0x8
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__SHIFT 0xe
+#define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__SHIFT 0x10
+#define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__SHIFT 0x11
+#define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__SHIFT 0x14
+#define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__SHIFT 0x15
+#define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__SHIFT 0x17
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__SHIFT 0x18
+//RCC_DEV0_EPF3_STRAP3
+#define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__SHIFT 0x1
+#define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__SHIFT 0x2
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__SHIFT 0x12
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__SHIFT 0x13
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__SHIFT 0x14
+#define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__SHIFT 0x18
+#define RCC_DEV0_EPF3_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F3__SHIFT 0x19
+#define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__SHIFT 0x1a
+#define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__SHIFT 0x1b
+//RCC_DEV0_EPF3_STRAP4
+#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__SHIFT 0x14
+#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__SHIFT 0x15
+#define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__SHIFT 0x16
+#define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__SHIFT 0x17
+#define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__SHIFT 0x1c
+#define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3__SHIFT 0x1f
+//RCC_DEV0_EPF3_STRAP5
+#define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESEL_DEV0_F3__SHIFT 0x10
+#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESELD_DEV0_F3__SHIFT 0x14
+//RCC_DEV0_EPF3_STRAP6
+#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F3__SHIFT 0x1
+#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F3__SHIFT 0x4
+//RCC_DEV0_EPF3_STRAP13
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__SHIFT 0x8
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__SHIFT 0x10
+//RCC_DEV0_EPF4_STRAP0
+#define RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4__SHIFT 0x0
+#define RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4__SHIFT 0x10
+#define RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4__SHIFT 0x14
+#define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4__SHIFT 0x1c
+#define RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4__SHIFT 0x1d
+#define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4__SHIFT 0x1e
+#define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4__SHIFT 0x1f
+//RCC_DEV0_EPF4_STRAP2
+#define RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4__SHIFT 0x7
+#define RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4__SHIFT 0x8
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4__SHIFT 0xe
+#define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4__SHIFT 0x10
+#define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4__SHIFT 0x11
+#define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4__SHIFT 0x14
+#define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4__SHIFT 0x15
+#define RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4__SHIFT 0x17
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4__SHIFT 0x18
+//RCC_DEV0_EPF4_STRAP3
+#define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4__SHIFT 0x0
+#define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4__SHIFT 0x1
+#define RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4__SHIFT 0x2
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4__SHIFT 0x12
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4__SHIFT 0x13
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4__SHIFT 0x14
+#define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4__SHIFT 0x18
+#define RCC_DEV0_EPF4_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F4__SHIFT 0x19
+#define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4__SHIFT 0x1a
+#define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4__SHIFT 0x1b
+//RCC_DEV0_EPF4_STRAP4
+#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4__SHIFT 0x14
+#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4__SHIFT 0x15
+#define RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4__SHIFT 0x16
+#define RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4__SHIFT 0x17
+#define RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4__SHIFT 0x1c
+#define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4__SHIFT 0x1f
+//RCC_DEV0_EPF4_STRAP5
+#define RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4__SHIFT 0x0
+#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESEL_DEV0_F4__SHIFT 0x10
+#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESELD_DEV0_F4__SHIFT 0x14
+//RCC_DEV0_EPF4_STRAP6
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4__SHIFT 0x0
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x1
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F4__SHIFT 0x4
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_EN_DEV0_F4__SHIFT 0x8
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x9
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_EN_DEV0_F4__SHIFT 0x10
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x11
+//RCC_DEV0_EPF4_STRAP13
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4__SHIFT 0x0
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4__SHIFT 0x8
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4__SHIFT 0x10
+//RCC_DEV0_EPF5_STRAP0
+#define RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5__SHIFT 0x0
+#define RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5__SHIFT 0x10
+#define RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5__SHIFT 0x14
+#define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5__SHIFT 0x1c
+#define RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5__SHIFT 0x1d
+#define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5__SHIFT 0x1e
+#define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5__SHIFT 0x1f
+//RCC_DEV0_EPF5_STRAP2
+#define RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5__SHIFT 0x7
+#define RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5__SHIFT 0x8
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5__SHIFT 0xe
+#define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5__SHIFT 0x10
+#define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5__SHIFT 0x11
+#define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5__SHIFT 0x14
+#define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5__SHIFT 0x15
+#define RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5__SHIFT 0x17
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5__SHIFT 0x18
+//RCC_DEV0_EPF5_STRAP3
+#define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5__SHIFT 0x0
+#define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5__SHIFT 0x1
+#define RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5__SHIFT 0x2
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5__SHIFT 0x12
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5__SHIFT 0x13
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5__SHIFT 0x14
+#define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5__SHIFT 0x18
+#define RCC_DEV0_EPF5_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F5__SHIFT 0x19
+#define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5__SHIFT 0x1a
+#define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5__SHIFT 0x1b
+//RCC_DEV0_EPF5_STRAP4
+#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5__SHIFT 0x14
+#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5__SHIFT 0x15
+#define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5__SHIFT 0x16
+#define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5__SHIFT 0x17
+#define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5__SHIFT 0x1c
+#define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5__SHIFT 0x1f
+//RCC_DEV0_EPF5_STRAP5
+#define RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5__SHIFT 0x0
+//RCC_DEV0_EPF5_STRAP6
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5__SHIFT 0x0
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x1
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F5__SHIFT 0x4
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_EN_DEV0_F5__SHIFT 0x8
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x9
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_EN_DEV0_F5__SHIFT 0x10
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x11
+//RCC_DEV0_EPF5_STRAP13
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5__SHIFT 0x0
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5__SHIFT 0x8
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5__SHIFT 0x10
+//RCC_DEV0_EPF6_STRAP0
+#define RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6__SHIFT 0x0
+#define RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6__SHIFT 0x10
+#define RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6__SHIFT 0x14
+#define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6__SHIFT 0x1c
+#define RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6__SHIFT 0x1d
+#define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6__SHIFT 0x1e
+#define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6__SHIFT 0x1f
+//RCC_DEV0_EPF6_STRAP2
+#define RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6__SHIFT 0x7
+#define RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6__SHIFT 0x8
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6__SHIFT 0xe
+#define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6__SHIFT 0x10
+#define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6__SHIFT 0x11
+#define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6__SHIFT 0x14
+#define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6__SHIFT 0x15
+#define RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6__SHIFT 0x17
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6__SHIFT 0x18
+//RCC_DEV0_EPF6_STRAP3
+#define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6__SHIFT 0x0
+#define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6__SHIFT 0x1
+#define RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6__SHIFT 0x2
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6__SHIFT 0x12
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6__SHIFT 0x13
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6__SHIFT 0x14
+#define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6__SHIFT 0x18
+#define RCC_DEV0_EPF6_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F6__SHIFT 0x19
+#define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6__SHIFT 0x1a
+#define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6__SHIFT 0x1b
+//RCC_DEV0_EPF6_STRAP4
+#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6__SHIFT 0x14
+#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6__SHIFT 0x15
+#define RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6__SHIFT 0x16
+#define RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6__SHIFT 0x17
+#define RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6__SHIFT 0x1c
+#define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6__SHIFT 0x1f
+//RCC_DEV0_EPF6_STRAP5
+#define RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6__SHIFT 0x0
+//RCC_DEV0_EPF6_STRAP6
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6__SHIFT 0x0
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x1
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F6__SHIFT 0x4
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_EN_DEV0_F6__SHIFT 0x8
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x9
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_EN_DEV0_F6__SHIFT 0x10
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x11
+//RCC_DEV0_EPF6_STRAP13
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6__SHIFT 0x0
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6__SHIFT 0x8
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6__SHIFT 0x10
+//RCC_DEV0_EPF7_STRAP0
+#define RCC_DEV0_EPF7_STRAP0__STRAP_DEVICE_ID_DEV0_F7__SHIFT 0x0
+#define RCC_DEV0_EPF7_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F7__SHIFT 0x10
+#define RCC_DEV0_EPF7_STRAP0__STRAP_MINOR_REV_ID_DEV0_F7__SHIFT 0x14
+#define RCC_DEV0_EPF7_STRAP0__STRAP_FUNC_EN_DEV0_F7__SHIFT 0x1c
+#define RCC_DEV0_EPF7_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7__SHIFT 0x1d
+#define RCC_DEV0_EPF7_STRAP0__STRAP_D1_SUPPORT_DEV0_F7__SHIFT 0x1e
+#define RCC_DEV0_EPF7_STRAP0__STRAP_D2_SUPPORT_DEV0_F7__SHIFT 0x1f
+//RCC_DEV0_EPF7_STRAP2
+#define RCC_DEV0_EPF7_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F7__SHIFT 0x7
+#define RCC_DEV0_EPF7_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F7__SHIFT 0x8
+#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7__SHIFT 0xe
+#define RCC_DEV0_EPF7_STRAP2__STRAP_AER_EN_DEV0_F7__SHIFT 0x10
+#define RCC_DEV0_EPF7_STRAP2__STRAP_ACS_EN_DEV0_F7__SHIFT 0x11
+#define RCC_DEV0_EPF7_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F7__SHIFT 0x14
+#define RCC_DEV0_EPF7_STRAP2__STRAP_DPA_EN_DEV0_F7__SHIFT 0x15
+#define RCC_DEV0_EPF7_STRAP2__STRAP_VC_EN_DEV0_F7__SHIFT 0x17
+#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F7__SHIFT 0x18
+//RCC_DEV0_EPF7_STRAP3
+#define RCC_DEV0_EPF7_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7__SHIFT 0x0
+#define RCC_DEV0_EPF7_STRAP3__STRAP_PWR_EN_DEV0_F7__SHIFT 0x1
+#define RCC_DEV0_EPF7_STRAP3__STRAP_SUBSYS_ID_DEV0_F7__SHIFT 0x2
+#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_EN_DEV0_F7__SHIFT 0x12
+#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F7__SHIFT 0x13
+#define RCC_DEV0_EPF7_STRAP3__STRAP_MSIX_EN_DEV0_F7__SHIFT 0x14
+#define RCC_DEV0_EPF7_STRAP3__STRAP_PMC_DSI_DEV0_F7__SHIFT 0x18
+#define RCC_DEV0_EPF7_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F7__SHIFT 0x19
+#define RCC_DEV0_EPF7_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7__SHIFT 0x1a
+#define RCC_DEV0_EPF7_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7__SHIFT 0x1b
+//RCC_DEV0_EPF7_STRAP4
+#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F7__SHIFT 0x14
+#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_EN_DEV0_F7__SHIFT 0x15
+#define RCC_DEV0_EPF7_STRAP4__STRAP_FLR_EN_DEV0_F7__SHIFT 0x16
+#define RCC_DEV0_EPF7_STRAP4__STRAP_PME_SUPPORT_DEV0_F7__SHIFT 0x17
+#define RCC_DEV0_EPF7_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F7__SHIFT 0x1c
+#define RCC_DEV0_EPF7_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F7__SHIFT 0x1f
+//RCC_DEV0_EPF7_STRAP5
+#define RCC_DEV0_EPF7_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F7__SHIFT 0x0
+//RCC_DEV0_EPF7_STRAP6
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_EN_DEV0_F7__SHIFT 0x0
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x1
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F7__SHIFT 0x4
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_EN_DEV0_F7__SHIFT 0x8
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x9
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_EN_DEV0_F7__SHIFT 0x10
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x11
+//RCC_DEV0_EPF7_STRAP13
+#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F7__SHIFT 0x0
+#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F7__SHIFT 0x8
+#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F7__SHIFT 0x10
+//RCC_DEV1_EPF0_STRAP0
+#define RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0__SHIFT 0x0
+#define RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0__SHIFT 0x10
+#define RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0__SHIFT 0x14
+#define RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0__SHIFT 0x1c
+#define RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0__SHIFT 0x1d
+#define RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0__SHIFT 0x1e
+#define RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0__SHIFT 0x1f
+//RCC_DEV1_EPF0_STRAP2
+#define RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0__SHIFT 0x7
+#define RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0__SHIFT 0x8
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0__SHIFT 0xe
+#define RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0__SHIFT 0xf
+#define RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0__SHIFT 0x10
+#define RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0__SHIFT 0x11
+#define RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0__SHIFT 0x14
+#define RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0__SHIFT 0x15
+#define RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0__SHIFT 0x17
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0__SHIFT 0x18
+//RCC_DEV1_EPF0_STRAP3
+#define RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0__SHIFT 0x0
+#define RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0__SHIFT 0x1
+#define RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0__SHIFT 0x2
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0__SHIFT 0x12
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0__SHIFT 0x13
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0__SHIFT 0x14
+#define RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0__SHIFT 0x18
+#define RCC_DEV1_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F0__SHIFT 0x19
+#define RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0__SHIFT 0x1a
+#define RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0__SHIFT 0x1b
+//RCC_DEV1_EPF0_STRAP4
+#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0__SHIFT 0x14
+#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0__SHIFT 0x15
+#define RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0__SHIFT 0x16
+#define RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0__SHIFT 0x17
+#define RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0__SHIFT 0x1c
+#define RCC_DEV1_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F0__SHIFT 0x1f
+//RCC_DEV1_EPF0_STRAP5
+#define RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0__SHIFT 0x0
+#define RCC_DEV1_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV1_F0__SHIFT 0x18
+//RCC_DEV1_EPF0_STRAP6
+#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0__SHIFT 0x0
+#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F0__SHIFT 0x1
+#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F0__SHIFT 0x4
+//RCC_DEV1_EPF0_STRAP13
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0__SHIFT 0x0
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0__SHIFT 0x8
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0__SHIFT 0x10
+//RCC_DEV1_EPF1_STRAP0
+#define RCC_DEV1_EPF1_STRAP0__STRAP_DEVICE_ID_DEV1_F1__SHIFT 0x0
+#define RCC_DEV1_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F1__SHIFT 0x10
+#define RCC_DEV1_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV1_F1__SHIFT 0x14
+#define RCC_DEV1_EPF1_STRAP0__STRAP_FUNC_EN_DEV1_F1__SHIFT 0x1c
+#define RCC_DEV1_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1__SHIFT 0x1d
+#define RCC_DEV1_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV1_F1__SHIFT 0x1e
+#define RCC_DEV1_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV1_F1__SHIFT 0x1f
+//RCC_DEV1_EPF1_STRAP2
+#define RCC_DEV1_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F1__SHIFT 0x7
+#define RCC_DEV1_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F1__SHIFT 0x8
+#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1__SHIFT 0xe
+#define RCC_DEV1_EPF1_STRAP2__STRAP_AER_EN_DEV1_F1__SHIFT 0x10
+#define RCC_DEV1_EPF1_STRAP2__STRAP_ACS_EN_DEV1_F1__SHIFT 0x11
+#define RCC_DEV1_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F1__SHIFT 0x14
+#define RCC_DEV1_EPF1_STRAP2__STRAP_DPA_EN_DEV1_F1__SHIFT 0x15
+#define RCC_DEV1_EPF1_STRAP2__STRAP_VC_EN_DEV1_F1__SHIFT 0x17
+#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F1__SHIFT 0x18
+//RCC_DEV1_EPF1_STRAP3
+#define RCC_DEV1_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1__SHIFT 0x0
+#define RCC_DEV1_EPF1_STRAP3__STRAP_PWR_EN_DEV1_F1__SHIFT 0x1
+#define RCC_DEV1_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV1_F1__SHIFT 0x2
+#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_EN_DEV1_F1__SHIFT 0x12
+#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F1__SHIFT 0x13
+#define RCC_DEV1_EPF1_STRAP3__STRAP_MSIX_EN_DEV1_F1__SHIFT 0x14
+#define RCC_DEV1_EPF1_STRAP3__STRAP_PMC_DSI_DEV1_F1__SHIFT 0x18
+#define RCC_DEV1_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F1__SHIFT 0x19
+#define RCC_DEV1_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1__SHIFT 0x1a
+#define RCC_DEV1_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1__SHIFT 0x1b
+//RCC_DEV1_EPF1_STRAP4
+#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F1__SHIFT 0x14
+#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV1_F1__SHIFT 0x15
+#define RCC_DEV1_EPF1_STRAP4__STRAP_FLR_EN_DEV1_F1__SHIFT 0x16
+#define RCC_DEV1_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV1_F1__SHIFT 0x17
+#define RCC_DEV1_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F1__SHIFT 0x1c
+#define RCC_DEV1_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F1__SHIFT 0x1f
+//RCC_DEV1_EPF1_STRAP5
+#define RCC_DEV1_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F1__SHIFT 0x0
+//RCC_DEV1_EPF1_STRAP6
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_EN_DEV1_F1__SHIFT 0x0
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x1
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F1__SHIFT 0x4
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_EN_DEV1_F1__SHIFT 0x8
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x9
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_EN_DEV1_F1__SHIFT 0x10
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x11
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_EN_DEV1_F1__SHIFT 0x18
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x19
+//RCC_DEV1_EPF1_STRAP13
+#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F1__SHIFT 0x0
+#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F1__SHIFT 0x8
+#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F1__SHIFT 0x10
+//RCC_DEV1_EPF2_STRAP0
+#define RCC_DEV1_EPF2_STRAP0__STRAP_DEVICE_ID_DEV1_F2__SHIFT 0x0
+#define RCC_DEV1_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F2__SHIFT 0x10
+#define RCC_DEV1_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV1_F2__SHIFT 0x14
+#define RCC_DEV1_EPF2_STRAP0__STRAP_FUNC_EN_DEV1_F2__SHIFT 0x1c
+#define RCC_DEV1_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F2__SHIFT 0x1d
+#define RCC_DEV1_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV1_F2__SHIFT 0x1e
+#define RCC_DEV1_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV1_F2__SHIFT 0x1f
+//RCC_DEV1_EPF2_STRAP2
+#define RCC_DEV1_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F2__SHIFT 0x7
+#define RCC_DEV1_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F2__SHIFT 0x8
+#define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F2__SHIFT 0xe
+#define RCC_DEV1_EPF2_STRAP2__STRAP_AER_EN_DEV1_F2__SHIFT 0x10
+#define RCC_DEV1_EPF2_STRAP2__STRAP_ACS_EN_DEV1_F2__SHIFT 0x11
+#define RCC_DEV1_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F2__SHIFT 0x14
+#define RCC_DEV1_EPF2_STRAP2__STRAP_DPA_EN_DEV1_F2__SHIFT 0x15
+#define RCC_DEV1_EPF2_STRAP2__STRAP_VC_EN_DEV1_F2__SHIFT 0x17
+#define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F2__SHIFT 0x18
+//RCC_DEV1_EPF2_STRAP3
+#define RCC_DEV1_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F2__SHIFT 0x0
+#define RCC_DEV1_EPF2_STRAP3__STRAP_PWR_EN_DEV1_F2__SHIFT 0x1
+#define RCC_DEV1_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV1_F2__SHIFT 0x2
+#define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_EN_DEV1_F2__SHIFT 0x12
+#define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F2__SHIFT 0x13
+#define RCC_DEV1_EPF2_STRAP3__STRAP_MSIX_EN_DEV1_F2__SHIFT 0x14
+#define RCC_DEV1_EPF2_STRAP3__STRAP_PMC_DSI_DEV1_F2__SHIFT 0x18
+#define RCC_DEV1_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F2__SHIFT 0x19
+#define RCC_DEV1_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F2__SHIFT 0x1a
+#define RCC_DEV1_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F2__SHIFT 0x1b
+//RCC_DEV1_EPF2_STRAP4
+#define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F2__SHIFT 0x14
+#define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV1_F2__SHIFT 0x15
+#define RCC_DEV1_EPF2_STRAP4__STRAP_FLR_EN_DEV1_F2__SHIFT 0x16
+#define RCC_DEV1_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV1_F2__SHIFT 0x17
+#define RCC_DEV1_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F2__SHIFT 0x1c
+#define RCC_DEV1_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F2__SHIFT 0x1f
+//RCC_DEV1_EPF2_STRAP5
+#define RCC_DEV1_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F2__SHIFT 0x0
+//RCC_DEV1_EPF2_STRAP6
+#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_EN_DEV1_F2__SHIFT 0x0
+#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x1
+#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F2__SHIFT 0x4
+#define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_EN_DEV1_F2__SHIFT 0x8
+#define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x9
+#define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_EN_DEV1_F2__SHIFT 0x10
+#define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x11
+#define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_EN_DEV1_F2__SHIFT 0x18
+#define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x19
+//RCC_DEV1_EPF2_STRAP13
+#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F2__SHIFT 0x0
+#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F2__SHIFT 0x8
+#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F2__SHIFT 0x10
+
+
+// addressBlock: bif_rst_bif_rst_regblk
+//HARD_RST_CTRL
+#define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0
+#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1
+#define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2
+#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3
+#define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4
+#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5
+#define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6
+#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7
+#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c
+#define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d
+#define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e
+#define HARD_RST_CTRL__CORE_RST_EN__SHIFT 0x1f
+//RSMU_SOFT_RST_CTRL
+#define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0
+#define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1
+#define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2
+#define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3
+#define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4
+#define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5
+#define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6
+#define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7
+#define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c
+#define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d
+#define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e
+#define RSMU_SOFT_RST_CTRL__CORE_RST_EN__SHIFT 0x1f
+//SELF_SOFT_RST
+#define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT 0x0
+#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT 0x1
+#define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT 0x2
+#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT 0x3
+#define SELF_SOFT_RST__EP0_CFG_RST__SHIFT 0x4
+#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT 0x5
+#define SELF_SOFT_RST__EP0_PRV_RST__SHIFT 0x6
+#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT 0x7
+#define SELF_SOFT_RST__SDP_PORT_RST__SHIFT 0x1b
+#define SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT 0x1c
+#define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT 0x1d
+#define SELF_SOFT_RST__RELOAD_STRAP__SHIFT 0x1e
+#define SELF_SOFT_RST__CORE_RST__SHIFT 0x1f
+//GFX_DRV_MODE1_RST_CTRL
+#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_RST__SHIFT 0x0
+#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT 0x1
+#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT 0x2
+#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_RST__SHIFT 0x3
+#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT 0x4
+#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_RST__SHIFT 0x5
+#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT 0x6
+#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_PRV_RST__SHIFT 0x7
+//BIF_RST_MISC_CTRL
+#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT 0x0
+#define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT 0x2
+#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT 0x4
+#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT 0x5
+#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT 0x6
+#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT 0x8
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT 0x9
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT 0xa
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT 0xd
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT 0xf
+#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x11
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT 0x17
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT 0x18
+//BIF_RST_MISC_CTRL2
+#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT 0x10
+#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT 0x11
+#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT 0x12
+#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT 0x1f
+//BIF_RST_MISC_CTRL3
+#define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT 0x0
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT 0x4
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT 0x6
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT 0x7
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT 0xa
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT 0xd
+//BIF_RST_GFXVF_FLR_IDLE
+#define BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE__SHIFT 0x0
+#define BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE__SHIFT 0x1
+#define BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE__SHIFT 0x2
+#define BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE__SHIFT 0x3
+#define BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE__SHIFT 0x4
+#define BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE__SHIFT 0x5
+#define BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE__SHIFT 0x6
+#define BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE__SHIFT 0x7
+#define BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE__SHIFT 0x8
+#define BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE__SHIFT 0x9
+#define BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE__SHIFT 0xa
+#define BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE__SHIFT 0xb
+#define BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE__SHIFT 0xc
+#define BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE__SHIFT 0xd
+#define BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE__SHIFT 0xe
+#define BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE__SHIFT 0xf
+#define BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE__SHIFT 0x1f
+//DEV0_PF0_FLR_RST_CTRL
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT 0x5
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT 0x6
+#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT 0x7
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT 0x8
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT 0x9
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT 0xa
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT 0xb
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT 0xc
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT 0xd
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT 0xe
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT 0xf
+#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+//DEV0_PF1_FLR_RST_CTRL
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+//DEV0_PF2_FLR_RST_CTRL
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+//DEV0_PF3_FLR_RST_CTRL
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+//DEV0_PF4_FLR_RST_CTRL
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+//DEV0_PF5_FLR_RST_CTRL
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+//DEV0_PF6_FLR_RST_CTRL
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+//DEV0_PF7_FLR_RST_CTRL
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+//BIF_INST_RESET_INTR_STS
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT 0x0
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x1
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT 0x2
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT 0x3
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT 0x4
+//BIF_PF_FLR_INTR_STS
+#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT 0x0
+#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT 0x1
+#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT 0x2
+#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT 0x3
+#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__SHIFT 0x4
+#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__SHIFT 0x5
+#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__SHIFT 0x6
+#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__SHIFT 0x7
+//BIF_D3HOTD0_INTR_STS
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT 0x0
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT 0x1
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT 0x2
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT 0x3
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__SHIFT 0x4
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__SHIFT 0x5
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__SHIFT 0x6
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__SHIFT 0x7
+//BIF_POWER_INTR_STS
+#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT 0x0
+#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT 0x10
+//BIF_PF_DSTATE_INTR_STS
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT 0x0
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT 0x1
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT 0x2
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT 0x3
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT 0x4
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT 0x5
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT 0x6
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT 0x7
+//BIF_PF0_VF_FLR_INTR_STS
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS__SHIFT 0x0
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS__SHIFT 0x1
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS__SHIFT 0x2
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS__SHIFT 0x3
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS__SHIFT 0x4
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS__SHIFT 0x5
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS__SHIFT 0x6
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS__SHIFT 0x7
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS__SHIFT 0x8
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS__SHIFT 0x9
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS__SHIFT 0xa
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS__SHIFT 0xb
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS__SHIFT 0xc
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS__SHIFT 0xd
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS__SHIFT 0xe
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS__SHIFT 0xf
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS__SHIFT 0x1f
+//BIF_INST_RESET_INTR_MASK
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT 0x0
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x1
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT 0x2
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT 0x3
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT 0x4
+//BIF_PF_FLR_INTR_MASK
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT 0x0
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT 0x1
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT 0x2
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT 0x3
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__SHIFT 0x4
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__SHIFT 0x5
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__SHIFT 0x6
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__SHIFT 0x7
+//BIF_D3HOTD0_INTR_MASK
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT 0x0
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT 0x1
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT 0x2
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT 0x3
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__SHIFT 0x4
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__SHIFT 0x5
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__SHIFT 0x6
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__SHIFT 0x7
+//BIF_POWER_INTR_MASK
+#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT 0x0
+#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT 0x10
+//BIF_PF_DSTATE_INTR_MASK
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT 0x0
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT 0x1
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT 0x2
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT 0x3
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT 0x4
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT 0x5
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT 0x6
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT 0x7
+//BIF_PF0_VF_FLR_INTR_MASK
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK__SHIFT 0x0
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__SHIFT 0x1
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK__SHIFT 0x2
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK__SHIFT 0x3
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK__SHIFT 0x4
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK__SHIFT 0x5
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK__SHIFT 0x6
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK__SHIFT 0x7
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK__SHIFT 0x8
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK__SHIFT 0x9
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK__SHIFT 0xa
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK__SHIFT 0xb
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK__SHIFT 0xc
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK__SHIFT 0xd
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK__SHIFT 0xe
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK__SHIFT 0xf
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK__SHIFT 0x1f
+//BIF_PF_FLR_RST
+#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0
+#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1
+#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2
+#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3
+#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x4
+#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x5
+#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x6
+#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT 0x7
+//BIF_PF0_VF_FLR_RST
+#define BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x0
+#define BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x1
+#define BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x2
+#define BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x3
+#define BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x4
+#define BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x5
+#define BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x6
+#define BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x7
+#define BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x8
+#define BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x9
+#define BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0xa
+#define BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0xb
+#define BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0xc
+#define BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0xd
+#define BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0xe
+#define BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0xf
+#define BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x1f
+//BIF_DEV0_PF0_DSTATE_VALUE
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT 0x10
+//BIF_DEV0_PF1_DSTATE_VALUE
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT 0x10
+//BIF_DEV0_PF2_DSTATE_VALUE
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT 0x10
+//BIF_DEV0_PF3_DSTATE_VALUE
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT 0x10
+//BIF_DEV0_PF4_DSTATE_VALUE
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__SHIFT 0x10
+//BIF_DEV0_PF5_DSTATE_VALUE
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__SHIFT 0x10
+//BIF_DEV0_PF6_DSTATE_VALUE
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__SHIFT 0x10
+//BIF_DEV0_PF7_DSTATE_VALUE
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__SHIFT 0x10
+//DEV0_PF0_D3HOTD0_RST_CTRL
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+//DEV0_PF1_D3HOTD0_RST_CTRL
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+//DEV0_PF2_D3HOTD0_RST_CTRL
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+//DEV0_PF3_D3HOTD0_RST_CTRL
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+//DEV0_PF4_D3HOTD0_RST_CTRL
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+//DEV0_PF5_D3HOTD0_RST_CTRL
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+//DEV0_PF6_D3HOTD0_RST_CTRL
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+//DEV0_PF7_D3HOTD0_RST_CTRL
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+//BIF_PORT0_DSTATE_VALUE
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT 0x10
+
+
+// addressBlock: bif_misc_bif_misc_regblk
+//MISC_SCRATCH
+#define MISC_SCRATCH__MISC_SCRATCH0__SHIFT 0x0
+//INTR_LINE_POLARITY
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT 0x0
+//INTR_LINE_ENABLE
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT 0x0
+//OUTSTANDING_VC_ALLOC
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT 0x0
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT 0x2
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT 0x4
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT 0x6
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT 0x8
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT 0xa
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT 0xc
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT 0xe
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT 0x10
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT 0x18
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT 0x1a
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT 0x1c
+//BIFC_MISC_CTRL0
+#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT 0x0
+#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT 0x1
+#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT 0x8
+#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__SHIFT 0x9
+#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT 0xa
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT 0x10
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT 0x11
+#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT 0x18
+#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__SHIFT 0x19
+#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT 0x1a
+#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT 0x1b
+#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT 0x1c
+#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT 0x1f
+//BIFC_MISC_CTRL1
+#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT 0x0
+#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT 0x1
+#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT 0x2
+#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT 0x3
+#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT 0x4
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT 0x5
+#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT 0x6
+#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT 0x7
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT 0x8
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT 0xa
+#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT 0xc
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT 0xd
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT 0xe
+#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT 0xf
+#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT 0x10
+#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT 0x11
+#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT 0x12
+#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT 0x13
+//BIFC_BME_ERR_LOG
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x0
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x1
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x2
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x3
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x4
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x5
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x6
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x7
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x10
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x11
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x12
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x13
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x14
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x15
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x16
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x17
+//BIFC_RCCBIH_BME_ERR_LOG
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x0
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x1
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x2
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x3
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x4
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x5
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x6
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x7
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x10
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x11
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x12
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x13
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x14
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x15
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x16
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x17
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT 0x1c
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT 0x1c
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT 0x1c
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT 0x1c
+//NBIF_VWIRE_CTRL
+#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT 0x4
+#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT 0x8
+#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT 0x14
+#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT 0x1a
+//NBIF_SMN_VWR_VCHG_DIS_CTRL
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT 0x3
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT 0x4
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT 0x5
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT 0x6
+//NBIF_SMN_VWR_VCHG_RST_CTRL0
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT 0x3
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT 0x4
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT 0x5
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT 0x6
+//NBIF_SMN_VWR_VCHG_TRIG
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT 0x3
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT 0x4
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT 0x5
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT 0x6
+//NBIF_SMN_VWR_WTRIG_CNTL
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT 0x0
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT 0x1
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT 0x2
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT 0x3
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT 0x4
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT 0x5
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT 0x6
+//NBIF_SMN_VWR_VCHG_DIS_CTRL_1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT 0x3
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT 0x4
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT 0x5
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT 0x6
+//NBIF_MGCG_CTRL
+#define NBIF_MGCG_CTRL__NBIF_MGCG_EN__SHIFT 0x0
+#define NBIF_MGCG_CTRL__NBIF_MGCG_MODE__SHIFT 0x1
+#define NBIF_MGCG_CTRL__NBIF_MGCG_HYSTERESIS__SHIFT 0x2
+//NBIF_DS_CTRL_LCLK
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT 0x0
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT 0x10
+//SMN_MST_CNTL0
+#define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT 0x0
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT 0x8
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT 0x9
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT 0xa
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT 0xb
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT 0x10
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT 0x14
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT 0x18
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT 0x1c
+//SMN_MST_EP_CNTL1
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT 0x7
+//SMN_MST_EP_CNTL2
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT 0x7
+//NBIF_SDP_VWR_VCHG_DIS_CTRL
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT 0x18
+//NBIF_SDP_VWR_VCHG_RST_CTRL0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT 0x18
+//NBIF_SDP_VWR_VCHG_RST_CTRL1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT 0x18
+//NBIF_SDP_VWR_VCHG_TRIG
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT 0x18
+//BME_DUMMY_CNTL_0
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT 0x0
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT 0x2
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT 0x4
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT 0x6
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT 0x8
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT 0xa
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT 0xc
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT 0xe
+//BIFC_THT_CNTL
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT 0x0
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT 0x4
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT 0x8
+//BIFC_HSTARB_CNTL
+#define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT 0x0
+//BIFC_GSI_CNTL
+#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT 0x0
+#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT 0x2
+#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT 0x5
+#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT 0x6
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT 0x7
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT 0x8
+#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT 0x9
+#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT 0xa
+#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT 0xc
+//BIFC_PCIEFUNC_CNTL
+#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT 0x0
+#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT 0x10
+//BIFC_SDP_CNTL_0
+#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT 0x0
+#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT 0x6
+#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT 0xc
+#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT 0x12
+//BIFC_PERF_CNTL_0
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT 0x0
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT 0x1
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT 0x8
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT 0x9
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT 0x10
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT 0x18
+//BIFC_PERF_CNTL_1
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT 0x0
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT 0x1
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT 0x8
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT 0x9
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT 0x10
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT 0x18
+//BIFC_PERF_CNT_MMIO_RD
+#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__SHIFT 0x0
+//BIFC_PERF_CNT_MMIO_WR
+#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__SHIFT 0x0
+//BIFC_PERF_CNT_DMA_RD
+#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__SHIFT 0x0
+//BIFC_PERF_CNT_DMA_WR
+#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__SHIFT 0x0
+//NBIF_REGIF_ERRSET_CTRL
+#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0
+//SMN_MST_EP_CNTL3
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT 0x7
+//SMN_MST_EP_CNTL4
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT 0x7
+//BIF_SELFRING_BUFFER_VID
+#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT 0x0
+#define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID__SHIFT 0x8
+//BIF_SELFRING_VECTOR_CNTL
+#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT 0x0
+
+
+// addressBlock: bif_ras_bif_ras_regblk
+//BIF_RAS_LEAF0_CTRL
+#define BIF_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x0
+#define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x15
+//BIF_RAS_LEAF1_CTRL
+#define BIF_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x0
+#define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x15
+//BIF_RAS_LEAF2_CTRL
+#define BIF_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x0
+#define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x15
+//BIF_RAS_MISC_CTRL
+#define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN__SHIFT 0x0
+//BIF_IOHUB_RAS_IH_CNTL
+#define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN__SHIFT 0x0
+//BIF_RAS_VWR_FROM_IOHUB
+#define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG__SHIFT 0x0
+
+
+// addressBlock: rcc_pfc_amdgfx_RCCPFCDEC
+//RCC_PFC_LTR_CNTL
+#define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+//RCC_PFC_PME_RESTORE
+#define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+//RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+//RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+//RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+//RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+//RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+//RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+//RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+
+
+// addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC
+//RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL
+#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+//RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE
+#define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+//RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL
+#define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+
+
+// addressBlock: pciemsix_amdgfx_MSIXTDEC
+//PCIEMSIX_VECT0_ADDR_LO
+#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT0_ADDR_HI
+#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT0_MSG_DATA
+#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT0_CONTROL
+#define PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT1_ADDR_LO
+#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT1_ADDR_HI
+#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT1_MSG_DATA
+#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT1_CONTROL
+#define PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT2_ADDR_LO
+#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT2_ADDR_HI
+#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT2_MSG_DATA
+#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT2_CONTROL
+#define PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT3_ADDR_LO
+#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT3_ADDR_HI
+#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT3_MSG_DATA
+#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT3_CONTROL
+#define PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT4_ADDR_LO
+#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT4_ADDR_HI
+#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT4_MSG_DATA
+#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT4_CONTROL
+#define PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT5_ADDR_LO
+#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT5_ADDR_HI
+#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT5_MSG_DATA
+#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT5_CONTROL
+#define PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT6_ADDR_LO
+#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT6_ADDR_HI
+#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT6_MSG_DATA
+#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT6_CONTROL
+#define PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT7_ADDR_LO
+#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT7_ADDR_HI
+#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT7_MSG_DATA
+#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT7_CONTROL
+#define PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT8_ADDR_LO
+#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT8_ADDR_HI
+#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT8_MSG_DATA
+#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT8_CONTROL
+#define PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT9_ADDR_LO
+#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT9_ADDR_HI
+#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT9_MSG_DATA
+#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT9_CONTROL
+#define PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT10_ADDR_LO
+#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT10_ADDR_HI
+#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT10_MSG_DATA
+#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT10_CONTROL
+#define PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT11_ADDR_LO
+#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT11_ADDR_HI
+#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT11_MSG_DATA
+#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT11_CONTROL
+#define PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT12_ADDR_LO
+#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT12_ADDR_HI
+#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT12_MSG_DATA
+#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT12_CONTROL
+#define PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT13_ADDR_LO
+#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT13_ADDR_HI
+#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT13_MSG_DATA
+#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT13_CONTROL
+#define PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT14_ADDR_LO
+#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT14_ADDR_HI
+#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT14_MSG_DATA
+#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT14_CONTROL
+#define PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT15_ADDR_LO
+#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT15_ADDR_HI
+#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT15_MSG_DATA
+#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT15_CONTROL
+#define PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT16_ADDR_LO
+#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT16_ADDR_HI
+#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT16_MSG_DATA
+#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT16_CONTROL
+#define PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT17_ADDR_LO
+#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT17_ADDR_HI
+#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT17_MSG_DATA
+#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT17_CONTROL
+#define PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT18_ADDR_LO
+#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT18_ADDR_HI
+#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT18_MSG_DATA
+#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT18_CONTROL
+#define PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT19_ADDR_LO
+#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT19_ADDR_HI
+#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT19_MSG_DATA
+#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT19_CONTROL
+#define PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT20_ADDR_LO
+#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT20_ADDR_HI
+#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT20_MSG_DATA
+#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT20_CONTROL
+#define PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT21_ADDR_LO
+#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT21_ADDR_HI
+#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT21_MSG_DATA
+#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT21_CONTROL
+#define PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT22_ADDR_LO
+#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT22_ADDR_HI
+#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT22_MSG_DATA
+#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT22_CONTROL
+#define PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT23_ADDR_LO
+#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT23_ADDR_HI
+#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT23_MSG_DATA
+#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT23_CONTROL
+#define PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT24_ADDR_LO
+#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT24_ADDR_HI
+#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT24_MSG_DATA
+#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT24_CONTROL
+#define PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT25_ADDR_LO
+#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT25_ADDR_HI
+#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT25_MSG_DATA
+#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT25_CONTROL
+#define PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT26_ADDR_LO
+#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT26_ADDR_HI
+#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT26_MSG_DATA
+#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT26_CONTROL
+#define PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT27_ADDR_LO
+#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT27_ADDR_HI
+#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT27_MSG_DATA
+#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT27_CONTROL
+#define PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT28_ADDR_LO
+#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT28_ADDR_HI
+#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT28_MSG_DATA
+#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT28_CONTROL
+#define PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT29_ADDR_LO
+#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT29_ADDR_HI
+#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT29_MSG_DATA
+#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT29_CONTROL
+#define PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT30_ADDR_LO
+#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT30_ADDR_HI
+#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT30_MSG_DATA
+#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT30_CONTROL
+#define PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0
+//PCIEMSIX_VECT31_ADDR_LO
+#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+//PCIEMSIX_VECT31_ADDR_HI
+#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+//PCIEMSIX_VECT31_MSG_DATA
+#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0
+//PCIEMSIX_VECT31_CONTROL
+#define PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0
+
+
+// addressBlock: pciemsix_amdgfx_MSIXPDEC
+//PCIEMSIX_PBA
+#define PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0
+
+
+// addressBlock: syshub_mmreg_ind_syshubind
+//SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f
+//SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0
+//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0xf
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x10
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x11
+//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0xf
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x10
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x11
+//SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+//SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL
+#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+//SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL
+#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL
+#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//SYSHUBMMREGIND_SYSHUB_CG_CNTL
+#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT 0x0
+#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT 0x8
+#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT 0x10
+//SYSHUBMMREGIND_SYSHUB_TRANS_IDLE
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT 0x0
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT 0x1
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT 0x2
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT 0x3
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT 0x4
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT 0x5
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT 0x6
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT 0x7
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT 0x8
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT 0x9
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT 0xa
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT 0xb
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT 0xc
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT 0xd
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT 0xe
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT 0xf
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT 0x10
+//SYSHUBMMREGIND_SYSHUB_HP_TIMER
+#define SYSHUBMMREGIND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT 0x0
+//SYSHUBMMREGIND_SYSHUB_SCRATCH
+#define SYSHUBMMREGIND_SYSHUB_SCRATCH__SCRATCH__SHIFT 0x0
+//SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f
+//SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0
+//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT 0xf
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT 0x10
+//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT 0xf
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT 0x10
+//SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+//SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+//SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+//MASK
+
+
+// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp
+//VENDOR_ID
+#define VENDOR_ID__VENDOR_ID__MASK 0xFFFFL
+//DEVICE_ID
+#define DEVICE_ID__DEVICE_ID__MASK 0xFFFFL
+//COMMAND
+#define COMMAND__IO_ACCESS_EN__MASK 0x0001L
+#define COMMAND__MEM_ACCESS_EN__MASK 0x0002L
+#define COMMAND__BUS_MASTER_EN__MASK 0x0004L
+#define COMMAND__SPECIAL_CYCLE_EN__MASK 0x0008L
+#define COMMAND__MEM_WRITE_INVALIDATE_EN__MASK 0x0010L
+#define COMMAND__PAL_SNOOP_EN__MASK 0x0020L
+#define COMMAND__PARITY_ERROR_RESPONSE__MASK 0x0040L
+#define COMMAND__AD_STEPPING__MASK 0x0080L
+#define COMMAND__SERR_EN__MASK 0x0100L
+#define COMMAND__FAST_B2B_EN__MASK 0x0200L
+#define COMMAND__INT_DIS__MASK 0x0400L
+//STATUS
+#define STATUS__INT_STATUS__MASK 0x0008L
+#define STATUS__CAP_LIST__MASK 0x0010L
+#define STATUS__PCI_66_EN__MASK 0x0020L
+#define STATUS__FAST_BACK_CAPABLE__MASK 0x0080L
+#define STATUS__MASTER_DATA_PARITY_ERROR__MASK 0x0100L
+#define STATUS__DEVSEL_TIMING__MASK 0x0600L
+#define STATUS__SIGNAL_TARGET_ABORT__MASK 0x0800L
+#define STATUS__RECEIVED_TARGET_ABORT__MASK 0x1000L
+#define STATUS__RECEIVED_MASTER_ABORT__MASK 0x2000L
+#define STATUS__SIGNALED_SYSTEM_ERROR__MASK 0x4000L
+#define STATUS__PARITY_ERROR_DETECTED__MASK 0x8000L
+//REVISION_ID
+#define REVISION_ID__MINOR_REV_ID__MASK 0x0FL
+#define REVISION_ID__MAJOR_REV_ID__MASK 0xF0L
+//PROG_INTERFACE
+#define PROG_INTERFACE__PROG_INTERFACE__MASK 0xFFL
+//SUB_CLASS
+#define SUB_CLASS__SUB_CLASS__MASK 0xFFL
+//BASE_CLASS
+#define BASE_CLASS__BASE_CLASS__MASK 0xFFL
+//CACHE_LINE
+#define CACHE_LINE__CACHE_LINE_SIZE__MASK 0xFFL
+//LATENCY
+#define LATENCY__LATENCY_TIMER__MASK 0xFFL
+//HEADER
+#define HEADER__HEADER_TYPE__MASK 0x7FL
+#define HEADER__DEVICE_TYPE__MASK 0x80L
+//BIST
+#define BIST__BIST_COMP__MASK 0x0FL
+#define BIST__BIST_STRT__MASK 0x40L
+#define BIST__BIST_CAP__MASK 0x80L
+//BASE_ADDR_1
+#define BASE_ADDR_1__BASE_ADDR__MASK 0xFFFFFFFFL
+//BASE_ADDR_2
+#define BASE_ADDR_2__BASE_ADDR__MASK 0xFFFFFFFFL
+//BASE_ADDR_3
+#define BASE_ADDR_3__BASE_ADDR__MASK 0xFFFFFFFFL
+//BASE_ADDR_4
+#define BASE_ADDR_4__BASE_ADDR__MASK 0xFFFFFFFFL
+//BASE_ADDR_5
+#define BASE_ADDR_5__BASE_ADDR__MASK 0xFFFFFFFFL
+//BASE_ADDR_6
+#define BASE_ADDR_6__BASE_ADDR__MASK 0xFFFFFFFFL
+//ADAPTER_ID
+#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__MASK 0x0000FFFFL
+#define ADAPTER_ID__SUBSYSTEM_ID__MASK 0xFFFF0000L
+//ROM_BASE_ADDR
+#define ROM_BASE_ADDR__BASE_ADDR__MASK 0xFFFFFFFFL
+//CAP_PTR
+#define CAP_PTR__CAP_PTR__MASK 0x000000FFL
+//INTERRUPT_LINE
+#define INTERRUPT_LINE__INTERRUPT_LINE__MASK 0xFFL
+//INTERRUPT_PIN
+#define INTERRUPT_PIN__INTERRUPT_PIN__MASK 0xFFL
+//MIN_GRANT
+#define MIN_GRANT__MIN_GNT__MASK 0xFFL
+//MAX_LATENCY
+#define MAX_LATENCY__MAX_LAT__MASK 0xFFL
+//VENDOR_CAP_LIST
+#define VENDOR_CAP_LIST__CAP_ID__MASK 0x000000FFL
+#define VENDOR_CAP_LIST__NEXT_PTR__MASK 0x0000FF00L
+#define VENDOR_CAP_LIST__LENGTH__MASK 0x00FF0000L
+//ADAPTER_ID_W
+#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__MASK 0x0000FFFFL
+#define ADAPTER_ID_W__SUBSYSTEM_ID__MASK 0xFFFF0000L
+//PMI_CAP_LIST
+#define PMI_CAP_LIST__CAP_ID__MASK 0x00FFL
+#define PMI_CAP_LIST__NEXT_PTR__MASK 0xFF00L
+//PMI_CAP
+#define PMI_CAP__VERSION__MASK 0x0007L
+#define PMI_CAP__PME_CLOCK__MASK 0x0008L
+#define PMI_CAP__DEV_SPECIFIC_INIT__MASK 0x0020L
+#define PMI_CAP__AUX_CURRENT__MASK 0x01C0L
+#define PMI_CAP__D1_SUPPORT__MASK 0x0200L
+#define PMI_CAP__D2_SUPPORT__MASK 0x0400L
+#define PMI_CAP__PME_SUPPORT__MASK 0xF800L
+//PMI_STATUS_CNTL
+#define PMI_STATUS_CNTL__POWER_STATE__MASK 0x00000003L
+#define PMI_STATUS_CNTL__NO_SOFT_RESET__MASK 0x00000008L
+#define PMI_STATUS_CNTL__PME_EN__MASK 0x00000100L
+#define PMI_STATUS_CNTL__DATA_SELECT__MASK 0x00001E00L
+#define PMI_STATUS_CNTL__DATA_SCALE__MASK 0x00006000L
+#define PMI_STATUS_CNTL__PME_STATUS__MASK 0x00008000L
+#define PMI_STATUS_CNTL__B2_B3_SUPPORT__MASK 0x00400000L
+#define PMI_STATUS_CNTL__BUS_PWR_EN__MASK 0x00800000L
+#define PMI_STATUS_CNTL__PMI_DATA__MASK 0xFF000000L
+//PCIE_CAP_LIST
+#define PCIE_CAP_LIST__CAP_ID__MASK 0x00FFL
+#define PCIE_CAP_LIST__NEXT_PTR__MASK 0xFF00L
+//PCIE_CAP
+#define PCIE_CAP__VERSION__MASK 0x000FL
+#define PCIE_CAP__DEVICE_TYPE__MASK 0x00F0L
+#define PCIE_CAP__SLOT_IMPLEMENTED__MASK 0x0100L
+#define PCIE_CAP__INT_MESSAGE_NUM__MASK 0x3E00L
+//DEVICE_CAP
+#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__MASK 0x00000007L
+#define DEVICE_CAP__PHANTOM_FUNC__MASK 0x00000018L
+#define DEVICE_CAP__EXTENDED_TAG__MASK 0x00000020L
+#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__MASK 0x000001C0L
+#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__MASK 0x00000E00L
+#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__MASK 0x00008000L
+#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__MASK 0x03FC0000L
+#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__MASK 0x0C000000L
+#define DEVICE_CAP__FLR_CAPABLE__MASK 0x10000000L
+//DEVICE_CNTL
+#define DEVICE_CNTL__CORR_ERR_EN__MASK 0x0001L
+#define DEVICE_CNTL__NON_FATAL_ERR_EN__MASK 0x0002L
+#define DEVICE_CNTL__FATAL_ERR_EN__MASK 0x0004L
+#define DEVICE_CNTL__USR_REPORT_EN__MASK 0x0008L
+#define DEVICE_CNTL__RELAXED_ORD_EN__MASK 0x0010L
+#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__MASK 0x00E0L
+#define DEVICE_CNTL__EXTENDED_TAG_EN__MASK 0x0100L
+#define DEVICE_CNTL__PHANTOM_FUNC_EN__MASK 0x0200L
+#define DEVICE_CNTL__AUX_POWER_PM_EN__MASK 0x0400L
+#define DEVICE_CNTL__NO_SNOOP_EN__MASK 0x0800L
+#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__MASK 0x7000L
+#define DEVICE_CNTL__INITIATE_FLR__MASK 0x8000L
+//DEVICE_STATUS
+#define DEVICE_STATUS__CORR_ERR__MASK 0x0001L
+#define DEVICE_STATUS__NON_FATAL_ERR__MASK 0x0002L
+#define DEVICE_STATUS__FATAL_ERR__MASK 0x0004L
+#define DEVICE_STATUS__USR_DETECTED__MASK 0x0008L
+#define DEVICE_STATUS__AUX_PWR__MASK 0x0010L
+#define DEVICE_STATUS__TRANSACTIONS_PEND__MASK 0x0020L
+//LINK_CAP
+#define LINK_CAP__LINK_SPEED__MASK 0x0000000FL
+#define LINK_CAP__LINK_WIDTH__MASK 0x000003F0L
+#define LINK_CAP__PM_SUPPORT__MASK 0x00000C00L
+#define LINK_CAP__L0S_EXIT_LATENCY__MASK 0x00007000L
+#define LINK_CAP__L1_EXIT_LATENCY__MASK 0x00038000L
+#define LINK_CAP__CLOCK_POWER_MANAGEMENT__MASK 0x00040000L
+#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__MASK 0x00080000L
+#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__MASK 0x00100000L
+#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__MASK 0x00200000L
+#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__MASK 0x00400000L
+#define LINK_CAP__PORT_NUMBER__MASK 0xFF000000L
+//LINK_CNTL
+#define LINK_CNTL__PM_CONTROL__MASK 0x0003L
+#define LINK_CNTL__READ_CPL_BOUNDARY__MASK 0x0008L
+#define LINK_CNTL__LINK_DIS__MASK 0x0010L
+#define LINK_CNTL__RETRAIN_LINK__MASK 0x0020L
+#define LINK_CNTL__COMMON_CLOCK_CFG__MASK 0x0040L
+#define LINK_CNTL__EXTENDED_SYNC__MASK 0x0080L
+#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__MASK 0x0100L
+#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__MASK 0x0200L
+#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__MASK 0x0400L
+#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__MASK 0x0800L
+//LINK_STATUS
+#define LINK_STATUS__CURRENT_LINK_SPEED__MASK 0x000FL
+#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__MASK 0x03F0L
+#define LINK_STATUS__LINK_TRAINING__MASK 0x0800L
+#define LINK_STATUS__SLOT_CLOCK_CFG__MASK 0x1000L
+#define LINK_STATUS__DL_ACTIVE__MASK 0x2000L
+#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__MASK 0x4000L
+#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__MASK 0x8000L
+//DEVICE_CAP2
+#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__MASK 0x0000000FL
+#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__MASK 0x00000010L
+#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__MASK 0x00000020L
+#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__MASK 0x00000040L
+#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__MASK 0x00000080L
+#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__MASK 0x00000100L
+#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__MASK 0x00000200L
+#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__MASK 0x00000400L
+#define DEVICE_CAP2__LTR_SUPPORTED__MASK 0x00000800L
+#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__MASK 0x00003000L
+#define DEVICE_CAP2__OBFF_SUPPORTED__MASK 0x000C0000L
+#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__MASK 0x00100000L
+#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__MASK 0x00200000L
+#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__MASK 0x00C00000L
+//DEVICE_CNTL2
+#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__MASK 0x000FL
+#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__MASK 0x0010L
+#define DEVICE_CNTL2__ARI_FORWARDING_EN__MASK 0x0020L
+#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__MASK 0x0040L
+#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__MASK 0x0080L
+#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__MASK 0x0100L
+#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__MASK 0x0200L
+#define DEVICE_CNTL2__LTR_EN__MASK 0x0400L
+#define DEVICE_CNTL2__OBFF_EN__MASK 0x6000L
+#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__MASK 0x8000L
+//DEVICE_STATUS2
+#define DEVICE_STATUS2__RESERVED__MASK 0xFFFFL
+//LINK_CAP2
+#define LINK_CAP2__SUPPORTED_LINK_SPEED__MASK 0x000000FEL
+#define LINK_CAP2__CROSSLINK_SUPPORTED__MASK 0x00000100L
+#define LINK_CAP2__RESERVED__MASK 0xFFFFFE00L
+//LINK_CNTL2
+#define LINK_CNTL2__TARGET_LINK_SPEED__MASK 0x000FL
+#define LINK_CNTL2__ENTER_COMPLIANCE__MASK 0x0010L
+#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__MASK 0x0020L
+#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__MASK 0x0040L
+#define LINK_CNTL2__XMIT_MARGIN__MASK 0x0380L
+#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__MASK 0x0400L
+#define LINK_CNTL2__COMPLIANCE_SOS__MASK 0x0800L
+#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__MASK 0xF000L
+//LINK_STATUS2
+#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__MASK 0x0001L
+#define LINK_STATUS2__EQUALIZATION_COMPLETE__MASK 0x0002L
+#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__MASK 0x0004L
+#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__MASK 0x0008L
+#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__MASK 0x0010L
+#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__MASK 0x0020L
+//SLOT_CAP2
+#define SLOT_CAP2__RESERVED__MASK 0xFFFFFFFFL
+//SLOT_CNTL2
+#define SLOT_CNTL2__RESERVED__MASK 0xFFFFL
+//SLOT_STATUS2
+#define SLOT_STATUS2__RESERVED__MASK 0xFFFFL
+//MSI_CAP_LIST
+#define MSI_CAP_LIST__CAP_ID__MASK 0x00FFL
+#define MSI_CAP_LIST__NEXT_PTR__MASK 0xFF00L
+//MSI_MSG_CNTL
+#define MSI_MSG_CNTL__MSI_EN__MASK 0x0001L
+#define MSI_MSG_CNTL__MSI_MULTI_CAP__MASK 0x000EL
+#define MSI_MSG_CNTL__MSI_MULTI_EN__MASK 0x0070L
+#define MSI_MSG_CNTL__MSI_64BIT__MASK 0x0080L
+#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__MASK 0x0100L
+//MSI_MSG_ADDR_LO
+#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//MSI_MSG_ADDR_HI
+#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//MSI_MSG_DATA
+#define MSI_MSG_DATA__MSI_DATA__MASK 0x0000FFFFL
+//MSI_MSG_DATA_64
+#define MSI_MSG_DATA_64__MSI_DATA_64__MASK 0x0000FFFFL
+//MSI_MASK
+#define MSI_MASK__MSI_MASK__MASK 0xFFFFFFFFL
+//MSI_PENDING
+#define MSI_PENDING__MSI_PENDING__MASK 0xFFFFFFFFL
+//MSI_MASK_64
+#define MSI_MASK_64__MSI_MASK_64__MASK 0xFFFFFFFFL
+//MSI_PENDING_64
+#define MSI_PENDING_64__MSI_PENDING_64__MASK 0xFFFFFFFFL
+//MSIX_CAP_LIST
+#define MSIX_CAP_LIST__CAP_ID__MASK 0x00FFL
+#define MSIX_CAP_LIST__NEXT_PTR__MASK 0xFF00L
+//MSIX_MSG_CNTL
+#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE__MASK 0x07FFL
+#define MSIX_MSG_CNTL__MSIX_FUNC_MASK__MASK 0x4000L
+#define MSIX_MSG_CNTL__MSIX_EN__MASK 0x8000L
+//MSIX_TABLE
+#define MSIX_TABLE__MSIX_TABLE_BIR__MASK 0x00000007L
+#define MSIX_TABLE__MSIX_TABLE_OFFSET__MASK 0xFFFFFFF8L
+//MSIX_PBA
+#define MSIX_PBA__MSIX_PBA_BIR__MASK 0x00000007L
+#define MSIX_PBA__MSIX_PBA_OFFSET__MASK 0xFFFFFFF8L
+//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
+//PCIE_VENDOR_SPECIFIC_HDR
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__MASK 0x000F0000L
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__MASK 0xFFF00000L
+//PCIE_VENDOR_SPECIFIC1
+#define PCIE_VENDOR_SPECIFIC1__SCRATCH__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC2
+#define PCIE_VENDOR_SPECIFIC2__SCRATCH__MASK 0xFFFFFFFFL
+//PCIE_VC_ENH_CAP_LIST
+#define PCIE_VC_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
+#define PCIE_VC_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
+#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
+//PCIE_PORT_VC_CAP_REG1
+#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__MASK 0x00000007L
+#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__MASK 0x00000070L
+#define PCIE_PORT_VC_CAP_REG1__REF_CLK__MASK 0x00000300L
+#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__MASK 0x00000C00L
+//PCIE_PORT_VC_CAP_REG2
+#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__MASK 0x000000FFL
+#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__MASK 0xFF000000L
+//PCIE_PORT_VC_CNTL
+#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__MASK 0x0001L
+#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__MASK 0x000EL
+//PCIE_PORT_VC_STATUS
+#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__MASK 0x0001L
+//PCIE_VC0_RESOURCE_CAP
+#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__MASK 0x000000FFL
+#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__MASK 0x00008000L
+#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__MASK 0x003F0000L
+#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__MASK 0xFF000000L
+//PCIE_VC0_RESOURCE_CNTL
+#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__MASK 0x00000001L
+#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__MASK 0x000000FEL
+#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__MASK 0x00010000L
+#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__MASK 0x000E0000L
+#define PCIE_VC0_RESOURCE_CNTL__VC_ID__MASK 0x07000000L
+#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__MASK 0x80000000L
+//PCIE_VC0_RESOURCE_STATUS
+#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__MASK 0x0001L
+#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__MASK 0x0002L
+//PCIE_VC1_RESOURCE_CAP
+#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__MASK 0x000000FFL
+#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__MASK 0x00008000L
+#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__MASK 0x003F0000L
+#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__MASK 0xFF000000L
+//PCIE_VC1_RESOURCE_CNTL
+#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__MASK 0x00000001L
+#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__MASK 0x000000FEL
+#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__MASK 0x00010000L
+#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__MASK 0x000E0000L
+#define PCIE_VC1_RESOURCE_CNTL__VC_ID__MASK 0x07000000L
+#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__MASK 0x80000000L
+//PCIE_VC1_RESOURCE_STATUS
+#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__MASK 0x0001L
+#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__MASK 0x0002L
+//PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
+//PCIE_DEV_SERIAL_NUM_DW1
+#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__MASK 0xFFFFFFFFL
+//PCIE_DEV_SERIAL_NUM_DW2
+#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__MASK 0xFFFFFFFFL
+//PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
+//PCIE_UNCORR_ERR_STATUS
+#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__MASK 0x00000010L
+#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__MASK 0x00000020L
+#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__MASK 0x00001000L
+#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__MASK 0x00002000L
+#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__MASK 0x00004000L
+#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__MASK 0x00008000L
+#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__MASK 0x00010000L
+#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__MASK 0x00020000L
+#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__MASK 0x00040000L
+#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__MASK 0x00080000L
+#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__MASK 0x00100000L
+#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__MASK 0x00200000L
+#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__MASK 0x00400000L
+#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__MASK 0x00800000L
+#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__MASK 0x01000000L
+#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__MASK 0x02000000L
+//PCIE_UNCORR_ERR_MASK
+#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__MASK 0x00000010L
+#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__MASK 0x00000020L
+#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__MASK 0x00001000L
+#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__MASK 0x00002000L
+#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__MASK 0x00004000L
+#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__MASK 0x00008000L
+#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__MASK 0x00010000L
+#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__MASK 0x00020000L
+#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__MASK 0x00040000L
+#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__MASK 0x00080000L
+#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__MASK 0x00100000L
+#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__MASK 0x00200000L
+#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__MASK 0x00400000L
+#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__MASK 0x00800000L
+#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__MASK 0x01000000L
+#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__MASK 0x02000000L
+//PCIE_UNCORR_ERR_SEVERITY
+#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__MASK 0x00000010L
+#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__MASK 0x00000020L
+#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__MASK 0x00001000L
+#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__MASK 0x00002000L
+#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__MASK 0x00004000L
+#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__MASK 0x00008000L
+#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__MASK 0x00010000L
+#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__MASK 0x00020000L
+#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__MASK 0x00040000L
+#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__MASK 0x00080000L
+#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__MASK 0x00100000L
+#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__MASK 0x00200000L
+#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__MASK 0x00400000L
+#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__MASK 0x00800000L
+#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__MASK 0x01000000L
+#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__MASK 0x02000000L
+//PCIE_CORR_ERR_STATUS
+#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__MASK 0x00000001L
+#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__MASK 0x00000040L
+#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__MASK 0x00000080L
+#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__MASK 0x00000100L
+#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__MASK 0x00001000L
+#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__MASK 0x00002000L
+#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__MASK 0x00004000L
+#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__MASK 0x00008000L
+//PCIE_CORR_ERR_MASK
+#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__MASK 0x00000001L
+#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__MASK 0x00000040L
+#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__MASK 0x00000080L
+#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__MASK 0x00000100L
+#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__MASK 0x00001000L
+#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__MASK 0x00002000L
+#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__MASK 0x00004000L
+#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__MASK 0x00008000L
+//PCIE_ADV_ERR_CAP_CNTL
+#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__MASK 0x0000001FL
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__MASK 0x00000020L
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__MASK 0x00000040L
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__MASK 0x00000080L
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__MASK 0x00000100L
+#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__MASK 0x00000200L
+#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__MASK 0x00000400L
+#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__MASK 0x00000800L
+//PCIE_HDR_LOG0
+#define PCIE_HDR_LOG0__TLP_HDR__MASK 0xFFFFFFFFL
+//PCIE_HDR_LOG1
+#define PCIE_HDR_LOG1__TLP_HDR__MASK 0xFFFFFFFFL
+//PCIE_HDR_LOG2
+#define PCIE_HDR_LOG2__TLP_HDR__MASK 0xFFFFFFFFL
+//PCIE_HDR_LOG3
+#define PCIE_HDR_LOG3__TLP_HDR__MASK 0xFFFFFFFFL
+//PCIE_ROOT_ERR_CMD
+#define PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__MASK 0x00000001L
+#define PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__MASK 0x00000002L
+#define PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__MASK 0x00000004L
+//PCIE_ROOT_ERR_STATUS
+#define PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__MASK 0x00000001L
+#define PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__MASK 0x00000002L
+#define PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__MASK 0x00000004L
+#define PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__MASK 0x00000008L
+#define PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__MASK 0x00000010L
+#define PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__MASK 0x00000020L
+#define PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__MASK 0x00000040L
+#define PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__MASK 0xF8000000L
+//PCIE_ERR_SRC_ID
+#define PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__MASK 0x0000FFFFL
+#define PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__MASK 0xFFFF0000L
+//PCIE_TLP_PREFIX_LOG0
+#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__MASK 0xFFFFFFFFL
+//PCIE_TLP_PREFIX_LOG1
+#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__MASK 0xFFFFFFFFL
+//PCIE_TLP_PREFIX_LOG2
+#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__MASK 0xFFFFFFFFL
+//PCIE_TLP_PREFIX_LOG3
+#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__MASK 0xFFFFFFFFL
+//PCIE_BAR_ENH_CAP_LIST
+#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
+#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
+#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
+//PCIE_BAR1_CAP
+#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L
+//PCIE_BAR1_CNTL
+#define PCIE_BAR1_CNTL__BAR_INDEX__MASK 0x0007L
+#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L
+#define PCIE_BAR1_CNTL__BAR_SIZE__MASK 0x1F00L
+//PCIE_BAR2_CAP
+#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L
+//PCIE_BAR2_CNTL
+#define PCIE_BAR2_CNTL__BAR_INDEX__MASK 0x0007L
+#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L
+#define PCIE_BAR2_CNTL__BAR_SIZE__MASK 0x1F00L
+//PCIE_BAR3_CAP
+#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L
+//PCIE_BAR3_CNTL
+#define PCIE_BAR3_CNTL__BAR_INDEX__MASK 0x0007L
+#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L
+#define PCIE_BAR3_CNTL__BAR_SIZE__MASK 0x1F00L
+//PCIE_BAR4_CAP
+#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L
+//PCIE_BAR4_CNTL
+#define PCIE_BAR4_CNTL__BAR_INDEX__MASK 0x0007L
+#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L
+#define PCIE_BAR4_CNTL__BAR_SIZE__MASK 0x1F00L
+//PCIE_BAR5_CAP
+#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L
+//PCIE_BAR5_CNTL
+#define PCIE_BAR5_CNTL__BAR_INDEX__MASK 0x0007L
+#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L
+#define PCIE_BAR5_CNTL__BAR_SIZE__MASK 0x1F00L
+//PCIE_BAR6_CAP
+#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L
+//PCIE_BAR6_CNTL
+#define PCIE_BAR6_CNTL__BAR_INDEX__MASK 0x0007L
+#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L
+#define PCIE_BAR6_CNTL__BAR_SIZE__MASK 0x1F00L
+//PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
+//PCIE_PWR_BUDGET_DATA_SELECT
+#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__MASK 0xFFL
+//PCIE_PWR_BUDGET_DATA
+#define PCIE_PWR_BUDGET_DATA__BASE_POWER__MASK 0x000000FFL
+#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__MASK 0x00000300L
+#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__MASK 0x00001C00L
+#define PCIE_PWR_BUDGET_DATA__PM_STATE__MASK 0x00006000L
+#define PCIE_PWR_BUDGET_DATA__TYPE__MASK 0x00038000L
+#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__MASK 0x001C0000L
+//PCIE_PWR_BUDGET_CAP
+#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__MASK 0x01L
+//PCIE_DPA_ENH_CAP_LIST
+#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
+#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
+#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
+//PCIE_DPA_CAP
+#define PCIE_DPA_CAP__SUBSTATE_MAX__MASK 0x0000001FL
+#define PCIE_DPA_CAP__TRANS_LAT_UNIT__MASK 0x00000300L
+#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__MASK 0x00003000L
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__MASK 0x00FF0000L
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__MASK 0xFF000000L
+//PCIE_DPA_LATENCY_INDICATOR
+#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__MASK 0xFFL
+//PCIE_DPA_STATUS
+#define PCIE_DPA_STATUS__SUBSTATE_STATUS__MASK 0x001FL
+#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__MASK 0x0100L
+//PCIE_DPA_CNTL
+#define PCIE_DPA_CNTL__SUBSTATE_CNTL__MASK 0x1FL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__MASK 0xFFL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__MASK 0xFFL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__MASK 0xFFL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__MASK 0xFFL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__MASK 0xFFL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__MASK 0xFFL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__MASK 0xFFL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__MASK 0xFFL
+//PCIE_SECONDARY_ENH_CAP_LIST
+#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
+#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
+#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
+//PCIE_LINK_CNTL3
+#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__MASK 0x00000001L
+#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__MASK 0x00000002L
+#define PCIE_LINK_CNTL3__RESERVED__MASK 0xFFFFFFFCL
+//PCIE_LANE_ERROR_STATUS
+#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__MASK 0x0000FFFFL
+#define PCIE_LANE_ERROR_STATUS__RESERVED__MASK 0xFFFF0000L
+//PCIE_LANE_0_EQUALIZATION_CNTL
+#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
+#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
+#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
+#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
+#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
+//PCIE_LANE_1_EQUALIZATION_CNTL
+#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
+#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
+#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
+#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
+#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
+//PCIE_LANE_2_EQUALIZATION_CNTL
+#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
+#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
+#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
+#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
+#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
+//PCIE_LANE_3_EQUALIZATION_CNTL
+#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
+#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
+#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
+#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
+#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
+//PCIE_LANE_4_EQUALIZATION_CNTL
+#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
+#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
+#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
+#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
+#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
+//PCIE_LANE_5_EQUALIZATION_CNTL
+#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
+#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
+#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
+#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
+#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
+//PCIE_LANE_6_EQUALIZATION_CNTL
+#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
+#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
+#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
+#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
+#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
+//PCIE_LANE_7_EQUALIZATION_CNTL
+#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
+#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
+#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
+#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
+#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
+//PCIE_LANE_8_EQUALIZATION_CNTL
+#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
+#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
+#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
+#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
+#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
+//PCIE_LANE_9_EQUALIZATION_CNTL
+#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
+#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
+#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
+#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
+#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
+//PCIE_LANE_10_EQUALIZATION_CNTL
+#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
+#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
+#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
+#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
+#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
+//PCIE_LANE_11_EQUALIZATION_CNTL
+#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
+#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
+#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
+#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
+#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
+//PCIE_LANE_12_EQUALIZATION_CNTL
+#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
+#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
+#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
+#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
+#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
+//PCIE_LANE_13_EQUALIZATION_CNTL
+#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
+#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
+#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
+#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
+#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
+//PCIE_LANE_14_EQUALIZATION_CNTL
+#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
+#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
+#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
+#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
+#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
+//PCIE_LANE_15_EQUALIZATION_CNTL
+#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
+#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
+#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
+#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
+#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
+//PCIE_ACS_ENH_CAP_LIST
+#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
+#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
+#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
+//PCIE_ACS_CAP
+#define PCIE_ACS_CAP__SOURCE_VALIDATION__MASK 0x0001L
+#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__MASK 0x0002L
+#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__MASK 0x0004L
+#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__MASK 0x0008L
+#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__MASK 0x0010L
+#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__MASK 0x0020L
+#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__MASK 0x0040L
+#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__MASK 0xFF00L
+//PCIE_ACS_CNTL
+#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__MASK 0x0001L
+#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__MASK 0x0002L
+#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__MASK 0x0004L
+#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__MASK 0x0008L
+#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__MASK 0x0010L
+#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__MASK 0x0020L
+#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__MASK 0x0040L
+//PCIE_ATS_ENH_CAP_LIST
+#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
+#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
+#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
+//PCIE_ATS_CAP
+#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__MASK 0x001FL
+#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__MASK 0x0020L
+#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__MASK 0x0040L
+//PCIE_ATS_CNTL
+#define PCIE_ATS_CNTL__STU__MASK 0x001FL
+#define PCIE_ATS_CNTL__ATC_ENABLE__MASK 0x8000L
+//PCIE_PAGE_REQ_ENH_CAP_LIST
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
+//PCIE_PAGE_REQ_CNTL
+#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__MASK 0x0001L
+#define PCIE_PAGE_REQ_CNTL__PRI_RESET__MASK 0x0002L
+//PCIE_PAGE_REQ_STATUS
+#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__MASK 0x0001L
+#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__MASK 0x0002L
+#define PCIE_PAGE_REQ_STATUS__STOPPED__MASK 0x0100L
+#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__MASK 0x8000L
+//PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__MASK 0xFFFFFFFFL
+//PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__MASK 0xFFFFFFFFL
+//PCIE_PASID_ENH_CAP_LIST
+#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
+#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
+#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
+//PCIE_PASID_CAP
+#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__MASK 0x0002L
+#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__MASK 0x0004L
+#define PCIE_PASID_CAP__MAX_PASID_WIDTH__MASK 0x1F00L
+//PCIE_PASID_CNTL
+#define PCIE_PASID_CNTL__PASID_ENABLE__MASK 0x0001L
+#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__MASK 0x0002L
+#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__MASK 0x0004L
+//PCIE_TPH_REQR_ENH_CAP_LIST
+#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
+#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
+#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
+//PCIE_TPH_REQR_CAP
+#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__MASK 0x00000001L
+#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__MASK 0x00000002L
+#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__MASK 0x00000004L
+#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__MASK 0x00000100L
+#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__MASK 0x00000600L
+#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__MASK 0x07FF0000L
+//PCIE_TPH_REQR_CNTL
+#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__MASK 0x00000007L
+#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__MASK 0x00000300L
+//PCIE_MC_ENH_CAP_LIST
+#define PCIE_MC_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
+#define PCIE_MC_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
+#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
+//PCIE_MC_CAP
+#define PCIE_MC_CAP__MC_MAX_GROUP__MASK 0x003FL
+#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__MASK 0x3F00L
+#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__MASK 0x8000L
+//PCIE_MC_CNTL
+#define PCIE_MC_CNTL__MC_NUM_GROUP__MASK 0x003FL
+#define PCIE_MC_CNTL__MC_ENABLE__MASK 0x8000L
+//PCIE_MC_ADDR0
+#define PCIE_MC_ADDR0__MC_INDEX_POS__MASK 0x0000003FL
+#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__MASK 0xFFFFF000L
+//PCIE_MC_ADDR1
+#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__MASK 0xFFFFFFFFL
+//PCIE_MC_RCV0
+#define PCIE_MC_RCV0__MC_RECEIVE_0__MASK 0xFFFFFFFFL
+//PCIE_MC_RCV1
+#define PCIE_MC_RCV1__MC_RECEIVE_1__MASK 0xFFFFFFFFL
+//PCIE_MC_BLOCK_ALL0
+#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__MASK 0xFFFFFFFFL
+//PCIE_MC_BLOCK_ALL1
+#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__MASK 0xFFFFFFFFL
+//PCIE_MC_BLOCK_UNTRANSLATED_0
+#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__MASK 0xFFFFFFFFL
+//PCIE_MC_BLOCK_UNTRANSLATED_1
+#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__MASK 0xFFFFFFFFL
+//PCIE_LTR_ENH_CAP_LIST
+#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
+#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
+#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
+//PCIE_LTR_CAP
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__MASK 0x000003FFL
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__MASK 0x00001C00L
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__MASK 0x03FF0000L
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__MASK 0x1C000000L
+//PCIE_ARI_ENH_CAP_LIST
+#define PCIE_ARI_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
+#define PCIE_ARI_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
+#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
+//PCIE_ARI_CAP
+#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__MASK 0x0001L
+#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__MASK 0x0002L
+#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__MASK 0xFF00L
+//PCIE_ARI_CNTL
+#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__MASK 0x0001L
+#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__MASK 0x0002L
+#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__MASK 0x0070L
+//PCIE_SRIOV_ENH_CAP_LIST
+#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
+#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
+#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
+//PCIE_SRIOV_CAP
+#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__MASK 0x00000001L
+#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__MASK 0x00000002L
+#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__MASK 0xFFE00000L
+//PCIE_SRIOV_CONTROL
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__MASK 0x0001L
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__MASK 0x0002L
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__MASK 0x0004L
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__MASK 0x0008L
+#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__MASK 0x0010L
+//PCIE_SRIOV_STATUS
+#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__MASK 0x0001L
+//PCIE_SRIOV_INITIAL_VFS
+#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__MASK 0xFFFFL
+//PCIE_SRIOV_TOTAL_VFS
+#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__MASK 0xFFFFL
+//PCIE_SRIOV_NUM_VFS
+#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__MASK 0xFFFFL
+//PCIE_SRIOV_FUNC_DEP_LINK
+#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__MASK 0x00FFL
+//PCIE_SRIOV_FIRST_VF_OFFSET
+#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__MASK 0xFFFFL
+//PCIE_SRIOV_VF_STRIDE
+#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__MASK 0xFFFFL
+//PCIE_SRIOV_VF_DEVICE_ID
+#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__MASK 0xFFFFL
+//PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__MASK 0xFFFFFFFFL
+//PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__MASK 0xFFFFFFFFL
+//PCIE_SRIOV_VF_BASE_ADDR_0
+#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__MASK 0xFFFFFFFFL
+//PCIE_SRIOV_VF_BASE_ADDR_1
+#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__MASK 0xFFFFFFFFL
+//PCIE_SRIOV_VF_BASE_ADDR_2
+#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__MASK 0xFFFFFFFFL
+//PCIE_SRIOV_VF_BASE_ADDR_3
+#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__MASK 0xFFFFFFFFL
+//PCIE_SRIOV_VF_BASE_ADDR_4
+#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__MASK 0xFFFFFFFFL
+//PCIE_SRIOV_VF_BASE_ADDR_5
+#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__MASK 0xFFFFFFFFL
+//PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__MASK 0x00000007L
+#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__MASK 0xFFFFFFF8L
+//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__MASK 0x000F0000L
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__MASK 0xFFF00000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__MASK 0x000F0000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__MASK 0xFFF00000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__MASK 0x00000001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__MASK 0x00000001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__MASK 0x00000002L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__MASK 0x00000004L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__MASK 0x00000008L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__MASK 0x00000100L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__MASK 0x00000200L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__MASK 0x00000400L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__MASK 0x00000800L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__MASK 0x00010000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__MASK 0x00020000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__MASK 0x00040000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__MASK 0x00080000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__MASK 0x01000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__MASK 0x02000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__MASK 0x00000001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__MASK 0x00000002L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__MASK 0x00000004L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__MASK 0x00000008L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__MASK 0x00000100L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__MASK 0x00000200L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__MASK 0x00000400L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__MASK 0x00000800L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__MASK 0x00010000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__MASK 0x00020000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__MASK 0x00040000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__MASK 0x00080000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__MASK 0x01000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__MASK 0x02000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__MASK 0x0001L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__MASK 0x000000FFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__MASK 0x00000F00L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__MASK 0x00008000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__MASK 0x000F0000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__MASK 0x01000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__MASK 0x00000001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__MASK 0x00000002L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__MASK 0x00000004L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__MASK 0x00000008L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__MASK 0x00000010L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__MASK 0x00000020L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__MASK 0x00000040L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__MASK 0x00000080L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__MASK 0x00000100L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__MASK 0x00000200L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__MASK 0x00000400L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__MASK 0x00000800L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__MASK 0x00001000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__MASK 0x00002000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__MASK 0x00004000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__MASK 0x00008000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__MASK 0x00010000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__MASK 0x00020000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__MASK 0x00040000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__MASK 0x00080000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__MASK 0x00100000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__MASK 0x00200000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__MASK 0x00400000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__MASK 0x00800000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__MASK 0x01000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__MASK 0x02000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__MASK 0x04000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__MASK 0x08000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__MASK 0x10000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__MASK 0x20000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__MASK 0x40000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__MASK 0x80000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__MASK 0x00000001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__MASK 0x00000002L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__MASK 0x0000007FL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__MASK 0x00000080L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__MASK 0xFFFFFC00L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__MASK 0x000000FFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__MASK 0x0000FF00L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__MASK 0x00FF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__MASK 0xFFFFFFFFL
+
+
+// addressBlock: bif_cfg_dev0_swds_bifcfgdecp
+//SUB_BUS_NUMBER_LATENCY
+#define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__MASK 0x000000FFL
+#define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__MASK 0x0000FF00L
+#define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__MASK 0x00FF0000L
+#define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__MASK 0xFF000000L
+//IO_BASE_LIMIT
+#define IO_BASE_LIMIT__IO_BASE_TYPE__MASK 0x000FL
+#define IO_BASE_LIMIT__IO_BASE__MASK 0x00F0L
+#define IO_BASE_LIMIT__IO_LIMIT_TYPE__MASK 0x0F00L
+#define IO_BASE_LIMIT__IO_LIMIT__MASK 0xF000L
+//SECONDARY_STATUS
+#define SECONDARY_STATUS__CAP_LIST__MASK 0x0010L
+#define SECONDARY_STATUS__PCI_66_EN__MASK 0x0020L
+#define SECONDARY_STATUS__FAST_BACK_CAPABLE__MASK 0x0080L
+#define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__MASK 0x0100L
+#define SECONDARY_STATUS__DEVSEL_TIMING__MASK 0x0600L
+#define SECONDARY_STATUS__SIGNAL_TARGET_ABORT__MASK 0x0800L
+#define SECONDARY_STATUS__RECEIVED_TARGET_ABORT__MASK 0x1000L
+#define SECONDARY_STATUS__RECEIVED_MASTER_ABORT__MASK 0x2000L
+#define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__MASK 0x4000L
+#define SECONDARY_STATUS__PARITY_ERROR_DETECTED__MASK 0x8000L
+//MEM_BASE_LIMIT
+#define MEM_BASE_LIMIT__MEM_BASE_TYPE__MASK 0x0000000FL
+#define MEM_BASE_LIMIT__MEM_BASE_31_20__MASK 0x0000FFF0L
+#define MEM_BASE_LIMIT__MEM_LIMIT_TYPE__MASK 0x000F0000L
+#define MEM_BASE_LIMIT__MEM_LIMIT_31_20__MASK 0xFFF00000L
+//PREF_BASE_LIMIT
+#define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__MASK 0x0000000FL
+#define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__MASK 0x0000FFF0L
+#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__MASK 0x000F0000L
+#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__MASK 0xFFF00000L
+//PREF_BASE_UPPER
+#define PREF_BASE_UPPER__PREF_BASE_UPPER__MASK 0xFFFFFFFFL
+//PREF_LIMIT_UPPER
+#define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__MASK 0xFFFFFFFFL
+//IO_BASE_LIMIT_HI
+#define IO_BASE_LIMIT_HI__IO_BASE_31_16__MASK 0x0000FFFFL
+#define IO_BASE_LIMIT_HI__IO_LIMIT_31_16__MASK 0xFFFF0000L
+//IRQ_BRIDGE_CNTL
+#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__MASK 0x0001L
+#define IRQ_BRIDGE_CNTL__SERR_EN__MASK 0x0002L
+#define IRQ_BRIDGE_CNTL__ISA_EN__MASK 0x0004L
+#define IRQ_BRIDGE_CNTL__VGA_EN__MASK 0x0008L
+#define IRQ_BRIDGE_CNTL__VGA_DEC__MASK 0x0010L
+#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__MASK 0x0020L
+#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__MASK 0x0040L
+#define IRQ_BRIDGE_CNTL__FAST_B2B_EN__MASK 0x0080L
+//SLOT_CAP
+#define SLOT_CAP__ATTN_BUTTON_PRESENT__MASK 0x00000001L
+#define SLOT_CAP__PWR_CONTROLLER_PRESENT__MASK 0x00000002L
+#define SLOT_CAP__MRL_SENSOR_PRESENT__MASK 0x00000004L
+#define SLOT_CAP__ATTN_INDICATOR_PRESENT__MASK 0x00000008L
+#define SLOT_CAP__PWR_INDICATOR_PRESENT__MASK 0x00000010L
+#define SLOT_CAP__HOTPLUG_SURPRISE__MASK 0x00000020L
+#define SLOT_CAP__HOTPLUG_CAPABLE__MASK 0x00000040L
+#define SLOT_CAP__SLOT_PWR_LIMIT_VALUE__MASK 0x00007F80L
+#define SLOT_CAP__SLOT_PWR_LIMIT_SCALE__MASK 0x00018000L
+#define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__MASK 0x00020000L
+#define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__MASK 0x00040000L
+#define SLOT_CAP__PHYSICAL_SLOT_NUM__MASK 0xFFF80000L
+//SLOT_CNTL
+#define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__MASK 0x0001L
+#define SLOT_CNTL__PWR_FAULT_DETECTED_EN__MASK 0x0002L
+#define SLOT_CNTL__MRL_SENSOR_CHANGED_EN__MASK 0x0004L
+#define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__MASK 0x0008L
+#define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__MASK 0x0010L
+#define SLOT_CNTL__HOTPLUG_INTR_EN__MASK 0x0020L
+#define SLOT_CNTL__ATTN_INDICATOR_CNTL__MASK 0x00C0L
+#define SLOT_CNTL__PWR_INDICATOR_CNTL__MASK 0x0300L
+#define SLOT_CNTL__PWR_CONTROLLER_CNTL__MASK 0x0400L
+#define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__MASK 0x0800L
+#define SLOT_CNTL__DL_STATE_CHANGED_EN__MASK 0x1000L
+//SLOT_STATUS
+#define SLOT_STATUS__ATTN_BUTTON_PRESSED__MASK 0x0001L
+#define SLOT_STATUS__PWR_FAULT_DETECTED__MASK 0x0002L
+#define SLOT_STATUS__MRL_SENSOR_CHANGED__MASK 0x0004L
+#define SLOT_STATUS__PRESENCE_DETECT_CHANGED__MASK 0x0008L
+#define SLOT_STATUS__COMMAND_COMPLETED__MASK 0x0010L
+#define SLOT_STATUS__MRL_SENSOR_STATE__MASK 0x0020L
+#define SLOT_STATUS__PRESENCE_DETECT_STATE__MASK 0x0040L
+#define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__MASK 0x0080L
+#define SLOT_STATUS__DL_STATE_CHANGED__MASK 0x0100L
+//SSID_CAP_LIST
+#define SSID_CAP_LIST__CAP_ID__MASK 0x00FFL
+#define SSID_CAP_LIST__NEXT_PTR__MASK 0xFF00L
+//SSID_CAP
+#define SSID_CAP__SUBSYSTEM_VENDOR_ID__MASK 0x0000FFFFL
+#define SSID_CAP__SUBSYSTEM_ID__MASK 0xFFFF0000L
+
+
+// addressBlock: rcc_shadow_reg_shadowdec
+//SHADOW_COMMAND
+#define SHADOW_COMMAND__IOEN_UP__MASK 0x0001L
+#define SHADOW_COMMAND__MEMEN_UP__MASK 0x0002L
+//SHADOW_BASE_ADDR_1
+#define SHADOW_BASE_ADDR_1__BAR1_UP__MASK 0xFFFFFFFFL
+//SHADOW_BASE_ADDR_2
+#define SHADOW_BASE_ADDR_2__BAR2_UP__MASK 0xFFFFFFFFL
+//SHADOW_SUB_BUS_NUMBER_LATENCY
+#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__MASK 0x0000FF00L
+#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__MASK 0x00FF0000L
+//SHADOW_IO_BASE_LIMIT
+#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__MASK 0x00F0L
+#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__MASK 0xF000L
+//SHADOW_MEM_BASE_LIMIT
+#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__MASK 0x0000000FL
+#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__MASK 0x0000FFF0L
+#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__MASK 0x000F0000L
+#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__MASK 0xFFF00000L
+//SHADOW_PREF_BASE_LIMIT
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__MASK 0x0000000FL
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__MASK 0x0000FFF0L
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__MASK 0x000F0000L
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__MASK 0xFFF00000L
+//SHADOW_PREF_BASE_UPPER
+#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__MASK 0xFFFFFFFFL
+//SHADOW_PREF_LIMIT_UPPER
+#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__MASK 0xFFFFFFFFL
+//SHADOW_IO_BASE_LIMIT_HI
+#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__MASK 0x0000FFFFL
+#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__MASK 0xFFFF0000L
+//SHADOW_IRQ_BRIDGE_CNTL
+#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__MASK 0x0004L
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__MASK 0x0008L
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__MASK 0x0010L
+#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__MASK 0x0040L
+//SUC_INDEX
+#define SUC_INDEX__SUC_INDEX__MASK 0xFFFFFFFFL
+//SUC_DATA
+#define SUC_DATA__SUC_DATA__MASK 0xFFFFFFFFL
+
+
+// addressBlock: bif_bx_pf_SUMDEC
+//SUM_INDEX
+#define SUM_INDEX__SUM_INDEX__MASK 0xFFFFFFFFL
+//SUM_DATA
+#define SUM_DATA__SUM_DATA__MASK 0xFFFFFFFFL
+
+
+// addressBlock: gdc_GDCDEC
+//A2S_CNTL_CL0
+#define A2S_CNTL_CL0__NSNOOP_MAP__MASK 0x00000003L
+#define A2S_CNTL_CL0__REQPASSPW_VC0_MAP__MASK 0x0000000CL
+#define A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__MASK 0x00000030L
+#define A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L
+#define A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L
+#define A2S_CNTL_CL0__BLKLVL_MAP__MASK 0x00000C00L
+#define A2S_CNTL_CL0__DATERR_MAP__MASK 0x00003000L
+#define A2S_CNTL_CL0__EXOKAY_WR_MAP__MASK 0x0000C000L
+#define A2S_CNTL_CL0__EXOKAY_RD_MAP__MASK 0x00030000L
+#define A2S_CNTL_CL0__RESP_WR_MAP__MASK 0x000C0000L
+#define A2S_CNTL_CL0__RESP_RD_MAP__MASK 0x00300000L
+//A2S_CNTL_CL1
+#define A2S_CNTL_CL1__NSNOOP_MAP__MASK 0x00000003L
+#define A2S_CNTL_CL1__REQPASSPW_VC0_MAP__MASK 0x0000000CL
+#define A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__MASK 0x00000030L
+#define A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L
+#define A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L
+#define A2S_CNTL_CL1__BLKLVL_MAP__MASK 0x00000C00L
+#define A2S_CNTL_CL1__DATERR_MAP__MASK 0x00003000L
+#define A2S_CNTL_CL1__EXOKAY_WR_MAP__MASK 0x0000C000L
+#define A2S_CNTL_CL1__EXOKAY_RD_MAP__MASK 0x00030000L
+#define A2S_CNTL_CL1__RESP_WR_MAP__MASK 0x000C0000L
+#define A2S_CNTL_CL1__RESP_RD_MAP__MASK 0x00300000L
+//A2S_CNTL_CL2
+#define A2S_CNTL_CL2__NSNOOP_MAP__MASK 0x00000003L
+#define A2S_CNTL_CL2__REQPASSPW_VC0_MAP__MASK 0x0000000CL
+#define A2S_CNTL_CL2__REQPASSPW_NVC0_MAP__MASK 0x00000030L
+#define A2S_CNTL_CL2__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L
+#define A2S_CNTL_CL2__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L
+#define A2S_CNTL_CL2__BLKLVL_MAP__MASK 0x00000C00L
+#define A2S_CNTL_CL2__DATERR_MAP__MASK 0x00003000L
+#define A2S_CNTL_CL2__EXOKAY_WR_MAP__MASK 0x0000C000L
+#define A2S_CNTL_CL2__EXOKAY_RD_MAP__MASK 0x00030000L
+#define A2S_CNTL_CL2__RESP_WR_MAP__MASK 0x000C0000L
+#define A2S_CNTL_CL2__RESP_RD_MAP__MASK 0x00300000L
+//A2S_CNTL_CL3
+#define A2S_CNTL_CL3__NSNOOP_MAP__MASK 0x00000003L
+#define A2S_CNTL_CL3__REQPASSPW_VC0_MAP__MASK 0x0000000CL
+#define A2S_CNTL_CL3__REQPASSPW_NVC0_MAP__MASK 0x00000030L
+#define A2S_CNTL_CL3__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L
+#define A2S_CNTL_CL3__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L
+#define A2S_CNTL_CL3__BLKLVL_MAP__MASK 0x00000C00L
+#define A2S_CNTL_CL3__DATERR_MAP__MASK 0x00003000L
+#define A2S_CNTL_CL3__EXOKAY_WR_MAP__MASK 0x0000C000L
+#define A2S_CNTL_CL3__EXOKAY_RD_MAP__MASK 0x00030000L
+#define A2S_CNTL_CL3__RESP_WR_MAP__MASK 0x000C0000L
+#define A2S_CNTL_CL3__RESP_RD_MAP__MASK 0x00300000L
+//A2S_CNTL_CL4
+#define A2S_CNTL_CL4__NSNOOP_MAP__MASK 0x00000003L
+#define A2S_CNTL_CL4__REQPASSPW_VC0_MAP__MASK 0x0000000CL
+#define A2S_CNTL_CL4__REQPASSPW_NVC0_MAP__MASK 0x00000030L
+#define A2S_CNTL_CL4__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L
+#define A2S_CNTL_CL4__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L
+#define A2S_CNTL_CL4__BLKLVL_MAP__MASK 0x00000C00L
+#define A2S_CNTL_CL4__DATERR_MAP__MASK 0x00003000L
+#define A2S_CNTL_CL4__EXOKAY_WR_MAP__MASK 0x0000C000L
+#define A2S_CNTL_CL4__EXOKAY_RD_MAP__MASK 0x00030000L
+#define A2S_CNTL_CL4__RESP_WR_MAP__MASK 0x000C0000L
+#define A2S_CNTL_CL4__RESP_RD_MAP__MASK 0x00300000L
+//A2S_CNTL_SW0
+#define A2S_CNTL_SW0__WR_TAG_SET_MIN__MASK 0x00000007L
+#define A2S_CNTL_SW0__RD_TAG_SET_MIN__MASK 0x00000038L
+#define A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__MASK 0x00000040L
+#define A2S_CNTL_SW0__RSP_REORDER_DIS__MASK 0x00000080L
+#define A2S_CNTL_SW0__WRRSP_ACCUM_SEL__MASK 0x00000100L
+#define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__MASK 0x00000200L
+#define A2S_CNTL_SW0__WRRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000400L
+#define A2S_CNTL_SW0__RDRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000800L
+#define A2S_CNTL_SW0__RDRSP_STS_DATSTS_PRIORITY__MASK 0x00001000L
+#define A2S_CNTL_SW0__WRR_RD_WEIGHT__MASK 0x00FF0000L
+#define A2S_CNTL_SW0__WRR_WR_WEIGHT__MASK 0xFF000000L
+//A2S_CNTL_SW1
+#define A2S_CNTL_SW1__WR_TAG_SET_MIN__MASK 0x00000007L
+#define A2S_CNTL_SW1__RD_TAG_SET_MIN__MASK 0x00000038L
+#define A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__MASK 0x00000040L
+#define A2S_CNTL_SW1__RSP_REORDER_DIS__MASK 0x00000080L
+#define A2S_CNTL_SW1__WRRSP_ACCUM_SEL__MASK 0x00000100L
+#define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__MASK 0x00000200L
+#define A2S_CNTL_SW1__WRRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000400L
+#define A2S_CNTL_SW1__RDRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000800L
+#define A2S_CNTL_SW1__RDRSP_STS_DATSTS_PRIORITY__MASK 0x00001000L
+#define A2S_CNTL_SW1__WRR_RD_WEIGHT__MASK 0x00FF0000L
+#define A2S_CNTL_SW1__WRR_WR_WEIGHT__MASK 0xFF000000L
+//A2S_CNTL_SW2
+#define A2S_CNTL_SW2__WR_TAG_SET_MIN__MASK 0x00000007L
+#define A2S_CNTL_SW2__RD_TAG_SET_MIN__MASK 0x00000038L
+#define A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__MASK 0x00000040L
+#define A2S_CNTL_SW2__RSP_REORDER_DIS__MASK 0x00000080L
+#define A2S_CNTL_SW2__WRRSP_ACCUM_SEL__MASK 0x00000100L
+#define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__MASK 0x00000200L
+#define A2S_CNTL_SW2__WRRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000400L
+#define A2S_CNTL_SW2__RDRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000800L
+#define A2S_CNTL_SW2__RDRSP_STS_DATSTS_PRIORITY__MASK 0x00001000L
+#define A2S_CNTL_SW2__WRR_RD_WEIGHT__MASK 0x00FF0000L
+#define A2S_CNTL_SW2__WRR_WR_WEIGHT__MASK 0xFF000000L
+//NGDC_MGCG_CTRL
+#define NGDC_MGCG_CTRL__NGDC_MGCG_EN__MASK 0x00000001L
+#define NGDC_MGCG_CTRL__NGDC_MGCG_MODE__MASK 0x00000002L
+#define NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__MASK 0x000003FCL
+//A2S_MISC_CNTL
+#define A2S_MISC_CNTL__BLKLVL_FOR_MSG__MASK 0x00000003L
+#define A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__MASK 0x00000004L
+//NGDC_SDP_PORT_CTRL
+#define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__MASK 0x0000003FL
+//NGDC_RESERVED_0
+#define NGDC_RESERVED_0__RESERVED__MASK 0xFFFFFFFFL
+//NGDC_RESERVED_1
+#define NGDC_RESERVED_1__RESERVED__MASK 0xFFFFFFFFL
+//BIF_SDMA0_DOORBELL_RANGE
+#define BIF_SDMA0_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL
+#define BIF_SDMA0_DOORBELL_RANGE__SIZE__MASK 0x001F0000L
+//BIF_SDMA1_DOORBELL_RANGE
+#define BIF_SDMA1_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL
+#define BIF_SDMA1_DOORBELL_RANGE__SIZE__MASK 0x001F0000L
+//BIF_IH_DOORBELL_RANGE
+#define BIF_IH_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL
+#define BIF_IH_DOORBELL_RANGE__SIZE__MASK 0x001F0000L
+//BIF_MMSCH0_DOORBELL_RANGE
+#define BIF_MMSCH0_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL
+#define BIF_MMSCH0_DOORBELL_RANGE__SIZE__MASK 0x001F0000L
+//BIF_DOORBELL_FENCE_CNTL
+#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__MASK 0x00000001L
+//S2A_MISC_CNTL
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__MASK 0x00000001L
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__MASK 0x00000002L
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__MASK 0x00000004L
+//A2S_CNTL2_SEC_CL0
+#define A2S_CNTL2_SEC_CL0__SECLVL_MAP__MASK 0x00000007L
+//A2S_CNTL2_SEC_CL1
+#define A2S_CNTL2_SEC_CL1__SECLVL_MAP__MASK 0x00000007L
+//A2S_CNTL2_SEC_CL2
+#define A2S_CNTL2_SEC_CL2__SECLVL_MAP__MASK 0x00000007L
+//A2S_CNTL2_SEC_CL3
+#define A2S_CNTL2_SEC_CL3__SECLVL_MAP__MASK 0x00000007L
+//A2S_CNTL2_SEC_CL4
+#define A2S_CNTL2_SEC_CL4__SECLVL_MAP__MASK 0x00000007L
+
+
+// addressBlock: nbif_sion_SIONDEC
+//SION_CL0_RdRsp_BurstTarget_REG0
+#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
+//SION_CL0_RdRsp_BurstTarget_REG1
+#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
+//SION_CL0_RdRsp_TimeSlot_REG0
+#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
+//SION_CL0_RdRsp_TimeSlot_REG1
+#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
+//SION_CL0_WrRsp_BurstTarget_REG0
+#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
+//SION_CL0_WrRsp_BurstTarget_REG1
+#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
+//SION_CL0_WrRsp_TimeSlot_REG0
+#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
+//SION_CL0_WrRsp_TimeSlot_REG1
+#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
+//SION_CL0_Req_BurstTarget_REG0
+#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL
+//SION_CL0_Req_BurstTarget_REG1
+#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL
+//SION_CL0_Req_TimeSlot_REG0
+#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL
+//SION_CL0_Req_TimeSlot_REG1
+#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL
+//SION_CL0_ReqPoolCredit_Alloc_REG0
+#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL0_ReqPoolCredit_Alloc_REG1
+#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL0_DataPoolCredit_Alloc_REG0
+#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL0_DataPoolCredit_Alloc_REG1
+#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL0_RdRspPoolCredit_Alloc_REG0
+#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL0_RdRspPoolCredit_Alloc_REG1
+#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL0_WrRspPoolCredit_Alloc_REG0
+#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL0_WrRspPoolCredit_Alloc_REG1
+#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL1_RdRsp_BurstTarget_REG0
+#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
+//SION_CL1_RdRsp_BurstTarget_REG1
+#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
+//SION_CL1_RdRsp_TimeSlot_REG0
+#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
+//SION_CL1_RdRsp_TimeSlot_REG1
+#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
+//SION_CL1_WrRsp_BurstTarget_REG0
+#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
+//SION_CL1_WrRsp_BurstTarget_REG1
+#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
+//SION_CL1_WrRsp_TimeSlot_REG0
+#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
+//SION_CL1_WrRsp_TimeSlot_REG1
+#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
+//SION_CL1_Req_BurstTarget_REG0
+#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL
+//SION_CL1_Req_BurstTarget_REG1
+#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL
+//SION_CL1_Req_TimeSlot_REG0
+#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL
+//SION_CL1_Req_TimeSlot_REG1
+#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL
+//SION_CL1_ReqPoolCredit_Alloc_REG0
+#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL1_ReqPoolCredit_Alloc_REG1
+#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL1_DataPoolCredit_Alloc_REG0
+#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL1_DataPoolCredit_Alloc_REG1
+#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL1_RdRspPoolCredit_Alloc_REG0
+#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL1_RdRspPoolCredit_Alloc_REG1
+#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL1_WrRspPoolCredit_Alloc_REG0
+#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL1_WrRspPoolCredit_Alloc_REG1
+#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL2_RdRsp_BurstTarget_REG0
+#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
+//SION_CL2_RdRsp_BurstTarget_REG1
+#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
+//SION_CL2_RdRsp_TimeSlot_REG0
+#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
+//SION_CL2_RdRsp_TimeSlot_REG1
+#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
+//SION_CL2_WrRsp_BurstTarget_REG0
+#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
+//SION_CL2_WrRsp_BurstTarget_REG1
+#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
+//SION_CL2_WrRsp_TimeSlot_REG0
+#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
+//SION_CL2_WrRsp_TimeSlot_REG1
+#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
+//SION_CL2_Req_BurstTarget_REG0
+#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL
+//SION_CL2_Req_BurstTarget_REG1
+#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL
+//SION_CL2_Req_TimeSlot_REG0
+#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL
+//SION_CL2_Req_TimeSlot_REG1
+#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL
+//SION_CL2_ReqPoolCredit_Alloc_REG0
+#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL2_ReqPoolCredit_Alloc_REG1
+#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL2_DataPoolCredit_Alloc_REG0
+#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL2_DataPoolCredit_Alloc_REG1
+#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL2_RdRspPoolCredit_Alloc_REG0
+#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL2_RdRspPoolCredit_Alloc_REG1
+#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL2_WrRspPoolCredit_Alloc_REG0
+#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL2_WrRspPoolCredit_Alloc_REG1
+#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL3_RdRsp_BurstTarget_REG0
+#define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
+//SION_CL3_RdRsp_BurstTarget_REG1
+#define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
+//SION_CL3_RdRsp_TimeSlot_REG0
+#define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
+//SION_CL3_RdRsp_TimeSlot_REG1
+#define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
+//SION_CL3_WrRsp_BurstTarget_REG0
+#define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
+//SION_CL3_WrRsp_BurstTarget_REG1
+#define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
+//SION_CL3_WrRsp_TimeSlot_REG0
+#define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
+//SION_CL3_WrRsp_TimeSlot_REG1
+#define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
+//SION_CL3_Req_BurstTarget_REG0
+#define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL
+//SION_CL3_Req_BurstTarget_REG1
+#define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL
+//SION_CL3_Req_TimeSlot_REG0
+#define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL
+//SION_CL3_Req_TimeSlot_REG1
+#define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL
+//SION_CL3_ReqPoolCredit_Alloc_REG0
+#define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL3_ReqPoolCredit_Alloc_REG1
+#define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL3_DataPoolCredit_Alloc_REG0
+#define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL3_DataPoolCredit_Alloc_REG1
+#define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL3_RdRspPoolCredit_Alloc_REG0
+#define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL3_RdRspPoolCredit_Alloc_REG1
+#define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL3_WrRspPoolCredit_Alloc_REG0
+#define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL3_WrRspPoolCredit_Alloc_REG1
+#define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL4_RdRsp_BurstTarget_REG0
+#define SION_CL4_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
+//SION_CL4_RdRsp_BurstTarget_REG1
+#define SION_CL4_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
+//SION_CL4_RdRsp_TimeSlot_REG0
+#define SION_CL4_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
+//SION_CL4_RdRsp_TimeSlot_REG1
+#define SION_CL4_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
+//SION_CL4_WrRsp_BurstTarget_REG0
+#define SION_CL4_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
+//SION_CL4_WrRsp_BurstTarget_REG1
+#define SION_CL4_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
+//SION_CL4_WrRsp_TimeSlot_REG0
+#define SION_CL4_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
+//SION_CL4_WrRsp_TimeSlot_REG1
+#define SION_CL4_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
+//SION_CL4_Req_BurstTarget_REG0
+#define SION_CL4_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL
+//SION_CL4_Req_BurstTarget_REG1
+#define SION_CL4_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL
+//SION_CL4_Req_TimeSlot_REG0
+#define SION_CL4_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL
+//SION_CL4_Req_TimeSlot_REG1
+#define SION_CL4_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL
+//SION_CL4_ReqPoolCredit_Alloc_REG0
+#define SION_CL4_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL4_ReqPoolCredit_Alloc_REG1
+#define SION_CL4_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL4_DataPoolCredit_Alloc_REG0
+#define SION_CL4_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL4_DataPoolCredit_Alloc_REG1
+#define SION_CL4_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL4_RdRspPoolCredit_Alloc_REG0
+#define SION_CL4_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL4_RdRspPoolCredit_Alloc_REG1
+#define SION_CL4_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL4_WrRspPoolCredit_Alloc_REG0
+#define SION_CL4_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL4_WrRspPoolCredit_Alloc_REG1
+#define SION_CL4_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL5_RdRsp_BurstTarget_REG0
+#define SION_CL5_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
+//SION_CL5_RdRsp_BurstTarget_REG1
+#define SION_CL5_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
+//SION_CL5_RdRsp_TimeSlot_REG0
+#define SION_CL5_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
+//SION_CL5_RdRsp_TimeSlot_REG1
+#define SION_CL5_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
+//SION_CL5_WrRsp_BurstTarget_REG0
+#define SION_CL5_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
+//SION_CL5_WrRsp_BurstTarget_REG1
+#define SION_CL5_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
+//SION_CL5_WrRsp_TimeSlot_REG0
+#define SION_CL5_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
+//SION_CL5_WrRsp_TimeSlot_REG1
+#define SION_CL5_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
+//SION_CL5_Req_BurstTarget_REG0
+#define SION_CL5_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL
+//SION_CL5_Req_BurstTarget_REG1
+#define SION_CL5_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL
+//SION_CL5_Req_TimeSlot_REG0
+#define SION_CL5_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL
+//SION_CL5_Req_TimeSlot_REG1
+#define SION_CL5_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL
+//SION_CL5_ReqPoolCredit_Alloc_REG0
+#define SION_CL5_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL5_ReqPoolCredit_Alloc_REG1
+#define SION_CL5_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL5_DataPoolCredit_Alloc_REG0
+#define SION_CL5_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL5_DataPoolCredit_Alloc_REG1
+#define SION_CL5_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL5_RdRspPoolCredit_Alloc_REG0
+#define SION_CL5_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL5_RdRspPoolCredit_Alloc_REG1
+#define SION_CL5_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CL5_WrRspPoolCredit_Alloc_REG0
+#define SION_CL5_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
+//SION_CL5_WrRspPoolCredit_Alloc_REG1
+#define SION_CL5_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
+//SION_CNTL_REG0
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__MASK 0x00000001L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__MASK 0x00000002L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__MASK 0x00000004L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__MASK 0x00000008L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__MASK 0x00000010L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__MASK 0x00000020L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__MASK 0x00000040L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__MASK 0x00000080L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__MASK 0x00000100L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__MASK 0x00000200L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__MASK 0x00000400L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__MASK 0x00000800L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__MASK 0x00001000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__MASK 0x00002000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__MASK 0x00004000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__MASK 0x00008000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__MASK 0x00010000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__MASK 0x00020000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__MASK 0x00040000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__MASK 0x00080000L
+//SION_CNTL_REG1
+#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__MASK 0x000000FFL
+#define SION_CNTL_REG1__CG_OFF_HYSTERESIS__MASK 0x0000FF00L
+
+
+// addressBlock: syshub_mmreg_direct_syshubdirect
+//SYSHUB_DS_CTRL_SOCCLK
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L
+#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L
+#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__MASK 0x80000000L
+//SYSHUB_DS_CTRL2_SOCCLK
+#define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__MASK 0x0000FFFFL
+//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__MASK 0x00000001L
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__MASK 0x00000002L
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__MASK 0x00008000L
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__MASK 0x00010000L
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__MASK 0x00020000L
+//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__MASK 0x00000001L
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__MASK 0x00000002L
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__MASK 0x00008000L
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__MASK 0x00010000L
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__MASK 0x00020000L
+//DMA_CLK0_SW0_SYSHUB_QOS_CNTL
+#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L
+#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL
+#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L
+//DMA_CLK0_SW1_SYSHUB_QOS_CNTL
+#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L
+#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL
+#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L
+//DMA_CLK0_SW0_CL0_CNTL
+#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//DMA_CLK0_SW0_CL1_CNTL
+#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//DMA_CLK0_SW0_CL2_CNTL
+#define DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//DMA_CLK0_SW0_CL3_CNTL
+#define DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//DMA_CLK0_SW0_CL4_CNTL
+#define DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//DMA_CLK0_SW0_CL5_CNTL
+#define DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//DMA_CLK0_SW1_CL0_CNTL
+#define DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//DMA_CLK0_SW2_CL0_CNTL
+#define DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//SYSHUB_CG_CNTL
+#define SYSHUB_CG_CNTL__SYSHUB_CG_EN__MASK 0x00000001L
+#define SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__MASK 0x0000FF00L
+#define SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__MASK 0x00FF0000L
+//SYSHUB_TRANS_IDLE
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__MASK 0x00000001L
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__MASK 0x00000002L
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__MASK 0x00000004L
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__MASK 0x00000008L
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__MASK 0x00000010L
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__MASK 0x00000020L
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__MASK 0x00000040L
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__MASK 0x00000080L
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__MASK 0x00000100L
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__MASK 0x00000200L
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__MASK 0x00000400L
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__MASK 0x00000800L
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__MASK 0x00001000L
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__MASK 0x00002000L
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__MASK 0x00004000L
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__MASK 0x00008000L
+#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__MASK 0x00010000L
+//SYSHUB_HP_TIMER
+#define SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__MASK 0xFFFFFFFFL
+//SYSHUB_SCRATCH
+#define SYSHUB_SCRATCH__SCRATCH__MASK 0xFFFFFFFFL
+//SYSHUB_DS_CTRL_SHUBCLK
+#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L
+#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L
+#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L
+#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L
+#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L
+#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L
+#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L
+#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L
+#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L
+#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L
+#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L
+#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L
+#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L
+#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L
+#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L
+#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L
+#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L
+#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__MASK 0x80000000L
+//SYSHUB_DS_CTRL2_SHUBCLK
+#define SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__MASK 0x0000FFFFL
+//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__MASK 0x00008000L
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__MASK 0x00010000L
+//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__MASK 0x00008000L
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__MASK 0x00010000L
+//DMA_CLK1_SW0_SYSHUB_QOS_CNTL
+#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L
+#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL
+#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L
+//DMA_CLK1_SW1_SYSHUB_QOS_CNTL
+#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L
+#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL
+#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L
+//DMA_CLK1_SW0_CL0_CNTL
+#define DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//DMA_CLK1_SW0_CL1_CNTL
+#define DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//DMA_CLK1_SW0_CL2_CNTL
+#define DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//DMA_CLK1_SW0_CL3_CNTL
+#define DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//DMA_CLK1_SW0_CL4_CNTL
+#define DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//DMA_CLK1_SW1_CL0_CNTL
+#define DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//DMA_CLK1_SW1_CL1_CNTL
+#define DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//DMA_CLK1_SW1_CL2_CNTL
+#define DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//DMA_CLK1_SW1_CL3_CNTL
+#define DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//DMA_CLK1_SW1_CL4_CNTL
+#define DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+
+
+// addressBlock: gdc_ras_gdc_ras_regblk
+//GDC_RAS_LEAF0_CTRL
+#define GDC_RAS_LEAF0_CTRL__POISON_DET_EN__MASK 0x00000001L
+#define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L
+#define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN__MASK 0x00000004L
+#define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN__MASK 0x00000010L
+#define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L
+#define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN__MASK 0x00000040L
+#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV__MASK 0x00010000L
+#define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV__MASK 0x00020000L
+#define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET__MASK 0x00040000L
+#define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET__MASK 0x00080000L
+#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT__MASK 0x00100000L
+#define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED__MASK 0x00200000L
+//GDC_RAS_LEAF1_CTRL
+#define GDC_RAS_LEAF1_CTRL__POISON_DET_EN__MASK 0x00000001L
+#define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L
+#define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN__MASK 0x00000004L
+#define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN__MASK 0x00000010L
+#define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L
+#define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN__MASK 0x00000040L
+#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV__MASK 0x00010000L
+#define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV__MASK 0x00020000L
+#define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET__MASK 0x00040000L
+#define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET__MASK 0x00080000L
+#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT__MASK 0x00100000L
+#define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED__MASK 0x00200000L
+//GDC_RAS_LEAF2_CTRL
+#define GDC_RAS_LEAF2_CTRL__POISON_DET_EN__MASK 0x00000001L
+#define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L
+#define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN__MASK 0x00000004L
+#define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN__MASK 0x00000010L
+#define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L
+#define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN__MASK 0x00000040L
+#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV__MASK 0x00010000L
+#define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV__MASK 0x00020000L
+#define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET__MASK 0x00040000L
+#define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET__MASK 0x00080000L
+#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT__MASK 0x00100000L
+#define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED__MASK 0x00200000L
+//GDC_RAS_LEAF3_CTRL
+#define GDC_RAS_LEAF3_CTRL__POISON_DET_EN__MASK 0x00000001L
+#define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L
+#define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN__MASK 0x00000004L
+#define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN__MASK 0x00000010L
+#define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L
+#define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN__MASK 0x00000040L
+#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV__MASK 0x00010000L
+#define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV__MASK 0x00020000L
+#define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET__MASK 0x00040000L
+#define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET__MASK 0x00080000L
+#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT__MASK 0x00100000L
+#define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED__MASK 0x00200000L
+//GDC_RAS_LEAF4_CTRL
+#define GDC_RAS_LEAF4_CTRL__POISON_DET_EN__MASK 0x00000001L
+#define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L
+#define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN__MASK 0x00000004L
+#define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN__MASK 0x00000010L
+#define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L
+#define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN__MASK 0x00000040L
+#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV__MASK 0x00010000L
+#define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV__MASK 0x00020000L
+#define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET__MASK 0x00040000L
+#define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET__MASK 0x00080000L
+#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT__MASK 0x00100000L
+#define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED__MASK 0x00200000L
+//GDC_RAS_LEAF5_CTRL
+#define GDC_RAS_LEAF5_CTRL__POISON_DET_EN__MASK 0x00000001L
+#define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L
+#define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN__MASK 0x00000004L
+#define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN__MASK 0x00000010L
+#define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L
+#define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN__MASK 0x00000040L
+#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV__MASK 0x00010000L
+#define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV__MASK 0x00020000L
+#define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET__MASK 0x00040000L
+#define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET__MASK 0x00080000L
+#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT__MASK 0x00100000L
+#define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED__MASK 0x00200000L
+
+
+// addressBlock: gdc_rst_GDCRST_DEC
+//SHUB_PF_FLR_RST
+#define SHUB_PF_FLR_RST__PF0_FLR_RST__MASK 0x00000001L
+#define SHUB_PF_FLR_RST__PF1_FLR_RST__MASK 0x00000002L
+#define SHUB_PF_FLR_RST__PF2_FLR_RST__MASK 0x00000004L
+#define SHUB_PF_FLR_RST__PF3_FLR_RST__MASK 0x00000008L
+#define SHUB_PF_FLR_RST__PF4_FLR_RST__MASK 0x00000010L
+#define SHUB_PF_FLR_RST__PF5_FLR_RST__MASK 0x00000020L
+#define SHUB_PF_FLR_RST__PF6_FLR_RST__MASK 0x00000040L
+#define SHUB_PF_FLR_RST__PF7_FLR_RST__MASK 0x00000080L
+//SHUB_GFX_DRV_MODE1_RST
+#define SHUB_GFX_DRV_MODE1_RST__GFX_DRV_MODE1_RST__MASK 0x00000001L
+//SHUB_LINK_RESET
+#define SHUB_LINK_RESET__LINK_RESET__MASK 0x00000001L
+//SHUB_PF0_VF_FLR_RST
+#define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__MASK 0x00000001L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__MASK 0x00000002L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__MASK 0x00000004L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__MASK 0x00000008L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__MASK 0x00000010L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__MASK 0x00000020L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__MASK 0x00000040L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__MASK 0x00000080L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__MASK 0x00000100L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__MASK 0x00000200L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__MASK 0x00000400L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__MASK 0x00000800L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__MASK 0x00001000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__MASK 0x00002000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__MASK 0x00004000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__MASK 0x00008000L
+#define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__MASK 0x80000000L
+//SHUB_HARD_RST_CTRL
+#define SHUB_HARD_RST_CTRL__COR_RESET_EN__MASK 0x00000001L
+#define SHUB_HARD_RST_CTRL__REG_RESET_EN__MASK 0x00000002L
+#define SHUB_HARD_RST_CTRL__STY_RESET_EN__MASK 0x00000004L
+#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__MASK 0x00000008L
+#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__MASK 0x00000010L
+//SHUB_SOFT_RST_CTRL
+#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__MASK 0x00000001L
+#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__MASK 0x00000002L
+#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__MASK 0x00000004L
+#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__MASK 0x00000008L
+#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__MASK 0x00000010L
+//SHUB_SDP_PORT_RST
+#define SHUB_SDP_PORT_RST__SDP_PORT_RST__MASK 0x00000001L
+
+
+// addressBlock: bif_bx_pf_SYSDEC
+//SBIOS_SCRATCH_0
+#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL
+//SBIOS_SCRATCH_1
+#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL
+//SBIOS_SCRATCH_2
+#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL
+//SBIOS_SCRATCH_3
+#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_0
+#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_1
+#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_2
+#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_3
+#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_4
+#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_5
+#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_6
+#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_7
+#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_8
+#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_9
+#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_10
+#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_11
+#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_12
+#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_13
+#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_14
+#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_15
+#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__MASK 0xFFFFFFFFL
+//BIF_RLC_INTR_CNTL
+#define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__MASK 0x00000001L
+#define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__MASK 0x00000002L
+#define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__MASK 0x00000004L
+#define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__MASK 0x00000008L
+//BIF_VCE_INTR_CNTL
+#define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__MASK 0x00000001L
+#define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__MASK 0x00000002L
+#define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__MASK 0x00000004L
+#define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__MASK 0x00000008L
+//BIF_UVD_INTR_CNTL
+#define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__MASK 0x00000001L
+#define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__MASK 0x00000002L
+#define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__MASK 0x00000004L
+#define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__MASK 0x00000008L
+//GFX_MMIOREG_CAM_ADDR0
+#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR0
+#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR1
+#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR1
+#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR2
+#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR2
+#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR3
+#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR3
+#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR4
+#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR4
+#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR5
+#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR5
+#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR6
+#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR6
+#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR7
+#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR7
+#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_CNTL
+#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__MASK 0x000000FFL
+//GFX_MMIOREG_CAM_ZERO_CPL
+#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__MASK 0xFFFFFFFFL
+//GFX_MMIOREG_CAM_ONE_CPL
+#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__MASK 0xFFFFFFFFL
+//GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
+#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__MASK 0xFFFFFFFFL
+
+
+// addressBlock: bif_bx_pf_SYSPFVFDEC
+//MM_INDEX
+#define MM_INDEX__MM_OFFSET__MASK 0x7FFFFFFFL
+#define MM_INDEX__MM_APER__MASK 0x80000000L
+//MM_DATA
+#define MM_DATA__MM_DATA__MASK 0xFFFFFFFFL
+//MM_INDEX_HI
+#define MM_INDEX_HI__MM_OFFSET_HI__MASK 0xFFFFFFFFL
+//SYSHUB_INDEX_OVLP
+#define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__MASK 0x003FFFFFL
+//SYSHUB_DATA_OVLP
+#define SYSHUB_DATA_OVLP__SYSHUB_DATA__MASK 0xFFFFFFFFL
+//PCIE_INDEX
+#define PCIE_INDEX__PCIE_INDEX__MASK 0xFFFFFFFFL
+//PCIE_DATA
+#define PCIE_DATA__PCIE_DATA__MASK 0xFFFFFFFFL
+//PCIE_INDEX2
+#define PCIE_INDEX2__PCIE_INDEX2__MASK 0xFFFFFFFFL
+//PCIE_DATA2
+#define PCIE_DATA2__PCIE_DATA2__MASK 0xFFFFFFFFL
+
+
+// addressBlock: rcc_dwn_BIFDEC1
+//DN_PCIE_RESERVED
+#define DN_PCIE_RESERVED__PCIE_RESERVED__MASK 0xFFFFFFFFL
+//DN_PCIE_SCRATCH
+#define DN_PCIE_SCRATCH__PCIE_SCRATCH__MASK 0xFFFFFFFFL
+//DN_PCIE_CNTL
+#define DN_PCIE_CNTL__HWINIT_WR_LOCK__MASK 0x00000001L
+#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__MASK 0x00000080L
+#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__MASK 0x40000000L
+//DN_PCIE_CONFIG_CNTL
+#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__MASK 0x06000000L
+//DN_PCIE_RX_CNTL2
+#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__MASK 0x70000000L
+//DN_PCIE_BUS_CNTL
+#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__MASK 0x00000080L
+#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__MASK 0x00000100L
+//DN_PCIE_CFG_CNTL
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__MASK 0x00000001L
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__MASK 0x00000002L
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__MASK 0x00000004L
+//DN_PCIE_STRAP_F0
+#define DN_PCIE_STRAP_F0__STRAP_F0_EN__MASK 0x00000001L
+#define DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__MASK 0x00020000L
+#define DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__MASK 0x00E00000L
+//DN_PCIE_STRAP_MISC
+#define DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__MASK 0x01000000L
+#define DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__MASK 0x20000000L
+//DN_PCIE_STRAP_MISC2
+#define DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__MASK 0x00000004L
+
+
+// addressBlock: rcc_dwnp_BIFDEC1
+//PCIEP_RESERVED
+#define PCIEP_RESERVED__PCIEP_RESERVED__MASK 0xFFFFFFFFL
+//PCIEP_SCRATCH
+#define PCIEP_SCRATCH__PCIEP_SCRATCH__MASK 0xFFFFFFFFL
+//PCIE_ERR_CNTL
+#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__MASK 0x00000001L
+#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__MASK 0x00000700L
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__MASK 0x00000800L
+#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__MASK 0x00020000L
+//PCIE_RX_CNTL
+#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__MASK 0x00000100L
+#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__MASK 0x00000200L
+#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__MASK 0x00100000L
+#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__MASK 0x00200000L
+#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__MASK 0x08000000L
+//PCIE_LC_SPEED_CNTL
+#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__MASK 0x00000001L
+#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__MASK 0x00000002L
+//PCIE_LC_CNTL2
+#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__MASK 0x08000000L
+//PCIEP_STRAP_MISC
+#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__MASK 0x00000400L
+//LTR_MSG_INFO_FROM_EP
+#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__MASK 0xFFFFFFFFL
+
+
+// addressBlock: rcc_ep_BIFDEC1
+//EP_PCIE_SCRATCH
+#define EP_PCIE_SCRATCH__PCIE_SCRATCH__MASK 0xFFFFFFFFL
+//EP_PCIE_CNTL
+#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS__MASK 0x00000080L
+#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__MASK 0x00000100L
+#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__MASK 0x40000000L
+//EP_PCIE_INT_CNTL
+#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__MASK 0x00000001L
+#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__MASK 0x00000002L
+#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__MASK 0x00000004L
+#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__MASK 0x00000008L
+#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__MASK 0x00000010L
+#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__MASK 0x00000040L
+//EP_PCIE_INT_STATUS
+#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__MASK 0x00000001L
+#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__MASK 0x00000002L
+#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__MASK 0x00000004L
+#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__MASK 0x00000008L
+#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__MASK 0x00000010L
+#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__MASK 0x00000040L
+//EP_PCIE_RX_CNTL2
+#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__MASK 0x00000001L
+//EP_PCIE_BUS_CNTL
+#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__MASK 0x00000080L
+//EP_PCIE_CFG_CNTL
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__MASK 0x00000001L
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__MASK 0x00000002L
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__MASK 0x00000004L
+//EP_PCIE_OBFF_CNTL
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__MASK 0x00000001L
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__MASK 0x00000002L
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__MASK 0x00000004L
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__MASK 0x00000008L
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__MASK 0x000000F0L
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__MASK 0x00000F00L
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__MASK 0x0000F000L
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__MASK 0x00010000L
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__MASK 0x00020000L
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__MASK 0x00040000L
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0__MASK 0x00080000L
+#define EP_PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__MASK 0x00F00000L
+//EP_PCIE_TX_LTR_CNTL
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__MASK 0x00000007L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__MASK 0x00000038L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__MASK 0x00000040L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__MASK 0x00000380L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__MASK 0x00001C00L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__MASK 0x00002000L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__MASK 0x00004000L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__MASK 0x00008000L
+#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__MASK 0x00010000L
+//EP_PCIE_STRAP_MISC
+#define EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__MASK 0x20000000L
+//EP_PCIE_STRAP_MISC2
+#define EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__MASK 0x00000010L
+//EP_PCIE_STRAP_PI
+//EP_PCIE_F0_DPA_CAP
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__MASK 0x00000300L
+#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__MASK 0x00003000L
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__MASK 0x00FF0000L
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__MASK 0xFF000000L
+//EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__MASK 0xFFL
+//EP_PCIE_F0_DPA_CNTL
+#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__MASK 0x001FL
+#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__MASK 0x0100L
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__MASK 0xFFL
+//EP_PCIE_PME_CONTROL
+#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__MASK 0x1FL
+//EP_PCIEP_RESERVED
+#define EP_PCIEP_RESERVED__PCIEP_RESERVED__MASK 0xFFFFFFFFL
+//EP_PCIE_TX_CNTL
+#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__MASK 0x00000C00L
+#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__MASK 0x00003000L
+#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__MASK 0x01000000L
+#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__MASK 0x02000000L
+#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__MASK 0x04000000L
+//EP_PCIE_TX_REQUESTER_ID
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__MASK 0x00000007L
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__MASK 0x000000F8L
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__MASK 0x0000FF00L
+//EP_PCIE_ERR_CNTL
+#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__MASK 0x00000001L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__MASK 0x00000700L
+#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__MASK 0x00020000L
+#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__MASK 0x00040000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__MASK 0x01000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__MASK 0x02000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__MASK 0x04000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__MASK 0x08000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__MASK 0x10000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__MASK 0x20000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__MASK 0x40000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__MASK 0x80000000L
+//EP_PCIE_RX_CNTL
+#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__MASK 0x00000100L
+#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__MASK 0x00000200L
+#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__MASK 0x00100000L
+#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__MASK 0x00200000L
+#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__MASK 0x00400000L
+#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__MASK 0x01000000L
+#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__MASK 0x02000000L
+#define EP_PCIE_RX_CNTL__RX_TPH_DIS__MASK 0x04000000L
+//EP_PCIE_LC_SPEED_CNTL
+#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__MASK 0x00000001L
+#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__MASK 0x00000002L
+
+
+// addressBlock: bif_bx_pf_BIFDEC1
+//BIF_MM_INDACCESS_CNTL
+#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__MASK 0x00000002L
+//BUS_CNTL
+#define BUS_CNTL__PMI_INT_DIS_EP__MASK 0x00000008L
+#define BUS_CNTL__PMI_INT_DIS_DN__MASK 0x00000010L
+#define BUS_CNTL__PMI_INT_DIS_SWUS__MASK 0x00000020L
+#define BUS_CNTL__VGA_REG_COHERENCY_DIS__MASK 0x00000040L
+#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__MASK 0x00000080L
+#define BUS_CNTL__SET_AZ_TC__MASK 0x00001C00L
+#define BUS_CNTL__SET_MC_TC__MASK 0x0000E000L
+#define BUS_CNTL__ZERO_BE_WR_EN__MASK 0x00010000L
+#define BUS_CNTL__ZERO_BE_RD_EN__MASK 0x00020000L
+#define BUS_CNTL__RD_STALL_IO_WR__MASK 0x00040000L
+#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__MASK 0x00080000L
+#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__MASK 0x00100000L
+#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__MASK 0x00200000L
+#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__MASK 0x00400000L
+#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__MASK 0x00800000L
+#define BUS_CNTL__UR_OVRD_FOR_ECRC_EN__MASK 0x01000000L
+//BIF_SCRATCH0
+#define BIF_SCRATCH0__BIF_SCRATCH0__MASK 0xFFFFFFFFL
+//BIF_SCRATCH1
+#define BIF_SCRATCH1__BIF_SCRATCH1__MASK 0xFFFFFFFFL
+//BX_RESET_EN
+#define BX_RESET_EN__COR_RESET_EN__MASK 0x00000001L
+#define BX_RESET_EN__REG_RESET_EN__MASK 0x00000002L
+#define BX_RESET_EN__STY_RESET_EN__MASK 0x00000004L
+#define BX_RESET_EN__FLR_TWICE_EN__MASK 0x00000100L
+#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__MASK 0x00010000L
+//MM_CFGREGS_CNTL
+#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__MASK 0x00000007L
+#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__MASK 0x000000C0L
+#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__MASK 0x80000000L
+//BX_RESET_CNTL
+#define BX_RESET_CNTL__LINK_TRAIN_EN__MASK 0x00000001L
+//INTERRUPT_CNTL
+#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__MASK 0x00000001L
+#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__MASK 0x00000002L
+#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__MASK 0x00000008L
+#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__MASK 0x000000F0L
+#define INTERRUPT_CNTL__GEN_IH_INT_EN__MASK 0x00000100L
+#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__MASK 0x00008000L
+//INTERRUPT_CNTL2
+#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__MASK 0xFFFFFFFFL
+//CLKREQB_PAD_CNTL
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__MASK 0x00000001L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__MASK 0x00000002L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__MASK 0x00000004L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__MASK 0x00000018L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__MASK 0x00000020L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__MASK 0x00000040L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__MASK 0x00000080L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__MASK 0x00000100L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__MASK 0x00000200L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__MASK 0x00000400L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__MASK 0x00000800L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__MASK 0x00001000L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__MASK 0x00002000L
+#define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER__MASK 0xFF000000L
+//CLKREQB_PERF_COUNTER
+#define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER__MASK 0xFFFFFFFFL
+//BIF_CLK_CTRL
+#define BIF_CLK_CTRL__BIF_XSTCLK_READY__MASK 0x00000001L
+#define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__MASK 0x00000002L
+//BIF_FEATURES_CONTROL_MISC
+#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__MASK 0x00000001L
+#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__MASK 0x00000002L
+#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__MASK 0x00000004L
+#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__MASK 0x00000008L
+#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__MASK 0x00000200L
+#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__MASK 0x00000400L
+#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__MASK 0x00000800L
+#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__MASK 0x00001000L
+#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__MASK 0x00002000L
+#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__MASK 0x00008000L
+#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__MASK 0x00020000L
+#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__MASK 0x00040000L
+#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__MASK 0x01000000L
+//BIF_DOORBELL_CNTL
+#define BIF_DOORBELL_CNTL__SELF_RING_DIS__MASK 0x00000001L
+#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__MASK 0x00000002L
+#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__MASK 0x00000004L
+#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__MASK 0x00000008L
+#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__MASK 0x00000010L
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__MASK 0x01000000L
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__MASK 0x02000000L
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__MASK 0x04000000L
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__MASK 0x08000000L
+//BIF_DOORBELL_INT_CNTL
+#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__MASK 0x00000001L
+#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__MASK 0x00000002L
+#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__MASK 0x00010000L
+#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__MASK 0x00020000L
+//BIF_SLVARB_MODE
+#define BIF_SLVARB_MODE__SLVARB_MODE__MASK 0x00000003L
+//BIF_FB_EN
+#define BIF_FB_EN__FB_READ_EN__MASK 0x00000001L
+#define BIF_FB_EN__FB_WRITE_EN__MASK 0x00000002L
+//BIF_BUSY_DELAY_CNTR
+#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__MASK 0x0000003FL
+//BIF_PERFMON_CNTL
+#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__MASK 0x00000001L
+#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__MASK 0x00000002L
+#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__MASK 0x00000004L
+#define BIF_PERFMON_CNTL__PERF_SEL0__MASK 0x00001F00L
+#define BIF_PERFMON_CNTL__PERF_SEL1__MASK 0x0003E000L
+//BIF_PERFCOUNTER0_RESULT
+#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__MASK 0xFFFFFFFFL
+//BIF_PERFCOUNTER1_RESULT
+#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__MASK 0xFFFFFFFFL
+//BIF_MST_TRANS_PENDING_VF
+#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__MASK 0x0000FFFFL
+//BIF_SLV_TRANS_PENDING_VF
+#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__MASK 0x0000FFFFL
+//BACO_CNTL
+#define BACO_CNTL__BACO_EN__MASK 0x00000001L
+#define BACO_CNTL__BACO_BIF_LCLK_SWITCH__MASK 0x00000002L
+#define BACO_CNTL__BACO_DUMMY_EN__MASK 0x00000004L
+#define BACO_CNTL__BACO_POWER_OFF__MASK 0x00000008L
+#define BACO_CNTL__BACO_DSTATE_BYPASS__MASK 0x00000020L
+#define BACO_CNTL__BACO_RST_INTR_MASK__MASK 0x00000040L
+#define BACO_CNTL__BACO_MODE__MASK 0x00000100L
+#define BACO_CNTL__RCU_BIF_CONFIG_DONE__MASK 0x00000200L
+#define BACO_CNTL__BACO_AUTO_EXIT__MASK 0x80000000L
+//BIF_BACO_EXIT_TIME0
+#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__MASK 0x000FFFFFL
+//BIF_BACO_EXIT_TIMER1
+#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__MASK 0x000FFFFFL
+#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__MASK 0x04000000L
+#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__MASK 0x08000000L
+#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__MASK 0x10000000L
+#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__MASK 0x60000000L
+#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__MASK 0x80000000L
+//BIF_BACO_EXIT_TIMER2
+#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__MASK 0x000FFFFFL
+//BIF_BACO_EXIT_TIMER3
+#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__MASK 0x000FFFFFL
+//BIF_BACO_EXIT_TIMER4
+#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__MASK 0x000FFFFFL
+//MEM_TYPE_CNTL
+#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__MASK 0x00000001L
+//SMU_BIF_VDDGFX_PWR_STATUS
+#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__MASK 0x00000001L
+//BIF_VDDGFX_GFX0_LOWER
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__MASK 0x0003FFFCL
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__MASK 0x40000000L
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__MASK 0x80000000L
+//BIF_VDDGFX_GFX0_UPPER
+#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__MASK 0x0003FFFCL
+//BIF_VDDGFX_GFX1_LOWER
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__MASK 0x0003FFFCL
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__MASK 0x40000000L
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__MASK 0x80000000L
+//BIF_VDDGFX_GFX1_UPPER
+#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__MASK 0x0003FFFCL
+//BIF_VDDGFX_GFX2_LOWER
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__MASK 0x0003FFFCL
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__MASK 0x40000000L
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__MASK 0x80000000L
+//BIF_VDDGFX_GFX2_UPPER
+#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__MASK 0x0003FFFCL
+//BIF_VDDGFX_GFX3_LOWER
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__MASK 0x0003FFFCL
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__MASK 0x40000000L
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__MASK 0x80000000L
+//BIF_VDDGFX_GFX3_UPPER
+#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__MASK 0x0003FFFCL
+//BIF_VDDGFX_GFX4_LOWER
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__MASK 0x0003FFFCL
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__MASK 0x40000000L
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__MASK 0x80000000L
+//BIF_VDDGFX_GFX4_UPPER
+#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__MASK 0x0003FFFCL
+//BIF_VDDGFX_GFX5_LOWER
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__MASK 0x0003FFFCL
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__MASK 0x40000000L
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__MASK 0x80000000L
+//BIF_VDDGFX_GFX5_UPPER
+#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__MASK 0x0003FFFCL
+//BIF_VDDGFX_RSV1_LOWER
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__MASK 0x0003FFFCL
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__MASK 0x40000000L
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__MASK 0x80000000L
+//BIF_VDDGFX_RSV1_UPPER
+#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__MASK 0x0003FFFCL
+//BIF_VDDGFX_RSV2_LOWER
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__MASK 0x0003FFFCL
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__MASK 0x40000000L
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__MASK 0x80000000L
+//BIF_VDDGFX_RSV2_UPPER
+#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__MASK 0x0003FFFCL
+//BIF_VDDGFX_RSV3_LOWER
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__MASK 0x0003FFFCL
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__MASK 0x40000000L
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__MASK 0x80000000L
+//BIF_VDDGFX_RSV3_UPPER
+#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__MASK 0x0003FFFCL
+//BIF_VDDGFX_RSV4_LOWER
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__MASK 0x0003FFFCL
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__MASK 0x40000000L
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__MASK 0x80000000L
+//BIF_VDDGFX_RSV4_UPPER
+#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__MASK 0x0003FFFCL
+//BIF_VDDGFX_FB_CMP
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__MASK 0x00000001L
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__MASK 0x00000002L
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__MASK 0x00000004L
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__MASK 0x00000008L
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__MASK 0x00000010L
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__MASK 0x00000020L
+//BIF_DOORBELL_GBLAPER1_LOWER
+#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__MASK 0x00000FFCL
+#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__MASK 0x80000000L
+//BIF_DOORBELL_GBLAPER1_UPPER
+#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__MASK 0x00000FFCL
+//BIF_DOORBELL_GBLAPER2_LOWER
+#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__MASK 0x00000FFCL
+#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__MASK 0x80000000L
+//BIF_DOORBELL_GBLAPER2_UPPER
+#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__MASK 0x00000FFCL
+//REMAP_HDP_MEM_FLUSH_CNTL
+#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__MASK 0x0007FFFCL
+//REMAP_HDP_REG_FLUSH_CNTL
+#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__MASK 0x0007FFFCL
+//BIF_RB_CNTL
+#define BIF_RB_CNTL__RB_ENABLE__MASK 0x00000001L
+#define BIF_RB_CNTL__RB_SIZE__MASK 0x0000003EL
+#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__MASK 0x00000100L
+#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__MASK 0x00003E00L
+#define BIF_RB_CNTL__BIF_RB_TRAN__MASK 0x00020000L
+#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__MASK 0x80000000L
+//BIF_RB_BASE
+#define BIF_RB_BASE__ADDR__MASK 0xFFFFFFFFL
+//BIF_RB_RPTR
+#define BIF_RB_RPTR__OFFSET__MASK 0x0003FFFCL
+//BIF_RB_WPTR
+#define BIF_RB_WPTR__BIF_RB_OVERFLOW__MASK 0x00000001L
+#define BIF_RB_WPTR__OFFSET__MASK 0x0003FFFCL
+//BIF_RB_WPTR_ADDR_HI
+#define BIF_RB_WPTR_ADDR_HI__ADDR__MASK 0x000000FFL
+//BIF_RB_WPTR_ADDR_LO
+#define BIF_RB_WPTR_ADDR_LO__ADDR__MASK 0xFFFFFFFCL
+//MAILBOX_INDEX
+#define MAILBOX_INDEX__MAILBOX_INDEX__MASK 0x0000001FL
+//BIF_GPUIOV_RESET_NOTIFICATION
+#define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__MASK 0xFFFFFFFFL
+//BIF_UVD_GPUIOV_CFG_SIZE
+#define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__MASK 0x0000000FL
+//BIF_VCE_GPUIOV_CFG_SIZE
+#define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__MASK 0x0000000FL
+//BIF_GFX_SDMA_GPUIOV_CFG_SIZE
+#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__MASK 0x0000000FL
+//BIF_GMI_WRR_WEIGHT
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT__MASK 0x000000FFL
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT__MASK 0x0000FF00L
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT__MASK 0x00FF0000L
+//NBIF_STRAP_WRITE_CTRL
+#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__MASK 0x00000001L
+//BIF_PERSTB_PAD_CNTL
+#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__MASK 0x0000FFFFL
+//BIF_PX_EN_PAD_CNTL
+#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__MASK 0x000000FFL
+//BIF_REFPADKIN_PAD_CNTL
+#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__MASK 0x000000FFL
+//BIF_CLKREQB_PAD_CNTL
+#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__MASK 0x00FFFFFFL
+
+
+// addressBlock: rcc_pf_0_BIFDEC1
+//RCC_BACO_CNTL_MISC
+#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__MASK 0x00000001L
+#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__MASK 0x00000002L
+//RCC_RESET_EN
+#define RCC_RESET_EN__DB_APER_RESET_EN__MASK 0x00008000L
+//RCC_VDM_SUPPORT
+#define RCC_VDM_SUPPORT__MCTP_SUPPORT__MASK 0x00000001L
+#define RCC_VDM_SUPPORT__AMPTP_SUPPORT__MASK 0x00000002L
+#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__MASK 0x00000004L
+#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__MASK 0x00000008L
+#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__MASK 0x00000010L
+//RCC_PEER_REG_RANGE0
+#define RCC_PEER_REG_RANGE0__START_ADDR__MASK 0x0000FFFFL
+#define RCC_PEER_REG_RANGE0__END_ADDR__MASK 0xFFFF0000L
+//RCC_PEER_REG_RANGE1
+#define RCC_PEER_REG_RANGE1__START_ADDR__MASK 0x0000FFFFL
+#define RCC_PEER_REG_RANGE1__END_ADDR__MASK 0xFFFF0000L
+//RCC_BUS_CNTL
+#define RCC_BUS_CNTL__PMI_IO_DIS__MASK 0x00000004L
+#define RCC_BUS_CNTL__PMI_MEM_DIS__MASK 0x00000008L
+#define RCC_BUS_CNTL__PMI_BM_DIS__MASK 0x00000010L
+#define RCC_BUS_CNTL__PMI_IO_DIS_DN__MASK 0x00000020L
+#define RCC_BUS_CNTL__PMI_MEM_DIS_DN__MASK 0x00000040L
+#define RCC_BUS_CNTL__PMI_IO_DIS_UP__MASK 0x00000080L
+#define RCC_BUS_CNTL__PMI_MEM_DIS_UP__MASK 0x00000100L
+#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__MASK 0x00001000L
+#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__MASK 0x00002000L
+#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__MASK 0x00010000L
+#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__MASK 0x00020000L
+#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__MASK 0x00040000L
+#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__MASK 0x00080000L
+#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__MASK 0x00100000L
+#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__MASK 0x00200000L
+#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__MASK 0x01000000L
+#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__MASK 0x0E000000L
+#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__MASK 0x10000000L
+#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__MASK 0xE0000000L
+//RCC_CONFIG_CNTL
+#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__MASK 0x00000001L
+#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__MASK 0x00000004L
+#define RCC_CONFIG_CNTL__GRPH_ADRSEL__MASK 0x00000018L
+//RCC_CONFIG_F0_BASE
+#define RCC_CONFIG_F0_BASE__F0_BASE__MASK 0xFFFFFFFFL
+//RCC_CONFIG_APER_SIZE
+#define RCC_CONFIG_APER_SIZE__APER_SIZE__MASK 0xFFFFFFFFL
+//RCC_CONFIG_REG_APER_SIZE
+#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__MASK 0x000FFFFFL
+//RCC_XDMA_LO
+#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__MASK 0x1FFFFFFFL
+#define RCC_XDMA_LO__BIF_XDMA_APER_EN__MASK 0x80000000L
+//RCC_XDMA_HI
+#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__MASK 0x1FFFFFFFL
+//RCC_FEATURES_CONTROL_MISC
+#define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__MASK 0x00000010L
+#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__MASK 0x00000020L
+#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__MASK 0x00000040L
+#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__MASK 0x00000100L
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__MASK 0x00000200L
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__MASK 0x00000400L
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__MASK 0x00000800L
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__MASK 0x00001000L
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__MASK 0x00002000L
+#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__MASK 0x00004000L
+#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__MASK 0x00008000L
+#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__MASK 0x00010000L
+#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__MASK 0x00020000L
+#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__MASK 0x00040000L
+//RCC_BUSNUM_CNTL1
+#define RCC_BUSNUM_CNTL1__ID_MASK__MASK 0x000000FFL
+//RCC_BUSNUM_LIST0
+#define RCC_BUSNUM_LIST0__ID0__MASK 0x000000FFL
+#define RCC_BUSNUM_LIST0__ID1__MASK 0x0000FF00L
+#define RCC_BUSNUM_LIST0__ID2__MASK 0x00FF0000L
+#define RCC_BUSNUM_LIST0__ID3__MASK 0xFF000000L
+//RCC_BUSNUM_LIST1
+#define RCC_BUSNUM_LIST1__ID4__MASK 0x000000FFL
+#define RCC_BUSNUM_LIST1__ID5__MASK 0x0000FF00L
+#define RCC_BUSNUM_LIST1__ID6__MASK 0x00FF0000L
+#define RCC_BUSNUM_LIST1__ID7__MASK 0xFF000000L
+//RCC_BUSNUM_CNTL2
+#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__MASK 0x000000FFL
+#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__MASK 0x00000100L
+#define RCC_BUSNUM_CNTL2__HDPREG_CNTL__MASK 0x00010000L
+#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__MASK 0x00020000L
+//RCC_CAPTURE_HOST_BUSNUM
+#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__MASK 0x00000001L
+//RCC_HOST_BUSNUM
+#define RCC_HOST_BUSNUM__HOST_ID__MASK 0x0000FFFFL
+//RCC_PEER0_FB_OFFSET_HI
+#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__MASK 0x000FFFFFL
+//RCC_PEER0_FB_OFFSET_LO
+#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__MASK 0x000FFFFFL
+#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__MASK 0x80000000L
+//RCC_PEER1_FB_OFFSET_HI
+#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__MASK 0x000FFFFFL
+//RCC_PEER1_FB_OFFSET_LO
+#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__MASK 0x000FFFFFL
+#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__MASK 0x80000000L
+//RCC_PEER2_FB_OFFSET_HI
+#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__MASK 0x000FFFFFL
+//RCC_PEER2_FB_OFFSET_LO
+#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__MASK 0x000FFFFFL
+#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__MASK 0x80000000L
+//RCC_PEER3_FB_OFFSET_HI
+#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__MASK 0x000FFFFFL
+//RCC_PEER3_FB_OFFSET_LO
+#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__MASK 0x000FFFFFL
+#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__MASK 0x80000000L
+//RCC_DEVFUNCNUM_LIST0
+#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__MASK 0x000000FFL
+#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__MASK 0x0000FF00L
+#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__MASK 0x00FF0000L
+#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__MASK 0xFF000000L
+//RCC_DEVFUNCNUM_LIST1
+#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__MASK 0x000000FFL
+#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__MASK 0x0000FF00L
+#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__MASK 0x00FF0000L
+#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__MASK 0xFF000000L
+//RCC_DEV0_LINK_CNTL
+#define RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__MASK 0x00000001L
+#define RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__MASK 0x00000100L
+//RCC_CMN_LINK_CNTL
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__MASK 0x00000001L
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__MASK 0x00000002L
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__MASK 0x00000004L
+#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__MASK 0x00000008L
+//RCC_EP_REQUESTERID_RESTORE
+#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__MASK 0x000000FFL
+#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__MASK 0x00001F00L
+//RCC_LTR_LSWITCH_CNTL
+#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__MASK 0x000003FFL
+//RCC_MH_ARB_CNTL
+#define RCC_MH_ARB_CNTL__MH_ARB_MODE__MASK 0x00000001L
+#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__MASK 0x00007FFEL
+
+
+// addressBlock: rcc_pf_0_BIFDEC2
+//GFXMSIX_VECT0_ADDR_LO
+#define GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//GFXMSIX_VECT0_ADDR_HI
+#define GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//GFXMSIX_VECT0_MSG_DATA
+#define GFXMSIX_VECT0_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//GFXMSIX_VECT0_CONTROL
+#define GFXMSIX_VECT0_CONTROL__MASK_BIT__MASK 0x00000001L
+//GFXMSIX_VECT1_ADDR_LO
+#define GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//GFXMSIX_VECT1_ADDR_HI
+#define GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//GFXMSIX_VECT1_MSG_DATA
+#define GFXMSIX_VECT1_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//GFXMSIX_VECT1_CONTROL
+#define GFXMSIX_VECT1_CONTROL__MASK_BIT__MASK 0x00000001L
+//GFXMSIX_VECT2_ADDR_LO
+#define GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//GFXMSIX_VECT2_ADDR_HI
+#define GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//GFXMSIX_VECT2_MSG_DATA
+#define GFXMSIX_VECT2_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//GFXMSIX_VECT2_CONTROL
+#define GFXMSIX_VECT2_CONTROL__MASK_BIT__MASK 0x00000001L
+//GFXMSIX_PBA
+#define GFXMSIX_PBA__MSIX_PENDING_BITS_0__MASK 0x00000001L
+#define GFXMSIX_PBA__MSIX_PENDING_BITS_1__MASK 0x00000002L
+#define GFXMSIX_PBA__MSIX_PENDING_BITS_2__MASK 0x00000004L
+
+
+// addressBlock: rcc_strap_BIFDEC1
+//RCC_DEV0_PORT_STRAP0
+#define RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__MASK 0x00000002L
+#define RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__MASK 0x00000004L
+#define RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__MASK 0x00000008L
+#define RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__MASK 0x00000010L
+#define RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__MASK 0x001FFFE0L
+#define RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__MASK 0x00E00000L
+#define RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__MASK 0x01000000L
+#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__MASK 0x0E000000L
+#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__MASK 0x70000000L
+#define RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__MASK 0x80000000L
+//RCC_DEV0_PORT_STRAP1
+#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__MASK 0x0000FFFFL
+#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__MASK 0xFFFF0000L
+//RCC_DEV0_PORT_STRAP2
+#define RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__MASK 0x00000001L
+#define RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__MASK 0x00000002L
+#define RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__MASK 0x00000004L
+#define RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__MASK 0x00000008L
+#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__MASK 0x00000010L
+#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__MASK 0x00000020L
+#define RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__MASK 0x00000040L
+#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__MASK 0x00000080L
+#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__MASK 0x00000100L
+#define RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__MASK 0x00000E00L
+#define RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__MASK 0x00001000L
+#define RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__MASK 0x00002000L
+#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__MASK 0x00004000L
+#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__MASK 0x00008000L
+#define RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__MASK 0x00010000L
+#define RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__MASK 0x00060000L
+#define RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__MASK 0x00080000L
+#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__MASK 0x00700000L
+#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__MASK 0x03800000L
+#define RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__MASK 0x1C000000L
+#define RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__MASK 0xE0000000L
+//RCC_DEV0_PORT_STRAP3
+#define RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__MASK 0x00000001L
+#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__MASK 0x00000002L
+#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__MASK 0x00000004L
+#define RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__MASK 0x00000038L
+#define RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__MASK 0x00000040L
+#define RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__MASK 0x00000080L
+#define RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__MASK 0x00000100L
+#define RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__MASK 0x00000600L
+#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x00003800L
+#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__MASK 0x0003C000L
+#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x001C0000L
+#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__MASK 0x01E00000L
+#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__MASK 0x06000000L
+#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__MASK 0x18000000L
+#define RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__MASK 0x20000000L
+#define RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__MASK 0x40000000L
+#define RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__MASK 0x80000000L
+//RCC_DEV0_PORT_STRAP4
+#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__MASK 0x000000FFL
+#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__MASK 0x0000FF00L
+#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__MASK 0x00FF0000L
+#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__MASK 0xFF000000L
+//RCC_DEV0_PORT_STRAP5
+#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__MASK 0x000000FFL
+#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__MASK 0x0000FF00L
+#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__MASK 0x00010000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__MASK 0x00020000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__MASK 0x00040000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__MASK 0x00080000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__MASK 0x00100000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__MASK 0x00200000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__MASK 0x00800000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__MASK 0x01000000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__MASK 0x02000000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__MASK 0x04000000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__MASK 0x08000000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__MASK 0x10000000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__MASK 0x20000000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__MASK 0x40000000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__MASK 0x80000000L
+//RCC_DEV0_PORT_STRAP6
+#define RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__MASK 0x00000001L
+#define RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__MASK 0x00000002L
+//RCC_DEV0_PORT_STRAP7
+#define RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__MASK 0x000000FFL
+#define RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__MASK 0x00000F00L
+#define RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__MASK 0x0000F000L
+#define RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__MASK 0x00FF0000L
+#define RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__MASK 0x1F000000L
+#define RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__MASK 0xE0000000L
+//RCC_DEV0_EPF0_STRAP0
+#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL
+#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__MASK 0x000F0000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__MASK 0x00F00000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__MASK 0x0F000000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__MASK 0x10000000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__MASK 0x20000000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__MASK 0x40000000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__MASK 0x80000000L
+//RCC_DEV0_EPF0_STRAP1
+#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL
+#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__MASK 0xFFFF0000L
+//RCC_DEV0_EPF0_STRAP13
+#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__MASK 0x000000FFL
+#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__MASK 0x0000FF00L
+#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__MASK 0x00FF0000L
+//RCC_DEV0_EPF0_STRAP2
+#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__MASK 0x00000001L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__MASK 0x0000003EL
+#define RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__MASK 0x00000040L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__MASK 0x00000080L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__MASK 0x00000100L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__MASK 0x00003E00L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__MASK 0x00004000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__MASK 0x00008000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__MASK 0x00010000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__MASK 0x00020000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__MASK 0x00040000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__MASK 0x00100000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__MASK 0x00200000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__MASK 0x00400000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__MASK 0x00800000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__MASK 0x07000000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__MASK 0x08000000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__MASK 0x10000000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__MASK 0x20000000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__MASK 0x40000000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__MASK 0x80000000L
+//RCC_DEV0_EPF0_STRAP3
+#define RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__MASK 0x00000001L
+#define RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__MASK 0x00000002L
+#define RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__MASK 0x0003FFFCL
+#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__MASK 0x00040000L
+#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__MASK 0x00080000L
+#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__MASK 0x00100000L
+#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__MASK 0x00E00000L
+#define RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__MASK 0x01000000L
+#define RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__MASK 0x02000000L
+#define RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__MASK 0x04000000L
+#define RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__MASK 0x08000000L
+//RCC_DEV0_EPF0_STRAP4
+#define RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__MASK 0x000FFFFFL
+#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__MASK 0x00100000L
+#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__MASK 0x00200000L
+#define RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__MASK 0x00400000L
+#define RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__MASK 0x0F800000L
+#define RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__MASK 0x70000000L
+#define RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__MASK 0x80000000L
+//RCC_DEV0_EPF0_STRAP5
+#define RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__MASK 0x0000FFFFL
+//RCC_DEV0_EPF0_STRAP8
+#define RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__MASK 0x00000001L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00000006L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__MASK 0x00000008L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__MASK 0x00000010L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__MASK 0x00000060L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__MASK 0x00000080L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__MASK 0x00000100L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__MASK 0x00000E00L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__MASK 0x00003000L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__MASK 0x0000C000L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00070000L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__MASK 0x00380000L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__MASK 0x00C00000L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__MASK 0x01000000L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__MASK 0x02000000L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__MASK 0x04000000L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__MASK 0x38000000L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__MASK 0xC0000000L
+//RCC_DEV0_EPF0_STRAP9
+//RCC_DEV0_EPF1_STRAP0
+#define RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__MASK 0x0000FFFFL
+#define RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__MASK 0x000F0000L
+#define RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__MASK 0x00F00000L
+#define RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__MASK 0x10000000L
+#define RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__MASK 0x20000000L
+#define RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__MASK 0x40000000L
+#define RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__MASK 0x80000000L
+//RCC_DEV0_EPF1_STRAP10
+#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__MASK 0x00000001L
+#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL
+//RCC_DEV0_EPF1_STRAP11
+#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__MASK 0x00000001L
+#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL
+//RCC_DEV0_EPF1_STRAP12
+#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__MASK 0x00000001L
+#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL
+//RCC_DEV0_EPF1_STRAP13
+#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__MASK 0x000000FFL
+#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__MASK 0x0000FF00L
+#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__MASK 0x00FF0000L
+//RCC_DEV0_EPF1_STRAP2
+#define RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__MASK 0x00000080L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__MASK 0x00000100L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__MASK 0x00004000L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__MASK 0x00010000L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__MASK 0x00020000L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__MASK 0x00040000L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__MASK 0x00100000L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__MASK 0x00200000L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__MASK 0x00400000L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__MASK 0x00800000L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__MASK 0x07000000L
+//RCC_DEV0_EPF1_STRAP3
+#define RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__MASK 0x00000001L
+#define RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__MASK 0x00000002L
+#define RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__MASK 0x0003FFFCL
+#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__MASK 0x00040000L
+#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__MASK 0x00080000L
+#define RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__MASK 0x00100000L
+#define RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__MASK 0x01000000L
+#define RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__MASK 0x02000000L
+#define RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__MASK 0x04000000L
+#define RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__MASK 0x08000000L
+//RCC_DEV0_EPF1_STRAP4
+#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__MASK 0x00100000L
+#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__MASK 0x00200000L
+#define RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__MASK 0x00400000L
+#define RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__MASK 0x0F800000L
+#define RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__MASK 0x70000000L
+#define RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__MASK 0x80000000L
+//RCC_DEV0_EPF1_STRAP5
+#define RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__MASK 0x0000FFFFL
+//RCC_DEV0_EPF1_STRAP6
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__MASK 0x00000001L
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000002L
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__MASK 0x00000004L
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__MASK 0x00000070L
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__MASK 0x00000100L
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000200L
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__MASK 0x00010000L
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__MASK 0x00020000L
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__MASK 0x01000000L
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__MASK 0x02000000L
+//RCC_DEV0_EPF1_STRAP7
+#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__MASK 0x00000001L
+#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__MASK 0x0000001EL
+
+
+// addressBlock: bif_bx_pf_BIFPFVFDEC1
+//BIF_BME_STATUS
+#define BIF_BME_STATUS__DMA_ON_BME_LOW__MASK 0x00000001L
+#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__MASK 0x00010000L
+//BIF_ATOMIC_ERR_LOG
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__MASK 0x00020000L
+//DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__MASK 0xFFFFFFFFL
+//DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__MASK 0xFFFFFFFFL
+//DOORBELL_SELFRING_GPA_APER_CNTL
+#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__MASK 0x00000001L
+#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__MASK 0x0000FF00L
+//HDP_REG_COHERENCY_FLUSH_CNTL
+#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__MASK 0x00000001L
+//HDP_MEM_COHERENCY_FLUSH_CNTL
+#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__MASK 0x00000001L
+//GPU_HDP_FLUSH_REQ
+#define GPU_HDP_FLUSH_REQ__CP0__MASK 0x00000001L
+#define GPU_HDP_FLUSH_REQ__CP1__MASK 0x00000002L
+#define GPU_HDP_FLUSH_REQ__CP2__MASK 0x00000004L
+#define GPU_HDP_FLUSH_REQ__CP3__MASK 0x00000008L
+#define GPU_HDP_FLUSH_REQ__CP4__MASK 0x00000010L
+#define GPU_HDP_FLUSH_REQ__CP5__MASK 0x00000020L
+#define GPU_HDP_FLUSH_REQ__CP6__MASK 0x00000040L
+#define GPU_HDP_FLUSH_REQ__CP7__MASK 0x00000080L
+#define GPU_HDP_FLUSH_REQ__CP8__MASK 0x00000100L
+#define GPU_HDP_FLUSH_REQ__CP9__MASK 0x00000200L
+#define GPU_HDP_FLUSH_REQ__SDMA0__MASK 0x00000400L
+#define GPU_HDP_FLUSH_REQ__SDMA1__MASK 0x00000800L
+//GPU_HDP_FLUSH_DONE
+#define GPU_HDP_FLUSH_DONE__CP0__MASK 0x00000001L
+#define GPU_HDP_FLUSH_DONE__CP1__MASK 0x00000002L
+#define GPU_HDP_FLUSH_DONE__CP2__MASK 0x00000004L
+#define GPU_HDP_FLUSH_DONE__CP3__MASK 0x00000008L
+#define GPU_HDP_FLUSH_DONE__CP4__MASK 0x00000010L
+#define GPU_HDP_FLUSH_DONE__CP5__MASK 0x00000020L
+#define GPU_HDP_FLUSH_DONE__CP6__MASK 0x00000040L
+#define GPU_HDP_FLUSH_DONE__CP7__MASK 0x00000080L
+#define GPU_HDP_FLUSH_DONE__CP8__MASK 0x00000100L
+#define GPU_HDP_FLUSH_DONE__CP9__MASK 0x00000200L
+#define GPU_HDP_FLUSH_DONE__SDMA0__MASK 0x00000400L
+#define GPU_HDP_FLUSH_DONE__SDMA1__MASK 0x00000800L
+//BIF_TRANS_PENDING
+#define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__MASK 0x00000001L
+#define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__MASK 0x00000002L
+//MAILBOX_MSGBUF_TRN_DW0
+#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__MASK 0xFFFFFFFFL
+//MAILBOX_MSGBUF_TRN_DW1
+#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__MASK 0xFFFFFFFFL
+//MAILBOX_MSGBUF_TRN_DW2
+#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__MASK 0xFFFFFFFFL
+//MAILBOX_MSGBUF_TRN_DW3
+#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__MASK 0xFFFFFFFFL
+//MAILBOX_MSGBUF_RCV_DW0
+#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__MASK 0xFFFFFFFFL
+//MAILBOX_MSGBUF_RCV_DW1
+#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__MASK 0xFFFFFFFFL
+//MAILBOX_MSGBUF_RCV_DW2
+#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__MASK 0xFFFFFFFFL
+//MAILBOX_MSGBUF_RCV_DW3
+#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__MASK 0xFFFFFFFFL
+//MAILBOX_CONTROL
+#define MAILBOX_CONTROL__TRN_MSG_VALID__MASK 0x00000001L
+#define MAILBOX_CONTROL__TRN_MSG_ACK__MASK 0x00000002L
+#define MAILBOX_CONTROL__RCV_MSG_VALID__MASK 0x00000100L
+#define MAILBOX_CONTROL__RCV_MSG_ACK__MASK 0x00000200L
+//MAILBOX_INT_CNTL
+#define MAILBOX_INT_CNTL__VALID_INT_EN__MASK 0x00000001L
+#define MAILBOX_INT_CNTL__ACK_INT_EN__MASK 0x00000002L
+//BIF_VMHV_MAILBOX
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__MASK 0x00000001L
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__MASK 0x00000002L
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__MASK 0x00000F00L
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__MASK 0x00008000L
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__MASK 0x000F0000L
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__MASK 0x00800000L
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__MASK 0x01000000L
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__MASK 0x02000000L
+
+
+// addressBlock: rcc_pf_0_BIFPFVFDEC1
+//RCC_DOORBELL_APER_EN
+#define RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__MASK 0x00000001L
+//RCC_CONFIG_MEMSIZE
+#define RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__MASK 0xFFFFFFFFL
+//RCC_CONFIG_RESERVED
+#define RCC_CONFIG_RESERVED__CONFIG_RESERVED__MASK 0xFFFFFFFFL
+//RCC_IOV_FUNC_IDENTIFIER
+#define RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__MASK 0x00000001L
+#define RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__MASK 0x80000000L
+
+
+// addressBlock: syshub_mmreg_ind_syshubdec
+//SYSHUB_INDEX
+#define SYSHUB_INDEX__INDEX__MASK 0xFFFFFFFFL
+//SYSHUB_DATA
+#define SYSHUB_DATA__DATA__MASK 0xFFFFFFFFL
+
+
+// addressBlock: rcc_strap_rcc_strap_internal
+//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__MASK 0x00000002L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__MASK 0x00000004L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__MASK 0x00000008L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__MASK 0x00000010L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__MASK 0x001FFFE0L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__MASK 0x00E00000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__MASK 0x01000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__MASK 0x0E000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__MASK 0x70000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__MASK 0x80000000L
+//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__MASK 0x0000FFFFL
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__MASK 0xFFFF0000L
+//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__MASK 0x00000001L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__MASK 0x00000002L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__MASK 0x00000004L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__MASK 0x00000008L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__MASK 0x00000010L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__MASK 0x00000020L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__MASK 0x00000040L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__MASK 0x00000080L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__MASK 0x00000100L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__MASK 0x00000E00L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__MASK 0x00001000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__MASK 0x00002000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__MASK 0x00004000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__MASK 0x00008000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__MASK 0x00010000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__MASK 0x00060000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__MASK 0x00080000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__MASK 0x00700000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__MASK 0x03800000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__MASK 0x1C000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__MASK 0xE0000000L
+//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__MASK 0x00000001L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__MASK 0x00000002L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__MASK 0x00000004L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__MASK 0x00000038L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__MASK 0x00000040L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__MASK 0x00000080L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__MASK 0x00000100L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__MASK 0x00000600L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x00003800L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__MASK 0x0003C000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x001C0000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__MASK 0x01E00000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__MASK 0x06000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__MASK 0x18000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__MASK 0x20000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__MASK 0x40000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__MASK 0x80000000L
+//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__MASK 0x000000FFL
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__MASK 0x0000FF00L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__MASK 0x00FF0000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__MASK 0xFF000000L
+//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__MASK 0x000000FFL
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__MASK 0x0000FF00L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__MASK 0x00010000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__MASK 0x00020000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__MASK 0x00040000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__MASK 0x00080000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__MASK 0x00100000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__MASK 0x00200000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__MASK 0x00800000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__MASK 0x01000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__MASK 0x02000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__MASK 0x04000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__MASK 0x08000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__MASK 0x10000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__MASK 0x20000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__MASK 0x40000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__MASK 0x80000000L
+//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__MASK 0x00000001L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__MASK 0x00000002L
+//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__MASK 0x000000FFL
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__MASK 0x00000F00L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__MASK 0x0000F000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__MASK 0x00FF0000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__MASK 0x1F000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__MASK 0xE0000000L
+//RCC_DEV1_PORT_STRAP0
+#define RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1__MASK 0x00000002L
+#define RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1__MASK 0x00000004L
+#define RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1__MASK 0x00000008L
+#define RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1__MASK 0x00000010L
+#define RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1__MASK 0x001FFFE0L
+#define RCC_DEV1_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV1__MASK 0x00E00000L
+#define RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1__MASK 0x01000000L
+#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1__MASK 0x0E000000L
+#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1__MASK 0x70000000L
+#define RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1__MASK 0x80000000L
+//RCC_DEV1_PORT_STRAP1
+#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1__MASK 0x0000FFFFL
+#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1__MASK 0xFFFF0000L
+//RCC_DEV1_PORT_STRAP2
+#define RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1__MASK 0x00000001L
+#define RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1__MASK 0x00000002L
+#define RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1__MASK 0x00000004L
+#define RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1__MASK 0x00000008L
+#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1__MASK 0x00000010L
+#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV1__MASK 0x00000020L
+#define RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1__MASK 0x00000040L
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1__MASK 0x00000080L
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1__MASK 0x00000100L
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1__MASK 0x00000E00L
+#define RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1__MASK 0x00001000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1__MASK 0x00002000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1__MASK 0x00004000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1__MASK 0x00008000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1__MASK 0x00010000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1__MASK 0x00060000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV1__MASK 0x00080000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1__MASK 0x00700000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1__MASK 0x03800000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1__MASK 0x1C000000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1__MASK 0xE0000000L
+//RCC_DEV1_PORT_STRAP3
+#define RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1__MASK 0x00000001L
+#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1__MASK 0x00000002L
+#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1__MASK 0x00000004L
+#define RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1__MASK 0x00000038L
+#define RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1__MASK 0x00000040L
+#define RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1__MASK 0x00000080L
+#define RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1__MASK 0x00000100L
+#define RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1__MASK 0x00000600L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1__MASK 0x00003800L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1__MASK 0x0003C000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1__MASK 0x001C0000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1__MASK 0x01E00000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1__MASK 0x06000000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1__MASK 0x18000000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1__MASK 0x20000000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV1__MASK 0x40000000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1__MASK 0x80000000L
+//RCC_DEV1_PORT_STRAP4
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1__MASK 0x000000FFL
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1__MASK 0x0000FF00L
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1__MASK 0x00FF0000L
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1__MASK 0xFF000000L
+//RCC_DEV1_PORT_STRAP5
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1__MASK 0x000000FFL
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1__MASK 0x0000FF00L
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1__MASK 0x00010000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1__MASK 0x00020000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1__MASK 0x00040000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1__MASK 0x00080000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1__MASK 0x00100000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1__MASK 0x00200000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1__MASK 0x00800000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1__MASK 0x01000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1__MASK 0x02000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1__MASK 0x04000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1__MASK 0x08000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1__MASK 0x10000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1__MASK 0x20000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1__MASK 0x40000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1__MASK 0x80000000L
+//RCC_DEV1_PORT_STRAP6
+#define RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1__MASK 0x00000001L
+#define RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1__MASK 0x00000002L
+//RCC_DEV1_PORT_STRAP7
+#define RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1__MASK 0x000000FFL
+#define RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1__MASK 0x00000F00L
+#define RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1__MASK 0x0000F000L
+#define RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1__MASK 0x00FF0000L
+#define RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1__MASK 0x1F000000L
+#define RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1__MASK 0xE0000000L
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__MASK 0x000F0000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__MASK 0x00F00000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__MASK 0x0F000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__MASK 0x10000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__MASK 0x20000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__MASK 0x40000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__MASK 0x80000000L
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__MASK 0xFFFF0000L
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__MASK 0x00000001L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__MASK 0x0000003EL
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__MASK 0x00000040L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__MASK 0x00000080L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__MASK 0x00000100L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__MASK 0x00003E00L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__MASK 0x00004000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__MASK 0x00008000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__MASK 0x00010000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__MASK 0x00020000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__MASK 0x00040000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__MASK 0x00100000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__MASK 0x00200000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__MASK 0x00400000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__MASK 0x00800000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__MASK 0x07000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__MASK 0x08000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__MASK 0x10000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__MASK 0x20000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__MASK 0x40000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__MASK 0x80000000L
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__MASK 0x00000001L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__MASK 0x00000002L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__MASK 0x0003FFFCL
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__MASK 0x00040000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__MASK 0x00080000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__MASK 0x00100000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__MASK 0x00E00000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__MASK 0x01000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__MASK 0x02000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__MASK 0x04000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__MASK 0x08000000L
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__MASK 0x000FFFFFL
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__MASK 0x00100000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__MASK 0x00200000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__MASK 0x00400000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__MASK 0x0F800000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__MASK 0x70000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__MASK 0x80000000L
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__MASK 0x0000FFFFL
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__MASK 0x00000001L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00000006L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__MASK 0x00000008L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__MASK 0x00000010L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__MASK 0x00000060L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__MASK 0x00000080L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__MASK 0x00000100L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__MASK 0x00000E00L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__MASK 0x00003000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__MASK 0x0000C000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00070000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__MASK 0x00380000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__MASK 0x00C00000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__MASK 0x01000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__MASK 0x02000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__MASK 0x04000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__MASK 0x38000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__MASK 0xC0000000L
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__MASK 0x000000FFL
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__MASK 0x0000FF00L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__MASK 0x00FF0000L
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__MASK 0x0000FFFFL
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__MASK 0x000F0000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__MASK 0x00F00000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__MASK 0x10000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__MASK 0x20000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__MASK 0x40000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__MASK 0x80000000L
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__MASK 0x00000080L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__MASK 0x00000100L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__MASK 0x00004000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__MASK 0x00010000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__MASK 0x00020000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__MASK 0x00040000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__MASK 0x00100000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__MASK 0x00200000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__MASK 0x00400000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__MASK 0x00800000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__MASK 0x07000000L
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__MASK 0x00000001L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__MASK 0x00000002L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__MASK 0x0003FFFCL
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__MASK 0x00040000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__MASK 0x00080000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__MASK 0x00100000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__MASK 0x01000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__MASK 0x02000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__MASK 0x04000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__MASK 0x08000000L
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__MASK 0x00100000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__MASK 0x00200000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__MASK 0x00400000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__MASK 0x0F800000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__MASK 0x70000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__MASK 0x80000000L
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__MASK 0x0000FFFFL
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__MASK 0x00000001L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000002L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__MASK 0x00000004L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__MASK 0x00000070L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__MASK 0x00000100L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000200L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__MASK 0x00010000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__MASK 0x00020000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__MASK 0x01000000L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__MASK 0x02000000L
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__MASK 0x00000001L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__MASK 0x0000001EL
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__MASK 0x00000001L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__MASK 0x00000001L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__MASK 0x00000001L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL
+//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__MASK 0x000000FFL
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__MASK 0x0000FF00L
+#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__MASK 0x00FF0000L
+//RCC_DEV0_EPF2_STRAP0
+#define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__MASK 0x0000FFFFL
+#define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__MASK 0x000F0000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__MASK 0x00F00000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__MASK 0x10000000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__MASK 0x20000000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__MASK 0x40000000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__MASK 0x80000000L
+//RCC_DEV0_EPF2_STRAP2
+#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__MASK 0x00000080L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__MASK 0x00000100L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__MASK 0x00004000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__MASK 0x00010000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__MASK 0x00020000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__MASK 0x00100000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__MASK 0x00200000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__MASK 0x00800000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__MASK 0x07000000L
+//RCC_DEV0_EPF2_STRAP3
+#define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__MASK 0x00000001L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__MASK 0x00000002L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__MASK 0x0003FFFCL
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__MASK 0x00040000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__MASK 0x00080000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__MASK 0x00100000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__MASK 0x01000000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F2__MASK 0x02000000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__MASK 0x04000000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__MASK 0x08000000L
+//RCC_DEV0_EPF2_STRAP4
+#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__MASK 0x00100000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__MASK 0x00200000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__MASK 0x00400000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__MASK 0x0F800000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__MASK 0x70000000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__MASK 0x80000000L
+//RCC_DEV0_EPF2_STRAP5
+#define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__MASK 0x0000FFFFL
+#define RCC_DEV0_EPF2_STRAP5__STRAP_SATAIDP_EN_DEV0_F2__MASK 0x01000000L
+//RCC_DEV0_EPF2_STRAP6
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__MASK 0x00000001L
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2__MASK 0x00000002L
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F2__MASK 0x00000070L
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2__MASK 0x00000100L
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F2__MASK 0x00000200L
+//RCC_DEV0_EPF2_STRAP13
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__MASK 0x000000FFL
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__MASK 0x0000FF00L
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__MASK 0x00FF0000L
+//RCC_DEV0_EPF3_STRAP0
+#define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__MASK 0x0000FFFFL
+#define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__MASK 0x000F0000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__MASK 0x00F00000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__MASK 0x10000000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__MASK 0x20000000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__MASK 0x40000000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__MASK 0x80000000L
+//RCC_DEV0_EPF3_STRAP2
+#define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__MASK 0x00000080L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__MASK 0x00000100L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__MASK 0x00004000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__MASK 0x00010000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__MASK 0x00020000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__MASK 0x00100000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__MASK 0x00200000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__MASK 0x00800000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__MASK 0x07000000L
+//RCC_DEV0_EPF3_STRAP3
+#define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__MASK 0x00000001L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__MASK 0x00000002L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__MASK 0x0003FFFCL
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__MASK 0x00040000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__MASK 0x00080000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__MASK 0x00100000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__MASK 0x01000000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F3__MASK 0x02000000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__MASK 0x04000000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__MASK 0x08000000L
+//RCC_DEV0_EPF3_STRAP4
+#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__MASK 0x00100000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__MASK 0x00200000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__MASK 0x00400000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__MASK 0x0F800000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__MASK 0x70000000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3__MASK 0x80000000L
+//RCC_DEV0_EPF3_STRAP5
+#define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__MASK 0x0000FFFFL
+#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESEL_DEV0_F3__MASK 0x000F0000L
+#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESELD_DEV0_F3__MASK 0x00F00000L
+//RCC_DEV0_EPF3_STRAP6
+#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__MASK 0x00000001L
+#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F3__MASK 0x00000002L
+#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F3__MASK 0x00000070L
+//RCC_DEV0_EPF3_STRAP13
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__MASK 0x000000FFL
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__MASK 0x0000FF00L
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__MASK 0x00FF0000L
+//RCC_DEV0_EPF4_STRAP0
+#define RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4__MASK 0x0000FFFFL
+#define RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4__MASK 0x000F0000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4__MASK 0x00F00000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4__MASK 0x10000000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4__MASK 0x20000000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4__MASK 0x40000000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4__MASK 0x80000000L
+//RCC_DEV0_EPF4_STRAP2
+#define RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4__MASK 0x00000080L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4__MASK 0x00000100L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4__MASK 0x00004000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4__MASK 0x00010000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4__MASK 0x00020000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4__MASK 0x00100000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4__MASK 0x00200000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4__MASK 0x00800000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4__MASK 0x07000000L
+//RCC_DEV0_EPF4_STRAP3
+#define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4__MASK 0x00000001L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4__MASK 0x00000002L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4__MASK 0x0003FFFCL
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4__MASK 0x00040000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4__MASK 0x00080000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4__MASK 0x00100000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4__MASK 0x01000000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F4__MASK 0x02000000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4__MASK 0x04000000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4__MASK 0x08000000L
+//RCC_DEV0_EPF4_STRAP4
+#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4__MASK 0x00100000L
+#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4__MASK 0x00200000L
+#define RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4__MASK 0x00400000L
+#define RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4__MASK 0x0F800000L
+#define RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4__MASK 0x70000000L
+#define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4__MASK 0x80000000L
+//RCC_DEV0_EPF4_STRAP5
+#define RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4__MASK 0x0000FFFFL
+#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESEL_DEV0_F4__MASK 0x000F0000L
+#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESELD_DEV0_F4__MASK 0x00F00000L
+//RCC_DEV0_EPF4_STRAP6
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4__MASK 0x00000001L
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F4__MASK 0x00000002L
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F4__MASK 0x00000070L
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_EN_DEV0_F4__MASK 0x00000100L
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F4__MASK 0x00000200L
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_EN_DEV0_F4__MASK 0x00010000L
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F4__MASK 0x00020000L
+//RCC_DEV0_EPF4_STRAP13
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4__MASK 0x000000FFL
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4__MASK 0x0000FF00L
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4__MASK 0x00FF0000L
+//RCC_DEV0_EPF5_STRAP0
+#define RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5__MASK 0x0000FFFFL
+#define RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5__MASK 0x000F0000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5__MASK 0x00F00000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5__MASK 0x10000000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5__MASK 0x20000000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5__MASK 0x40000000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5__MASK 0x80000000L
+//RCC_DEV0_EPF5_STRAP2
+#define RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5__MASK 0x00000080L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5__MASK 0x00000100L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5__MASK 0x00004000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5__MASK 0x00010000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5__MASK 0x00020000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5__MASK 0x00100000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5__MASK 0x00200000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5__MASK 0x00800000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5__MASK 0x07000000L
+//RCC_DEV0_EPF5_STRAP3
+#define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5__MASK 0x00000001L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5__MASK 0x00000002L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5__MASK 0x0003FFFCL
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5__MASK 0x00040000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5__MASK 0x00080000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5__MASK 0x00100000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5__MASK 0x01000000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F5__MASK 0x02000000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5__MASK 0x04000000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5__MASK 0x08000000L
+//RCC_DEV0_EPF5_STRAP4
+#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5__MASK 0x00100000L
+#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5__MASK 0x00200000L
+#define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5__MASK 0x00400000L
+#define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5__MASK 0x0F800000L
+#define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5__MASK 0x70000000L
+#define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5__MASK 0x80000000L
+//RCC_DEV0_EPF5_STRAP5
+#define RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5__MASK 0x0000FFFFL
+//RCC_DEV0_EPF5_STRAP6
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5__MASK 0x00000001L
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F5__MASK 0x00000002L
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F5__MASK 0x00000070L
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_EN_DEV0_F5__MASK 0x00000100L
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F5__MASK 0x00000200L
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_EN_DEV0_F5__MASK 0x00010000L
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F5__MASK 0x00020000L
+//RCC_DEV0_EPF5_STRAP13
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5__MASK 0x000000FFL
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5__MASK 0x0000FF00L
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5__MASK 0x00FF0000L
+//RCC_DEV0_EPF6_STRAP0
+#define RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6__MASK 0x0000FFFFL
+#define RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6__MASK 0x000F0000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6__MASK 0x00F00000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6__MASK 0x10000000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6__MASK 0x20000000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6__MASK 0x40000000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6__MASK 0x80000000L
+//RCC_DEV0_EPF6_STRAP2
+#define RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6__MASK 0x00000080L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6__MASK 0x00000100L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6__MASK 0x00004000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6__MASK 0x00010000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6__MASK 0x00020000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6__MASK 0x00100000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6__MASK 0x00200000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6__MASK 0x00800000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6__MASK 0x07000000L
+//RCC_DEV0_EPF6_STRAP3
+#define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6__MASK 0x00000001L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6__MASK 0x00000002L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6__MASK 0x0003FFFCL
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6__MASK 0x00040000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6__MASK 0x00080000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6__MASK 0x00100000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6__MASK 0x01000000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F6__MASK 0x02000000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6__MASK 0x04000000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6__MASK 0x08000000L
+//RCC_DEV0_EPF6_STRAP4
+#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6__MASK 0x00100000L
+#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6__MASK 0x00200000L
+#define RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6__MASK 0x00400000L
+#define RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6__MASK 0x0F800000L
+#define RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6__MASK 0x70000000L
+#define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6__MASK 0x80000000L
+//RCC_DEV0_EPF6_STRAP5
+#define RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6__MASK 0x0000FFFFL
+//RCC_DEV0_EPF6_STRAP6
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6__MASK 0x00000001L
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F6__MASK 0x00000002L
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F6__MASK 0x00000070L
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_EN_DEV0_F6__MASK 0x00000100L
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F6__MASK 0x00000200L
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_EN_DEV0_F6__MASK 0x00010000L
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F6__MASK 0x00020000L
+//RCC_DEV0_EPF6_STRAP13
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6__MASK 0x000000FFL
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6__MASK 0x0000FF00L
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6__MASK 0x00FF0000L
+//RCC_DEV0_EPF7_STRAP0
+#define RCC_DEV0_EPF7_STRAP0__STRAP_DEVICE_ID_DEV0_F7__MASK 0x0000FFFFL
+#define RCC_DEV0_EPF7_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F7__MASK 0x000F0000L
+#define RCC_DEV0_EPF7_STRAP0__STRAP_MINOR_REV_ID_DEV0_F7__MASK 0x00F00000L
+#define RCC_DEV0_EPF7_STRAP0__STRAP_FUNC_EN_DEV0_F7__MASK 0x10000000L
+#define RCC_DEV0_EPF7_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7__MASK 0x20000000L
+#define RCC_DEV0_EPF7_STRAP0__STRAP_D1_SUPPORT_DEV0_F7__MASK 0x40000000L
+#define RCC_DEV0_EPF7_STRAP0__STRAP_D2_SUPPORT_DEV0_F7__MASK 0x80000000L
+//RCC_DEV0_EPF7_STRAP2
+#define RCC_DEV0_EPF7_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F7__MASK 0x00000080L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F7__MASK 0x00000100L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7__MASK 0x00004000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_AER_EN_DEV0_F7__MASK 0x00010000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_ACS_EN_DEV0_F7__MASK 0x00020000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F7__MASK 0x00100000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_DPA_EN_DEV0_F7__MASK 0x00200000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_VC_EN_DEV0_F7__MASK 0x00800000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F7__MASK 0x07000000L
+//RCC_DEV0_EPF7_STRAP3
+#define RCC_DEV0_EPF7_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7__MASK 0x00000001L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_PWR_EN_DEV0_F7__MASK 0x00000002L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_SUBSYS_ID_DEV0_F7__MASK 0x0003FFFCL
+#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_EN_DEV0_F7__MASK 0x00040000L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F7__MASK 0x00080000L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_MSIX_EN_DEV0_F7__MASK 0x00100000L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_PMC_DSI_DEV0_F7__MASK 0x01000000L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F7__MASK 0x02000000L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7__MASK 0x04000000L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7__MASK 0x08000000L
+//RCC_DEV0_EPF7_STRAP4
+#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F7__MASK 0x00100000L
+#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_EN_DEV0_F7__MASK 0x00200000L
+#define RCC_DEV0_EPF7_STRAP4__STRAP_FLR_EN_DEV0_F7__MASK 0x00400000L
+#define RCC_DEV0_EPF7_STRAP4__STRAP_PME_SUPPORT_DEV0_F7__MASK 0x0F800000L
+#define RCC_DEV0_EPF7_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F7__MASK 0x70000000L
+#define RCC_DEV0_EPF7_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F7__MASK 0x80000000L
+//RCC_DEV0_EPF7_STRAP5
+#define RCC_DEV0_EPF7_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F7__MASK 0x0000FFFFL
+//RCC_DEV0_EPF7_STRAP6
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_EN_DEV0_F7__MASK 0x00000001L
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F7__MASK 0x00000002L
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F7__MASK 0x00000070L
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_EN_DEV0_F7__MASK 0x00000100L
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F7__MASK 0x00000200L
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_EN_DEV0_F7__MASK 0x00010000L
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F7__MASK 0x00020000L
+//RCC_DEV0_EPF7_STRAP13
+#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F7__MASK 0x000000FFL
+#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F7__MASK 0x0000FF00L
+#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F7__MASK 0x00FF0000L
+//RCC_DEV1_EPF0_STRAP0
+#define RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0__MASK 0x0000FFFFL
+#define RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0__MASK 0x000F0000L
+#define RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0__MASK 0x00F00000L
+#define RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0__MASK 0x10000000L
+#define RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0__MASK 0x20000000L
+#define RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0__MASK 0x40000000L
+#define RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0__MASK 0x80000000L
+//RCC_DEV1_EPF0_STRAP2
+#define RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0__MASK 0x00000080L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0__MASK 0x00000100L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0__MASK 0x00004000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0__MASK 0x00008000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0__MASK 0x00010000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0__MASK 0x00020000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0__MASK 0x00100000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0__MASK 0x00200000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0__MASK 0x00800000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0__MASK 0x07000000L
+//RCC_DEV1_EPF0_STRAP3
+#define RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0__MASK 0x00000001L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0__MASK 0x00000002L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0__MASK 0x0003FFFCL
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0__MASK 0x00040000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0__MASK 0x00080000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0__MASK 0x00100000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0__MASK 0x01000000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F0__MASK 0x02000000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0__MASK 0x04000000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0__MASK 0x08000000L
+//RCC_DEV1_EPF0_STRAP4
+#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0__MASK 0x00100000L
+#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0__MASK 0x00200000L
+#define RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0__MASK 0x00400000L
+#define RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0__MASK 0x0F800000L
+#define RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0__MASK 0x70000000L
+#define RCC_DEV1_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F0__MASK 0x80000000L
+//RCC_DEV1_EPF0_STRAP5
+#define RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0__MASK 0x0000FFFFL
+#define RCC_DEV1_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV1_F0__MASK 0x01000000L
+//RCC_DEV1_EPF0_STRAP6
+#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0__MASK 0x00000001L
+#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F0__MASK 0x00000002L
+#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F0__MASK 0x00000070L
+//RCC_DEV1_EPF0_STRAP13
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0__MASK 0x000000FFL
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0__MASK 0x0000FF00L
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0__MASK 0x00FF0000L
+//RCC_DEV1_EPF1_STRAP0
+#define RCC_DEV1_EPF1_STRAP0__STRAP_DEVICE_ID_DEV1_F1__MASK 0x0000FFFFL
+#define RCC_DEV1_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F1__MASK 0x000F0000L
+#define RCC_DEV1_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV1_F1__MASK 0x00F00000L
+#define RCC_DEV1_EPF1_STRAP0__STRAP_FUNC_EN_DEV1_F1__MASK 0x10000000L
+#define RCC_DEV1_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1__MASK 0x20000000L
+#define RCC_DEV1_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV1_F1__MASK 0x40000000L
+#define RCC_DEV1_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV1_F1__MASK 0x80000000L
+//RCC_DEV1_EPF1_STRAP2
+#define RCC_DEV1_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F1__MASK 0x00000080L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F1__MASK 0x00000100L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1__MASK 0x00004000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_AER_EN_DEV1_F1__MASK 0x00010000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_ACS_EN_DEV1_F1__MASK 0x00020000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F1__MASK 0x00100000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_DPA_EN_DEV1_F1__MASK 0x00200000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_VC_EN_DEV1_F1__MASK 0x00800000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F1__MASK 0x07000000L
+//RCC_DEV1_EPF1_STRAP3
+#define RCC_DEV1_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1__MASK 0x00000001L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_PWR_EN_DEV1_F1__MASK 0x00000002L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV1_F1__MASK 0x0003FFFCL
+#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_EN_DEV1_F1__MASK 0x00040000L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F1__MASK 0x00080000L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_MSIX_EN_DEV1_F1__MASK 0x00100000L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_PMC_DSI_DEV1_F1__MASK 0x01000000L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F1__MASK 0x02000000L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1__MASK 0x04000000L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1__MASK 0x08000000L
+//RCC_DEV1_EPF1_STRAP4
+#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F1__MASK 0x00100000L
+#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV1_F1__MASK 0x00200000L
+#define RCC_DEV1_EPF1_STRAP4__STRAP_FLR_EN_DEV1_F1__MASK 0x00400000L
+#define RCC_DEV1_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV1_F1__MASK 0x0F800000L
+#define RCC_DEV1_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F1__MASK 0x70000000L
+#define RCC_DEV1_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F1__MASK 0x80000000L
+//RCC_DEV1_EPF1_STRAP5
+#define RCC_DEV1_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F1__MASK 0x0000FFFFL
+//RCC_DEV1_EPF1_STRAP6
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_EN_DEV1_F1__MASK 0x00000001L
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F1__MASK 0x00000002L
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F1__MASK 0x00000070L
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_EN_DEV1_F1__MASK 0x00000100L
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F1__MASK 0x00000200L
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_EN_DEV1_F1__MASK 0x00010000L
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F1__MASK 0x00020000L
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_EN_DEV1_F1__MASK 0x01000000L
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F1__MASK 0x02000000L
+//RCC_DEV1_EPF1_STRAP13
+#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F1__MASK 0x000000FFL
+#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F1__MASK 0x0000FF00L
+#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F1__MASK 0x00FF0000L
+//RCC_DEV1_EPF2_STRAP0
+#define RCC_DEV1_EPF2_STRAP0__STRAP_DEVICE_ID_DEV1_F2__MASK 0x0000FFFFL
+#define RCC_DEV1_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F2__MASK 0x000F0000L
+#define RCC_DEV1_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV1_F2__MASK 0x00F00000L
+#define RCC_DEV1_EPF2_STRAP0__STRAP_FUNC_EN_DEV1_F2__MASK 0x10000000L
+#define RCC_DEV1_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F2__MASK 0x20000000L
+#define RCC_DEV1_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV1_F2__MASK 0x40000000L
+#define RCC_DEV1_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV1_F2__MASK 0x80000000L
+//RCC_DEV1_EPF2_STRAP2
+#define RCC_DEV1_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F2__MASK 0x00000080L
+#define RCC_DEV1_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F2__MASK 0x00000100L
+#define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F2__MASK 0x00004000L
+#define RCC_DEV1_EPF2_STRAP2__STRAP_AER_EN_DEV1_F2__MASK 0x00010000L
+#define RCC_DEV1_EPF2_STRAP2__STRAP_ACS_EN_DEV1_F2__MASK 0x00020000L
+#define RCC_DEV1_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F2__MASK 0x00100000L
+#define RCC_DEV1_EPF2_STRAP2__STRAP_DPA_EN_DEV1_F2__MASK 0x00200000L
+#define RCC_DEV1_EPF2_STRAP2__STRAP_VC_EN_DEV1_F2__MASK 0x00800000L
+#define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F2__MASK 0x07000000L
+//RCC_DEV1_EPF2_STRAP3
+#define RCC_DEV1_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F2__MASK 0x00000001L
+#define RCC_DEV1_EPF2_STRAP3__STRAP_PWR_EN_DEV1_F2__MASK 0x00000002L
+#define RCC_DEV1_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV1_F2__MASK 0x0003FFFCL
+#define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_EN_DEV1_F2__MASK 0x00040000L
+#define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F2__MASK 0x00080000L
+#define RCC_DEV1_EPF2_STRAP3__STRAP_MSIX_EN_DEV1_F2__MASK 0x00100000L
+#define RCC_DEV1_EPF2_STRAP3__STRAP_PMC_DSI_DEV1_F2__MASK 0x01000000L
+#define RCC_DEV1_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F2__MASK 0x02000000L
+#define RCC_DEV1_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F2__MASK 0x04000000L
+#define RCC_DEV1_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F2__MASK 0x08000000L
+//RCC_DEV1_EPF2_STRAP4
+#define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F2__MASK 0x00100000L
+#define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV1_F2__MASK 0x00200000L
+#define RCC_DEV1_EPF2_STRAP4__STRAP_FLR_EN_DEV1_F2__MASK 0x00400000L
+#define RCC_DEV1_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV1_F2__MASK 0x0F800000L
+#define RCC_DEV1_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F2__MASK 0x70000000L
+#define RCC_DEV1_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F2__MASK 0x80000000L
+//RCC_DEV1_EPF2_STRAP5
+#define RCC_DEV1_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F2__MASK 0x0000FFFFL
+//RCC_DEV1_EPF2_STRAP6
+#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_EN_DEV1_F2__MASK 0x00000001L
+#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F2__MASK 0x00000002L
+#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F2__MASK 0x00000070L
+#define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_EN_DEV1_F2__MASK 0x00000100L
+#define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F2__MASK 0x00000200L
+#define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_EN_DEV1_F2__MASK 0x00010000L
+#define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F2__MASK 0x00020000L
+#define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_EN_DEV1_F2__MASK 0x01000000L
+#define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F2__MASK 0x02000000L
+//RCC_DEV1_EPF2_STRAP13
+#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F2__MASK 0x000000FFL
+#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F2__MASK 0x0000FF00L
+#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F2__MASK 0x00FF0000L
+
+
+// addressBlock: bif_rst_bif_rst_regblk
+//HARD_RST_CTRL
+#define HARD_RST_CTRL__DSPT_CFG_RST_EN__MASK 0x00000001L
+#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__MASK 0x00000002L
+#define HARD_RST_CTRL__DSPT_PRV_RST_EN__MASK 0x00000004L
+#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__MASK 0x00000008L
+#define HARD_RST_CTRL__EP_CFG_RST_EN__MASK 0x00000010L
+#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__MASK 0x00000020L
+#define HARD_RST_CTRL__EP_PRV_RST_EN__MASK 0x00000040L
+#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__MASK 0x00000080L
+#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__MASK 0x10000000L
+#define HARD_RST_CTRL__CORE_STICKY_RST_EN__MASK 0x20000000L
+#define HARD_RST_CTRL__RELOAD_STRAP_EN__MASK 0x40000000L
+#define HARD_RST_CTRL__CORE_RST_EN__MASK 0x80000000L
+//RSMU_SOFT_RST_CTRL
+#define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN__MASK 0x00000001L
+#define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN__MASK 0x00000002L
+#define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN__MASK 0x00000004L
+#define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN__MASK 0x00000008L
+#define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN__MASK 0x00000010L
+#define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN__MASK 0x00000020L
+#define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN__MASK 0x00000040L
+#define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN__MASK 0x00000080L
+#define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN__MASK 0x10000000L
+#define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN__MASK 0x20000000L
+#define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN__MASK 0x40000000L
+#define RSMU_SOFT_RST_CTRL__CORE_RST_EN__MASK 0x80000000L
+//SELF_SOFT_RST
+#define SELF_SOFT_RST__DSPT0_CFG_RST__MASK 0x00000001L
+#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__MASK 0x00000002L
+#define SELF_SOFT_RST__DSPT0_PRV_RST__MASK 0x00000004L
+#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__MASK 0x00000008L
+#define SELF_SOFT_RST__EP0_CFG_RST__MASK 0x00000010L
+#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__MASK 0x00000020L
+#define SELF_SOFT_RST__EP0_PRV_RST__MASK 0x00000040L
+#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__MASK 0x00000080L
+#define SELF_SOFT_RST__SDP_PORT_RST__MASK 0x08000000L
+#define SELF_SOFT_RST__SWUS_SHADOW_RST__MASK 0x10000000L
+#define SELF_SOFT_RST__CORE_STICKY_RST__MASK 0x20000000L
+#define SELF_SOFT_RST__RELOAD_STRAP__MASK 0x40000000L
+#define SELF_SOFT_RST__CORE_RST__MASK 0x80000000L
+//GFX_DRV_MODE1_RST_CTRL
+#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_RST__MASK 0x00000001L
+#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_FLR_EXC_RST__MASK 0x00000002L
+#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_STICKY_RST__MASK 0x00000004L
+#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_RST__MASK 0x00000008L
+#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_STICKY_RST__MASK 0x00000010L
+#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_RST__MASK 0x00000020L
+#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_STICKY_RST__MASK 0x00000040L
+#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_PRV_RST__MASK 0x00000080L
+//BIF_RST_MISC_CTRL
+#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__MASK 0x00000001L
+#define BIF_RST_MISC_CTRL__DRV_RST_MODE__MASK 0x0000000CL
+#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__MASK 0x00000010L
+#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__MASK 0x00000020L
+#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__MASK 0x00000040L
+#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__MASK 0x00000100L
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__MASK 0x00000200L
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__MASK 0x00001C00L
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__MASK 0x00006000L
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__MASK 0x00018000L
+#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__MASK 0x00060000L
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__MASK 0x00800000L
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__MASK 0x03000000L
+//BIF_RST_MISC_CTRL2
+#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__MASK 0x00010000L
+#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__MASK 0x00020000L
+#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__MASK 0x00040000L
+#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__MASK 0x80000000L
+//BIF_RST_MISC_CTRL3
+#define BIF_RST_MISC_CTRL3__TIMER_SCALE__MASK 0x0000000FL
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__MASK 0x00000030L
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__MASK 0x00000040L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__MASK 0x00000380L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__MASK 0x00001C00L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__MASK 0x0000E000L
+//BIF_RST_GFXVF_FLR_IDLE
+#define BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE__MASK 0x00000001L
+#define BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE__MASK 0x00000002L
+#define BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE__MASK 0x00000004L
+#define BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE__MASK 0x00000008L
+#define BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE__MASK 0x00000010L
+#define BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE__MASK 0x00000020L
+#define BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE__MASK 0x00000040L
+#define BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE__MASK 0x00000080L
+#define BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE__MASK 0x00000100L
+#define BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE__MASK 0x00000200L
+#define BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE__MASK 0x00000400L
+#define BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE__MASK 0x00000800L
+#define BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE__MASK 0x00001000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE__MASK 0x00002000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE__MASK 0x00004000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE__MASK 0x00008000L
+#define BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE__MASK 0x80000000L
+//DEV0_PF0_FLR_RST_CTRL
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__MASK 0x00000020L
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__MASK 0x00000040L
+#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__MASK 0x00000080L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__MASK 0x00000100L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__MASK 0x00000200L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__MASK 0x00000400L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__MASK 0x00000800L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__MASK 0x00001000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__MASK 0x00002000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__MASK 0x00004000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__MASK 0x00008000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__MASK 0x00010000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L
+//DEV0_PF1_FLR_RST_CTRL
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L
+//DEV0_PF2_FLR_RST_CTRL
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L
+//DEV0_PF3_FLR_RST_CTRL
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L
+//DEV0_PF4_FLR_RST_CTRL
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L
+//DEV0_PF5_FLR_RST_CTRL
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L
+//DEV0_PF6_FLR_RST_CTRL
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L
+//DEV0_PF7_FLR_RST_CTRL
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L
+//BIF_INST_RESET_INTR_STS
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__MASK 0x00000001L
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__MASK 0x00000002L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__MASK 0x00000004L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__MASK 0x00000008L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__MASK 0x00000010L
+//BIF_PF_FLR_INTR_STS
+#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__MASK 0x00000001L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__MASK 0x00000002L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__MASK 0x00000004L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__MASK 0x00000008L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__MASK 0x00000010L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__MASK 0x00000020L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__MASK 0x00000040L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__MASK 0x00000080L
+//BIF_D3HOTD0_INTR_STS
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__MASK 0x00000001L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__MASK 0x00000002L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__MASK 0x00000004L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__MASK 0x00000008L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__MASK 0x00000010L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__MASK 0x00000020L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__MASK 0x00000040L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__MASK 0x00000080L
+//BIF_POWER_INTR_STS
+#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__MASK 0x00000001L
+#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__MASK 0x00010000L
+//BIF_PF_DSTATE_INTR_STS
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__MASK 0x00000001L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__MASK 0x00000002L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__MASK 0x00000004L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__MASK 0x00000008L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__MASK 0x00000010L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__MASK 0x00000020L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__MASK 0x00000040L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__MASK 0x00000080L
+//BIF_PF0_VF_FLR_INTR_STS
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS__MASK 0x00000001L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS__MASK 0x00000002L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS__MASK 0x00000004L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS__MASK 0x00000008L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS__MASK 0x00000010L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS__MASK 0x00000020L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS__MASK 0x00000040L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS__MASK 0x00000080L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS__MASK 0x00000100L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS__MASK 0x00000200L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS__MASK 0x00000400L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS__MASK 0x00000800L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS__MASK 0x00001000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS__MASK 0x00002000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS__MASK 0x00004000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS__MASK 0x00008000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS__MASK 0x80000000L
+//BIF_INST_RESET_INTR_MASK
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__MASK 0x00000001L
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__MASK 0x00000002L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__MASK 0x00000004L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__MASK 0x00000008L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__MASK 0x00000010L
+//BIF_PF_FLR_INTR_MASK
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__MASK 0x00000001L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__MASK 0x00000002L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__MASK 0x00000004L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__MASK 0x00000008L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__MASK 0x00000010L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__MASK 0x00000020L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__MASK 0x00000040L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__MASK 0x00000080L
+//BIF_D3HOTD0_INTR_MASK
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__MASK 0x00000001L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__MASK 0x00000002L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__MASK 0x00000004L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__MASK 0x00000008L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__MASK 0x00000010L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__MASK 0x00000020L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__MASK 0x00000040L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__MASK 0x00000080L
+//BIF_POWER_INTR_MASK
+#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__MASK 0x00000001L
+#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__MASK 0x00010000L
+//BIF_PF_DSTATE_INTR_MASK
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__MASK 0x00000001L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__MASK 0x00000002L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__MASK 0x00000004L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__MASK 0x00000008L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__MASK 0x00000010L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__MASK 0x00000020L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__MASK 0x00000040L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__MASK 0x00000080L
+//BIF_PF0_VF_FLR_INTR_MASK
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK__MASK 0x00000001L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__MASK 0x00000002L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK__MASK 0x00000004L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK__MASK 0x00000008L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK__MASK 0x00000010L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK__MASK 0x00000020L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK__MASK 0x00000040L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK__MASK 0x00000080L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK__MASK 0x00000100L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK__MASK 0x00000200L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK__MASK 0x00000400L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK__MASK 0x00000800L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK__MASK 0x00001000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK__MASK 0x00002000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK__MASK 0x00004000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK__MASK 0x00008000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK__MASK 0x80000000L
+//BIF_PF_FLR_RST
+#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__MASK 0x00000001L
+#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__MASK 0x00000002L
+#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__MASK 0x00000004L
+#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__MASK 0x00000008L
+#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__MASK 0x00000010L
+#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__MASK 0x00000020L
+#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__MASK 0x00000040L
+#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__MASK 0x00000080L
+//BIF_PF0_VF_FLR_RST
+#define BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__MASK 0x00000001L
+#define BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__MASK 0x00000002L
+#define BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__MASK 0x00000004L
+#define BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__MASK 0x00000008L
+#define BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__MASK 0x00000010L
+#define BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__MASK 0x00000020L
+#define BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__MASK 0x00000040L
+#define BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__MASK 0x00000080L
+#define BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__MASK 0x00000100L
+#define BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__MASK 0x00000200L
+#define BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__MASK 0x00000400L
+#define BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__MASK 0x00000800L
+#define BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__MASK 0x00001000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__MASK 0x00002000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__MASK 0x00004000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__MASK 0x00008000L
+#define BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__MASK 0x80000000L
+//BIF_DEV0_PF0_DSTATE_VALUE
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__MASK 0x00000003L
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__MASK 0x00030000L
+//BIF_DEV0_PF1_DSTATE_VALUE
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__MASK 0x00000003L
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__MASK 0x00030000L
+//BIF_DEV0_PF2_DSTATE_VALUE
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__MASK 0x00000003L
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__MASK 0x00030000L
+//BIF_DEV0_PF3_DSTATE_VALUE
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__MASK 0x00000003L
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__MASK 0x00030000L
+//BIF_DEV0_PF4_DSTATE_VALUE
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__MASK 0x00000003L
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__MASK 0x00030000L
+//BIF_DEV0_PF5_DSTATE_VALUE
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__MASK 0x00000003L
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__MASK 0x00030000L
+//BIF_DEV0_PF6_DSTATE_VALUE
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__MASK 0x00000003L
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__MASK 0x00030000L
+//BIF_DEV0_PF7_DSTATE_VALUE
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__MASK 0x00000003L
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__MASK 0x00030000L
+//DEV0_PF0_D3HOTD0_RST_CTRL
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
+//DEV0_PF1_D3HOTD0_RST_CTRL
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
+//DEV0_PF2_D3HOTD0_RST_CTRL
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
+//DEV0_PF3_D3HOTD0_RST_CTRL
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
+//DEV0_PF4_D3HOTD0_RST_CTRL
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
+//DEV0_PF5_D3HOTD0_RST_CTRL
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
+//DEV0_PF6_D3HOTD0_RST_CTRL
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
+//DEV0_PF7_D3HOTD0_RST_CTRL
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
+//BIF_PORT0_DSTATE_VALUE
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__MASK 0x00000003L
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__MASK 0x00030000L
+
+
+// addressBlock: bif_misc_bif_misc_regblk
+//MISC_SCRATCH
+#define MISC_SCRATCH__MISC_SCRATCH0__MASK 0xFFFFFFFFL
+//INTR_LINE_POLARITY
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__MASK 0x000000FFL
+//INTR_LINE_ENABLE
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__MASK 0x000000FFL
+//OUTSTANDING_VC_ALLOC
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__MASK 0x00000003L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__MASK 0x0000000CL
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__MASK 0x00000030L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__MASK 0x000000C0L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__MASK 0x00000300L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__MASK 0x00000C00L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__MASK 0x00003000L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__MASK 0x0000C000L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__MASK 0x000F0000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__MASK 0x03000000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__MASK 0x0C000000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__MASK 0xF0000000L
+//BIFC_MISC_CTRL0
+#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__MASK 0x00000001L
+#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__MASK 0x00000006L
+#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__MASK 0x00000100L
+#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__MASK 0x00000200L
+#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__MASK 0x00000400L
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__MASK 0x00010000L
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__MASK 0x00020000L
+#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__MASK 0x01000000L
+#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__MASK 0x02000000L
+#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__MASK 0x04000000L
+#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__MASK 0x08000000L
+#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__MASK 0x10000000L
+#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__MASK 0x80000000L
+//BIFC_MISC_CTRL1
+#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__MASK 0x00000001L
+#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__MASK 0x00000002L
+#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__MASK 0x00000004L
+#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__MASK 0x00000008L
+#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__MASK 0x00000010L
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__MASK 0x00000020L
+#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__MASK 0x00000040L
+#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__MASK 0x00000080L
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__MASK 0x00000300L
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__MASK 0x00000C00L
+#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__MASK 0x00001000L
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__MASK 0x00002000L
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__MASK 0x00004000L
+#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__MASK 0x00008000L
+#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__MASK 0x00010000L
+#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__MASK 0x00020000L
+#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__MASK 0x00040000L
+#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__MASK 0x00080000L
+//BIFC_BME_ERR_LOG
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__MASK 0x00000001L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__MASK 0x00000002L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__MASK 0x00000004L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__MASK 0x00000008L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__MASK 0x00000010L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__MASK 0x00000020L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__MASK 0x00000040L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__MASK 0x00000080L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__MASK 0x00010000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__MASK 0x00020000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__MASK 0x00040000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__MASK 0x00080000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__MASK 0x00100000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__MASK 0x00200000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__MASK 0x00400000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__MASK 0x00800000L
+//BIFC_RCCBIH_BME_ERR_LOG
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0__MASK 0x00000001L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1__MASK 0x00000002L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2__MASK 0x00000004L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3__MASK 0x00000008L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4__MASK 0x00000010L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5__MASK 0x00000020L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6__MASK 0x00000040L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7__MASK 0x00000080L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__MASK 0x00010000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__MASK 0x00020000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__MASK 0x00040000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__MASK 0x00080000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__MASK 0x00100000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__MASK 0x00200000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__MASK 0x00400000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__MASK 0x00800000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__MASK 0x30000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__MASK 0x30000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__MASK 0x30000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__MASK 0x30000000L
+//NBIF_VWIRE_CTRL
+#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__MASK 0x000000F0L
+#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__MASK 0x00000100L
+#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__MASK 0x00F00000L
+#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__MASK 0x0C000000L
+//NBIF_SMN_VWR_VCHG_DIS_CTRL
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__MASK 0x00000004L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__MASK 0x00000008L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__MASK 0x00000010L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__MASK 0x00000020L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__MASK 0x00000040L
+//NBIF_SMN_VWR_VCHG_RST_CTRL0
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__MASK 0x00000004L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__MASK 0x00000008L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__MASK 0x00000010L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__MASK 0x00000020L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__MASK 0x00000040L
+//NBIF_SMN_VWR_VCHG_TRIG
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__MASK 0x00000004L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__MASK 0x00000008L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__MASK 0x00000010L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__MASK 0x00000020L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__MASK 0x00000040L
+//NBIF_SMN_VWR_WTRIG_CNTL
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__MASK 0x00000001L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__MASK 0x00000002L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__MASK 0x00000004L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__MASK 0x00000008L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__MASK 0x00000010L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__MASK 0x00000020L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__MASK 0x00000040L
+//NBIF_SMN_VWR_VCHG_DIS_CTRL_1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__MASK 0x00000004L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__MASK 0x00000008L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__MASK 0x00000010L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__MASK 0x00000020L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__MASK 0x00000040L
+//NBIF_MGCG_CTRL
+#define NBIF_MGCG_CTRL__NBIF_MGCG_EN__MASK 0x00000001L
+#define NBIF_MGCG_CTRL__NBIF_MGCG_MODE__MASK 0x00000002L
+#define NBIF_MGCG_CTRL__NBIF_MGCG_HYSTERESIS__MASK 0x000003FCL
+//NBIF_DS_CTRL_LCLK
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__MASK 0x00000001L
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__MASK 0xFFFF0000L
+//SMN_MST_CNTL0
+#define SMN_MST_CNTL0__SMN_ARB_MODE__MASK 0x00000003L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__MASK 0x00000100L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__MASK 0x00000200L
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__MASK 0x00000400L
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__MASK 0x00000800L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__MASK 0x00010000L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__MASK 0x00100000L
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__MASK 0x01000000L
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__MASK 0x10000000L
+//SMN_MST_EP_CNTL1
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__MASK 0x00000001L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__MASK 0x00000002L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__MASK 0x00000004L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__MASK 0x00000008L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__MASK 0x00000010L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__MASK 0x00000020L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__MASK 0x00000040L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__MASK 0x00000080L
+//SMN_MST_EP_CNTL2
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__MASK 0x00000001L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__MASK 0x00000002L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__MASK 0x00000004L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__MASK 0x00000008L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__MASK 0x00000010L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__MASK 0x00000020L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__MASK 0x00000040L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__MASK 0x00000080L
+//NBIF_SDP_VWR_VCHG_DIS_CTRL
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__MASK 0x01000000L
+//NBIF_SDP_VWR_VCHG_RST_CTRL0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__MASK 0x01000000L
+//NBIF_SDP_VWR_VCHG_RST_CTRL1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__MASK 0x01000000L
+//NBIF_SDP_VWR_VCHG_TRIG
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__MASK 0x01000000L
+//BME_DUMMY_CNTL_0
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__MASK 0x00000003L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__MASK 0x0000000CL
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__MASK 0x00000030L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__MASK 0x000000C0L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__MASK 0x00000300L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__MASK 0x00000C00L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__MASK 0x00003000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__MASK 0x0000C000L
+//BIFC_THT_CNTL
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__MASK 0x0000000FL
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__MASK 0x000000F0L
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__MASK 0x00000F00L
+//BIFC_HSTARB_CNTL
+#define BIFC_HSTARB_CNTL__SLVARB_MODE__MASK 0x00000003L
+//BIFC_GSI_CNTL
+#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__MASK 0x00000003L
+#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__MASK 0x0000001CL
+#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__MASK 0x00000020L
+#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__MASK 0x00000040L
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__MASK 0x00000080L
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__MASK 0x00000100L
+#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__MASK 0x00000200L
+#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__MASK 0x00000C00L
+#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__MASK 0x00003000L
+//BIFC_PCIEFUNC_CNTL
+#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__MASK 0x0000FFFFL
+#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__MASK 0x00010000L
+//BIFC_SDP_CNTL_0
+#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__MASK 0x0000003FL
+#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__MASK 0x00000FC0L
+#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__MASK 0x0003F000L
+#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__MASK 0x00FC0000L
+//BIFC_PERF_CNTL_0
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__MASK 0x00000001L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__MASK 0x00000002L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__MASK 0x00000100L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__MASK 0x00000200L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__MASK 0x001F0000L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__MASK 0x1F000000L
+//BIFC_PERF_CNTL_1
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__MASK 0x00000001L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__MASK 0x00000002L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__MASK 0x00000100L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__MASK 0x00000200L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__MASK 0x003F0000L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__MASK 0x7F000000L
+//BIFC_PERF_CNT_MMIO_RD
+#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__MASK 0xFFFFFFFFL
+//BIFC_PERF_CNT_MMIO_WR
+#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__MASK 0xFFFFFFFFL
+//BIFC_PERF_CNT_DMA_RD
+#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__MASK 0xFFFFFFFFL
+//BIFC_PERF_CNT_DMA_WR
+#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__MASK 0xFFFFFFFFL
+//NBIF_REGIF_ERRSET_CTRL
+#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__MASK 0x00000001L
+//SMN_MST_EP_CNTL3
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__MASK 0x00000001L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__MASK 0x00000002L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__MASK 0x00000004L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__MASK 0x00000008L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__MASK 0x00000010L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__MASK 0x00000020L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__MASK 0x00000040L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__MASK 0x00000080L
+//SMN_MST_EP_CNTL4
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__MASK 0x00000001L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__MASK 0x00000002L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__MASK 0x00000004L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__MASK 0x00000008L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__MASK 0x00000010L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__MASK 0x00000020L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__MASK 0x00000040L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__MASK 0x00000080L
+//BIF_SELFRING_BUFFER_VID
+#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__MASK 0x000000FFL
+#define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID__MASK 0x0000FF00L
+//BIF_SELFRING_VECTOR_CNTL
+#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__MASK 0x00000001L
+
+
+// addressBlock: bif_ras_bif_ras_regblk
+//BIF_RAS_LEAF0_CTRL
+#define BIF_RAS_LEAF0_CTRL__POISON_DET_EN__MASK 0x00000001L
+#define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L
+#define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN__MASK 0x00000004L
+#define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN__MASK 0x00000010L
+#define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L
+#define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN__MASK 0x00000040L
+#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV__MASK 0x00010000L
+#define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV__MASK 0x00020000L
+#define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET__MASK 0x00040000L
+#define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET__MASK 0x00080000L
+#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT__MASK 0x00100000L
+#define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED__MASK 0x00200000L
+//BIF_RAS_LEAF1_CTRL
+#define BIF_RAS_LEAF1_CTRL__POISON_DET_EN__MASK 0x00000001L
+#define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L
+#define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN__MASK 0x00000004L
+#define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN__MASK 0x00000010L
+#define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L
+#define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN__MASK 0x00000040L
+#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV__MASK 0x00010000L
+#define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV__MASK 0x00020000L
+#define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET__MASK 0x00040000L
+#define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET__MASK 0x00080000L
+#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT__MASK 0x00100000L
+#define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED__MASK 0x00200000L
+//BIF_RAS_LEAF2_CTRL
+#define BIF_RAS_LEAF2_CTRL__POISON_DET_EN__MASK 0x00000001L
+#define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L
+#define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN__MASK 0x00000004L
+#define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN__MASK 0x00000010L
+#define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L
+#define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN__MASK 0x00000040L
+#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV__MASK 0x00010000L
+#define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV__MASK 0x00020000L
+#define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET__MASK 0x00040000L
+#define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET__MASK 0x00080000L
+#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT__MASK 0x00100000L
+#define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED__MASK 0x00200000L
+//BIF_RAS_MISC_CTRL
+#define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN__MASK 0x00000001L
+//BIF_IOHUB_RAS_IH_CNTL
+#define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN__MASK 0x00000001L
+//BIF_RAS_VWR_FROM_IOHUB
+#define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG__MASK 0x00000001L
+
+
+// addressBlock: rcc_pfc_amdgfx_RCCPFCDEC
+//RCC_PFC_LTR_CNTL
+#define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__MASK 0x000003FFL
+#define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__MASK 0x00001C00L
+#define RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__MASK 0x00008000L
+#define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__MASK 0x03FF0000L
+#define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__MASK 0x1C000000L
+#define RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__MASK 0x80000000L
+//RCC_PFC_PME_RESTORE
+#define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__MASK 0x00000001L
+#define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__MASK 0x00000100L
+//RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__MASK 0x00000001L
+#define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__MASK 0x00000002L
+#define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__MASK 0x00000004L
+#define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__MASK 0x00000008L
+#define RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__MASK 0x00000010L
+#define RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__MASK 0x00000020L
+#define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__MASK 0x00000040L
+#define RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__MASK 0x00000080L
+//RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__MASK 0xFFFFFFFFL
+//RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__MASK 0xFFFFFFFFL
+//RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__MASK 0xFFFFFFFFL
+//RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__MASK 0xFFFFFFFFL
+//RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__MASK 0xFFFFFFFFL
+//RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__MASK 0x00000007L
+#define RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__MASK 0x00000008L
+
+
+// addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC
+//RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL
+#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__MASK 0x000003FFL
+#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__MASK 0x00001C00L
+#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__MASK 0x00008000L
+#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__MASK 0x03FF0000L
+#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__MASK 0x1C000000L
+#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__MASK 0x80000000L
+//RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE
+#define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__MASK 0x00000001L
+#define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__MASK 0x00000100L
+//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__MASK 0x00000001L
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__MASK 0x00000002L
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__MASK 0x00000004L
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__MASK 0x00000008L
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__MASK 0x00000010L
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__MASK 0x00000020L
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__MASK 0x00000040L
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__MASK 0x00000080L
+//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__MASK 0xFFFFFFFFL
+//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__MASK 0xFFFFFFFFL
+//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__MASK 0xFFFFFFFFL
+//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__MASK 0xFFFFFFFFL
+//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5
+#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__MASK 0xFFFFFFFFL
+//RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL
+#define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__MASK 0x00000007L
+#define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__MASK 0x00000008L
+
+
+// addressBlock: pciemsix_amdgfx_MSIXTDEC
+//PCIEMSIX_VECT0_ADDR_LO
+#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT0_ADDR_HI
+#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT0_MSG_DATA
+#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT0_CONTROL
+#define PCIEMSIX_VECT0_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT1_ADDR_LO
+#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT1_ADDR_HI
+#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT1_MSG_DATA
+#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT1_CONTROL
+#define PCIEMSIX_VECT1_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT2_ADDR_LO
+#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT2_ADDR_HI
+#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT2_MSG_DATA
+#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT2_CONTROL
+#define PCIEMSIX_VECT2_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT3_ADDR_LO
+#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT3_ADDR_HI
+#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT3_MSG_DATA
+#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT3_CONTROL
+#define PCIEMSIX_VECT3_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT4_ADDR_LO
+#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT4_ADDR_HI
+#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT4_MSG_DATA
+#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT4_CONTROL
+#define PCIEMSIX_VECT4_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT5_ADDR_LO
+#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT5_ADDR_HI
+#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT5_MSG_DATA
+#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT5_CONTROL
+#define PCIEMSIX_VECT5_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT6_ADDR_LO
+#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT6_ADDR_HI
+#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT6_MSG_DATA
+#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT6_CONTROL
+#define PCIEMSIX_VECT6_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT7_ADDR_LO
+#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT7_ADDR_HI
+#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT7_MSG_DATA
+#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT7_CONTROL
+#define PCIEMSIX_VECT7_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT8_ADDR_LO
+#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT8_ADDR_HI
+#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT8_MSG_DATA
+#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT8_CONTROL
+#define PCIEMSIX_VECT8_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT9_ADDR_LO
+#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT9_ADDR_HI
+#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT9_MSG_DATA
+#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT9_CONTROL
+#define PCIEMSIX_VECT9_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT10_ADDR_LO
+#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT10_ADDR_HI
+#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT10_MSG_DATA
+#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT10_CONTROL
+#define PCIEMSIX_VECT10_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT11_ADDR_LO
+#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT11_ADDR_HI
+#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT11_MSG_DATA
+#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT11_CONTROL
+#define PCIEMSIX_VECT11_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT12_ADDR_LO
+#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT12_ADDR_HI
+#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT12_MSG_DATA
+#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT12_CONTROL
+#define PCIEMSIX_VECT12_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT13_ADDR_LO
+#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT13_ADDR_HI
+#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT13_MSG_DATA
+#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT13_CONTROL
+#define PCIEMSIX_VECT13_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT14_ADDR_LO
+#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT14_ADDR_HI
+#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT14_MSG_DATA
+#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT14_CONTROL
+#define PCIEMSIX_VECT14_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT15_ADDR_LO
+#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT15_ADDR_HI
+#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT15_MSG_DATA
+#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT15_CONTROL
+#define PCIEMSIX_VECT15_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT16_ADDR_LO
+#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT16_ADDR_HI
+#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT16_MSG_DATA
+#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT16_CONTROL
+#define PCIEMSIX_VECT16_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT17_ADDR_LO
+#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT17_ADDR_HI
+#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT17_MSG_DATA
+#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT17_CONTROL
+#define PCIEMSIX_VECT17_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT18_ADDR_LO
+#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT18_ADDR_HI
+#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT18_MSG_DATA
+#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT18_CONTROL
+#define PCIEMSIX_VECT18_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT19_ADDR_LO
+#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT19_ADDR_HI
+#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT19_MSG_DATA
+#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT19_CONTROL
+#define PCIEMSIX_VECT19_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT20_ADDR_LO
+#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT20_ADDR_HI
+#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT20_MSG_DATA
+#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT20_CONTROL
+#define PCIEMSIX_VECT20_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT21_ADDR_LO
+#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT21_ADDR_HI
+#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT21_MSG_DATA
+#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT21_CONTROL
+#define PCIEMSIX_VECT21_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT22_ADDR_LO
+#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT22_ADDR_HI
+#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT22_MSG_DATA
+#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT22_CONTROL
+#define PCIEMSIX_VECT22_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT23_ADDR_LO
+#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT23_ADDR_HI
+#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT23_MSG_DATA
+#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT23_CONTROL
+#define PCIEMSIX_VECT23_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT24_ADDR_LO
+#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT24_ADDR_HI
+#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT24_MSG_DATA
+#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT24_CONTROL
+#define PCIEMSIX_VECT24_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT25_ADDR_LO
+#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT25_ADDR_HI
+#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT25_MSG_DATA
+#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT25_CONTROL
+#define PCIEMSIX_VECT25_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT26_ADDR_LO
+#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT26_ADDR_HI
+#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT26_MSG_DATA
+#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT26_CONTROL
+#define PCIEMSIX_VECT26_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT27_ADDR_LO
+#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT27_ADDR_HI
+#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT27_MSG_DATA
+#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT27_CONTROL
+#define PCIEMSIX_VECT27_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT28_ADDR_LO
+#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT28_ADDR_HI
+#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT28_MSG_DATA
+#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT28_CONTROL
+#define PCIEMSIX_VECT28_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT29_ADDR_LO
+#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT29_ADDR_HI
+#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT29_MSG_DATA
+#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT29_CONTROL
+#define PCIEMSIX_VECT29_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT30_ADDR_LO
+#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT30_ADDR_HI
+#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT30_MSG_DATA
+#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT30_CONTROL
+#define PCIEMSIX_VECT30_CONTROL__MASK_BIT__MASK 0x00000001L
+//PCIEMSIX_VECT31_ADDR_LO
+#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT31_ADDR_HI
+#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT31_MSG_DATA
+#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT31_CONTROL
+#define PCIEMSIX_VECT31_CONTROL__MASK_BIT__MASK 0x00000001L
+
+
+// addressBlock: pciemsix_amdgfx_MSIXPDEC
+//PCIEMSIX_PBA
+#define PCIEMSIX_PBA__MSIX_PENDING_BITS__MASK 0xFFFFFFFFL
+
+
+// addressBlock: syshub_mmreg_ind_syshubind
+//SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__MASK 0x80000000L
+//SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__MASK 0x0000FFFFL
+//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__MASK 0x00000001L
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__MASK 0x00000002L
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__MASK 0x00008000L
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__MASK 0x00010000L
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__MASK 0x00020000L
+//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__MASK 0x00000001L
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__MASK 0x00000002L
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__MASK 0x00008000L
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__MASK 0x00010000L
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__MASK 0x00020000L
+//SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L
+//SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL
+#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL
+#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L
+//SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL
+#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL
+#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//SYSHUBMMREGIND_SYSHUB_CG_CNTL
+#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_EN__MASK 0x00000001L
+#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__MASK 0x0000FF00L
+#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__MASK 0x00FF0000L
+//SYSHUBMMREGIND_SYSHUB_TRANS_IDLE
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__MASK 0x00000001L
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__MASK 0x00000002L
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__MASK 0x00000004L
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__MASK 0x00000008L
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__MASK 0x00000010L
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__MASK 0x00000020L
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__MASK 0x00000040L
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__MASK 0x00000080L
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__MASK 0x00000100L
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__MASK 0x00000200L
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__MASK 0x00000400L
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__MASK 0x00000800L
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__MASK 0x00001000L
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__MASK 0x00002000L
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__MASK 0x00004000L
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__MASK 0x00008000L
+#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__MASK 0x00010000L
+//SYSHUBMMREGIND_SYSHUB_HP_TIMER
+#define SYSHUBMMREGIND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__MASK 0xFFFFFFFFL
+//SYSHUBMMREGIND_SYSHUB_SCRATCH
+#define SYSHUBMMREGIND_SYSHUB_SCRATCH__SCRATCH__MASK 0xFFFFFFFFL
+//SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__MASK 0x80000000L
+//SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK
+#define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__MASK 0x0000FFFFL
+//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__MASK 0x00008000L
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__MASK 0x00010000L
+//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__MASK 0x00008000L
+#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__MASK 0x00010000L
+//SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L
+//SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L
+//SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+//SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
+#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_default.h
new file mode 100644
index 000000000000..8058796d658a
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_default.h
@@ -0,0 +1,22340 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _nbio_6_1_DEFAULT_HEADER
+#define _nbio_6_1_DEFAULT_HEADER
+
+
+// addressBlock: nbio_pcie_pswuscfg0_cfgdecp
+#define cfgPSWUSCFG0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_COMMAND_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_REVISION_ID_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_LATENCY_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_HEADER_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_BIST_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_IO_BASE_LIMIT_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_SECONDARY_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_MEM_BASE_LIMIT_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PREF_BASE_LIMIT_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PREF_BASE_UPPER_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PREF_LIMIT_UPPER_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_CAP_PTR_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000
+#define cfgEXT_BRIDGE_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_VENDOR_CAP_LIST_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_ADAPTER_ID_W_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PMI_CAP_LIST_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PMI_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgPSWUSCFG0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgPSWUSCFG0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgPSWUSCFG0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_LINK_CAP_DEFAULT 0x00011c03
+#define cfgPSWUSCFG0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgPSWUSCFG0_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_LINK_CAP2_DEFAULT 0x0000000e
+#define cfgPSWUSCFG0_LINK_CNTL2_DEFAULT 0x00000003
+#define cfgPSWUSCFG0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgPSWUSCFG0_MSI_MSG_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_SSID_CAP_LIST_DEFAULT 0x0000c800
+#define cfgPSWUSCFG0_SSID_CAP_DEFAULT 0x00000000
+#define cfgMSI_MAP_CAP_LIST_DEFAULT 0x00000000
+#define cfgMSI_MAP_CAP_DEFAULT 0x00000000
+#define cfgMSI_MAP_ADDR_LO_DEFAULT 0x00000000
+#define cfgMSI_MAP_ADDR_HI_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
+#define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
+#define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002
+#define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002
+#define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
+#define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000
+#define cfgPSWUSCFG0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
+#define cfgPSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgPSWUSCFG0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
+#define cfgPSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000
+#define cfgPSWUSCFG0_PCIE_LINK_CNTL3_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define cfgPSWUSCFG0_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
+#define cfgPSWUSCFG0_PCIE_MC_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_MC_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_MC_ADDR0_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_MC_ADDR1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_MC_RCV0_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_MC_RCV1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
+#define cfgPCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000
+#define cfgPCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
+#define cfgPSWUSCFG0_PCIE_LTR_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x38000000
+#define cfgPSWUSCFG0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+#define cfgPCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000
+#define cfgPCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000
+#define cfgPCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000
+#define cfgPCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028
+#define cfgPCIE_ESM_CAP_LIST_DEFAULT 0x00000000
+#define cfgPCIE_ESM_HEADER_1_DEFAULT 0x00000000
+#define cfgPCIE_ESM_HEADER_2_DEFAULT 0x00000000
+#define cfgPCIE_ESM_STATUS_DEFAULT 0x00000000
+#define cfgPCIE_ESM_CTRL_DEFAULT 0x00000000
+#define cfgPCIE_ESM_CAP_1_DEFAULT 0x00000000
+#define cfgPCIE_ESM_CAP_2_DEFAULT 0x00000000
+#define cfgPCIE_ESM_CAP_3_DEFAULT 0x00000000
+#define cfgPCIE_ESM_CAP_4_DEFAULT 0x00000000
+#define cfgPCIE_ESM_CAP_5_DEFAULT 0x00000000
+#define cfgPCIE_ESM_CAP_6_DEFAULT 0x00000000
+#define cfgPCIE_ESM_CAP_7_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP_DEFAULT 0x10000000
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_DEFAULT 0x00011c03
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2_DEFAULT 0x0000000e
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_SLOT_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_SLOT_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_SLOT_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS_DEFAULT 0x00000100
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf1_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP_DEFAULT 0x10000000
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP_DEFAULT 0x00011c03
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2_DEFAULT 0x0000000e
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_SLOT_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS_DEFAULT 0x00000100
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_swds_bifcfgdecp
+#define cfgBIF_CFG_DEV0_SWDS0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_SECONDARY_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_CAP_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_PIN_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_DEFAULT 0x00000062
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP_DEFAULT 0x00011c03
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS_DEFAULT 0x00002001
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP2_DEFAULT 0x0000000e
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL2_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf0_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP_DEFAULT 0x10000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP_DEFAULT 0x00011c03
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2_DEFAULT 0x0000000e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf1_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP_DEFAULT 0x10000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP_DEFAULT 0x00011c03
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2_DEFAULT 0x0000000e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf2_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP_DEFAULT 0x10000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP_DEFAULT 0x00011c03
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2_DEFAULT 0x0000000e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf3_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP_DEFAULT 0x10000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP_DEFAULT 0x00011c03
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2_DEFAULT 0x0000000e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf4_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP_DEFAULT 0x10000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP_DEFAULT 0x00011c03
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2_DEFAULT 0x0000000e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf5_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP_DEFAULT 0x10000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP_DEFAULT 0x00011c03
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2_DEFAULT 0x0000000e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf6_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP_DEFAULT 0x10000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP_DEFAULT 0x00011c03
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2_DEFAULT 0x0000000e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf7_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP_DEFAULT 0x10000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP_DEFAULT 0x00011c03
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2_DEFAULT 0x0000000e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf8_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP_DEFAULT 0x10000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP_DEFAULT 0x00011c03
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2_DEFAULT 0x0000000e
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf9_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP_DEFAULT 0x10000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP_DEFAULT 0x00011c03
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2_DEFAULT 0x0000000e
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf10_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP_DEFAULT 0x10000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP_DEFAULT 0x00011c03
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2_DEFAULT 0x0000000e
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf11_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP_DEFAULT 0x10000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP_DEFAULT 0x00011c03
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2_DEFAULT 0x0000000e
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf12_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP_DEFAULT 0x10000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP_DEFAULT 0x00011c03
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2_DEFAULT 0x0000000e
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf13_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP_DEFAULT 0x10000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP_DEFAULT 0x00011c03
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2_DEFAULT 0x0000000e
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf14_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP_DEFAULT 0x10000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP_DEFAULT 0x00011c03
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2_DEFAULT 0x0000000e
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf15_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP_DEFAULT 0x10000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP_DEFAULT 0x00011c03
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2_DEFAULT 0x0000000e
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_SYSPFVFDEC[0..767]
+#define mmMM_INDEX_DEFAULT 0x00000000
+#define mmMM_DATA_DEFAULT 0x00000000
+#define mmMM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_SYSDEC[0..767]
+#define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000
+#define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000
+#define mmPCIE_INDEX_DEFAULT 0x00000000
+#define mmPCIE_DATA_DEFAULT 0x00000000
+#define mmPCIE_INDEX2_DEFAULT 0x00000000
+#define mmPCIE_DATA2_DEFAULT 0x00000000
+#define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000
+#define mmSBIOS_SCRATCH_1_DEFAULT 0x00000000
+#define mmSBIOS_SCRATCH_2_DEFAULT 0x00000000
+#define mmSBIOS_SCRATCH_3_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_0_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_1_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_2_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_3_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_4_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_5_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_6_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_7_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_8_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_9_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_10_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_11_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_12_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_13_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_14_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_15_DEFAULT 0x00000000
+#define mmBIF_RLC_INTR_CNTL_DEFAULT 0x00000000
+#define mmBIF_VCE_INTR_CNTL_DEFAULT 0x00000000
+#define mmBIF_UVD_INTR_CNTL_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_syshub_mmreg_ind_syshubdec[32..39]
+#define mmSYSHUB_INDEX_DEFAULT 0x00000000
+#define mmSYSHUB_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_rcc_strap_BIFDEC1[13440..14975]
+#define mmRCC_DEV0_EPF0_STRAP0_DEFAULT 0x30000000
+
+
+// addressBlock: nbio_nbif_rcc_ep_dev0_BIFDEC1[13440..14975]
+#define mmEP_PCIE_SCRATCH_DEFAULT 0x00000000
+#define mmEP_PCIE_CNTL_DEFAULT 0x00000100
+#define mmEP_PCIE_INT_CNTL_DEFAULT 0x00000000
+#define mmEP_PCIE_INT_STATUS_DEFAULT 0x00000000
+#define mmEP_PCIE_RX_CNTL2_DEFAULT 0x00000000
+#define mmEP_PCIE_BUS_CNTL_DEFAULT 0x00000080
+#define mmEP_PCIE_CFG_CNTL_DEFAULT 0x00000000
+#define mmEP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a
+#define mmEP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000
+#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0
+#define mmEP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a
+#define mmEP_PCIE_PME_CONTROL_DEFAULT 0x00000000
+#define mmEP_PCIEP_RESERVED_DEFAULT 0x00000000
+#define mmEP_PCIE_TX_CNTL_DEFAULT 0x00000000
+#define mmEP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000
+#define mmEP_PCIE_ERR_CNTL_DEFAULT 0x00000500
+#define mmEP_PCIE_RX_CNTL_DEFAULT 0x01000000
+#define mmEP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_rcc_dwn_dev0_BIFDEC1[13440..14975]
+#define mmDN_PCIE_RESERVED_DEFAULT 0x00000000
+#define mmDN_PCIE_SCRATCH_DEFAULT 0x00000000
+#define mmDN_PCIE_CNTL_DEFAULT 0x00000000
+#define mmDN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000
+#define mmDN_PCIE_RX_CNTL2_DEFAULT 0x00000000
+#define mmDN_PCIE_BUS_CNTL_DEFAULT 0x00000080
+#define mmDN_PCIE_CFG_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_rcc_dwnp_dev0_BIFDEC1[13440..14975]
+#define mmPCIE_ERR_CNTL_DEFAULT 0x00000500
+#define mmPCIE_RX_CNTL_DEFAULT 0x00000000
+#define mmPCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
+#define mmPCIE_LC_CNTL2_DEFAULT 0x00000000
+#define mmPCIEP_STRAP_MISC_DEFAULT 0x00000000
+#define mmLTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_rcc_pf_0_BIFPFVFDEC1[13440..14975]
+#define mmRCC_PF_0_0_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_PF_0_0_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_PF_0_0_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_rcc_pf_0_BIFDEC1[13440..14975]
+#define mmRCC_ERR_INT_CNTL_DEFAULT 0x00000000
+#define mmRCC_BACO_CNTL_MISC_DEFAULT 0x00000000
+#define mmRCC_RESET_EN_DEFAULT 0x00008000
+#define mmRCC_VDM_SUPPORT_DEFAULT 0x00000000
+#define mmRCC_PEER_REG_RANGE0_DEFAULT 0xffff0000
+#define mmRCC_PEER_REG_RANGE1_DEFAULT 0xffff0000
+#define mmRCC_BUS_CNTL_DEFAULT 0x00000000
+#define mmRCC_CONFIG_CNTL_DEFAULT 0x00000000
+#define mmRCC_CONFIG_F0_BASE_DEFAULT 0x00000000
+#define mmRCC_CONFIG_APER_SIZE_DEFAULT 0x00000000
+#define mmRCC_CONFIG_REG_APER_SIZE_DEFAULT 0x00000000
+#define mmRCC_XDMA_LO_DEFAULT 0x00000000
+#define mmRCC_XDMA_HI_DEFAULT 0x00000000
+#define mmRCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000
+#define mmRCC_BUSNUM_CNTL1_DEFAULT 0x00000000
+#define mmRCC_BUSNUM_LIST0_DEFAULT 0x00000000
+#define mmRCC_BUSNUM_LIST1_DEFAULT 0x00000000
+#define mmRCC_BUSNUM_CNTL2_DEFAULT 0x00000000
+#define mmRCC_CAPTURE_HOST_BUSNUM_DEFAULT 0x00000000
+#define mmRCC_HOST_BUSNUM_DEFAULT 0x00000000
+#define mmRCC_PEER0_FB_OFFSET_HI_DEFAULT 0x00000000
+#define mmRCC_PEER0_FB_OFFSET_LO_DEFAULT 0x00000000
+#define mmRCC_PEER1_FB_OFFSET_HI_DEFAULT 0x00000000
+#define mmRCC_PEER1_FB_OFFSET_LO_DEFAULT 0x00000000
+#define mmRCC_PEER2_FB_OFFSET_HI_DEFAULT 0x00000000
+#define mmRCC_PEER2_FB_OFFSET_LO_DEFAULT 0x00000000
+#define mmRCC_PEER3_FB_OFFSET_HI_DEFAULT 0x00000000
+#define mmRCC_PEER3_FB_OFFSET_LO_DEFAULT 0x00000000
+#define mmRCC_CMN_LINK_CNTL_DEFAULT 0x00400000
+#define mmRCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000
+#define mmRCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000
+#define mmRCC_MH_ARB_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_BIFDEC1[13440..14975]
+#define mmBIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000
+#define mmBUS_CNTL_DEFAULT 0x00000000
+#define mmBIF_SCRATCH0_DEFAULT 0x00000000
+#define mmBIF_SCRATCH1_DEFAULT 0x00000000
+#define mmBX_RESET_EN_DEFAULT 0x00010003
+#define mmMM_CFGREGS_CNTL_DEFAULT 0x00000000
+#define mmBX_RESET_CNTL_DEFAULT 0x00000000
+#define mmINTERRUPT_CNTL_DEFAULT 0x00000000
+#define mmINTERRUPT_CNTL2_DEFAULT 0x00000000
+#define mmCLKREQB_PAD_CNTL_DEFAULT 0x000008e0
+#define mmBIF_FEATURES_CONTROL_MISC_DEFAULT 0x00000000
+#define mmBIF_DOORBELL_CNTL_DEFAULT 0x00000000
+#define mmBIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_FB_EN_DEFAULT 0x00000000
+#define mmBIF_BUSY_DELAY_CNTR_DEFAULT 0x0000003f
+#define mmBIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000
+#define mmBIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000
+#define mmBACO_CNTL_DEFAULT 0x00000000
+#define mmBIF_BACO_EXIT_TIME0_DEFAULT 0x00000100
+#define mmBIF_BACO_EXIT_TIMER1_DEFAULT 0x00000200
+#define mmBIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300
+#define mmBIF_BACO_EXIT_TIMER3_DEFAULT 0x00000500
+#define mmBIF_BACO_EXIT_TIMER4_DEFAULT 0x00000400
+#define mmMEM_TYPE_CNTL_DEFAULT 0x00000000
+#define mmSMU_BIF_VDDGFX_PWR_STATUS_DEFAULT 0x00000000
+#define mmBIF_VDDGFX_GFX0_LOWER_DEFAULT 0xc0008000
+#define mmBIF_VDDGFX_GFX0_UPPER_DEFAULT 0x0000cffc
+#define mmBIF_VDDGFX_GFX1_LOWER_DEFAULT 0xc0028000
+#define mmBIF_VDDGFX_GFX1_UPPER_DEFAULT 0x00031ffc
+#define mmBIF_VDDGFX_GFX2_LOWER_DEFAULT 0xc0034000
+#define mmBIF_VDDGFX_GFX2_UPPER_DEFAULT 0x00037ffc
+#define mmBIF_VDDGFX_GFX3_LOWER_DEFAULT 0xc003c000
+#define mmBIF_VDDGFX_GFX3_UPPER_DEFAULT 0x0003e1fc
+#define mmBIF_VDDGFX_GFX4_LOWER_DEFAULT 0xc003ec00
+#define mmBIF_VDDGFX_GFX4_UPPER_DEFAULT 0x0003f1fc
+#define mmBIF_VDDGFX_GFX5_LOWER_DEFAULT 0xc003fc00
+#define mmBIF_VDDGFX_GFX5_UPPER_DEFAULT 0x0003fffc
+#define mmBIF_VDDGFX_RSV1_LOWER_DEFAULT 0x00000000
+#define mmBIF_VDDGFX_RSV1_UPPER_DEFAULT 0x00000000
+#define mmBIF_VDDGFX_RSV2_LOWER_DEFAULT 0x00000000
+#define mmBIF_VDDGFX_RSV2_UPPER_DEFAULT 0x00000000
+#define mmBIF_VDDGFX_RSV3_LOWER_DEFAULT 0x00000000
+#define mmBIF_VDDGFX_RSV3_UPPER_DEFAULT 0x00000000
+#define mmBIF_VDDGFX_RSV4_LOWER_DEFAULT 0x00000000
+#define mmBIF_VDDGFX_RSV4_UPPER_DEFAULT 0x00000000
+#define mmBIF_VDDGFX_FB_CMP_DEFAULT 0x00000000
+#define mmBIF_DOORBELL_GBLAPER1_LOWER_DEFAULT 0x80000780
+#define mmBIF_DOORBELL_GBLAPER1_UPPER_DEFAULT 0x000007fc
+#define mmBIF_DOORBELL_GBLAPER2_LOWER_DEFAULT 0x80000800
+#define mmBIF_DOORBELL_GBLAPER2_UPPER_DEFAULT 0x0000087c
+#define mmREMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c
+#define mmREMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858
+#define mmBIF_RB_CNTL_DEFAULT 0x00000000
+#define mmBIF_RB_BASE_DEFAULT 0x00000000
+#define mmBIF_RB_RPTR_DEFAULT 0x00000000
+#define mmBIF_RB_WPTR_DEFAULT 0x00000000
+#define mmBIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmBIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmMAILBOX_INDEX_DEFAULT 0x00000000
+#define mmBIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
+#define mmBIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
+#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
+#define mmBIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0
+#define mmBIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031
+#define mmBIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007
+#define mmBIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_BIFPFVFDEC1
+#define mmBIF_BX_PF0_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_PF0_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_PF0_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_PF0_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_PF0_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_gdc_GDCDEC[14976..15487]
+#define mmNGDC_SDP_PORT_CTRL_DEFAULT 0x0000000f
+#define mmSHUB_REGS_IF_CTL_DEFAULT 0x00000000
+#define mmNGDC_RESERVED_0_DEFAULT 0x00000000
+#define mmNGDC_RESERVED_1_DEFAULT 0x00000000
+#define mmNGDC_SDP_PORT_CTRL_SOCCLK_DEFAULT 0x0000000f
+#define mmBIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000
+#define mmBIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000
+#define mmBIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000
+#define mmBIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000
+#define mmBIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000
+#define mmS2A_MISC_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_rcc_pf_0_BIFDEC2
+#define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_PF_0_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_PF_0_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_PF_0_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_PF_0_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_PF_0_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_PF_0_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_PF_0_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_gdc_GDCDEC
+#define smnGDC1_NGDC_SDP_PORT_CTRL_DEFAULT 0x0000000f
+#define smnGDC1_SHUB_REGS_IF_CTL_DEFAULT 0x00000000
+#define smnGDC1_NGDC_RESERVED_0_DEFAULT 0x00000000
+#define smnGDC1_NGDC_RESERVED_1_DEFAULT 0x00000000
+#define smnGDC1_NGDC_SDP_PORT_CTRL_SOCCLK_DEFAULT 0x0000000f
+#define smnGDC1_BIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000
+#define smnGDC1_BIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000
+#define smnGDC1_BIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000
+#define smnGDC1_BIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000
+#define smnGDC1_BIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000
+#define smnGDC1_S2A_MISC_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_syshub_mmreg_direct_syshubdirect
+#define smnSYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100
+#define smnSYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL_DEFAULT 0x20200000
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL_DEFAULT 0x20200000
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL_DEFAULT 0x20200000
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL_DEFAULT 0x20200000
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL_DEFAULT 0x20200000
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL_DEFAULT 0x20200000
+#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL_DEFAULT 0x00082000
+#define smnSYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_SYSHUB_HP_TIMER_DEFAULT 0x00000100
+#define smnSYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK_DEFAULT 0x00000080
+#define smnSYSHUB_MMREG_DIRECT_SYSHUB_SCRATCH_DEFAULT 0x00000040
+#define smnSYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100
+#define smnSYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL_DEFAULT 0x20200000
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL_DEFAULT 0x20200000
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL_DEFAULT 0x20200000
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL_DEFAULT 0x20200000
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL_DEFAULT 0x20200000
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL_DEFAULT 0x20200000
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL_DEFAULT 0x20200000
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL_DEFAULT 0x20200000
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL_DEFAULT 0x20200000
+#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL_DEFAULT 0x20200000
+#define smnSYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK_DEFAULT 0x00000080
+#define smnSYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_NIC400_0_AMIB_2_FN_MOD_BM_ISS_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_NIC400_1_AMIB_3_FN_MOD_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_NIC400_1_AMIB_4_FN_MOD_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD_DEFAULT 0x00000000
+#define smnSYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_nbif_sion_SIONDEC
+#define smnSION_CL0_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL0_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL0_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL0_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL0_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL0_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL0_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL0_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL0_Req_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL0_Req_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL0_Req_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL0_Req_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL0_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL0_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL0_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL0_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL0_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL0_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL0_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL0_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL1_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL1_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL1_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL1_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL1_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL1_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL1_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL1_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL1_Req_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL1_Req_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL1_Req_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL1_Req_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL1_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL1_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL1_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL1_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL1_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL1_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL1_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL1_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL2_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL2_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL2_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL2_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL2_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL2_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL2_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL2_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL2_Req_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL2_Req_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL2_Req_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL2_Req_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL2_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL2_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL2_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL2_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL2_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL2_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL2_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL2_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL3_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL3_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL3_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL3_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL3_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL3_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL3_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL3_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL3_Req_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL3_Req_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL3_Req_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL3_Req_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL3_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL3_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL3_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL3_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL3_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL3_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL3_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL3_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL4_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL4_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL4_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL4_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL4_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL4_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL4_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL4_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL4_Req_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL4_Req_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL4_Req_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL4_Req_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL4_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL4_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL4_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL4_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL4_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL4_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL4_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL4_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL5_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL5_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL5_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL5_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL5_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL5_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL5_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL5_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL5_Req_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL5_Req_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL5_Req_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL5_Req_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL5_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL5_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL5_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL5_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL5_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL5_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL5_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL5_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CNTL_REG0_DEFAULT 0x00000000
+#define smnSION_CNTL_REG1_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_gdc_rst_GDCRST_DEC
+#define smnSHUB_PF_FLR_RST_DEFAULT 0x00000000
+#define smnSHUB_GFX_DRV_VPU_RST_DEFAULT 0x00000000
+#define smnSHUB_LINK_RESET_DEFAULT 0x00000000
+#define smnSHUB_PF0_VF_FLR_RST_DEFAULT 0x00000000
+#define smnSHUB_HARD_RST_CTRL_DEFAULT 0x0000001b
+#define smnSHUB_SOFT_RST_CTRL_DEFAULT 0x00000009
+#define smnSHUB_SDP_PORT_RST_DEFAULT 0x00000000
+#define smnSHUB_RST_MISC_TRL_DEFAULT 0x00100001
+
+
+// addressBlock: nbio_nbif_gdc_ras_gdc_ras_regblk
+#define smnGDC_RAS_LEAF0_CTRL_DEFAULT 0x00000000
+#define smnGDC_RAS_LEAF1_CTRL_DEFAULT 0x00000000
+#define smnGDC_RAS_LEAF2_CTRL_DEFAULT 0x00000000
+#define smnGDC_RAS_LEAF3_CTRL_DEFAULT 0x00000000
+#define smnGDC_RAS_LEAF4_CTRL_DEFAULT 0x00000000
+#define smnGDC_RAS_LEAF5_CTRL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_swds_bifcfgdecp
+#define smnBIF_CFG_DEV0_SWDS1_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_SECONDARY_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_CAP_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_SWDS1_INTERRUPT_PIN_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PMI_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PMI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_CAP_DEFAULT 0x00000062
+#define smnBIF_CFG_DEV0_SWDS1_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_SWDS1_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_LINK_CAP_DEFAULT 0x00011c03
+#define smnBIF_CFG_DEV0_SWDS1_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_LINK_STATUS_DEFAULT 0x00002001
+#define smnBIF_CFG_DEV0_SWDS1_SLOT_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_SLOT_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_SLOT_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_DEVICE_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_LINK_CAP2_DEFAULT 0x0000000e
+#define smnBIF_CFG_DEV0_SWDS1_LINK_CNTL2_DEFAULT 0x00000003
+#define smnBIF_CFG_DEV0_SWDS1_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_SLOT_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_SLOT_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_SLOT_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_SSID_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_SSID_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_SYSPFVFDEC
+#define smnBIF_BX_PF3_MM_INDEX_DEFAULT 0x00000000
+#define smnBIF_BX_PF3_MM_DATA_DEFAULT 0x00000000
+#define smnBIF_BX_PF3_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_SYSDEC
+#define smnBIF_BX_PF1_SYSHUB_INDEX_OVLP_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_SYSHUB_DATA_OVLP_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_PCIE_INDEX_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_PCIE_DATA_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_PCIE_INDEX2_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_PCIE_DATA2_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_SBIOS_SCRATCH_0_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_SBIOS_SCRATCH_1_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_SBIOS_SCRATCH_2_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_SBIOS_SCRATCH_3_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIOS_SCRATCH_0_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIOS_SCRATCH_1_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIOS_SCRATCH_2_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIOS_SCRATCH_3_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIOS_SCRATCH_4_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIOS_SCRATCH_5_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIOS_SCRATCH_6_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIOS_SCRATCH_7_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIOS_SCRATCH_8_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIOS_SCRATCH_9_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIOS_SCRATCH_10_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIOS_SCRATCH_11_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIOS_SCRATCH_12_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIOS_SCRATCH_13_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIOS_SCRATCH_14_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIOS_SCRATCH_15_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_RLC_INTR_CNTL_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_VCE_INTR_CNTL_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_UVD_INTR_CNTL_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_rcc_strap_BIFDEC1
+#define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x30000000
+
+
+// addressBlock: nbio_nbif_rcc_pf_0_BIFPFVFDEC1
+#define smnRCC_PF_0_1_RCC_ERR_LOG_DEFAULT 0x00000000
+#define smnRCC_PF_0_1_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define smnRCC_PF_0_1_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define smnRCC_PF_0_1_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define smnRCC_PF_0_1_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_BIFDEC1
+#define smnBIF_BX_PF1_BIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BUS_CNTL_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_SCRATCH0_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_SCRATCH1_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BX_RESET_EN_DEFAULT 0x00010003
+#define smnBIF_BX_PF1_MM_CFGREGS_CNTL_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BX_RESET_CNTL_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_INTERRUPT_CNTL_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_INTERRUPT_CNTL2_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_CLKREQB_PAD_CNTL_DEFAULT 0x000008e0
+#define smnBIF_BX_PF1_BIF_FEATURES_CONTROL_MISC_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_DOORBELL_CNTL_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_FB_EN_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_BUSY_DELAY_CNTR_DEFAULT 0x0000003f
+#define smnBIF_BX_PF1_BIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BACO_CNTL_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_BACO_EXIT_TIME0_DEFAULT 0x00000100
+#define smnBIF_BX_PF1_BIF_BACO_EXIT_TIMER1_DEFAULT 0x00000200
+#define smnBIF_BX_PF1_BIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300
+#define smnBIF_BX_PF1_BIF_BACO_EXIT_TIMER3_DEFAULT 0x00000500
+#define smnBIF_BX_PF1_BIF_BACO_EXIT_TIMER4_DEFAULT 0x00000400
+#define smnBIF_BX_PF1_MEM_TYPE_CNTL_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER_DEFAULT 0xc0008000
+#define smnBIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER_DEFAULT 0x0000cffc
+#define smnBIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER_DEFAULT 0xc0028000
+#define smnBIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER_DEFAULT 0x00031ffc
+#define smnBIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER_DEFAULT 0xc0034000
+#define smnBIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER_DEFAULT 0x00037ffc
+#define smnBIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER_DEFAULT 0xc003c000
+#define smnBIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER_DEFAULT 0x0003e1fc
+#define smnBIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER_DEFAULT 0xc003ec00
+#define smnBIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER_DEFAULT 0x0003f1fc
+#define smnBIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER_DEFAULT 0xc003fc00
+#define smnBIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER_DEFAULT 0x0003fffc
+#define smnBIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_VDDGFX_FB_CMP_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER_DEFAULT 0x80000780
+#define smnBIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER_DEFAULT 0x000007fc
+#define smnBIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER_DEFAULT 0x80000800
+#define smnBIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER_DEFAULT 0x0000087c
+#define smnBIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c
+#define smnBIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858
+#define smnBIF_BX_PF1_BIF_RB_CNTL_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_RB_BASE_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_RB_RPTR_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_RB_WPTR_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_MAILBOX_INDEX_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
+#define smnBIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
+#define smnBIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
+#define smnBIF_BX_PF1_BIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0
+#define smnBIF_BX_PF1_BIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031
+#define smnBIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007
+#define smnBIF_BX_PF1_BIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_BIFPFVFDEC1
+#define smnBIF_BX_PF1_BIF_BME_STATUS_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define smnBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define smnBIF_BX_PF1_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_rcc_shadow_reg_shadowdec
+#define smnSHADOW_COMMAND_DEFAULT 0x00000000
+#define smnSHADOW_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnSHADOW_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnSHADOW_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
+#define smnSHADOW_IO_BASE_LIMIT_DEFAULT 0x00000000
+#define smnSHADOW_MEM_BASE_LIMIT_DEFAULT 0x00000000
+#define smnSHADOW_PREF_BASE_LIMIT_DEFAULT 0x00000000
+#define smnSHADOW_PREF_BASE_UPPER_DEFAULT 0x00000000
+#define smnSHADOW_PREF_LIMIT_UPPER_DEFAULT 0x00000000
+#define smnSHADOW_IO_BASE_LIMIT_HI_DEFAULT 0x00000000
+#define smnSHADOW_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000
+#define smnSUC_INDEX_DEFAULT 0x00000000
+#define smnSUC_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_rcc_ep_dev0_RCCPORTDEC
+#define smnRCC_EP_DEV0_1_EP_PCIE_SCRATCH_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_1_EP_PCIE_CNTL_DEFAULT 0x00000100
+#define smnRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_DEFAULT 0x00000080
+#define smnRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468
+#define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000
+#define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0
+#define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100
+#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa
+#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8
+#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096
+#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064
+#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b
+#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032
+#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019
+#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a
+#define smnRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_1_EP_PCIEP_RESERVED_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_DEFAULT 0x00000500
+#define smnRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_DEFAULT 0x01000000
+#define smnRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_rcc_dwn_dev0_RCCPORTDEC
+#define smnRCC_DWN_DEV0_1_DN_PCIE_RESERVED_DEFAULT 0x00000000
+#define smnRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_DEFAULT 0x00000000
+#define smnRCC_DWN_DEV0_1_DN_PCIE_CNTL_DEFAULT 0x00000000
+#define smnRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000
+#define smnRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_DEFAULT 0x00000000
+#define smnRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_DEFAULT 0x00000080
+#define smnRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_rcc_dwnp_dev0_RCCPORTDEC
+#define smnRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_DEFAULT 0x00000500
+#define smnRCC_DWNP_DEV0_1_PCIE_RX_CNTL_DEFAULT 0x00000000
+#define smnRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
+#define smnRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_DEFAULT 0x00000000
+#define smnRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_DEFAULT 0x00000000
+#define smnRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_rcc_strap_rcc_strap_internal
+#define smnRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x30000000
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_SUMDEC
+#define smnSUM_INDEX_DEFAULT 0x00000000
+#define smnSUM_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_misc_bif_misc_regblk
+#define smnMISC_SCRATCH_DEFAULT 0x00000000
+#define smnINTR_LINE_POLARITY_DEFAULT 0x00000000
+#define smnINTR_LINE_ENABLE_DEFAULT 0x00000000
+#define smnOUTSTANDING_VC_ALLOC_DEFAULT 0x6f06c0cf
+#define smnBIFC_MISC_CTRL0_DEFAULT 0x08000004
+#define smnBIFC_MISC_CTRL1_DEFAULT 0x10108c04
+#define smnBIFC_BME_ERR_LOG_DEFAULT 0x00000000
+#define smnBIFC_RCCBIH_BME_ERR_LOG_DEFAULT 0x00000000
+#define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_DEFAULT 0x00000000
+#define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_DEFAULT 0x00000000
+#define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_DEFAULT 0x00000000
+#define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_DEFAULT 0x00000000
+#define smnNBIF_VWIRE_CTRL_DEFAULT 0x00000000
+#define smnNBIF_SMN_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000
+#define smnNBIF_SMN_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000
+#define smnNBIF_SMN_VWR_VCHG_TRIG_DEFAULT 0x00000000
+#define smnNBIF_SMN_VWR_WTRIG_CNTL_DEFAULT 0x00000000
+#define smnNBIF_SMN_VWR_VCHG_DIS_CTRL_1_DEFAULT 0x00000000
+#define smnNBIF_MGCG_CTRL_LCLK_DEFAULT 0x00000080
+#define smnNBIF_DS_CTRL_LCLK_DEFAULT 0x01000000
+#define smnSMN_MST_CNTL0_DEFAULT 0x00000001
+#define smnSMN_MST_EP_CNTL1_DEFAULT 0x00000000
+#define smnSMN_MST_EP_CNTL2_DEFAULT 0x00000000
+#define smnNBIF_SDP_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000
+#define smnNBIF_SDP_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000
+#define smnNBIF_SDP_VWR_VCHG_RST_CTRL1_DEFAULT 0x00000000
+#define smnNBIF_SDP_VWR_VCHG_TRIG_DEFAULT 0x00000000
+#define smnBME_DUMMY_CNTL_0_DEFAULT 0x0000aaaa
+#define smnBIFC_THT_CNTL_DEFAULT 0x00000222
+#define smnBIFC_HSTARB_CNTL_DEFAULT 0x00000000
+#define smnBIFC_GSI_CNTL_DEFAULT 0x000017c0
+#define smnBIFC_PCIEFUNC_CNTL_DEFAULT 0x00000000
+#define smnBIFC_SDP_CNTL_0_DEFAULT 0x3f3f3f3f
+#define smnBIFC_SDP_CNTL_1_DEFAULT 0x00000000
+#define smnBIFC_PERF_CNTL_0_DEFAULT 0x00000000
+#define smnBIFC_PERF_CNTL_1_DEFAULT 0x00000000
+#define smnBIFC_PERF_CNT_MMIO_RD_DEFAULT 0x00000000
+#define smnBIFC_PERF_CNT_MMIO_WR_DEFAULT 0x00000000
+#define smnBIFC_PERF_CNT_DMA_RD_DEFAULT 0x00000000
+#define smnBIFC_PERF_CNT_DMA_WR_DEFAULT 0x00000000
+#define smnNBIF_REGIF_ERRSET_CTRL_DEFAULT 0x00000000
+#define smnSMN_MST_EP_CNTL3_DEFAULT 0x00000000
+#define smnSMN_MST_EP_CNTL4_DEFAULT 0x00000000
+#define smnSMN_MST_CNTL1_DEFAULT 0x00000000
+#define smnSMN_MST_EP_CNTL5_DEFAULT 0x00000000
+#define smnBIF_SELFRING_BUFFER_VID_DEFAULT 0x0000605f
+#define smnBIF_SELFRING_VECTOR_CNTL_DEFAULT 0x00000000
+#define smnBIF_GMI_WRR_WEIGHT_DEFAULT 0x00040404
+
+
+// addressBlock: nbio_nbif_rcc_pfc_amdgfx_RCCPFCDEC
+#define smnRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_rcc_pfc_amdgfxaz_RCCPFCDEC
+#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_rst_bif_rst_regblk
+#define smnHARD_RST_CTRL_DEFAULT 0xb0000055
+#define smnRSMU_SOFT_RST_CTRL_DEFAULT 0x90000000
+#define smnSELF_SOFT_RST_DEFAULT 0x00000000
+#define smnBIF_GFX_DRV_VPU_RST_DEFAULT 0x00000000
+#define smnBIF_RST_MISC_CTRL_DEFAULT 0x000e0648
+#define smnBIF_RST_MISC_CTRL2_DEFAULT 0x00000000
+#define smnBIF_RST_MISC_CTRL3_DEFAULT 0x00104900
+#define smnBIF_RST_GFXVF_FLR_IDLE_DEFAULT 0x00000000
+#define smnDEV0_PF0_FLR_RST_CTRL_DEFAULT 0x8206a0a9
+#define smnDEV0_PF1_FLR_RST_CTRL_DEFAULT 0x02060009
+#define smnDEV0_PF2_FLR_RST_CTRL_DEFAULT 0x02060009
+#define smnDEV0_PF3_FLR_RST_CTRL_DEFAULT 0x02060009
+#define smnDEV0_PF4_FLR_RST_CTRL_DEFAULT 0x02060009
+#define smnDEV0_PF5_FLR_RST_CTRL_DEFAULT 0x02060009
+#define smnDEV0_PF6_FLR_RST_CTRL_DEFAULT 0x02060009
+#define smnDEV0_PF7_FLR_RST_CTRL_DEFAULT 0x02060009
+#define smnBIF_INST_RESET_INTR_STS_DEFAULT 0x00000000
+#define smnBIF_PF_FLR_INTR_STS_DEFAULT 0x00000000
+#define smnBIF_D3HOTD0_INTR_STS_DEFAULT 0x00000000
+#define smnBIF_POWER_INTR_STS_DEFAULT 0x00000000
+#define smnBIF_PF_DSTATE_INTR_STS_DEFAULT 0x00000000
+#define smnBIF_PF0_VF_FLR_INTR_STS_DEFAULT 0x00000000
+#define smnBIF_INST_RESET_INTR_MASK_DEFAULT 0x00000000
+#define smnBIF_PF_FLR_INTR_MASK_DEFAULT 0x00000000
+#define smnBIF_D3HOTD0_INTR_MASK_DEFAULT 0x000000ff
+#define smnBIF_POWER_INTR_MASK_DEFAULT 0x00000000
+#define smnBIF_PF_DSTATE_INTR_MASK_DEFAULT 0x00000000
+#define smnBIF_PF0_VF_FLR_INTR_MASK_DEFAULT 0x00000000
+#define smnBIF_PF_FLR_RST_DEFAULT 0x00000000
+#define smnBIF_PF0_VF_FLR_RST_DEFAULT 0x00000000
+#define smnBIF_DEV0_PF0_DSTATE_VALUE_DEFAULT 0x00000000
+#define smnBIF_DEV0_PF1_DSTATE_VALUE_DEFAULT 0x00000000
+#define smnBIF_DEV0_PF2_DSTATE_VALUE_DEFAULT 0x00000000
+#define smnBIF_DEV0_PF3_DSTATE_VALUE_DEFAULT 0x00000000
+#define smnBIF_DEV0_PF4_DSTATE_VALUE_DEFAULT 0x00000000
+#define smnBIF_DEV0_PF5_DSTATE_VALUE_DEFAULT 0x00000000
+#define smnBIF_DEV0_PF6_DSTATE_VALUE_DEFAULT 0x00000000
+#define smnBIF_DEV0_PF7_DSTATE_VALUE_DEFAULT 0x00000000
+#define smnDEV0_PF0_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define smnDEV0_PF1_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define smnDEV0_PF2_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define smnDEV0_PF3_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define smnDEV0_PF4_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define smnDEV0_PF5_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define smnDEV0_PF6_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define smnDEV0_PF7_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define smnBIF_PORT0_DSTATE_VALUE_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_ras_bif_ras_regblk
+#define smnBIF_RAS_LEAF0_CTRL_DEFAULT 0x00000000
+#define smnBIF_RAS_LEAF1_CTRL_DEFAULT 0x00000000
+#define smnBIF_RAS_LEAF2_CTRL_DEFAULT 0x00000000
+#define smnBIF_RAS_MISC_CTRL_DEFAULT 0x00000000
+#define smnBIF_IOHUB_RAS_IH_CNTL_DEFAULT 0x00000000
+#define smnBIF_RAS_VWR_FROM_IOHUB_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_1_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_CAP_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PMI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_1_DEVICE_CAP_DEFAULT 0x10000000
+#define smnBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_LINK_CAP_DEFAULT 0x00011c03
+#define smnBIF_CFG_DEV0_EPF0_1_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_1_DEVICE_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_LINK_CAP2_DEFAULT 0x0000000e
+#define smnBIF_CFG_DEV0_EPF0_1_LINK_CNTL2_DEFAULT 0x00000003
+#define smnBIF_CFG_DEV0_EPF0_1_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_SLOT_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_SLOT_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_SLOT_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS_DEFAULT 0x00000100
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf1_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF1_1_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_CAP_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PMI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF1_1_DEVICE_CAP_DEFAULT 0x10000000
+#define smnBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_LINK_CAP_DEFAULT 0x00011c03
+#define smnBIF_CFG_DEV0_EPF1_1_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF1_1_DEVICE_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_LINK_CAP2_DEFAULT 0x0000000e
+#define smnBIF_CFG_DEV0_EPF1_1_LINK_CNTL2_DEFAULT 0x00000003
+#define smnBIF_CFG_DEV0_EPF1_1_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_SLOT_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_SLOT_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_SLOT_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS_DEFAULT 0x00000100
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf0_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP_DEFAULT 0x10000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP_DEFAULT 0x00011c03
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2_DEFAULT 0x0000000e
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2_DEFAULT 0x00000003
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_SLOT_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_SLOT_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_SLOT_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf1_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP_DEFAULT 0x10000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP_DEFAULT 0x00011c03
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2_DEFAULT 0x0000000e
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2_DEFAULT 0x00000003
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_SLOT_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_SLOT_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_SLOT_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf2_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP_DEFAULT 0x10000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP_DEFAULT 0x00011c03
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2_DEFAULT 0x0000000e
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2_DEFAULT 0x00000003
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_SLOT_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_SLOT_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_SLOT_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf3_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP_DEFAULT 0x10000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP_DEFAULT 0x00011c03
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2_DEFAULT 0x0000000e
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2_DEFAULT 0x00000003
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_SLOT_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_SLOT_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_SLOT_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf4_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP_DEFAULT 0x10000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP_DEFAULT 0x00011c03
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2_DEFAULT 0x0000000e
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2_DEFAULT 0x00000003
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_SLOT_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_SLOT_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_SLOT_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf5_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP_DEFAULT 0x10000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP_DEFAULT 0x00011c03
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2_DEFAULT 0x0000000e
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2_DEFAULT 0x00000003
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_SLOT_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_SLOT_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_SLOT_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf6_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP_DEFAULT 0x10000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP_DEFAULT 0x00011c03
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2_DEFAULT 0x0000000e
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2_DEFAULT 0x00000003
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_SLOT_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_SLOT_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_SLOT_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf7_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP_DEFAULT 0x10000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP_DEFAULT 0x00011c03
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2_DEFAULT 0x0000000e
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2_DEFAULT 0x00000003
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_SLOT_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_SLOT_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_SLOT_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf8_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP_DEFAULT 0x10000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP_DEFAULT 0x00011c03
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2_DEFAULT 0x0000000e
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2_DEFAULT 0x00000003
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_SLOT_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_SLOT_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_SLOT_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf9_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP_DEFAULT 0x10000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP_DEFAULT 0x00011c03
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2_DEFAULT 0x0000000e
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2_DEFAULT 0x00000003
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_SLOT_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_SLOT_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_SLOT_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf10_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP_DEFAULT 0x10000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP_DEFAULT 0x00011c03
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2_DEFAULT 0x0000000e
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2_DEFAULT 0x00000003
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_SLOT_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_SLOT_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_SLOT_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf11_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP_DEFAULT 0x10000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP_DEFAULT 0x00011c03
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2_DEFAULT 0x0000000e
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2_DEFAULT 0x00000003
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_SLOT_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_SLOT_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_SLOT_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf12_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP_DEFAULT 0x10000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP_DEFAULT 0x00011c03
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2_DEFAULT 0x0000000e
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2_DEFAULT 0x00000003
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_SLOT_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_SLOT_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_SLOT_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf13_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP_DEFAULT 0x10000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP_DEFAULT 0x00011c03
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2_DEFAULT 0x0000000e
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2_DEFAULT 0x00000003
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_SLOT_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_SLOT_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_SLOT_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf14_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP_DEFAULT 0x10000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP_DEFAULT 0x00011c03
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2_DEFAULT 0x0000000e
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2_DEFAULT 0x00000003
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_SLOT_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_SLOT_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_SLOT_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf15_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP_DEFAULT 0x10000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP_DEFAULT 0x00011c03
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2_DEFAULT 0x0000000e
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2_DEFAULT 0x00000003
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_SLOT_CAP2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_SLOT_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_SLOT_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_pciemsix_amdgfx_MSIXTDEC
+#define smnPCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_pciemsix_amdgfx_MSIXPDEC
+#define smnPCIEMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_pcie_pswusp0_pciedir_p
+#define smnPCIEP_RESERVED_DEFAULT 0x00000000
+#define smnPCIEP_SCRATCH_DEFAULT 0x00000000
+#define smnPCIEP_PORT_CNTL_DEFAULT 0x00010009
+#define smnPCIE_TX_CNTL_DEFAULT 0x00508000
+#define smnPCIE_TX_REQUESTER_ID_DEFAULT 0x00000000
+#define smnPCIE_TX_VENDOR_SPECIFIC_DEFAULT 0x00000000
+#define smnPCIE_TX_REQUEST_NUM_CNTL_DEFAULT 0x02000000
+#define smnPCIE_TX_SEQ_DEFAULT 0x00000000
+#define smnPCIE_TX_REPLAY_DEFAULT 0x00900003
+#define smnPCIE_TX_ACK_LATENCY_LIMIT_DEFAULT 0x00000000
+#define smnPCIE_TX_CREDITS_ADVT_P_DEFAULT 0x00000000
+#define smnPCIE_TX_CREDITS_ADVT_NP_DEFAULT 0x00000000
+#define smnPCIE_TX_CREDITS_ADVT_CPL_DEFAULT 0x00000000
+#define smnPCIE_TX_CREDITS_INIT_P_DEFAULT 0x00000000
+#define smnPCIE_TX_CREDITS_INIT_NP_DEFAULT 0x00000000
+#define smnPCIE_TX_CREDITS_INIT_CPL_DEFAULT 0x00000000
+#define smnPCIE_TX_CREDITS_STATUS_DEFAULT 0x00000000
+#define smnPCIE_TX_CREDITS_FCU_THRESHOLD_DEFAULT 0x03330333
+#define smnPCIE_P_PORT_LANE_STATUS_DEFAULT 0x00000000
+#define smnPCIE_FC_P_DEFAULT 0x00000208
+#define smnPCIE_FC_NP_DEFAULT 0x00000202
+#define smnPCIE_FC_CPL_DEFAULT 0x00000000
+#define smnPSWUSP0_PCIE_ERR_CNTL_DEFAULT 0x00000500
+#define smnPSWUSP0_PCIE_RX_CNTL_DEFAULT 0x01084000
+#define smnPCIE_RX_EXPECTED_SEQNUM_DEFAULT 0x00000000
+#define smnPCIE_RX_VENDOR_SPECIFIC_DEFAULT 0x00000000
+#define smnPCIE_RX_CNTL3_DEFAULT 0x00000000
+#define smnPCIE_RX_CREDITS_ALLOCATED_P_DEFAULT 0x00000000
+#define smnPCIE_RX_CREDITS_ALLOCATED_NP_DEFAULT 0x00000000
+#define smnPCIE_RX_CREDITS_ALLOCATED_CPL_DEFAULT 0x00000000
+#define smnPCIEP_ERROR_INJECT_PHYSICAL_DEFAULT 0x00000000
+#define smnPCIEP_ERROR_INJECT_TRANSACTION_DEFAULT 0x00000000
+#define smnPCIEP_SRIOV_PRIV_CTRL_DEFAULT 0x00000000
+#define smnPCIEP_NAK_COUNTER_DEFAULT 0x00000000
+#define smnPCIE_LC_CNTL_DEFAULT 0x40010050
+#define smnPCIE_LC_TRAINING_CNTL_DEFAULT 0x94009880
+#define smnPCIE_LC_LINK_WIDTH_CNTL_DEFAULT 0xda800006
+#define smnPCIE_LC_N_FTS_CNTL_DEFAULT 0x00ff820c
+#define smnPSWUSP0_PCIE_LC_SPEED_CNTL_DEFAULT 0x04400100
+#define smnPCIE_LC_STATE0_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE1_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE2_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE3_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE4_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE5_DEFAULT 0x00000000
+#define smnPCIE_LINK_MANAGEMENT_CNTL2_DEFAULT 0x00000000
+#define smnPSWUSP0_PCIE_LC_CNTL2_DEFAULT 0x96180280
+#define smnPCIE_LC_BW_CHANGE_CNTL_DEFAULT 0x00000000
+#define smnPCIE_LC_CDR_CNTL_DEFAULT 0x01018060
+#define smnPCIE_LC_LANE_CNTL_DEFAULT 0x00000000
+#define smnPCIE_LC_CNTL3_DEFAULT 0x2850a020
+#define smnPCIE_LC_CNTL4_DEFAULT 0x0340048c
+#define smnPCIE_LC_CNTL5_DEFAULT 0x40410b2c
+#define smnPCIE_LC_FORCE_COEFF_DEFAULT 0x00080000
+#define smnPCIE_LC_BEST_EQ_SETTINGS_DEFAULT 0x00000000
+#define smnPCIE_LC_FORCE_EQ_REQ_COEFF_DEFAULT 0x00000000
+#define smnPCIE_LC_CNTL6_DEFAULT 0x8a000010
+#define smnPCIE_LC_CNTL7_DEFAULT 0x8000020e
+#define smnPCIE_LINK_MANAGEMENT_STATUS_DEFAULT 0x00000000
+#define smnPCIE_LINK_MANAGEMENT_MASK_DEFAULT 0x00003fff
+#define smnPCIE_LINK_MANAGEMENT_CNTL_DEFAULT 0x00000000
+#define smnPCIEP_STRAP_LC_DEFAULT 0x00000000
+#define smnPSWUSP0_PCIEP_STRAP_MISC_DEFAULT 0x00000000
+#define smnPCIE_LC_L1_PM_SUBSTATE_DEFAULT 0x00540000
+#define smnPCIE_LC_L1_PM_SUBSTATE2_DEFAULT 0x00000000
+#define smnPCIE_LC_PORT_ORDER_DEFAULT 0x00000000
+#define smnPCIEP_BCH_ECC_CNTL_DEFAULT 0x00000100
+
+
+// addressBlock: nbio_pcie_pciedir
+#define smnPCIE_RESERVED_DEFAULT 0x00000000
+#define smnPCIE_SCRATCH_DEFAULT 0x00000000
+#define smnPCIE_RX_NUM_NAK_DEFAULT 0x00000000
+#define smnPCIE_RX_NUM_NAK_GENERATED_DEFAULT 0x00000000
+#define smnPCIE_CNTL_DEFAULT 0x80e31000
+#define smnPCIE_CONFIG_CNTL_DEFAULT 0x0800010f
+#define smnPCIE_TX_TRACKING_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIE_TX_TRACKING_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIE_TX_TRACKING_CTRL_STATUS_DEFAULT 0x00000000
+#define smnPCIE_BW_BY_UNITID_DEFAULT 0x00000000
+#define smnPCIE_CNTL2_DEFAULT 0x0e000109
+#define smnPCIE_RX_CNTL2_DEFAULT 0x00000000
+#define smnPCIE_TX_F0_ATTR_CNTL_DEFAULT 0x00000000
+#define smnPCIE_TX_SWUS_ATTR_CNTL_DEFAULT 0x00000000
+#define smnPCIE_CI_CNTL_DEFAULT 0x00000010
+#define smnPCIE_BUS_CNTL_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE6_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE7_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE8_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE9_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE10_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE11_DEFAULT 0x00000000
+#define smnPCIE_LC_STATUS1_DEFAULT 0x00000000
+#define smnPCIE_LC_STATUS2_DEFAULT 0x00000000
+#define smnPCIE_WPR_CNTL_DEFAULT 0x00000005
+#define smnPCIE_RX_LAST_TLP0_DEFAULT 0x00000000
+#define smnPCIE_RX_LAST_TLP1_DEFAULT 0x00000000
+#define smnPCIE_RX_LAST_TLP2_DEFAULT 0x00000000
+#define smnPCIE_RX_LAST_TLP3_DEFAULT 0x00000000
+#define smnPCIE_TX_LAST_TLP0_DEFAULT 0x00000000
+#define smnPCIE_TX_LAST_TLP1_DEFAULT 0x00000000
+#define smnPCIE_TX_LAST_TLP2_DEFAULT 0x00000000
+#define smnPCIE_TX_LAST_TLP3_DEFAULT 0x00000000
+#define smnPCIE_I2C_REG_ADDR_EXPAND_DEFAULT 0x00000000
+#define smnPCIE_I2C_REG_DATA_DEFAULT 0x00000000
+#define smnPCIE_CFG_CNTL_DEFAULT 0x00000000
+#define smnPCIE_LC_PM_CNTL_DEFAULT 0x76543210
+#define smnPCIE_LC_PORT_ORDER_CNTL_DEFAULT 0x00000000
+#define smnPCIE_P_CNTL_DEFAULT 0x00010000
+#define smnPCIE_P_BUF_STATUS_DEFAULT 0x00000000
+#define smnPCIE_P_DECODER_STATUS_DEFAULT 0x00000000
+#define smnPCIE_P_MISC_STATUS_DEFAULT 0x00000000
+#define smnPCIE_P_RCV_L0S_FTS_DET_DEFAULT 0x000000ff
+#define smnPCIE_RX_AD_DEFAULT 0x00000002
+#define smnPCIE_SDP_CTRL_DEFAULT 0x00000002
+#define smnPCIE_SDP_SWUS_SLV_ATTR_CTRL_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT_CNTL_DEFAULT 0x00000000
+#define smnPCIE_PERF_CNTL_TXCLK_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT0_TXCLK_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT1_TXCLK_DEFAULT 0x00000000
+#define smnPCIE_PERF_CNTL_MST_R_CLK_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT0_MST_R_CLK_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT1_MST_R_CLK_DEFAULT 0x00000000
+#define smnPCIE_PERF_CNTL_MST_C_CLK_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT0_MST_C_CLK_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT1_MST_C_CLK_DEFAULT 0x00000000
+#define smnPCIE_PERF_CNTL_SLV_R_CLK_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT0_SLV_R_CLK_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT1_SLV_R_CLK_DEFAULT 0x00000000
+#define smnPCIE_PERF_CNTL_SLV_S_C_CLK_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT0_SLV_S_C_CLK_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT1_SLV_S_C_CLK_DEFAULT 0x00000000
+#define smnPCIE_PERF_CNTL_SLV_NS_C_CLK_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT0_SLV_NS_C_CLK_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT1_SLV_NS_C_CLK_DEFAULT 0x00000000
+#define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL_DEFAULT 0x00000000
+#define smnPCIE_PERF_CNTL_EVENT1_PORT_SEL_DEFAULT 0x00000000
+#define smnPCIE_PERF_CNTL_TXCLK2_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT0_TXCLK2_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT1_TXCLK2_DEFAULT 0x00000000
+#define smnPCIE_PRBS_CLR_DEFAULT 0x00000000
+#define smnPCIE_PRBS_STATUS1_DEFAULT 0x00000000
+#define smnPCIE_PRBS_STATUS2_DEFAULT 0x00000000
+#define smnPCIE_PRBS_FREERUN_DEFAULT 0x00000000
+#define smnPCIE_PRBS_MISC_DEFAULT 0x00000000
+#define smnPCIE_PRBS_USER_PATTERN_DEFAULT 0x00000000
+#define smnPCIE_PRBS_LO_BITCNT_DEFAULT 0x00000000
+#define smnPCIE_PRBS_HI_BITCNT_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_0_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_1_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_2_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_3_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_4_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_5_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_6_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_7_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_8_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_9_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_10_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_11_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_12_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_13_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_14_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_15_DEFAULT 0x00000000
+#define smnSWRST_COMMAND_STATUS_DEFAULT 0x00000000
+#define smnSWRST_GENERAL_CONTROL_DEFAULT 0x02001002
+#define smnSWRST_COMMAND_0_DEFAULT 0x00000000
+#define smnSWRST_COMMAND_1_DEFAULT 0x04000000
+#define smnSWRST_CONTROL_0_DEFAULT 0x5600ff00
+#define smnSWRST_CONTROL_1_DEFAULT 0xc220ffff
+#define smnSWRST_CONTROL_2_DEFAULT 0x00000000
+#define smnSWRST_CONTROL_3_DEFAULT 0x00000000
+#define smnSWRST_CONTROL_4_DEFAULT 0x5c00ff01
+#define smnSWRST_CONTROL_5_DEFAULT 0xfe20ffff
+#define smnSWRST_CONTROL_6_DEFAULT 0x000007ff
+#define smnSWRST_EP_COMMAND_0_DEFAULT 0x00000000
+#define smnSWRST_EP_CONTROL_0_DEFAULT 0x00000500
+#define smnCPM_CONTROL_DEFAULT 0x00803e00
+#define smnSMN_APERTURE_ID_A_DEFAULT 0x00000000
+#define smnSMN_APERTURE_ID_B_DEFAULT 0x00000000
+#define smnRSMU_MASTER_CONTROL_DEFAULT 0x00000000
+#define smnRSMU_SLAVE_CONTROL_DEFAULT 0x00000001
+#define smnRSMU_POWER_GATING_CONTROL_DEFAULT 0x00000800
+#define smnRSMU_BIOS_TIMER_CMD_DEFAULT 0x00000000
+#define smnRSMU_BIOS_TIMER_CNTL_DEFAULT 0x00000064
+#define smnLNCNT_CONTROL_DEFAULT 0x00000000
+#define smnCFG_LNC_WINDOW_REGISTER_DEFAULT 0x00000000
+#define smnLNCNT_QUAN_THRD_DEFAULT 0x00000000
+#define smnLNCNT_WEIGHT_DEFAULT 0x00000000
+#define smnLNC_TOTAL_WACC_REGISTER_DEFAULT 0x00000000
+#define smnLNC_BW_WACC_REGISTER_DEFAULT 0x00000000
+#define smnLNC_CMN_WACC_REGISTER_DEFAULT 0x00000000
+#define smnSMU_INT_PIN_SHARING_PORT_INDICATOR_DEFAULT 0x00000000
+#define smnSMU_PCIE_FENCED1_REG_DEFAULT 0x00000000
+#define smnSMU_PCIE_FENCED2_REG_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_pipe_pcs_dwc_e12mp_phy_x4_ns0_dwc_e12mp_phy_x4_ns_UP16_dwc_e12mp_phy_x4_ns_UP16_mem_map
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_LO_DEFAULT 0x000074cd
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_HI_DEFAULT 0x00000733
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN_DEFAULT 0x00000070
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0_DEFAULT 0x00000328
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_2_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0_DEFAULT 0x00000194
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1_DEFAULT 0x0000a000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_2_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN_DEFAULT 0x000001d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RX_TERM_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT 0x00000d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT 0x00005200
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT 0x0000894a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0_DEFAULT 0x00000025
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT 0x00000d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT 0x00005200
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT 0x0000894a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0_DEFAULT 0x00000025
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC_DEFAULT 0x00000028
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC_DEFAULT 0x00000028
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG_DEFAULT 0x0000000e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_CONFIG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R0_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R1_DEFAULT 0x00001f4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R2_DEFAULT 0x0000297c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R3_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R4_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R5_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R6_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R7_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R9_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R10_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R11_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R12_DEFAULT 0x00000750
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R13_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R14_DEFAULT 0x00000212
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R15_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R16_DEFAULT 0x00004214
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R17_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R18_DEFAULT 0x00001f50
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R19_DEFAULT 0x0000297d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R20_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R21_DEFAULT 0x00000140
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R22_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R23_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R24_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R25_DEFAULT 0x00002800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R26_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R28_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R29_DEFAULT 0x00006800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R31_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R0_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R1_DEFAULT 0x00000745
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R2_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R3_DEFAULT 0x00000227
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R4_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R5_DEFAULT 0x00004227
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R6_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R7_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R8_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R9_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R10_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R11_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R13_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R14_DEFAULT 0x00000015
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R15_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R16_DEFAULT 0x00000746
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R17_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R18_DEFAULT 0x00000236
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R19_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R20_DEFAULT 0x00004236
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R21_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R22_DEFAULT 0x000001b3
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R23_DEFAULT 0x00000177
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R24_DEFAULT 0x000055dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R25_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R26_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R27_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R28_DEFAULT 0x00002800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R29_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R31_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R0_DEFAULT 0x00007000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R1_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R2_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R4_DEFAULT 0x00000173
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R5_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R6_DEFAULT 0x0000024a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R7_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R8_DEFAULT 0x0000424a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R9_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R10_DEFAULT 0x000055fb
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R12_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R13_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R14_DEFAULT 0x00000174
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R15_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R16_DEFAULT 0x00000254
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R17_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R18_DEFAULT 0x00004254
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R19_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R20_DEFAULT 0x00005612
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R21_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R22_DEFAULT 0x00006c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R23_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R24_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R25_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R26_DEFAULT 0x00000179
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R27_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R28_DEFAULT 0x00000260
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R29_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R30_DEFAULT 0x00004260
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R31_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R0_DEFAULT 0x00005625
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R1_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R2_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R3_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R4_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R5_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R7_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R8_DEFAULT 0x00007000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R9_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R10_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R11_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R12_DEFAULT 0x00000175
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R13_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R14_DEFAULT 0x00000272
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R15_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R16_DEFAULT 0x00004272
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R17_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R18_DEFAULT 0x00005642
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R19_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R20_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R22_DEFAULT 0x00000176
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R23_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R24_DEFAULT 0x0000027c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R25_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R26_DEFAULT 0x0000427c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R27_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R28_DEFAULT 0x00005659
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R29_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R30_DEFAULT 0x00006c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R31_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R0_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R2_DEFAULT 0x0000017a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R3_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R4_DEFAULT 0x00000288
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R5_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R6_DEFAULT 0x00004288
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R7_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R8_DEFAULT 0x00001973
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R9_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R10_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R11_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R12_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R13_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R14_DEFAULT 0x00001974
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R15_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R16_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R17_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R18_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R19_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R20_DEFAULT 0x00001979
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R21_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R22_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R23_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R24_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R25_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R26_DEFAULT 0x00001975
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R27_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R29_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R0_DEFAULT 0x00001976
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R1_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R3_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R4_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R6_DEFAULT 0x0000197a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R9_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R12_DEFAULT 0x00001973
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R13_DEFAULT 0x00002f4b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R14_DEFAULT 0x00001974
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R15_DEFAULT 0x00002f4c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R16_DEFAULT 0x00001979
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R17_DEFAULT 0x00002f51
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R18_DEFAULT 0x00001975
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R19_DEFAULT 0x00002f4d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R20_DEFAULT 0x00001976
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R21_DEFAULT 0x00002f4e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R22_DEFAULT 0x0000197a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R23_DEFAULT 0x00002f52
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R24_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R25_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R26_DEFAULT 0x00001f4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R27_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R29_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R0_DEFAULT 0x00001f50
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R1_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R3_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R4_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R6_DEFAULT 0x00001f42
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R9_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R12_DEFAULT 0x00001f43
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R13_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R14_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R15_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R16_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R18_DEFAULT 0x00001f44
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R19_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R20_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R21_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R24_DEFAULT 0x00001f29
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R25_DEFAULT 0x000042f1
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R26_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R27_DEFAULT 0x0000a3a0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R28_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R29_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R30_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R0_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R2_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R4_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R5_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R6_DEFAULT 0x000001b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R8_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R10_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R12_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R13_DEFAULT 0x00000749
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R14_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R15_DEFAULT 0x000002f5
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R16_DEFAULT 0x00005329
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R17_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R18_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R19_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R20_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R21_DEFAULT 0x000001b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R23_DEFAULT 0x000019b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R24_DEFAULT 0x00002f53
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R25_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R27_DEFAULT 0x000001b3
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R28_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R29_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R31_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R1_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R3_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R5_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R6_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R7_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R9_DEFAULT 0x00008660
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R10_DEFAULT 0x00004b15
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R11_DEFAULT 0x00008270
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R12_DEFAULT 0x00004b0e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R13_DEFAULT 0x0000530f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R14_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R15_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R16_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R18_DEFAULT 0x00004b1c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R19_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R20_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R21_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R22_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R24_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R25_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R26_DEFAULT 0x00004313
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R27_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R28_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R29_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R30_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R31_DEFAULT 0x0000301d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R0_DEFAULT 0x00004325
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R1_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R2_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R3_DEFAULT 0x00003054
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R4_DEFAULT 0x00005327
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R5_DEFAULT 0x00007445
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R6_DEFAULT 0x0000430e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R7_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R8_DEFAULT 0x00005309
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R9_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R10_DEFAULT 0x00008670
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R11_DEFAULT 0x00004b2d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R12_DEFAULT 0x0000532e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R13_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R14_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R15_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R16_DEFAULT 0x0000ffe8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R17_DEFAULT 0x0000701d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R18_DEFAULT 0x00004b35
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R19_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R20_DEFAULT 0x0000532d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R21_DEFAULT 0x0000741d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R22_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R23_DEFAULT 0x0000074a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R24_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R25_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R26_DEFAULT 0x00003323
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R27_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R29_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R30_DEFAULT 0x0000532a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R31_DEFAULT 0x00001f2a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R0_DEFAULT 0x00004377
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R1_DEFAULT 0x0000075e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R4_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R5_DEFAULT 0x00001f09
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R8_DEFAULT 0x0000080c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R9_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R10_DEFAULT 0x000070cd
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R11_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R12_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R13_DEFAULT 0x00002f05
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R14_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R15_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R16_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R17_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R19_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R20_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R21_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R22_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R23_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R24_DEFAULT 0x0000435a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R25_DEFAULT 0x00005357
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R26_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R27_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R28_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R29_DEFAULT 0x0000435c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R30_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R31_DEFAULT 0x00000600
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R0_DEFAULT 0x00001f09
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R1_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R2_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R3_DEFAULT 0x0000608d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R4_DEFAULT 0x0000700d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R5_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R6_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R7_DEFAULT 0x00002f05
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R8_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R9_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R10_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R11_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R12_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R13_DEFAULT 0x0000436f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R14_DEFAULT 0x0000536c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R15_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R17_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R18_DEFAULT 0x00004371
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R19_DEFAULT 0x00000705
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R20_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R21_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R23_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R24_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R25_DEFAULT 0x00000147
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R27_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R29_DEFAULT 0x00001f6b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R30_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R31_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R0_DEFAULT 0x00000200
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R1_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R2_DEFAULT 0x00000042
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R3_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R4_DEFAULT 0x0000007e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R5_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R7_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R9_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R10_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R11_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R12_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R13_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R15_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R16_DEFAULT 0x00003636
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R17_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R18_DEFAULT 0x0000608c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R19_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R20_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R21_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R22_DEFAULT 0x0000702c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R23_DEFAULT 0x00002969
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R24_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R25_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R26_DEFAULT 0x00001f67
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R27_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R28_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R29_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R30_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R31_DEFAULT 0x00003c02
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R0_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R2_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R3_DEFAULT 0x00007060
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R4_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R5_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R6_DEFAULT 0x00001f2a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R7_DEFAULT 0x000043a9
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R8_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R9_DEFAULT 0x00001f68
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R10_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R11_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R12_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R13_DEFAULT 0x00001f6c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R14_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R15_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R16_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R17_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R18_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R19_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R20_DEFAULT 0x00004fa0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R22_DEFAULT 0x00007828
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R23_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R24_DEFAULT 0x000036dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R25_DEFAULT 0x00001f2b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R26_DEFAULT 0x000043bc
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R27_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R28_DEFAULT 0x00001f69
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R29_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R30_DEFAULT 0x00001f6d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R31_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R0_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R1_DEFAULT 0x00007818
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R2_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R3_DEFAULT 0x0000124a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R4_DEFAULT 0x00001f2b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R5_DEFAULT 0x000043c7
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R6_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R7_DEFAULT 0x00001f6a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R8_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R9_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R10_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R11_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R12_DEFAULT 0x00002806
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R13_DEFAULT 0x00001f6e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R14_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R15_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R16_DEFAULT 0x000000c6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R17_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R18_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R19_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R20_DEFAULT 0x00003000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R22_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R23_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R24_DEFAULT 0x0000b6b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R25_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R26_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R27_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R28_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R29_DEFAULT 0x00001f6a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R30_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R31_DEFAULT 0x00001f6e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R0_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R1_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R2_DEFAULT 0x00000084
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R3_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R4_DEFAULT 0x0000b000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R5_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R6_DEFAULT 0x00008080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R7_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R8_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R9_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R10_DEFAULT 0x000074d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R11_DEFAULT 0x00004bef
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R12_DEFAULT 0x00000711
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R14_DEFAULT 0x000053f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R15_DEFAULT 0x00002f11
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R16_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R17_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R18_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R20_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R21_DEFAULT 0x00003c46
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R22_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R24_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R25_DEFAULT 0x00007020
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R26_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R27_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R28_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R29_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R30_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R31_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R0_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R1_DEFAULT 0x00004408
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R2_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R3_DEFAULT 0x00000fe0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R4_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R5_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R6_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R7_DEFAULT 0x0000540d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R8_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R9_DEFAULT 0x00000fc0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R10_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R11_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R12_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R13_DEFAULT 0x000030c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R14_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R15_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R16_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R17_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R18_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R19_DEFAULT 0x000030c5
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R20_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R21_DEFAULT 0x00000036
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R22_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R23_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R24_DEFAULT 0x000030dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R25_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R27_DEFAULT 0x00007435
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R28_DEFAULT 0x00004c23
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R29_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R30_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R31_DEFAULT 0x00004c38
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R0_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R2_DEFAULT 0x00005438
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R4_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R5_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R8_DEFAULT 0x0000442c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R9_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R10_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R11_DEFAULT 0x0000542e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R12_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R13_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R14_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R15_DEFAULT 0x0000703d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R16_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R17_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R18_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R19_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R20_DEFAULT 0x00004c36
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R21_DEFAULT 0x00005438
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R22_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R23_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R24_DEFAULT 0x00006082
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R25_DEFAULT 0x00006182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R26_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R27_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R29_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R31_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R0_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R1_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R2_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R3_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R4_DEFAULT 0x000030dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R5_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R6_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R7_DEFAULT 0x00007435
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R8_DEFAULT 0x00004c4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R9_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R10_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R11_DEFAULT 0x00004c64
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R12_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R14_DEFAULT 0x00005464
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R16_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R17_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R18_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R20_DEFAULT 0x00004458
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R21_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R22_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R23_DEFAULT 0x0000545a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R24_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R25_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R26_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R27_DEFAULT 0x0000703d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R28_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R29_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R30_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R31_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R0_DEFAULT 0x00004c62
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R1_DEFAULT 0x00005464
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R2_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R3_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R4_DEFAULT 0x00006082
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R5_DEFAULT 0x00006182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R6_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R9_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R12_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R14_DEFAULT 0x00008647
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R16_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R17_DEFAULT 0x00001989
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R18_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R20_DEFAULT 0x0000601d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R21_DEFAULT 0x000030d3
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R22_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R23_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R24_DEFAULT 0x00001986
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R25_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R26_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R27_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R28_DEFAULT 0x000030d4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R29_DEFAULT 0x0000613d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R30_DEFAULT 0x000030d1
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R31_DEFAULT 0x00003025
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R0_DEFAULT 0x00006115
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R1_DEFAULT 0x00007052
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R2_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R3_DEFAULT 0x00007021
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R4_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R5_DEFAULT 0x00004c87
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R6_DEFAULT 0x0000548d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R7_DEFAULT 0x00007414
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R8_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R9_DEFAULT 0x00007052
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R10_DEFAULT 0x000074d3
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R11_DEFAULT 0x00004c93
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R12_DEFAULT 0x00005490
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R13_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R15_DEFAULT 0x00005495
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R16_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R17_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R18_DEFAULT 0x00005495
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R19_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R22_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R23_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R24_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R25_DEFAULT 0x00000804
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R26_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R27_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R28_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R29_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R30_DEFAULT 0x000003e0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R31_DEFAULT 0x0000116d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R0_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R1_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R2_DEFAULT 0x000030c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R4_DEFAULT 0x00000fe0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R5_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R8_DEFAULT 0x000030c3
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R9_DEFAULT 0x00007420
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R10_DEFAULT 0x00004cac
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R11_DEFAULT 0x000054c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R12_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R13_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R14_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R16_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R17_DEFAULT 0x000044b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R18_DEFAULT 0x00007434
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R19_DEFAULT 0x00004cb5
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R20_DEFAULT 0x000054c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R21_DEFAULT 0x00007412
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R22_DEFAULT 0x00004cb8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R23_DEFAULT 0x000054c1
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R24_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R25_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R26_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R27_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R28_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R29_DEFAULT 0x000044c1
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R30_DEFAULT 0x000054bf
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R31_DEFAULT 0x00007453
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R0_DEFAULT 0x00004cc7
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R1_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R2_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R3_DEFAULT 0x000054c9
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R4_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R6_DEFAULT 0x000054c9
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R7_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R9_DEFAULT 0x0000196b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R10_DEFAULT 0x00002f5a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R11_DEFAULT 0x0000196d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R12_DEFAULT 0x00002f5c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R13_DEFAULT 0x0000196c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R14_DEFAULT 0x00002f5b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R15_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R16_DEFAULT 0x00002f5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R17_DEFAULT 0x0000196f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R18_DEFAULT 0x00002f60
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R19_DEFAULT 0x00001970
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R20_DEFAULT 0x00002f61
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R21_DEFAULT 0x00001971
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R22_DEFAULT 0x00002f62
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R23_DEFAULT 0x00001972
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R24_DEFAULT 0x00002f63
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R25_DEFAULT 0x00000147
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R27_DEFAULT 0x0000075e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R29_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R31_DEFAULT 0x00000710
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R1_DEFAULT 0x00001f86
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R2_DEFAULT 0x000044e4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R3_DEFAULT 0x000054e1
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R4_DEFAULT 0x00000710
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R6_DEFAULT 0x0000078c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R8_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R9_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R10_DEFAULT 0x00000029
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R11_DEFAULT 0x00001fe3
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R12_DEFAULT 0x000044f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R13_DEFAULT 0x00001fe4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R14_DEFAULT 0x000044f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R15_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R16_DEFAULT 0x00009fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R17_DEFAULT 0x00001fe3
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R18_DEFAULT 0x000044f4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R19_DEFAULT 0x000054f7
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R20_DEFAULT 0x00000806
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R21_DEFAULT 0x000004f7
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R22_DEFAULT 0x00005500
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R23_DEFAULT 0x00001fe4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R24_DEFAULT 0x000044fa
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R25_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R26_DEFAULT 0x00000806
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R27_DEFAULT 0x000004fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R28_DEFAULT 0x00005571
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R29_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R31_DEFAULT 0x00005027
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R0_DEFAULT 0x00001f59
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R1_DEFAULT 0x00004503
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R2_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R3_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R5_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R6_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R7_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R8_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R9_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R11_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R13_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R14_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R15_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R16_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R17_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R18_DEFAULT 0x0000a080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R19_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R20_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R22_DEFAULT 0x00000741
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R23_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R24_DEFAULT 0x0000051a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R25_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R26_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R27_DEFAULT 0x0000a0c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R29_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R30_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R31_DEFAULT 0x00000742
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R0_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R1_DEFAULT 0x00000523
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R2_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R3_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R4_DEFAULT 0x0000a200
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R6_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R7_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R8_DEFAULT 0x00000743
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R9_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R10_DEFAULT 0x0000052c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R11_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R12_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R13_DEFAULT 0x0000a220
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R14_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R15_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R16_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R17_DEFAULT 0x00000744
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R18_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R19_DEFAULT 0x00000535
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R20_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R21_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R22_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R23_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R25_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R27_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R28_DEFAULT 0x0000320d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R29_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R0_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R1_DEFAULT 0x0000866c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R2_DEFAULT 0x00004d4b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R3_DEFAULT 0x0000827c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R4_DEFAULT 0x00004d46
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R5_DEFAULT 0x00005547
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R6_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R7_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R8_DEFAULT 0x00004d50
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R9_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R10_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R11_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R12_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R13_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R14_DEFAULT 0x00004549
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R15_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R16_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R17_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R18_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R19_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R20_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R21_DEFAULT 0x0000320d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R22_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R23_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R24_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R25_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R26_DEFAULT 0x000078a5
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R27_DEFAULT 0x0000744d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R28_DEFAULT 0x00004d5e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R29_DEFAULT 0x00005567
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R30_DEFAULT 0x000078a4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R31_DEFAULT 0x0000745d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R0_DEFAULT 0x00004d62
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R1_DEFAULT 0x00005563
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R2_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R3_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R4_DEFAULT 0x00004d6c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R5_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R6_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R7_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R8_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R9_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R10_DEFAULT 0x00004565
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R11_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R12_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R13_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R15_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R16_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R17_DEFAULT 0x00001f5e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R18_DEFAULT 0x00004574
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R19_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R20_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R21_DEFAULT 0x00003636
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R22_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R23_DEFAULT 0x0000608c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R24_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R25_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R26_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R27_DEFAULT 0x0000702c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R28_DEFAULT 0x00002969
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R29_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R30_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R31_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R0_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R1_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R2_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R3_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R5_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R6_DEFAULT 0x00003060
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R7_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R8_DEFAULT 0x0000647e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R9_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R10_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R11_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R12_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R13_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R14_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R15_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R16_DEFAULT 0x00000f20
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R17_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R18_DEFAULT 0x000090a0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R19_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R20_DEFAULT 0x00000999
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R22_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R23_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R24_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R25_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R27_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R28_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R29_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R30_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R31_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R0_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R1_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R2_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R3_DEFAULT 0x00002806
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R4_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R6_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R7_DEFAULT 0x00003060
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R8_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R9_DEFAULT 0x0000647e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R10_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R11_DEFAULT 0x00003fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R12_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R13_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R14_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R15_DEFAULT 0x000000c6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R16_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R17_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R18_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R20_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R21_DEFAULT 0x00003000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R22_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R23_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R24_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R25_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R26_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R28_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R29_DEFAULT 0x0000b6b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R30_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R31_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R0_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R1_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R2_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R3_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R4_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R5_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R6_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R7_DEFAULT 0x00003fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R8_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R9_DEFAULT 0x00000084
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R10_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R11_DEFAULT 0x0000b000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R12_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R13_DEFAULT 0x00008080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R14_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R15_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R16_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R17_DEFAULT 0x000030d1
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R18_DEFAULT 0x00007410
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R19_DEFAULT 0x00004dd7
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R20_DEFAULT 0x00000711
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R22_DEFAULT 0x000055d8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R23_DEFAULT 0x00002f11
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R24_DEFAULT 0x00007010
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R25_DEFAULT 0x0000611d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R26_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R27_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R29_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R30_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R31_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R0_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R1_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R3_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R4_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R6_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R9_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R12_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R13_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R14_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R15_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R16_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R17_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R18_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R19_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R20_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R21_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R22_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R23_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R24_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R25_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R26_DEFAULT 0x00005239
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R27_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R28_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R29_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R31_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R1_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R2_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R3_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R4_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R5_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R6_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R7_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R8_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R9_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R10_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R11_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R12_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R13_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R14_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R15_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R16_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R17_DEFAULT 0x0000524b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R18_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R19_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R20_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R21_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R24_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R25_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R26_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R28_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R29_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R31_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R0_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R1_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R2_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R3_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R4_DEFAULT 0x00005255
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R6_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R7_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R9_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R10_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R12_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R13_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R15_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R16_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R17_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R18_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R19_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R20_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R21_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R22_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R23_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R25_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R27_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R28_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R29_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R30_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R31_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R1_DEFAULT 0x00005261
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R3_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R4_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R5_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R6_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R9_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R12_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R13_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R14_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R16_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R18_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R19_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R20_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R21_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R24_DEFAULT 0x00005273
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R25_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R26_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R27_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R29_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R30_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R31_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R0_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R1_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R3_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R6_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R7_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R8_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R9_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R10_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R12_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R13_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R14_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R15_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R16_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R17_DEFAULT 0x0000527d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_CMN_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_DEFAULT 0x00005000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_DEFAULT 0x00005000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_LO_DEFAULT 0x000004cd
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_HI_DEFAULT 0x00003006
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN_DEFAULT 0x00000070
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0_DEFAULT 0x00000328
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_2_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0_DEFAULT 0x00000194
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1_DEFAULT 0x0000a000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_2_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN_DEFAULT 0x000001d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RX_TERM_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT 0x00000d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT 0x00005200
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT 0x0000894a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0_DEFAULT 0x00000025
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT 0x00000d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT 0x00005200
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT 0x0000894a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0_DEFAULT 0x00000025
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC_DEFAULT 0x00000028
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC_DEFAULT 0x00000028
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG_DEFAULT 0x0000000e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_CONFIG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R0_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R1_DEFAULT 0x00001f4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R2_DEFAULT 0x0000297c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R3_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R4_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R5_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R6_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R7_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R9_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R10_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R11_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R12_DEFAULT 0x00000750
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R13_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R14_DEFAULT 0x00000212
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R15_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R16_DEFAULT 0x00004214
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R17_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R18_DEFAULT 0x00001f50
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R19_DEFAULT 0x0000297d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R20_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R21_DEFAULT 0x00000140
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R22_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R23_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R24_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R25_DEFAULT 0x00002800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R26_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R28_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R29_DEFAULT 0x00006800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R31_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R0_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R1_DEFAULT 0x00000745
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R2_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R3_DEFAULT 0x00000227
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R4_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R5_DEFAULT 0x00004227
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R6_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R7_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R8_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R9_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R10_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R11_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R13_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R14_DEFAULT 0x00000015
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R15_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R16_DEFAULT 0x00000746
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R17_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R18_DEFAULT 0x00000236
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R19_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R20_DEFAULT 0x00004236
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R21_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R22_DEFAULT 0x000001b3
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R23_DEFAULT 0x00000177
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R24_DEFAULT 0x000055dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R25_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R26_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R27_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R28_DEFAULT 0x00002800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R29_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R31_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R0_DEFAULT 0x00007000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R1_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R2_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R4_DEFAULT 0x00000173
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R5_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R6_DEFAULT 0x0000024a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R7_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R8_DEFAULT 0x0000424a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R9_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R10_DEFAULT 0x000055fb
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R12_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R13_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R14_DEFAULT 0x00000174
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R15_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R16_DEFAULT 0x00000254
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R17_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R18_DEFAULT 0x00004254
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R19_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R20_DEFAULT 0x00005612
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R21_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R22_DEFAULT 0x00006c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R23_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R24_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R25_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R26_DEFAULT 0x00000179
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R27_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R28_DEFAULT 0x00000260
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R29_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R30_DEFAULT 0x00004260
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R31_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R0_DEFAULT 0x00005625
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R1_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R2_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R3_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R4_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R5_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R7_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R8_DEFAULT 0x00007000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R9_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R10_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R11_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R12_DEFAULT 0x00000175
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R13_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R14_DEFAULT 0x00000272
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R15_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R16_DEFAULT 0x00004272
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R17_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R18_DEFAULT 0x00005642
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R19_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R20_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R22_DEFAULT 0x00000176
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R23_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R24_DEFAULT 0x0000027c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R25_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R26_DEFAULT 0x0000427c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R27_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R28_DEFAULT 0x00005659
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R29_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R30_DEFAULT 0x00006c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R31_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R0_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R2_DEFAULT 0x0000017a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R3_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R4_DEFAULT 0x00000288
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R5_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R6_DEFAULT 0x00004288
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R7_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R8_DEFAULT 0x00001973
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R9_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R10_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R11_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R12_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R13_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R14_DEFAULT 0x00001974
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R15_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R16_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R17_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R18_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R19_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R20_DEFAULT 0x00001979
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R21_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R22_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R23_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R24_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R25_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R26_DEFAULT 0x00001975
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R27_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R29_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R0_DEFAULT 0x00001976
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R1_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R3_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R4_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R6_DEFAULT 0x0000197a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R9_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R12_DEFAULT 0x00001973
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R13_DEFAULT 0x00002f4b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R14_DEFAULT 0x00001974
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R15_DEFAULT 0x00002f4c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R16_DEFAULT 0x00001979
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R17_DEFAULT 0x00002f51
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R18_DEFAULT 0x00001975
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R19_DEFAULT 0x00002f4d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R20_DEFAULT 0x00001976
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R21_DEFAULT 0x00002f4e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R22_DEFAULT 0x0000197a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R23_DEFAULT 0x00002f52
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R24_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R25_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R26_DEFAULT 0x00001f4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R27_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R29_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R0_DEFAULT 0x00001f50
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R1_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R3_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R4_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R6_DEFAULT 0x00001f42
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R9_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R12_DEFAULT 0x00001f43
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R13_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R14_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R15_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R16_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R18_DEFAULT 0x00001f44
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R19_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R20_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R21_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R24_DEFAULT 0x00001f29
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R25_DEFAULT 0x000042f1
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R26_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R27_DEFAULT 0x0000a3a0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R28_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R29_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R30_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R0_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R2_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R4_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R5_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R6_DEFAULT 0x000001b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R8_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R10_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R12_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R13_DEFAULT 0x00000749
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R14_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R15_DEFAULT 0x000002f5
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R16_DEFAULT 0x00005329
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R17_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R18_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R19_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R20_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R21_DEFAULT 0x000001b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R23_DEFAULT 0x000019b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R24_DEFAULT 0x00002f53
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R25_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R27_DEFAULT 0x000001b3
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R28_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R29_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R31_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R1_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R3_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R5_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R6_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R7_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R9_DEFAULT 0x00008660
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R10_DEFAULT 0x00004b15
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R11_DEFAULT 0x00008270
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R12_DEFAULT 0x00004b0e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R13_DEFAULT 0x0000530f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R14_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R15_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R16_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R18_DEFAULT 0x00004b1c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R19_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R20_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R21_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R22_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R24_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R25_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R26_DEFAULT 0x00004313
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R27_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R28_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R29_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R30_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R31_DEFAULT 0x0000301d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R0_DEFAULT 0x00004325
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R1_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R2_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R3_DEFAULT 0x00003054
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R4_DEFAULT 0x00005327
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R5_DEFAULT 0x00007445
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R6_DEFAULT 0x0000430e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R7_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R8_DEFAULT 0x00005309
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R9_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R10_DEFAULT 0x00008670
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R11_DEFAULT 0x00004b2d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R12_DEFAULT 0x0000532e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R13_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R14_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R15_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R16_DEFAULT 0x0000ffe8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R17_DEFAULT 0x0000701d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R18_DEFAULT 0x00004b35
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R19_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R20_DEFAULT 0x0000532d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R21_DEFAULT 0x0000741d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R22_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R23_DEFAULT 0x0000074a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R24_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R25_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R26_DEFAULT 0x00003323
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R27_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R29_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R30_DEFAULT 0x0000532a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R31_DEFAULT 0x00001f2a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R0_DEFAULT 0x00004377
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R1_DEFAULT 0x0000075e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R4_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R5_DEFAULT 0x00001f09
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R8_DEFAULT 0x0000080c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R9_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R10_DEFAULT 0x000070cd
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R11_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R12_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R13_DEFAULT 0x00002f05
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R14_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R15_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R16_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R17_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R19_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R20_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R21_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R22_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R23_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R24_DEFAULT 0x0000435a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R25_DEFAULT 0x00005357
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R26_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R27_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R28_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R29_DEFAULT 0x0000435c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R30_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R31_DEFAULT 0x00000600
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R0_DEFAULT 0x00001f09
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R1_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R2_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R3_DEFAULT 0x0000608d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R4_DEFAULT 0x0000700d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R5_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R6_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R7_DEFAULT 0x00002f05
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R8_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R9_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R10_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R11_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R12_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R13_DEFAULT 0x0000436f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R14_DEFAULT 0x0000536c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R15_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R17_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R18_DEFAULT 0x00004371
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R19_DEFAULT 0x00000705
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R20_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R21_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R23_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R24_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R25_DEFAULT 0x00000147
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R27_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R29_DEFAULT 0x00001f6b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R30_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R31_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R0_DEFAULT 0x00000200
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R1_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R2_DEFAULT 0x00000042
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R3_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R4_DEFAULT 0x0000007e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R5_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R7_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R9_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R10_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R11_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R12_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R13_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R15_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R16_DEFAULT 0x00003636
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R17_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R18_DEFAULT 0x0000608c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R19_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R20_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R21_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R22_DEFAULT 0x0000702c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R23_DEFAULT 0x00002969
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R24_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R25_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R26_DEFAULT 0x00001f67
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R27_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R28_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R29_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R30_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R31_DEFAULT 0x00003c02
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R0_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R2_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R3_DEFAULT 0x00007060
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R4_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R5_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R6_DEFAULT 0x00001f2a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R7_DEFAULT 0x000043a9
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R8_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R9_DEFAULT 0x00001f68
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R10_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R11_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R12_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R13_DEFAULT 0x00001f6c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R14_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R15_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R16_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R17_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R18_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R19_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R20_DEFAULT 0x00004fa0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R22_DEFAULT 0x00007828
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R23_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R24_DEFAULT 0x000036dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R25_DEFAULT 0x00001f2b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R26_DEFAULT 0x000043bc
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R27_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R28_DEFAULT 0x00001f69
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R29_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R30_DEFAULT 0x00001f6d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R31_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R0_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R1_DEFAULT 0x00007818
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R2_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R3_DEFAULT 0x0000124a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R4_DEFAULT 0x00001f2b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R5_DEFAULT 0x000043c7
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R6_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R7_DEFAULT 0x00001f6a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R8_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R9_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R10_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R11_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R12_DEFAULT 0x00002806
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R13_DEFAULT 0x00001f6e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R14_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R15_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R16_DEFAULT 0x000000c6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R17_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R18_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R19_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R20_DEFAULT 0x00003000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R22_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R23_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R24_DEFAULT 0x0000b6b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R25_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R26_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R27_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R28_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R29_DEFAULT 0x00001f6a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R30_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R31_DEFAULT 0x00001f6e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R0_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R1_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R2_DEFAULT 0x00000084
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R3_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R4_DEFAULT 0x0000b000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R5_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R6_DEFAULT 0x00008080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R7_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R8_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R9_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R10_DEFAULT 0x000074d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R11_DEFAULT 0x00004bef
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R12_DEFAULT 0x00000711
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R14_DEFAULT 0x000053f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R15_DEFAULT 0x00002f11
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R16_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R17_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R18_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R20_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R21_DEFAULT 0x00003c46
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R22_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R24_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R25_DEFAULT 0x00007020
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R26_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R27_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R28_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R29_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R30_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R31_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R0_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R1_DEFAULT 0x00004408
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R2_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R3_DEFAULT 0x00000fe0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R4_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R5_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R6_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R7_DEFAULT 0x0000540d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R8_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R9_DEFAULT 0x00000fc0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R10_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R11_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R12_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R13_DEFAULT 0x000030c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R14_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R15_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R16_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R17_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R18_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R19_DEFAULT 0x000030c5
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R20_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R21_DEFAULT 0x00000036
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R22_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R23_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R24_DEFAULT 0x000030dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R25_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R27_DEFAULT 0x00007435
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R28_DEFAULT 0x00004c23
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R29_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R30_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R31_DEFAULT 0x00004c38
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R0_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R2_DEFAULT 0x00005438
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R4_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R5_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R8_DEFAULT 0x0000442c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R9_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R10_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R11_DEFAULT 0x0000542e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R12_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R13_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R14_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R15_DEFAULT 0x0000703d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R16_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R17_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R18_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R19_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R20_DEFAULT 0x00004c36
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R21_DEFAULT 0x00005438
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R22_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R23_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R24_DEFAULT 0x00006082
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R25_DEFAULT 0x00006182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R26_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R27_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R29_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R31_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R0_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R1_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R2_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R3_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R4_DEFAULT 0x000030dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R5_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R6_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R7_DEFAULT 0x00007435
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R8_DEFAULT 0x00004c4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R9_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R10_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R11_DEFAULT 0x00004c64
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R12_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R14_DEFAULT 0x00005464
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R16_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R17_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R18_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R20_DEFAULT 0x00004458
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R21_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R22_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R23_DEFAULT 0x0000545a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R24_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R25_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R26_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R27_DEFAULT 0x0000703d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R28_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R29_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R30_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R31_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R0_DEFAULT 0x00004c62
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R1_DEFAULT 0x00005464
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R2_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R3_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R4_DEFAULT 0x00006082
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R5_DEFAULT 0x00006182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R6_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R9_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R12_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R14_DEFAULT 0x00008647
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R16_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R17_DEFAULT 0x00001989
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R18_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R20_DEFAULT 0x0000601d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R21_DEFAULT 0x000030d3
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R22_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R23_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R24_DEFAULT 0x00001986
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R25_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R26_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R27_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R28_DEFAULT 0x000030d4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R29_DEFAULT 0x0000613d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R30_DEFAULT 0x000030d1
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R31_DEFAULT 0x00003025
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R0_DEFAULT 0x00006115
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R1_DEFAULT 0x00007052
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R2_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R3_DEFAULT 0x00007021
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R4_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R5_DEFAULT 0x00004c87
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R6_DEFAULT 0x0000548d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R7_DEFAULT 0x00007414
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R8_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R9_DEFAULT 0x00007052
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R10_DEFAULT 0x000074d3
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R11_DEFAULT 0x00004c93
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R12_DEFAULT 0x00005490
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R13_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R15_DEFAULT 0x00005495
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R16_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R17_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R18_DEFAULT 0x00005495
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R19_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R22_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R23_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R24_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R25_DEFAULT 0x00000804
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R26_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R27_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R28_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R29_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R30_DEFAULT 0x000003e0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R31_DEFAULT 0x0000116d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R0_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R1_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R2_DEFAULT 0x000030c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R4_DEFAULT 0x00000fe0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R5_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R8_DEFAULT 0x000030c3
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R9_DEFAULT 0x00007420
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R10_DEFAULT 0x00004cac
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R11_DEFAULT 0x000054c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R12_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R13_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R14_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R16_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R17_DEFAULT 0x000044b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R18_DEFAULT 0x00007434
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R19_DEFAULT 0x00004cb5
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R20_DEFAULT 0x000054c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R21_DEFAULT 0x00007412
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R22_DEFAULT 0x00004cb8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R23_DEFAULT 0x000054c1
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R24_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R25_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R26_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R27_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R28_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R29_DEFAULT 0x000044c1
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R30_DEFAULT 0x000054bf
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R31_DEFAULT 0x00007453
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R0_DEFAULT 0x00004cc7
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R1_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R2_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R3_DEFAULT 0x000054c9
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R4_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R6_DEFAULT 0x000054c9
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R7_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R9_DEFAULT 0x0000196b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R10_DEFAULT 0x00002f5a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R11_DEFAULT 0x0000196d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R12_DEFAULT 0x00002f5c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R13_DEFAULT 0x0000196c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R14_DEFAULT 0x00002f5b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R15_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R16_DEFAULT 0x00002f5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R17_DEFAULT 0x0000196f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R18_DEFAULT 0x00002f60
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R19_DEFAULT 0x00001970
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R20_DEFAULT 0x00002f61
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R21_DEFAULT 0x00001971
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R22_DEFAULT 0x00002f62
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R23_DEFAULT 0x00001972
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R24_DEFAULT 0x00002f63
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R25_DEFAULT 0x00000147
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R27_DEFAULT 0x0000075e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R29_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R31_DEFAULT 0x00000710
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R1_DEFAULT 0x00001f86
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R2_DEFAULT 0x000044e4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R3_DEFAULT 0x000054e1
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R4_DEFAULT 0x00000710
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R6_DEFAULT 0x0000078c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R8_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R9_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R10_DEFAULT 0x00000029
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R11_DEFAULT 0x00001fe3
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R12_DEFAULT 0x000044f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R13_DEFAULT 0x00001fe4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R14_DEFAULT 0x000044f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R15_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R16_DEFAULT 0x00009fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R17_DEFAULT 0x00001fe3
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R18_DEFAULT 0x000044f4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R19_DEFAULT 0x000054f7
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R20_DEFAULT 0x00000806
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R21_DEFAULT 0x000004f7
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R22_DEFAULT 0x00005500
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R23_DEFAULT 0x00001fe4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R24_DEFAULT 0x000044fa
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R25_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R26_DEFAULT 0x00000806
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R27_DEFAULT 0x000004fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R28_DEFAULT 0x00005571
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R29_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R31_DEFAULT 0x00005027
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R0_DEFAULT 0x00001f59
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R1_DEFAULT 0x00004503
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R2_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R3_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R5_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R6_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R7_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R8_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R9_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R11_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R13_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R14_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R15_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R16_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R17_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R18_DEFAULT 0x0000a080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R19_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R20_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R22_DEFAULT 0x00000741
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R23_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R24_DEFAULT 0x0000051a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R25_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R26_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R27_DEFAULT 0x0000a0c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R29_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R30_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R31_DEFAULT 0x00000742
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R0_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R1_DEFAULT 0x00000523
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R2_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R3_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R4_DEFAULT 0x0000a200
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R6_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R7_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R8_DEFAULT 0x00000743
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R9_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R10_DEFAULT 0x0000052c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R11_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R12_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R13_DEFAULT 0x0000a220
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R14_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R15_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R16_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R17_DEFAULT 0x00000744
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R18_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R19_DEFAULT 0x00000535
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R20_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R21_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R22_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R23_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R25_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R27_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R28_DEFAULT 0x0000320d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R29_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R0_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R1_DEFAULT 0x0000866c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R2_DEFAULT 0x00004d4b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R3_DEFAULT 0x0000827c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R4_DEFAULT 0x00004d46
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R5_DEFAULT 0x00005547
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R6_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R7_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R8_DEFAULT 0x00004d50
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R9_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R10_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R11_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R12_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R13_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R14_DEFAULT 0x00004549
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R15_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R16_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R17_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R18_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R19_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R20_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R21_DEFAULT 0x0000320d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R22_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R23_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R24_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R25_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R26_DEFAULT 0x000078a5
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R27_DEFAULT 0x0000744d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R28_DEFAULT 0x00004d5e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R29_DEFAULT 0x00005567
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R30_DEFAULT 0x000078a4
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R31_DEFAULT 0x0000745d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R0_DEFAULT 0x00004d62
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R1_DEFAULT 0x00005563
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R2_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R3_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R4_DEFAULT 0x00004d6c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R5_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R6_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R7_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R8_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R9_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R10_DEFAULT 0x00004565
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R11_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R12_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R13_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R15_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R16_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R17_DEFAULT 0x00001f5e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R18_DEFAULT 0x00004574
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R19_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R20_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R21_DEFAULT 0x00003636
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R22_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R23_DEFAULT 0x0000608c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R24_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R25_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R26_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R27_DEFAULT 0x0000702c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R28_DEFAULT 0x00002969
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R29_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R30_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R31_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R0_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R1_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R2_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R3_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R5_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R6_DEFAULT 0x00003060
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R7_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R8_DEFAULT 0x0000647e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R9_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R10_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R11_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R12_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R13_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R14_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R15_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R16_DEFAULT 0x00000f20
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R17_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R18_DEFAULT 0x000090a0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R19_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R20_DEFAULT 0x00000999
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R22_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R23_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R24_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R25_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R27_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R28_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R29_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R30_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R31_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R0_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R1_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R2_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R3_DEFAULT 0x00002806
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R4_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R6_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R7_DEFAULT 0x00003060
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R8_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R9_DEFAULT 0x0000647e
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R10_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R11_DEFAULT 0x00003fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R12_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R13_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R14_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R15_DEFAULT 0x000000c6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R16_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R17_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R18_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R20_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R21_DEFAULT 0x00003000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R22_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R23_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R24_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R25_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R26_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R28_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R29_DEFAULT 0x0000b6b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R30_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R31_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R0_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R1_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R2_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R3_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R4_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R5_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R6_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R7_DEFAULT 0x00003fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R8_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R9_DEFAULT 0x00000084
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R10_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R11_DEFAULT 0x0000b000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R12_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R13_DEFAULT 0x00008080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R14_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R15_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R16_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R17_DEFAULT 0x000030d1
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R18_DEFAULT 0x00007410
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R19_DEFAULT 0x00004dd7
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R20_DEFAULT 0x00000711
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R22_DEFAULT 0x000055d8
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R23_DEFAULT 0x00002f11
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R24_DEFAULT 0x00007010
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R25_DEFAULT 0x0000611d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R26_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R27_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R29_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R30_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R31_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R0_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R1_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R3_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R4_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R6_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R9_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R12_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R13_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R14_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R15_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R16_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R17_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R18_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R19_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R20_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R21_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R22_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R23_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R24_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R25_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R26_DEFAULT 0x00005239
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R27_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R28_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R29_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R31_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R1_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R2_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R3_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R4_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R5_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R6_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R7_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R8_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R9_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R10_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R11_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R12_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R13_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R14_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R15_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R16_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R17_DEFAULT 0x0000524b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R18_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R19_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R20_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R21_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R24_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R25_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R26_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R28_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R29_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R31_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R0_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R1_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R2_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R3_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R4_DEFAULT 0x00005255
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R6_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R7_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R9_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R10_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R12_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R13_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R15_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R16_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R17_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R18_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R19_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R20_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R21_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R22_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R23_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R25_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R27_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R28_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R29_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R30_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R31_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R1_DEFAULT 0x00005261
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R3_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R4_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R5_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R6_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R9_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R12_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R13_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R14_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R16_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R18_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R19_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R20_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R21_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R24_DEFAULT 0x00005273
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R25_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R26_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R27_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R29_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R30_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R31_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R0_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R1_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R3_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R6_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R7_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R8_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R9_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R10_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R12_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R13_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R14_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R15_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R16_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R17_DEFAULT 0x0000527d
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_CMN_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN_DEFAULT 0x00005000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN_DEFAULT 0x00005000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_pipe_pcs_lcu_pcie_pcs_prime_phyx4_pcs_prime_dir
+#define smnDXIO_HWDID_DEFAULT 0x00102000
+#define smnDXIO_LINKAGE_LANEGRP_DEFAULT 0x00000000
+#define smnDXIO_LINKAGE_KPDMX_DEFAULT 0x00000000
+#define smnDXIO_LINKAGE_KPMX_DEFAULT 0x00000000
+#define smnDXIO_LINKAGE_KPFIFO_DEFAULT 0x00000000
+#define smnDXIO_LINKAGE_KPNP_DEFAULT 0x00000000
+#define smnPCS_LANEGRP0_MAPPING_DEFAULT 0x00000000
+#define smnPCS_LANEGRP1_MAPPING_DEFAULT 0x00000000
+#define smnPCS_LANEGRP2_MAPPING_DEFAULT 0x00000000
+#define smnPCS_LANEGRP3_MAPPING_DEFAULT 0x00000000
+#define smnPCS_LANEGRP4_MAPPING_DEFAULT 0x00000000
+#define smnPCS_LANEGRP5_MAPPING_DEFAULT 0x00000000
+#define smnPCS_LANEGRP6_MAPPING_DEFAULT 0x00000000
+#define smnPCS_LANEGRP7_MAPPING_DEFAULT 0x00000000
+#define smnMAC_CAPABILITIES1_DEFAULT 0x00000000
+#define smnMAC_CAPABILITIES2_DEFAULT 0x00000000
+#define smnPCS_CAPABILITIES_DEFAULT 0x00000000
+#define smnPCS_EXTENDED_CAP_DEFAULT 0x000099fc
+#define smnPCS_APERTURE0_LOC_DEFAULT 0x00000000
+#define smnPCS_APERTURE0_IDX_DEFAULT 0x00000000
+#define smnPCS_APERTURE1_LOC_DEFAULT 0x00000000
+#define smnPCS_APERTURE1_IDX_DEFAULT 0x00000000
+#define smnPCS_APERTURE2_LOC_DEFAULT 0x00000000
+#define smnPCS_APERTURE2_IDX_DEFAULT 0x00000000
+#define smnPCS_APERTURE3_LOC_DEFAULT 0x00000000
+#define smnPCS_APERTURE3_IDX_DEFAULT 0x00000000
+#define smnDXIO_CFG_SOFT_RESET_DEFAULT 0x00000000
+#define smnKPX_LANE_DATA_SOFT_RESET1_DEFAULT 0x00000000
+#define smnKPX_LANE_DATA_SOFT_RESET_DEFAULT 0x00000000
+#define smnKPX_PMA_INFO_SOFT_RESET_DEFAULT 0x00000000
+#define smnPCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET_DEFAULT 0x00000000
+#define smnPCS_SOFT_RESET_DEFAULT 0x00000000
+#define smnPCS_LCU_CNTL_DEFAULT 0x00000a00
+#define smnPCS_PIPE_PER_LANE_SOFT_RESET_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_lcu_kpfifo_kpfifo0_kpfifo_dir
+#define smnKPFIFO0_PRI_TX_FIFO_HSCID_DEFAULT 0x00000000
+#define smnKPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0_DEFAULT 0x00000000
+#define smnKPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1_DEFAULT 0x00000000
+#define smnKPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2_DEFAULT 0x00000000
+#define smnKPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3_DEFAULT 0x00000000
+#define smnKPFIFO0_PCS_PMA_SOFT_RESET_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_lcu_kpnp_kpnp0_kpnp_dir
+#define smnKPNP_SNPS0_KPNP_HWSCVER_DEFAULT 0x00000000
+#define smnKPNP_SNPS0_KPNP_PHY_INFO_DEFAULT 0x00000000
+#define smnKPNP_SNPS0_KPNP_LANE_ID_DEFAULT 0x00000000
+#define smnKPNP_SNPS0_KPNP_LANE_REQ_CONTROL_DEFAULT 0x00000000
+#define smnKPNP_SNPS0_KPNP_LANE_REQ_STATUS_DEFAULT 0x00000000
+#define smnKPNP_SNPS0_KPNP_PMA_CONTROL0_DEFAULT 0x00000000
+#define smnKPNP_SNPS0_KPNP_PMA_CONTROL1_DEFAULT 0x000000b1
+#define smnKPNP_SNPS0_KPNP_PMA_CONTROL2_DEFAULT 0x00000004
+#define smnKPNP_SNPS0_KPNP_PHY_SOFT_RESET_DEFAULT 0x00000000
+#define smnKPNP_SNPS0_KPNP_LANE_SOFT_RESET_DEFAULT 0x000000ff
+#define smnKPNP_SNPS0_REG_RST_CTRL_DEFAULT 0x00000001
+
+
+// addressBlock: nbio_pipe_pcs_pcs_core0_dir
+#define smnPCS_PCIEX16_IP_IDENTITY_DEFAULT 0x00000000
+#define smnPCS_PCIEX16_GLOBAL_CONTROL0_DEFAULT 0x03f50001
+#define smnPCS_PCIEX16_GLOBAL_CONTROL1_DEFAULT 0x00000000
+#define smnPCS_PCIEX16_GLOBAL_CONTROL2_DEFAULT 0x00242078
+#define smnPCS_PCIEX16_GLOBAL_CONTROL3_DEFAULT 0x00000010
+#define smnPCS_PCIEX16_GLOBAL_CONTROL4_DEFAULT 0x00000000
+#define smnPCS_PCIEX16_GLOBAL_CONTROL5_DEFAULT 0x00000000
+#define smnPCS_PCIEX16_GLOBAL_CONTROL6_DEFAULT 0x00000000
+#define smnPCS_PCIEX16_GLOBAL_CONTROL7_DEFAULT 0x00000100
+#define smnPCS_PCIEX16_GLOBAL_CONTROL8_DEFAULT 0x00000000
+#define smnPCS_PCIEX16_LANE0_CONTROL_DEFAULT 0x00000000
+#define smnPCS_PCIEX16_LANE1_CONTROL_DEFAULT 0x00000001
+#define smnPCS_PCIEX16_LANE2_CONTROL_DEFAULT 0x00000002
+#define smnPCS_PCIEX16_LANE3_CONTROL_DEFAULT 0x00000003
+#define smnPCS_PCIEX16_LANE4_CONTROL_DEFAULT 0x00000004
+#define smnPCS_PCIEX16_LANE5_CONTROL_DEFAULT 0x00000005
+#define smnPCS_PCIEX16_LANE6_CONTROL_DEFAULT 0x00000006
+#define smnPCS_PCIEX16_LANE7_CONTROL_DEFAULT 0x00000007
+#define smnPCS_PCIEX16_LANE8_CONTROL_DEFAULT 0x00000008
+#define smnPCS_PCIEX16_LANE9_CONTROL_DEFAULT 0x00000009
+#define smnPCS_PCIEX16_LANE10_CONTROL_DEFAULT 0x0000000a
+#define smnPCS_PCIEX16_LANE11_CONTROL_DEFAULT 0x0000000b
+#define smnPCS_PCIEX16_LANE12_CONTROL_DEFAULT 0x0000000c
+#define smnPCS_PCIEX16_LANE13_CONTROL_DEFAULT 0x0000000d
+#define smnPCS_PCIEX16_LANE14_CONTROL_DEFAULT 0x0000000e
+#define smnPCS_PCIEX16_LANE15_CONTROL_DEFAULT 0x0000000f
+#define smnPCS_PCIEX16_GLOBAL_CONTROL9_DEFAULT 0x00001030
+#define smnPCS_PCIEX16_GLOBAL_CONTROL10_DEFAULT 0x00ad0208
+#define smnPCS_PCIEX16_GLOBAL_CONTROL11_DEFAULT 0x00060000
+#define smnPCS_PCIEX16_GLOBAL_CONTROL12_DEFAULT 0xc0500200
+#define smnPCS_PCIEX16_GLOBAL_CONTROL13_DEFAULT 0x20040410
+#define smnPCS_PCIEX16_GLOBAL_CONTROL14_DEFAULT 0x000f0000
+#define smnPCS_PCIEX16_GLOBAL_CONTROL15_DEFAULT 0x02022230
+#define smnPCS_PCIEX16_GLOBAL_CONTROL16_DEFAULT 0x03030310
+#define smnPCS_PCIEX16_GLOBAL_CONTROL17_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_pipe_pcs_pcs_pciex16_gaskt_pcs_pciex16_gaskt_dir
+#define smnPCS_GLOBAL_CONTROL17_DEFAULT 0x00000003
+#define smnPCS_GLOBAL_CONTROL18_DEFAULT 0x00000000
+#define smnPCS_GLOBAL_CONTROL19_DEFAULT 0x0017b919
+#define smnPCS_GLOBAL_CONTROL20_DEFAULT 0x000fb919
+#define smnPCS_GLOBAL_CONTROL21_DEFAULT 0x010d3650
+#define smnPCS_GLOBAL_CONTROL22_DEFAULT 0x00000000
+#define smnPCS_GLOBAL_CONTROL23_DEFAULT 0x17dfdfdf
+#define smnPCS_GLOBAL_CONTROL24_DEFAULT 0x00000077
+#define smnPCS_GLOBAL_CONTROL25_DEFAULT 0x00000077
+#define smnPCS_GLOBAL_CONTROL26_DEFAULT 0x30000077
+#define smnPCS_GLOBAL_CONTROL27_DEFAULT 0x111b0546
+#define smnPCS_GLOBAL_CONTROL28_DEFAULT 0x111b0546
+#define smnPCS_GLOBAL_CONTROL29_DEFAULT 0x11220550
+#define smnPCS_GLOBAL_CONTROL30_DEFAULT 0x00001800
+#define smnPCS_STATUS1_DEFAULT 0x00000000
+#define smnPCS_LANE0_CNTRL1_DEFAULT 0x00000002
+#define smnPCS_LANE1_CNTRL1_DEFAULT 0x00000002
+#define smnPCS_LANE2_CNTRL1_DEFAULT 0x00000002
+#define smnPCS_LANE3_CNTRL1_DEFAULT 0x00000002
+#define smnPCS_LANE4_CNTRL1_DEFAULT 0x00000002
+#define smnPCS_LANE5_CNTRL1_DEFAULT 0x00000002
+#define smnPCS_LANE6_CNTRL1_DEFAULT 0x00000002
+#define smnPCS_LANE7_CNTRL1_DEFAULT 0x00000002
+#define smnPCS_LANE8_CNTRL1_DEFAULT 0x00000002
+#define smnPCS_LANE9_CNTRL1_DEFAULT 0x00000002
+#define smnPCS_LANE10_CNTRL1_DEFAULT 0x00000002
+#define smnPCS_LANE11_CNTRL1_DEFAULT 0x00000002
+#define smnPCS_LANE12_CNTRL1_DEFAULT 0x00000002
+#define smnPCS_LANE13_CNTRL1_DEFAULT 0x00000002
+#define smnPCS_LANE14_CNTRL1_DEFAULT 0x00000002
+#define smnPCS_LANE15_CNTRL1_DEFAULT 0x00000002
+#define smnPCS_LANE0_COEFF1_DEFAULT 0xa6121400
+#define smnPCS_LANE1_COEFF1_DEFAULT 0xa6121400
+#define smnPCS_LANE2_COEFF1_DEFAULT 0xa6121400
+#define smnPCS_LANE3_COEFF1_DEFAULT 0xa6121400
+#define smnPCS_LANE4_COEFF1_DEFAULT 0xa6121400
+#define smnPCS_LANE5_COEFF1_DEFAULT 0xa6121400
+#define smnPCS_LANE6_COEFF1_DEFAULT 0xa6121400
+#define smnPCS_LANE7_COEFF1_DEFAULT 0xa6121400
+#define smnPCS_LANE8_COEFF1_DEFAULT 0xa6121400
+#define smnPCS_LANE9_COEFF1_DEFAULT 0xa6121400
+#define smnPCS_LANE10_COEFF1_DEFAULT 0xa6121400
+#define smnPCS_LANE11_COEFF1_DEFAULT 0xa6121400
+#define smnPCS_LANE12_COEFF1_DEFAULT 0xa6121400
+#define smnPCS_LANE13_COEFF1_DEFAULT 0xa6121400
+#define smnPCS_LANE14_COEFF1_DEFAULT 0xa6121400
+#define smnPCS_LANE15_COEFF1_DEFAULT 0xa6121400
+#define smnPCS_LANE0_COEFF2_DEFAULT 0xa6141700
+#define smnPCS_LANE1_COEFF2_DEFAULT 0xa6141700
+#define smnPCS_LANE2_COEFF2_DEFAULT 0xa6141700
+#define smnPCS_LANE3_COEFF2_DEFAULT 0xa6141700
+#define smnPCS_LANE4_COEFF2_DEFAULT 0xa6141700
+#define smnPCS_LANE5_COEFF2_DEFAULT 0xa6141700
+#define smnPCS_LANE6_COEFF2_DEFAULT 0xa6141700
+#define smnPCS_LANE7_COEFF2_DEFAULT 0xa6141700
+#define smnPCS_LANE8_COEFF2_DEFAULT 0xa6141700
+#define smnPCS_LANE9_COEFF2_DEFAULT 0xa6141700
+#define smnPCS_LANE10_COEFF2_DEFAULT 0xa6141700
+#define smnPCS_LANE11_COEFF2_DEFAULT 0xa6141700
+#define smnPCS_LANE12_COEFF2_DEFAULT 0xa6141700
+#define smnPCS_LANE13_COEFF2_DEFAULT 0xa6141700
+#define smnPCS_LANE14_COEFF2_DEFAULT 0xa6141700
+#define smnPCS_LANE15_COEFF2_DEFAULT 0xa6141700
+#define smnPCS_LANE0_COEFF3_DEFAULT 0xd02c1d00
+#define smnPCS_LANE1_COEFF3_DEFAULT 0xd02c1d00
+#define smnPCS_LANE2_COEFF3_DEFAULT 0xd02c1d00
+#define smnPCS_LANE3_COEFF3_DEFAULT 0xd02c1d00
+#define smnPCS_LANE4_COEFF3_DEFAULT 0xd02c1d00
+#define smnPCS_LANE5_COEFF3_DEFAULT 0xd02c1d00
+#define smnPCS_LANE6_COEFF3_DEFAULT 0xd02c1d00
+#define smnPCS_LANE7_COEFF3_DEFAULT 0xd02c1d00
+#define smnPCS_LANE8_COEFF3_DEFAULT 0xd02c1d00
+#define smnPCS_LANE9_COEFF3_DEFAULT 0xd02c1d00
+#define smnPCS_LANE10_COEFF3_DEFAULT 0xd02c1d00
+#define smnPCS_LANE11_COEFF3_DEFAULT 0xd02c1d00
+#define smnPCS_LANE12_COEFF3_DEFAULT 0xd02c1d00
+#define smnPCS_LANE13_COEFF3_DEFAULT 0xd02c1d00
+#define smnPCS_LANE14_COEFF3_DEFAULT 0xd02c1d00
+#define smnPCS_LANE15_COEFF3_DEFAULT 0xd02c1d00
+
+
+// addressBlock: nbio_pipe_pcs_dwc_e12mp_phy_x4_ns1_dwc_e12mp_phy_x4_ns_UP16_dwc_e12mp_phy_x4_ns_UP16_mem_map
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_IDCODE_LO_DEFAULT 0x000074cd
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_IDCODE_HI_DEFAULT 0x00000733
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN_DEFAULT 0x00000070
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0_DEFAULT 0x00000328
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_2_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0_DEFAULT 0x00000194
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1_DEFAULT 0x0000a000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_2_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN_DEFAULT 0x000001d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RX_TERM_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT 0x00000d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT 0x00005200
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT 0x0000894a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0_DEFAULT 0x00000025
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT 0x00000d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT 0x00005200
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT 0x0000894a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0_DEFAULT 0x00000025
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC_DEFAULT 0x00000028
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC_DEFAULT 0x00000028
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG_DEFAULT 0x0000000e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_CONFIG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R0_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R1_DEFAULT 0x00001f4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R2_DEFAULT 0x0000297c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R3_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R4_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R5_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R6_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R7_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R9_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R10_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R11_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R12_DEFAULT 0x00000750
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R13_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R14_DEFAULT 0x00000212
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R15_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R16_DEFAULT 0x00004214
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R17_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R18_DEFAULT 0x00001f50
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R19_DEFAULT 0x0000297d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R20_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R21_DEFAULT 0x00000140
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R22_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R23_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R24_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R25_DEFAULT 0x00002800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R26_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R28_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R29_DEFAULT 0x00006800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R31_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R0_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R1_DEFAULT 0x00000745
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R2_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R3_DEFAULT 0x00000227
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R4_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R5_DEFAULT 0x00004227
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R6_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R7_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R8_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R9_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R10_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R11_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R13_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R14_DEFAULT 0x00000015
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R15_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R16_DEFAULT 0x00000746
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R17_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R18_DEFAULT 0x00000236
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R19_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R20_DEFAULT 0x00004236
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R21_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R22_DEFAULT 0x000001b3
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R23_DEFAULT 0x00000177
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R24_DEFAULT 0x000055dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R25_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R26_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R27_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R28_DEFAULT 0x00002800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R29_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R31_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R0_DEFAULT 0x00007000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R1_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R2_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R4_DEFAULT 0x00000173
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R5_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R6_DEFAULT 0x0000024a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R7_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R8_DEFAULT 0x0000424a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R9_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R10_DEFAULT 0x000055fb
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R12_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R13_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R14_DEFAULT 0x00000174
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R15_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R16_DEFAULT 0x00000254
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R17_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R18_DEFAULT 0x00004254
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R19_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R20_DEFAULT 0x00005612
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R21_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R22_DEFAULT 0x00006c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R23_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R24_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R25_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R26_DEFAULT 0x00000179
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R27_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R28_DEFAULT 0x00000260
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R29_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R30_DEFAULT 0x00004260
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R31_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R0_DEFAULT 0x00005625
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R1_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R2_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R3_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R4_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R5_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R7_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R8_DEFAULT 0x00007000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R9_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R10_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R11_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R12_DEFAULT 0x00000175
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R13_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R14_DEFAULT 0x00000272
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R15_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R16_DEFAULT 0x00004272
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R17_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R18_DEFAULT 0x00005642
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R19_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R20_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R22_DEFAULT 0x00000176
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R23_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R24_DEFAULT 0x0000027c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R25_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R26_DEFAULT 0x0000427c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R27_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R28_DEFAULT 0x00005659
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R29_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R30_DEFAULT 0x00006c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R31_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R0_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R2_DEFAULT 0x0000017a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R3_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R4_DEFAULT 0x00000288
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R5_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R6_DEFAULT 0x00004288
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R7_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R8_DEFAULT 0x00001973
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R9_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R10_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R11_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R12_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R13_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R14_DEFAULT 0x00001974
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R15_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R16_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R17_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R18_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R19_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R20_DEFAULT 0x00001979
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R21_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R22_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R23_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R24_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R25_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R26_DEFAULT 0x00001975
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R27_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R29_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R0_DEFAULT 0x00001976
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R1_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R3_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R4_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R6_DEFAULT 0x0000197a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R9_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R12_DEFAULT 0x00001973
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R13_DEFAULT 0x00002f4b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R14_DEFAULT 0x00001974
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R15_DEFAULT 0x00002f4c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R16_DEFAULT 0x00001979
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R17_DEFAULT 0x00002f51
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R18_DEFAULT 0x00001975
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R19_DEFAULT 0x00002f4d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R20_DEFAULT 0x00001976
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R21_DEFAULT 0x00002f4e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R22_DEFAULT 0x0000197a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R23_DEFAULT 0x00002f52
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R24_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R25_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R26_DEFAULT 0x00001f4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R27_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R29_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R0_DEFAULT 0x00001f50
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R1_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R3_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R4_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R6_DEFAULT 0x00001f42
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R9_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R12_DEFAULT 0x00001f43
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R13_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R14_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R15_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R16_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R18_DEFAULT 0x00001f44
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R19_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R20_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R21_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R24_DEFAULT 0x00001f29
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R25_DEFAULT 0x000042f1
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R26_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R27_DEFAULT 0x0000a3a0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R28_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R29_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R30_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R0_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R2_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R4_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R5_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R6_DEFAULT 0x000001b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R8_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R10_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R12_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R13_DEFAULT 0x00000749
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R14_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R15_DEFAULT 0x000002f5
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R16_DEFAULT 0x00005329
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R17_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R18_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R19_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R20_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R21_DEFAULT 0x000001b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R23_DEFAULT 0x000019b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R24_DEFAULT 0x00002f53
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R25_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R27_DEFAULT 0x000001b3
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R28_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R29_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R31_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R1_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R3_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R5_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R6_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R7_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R9_DEFAULT 0x00008660
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R10_DEFAULT 0x00004b15
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R11_DEFAULT 0x00008270
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R12_DEFAULT 0x00004b0e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R13_DEFAULT 0x0000530f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R14_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R15_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R16_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R18_DEFAULT 0x00004b1c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R19_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R20_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R21_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R22_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R24_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R25_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R26_DEFAULT 0x00004313
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R27_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R28_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R29_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R30_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R31_DEFAULT 0x0000301d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R0_DEFAULT 0x00004325
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R1_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R2_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R3_DEFAULT 0x00003054
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R4_DEFAULT 0x00005327
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R5_DEFAULT 0x00007445
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R6_DEFAULT 0x0000430e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R7_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R8_DEFAULT 0x00005309
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R9_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R10_DEFAULT 0x00008670
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R11_DEFAULT 0x00004b2d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R12_DEFAULT 0x0000532e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R13_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R14_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R15_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R16_DEFAULT 0x0000ffe8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R17_DEFAULT 0x0000701d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R18_DEFAULT 0x00004b35
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R19_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R20_DEFAULT 0x0000532d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R21_DEFAULT 0x0000741d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R22_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R23_DEFAULT 0x0000074a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R24_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R25_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R26_DEFAULT 0x00003323
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R27_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R29_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R30_DEFAULT 0x0000532a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R31_DEFAULT 0x00001f2a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R0_DEFAULT 0x00004377
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R1_DEFAULT 0x0000075e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R4_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R5_DEFAULT 0x00001f09
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R8_DEFAULT 0x0000080c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R9_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R10_DEFAULT 0x000070cd
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R11_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R12_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R13_DEFAULT 0x00002f05
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R14_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R15_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R16_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R17_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R19_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R20_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R21_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R22_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R23_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R24_DEFAULT 0x0000435a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R25_DEFAULT 0x00005357
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R26_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R27_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R28_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R29_DEFAULT 0x0000435c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R30_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R31_DEFAULT 0x00000600
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R0_DEFAULT 0x00001f09
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R1_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R2_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R3_DEFAULT 0x0000608d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R4_DEFAULT 0x0000700d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R5_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R6_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R7_DEFAULT 0x00002f05
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R8_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R9_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R10_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R11_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R12_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R13_DEFAULT 0x0000436f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R14_DEFAULT 0x0000536c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R15_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R17_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R18_DEFAULT 0x00004371
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R19_DEFAULT 0x00000705
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R20_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R21_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R23_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R24_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R25_DEFAULT 0x00000147
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R27_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R29_DEFAULT 0x00001f6b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R30_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R31_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R0_DEFAULT 0x00000200
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R1_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R2_DEFAULT 0x00000042
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R3_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R4_DEFAULT 0x0000007e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R5_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R7_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R9_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R10_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R11_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R12_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R13_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R15_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R16_DEFAULT 0x00003636
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R17_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R18_DEFAULT 0x0000608c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R19_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R20_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R21_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R22_DEFAULT 0x0000702c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R23_DEFAULT 0x00002969
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R24_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R25_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R26_DEFAULT 0x00001f67
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R27_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R28_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R29_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R30_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R31_DEFAULT 0x00003c02
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R0_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R2_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R3_DEFAULT 0x00007060
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R4_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R5_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R6_DEFAULT 0x00001f2a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R7_DEFAULT 0x000043a9
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R8_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R9_DEFAULT 0x00001f68
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R10_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R11_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R12_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R13_DEFAULT 0x00001f6c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R14_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R15_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R16_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R17_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R18_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R19_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R20_DEFAULT 0x00004fa0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R22_DEFAULT 0x00007828
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R23_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R24_DEFAULT 0x000036dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R25_DEFAULT 0x00001f2b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R26_DEFAULT 0x000043bc
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R27_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R28_DEFAULT 0x00001f69
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R29_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R30_DEFAULT 0x00001f6d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R31_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R0_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R1_DEFAULT 0x00007818
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R2_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R3_DEFAULT 0x0000124a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R4_DEFAULT 0x00001f2b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R5_DEFAULT 0x000043c7
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R6_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R7_DEFAULT 0x00001f6a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R8_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R9_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R10_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R11_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R12_DEFAULT 0x00002806
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R13_DEFAULT 0x00001f6e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R14_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R15_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R16_DEFAULT 0x000000c6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R17_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R18_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R19_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R20_DEFAULT 0x00003000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R22_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R23_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R24_DEFAULT 0x0000b6b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R25_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R26_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R27_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R28_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R29_DEFAULT 0x00001f6a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R30_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R31_DEFAULT 0x00001f6e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R0_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R1_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R2_DEFAULT 0x00000084
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R3_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R4_DEFAULT 0x0000b000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R5_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R6_DEFAULT 0x00008080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R7_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R8_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R9_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R10_DEFAULT 0x000074d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R11_DEFAULT 0x00004bef
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R12_DEFAULT 0x00000711
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R14_DEFAULT 0x000053f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R15_DEFAULT 0x00002f11
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R16_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R17_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R18_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R20_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R21_DEFAULT 0x00003c46
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R22_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R24_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R25_DEFAULT 0x00007020
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R26_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R27_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R28_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R29_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R30_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R31_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R0_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R1_DEFAULT 0x00004408
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R2_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R3_DEFAULT 0x00000fe0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R4_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R5_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R6_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R7_DEFAULT 0x0000540d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R8_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R9_DEFAULT 0x00000fc0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R10_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R11_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R12_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R13_DEFAULT 0x000030c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R14_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R15_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R16_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R17_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R18_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R19_DEFAULT 0x000030c5
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R20_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R21_DEFAULT 0x00000036
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R22_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R23_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R24_DEFAULT 0x000030dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R25_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R27_DEFAULT 0x00007435
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R28_DEFAULT 0x00004c23
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R29_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R30_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R31_DEFAULT 0x00004c38
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R0_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R2_DEFAULT 0x00005438
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R4_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R5_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R8_DEFAULT 0x0000442c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R9_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R10_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R11_DEFAULT 0x0000542e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R12_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R13_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R14_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R15_DEFAULT 0x0000703d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R16_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R17_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R18_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R19_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R20_DEFAULT 0x00004c36
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R21_DEFAULT 0x00005438
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R22_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R23_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R24_DEFAULT 0x00006082
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R25_DEFAULT 0x00006182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R26_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R27_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R29_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R31_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R0_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R1_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R2_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R3_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R4_DEFAULT 0x000030dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R5_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R6_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R7_DEFAULT 0x00007435
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R8_DEFAULT 0x00004c4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R9_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R10_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R11_DEFAULT 0x00004c64
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R12_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R14_DEFAULT 0x00005464
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R16_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R17_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R18_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R20_DEFAULT 0x00004458
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R21_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R22_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R23_DEFAULT 0x0000545a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R24_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R25_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R26_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R27_DEFAULT 0x0000703d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R28_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R29_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R30_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R31_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R0_DEFAULT 0x00004c62
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R1_DEFAULT 0x00005464
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R2_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R3_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R4_DEFAULT 0x00006082
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R5_DEFAULT 0x00006182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R6_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R9_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R12_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R14_DEFAULT 0x00008647
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R16_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R17_DEFAULT 0x00001989
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R18_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R20_DEFAULT 0x0000601d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R21_DEFAULT 0x000030d3
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R22_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R23_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R24_DEFAULT 0x00001986
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R25_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R26_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R27_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R28_DEFAULT 0x000030d4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R29_DEFAULT 0x0000613d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R30_DEFAULT 0x000030d1
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R31_DEFAULT 0x00003025
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R0_DEFAULT 0x00006115
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R1_DEFAULT 0x00007052
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R2_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R3_DEFAULT 0x00007021
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R4_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R5_DEFAULT 0x00004c87
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R6_DEFAULT 0x0000548d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R7_DEFAULT 0x00007414
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R8_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R9_DEFAULT 0x00007052
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R10_DEFAULT 0x000074d3
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R11_DEFAULT 0x00004c93
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R12_DEFAULT 0x00005490
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R13_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R15_DEFAULT 0x00005495
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R16_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R17_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R18_DEFAULT 0x00005495
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R19_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R22_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R23_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R24_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R25_DEFAULT 0x00000804
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R26_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R27_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R28_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R29_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R30_DEFAULT 0x000003e0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R31_DEFAULT 0x0000116d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R0_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R1_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R2_DEFAULT 0x000030c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R4_DEFAULT 0x00000fe0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R5_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R8_DEFAULT 0x000030c3
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R9_DEFAULT 0x00007420
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R10_DEFAULT 0x00004cac
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R11_DEFAULT 0x000054c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R12_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R13_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R14_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R16_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R17_DEFAULT 0x000044b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R18_DEFAULT 0x00007434
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R19_DEFAULT 0x00004cb5
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R20_DEFAULT 0x000054c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R21_DEFAULT 0x00007412
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R22_DEFAULT 0x00004cb8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R23_DEFAULT 0x000054c1
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R24_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R25_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R26_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R27_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R28_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R29_DEFAULT 0x000044c1
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R30_DEFAULT 0x000054bf
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R31_DEFAULT 0x00007453
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R0_DEFAULT 0x00004cc7
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R1_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R2_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R3_DEFAULT 0x000054c9
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R4_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R6_DEFAULT 0x000054c9
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R7_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R9_DEFAULT 0x0000196b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R10_DEFAULT 0x00002f5a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R11_DEFAULT 0x0000196d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R12_DEFAULT 0x00002f5c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R13_DEFAULT 0x0000196c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R14_DEFAULT 0x00002f5b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R15_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R16_DEFAULT 0x00002f5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R17_DEFAULT 0x0000196f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R18_DEFAULT 0x00002f60
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R19_DEFAULT 0x00001970
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R20_DEFAULT 0x00002f61
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R21_DEFAULT 0x00001971
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R22_DEFAULT 0x00002f62
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R23_DEFAULT 0x00001972
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R24_DEFAULT 0x00002f63
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R25_DEFAULT 0x00000147
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R27_DEFAULT 0x0000075e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R29_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R31_DEFAULT 0x00000710
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R1_DEFAULT 0x00001f86
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R2_DEFAULT 0x000044e4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R3_DEFAULT 0x000054e1
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R4_DEFAULT 0x00000710
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R6_DEFAULT 0x0000078c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R8_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R9_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R10_DEFAULT 0x00000029
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R11_DEFAULT 0x00001fe3
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R12_DEFAULT 0x000044f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R13_DEFAULT 0x00001fe4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R14_DEFAULT 0x000044f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R15_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R16_DEFAULT 0x00009fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R17_DEFAULT 0x00001fe3
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R18_DEFAULT 0x000044f4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R19_DEFAULT 0x000054f7
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R20_DEFAULT 0x00000806
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R21_DEFAULT 0x000004f7
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R22_DEFAULT 0x00005500
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R23_DEFAULT 0x00001fe4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R24_DEFAULT 0x000044fa
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R25_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R26_DEFAULT 0x00000806
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R27_DEFAULT 0x000004fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R28_DEFAULT 0x00005571
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R29_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R31_DEFAULT 0x00005027
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R0_DEFAULT 0x00001f59
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R1_DEFAULT 0x00004503
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R2_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R3_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R5_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R6_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R7_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R8_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R9_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R11_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R13_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R14_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R15_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R16_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R17_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R18_DEFAULT 0x0000a080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R19_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R20_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R22_DEFAULT 0x00000741
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R23_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R24_DEFAULT 0x0000051a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R25_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R26_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R27_DEFAULT 0x0000a0c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R29_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R30_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R31_DEFAULT 0x00000742
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R0_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R1_DEFAULT 0x00000523
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R2_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R3_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R4_DEFAULT 0x0000a200
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R6_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R7_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R8_DEFAULT 0x00000743
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R9_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R10_DEFAULT 0x0000052c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R11_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R12_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R13_DEFAULT 0x0000a220
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R14_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R15_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R16_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R17_DEFAULT 0x00000744
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R18_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R19_DEFAULT 0x00000535
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R20_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R21_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R22_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R23_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R25_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R27_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R28_DEFAULT 0x0000320d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R29_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R0_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R1_DEFAULT 0x0000866c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R2_DEFAULT 0x00004d4b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R3_DEFAULT 0x0000827c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R4_DEFAULT 0x00004d46
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R5_DEFAULT 0x00005547
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R6_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R7_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R8_DEFAULT 0x00004d50
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R9_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R10_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R11_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R12_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R13_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R14_DEFAULT 0x00004549
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R15_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R16_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R17_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R18_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R19_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R20_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R21_DEFAULT 0x0000320d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R22_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R23_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R24_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R25_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R26_DEFAULT 0x000078a5
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R27_DEFAULT 0x0000744d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R28_DEFAULT 0x00004d5e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R29_DEFAULT 0x00005567
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R30_DEFAULT 0x000078a4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R31_DEFAULT 0x0000745d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R0_DEFAULT 0x00004d62
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R1_DEFAULT 0x00005563
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R2_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R3_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R4_DEFAULT 0x00004d6c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R5_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R6_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R7_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R8_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R9_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R10_DEFAULT 0x00004565
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R11_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R12_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R13_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R15_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R16_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R17_DEFAULT 0x00001f5e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R18_DEFAULT 0x00004574
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R19_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R20_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R21_DEFAULT 0x00003636
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R22_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R23_DEFAULT 0x0000608c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R24_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R25_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R26_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R27_DEFAULT 0x0000702c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R28_DEFAULT 0x00002969
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R29_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R30_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R31_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R0_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R1_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R2_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R3_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R5_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R6_DEFAULT 0x00003060
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R7_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R8_DEFAULT 0x0000647e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R9_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R10_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R11_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R12_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R13_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R14_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R15_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R16_DEFAULT 0x00000f20
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R17_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R18_DEFAULT 0x000090a0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R19_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R20_DEFAULT 0x00000999
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R22_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R23_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R24_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R25_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R27_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R28_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R29_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R30_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R31_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R0_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R1_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R2_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R3_DEFAULT 0x00002806
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R4_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R6_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R7_DEFAULT 0x00003060
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R8_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R9_DEFAULT 0x0000647e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R10_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R11_DEFAULT 0x00003fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R12_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R13_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R14_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R15_DEFAULT 0x000000c6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R16_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R17_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R18_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R20_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R21_DEFAULT 0x00003000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R22_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R23_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R24_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R25_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R26_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R28_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R29_DEFAULT 0x0000b6b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R30_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R31_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R0_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R1_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R2_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R3_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R4_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R5_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R6_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R7_DEFAULT 0x00003fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R8_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R9_DEFAULT 0x00000084
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R10_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R11_DEFAULT 0x0000b000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R12_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R13_DEFAULT 0x00008080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R14_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R15_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R16_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R17_DEFAULT 0x000030d1
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R18_DEFAULT 0x00007410
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R19_DEFAULT 0x00004dd7
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R20_DEFAULT 0x00000711
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R22_DEFAULT 0x000055d8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R23_DEFAULT 0x00002f11
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R24_DEFAULT 0x00007010
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R25_DEFAULT 0x0000611d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R26_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R27_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R29_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R30_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R31_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R0_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R1_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R3_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R4_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R6_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R9_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R12_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R13_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R14_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R15_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R16_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R17_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R18_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R19_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R20_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R21_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R22_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R23_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R24_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R25_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R26_DEFAULT 0x00005239
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R27_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R28_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R29_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R31_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R1_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R2_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R3_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R4_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R5_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R6_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R7_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R8_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R9_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R10_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R11_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R12_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R13_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R14_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R15_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R16_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R17_DEFAULT 0x0000524b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R18_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R19_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R20_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R21_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R24_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R25_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R26_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R28_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R29_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R31_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R0_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R1_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R2_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R3_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R4_DEFAULT 0x00005255
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R6_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R7_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R9_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R10_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R12_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R13_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R15_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R16_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R17_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R18_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R19_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R20_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R21_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R22_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R23_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R25_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R27_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R28_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R29_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R30_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R31_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R1_DEFAULT 0x00005261
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R3_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R4_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R5_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R6_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R9_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R12_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R13_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R14_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R16_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R18_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R19_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R20_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R21_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R24_DEFAULT 0x00005273
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R25_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R26_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R27_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R29_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R30_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R31_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R0_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R1_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R3_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R6_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R7_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R8_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R9_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R10_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R12_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R13_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R14_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R15_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R16_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R17_DEFAULT 0x0000527d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_CMN_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_DEFAULT 0x00005000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_DEFAULT 0x00005000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_IDCODE_LO_DEFAULT 0x000004cd
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_IDCODE_HI_DEFAULT 0x00003006
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN_DEFAULT 0x00000070
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0_DEFAULT 0x00000328
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_2_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0_DEFAULT 0x00000194
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1_DEFAULT 0x0000a000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_2_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN_DEFAULT 0x000001d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RX_TERM_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT 0x00000d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT 0x00005200
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT 0x0000894a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0_DEFAULT 0x00000025
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT 0x00000d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT 0x00005200
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT 0x0000894a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0_DEFAULT 0x00000025
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC_DEFAULT 0x00000028
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC_DEFAULT 0x00000028
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG_DEFAULT 0x0000000e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_CONFIG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R0_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R1_DEFAULT 0x00001f4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R2_DEFAULT 0x0000297c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R3_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R4_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R5_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R6_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R7_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R9_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R10_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R11_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R12_DEFAULT 0x00000750
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R13_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R14_DEFAULT 0x00000212
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R15_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R16_DEFAULT 0x00004214
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R17_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R18_DEFAULT 0x00001f50
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R19_DEFAULT 0x0000297d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R20_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R21_DEFAULT 0x00000140
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R22_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R23_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R24_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R25_DEFAULT 0x00002800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R26_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R28_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R29_DEFAULT 0x00006800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R31_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R0_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R1_DEFAULT 0x00000745
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R2_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R3_DEFAULT 0x00000227
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R4_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R5_DEFAULT 0x00004227
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R6_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R7_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R8_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R9_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R10_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R11_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R13_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R14_DEFAULT 0x00000015
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R15_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R16_DEFAULT 0x00000746
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R17_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R18_DEFAULT 0x00000236
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R19_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R20_DEFAULT 0x00004236
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R21_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R22_DEFAULT 0x000001b3
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R23_DEFAULT 0x00000177
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R24_DEFAULT 0x000055dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R25_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R26_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R27_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R28_DEFAULT 0x00002800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R29_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R31_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R0_DEFAULT 0x00007000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R1_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R2_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R4_DEFAULT 0x00000173
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R5_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R6_DEFAULT 0x0000024a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R7_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R8_DEFAULT 0x0000424a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R9_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R10_DEFAULT 0x000055fb
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R12_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R13_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R14_DEFAULT 0x00000174
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R15_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R16_DEFAULT 0x00000254
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R17_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R18_DEFAULT 0x00004254
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R19_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R20_DEFAULT 0x00005612
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R21_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R22_DEFAULT 0x00006c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R23_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R24_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R25_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R26_DEFAULT 0x00000179
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R27_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R28_DEFAULT 0x00000260
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R29_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R30_DEFAULT 0x00004260
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R31_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R0_DEFAULT 0x00005625
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R1_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R2_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R3_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R4_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R5_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R7_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R8_DEFAULT 0x00007000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R9_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R10_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R11_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R12_DEFAULT 0x00000175
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R13_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R14_DEFAULT 0x00000272
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R15_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R16_DEFAULT 0x00004272
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R17_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R18_DEFAULT 0x00005642
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R19_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R20_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R22_DEFAULT 0x00000176
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R23_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R24_DEFAULT 0x0000027c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R25_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R26_DEFAULT 0x0000427c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R27_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R28_DEFAULT 0x00005659
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R29_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R30_DEFAULT 0x00006c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R31_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R0_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R2_DEFAULT 0x0000017a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R3_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R4_DEFAULT 0x00000288
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R5_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R6_DEFAULT 0x00004288
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R7_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R8_DEFAULT 0x00001973
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R9_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R10_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R11_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R12_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R13_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R14_DEFAULT 0x00001974
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R15_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R16_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R17_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R18_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R19_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R20_DEFAULT 0x00001979
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R21_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R22_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R23_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R24_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R25_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R26_DEFAULT 0x00001975
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R27_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R29_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R0_DEFAULT 0x00001976
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R1_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R3_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R4_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R6_DEFAULT 0x0000197a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R9_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R12_DEFAULT 0x00001973
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R13_DEFAULT 0x00002f4b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R14_DEFAULT 0x00001974
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R15_DEFAULT 0x00002f4c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R16_DEFAULT 0x00001979
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R17_DEFAULT 0x00002f51
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R18_DEFAULT 0x00001975
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R19_DEFAULT 0x00002f4d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R20_DEFAULT 0x00001976
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R21_DEFAULT 0x00002f4e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R22_DEFAULT 0x0000197a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R23_DEFAULT 0x00002f52
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R24_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R25_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R26_DEFAULT 0x00001f4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R27_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R29_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R0_DEFAULT 0x00001f50
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R1_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R3_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R4_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R6_DEFAULT 0x00001f42
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R9_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R12_DEFAULT 0x00001f43
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R13_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R14_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R15_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R16_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R18_DEFAULT 0x00001f44
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R19_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R20_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R21_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R24_DEFAULT 0x00001f29
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R25_DEFAULT 0x000042f1
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R26_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R27_DEFAULT 0x0000a3a0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R28_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R29_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R30_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R0_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R2_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R4_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R5_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R6_DEFAULT 0x000001b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R8_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R10_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R12_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R13_DEFAULT 0x00000749
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R14_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R15_DEFAULT 0x000002f5
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R16_DEFAULT 0x00005329
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R17_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R18_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R19_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R20_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R21_DEFAULT 0x000001b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R23_DEFAULT 0x000019b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R24_DEFAULT 0x00002f53
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R25_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R27_DEFAULT 0x000001b3
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R28_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R29_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R31_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R1_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R3_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R5_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R6_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R7_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R9_DEFAULT 0x00008660
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R10_DEFAULT 0x00004b15
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R11_DEFAULT 0x00008270
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R12_DEFAULT 0x00004b0e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R13_DEFAULT 0x0000530f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R14_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R15_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R16_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R18_DEFAULT 0x00004b1c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R19_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R20_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R21_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R22_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R24_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R25_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R26_DEFAULT 0x00004313
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R27_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R28_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R29_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R30_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R31_DEFAULT 0x0000301d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R0_DEFAULT 0x00004325
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R1_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R2_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R3_DEFAULT 0x00003054
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R4_DEFAULT 0x00005327
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R5_DEFAULT 0x00007445
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R6_DEFAULT 0x0000430e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R7_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R8_DEFAULT 0x00005309
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R9_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R10_DEFAULT 0x00008670
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R11_DEFAULT 0x00004b2d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R12_DEFAULT 0x0000532e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R13_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R14_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R15_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R16_DEFAULT 0x0000ffe8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R17_DEFAULT 0x0000701d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R18_DEFAULT 0x00004b35
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R19_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R20_DEFAULT 0x0000532d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R21_DEFAULT 0x0000741d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R22_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R23_DEFAULT 0x0000074a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R24_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R25_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R26_DEFAULT 0x00003323
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R27_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R29_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R30_DEFAULT 0x0000532a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R31_DEFAULT 0x00001f2a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R0_DEFAULT 0x00004377
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R1_DEFAULT 0x0000075e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R4_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R5_DEFAULT 0x00001f09
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R8_DEFAULT 0x0000080c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R9_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R10_DEFAULT 0x000070cd
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R11_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R12_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R13_DEFAULT 0x00002f05
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R14_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R15_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R16_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R17_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R19_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R20_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R21_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R22_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R23_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R24_DEFAULT 0x0000435a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R25_DEFAULT 0x00005357
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R26_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R27_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R28_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R29_DEFAULT 0x0000435c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R30_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R31_DEFAULT 0x00000600
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R0_DEFAULT 0x00001f09
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R1_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R2_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R3_DEFAULT 0x0000608d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R4_DEFAULT 0x0000700d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R5_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R6_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R7_DEFAULT 0x00002f05
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R8_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R9_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R10_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R11_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R12_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R13_DEFAULT 0x0000436f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R14_DEFAULT 0x0000536c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R15_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R17_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R18_DEFAULT 0x00004371
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R19_DEFAULT 0x00000705
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R20_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R21_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R23_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R24_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R25_DEFAULT 0x00000147
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R27_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R29_DEFAULT 0x00001f6b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R30_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R31_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R0_DEFAULT 0x00000200
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R1_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R2_DEFAULT 0x00000042
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R3_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R4_DEFAULT 0x0000007e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R5_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R7_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R9_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R10_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R11_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R12_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R13_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R15_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R16_DEFAULT 0x00003636
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R17_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R18_DEFAULT 0x0000608c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R19_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R20_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R21_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R22_DEFAULT 0x0000702c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R23_DEFAULT 0x00002969
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R24_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R25_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R26_DEFAULT 0x00001f67
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R27_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R28_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R29_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R30_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R31_DEFAULT 0x00003c02
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R0_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R2_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R3_DEFAULT 0x00007060
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R4_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R5_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R6_DEFAULT 0x00001f2a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R7_DEFAULT 0x000043a9
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R8_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R9_DEFAULT 0x00001f68
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R10_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R11_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R12_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R13_DEFAULT 0x00001f6c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R14_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R15_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R16_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R17_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R18_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R19_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R20_DEFAULT 0x00004fa0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R22_DEFAULT 0x00007828
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R23_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R24_DEFAULT 0x000036dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R25_DEFAULT 0x00001f2b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R26_DEFAULT 0x000043bc
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R27_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R28_DEFAULT 0x00001f69
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R29_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R30_DEFAULT 0x00001f6d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R31_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R0_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R1_DEFAULT 0x00007818
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R2_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R3_DEFAULT 0x0000124a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R4_DEFAULT 0x00001f2b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R5_DEFAULT 0x000043c7
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R6_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R7_DEFAULT 0x00001f6a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R8_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R9_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R10_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R11_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R12_DEFAULT 0x00002806
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R13_DEFAULT 0x00001f6e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R14_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R15_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R16_DEFAULT 0x000000c6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R17_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R18_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R19_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R20_DEFAULT 0x00003000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R22_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R23_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R24_DEFAULT 0x0000b6b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R25_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R26_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R27_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R28_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R29_DEFAULT 0x00001f6a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R30_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R31_DEFAULT 0x00001f6e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R0_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R1_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R2_DEFAULT 0x00000084
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R3_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R4_DEFAULT 0x0000b000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R5_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R6_DEFAULT 0x00008080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R7_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R8_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R9_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R10_DEFAULT 0x000074d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R11_DEFAULT 0x00004bef
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R12_DEFAULT 0x00000711
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R14_DEFAULT 0x000053f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R15_DEFAULT 0x00002f11
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R16_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R17_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R18_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R20_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R21_DEFAULT 0x00003c46
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R22_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R24_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R25_DEFAULT 0x00007020
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R26_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R27_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R28_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R29_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R30_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R31_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R0_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R1_DEFAULT 0x00004408
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R2_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R3_DEFAULT 0x00000fe0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R4_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R5_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R6_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R7_DEFAULT 0x0000540d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R8_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R9_DEFAULT 0x00000fc0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R10_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R11_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R12_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R13_DEFAULT 0x000030c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R14_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R15_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R16_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R17_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R18_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R19_DEFAULT 0x000030c5
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R20_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R21_DEFAULT 0x00000036
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R22_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R23_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R24_DEFAULT 0x000030dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R25_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R27_DEFAULT 0x00007435
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R28_DEFAULT 0x00004c23
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R29_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R30_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R31_DEFAULT 0x00004c38
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R0_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R2_DEFAULT 0x00005438
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R4_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R5_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R8_DEFAULT 0x0000442c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R9_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R10_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R11_DEFAULT 0x0000542e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R12_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R13_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R14_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R15_DEFAULT 0x0000703d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R16_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R17_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R18_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R19_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R20_DEFAULT 0x00004c36
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R21_DEFAULT 0x00005438
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R22_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R23_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R24_DEFAULT 0x00006082
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R25_DEFAULT 0x00006182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R26_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R27_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R29_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R31_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R0_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R1_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R2_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R3_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R4_DEFAULT 0x000030dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R5_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R6_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R7_DEFAULT 0x00007435
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R8_DEFAULT 0x00004c4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R9_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R10_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R11_DEFAULT 0x00004c64
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R12_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R14_DEFAULT 0x00005464
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R16_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R17_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R18_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R20_DEFAULT 0x00004458
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R21_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R22_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R23_DEFAULT 0x0000545a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R24_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R25_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R26_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R27_DEFAULT 0x0000703d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R28_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R29_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R30_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R31_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R0_DEFAULT 0x00004c62
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R1_DEFAULT 0x00005464
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R2_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R3_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R4_DEFAULT 0x00006082
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R5_DEFAULT 0x00006182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R6_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R9_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R12_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R14_DEFAULT 0x00008647
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R16_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R17_DEFAULT 0x00001989
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R18_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R20_DEFAULT 0x0000601d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R21_DEFAULT 0x000030d3
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R22_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R23_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R24_DEFAULT 0x00001986
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R25_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R26_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R27_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R28_DEFAULT 0x000030d4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R29_DEFAULT 0x0000613d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R30_DEFAULT 0x000030d1
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R31_DEFAULT 0x00003025
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R0_DEFAULT 0x00006115
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R1_DEFAULT 0x00007052
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R2_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R3_DEFAULT 0x00007021
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R4_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R5_DEFAULT 0x00004c87
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R6_DEFAULT 0x0000548d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R7_DEFAULT 0x00007414
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R8_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R9_DEFAULT 0x00007052
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R10_DEFAULT 0x000074d3
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R11_DEFAULT 0x00004c93
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R12_DEFAULT 0x00005490
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R13_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R15_DEFAULT 0x00005495
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R16_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R17_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R18_DEFAULT 0x00005495
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R19_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R22_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R23_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R24_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R25_DEFAULT 0x00000804
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R26_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R27_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R28_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R29_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R30_DEFAULT 0x000003e0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R31_DEFAULT 0x0000116d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R0_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R1_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R2_DEFAULT 0x000030c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R4_DEFAULT 0x00000fe0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R5_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R8_DEFAULT 0x000030c3
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R9_DEFAULT 0x00007420
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R10_DEFAULT 0x00004cac
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R11_DEFAULT 0x000054c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R12_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R13_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R14_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R16_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R17_DEFAULT 0x000044b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R18_DEFAULT 0x00007434
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R19_DEFAULT 0x00004cb5
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R20_DEFAULT 0x000054c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R21_DEFAULT 0x00007412
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R22_DEFAULT 0x00004cb8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R23_DEFAULT 0x000054c1
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R24_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R25_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R26_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R27_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R28_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R29_DEFAULT 0x000044c1
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R30_DEFAULT 0x000054bf
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R31_DEFAULT 0x00007453
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R0_DEFAULT 0x00004cc7
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R1_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R2_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R3_DEFAULT 0x000054c9
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R4_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R6_DEFAULT 0x000054c9
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R7_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R9_DEFAULT 0x0000196b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R10_DEFAULT 0x00002f5a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R11_DEFAULT 0x0000196d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R12_DEFAULT 0x00002f5c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R13_DEFAULT 0x0000196c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R14_DEFAULT 0x00002f5b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R15_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R16_DEFAULT 0x00002f5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R17_DEFAULT 0x0000196f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R18_DEFAULT 0x00002f60
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R19_DEFAULT 0x00001970
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R20_DEFAULT 0x00002f61
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R21_DEFAULT 0x00001971
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R22_DEFAULT 0x00002f62
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R23_DEFAULT 0x00001972
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R24_DEFAULT 0x00002f63
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R25_DEFAULT 0x00000147
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R27_DEFAULT 0x0000075e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R29_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R31_DEFAULT 0x00000710
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R1_DEFAULT 0x00001f86
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R2_DEFAULT 0x000044e4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R3_DEFAULT 0x000054e1
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R4_DEFAULT 0x00000710
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R6_DEFAULT 0x0000078c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R8_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R9_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R10_DEFAULT 0x00000029
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R11_DEFAULT 0x00001fe3
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R12_DEFAULT 0x000044f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R13_DEFAULT 0x00001fe4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R14_DEFAULT 0x000044f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R15_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R16_DEFAULT 0x00009fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R17_DEFAULT 0x00001fe3
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R18_DEFAULT 0x000044f4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R19_DEFAULT 0x000054f7
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R20_DEFAULT 0x00000806
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R21_DEFAULT 0x000004f7
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R22_DEFAULT 0x00005500
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R23_DEFAULT 0x00001fe4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R24_DEFAULT 0x000044fa
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R25_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R26_DEFAULT 0x00000806
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R27_DEFAULT 0x000004fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R28_DEFAULT 0x00005571
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R29_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R31_DEFAULT 0x00005027
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R0_DEFAULT 0x00001f59
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R1_DEFAULT 0x00004503
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R2_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R3_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R5_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R6_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R7_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R8_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R9_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R11_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R13_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R14_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R15_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R16_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R17_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R18_DEFAULT 0x0000a080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R19_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R20_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R22_DEFAULT 0x00000741
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R23_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R24_DEFAULT 0x0000051a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R25_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R26_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R27_DEFAULT 0x0000a0c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R29_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R30_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R31_DEFAULT 0x00000742
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R0_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R1_DEFAULT 0x00000523
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R2_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R3_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R4_DEFAULT 0x0000a200
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R6_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R7_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R8_DEFAULT 0x00000743
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R9_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R10_DEFAULT 0x0000052c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R11_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R12_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R13_DEFAULT 0x0000a220
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R14_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R15_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R16_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R17_DEFAULT 0x00000744
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R18_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R19_DEFAULT 0x00000535
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R20_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R21_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R22_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R23_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R25_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R27_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R28_DEFAULT 0x0000320d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R29_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R0_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R1_DEFAULT 0x0000866c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R2_DEFAULT 0x00004d4b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R3_DEFAULT 0x0000827c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R4_DEFAULT 0x00004d46
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R5_DEFAULT 0x00005547
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R6_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R7_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R8_DEFAULT 0x00004d50
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R9_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R10_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R11_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R12_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R13_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R14_DEFAULT 0x00004549
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R15_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R16_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R17_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R18_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R19_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R20_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R21_DEFAULT 0x0000320d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R22_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R23_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R24_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R25_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R26_DEFAULT 0x000078a5
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R27_DEFAULT 0x0000744d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R28_DEFAULT 0x00004d5e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R29_DEFAULT 0x00005567
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R30_DEFAULT 0x000078a4
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R31_DEFAULT 0x0000745d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R0_DEFAULT 0x00004d62
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R1_DEFAULT 0x00005563
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R2_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R3_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R4_DEFAULT 0x00004d6c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R5_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R6_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R7_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R8_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R9_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R10_DEFAULT 0x00004565
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R11_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R12_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R13_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R15_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R16_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R17_DEFAULT 0x00001f5e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R18_DEFAULT 0x00004574
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R19_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R20_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R21_DEFAULT 0x00003636
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R22_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R23_DEFAULT 0x0000608c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R24_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R25_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R26_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R27_DEFAULT 0x0000702c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R28_DEFAULT 0x00002969
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R29_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R30_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R31_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R0_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R1_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R2_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R3_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R5_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R6_DEFAULT 0x00003060
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R7_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R8_DEFAULT 0x0000647e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R9_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R10_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R11_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R12_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R13_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R14_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R15_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R16_DEFAULT 0x00000f20
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R17_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R18_DEFAULT 0x000090a0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R19_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R20_DEFAULT 0x00000999
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R22_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R23_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R24_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R25_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R27_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R28_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R29_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R30_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R31_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R0_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R1_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R2_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R3_DEFAULT 0x00002806
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R4_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R6_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R7_DEFAULT 0x00003060
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R8_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R9_DEFAULT 0x0000647e
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R10_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R11_DEFAULT 0x00003fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R12_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R13_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R14_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R15_DEFAULT 0x000000c6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R16_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R17_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R18_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R20_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R21_DEFAULT 0x00003000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R22_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R23_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R24_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R25_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R26_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R28_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R29_DEFAULT 0x0000b6b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R30_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R31_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R0_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R1_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R2_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R3_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R4_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R5_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R6_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R7_DEFAULT 0x00003fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R8_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R9_DEFAULT 0x00000084
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R10_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R11_DEFAULT 0x0000b000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R12_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R13_DEFAULT 0x00008080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R14_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R15_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R16_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R17_DEFAULT 0x000030d1
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R18_DEFAULT 0x00007410
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R19_DEFAULT 0x00004dd7
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R20_DEFAULT 0x00000711
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R22_DEFAULT 0x000055d8
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R23_DEFAULT 0x00002f11
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R24_DEFAULT 0x00007010
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R25_DEFAULT 0x0000611d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R26_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R27_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R29_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R30_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R31_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R0_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R1_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R3_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R4_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R6_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R9_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R12_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R13_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R14_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R15_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R16_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R17_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R18_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R19_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R20_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R21_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R22_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R23_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R24_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R25_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R26_DEFAULT 0x00005239
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R27_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R28_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R29_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R31_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R1_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R2_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R3_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R4_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R5_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R6_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R7_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R8_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R9_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R10_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R11_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R12_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R13_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R14_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R15_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R16_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R17_DEFAULT 0x0000524b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R18_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R19_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R20_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R21_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R24_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R25_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R26_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R28_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R29_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R31_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R0_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R1_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R2_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R3_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R4_DEFAULT 0x00005255
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R6_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R7_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R9_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R10_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R12_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R13_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R15_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R16_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R17_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R18_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R19_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R20_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R21_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R22_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R23_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R25_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R27_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R28_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R29_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R30_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R31_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R1_DEFAULT 0x00005261
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R3_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R4_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R5_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R6_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R9_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R12_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R13_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R14_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R16_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R18_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R19_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R20_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R21_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R24_DEFAULT 0x00005273
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R25_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R26_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R27_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R29_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R30_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R31_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R0_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R1_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R3_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R6_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R7_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R8_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R9_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R10_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R12_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R13_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R14_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R15_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R16_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R17_DEFAULT 0x0000527d
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_CMN_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN_DEFAULT 0x00005000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN_DEFAULT 0x00005000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_lcu_kpfifo_kpfifo1_kpfifo_dir
+#define smnKPFIFO1_PRI_TX_FIFO_HSCID_DEFAULT 0x00000000
+#define smnKPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0_DEFAULT 0x00000000
+#define smnKPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1_DEFAULT 0x00000000
+#define smnKPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2_DEFAULT 0x00000000
+#define smnKPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3_DEFAULT 0x00000000
+#define smnKPFIFO1_PCS_PMA_SOFT_RESET_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_lcu_kpnp_kpnp1_kpnp_dir
+#define smnKPNP_SNPS1_KPNP_HWSCVER_DEFAULT 0x00000000
+#define smnKPNP_SNPS1_KPNP_PHY_INFO_DEFAULT 0x00000000
+#define smnKPNP_SNPS1_KPNP_LANE_ID_DEFAULT 0x00000000
+#define smnKPNP_SNPS1_KPNP_LANE_REQ_CONTROL_DEFAULT 0x00000000
+#define smnKPNP_SNPS1_KPNP_LANE_REQ_STATUS_DEFAULT 0x00000000
+#define smnKPNP_SNPS1_KPNP_PMA_CONTROL0_DEFAULT 0x00000000
+#define smnKPNP_SNPS1_KPNP_PMA_CONTROL1_DEFAULT 0x000000b1
+#define smnKPNP_SNPS1_KPNP_PMA_CONTROL2_DEFAULT 0x00000004
+#define smnKPNP_SNPS1_KPNP_PHY_SOFT_RESET_DEFAULT 0x00000000
+#define smnKPNP_SNPS1_KPNP_LANE_SOFT_RESET_DEFAULT 0x000000ff
+#define smnKPNP_SNPS1_REG_RST_CTRL_DEFAULT 0x00000001
+
+
+// addressBlock: nbio_pipe_pcs_dwc_e12mp_phy_x4_ns2_dwc_e12mp_phy_x4_ns_UP16_dwc_e12mp_phy_x4_ns_UP16_mem_map
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_IDCODE_LO_DEFAULT 0x000074cd
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_IDCODE_HI_DEFAULT 0x00000733
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN_DEFAULT 0x00000070
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0_DEFAULT 0x00000328
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_2_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0_DEFAULT 0x00000194
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1_DEFAULT 0x0000a000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_2_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN_DEFAULT 0x000001d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RX_TERM_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT 0x00000d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT 0x00005200
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT 0x0000894a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0_DEFAULT 0x00000025
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT 0x00000d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT 0x00005200
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT 0x0000894a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0_DEFAULT 0x00000025
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC_DEFAULT 0x00000028
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC_DEFAULT 0x00000028
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG_DEFAULT 0x0000000e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_CONFIG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R0_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R1_DEFAULT 0x00001f4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R2_DEFAULT 0x0000297c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R3_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R4_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R5_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R6_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R7_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R9_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R10_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R11_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R12_DEFAULT 0x00000750
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R13_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R14_DEFAULT 0x00000212
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R15_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R16_DEFAULT 0x00004214
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R17_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R18_DEFAULT 0x00001f50
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R19_DEFAULT 0x0000297d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R20_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R21_DEFAULT 0x00000140
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R22_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R23_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R24_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R25_DEFAULT 0x00002800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R26_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R28_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R29_DEFAULT 0x00006800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R31_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R0_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R1_DEFAULT 0x00000745
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R2_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R3_DEFAULT 0x00000227
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R4_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R5_DEFAULT 0x00004227
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R6_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R7_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R8_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R9_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R10_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R11_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R13_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R14_DEFAULT 0x00000015
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R15_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R16_DEFAULT 0x00000746
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R17_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R18_DEFAULT 0x00000236
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R19_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R20_DEFAULT 0x00004236
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R21_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R22_DEFAULT 0x000001b3
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R23_DEFAULT 0x00000177
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R24_DEFAULT 0x000055dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R25_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R26_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R27_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R28_DEFAULT 0x00002800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R29_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R31_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R0_DEFAULT 0x00007000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R1_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R2_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R4_DEFAULT 0x00000173
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R5_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R6_DEFAULT 0x0000024a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R7_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R8_DEFAULT 0x0000424a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R9_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R10_DEFAULT 0x000055fb
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R12_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R13_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R14_DEFAULT 0x00000174
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R15_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R16_DEFAULT 0x00000254
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R17_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R18_DEFAULT 0x00004254
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R19_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R20_DEFAULT 0x00005612
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R21_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R22_DEFAULT 0x00006c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R23_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R24_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R25_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R26_DEFAULT 0x00000179
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R27_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R28_DEFAULT 0x00000260
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R29_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R30_DEFAULT 0x00004260
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R31_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R0_DEFAULT 0x00005625
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R1_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R2_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R3_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R4_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R5_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R7_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R8_DEFAULT 0x00007000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R9_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R10_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R11_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R12_DEFAULT 0x00000175
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R13_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R14_DEFAULT 0x00000272
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R15_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R16_DEFAULT 0x00004272
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R17_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R18_DEFAULT 0x00005642
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R19_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R20_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R22_DEFAULT 0x00000176
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R23_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R24_DEFAULT 0x0000027c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R25_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R26_DEFAULT 0x0000427c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R27_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R28_DEFAULT 0x00005659
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R29_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R30_DEFAULT 0x00006c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R31_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R0_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R2_DEFAULT 0x0000017a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R3_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R4_DEFAULT 0x00000288
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R5_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R6_DEFAULT 0x00004288
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R7_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R8_DEFAULT 0x00001973
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R9_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R10_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R11_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R12_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R13_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R14_DEFAULT 0x00001974
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R15_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R16_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R17_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R18_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R19_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R20_DEFAULT 0x00001979
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R21_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R22_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R23_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R24_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R25_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R26_DEFAULT 0x00001975
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R27_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R29_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R0_DEFAULT 0x00001976
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R1_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R3_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R4_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R6_DEFAULT 0x0000197a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R9_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R12_DEFAULT 0x00001973
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R13_DEFAULT 0x00002f4b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R14_DEFAULT 0x00001974
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R15_DEFAULT 0x00002f4c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R16_DEFAULT 0x00001979
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R17_DEFAULT 0x00002f51
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R18_DEFAULT 0x00001975
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R19_DEFAULT 0x00002f4d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R20_DEFAULT 0x00001976
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R21_DEFAULT 0x00002f4e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R22_DEFAULT 0x0000197a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R23_DEFAULT 0x00002f52
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R24_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R25_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R26_DEFAULT 0x00001f4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R27_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R29_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R0_DEFAULT 0x00001f50
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R1_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R3_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R4_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R6_DEFAULT 0x00001f42
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R9_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R12_DEFAULT 0x00001f43
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R13_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R14_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R15_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R16_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R18_DEFAULT 0x00001f44
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R19_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R20_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R21_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R24_DEFAULT 0x00001f29
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R25_DEFAULT 0x000042f1
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R26_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R27_DEFAULT 0x0000a3a0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R28_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R29_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R30_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R0_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R2_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R4_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R5_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R6_DEFAULT 0x000001b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R8_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R10_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R12_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R13_DEFAULT 0x00000749
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R14_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R15_DEFAULT 0x000002f5
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R16_DEFAULT 0x00005329
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R17_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R18_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R19_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R20_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R21_DEFAULT 0x000001b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R23_DEFAULT 0x000019b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R24_DEFAULT 0x00002f53
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R25_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R27_DEFAULT 0x000001b3
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R28_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R29_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R31_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R1_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R3_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R5_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R6_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R7_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R9_DEFAULT 0x00008660
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R10_DEFAULT 0x00004b15
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R11_DEFAULT 0x00008270
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R12_DEFAULT 0x00004b0e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R13_DEFAULT 0x0000530f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R14_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R15_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R16_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R18_DEFAULT 0x00004b1c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R19_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R20_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R21_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R22_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R24_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R25_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R26_DEFAULT 0x00004313
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R27_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R28_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R29_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R30_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R31_DEFAULT 0x0000301d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R0_DEFAULT 0x00004325
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R1_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R2_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R3_DEFAULT 0x00003054
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R4_DEFAULT 0x00005327
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R5_DEFAULT 0x00007445
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R6_DEFAULT 0x0000430e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R7_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R8_DEFAULT 0x00005309
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R9_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R10_DEFAULT 0x00008670
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R11_DEFAULT 0x00004b2d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R12_DEFAULT 0x0000532e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R13_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R14_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R15_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R16_DEFAULT 0x0000ffe8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R17_DEFAULT 0x0000701d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R18_DEFAULT 0x00004b35
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R19_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R20_DEFAULT 0x0000532d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R21_DEFAULT 0x0000741d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R22_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R23_DEFAULT 0x0000074a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R24_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R25_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R26_DEFAULT 0x00003323
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R27_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R29_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R30_DEFAULT 0x0000532a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R31_DEFAULT 0x00001f2a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R0_DEFAULT 0x00004377
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R1_DEFAULT 0x0000075e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R4_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R5_DEFAULT 0x00001f09
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R8_DEFAULT 0x0000080c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R9_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R10_DEFAULT 0x000070cd
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R11_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R12_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R13_DEFAULT 0x00002f05
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R14_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R15_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R16_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R17_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R19_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R20_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R21_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R22_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R23_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R24_DEFAULT 0x0000435a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R25_DEFAULT 0x00005357
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R26_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R27_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R28_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R29_DEFAULT 0x0000435c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R30_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R31_DEFAULT 0x00000600
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R0_DEFAULT 0x00001f09
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R1_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R2_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R3_DEFAULT 0x0000608d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R4_DEFAULT 0x0000700d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R5_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R6_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R7_DEFAULT 0x00002f05
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R8_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R9_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R10_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R11_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R12_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R13_DEFAULT 0x0000436f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R14_DEFAULT 0x0000536c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R15_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R17_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R18_DEFAULT 0x00004371
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R19_DEFAULT 0x00000705
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R20_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R21_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R23_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R24_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R25_DEFAULT 0x00000147
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R27_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R29_DEFAULT 0x00001f6b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R30_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R31_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R0_DEFAULT 0x00000200
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R1_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R2_DEFAULT 0x00000042
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R3_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R4_DEFAULT 0x0000007e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R5_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R7_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R9_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R10_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R11_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R12_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R13_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R15_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R16_DEFAULT 0x00003636
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R17_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R18_DEFAULT 0x0000608c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R19_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R20_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R21_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R22_DEFAULT 0x0000702c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R23_DEFAULT 0x00002969
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R24_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R25_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R26_DEFAULT 0x00001f67
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R27_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R28_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R29_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R30_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R31_DEFAULT 0x00003c02
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R0_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R2_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R3_DEFAULT 0x00007060
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R4_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R5_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R6_DEFAULT 0x00001f2a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R7_DEFAULT 0x000043a9
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R8_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R9_DEFAULT 0x00001f68
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R10_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R11_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R12_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R13_DEFAULT 0x00001f6c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R14_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R15_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R16_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R17_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R18_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R19_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R20_DEFAULT 0x00004fa0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R22_DEFAULT 0x00007828
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R23_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R24_DEFAULT 0x000036dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R25_DEFAULT 0x00001f2b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R26_DEFAULT 0x000043bc
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R27_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R28_DEFAULT 0x00001f69
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R29_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R30_DEFAULT 0x00001f6d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R31_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R0_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R1_DEFAULT 0x00007818
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R2_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R3_DEFAULT 0x0000124a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R4_DEFAULT 0x00001f2b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R5_DEFAULT 0x000043c7
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R6_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R7_DEFAULT 0x00001f6a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R8_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R9_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R10_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R11_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R12_DEFAULT 0x00002806
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R13_DEFAULT 0x00001f6e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R14_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R15_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R16_DEFAULT 0x000000c6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R17_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R18_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R19_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R20_DEFAULT 0x00003000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R22_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R23_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R24_DEFAULT 0x0000b6b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R25_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R26_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R27_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R28_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R29_DEFAULT 0x00001f6a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R30_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R31_DEFAULT 0x00001f6e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R0_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R1_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R2_DEFAULT 0x00000084
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R3_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R4_DEFAULT 0x0000b000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R5_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R6_DEFAULT 0x00008080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R7_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R8_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R9_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R10_DEFAULT 0x000074d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R11_DEFAULT 0x00004bef
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R12_DEFAULT 0x00000711
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R14_DEFAULT 0x000053f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R15_DEFAULT 0x00002f11
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R16_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R17_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R18_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R20_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R21_DEFAULT 0x00003c46
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R22_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R24_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R25_DEFAULT 0x00007020
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R26_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R27_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R28_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R29_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R30_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R31_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R0_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R1_DEFAULT 0x00004408
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R2_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R3_DEFAULT 0x00000fe0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R4_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R5_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R6_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R7_DEFAULT 0x0000540d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R8_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R9_DEFAULT 0x00000fc0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R10_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R11_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R12_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R13_DEFAULT 0x000030c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R14_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R15_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R16_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R17_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R18_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R19_DEFAULT 0x000030c5
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R20_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R21_DEFAULT 0x00000036
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R22_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R23_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R24_DEFAULT 0x000030dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R25_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R27_DEFAULT 0x00007435
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R28_DEFAULT 0x00004c23
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R29_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R30_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R31_DEFAULT 0x00004c38
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R0_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R2_DEFAULT 0x00005438
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R4_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R5_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R8_DEFAULT 0x0000442c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R9_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R10_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R11_DEFAULT 0x0000542e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R12_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R13_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R14_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R15_DEFAULT 0x0000703d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R16_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R17_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R18_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R19_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R20_DEFAULT 0x00004c36
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R21_DEFAULT 0x00005438
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R22_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R23_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R24_DEFAULT 0x00006082
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R25_DEFAULT 0x00006182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R26_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R27_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R29_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R31_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R0_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R1_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R2_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R3_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R4_DEFAULT 0x000030dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R5_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R6_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R7_DEFAULT 0x00007435
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R8_DEFAULT 0x00004c4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R9_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R10_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R11_DEFAULT 0x00004c64
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R12_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R14_DEFAULT 0x00005464
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R16_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R17_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R18_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R20_DEFAULT 0x00004458
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R21_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R22_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R23_DEFAULT 0x0000545a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R24_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R25_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R26_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R27_DEFAULT 0x0000703d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R28_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R29_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R30_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R31_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R0_DEFAULT 0x00004c62
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R1_DEFAULT 0x00005464
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R2_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R3_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R4_DEFAULT 0x00006082
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R5_DEFAULT 0x00006182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R6_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R9_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R12_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R14_DEFAULT 0x00008647
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R16_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R17_DEFAULT 0x00001989
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R18_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R20_DEFAULT 0x0000601d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R21_DEFAULT 0x000030d3
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R22_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R23_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R24_DEFAULT 0x00001986
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R25_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R26_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R27_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R28_DEFAULT 0x000030d4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R29_DEFAULT 0x0000613d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R30_DEFAULT 0x000030d1
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R31_DEFAULT 0x00003025
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R0_DEFAULT 0x00006115
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R1_DEFAULT 0x00007052
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R2_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R3_DEFAULT 0x00007021
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R4_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R5_DEFAULT 0x00004c87
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R6_DEFAULT 0x0000548d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R7_DEFAULT 0x00007414
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R8_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R9_DEFAULT 0x00007052
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R10_DEFAULT 0x000074d3
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R11_DEFAULT 0x00004c93
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R12_DEFAULT 0x00005490
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R13_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R15_DEFAULT 0x00005495
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R16_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R17_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R18_DEFAULT 0x00005495
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R19_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R22_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R23_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R24_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R25_DEFAULT 0x00000804
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R26_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R27_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R28_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R29_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R30_DEFAULT 0x000003e0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R31_DEFAULT 0x0000116d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R0_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R1_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R2_DEFAULT 0x000030c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R4_DEFAULT 0x00000fe0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R5_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R8_DEFAULT 0x000030c3
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R9_DEFAULT 0x00007420
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R10_DEFAULT 0x00004cac
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R11_DEFAULT 0x000054c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R12_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R13_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R14_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R16_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R17_DEFAULT 0x000044b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R18_DEFAULT 0x00007434
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R19_DEFAULT 0x00004cb5
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R20_DEFAULT 0x000054c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R21_DEFAULT 0x00007412
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R22_DEFAULT 0x00004cb8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R23_DEFAULT 0x000054c1
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R24_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R25_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R26_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R27_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R28_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R29_DEFAULT 0x000044c1
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R30_DEFAULT 0x000054bf
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R31_DEFAULT 0x00007453
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R0_DEFAULT 0x00004cc7
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R1_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R2_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R3_DEFAULT 0x000054c9
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R4_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R6_DEFAULT 0x000054c9
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R7_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R9_DEFAULT 0x0000196b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R10_DEFAULT 0x00002f5a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R11_DEFAULT 0x0000196d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R12_DEFAULT 0x00002f5c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R13_DEFAULT 0x0000196c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R14_DEFAULT 0x00002f5b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R15_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R16_DEFAULT 0x00002f5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R17_DEFAULT 0x0000196f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R18_DEFAULT 0x00002f60
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R19_DEFAULT 0x00001970
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R20_DEFAULT 0x00002f61
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R21_DEFAULT 0x00001971
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R22_DEFAULT 0x00002f62
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R23_DEFAULT 0x00001972
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R24_DEFAULT 0x00002f63
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R25_DEFAULT 0x00000147
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R27_DEFAULT 0x0000075e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R29_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R31_DEFAULT 0x00000710
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R1_DEFAULT 0x00001f86
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R2_DEFAULT 0x000044e4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R3_DEFAULT 0x000054e1
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R4_DEFAULT 0x00000710
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R6_DEFAULT 0x0000078c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R8_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R9_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R10_DEFAULT 0x00000029
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R11_DEFAULT 0x00001fe3
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R12_DEFAULT 0x000044f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R13_DEFAULT 0x00001fe4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R14_DEFAULT 0x000044f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R15_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R16_DEFAULT 0x00009fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R17_DEFAULT 0x00001fe3
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R18_DEFAULT 0x000044f4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R19_DEFAULT 0x000054f7
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R20_DEFAULT 0x00000806
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R21_DEFAULT 0x000004f7
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R22_DEFAULT 0x00005500
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R23_DEFAULT 0x00001fe4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R24_DEFAULT 0x000044fa
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R25_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R26_DEFAULT 0x00000806
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R27_DEFAULT 0x000004fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R28_DEFAULT 0x00005571
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R29_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R31_DEFAULT 0x00005027
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R0_DEFAULT 0x00001f59
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R1_DEFAULT 0x00004503
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R2_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R3_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R5_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R6_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R7_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R8_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R9_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R11_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R13_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R14_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R15_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R16_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R17_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R18_DEFAULT 0x0000a080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R19_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R20_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R22_DEFAULT 0x00000741
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R23_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R24_DEFAULT 0x0000051a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R25_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R26_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R27_DEFAULT 0x0000a0c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R29_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R30_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R31_DEFAULT 0x00000742
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R0_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R1_DEFAULT 0x00000523
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R2_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R3_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R4_DEFAULT 0x0000a200
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R6_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R7_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R8_DEFAULT 0x00000743
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R9_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R10_DEFAULT 0x0000052c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R11_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R12_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R13_DEFAULT 0x0000a220
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R14_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R15_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R16_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R17_DEFAULT 0x00000744
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R18_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R19_DEFAULT 0x00000535
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R20_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R21_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R22_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R23_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R25_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R27_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R28_DEFAULT 0x0000320d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R29_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R0_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R1_DEFAULT 0x0000866c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R2_DEFAULT 0x00004d4b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R3_DEFAULT 0x0000827c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R4_DEFAULT 0x00004d46
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R5_DEFAULT 0x00005547
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R6_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R7_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R8_DEFAULT 0x00004d50
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R9_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R10_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R11_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R12_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R13_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R14_DEFAULT 0x00004549
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R15_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R16_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R17_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R18_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R19_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R20_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R21_DEFAULT 0x0000320d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R22_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R23_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R24_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R25_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R26_DEFAULT 0x000078a5
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R27_DEFAULT 0x0000744d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R28_DEFAULT 0x00004d5e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R29_DEFAULT 0x00005567
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R30_DEFAULT 0x000078a4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R31_DEFAULT 0x0000745d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R0_DEFAULT 0x00004d62
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R1_DEFAULT 0x00005563
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R2_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R3_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R4_DEFAULT 0x00004d6c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R5_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R6_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R7_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R8_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R9_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R10_DEFAULT 0x00004565
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R11_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R12_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R13_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R15_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R16_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R17_DEFAULT 0x00001f5e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R18_DEFAULT 0x00004574
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R19_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R20_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R21_DEFAULT 0x00003636
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R22_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R23_DEFAULT 0x0000608c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R24_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R25_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R26_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R27_DEFAULT 0x0000702c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R28_DEFAULT 0x00002969
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R29_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R30_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R31_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R0_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R1_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R2_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R3_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R5_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R6_DEFAULT 0x00003060
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R7_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R8_DEFAULT 0x0000647e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R9_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R10_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R11_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R12_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R13_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R14_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R15_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R16_DEFAULT 0x00000f20
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R17_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R18_DEFAULT 0x000090a0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R19_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R20_DEFAULT 0x00000999
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R22_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R23_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R24_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R25_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R27_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R28_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R29_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R30_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R31_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R0_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R1_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R2_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R3_DEFAULT 0x00002806
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R4_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R6_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R7_DEFAULT 0x00003060
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R8_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R9_DEFAULT 0x0000647e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R10_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R11_DEFAULT 0x00003fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R12_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R13_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R14_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R15_DEFAULT 0x000000c6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R16_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R17_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R18_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R20_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R21_DEFAULT 0x00003000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R22_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R23_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R24_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R25_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R26_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R28_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R29_DEFAULT 0x0000b6b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R30_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R31_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R0_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R1_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R2_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R3_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R4_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R5_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R6_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R7_DEFAULT 0x00003fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R8_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R9_DEFAULT 0x00000084
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R10_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R11_DEFAULT 0x0000b000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R12_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R13_DEFAULT 0x00008080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R14_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R15_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R16_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R17_DEFAULT 0x000030d1
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R18_DEFAULT 0x00007410
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R19_DEFAULT 0x00004dd7
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R20_DEFAULT 0x00000711
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R22_DEFAULT 0x000055d8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R23_DEFAULT 0x00002f11
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R24_DEFAULT 0x00007010
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R25_DEFAULT 0x0000611d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R26_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R27_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R29_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R30_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R31_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R0_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R1_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R3_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R4_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R6_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R9_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R12_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R13_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R14_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R15_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R16_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R17_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R18_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R19_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R20_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R21_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R22_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R23_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R24_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R25_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R26_DEFAULT 0x00005239
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R27_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R28_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R29_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R31_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R1_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R2_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R3_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R4_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R5_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R6_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R7_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R8_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R9_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R10_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R11_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R12_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R13_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R14_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R15_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R16_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R17_DEFAULT 0x0000524b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R18_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R19_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R20_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R21_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R24_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R25_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R26_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R28_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R29_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R31_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R0_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R1_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R2_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R3_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R4_DEFAULT 0x00005255
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R6_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R7_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R9_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R10_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R12_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R13_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R15_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R16_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R17_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R18_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R19_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R20_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R21_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R22_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R23_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R25_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R27_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R28_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R29_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R30_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R31_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R1_DEFAULT 0x00005261
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R3_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R4_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R5_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R6_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R9_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R12_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R13_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R14_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R16_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R18_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R19_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R20_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R21_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R24_DEFAULT 0x00005273
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R25_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R26_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R27_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R29_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R30_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R31_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R0_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R1_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R3_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R6_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R7_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R8_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R9_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R10_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R12_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R13_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R14_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R15_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R16_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R17_DEFAULT 0x0000527d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_CMN_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_DEFAULT 0x00005000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_DEFAULT 0x00005000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_IDCODE_LO_DEFAULT 0x000004cd
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_IDCODE_HI_DEFAULT 0x00003006
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN_DEFAULT 0x00000070
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0_DEFAULT 0x00000328
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_2_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0_DEFAULT 0x00000194
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1_DEFAULT 0x0000a000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_2_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN_DEFAULT 0x000001d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RX_TERM_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT 0x00000d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT 0x00005200
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT 0x0000894a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0_DEFAULT 0x00000025
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT 0x00000d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT 0x00005200
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT 0x0000894a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0_DEFAULT 0x00000025
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC_DEFAULT 0x00000028
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC_DEFAULT 0x00000028
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG_DEFAULT 0x0000000e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_CONFIG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R0_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R1_DEFAULT 0x00001f4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R2_DEFAULT 0x0000297c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R3_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R4_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R5_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R6_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R7_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R9_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R10_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R11_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R12_DEFAULT 0x00000750
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R13_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R14_DEFAULT 0x00000212
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R15_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R16_DEFAULT 0x00004214
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R17_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R18_DEFAULT 0x00001f50
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R19_DEFAULT 0x0000297d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R20_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R21_DEFAULT 0x00000140
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R22_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R23_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R24_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R25_DEFAULT 0x00002800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R26_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R28_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R29_DEFAULT 0x00006800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R31_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R0_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R1_DEFAULT 0x00000745
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R2_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R3_DEFAULT 0x00000227
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R4_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R5_DEFAULT 0x00004227
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R6_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R7_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R8_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R9_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R10_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R11_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R13_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R14_DEFAULT 0x00000015
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R15_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R16_DEFAULT 0x00000746
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R17_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R18_DEFAULT 0x00000236
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R19_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R20_DEFAULT 0x00004236
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R21_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R22_DEFAULT 0x000001b3
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R23_DEFAULT 0x00000177
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R24_DEFAULT 0x000055dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R25_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R26_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R27_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R28_DEFAULT 0x00002800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R29_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R31_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R0_DEFAULT 0x00007000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R1_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R2_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R4_DEFAULT 0x00000173
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R5_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R6_DEFAULT 0x0000024a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R7_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R8_DEFAULT 0x0000424a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R9_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R10_DEFAULT 0x000055fb
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R12_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R13_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R14_DEFAULT 0x00000174
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R15_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R16_DEFAULT 0x00000254
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R17_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R18_DEFAULT 0x00004254
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R19_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R20_DEFAULT 0x00005612
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R21_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R22_DEFAULT 0x00006c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R23_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R24_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R25_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R26_DEFAULT 0x00000179
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R27_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R28_DEFAULT 0x00000260
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R29_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R30_DEFAULT 0x00004260
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R31_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R0_DEFAULT 0x00005625
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R1_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R2_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R3_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R4_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R5_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R7_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R8_DEFAULT 0x00007000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R9_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R10_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R11_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R12_DEFAULT 0x00000175
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R13_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R14_DEFAULT 0x00000272
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R15_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R16_DEFAULT 0x00004272
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R17_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R18_DEFAULT 0x00005642
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R19_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R20_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R22_DEFAULT 0x00000176
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R23_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R24_DEFAULT 0x0000027c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R25_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R26_DEFAULT 0x0000427c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R27_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R28_DEFAULT 0x00005659
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R29_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R30_DEFAULT 0x00006c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R31_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R0_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R2_DEFAULT 0x0000017a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R3_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R4_DEFAULT 0x00000288
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R5_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R6_DEFAULT 0x00004288
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R7_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R8_DEFAULT 0x00001973
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R9_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R10_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R11_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R12_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R13_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R14_DEFAULT 0x00001974
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R15_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R16_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R17_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R18_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R19_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R20_DEFAULT 0x00001979
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R21_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R22_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R23_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R24_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R25_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R26_DEFAULT 0x00001975
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R27_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R29_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R0_DEFAULT 0x00001976
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R1_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R3_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R4_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R6_DEFAULT 0x0000197a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R9_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R12_DEFAULT 0x00001973
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R13_DEFAULT 0x00002f4b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R14_DEFAULT 0x00001974
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R15_DEFAULT 0x00002f4c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R16_DEFAULT 0x00001979
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R17_DEFAULT 0x00002f51
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R18_DEFAULT 0x00001975
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R19_DEFAULT 0x00002f4d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R20_DEFAULT 0x00001976
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R21_DEFAULT 0x00002f4e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R22_DEFAULT 0x0000197a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R23_DEFAULT 0x00002f52
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R24_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R25_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R26_DEFAULT 0x00001f4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R27_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R29_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R0_DEFAULT 0x00001f50
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R1_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R3_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R4_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R6_DEFAULT 0x00001f42
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R9_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R12_DEFAULT 0x00001f43
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R13_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R14_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R15_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R16_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R18_DEFAULT 0x00001f44
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R19_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R20_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R21_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R24_DEFAULT 0x00001f29
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R25_DEFAULT 0x000042f1
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R26_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R27_DEFAULT 0x0000a3a0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R28_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R29_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R30_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R0_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R2_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R4_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R5_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R6_DEFAULT 0x000001b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R8_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R10_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R12_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R13_DEFAULT 0x00000749
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R14_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R15_DEFAULT 0x000002f5
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R16_DEFAULT 0x00005329
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R17_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R18_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R19_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R20_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R21_DEFAULT 0x000001b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R23_DEFAULT 0x000019b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R24_DEFAULT 0x00002f53
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R25_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R27_DEFAULT 0x000001b3
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R28_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R29_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R31_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R1_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R3_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R5_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R6_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R7_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R9_DEFAULT 0x00008660
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R10_DEFAULT 0x00004b15
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R11_DEFAULT 0x00008270
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R12_DEFAULT 0x00004b0e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R13_DEFAULT 0x0000530f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R14_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R15_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R16_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R18_DEFAULT 0x00004b1c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R19_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R20_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R21_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R22_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R24_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R25_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R26_DEFAULT 0x00004313
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R27_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R28_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R29_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R30_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R31_DEFAULT 0x0000301d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R0_DEFAULT 0x00004325
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R1_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R2_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R3_DEFAULT 0x00003054
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R4_DEFAULT 0x00005327
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R5_DEFAULT 0x00007445
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R6_DEFAULT 0x0000430e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R7_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R8_DEFAULT 0x00005309
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R9_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R10_DEFAULT 0x00008670
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R11_DEFAULT 0x00004b2d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R12_DEFAULT 0x0000532e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R13_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R14_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R15_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R16_DEFAULT 0x0000ffe8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R17_DEFAULT 0x0000701d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R18_DEFAULT 0x00004b35
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R19_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R20_DEFAULT 0x0000532d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R21_DEFAULT 0x0000741d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R22_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R23_DEFAULT 0x0000074a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R24_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R25_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R26_DEFAULT 0x00003323
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R27_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R29_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R30_DEFAULT 0x0000532a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R31_DEFAULT 0x00001f2a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R0_DEFAULT 0x00004377
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R1_DEFAULT 0x0000075e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R4_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R5_DEFAULT 0x00001f09
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R8_DEFAULT 0x0000080c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R9_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R10_DEFAULT 0x000070cd
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R11_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R12_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R13_DEFAULT 0x00002f05
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R14_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R15_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R16_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R17_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R19_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R20_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R21_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R22_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R23_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R24_DEFAULT 0x0000435a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R25_DEFAULT 0x00005357
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R26_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R27_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R28_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R29_DEFAULT 0x0000435c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R30_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R31_DEFAULT 0x00000600
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R0_DEFAULT 0x00001f09
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R1_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R2_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R3_DEFAULT 0x0000608d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R4_DEFAULT 0x0000700d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R5_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R6_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R7_DEFAULT 0x00002f05
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R8_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R9_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R10_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R11_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R12_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R13_DEFAULT 0x0000436f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R14_DEFAULT 0x0000536c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R15_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R17_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R18_DEFAULT 0x00004371
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R19_DEFAULT 0x00000705
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R20_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R21_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R23_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R24_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R25_DEFAULT 0x00000147
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R27_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R29_DEFAULT 0x00001f6b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R30_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R31_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R0_DEFAULT 0x00000200
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R1_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R2_DEFAULT 0x00000042
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R3_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R4_DEFAULT 0x0000007e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R5_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R7_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R9_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R10_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R11_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R12_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R13_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R15_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R16_DEFAULT 0x00003636
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R17_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R18_DEFAULT 0x0000608c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R19_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R20_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R21_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R22_DEFAULT 0x0000702c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R23_DEFAULT 0x00002969
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R24_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R25_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R26_DEFAULT 0x00001f67
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R27_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R28_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R29_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R30_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R31_DEFAULT 0x00003c02
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R0_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R2_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R3_DEFAULT 0x00007060
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R4_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R5_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R6_DEFAULT 0x00001f2a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R7_DEFAULT 0x000043a9
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R8_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R9_DEFAULT 0x00001f68
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R10_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R11_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R12_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R13_DEFAULT 0x00001f6c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R14_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R15_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R16_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R17_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R18_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R19_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R20_DEFAULT 0x00004fa0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R22_DEFAULT 0x00007828
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R23_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R24_DEFAULT 0x000036dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R25_DEFAULT 0x00001f2b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R26_DEFAULT 0x000043bc
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R27_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R28_DEFAULT 0x00001f69
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R29_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R30_DEFAULT 0x00001f6d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R31_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R0_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R1_DEFAULT 0x00007818
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R2_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R3_DEFAULT 0x0000124a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R4_DEFAULT 0x00001f2b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R5_DEFAULT 0x000043c7
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R6_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R7_DEFAULT 0x00001f6a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R8_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R9_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R10_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R11_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R12_DEFAULT 0x00002806
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R13_DEFAULT 0x00001f6e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R14_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R15_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R16_DEFAULT 0x000000c6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R17_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R18_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R19_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R20_DEFAULT 0x00003000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R22_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R23_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R24_DEFAULT 0x0000b6b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R25_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R26_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R27_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R28_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R29_DEFAULT 0x00001f6a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R30_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R31_DEFAULT 0x00001f6e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R0_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R1_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R2_DEFAULT 0x00000084
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R3_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R4_DEFAULT 0x0000b000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R5_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R6_DEFAULT 0x00008080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R7_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R8_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R9_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R10_DEFAULT 0x000074d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R11_DEFAULT 0x00004bef
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R12_DEFAULT 0x00000711
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R14_DEFAULT 0x000053f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R15_DEFAULT 0x00002f11
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R16_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R17_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R18_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R20_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R21_DEFAULT 0x00003c46
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R22_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R24_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R25_DEFAULT 0x00007020
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R26_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R27_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R28_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R29_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R30_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R31_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R0_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R1_DEFAULT 0x00004408
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R2_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R3_DEFAULT 0x00000fe0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R4_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R5_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R6_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R7_DEFAULT 0x0000540d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R8_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R9_DEFAULT 0x00000fc0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R10_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R11_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R12_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R13_DEFAULT 0x000030c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R14_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R15_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R16_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R17_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R18_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R19_DEFAULT 0x000030c5
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R20_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R21_DEFAULT 0x00000036
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R22_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R23_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R24_DEFAULT 0x000030dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R25_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R27_DEFAULT 0x00007435
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R28_DEFAULT 0x00004c23
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R29_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R30_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R31_DEFAULT 0x00004c38
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R0_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R2_DEFAULT 0x00005438
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R4_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R5_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R8_DEFAULT 0x0000442c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R9_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R10_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R11_DEFAULT 0x0000542e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R12_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R13_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R14_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R15_DEFAULT 0x0000703d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R16_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R17_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R18_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R19_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R20_DEFAULT 0x00004c36
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R21_DEFAULT 0x00005438
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R22_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R23_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R24_DEFAULT 0x00006082
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R25_DEFAULT 0x00006182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R26_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R27_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R29_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R31_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R0_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R1_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R2_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R3_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R4_DEFAULT 0x000030dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R5_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R6_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R7_DEFAULT 0x00007435
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R8_DEFAULT 0x00004c4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R9_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R10_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R11_DEFAULT 0x00004c64
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R12_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R14_DEFAULT 0x00005464
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R16_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R17_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R18_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R20_DEFAULT 0x00004458
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R21_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R22_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R23_DEFAULT 0x0000545a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R24_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R25_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R26_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R27_DEFAULT 0x0000703d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R28_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R29_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R30_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R31_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R0_DEFAULT 0x00004c62
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R1_DEFAULT 0x00005464
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R2_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R3_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R4_DEFAULT 0x00006082
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R5_DEFAULT 0x00006182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R6_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R9_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R12_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R14_DEFAULT 0x00008647
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R16_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R17_DEFAULT 0x00001989
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R18_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R20_DEFAULT 0x0000601d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R21_DEFAULT 0x000030d3
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R22_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R23_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R24_DEFAULT 0x00001986
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R25_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R26_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R27_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R28_DEFAULT 0x000030d4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R29_DEFAULT 0x0000613d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R30_DEFAULT 0x000030d1
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R31_DEFAULT 0x00003025
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R0_DEFAULT 0x00006115
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R1_DEFAULT 0x00007052
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R2_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R3_DEFAULT 0x00007021
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R4_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R5_DEFAULT 0x00004c87
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R6_DEFAULT 0x0000548d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R7_DEFAULT 0x00007414
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R8_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R9_DEFAULT 0x00007052
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R10_DEFAULT 0x000074d3
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R11_DEFAULT 0x00004c93
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R12_DEFAULT 0x00005490
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R13_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R15_DEFAULT 0x00005495
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R16_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R17_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R18_DEFAULT 0x00005495
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R19_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R22_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R23_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R24_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R25_DEFAULT 0x00000804
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R26_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R27_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R28_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R29_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R30_DEFAULT 0x000003e0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R31_DEFAULT 0x0000116d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R0_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R1_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R2_DEFAULT 0x000030c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R4_DEFAULT 0x00000fe0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R5_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R8_DEFAULT 0x000030c3
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R9_DEFAULT 0x00007420
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R10_DEFAULT 0x00004cac
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R11_DEFAULT 0x000054c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R12_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R13_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R14_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R16_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R17_DEFAULT 0x000044b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R18_DEFAULT 0x00007434
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R19_DEFAULT 0x00004cb5
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R20_DEFAULT 0x000054c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R21_DEFAULT 0x00007412
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R22_DEFAULT 0x00004cb8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R23_DEFAULT 0x000054c1
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R24_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R25_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R26_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R27_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R28_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R29_DEFAULT 0x000044c1
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R30_DEFAULT 0x000054bf
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R31_DEFAULT 0x00007453
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R0_DEFAULT 0x00004cc7
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R1_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R2_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R3_DEFAULT 0x000054c9
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R4_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R6_DEFAULT 0x000054c9
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R7_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R9_DEFAULT 0x0000196b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R10_DEFAULT 0x00002f5a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R11_DEFAULT 0x0000196d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R12_DEFAULT 0x00002f5c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R13_DEFAULT 0x0000196c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R14_DEFAULT 0x00002f5b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R15_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R16_DEFAULT 0x00002f5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R17_DEFAULT 0x0000196f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R18_DEFAULT 0x00002f60
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R19_DEFAULT 0x00001970
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R20_DEFAULT 0x00002f61
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R21_DEFAULT 0x00001971
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R22_DEFAULT 0x00002f62
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R23_DEFAULT 0x00001972
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R24_DEFAULT 0x00002f63
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R25_DEFAULT 0x00000147
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R27_DEFAULT 0x0000075e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R29_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R31_DEFAULT 0x00000710
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R1_DEFAULT 0x00001f86
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R2_DEFAULT 0x000044e4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R3_DEFAULT 0x000054e1
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R4_DEFAULT 0x00000710
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R6_DEFAULT 0x0000078c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R8_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R9_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R10_DEFAULT 0x00000029
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R11_DEFAULT 0x00001fe3
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R12_DEFAULT 0x000044f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R13_DEFAULT 0x00001fe4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R14_DEFAULT 0x000044f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R15_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R16_DEFAULT 0x00009fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R17_DEFAULT 0x00001fe3
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R18_DEFAULT 0x000044f4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R19_DEFAULT 0x000054f7
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R20_DEFAULT 0x00000806
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R21_DEFAULT 0x000004f7
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R22_DEFAULT 0x00005500
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R23_DEFAULT 0x00001fe4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R24_DEFAULT 0x000044fa
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R25_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R26_DEFAULT 0x00000806
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R27_DEFAULT 0x000004fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R28_DEFAULT 0x00005571
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R29_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R31_DEFAULT 0x00005027
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R0_DEFAULT 0x00001f59
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R1_DEFAULT 0x00004503
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R2_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R3_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R5_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R6_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R7_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R8_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R9_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R11_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R13_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R14_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R15_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R16_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R17_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R18_DEFAULT 0x0000a080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R19_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R20_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R22_DEFAULT 0x00000741
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R23_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R24_DEFAULT 0x0000051a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R25_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R26_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R27_DEFAULT 0x0000a0c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R29_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R30_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R31_DEFAULT 0x00000742
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R0_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R1_DEFAULT 0x00000523
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R2_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R3_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R4_DEFAULT 0x0000a200
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R6_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R7_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R8_DEFAULT 0x00000743
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R9_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R10_DEFAULT 0x0000052c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R11_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R12_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R13_DEFAULT 0x0000a220
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R14_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R15_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R16_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R17_DEFAULT 0x00000744
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R18_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R19_DEFAULT 0x00000535
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R20_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R21_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R22_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R23_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R25_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R27_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R28_DEFAULT 0x0000320d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R29_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R0_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R1_DEFAULT 0x0000866c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R2_DEFAULT 0x00004d4b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R3_DEFAULT 0x0000827c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R4_DEFAULT 0x00004d46
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R5_DEFAULT 0x00005547
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R6_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R7_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R8_DEFAULT 0x00004d50
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R9_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R10_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R11_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R12_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R13_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R14_DEFAULT 0x00004549
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R15_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R16_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R17_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R18_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R19_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R20_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R21_DEFAULT 0x0000320d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R22_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R23_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R24_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R25_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R26_DEFAULT 0x000078a5
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R27_DEFAULT 0x0000744d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R28_DEFAULT 0x00004d5e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R29_DEFAULT 0x00005567
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R30_DEFAULT 0x000078a4
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R31_DEFAULT 0x0000745d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R0_DEFAULT 0x00004d62
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R1_DEFAULT 0x00005563
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R2_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R3_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R4_DEFAULT 0x00004d6c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R5_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R6_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R7_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R8_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R9_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R10_DEFAULT 0x00004565
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R11_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R12_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R13_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R15_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R16_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R17_DEFAULT 0x00001f5e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R18_DEFAULT 0x00004574
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R19_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R20_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R21_DEFAULT 0x00003636
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R22_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R23_DEFAULT 0x0000608c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R24_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R25_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R26_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R27_DEFAULT 0x0000702c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R28_DEFAULT 0x00002969
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R29_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R30_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R31_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R0_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R1_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R2_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R3_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R5_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R6_DEFAULT 0x00003060
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R7_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R8_DEFAULT 0x0000647e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R9_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R10_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R11_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R12_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R13_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R14_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R15_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R16_DEFAULT 0x00000f20
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R17_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R18_DEFAULT 0x000090a0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R19_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R20_DEFAULT 0x00000999
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R22_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R23_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R24_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R25_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R27_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R28_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R29_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R30_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R31_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R0_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R1_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R2_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R3_DEFAULT 0x00002806
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R4_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R6_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R7_DEFAULT 0x00003060
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R8_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R9_DEFAULT 0x0000647e
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R10_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R11_DEFAULT 0x00003fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R12_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R13_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R14_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R15_DEFAULT 0x000000c6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R16_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R17_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R18_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R20_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R21_DEFAULT 0x00003000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R22_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R23_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R24_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R25_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R26_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R28_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R29_DEFAULT 0x0000b6b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R30_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R31_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R0_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R1_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R2_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R3_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R4_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R5_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R6_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R7_DEFAULT 0x00003fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R8_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R9_DEFAULT 0x00000084
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R10_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R11_DEFAULT 0x0000b000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R12_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R13_DEFAULT 0x00008080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R14_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R15_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R16_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R17_DEFAULT 0x000030d1
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R18_DEFAULT 0x00007410
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R19_DEFAULT 0x00004dd7
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R20_DEFAULT 0x00000711
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R22_DEFAULT 0x000055d8
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R23_DEFAULT 0x00002f11
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R24_DEFAULT 0x00007010
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R25_DEFAULT 0x0000611d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R26_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R27_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R29_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R30_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R31_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R0_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R1_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R3_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R4_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R6_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R9_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R12_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R13_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R14_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R15_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R16_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R17_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R18_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R19_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R20_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R21_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R22_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R23_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R24_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R25_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R26_DEFAULT 0x00005239
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R27_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R28_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R29_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R31_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R1_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R2_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R3_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R4_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R5_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R6_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R7_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R8_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R9_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R10_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R11_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R12_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R13_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R14_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R15_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R16_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R17_DEFAULT 0x0000524b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R18_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R19_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R20_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R21_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R24_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R25_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R26_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R28_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R29_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R31_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R0_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R1_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R2_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R3_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R4_DEFAULT 0x00005255
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R6_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R7_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R9_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R10_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R12_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R13_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R15_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R16_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R17_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R18_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R19_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R20_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R21_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R22_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R23_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R25_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R27_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R28_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R29_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R30_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R31_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R1_DEFAULT 0x00005261
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R3_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R4_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R5_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R6_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R9_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R12_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R13_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R14_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R16_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R18_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R19_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R20_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R21_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R24_DEFAULT 0x00005273
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R25_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R26_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R27_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R29_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R30_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R31_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R0_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R1_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R3_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R6_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R7_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R8_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R9_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R10_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R12_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R13_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R14_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R15_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R16_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R17_DEFAULT 0x0000527d
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_CMN_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN_DEFAULT 0x00005000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN_DEFAULT 0x00005000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_lcu_kpfifo_kpfifo2_kpfifo_dir
+#define smnKPFIFO2_PRI_TX_FIFO_HSCID_DEFAULT 0x00000000
+#define smnKPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0_DEFAULT 0x00000000
+#define smnKPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1_DEFAULT 0x00000000
+#define smnKPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2_DEFAULT 0x00000000
+#define smnKPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3_DEFAULT 0x00000000
+#define smnKPFIFO2_PCS_PMA_SOFT_RESET_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_lcu_kpnp_kpnp2_kpnp_dir
+#define smnKPNP_SNPS2_KPNP_HWSCVER_DEFAULT 0x00000000
+#define smnKPNP_SNPS2_KPNP_PHY_INFO_DEFAULT 0x00000000
+#define smnKPNP_SNPS2_KPNP_LANE_ID_DEFAULT 0x00000000
+#define smnKPNP_SNPS2_KPNP_LANE_REQ_CONTROL_DEFAULT 0x00000000
+#define smnKPNP_SNPS2_KPNP_LANE_REQ_STATUS_DEFAULT 0x00000000
+#define smnKPNP_SNPS2_KPNP_PMA_CONTROL0_DEFAULT 0x00000000
+#define smnKPNP_SNPS2_KPNP_PMA_CONTROL1_DEFAULT 0x000000b1
+#define smnKPNP_SNPS2_KPNP_PMA_CONTROL2_DEFAULT 0x00000004
+#define smnKPNP_SNPS2_KPNP_PHY_SOFT_RESET_DEFAULT 0x00000000
+#define smnKPNP_SNPS2_KPNP_LANE_SOFT_RESET_DEFAULT 0x000000ff
+#define smnKPNP_SNPS2_REG_RST_CTRL_DEFAULT 0x00000001
+
+
+// addressBlock: nbio_pipe_pcs_dwc_e12mp_phy_x4_ns3_dwc_e12mp_phy_x4_ns_UP16_dwc_e12mp_phy_x4_ns_UP16_mem_map
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_IDCODE_LO_DEFAULT 0x000074cd
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_IDCODE_HI_DEFAULT 0x00000733
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN_DEFAULT 0x00000070
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0_DEFAULT 0x00000328
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_2_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0_DEFAULT 0x00000194
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1_DEFAULT 0x0000a000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_2_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN_DEFAULT 0x000001d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RX_TERM_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT 0x00000d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT 0x00005200
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT 0x0000894a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0_DEFAULT 0x00000025
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT 0x00000d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT 0x00005200
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT 0x0000894a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0_DEFAULT 0x00000025
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC_DEFAULT 0x00000028
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC_DEFAULT 0x00000028
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG_DEFAULT 0x0000000e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_CONFIG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R0_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R1_DEFAULT 0x00001f4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R2_DEFAULT 0x0000297c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R3_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R4_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R5_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R6_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R7_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R9_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R10_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R11_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R12_DEFAULT 0x00000750
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R13_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R14_DEFAULT 0x00000212
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R15_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R16_DEFAULT 0x00004214
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R17_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R18_DEFAULT 0x00001f50
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R19_DEFAULT 0x0000297d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R20_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R21_DEFAULT 0x00000140
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R22_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R23_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R24_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R25_DEFAULT 0x00002800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R26_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R28_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R29_DEFAULT 0x00006800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R31_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R0_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R1_DEFAULT 0x00000745
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R2_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R3_DEFAULT 0x00000227
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R4_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R5_DEFAULT 0x00004227
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R6_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R7_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R8_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R9_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R10_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R11_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R13_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R14_DEFAULT 0x00000015
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R15_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R16_DEFAULT 0x00000746
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R17_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R18_DEFAULT 0x00000236
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R19_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R20_DEFAULT 0x00004236
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R21_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R22_DEFAULT 0x000001b3
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R23_DEFAULT 0x00000177
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R24_DEFAULT 0x000055dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R25_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R26_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R27_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R28_DEFAULT 0x00002800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R29_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R31_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R0_DEFAULT 0x00007000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R1_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R2_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R4_DEFAULT 0x00000173
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R5_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R6_DEFAULT 0x0000024a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R7_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R8_DEFAULT 0x0000424a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R9_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R10_DEFAULT 0x000055fb
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R12_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R13_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R14_DEFAULT 0x00000174
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R15_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R16_DEFAULT 0x00000254
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R17_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R18_DEFAULT 0x00004254
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R19_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R20_DEFAULT 0x00005612
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R21_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R22_DEFAULT 0x00006c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R23_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R24_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R25_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R26_DEFAULT 0x00000179
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R27_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R28_DEFAULT 0x00000260
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R29_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R30_DEFAULT 0x00004260
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R31_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R0_DEFAULT 0x00005625
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R1_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R2_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R3_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R4_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R5_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R7_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R8_DEFAULT 0x00007000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R9_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R10_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R11_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R12_DEFAULT 0x00000175
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R13_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R14_DEFAULT 0x00000272
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R15_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R16_DEFAULT 0x00004272
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R17_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R18_DEFAULT 0x00005642
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R19_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R20_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R22_DEFAULT 0x00000176
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R23_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R24_DEFAULT 0x0000027c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R25_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R26_DEFAULT 0x0000427c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R27_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R28_DEFAULT 0x00005659
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R29_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R30_DEFAULT 0x00006c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R31_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R0_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R2_DEFAULT 0x0000017a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R3_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R4_DEFAULT 0x00000288
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R5_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R6_DEFAULT 0x00004288
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R7_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R8_DEFAULT 0x00001973
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R9_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R10_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R11_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R12_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R13_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R14_DEFAULT 0x00001974
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R15_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R16_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R17_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R18_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R19_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R20_DEFAULT 0x00001979
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R21_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R22_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R23_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R24_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R25_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R26_DEFAULT 0x00001975
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R27_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R29_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R0_DEFAULT 0x00001976
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R1_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R3_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R4_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R6_DEFAULT 0x0000197a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R9_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R12_DEFAULT 0x00001973
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R13_DEFAULT 0x00002f4b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R14_DEFAULT 0x00001974
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R15_DEFAULT 0x00002f4c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R16_DEFAULT 0x00001979
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R17_DEFAULT 0x00002f51
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R18_DEFAULT 0x00001975
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R19_DEFAULT 0x00002f4d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R20_DEFAULT 0x00001976
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R21_DEFAULT 0x00002f4e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R22_DEFAULT 0x0000197a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R23_DEFAULT 0x00002f52
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R24_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R25_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R26_DEFAULT 0x00001f4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R27_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R29_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R0_DEFAULT 0x00001f50
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R1_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R3_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R4_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R6_DEFAULT 0x00001f42
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R9_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R12_DEFAULT 0x00001f43
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R13_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R14_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R15_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R16_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R18_DEFAULT 0x00001f44
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R19_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R20_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R21_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R24_DEFAULT 0x00001f29
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R25_DEFAULT 0x000042f1
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R26_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R27_DEFAULT 0x0000a3a0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R28_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R29_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R30_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R0_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R2_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R4_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R5_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R6_DEFAULT 0x000001b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R8_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R10_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R12_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R13_DEFAULT 0x00000749
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R14_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R15_DEFAULT 0x000002f5
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R16_DEFAULT 0x00005329
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R17_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R18_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R19_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R20_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R21_DEFAULT 0x000001b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R23_DEFAULT 0x000019b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R24_DEFAULT 0x00002f53
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R25_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R27_DEFAULT 0x000001b3
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R28_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R29_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R31_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R1_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R3_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R5_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R6_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R7_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R9_DEFAULT 0x00008660
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R10_DEFAULT 0x00004b15
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R11_DEFAULT 0x00008270
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R12_DEFAULT 0x00004b0e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R13_DEFAULT 0x0000530f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R14_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R15_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R16_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R18_DEFAULT 0x00004b1c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R19_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R20_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R21_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R22_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R24_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R25_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R26_DEFAULT 0x00004313
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R27_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R28_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R29_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R30_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R31_DEFAULT 0x0000301d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R0_DEFAULT 0x00004325
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R1_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R2_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R3_DEFAULT 0x00003054
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R4_DEFAULT 0x00005327
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R5_DEFAULT 0x00007445
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R6_DEFAULT 0x0000430e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R7_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R8_DEFAULT 0x00005309
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R9_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R10_DEFAULT 0x00008670
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R11_DEFAULT 0x00004b2d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R12_DEFAULT 0x0000532e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R13_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R14_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R15_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R16_DEFAULT 0x0000ffe8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R17_DEFAULT 0x0000701d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R18_DEFAULT 0x00004b35
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R19_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R20_DEFAULT 0x0000532d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R21_DEFAULT 0x0000741d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R22_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R23_DEFAULT 0x0000074a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R24_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R25_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R26_DEFAULT 0x00003323
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R27_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R29_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R30_DEFAULT 0x0000532a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R31_DEFAULT 0x00001f2a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R0_DEFAULT 0x00004377
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R1_DEFAULT 0x0000075e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R4_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R5_DEFAULT 0x00001f09
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R8_DEFAULT 0x0000080c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R9_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R10_DEFAULT 0x000070cd
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R11_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R12_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R13_DEFAULT 0x00002f05
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R14_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R15_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R16_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R17_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R19_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R20_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R21_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R22_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R23_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R24_DEFAULT 0x0000435a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R25_DEFAULT 0x00005357
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R26_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R27_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R28_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R29_DEFAULT 0x0000435c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R30_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R31_DEFAULT 0x00000600
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R0_DEFAULT 0x00001f09
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R1_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R2_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R3_DEFAULT 0x0000608d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R4_DEFAULT 0x0000700d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R5_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R6_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R7_DEFAULT 0x00002f05
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R8_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R9_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R10_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R11_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R12_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R13_DEFAULT 0x0000436f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R14_DEFAULT 0x0000536c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R15_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R17_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R18_DEFAULT 0x00004371
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R19_DEFAULT 0x00000705
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R20_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R21_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R23_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R24_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R25_DEFAULT 0x00000147
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R27_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R29_DEFAULT 0x00001f6b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R30_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R31_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R0_DEFAULT 0x00000200
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R1_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R2_DEFAULT 0x00000042
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R3_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R4_DEFAULT 0x0000007e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R5_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R7_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R9_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R10_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R11_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R12_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R13_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R15_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R16_DEFAULT 0x00003636
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R17_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R18_DEFAULT 0x0000608c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R19_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R20_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R21_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R22_DEFAULT 0x0000702c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R23_DEFAULT 0x00002969
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R24_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R25_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R26_DEFAULT 0x00001f67
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R27_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R28_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R29_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R30_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R31_DEFAULT 0x00003c02
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R0_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R2_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R3_DEFAULT 0x00007060
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R4_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R5_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R6_DEFAULT 0x00001f2a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R7_DEFAULT 0x000043a9
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R8_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R9_DEFAULT 0x00001f68
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R10_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R11_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R12_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R13_DEFAULT 0x00001f6c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R14_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R15_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R16_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R17_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R18_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R19_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R20_DEFAULT 0x00004fa0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R22_DEFAULT 0x00007828
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R23_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R24_DEFAULT 0x000036dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R25_DEFAULT 0x00001f2b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R26_DEFAULT 0x000043bc
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R27_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R28_DEFAULT 0x00001f69
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R29_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R30_DEFAULT 0x00001f6d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R31_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R0_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R1_DEFAULT 0x00007818
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R2_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R3_DEFAULT 0x0000124a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R4_DEFAULT 0x00001f2b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R5_DEFAULT 0x000043c7
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R6_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R7_DEFAULT 0x00001f6a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R8_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R9_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R10_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R11_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R12_DEFAULT 0x00002806
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R13_DEFAULT 0x00001f6e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R14_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R15_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R16_DEFAULT 0x000000c6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R17_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R18_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R19_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R20_DEFAULT 0x00003000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R22_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R23_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R24_DEFAULT 0x0000b6b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R25_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R26_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R27_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R28_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R29_DEFAULT 0x00001f6a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R30_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R31_DEFAULT 0x00001f6e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R0_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R1_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R2_DEFAULT 0x00000084
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R3_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R4_DEFAULT 0x0000b000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R5_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R6_DEFAULT 0x00008080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R7_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R8_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R9_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R10_DEFAULT 0x000074d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R11_DEFAULT 0x00004bef
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R12_DEFAULT 0x00000711
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R14_DEFAULT 0x000053f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R15_DEFAULT 0x00002f11
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R16_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R17_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R18_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R20_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R21_DEFAULT 0x00003c46
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R22_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R24_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R25_DEFAULT 0x00007020
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R26_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R27_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R28_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R29_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R30_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R31_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R0_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R1_DEFAULT 0x00004408
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R2_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R3_DEFAULT 0x00000fe0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R4_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R5_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R6_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R7_DEFAULT 0x0000540d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R8_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R9_DEFAULT 0x00000fc0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R10_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R11_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R12_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R13_DEFAULT 0x000030c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R14_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R15_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R16_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R17_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R18_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R19_DEFAULT 0x000030c5
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R20_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R21_DEFAULT 0x00000036
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R22_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R23_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R24_DEFAULT 0x000030dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R25_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R27_DEFAULT 0x00007435
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R28_DEFAULT 0x00004c23
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R29_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R30_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R31_DEFAULT 0x00004c38
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R0_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R2_DEFAULT 0x00005438
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R4_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R5_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R8_DEFAULT 0x0000442c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R9_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R10_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R11_DEFAULT 0x0000542e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R12_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R13_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R14_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R15_DEFAULT 0x0000703d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R16_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R17_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R18_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R19_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R20_DEFAULT 0x00004c36
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R21_DEFAULT 0x00005438
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R22_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R23_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R24_DEFAULT 0x00006082
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R25_DEFAULT 0x00006182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R26_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R27_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R29_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R31_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R0_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R1_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R2_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R3_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R4_DEFAULT 0x000030dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R5_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R6_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R7_DEFAULT 0x00007435
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R8_DEFAULT 0x00004c4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R9_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R10_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R11_DEFAULT 0x00004c64
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R12_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R14_DEFAULT 0x00005464
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R16_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R17_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R18_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R20_DEFAULT 0x00004458
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R21_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R22_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R23_DEFAULT 0x0000545a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R24_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R25_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R26_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R27_DEFAULT 0x0000703d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R28_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R29_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R30_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R31_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R0_DEFAULT 0x00004c62
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R1_DEFAULT 0x00005464
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R2_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R3_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R4_DEFAULT 0x00006082
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R5_DEFAULT 0x00006182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R6_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R9_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R12_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R14_DEFAULT 0x00008647
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R16_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R17_DEFAULT 0x00001989
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R18_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R20_DEFAULT 0x0000601d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R21_DEFAULT 0x000030d3
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R22_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R23_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R24_DEFAULT 0x00001986
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R25_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R26_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R27_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R28_DEFAULT 0x000030d4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R29_DEFAULT 0x0000613d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R30_DEFAULT 0x000030d1
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R31_DEFAULT 0x00003025
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R0_DEFAULT 0x00006115
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R1_DEFAULT 0x00007052
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R2_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R3_DEFAULT 0x00007021
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R4_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R5_DEFAULT 0x00004c87
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R6_DEFAULT 0x0000548d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R7_DEFAULT 0x00007414
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R8_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R9_DEFAULT 0x00007052
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R10_DEFAULT 0x000074d3
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R11_DEFAULT 0x00004c93
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R12_DEFAULT 0x00005490
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R13_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R15_DEFAULT 0x00005495
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R16_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R17_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R18_DEFAULT 0x00005495
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R19_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R22_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R23_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R24_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R25_DEFAULT 0x00000804
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R26_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R27_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R28_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R29_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R30_DEFAULT 0x000003e0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R31_DEFAULT 0x0000116d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R0_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R1_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R2_DEFAULT 0x000030c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R4_DEFAULT 0x00000fe0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R5_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R8_DEFAULT 0x000030c3
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R9_DEFAULT 0x00007420
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R10_DEFAULT 0x00004cac
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R11_DEFAULT 0x000054c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R12_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R13_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R14_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R16_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R17_DEFAULT 0x000044b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R18_DEFAULT 0x00007434
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R19_DEFAULT 0x00004cb5
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R20_DEFAULT 0x000054c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R21_DEFAULT 0x00007412
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R22_DEFAULT 0x00004cb8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R23_DEFAULT 0x000054c1
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R24_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R25_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R26_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R27_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R28_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R29_DEFAULT 0x000044c1
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R30_DEFAULT 0x000054bf
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R31_DEFAULT 0x00007453
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R0_DEFAULT 0x00004cc7
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R1_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R2_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R3_DEFAULT 0x000054c9
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R4_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R6_DEFAULT 0x000054c9
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R7_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R9_DEFAULT 0x0000196b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R10_DEFAULT 0x00002f5a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R11_DEFAULT 0x0000196d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R12_DEFAULT 0x00002f5c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R13_DEFAULT 0x0000196c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R14_DEFAULT 0x00002f5b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R15_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R16_DEFAULT 0x00002f5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R17_DEFAULT 0x0000196f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R18_DEFAULT 0x00002f60
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R19_DEFAULT 0x00001970
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R20_DEFAULT 0x00002f61
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R21_DEFAULT 0x00001971
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R22_DEFAULT 0x00002f62
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R23_DEFAULT 0x00001972
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R24_DEFAULT 0x00002f63
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R25_DEFAULT 0x00000147
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R27_DEFAULT 0x0000075e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R29_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R31_DEFAULT 0x00000710
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R1_DEFAULT 0x00001f86
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R2_DEFAULT 0x000044e4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R3_DEFAULT 0x000054e1
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R4_DEFAULT 0x00000710
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R6_DEFAULT 0x0000078c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R8_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R9_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R10_DEFAULT 0x00000029
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R11_DEFAULT 0x00001fe3
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R12_DEFAULT 0x000044f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R13_DEFAULT 0x00001fe4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R14_DEFAULT 0x000044f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R15_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R16_DEFAULT 0x00009fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R17_DEFAULT 0x00001fe3
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R18_DEFAULT 0x000044f4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R19_DEFAULT 0x000054f7
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R20_DEFAULT 0x00000806
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R21_DEFAULT 0x000004f7
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R22_DEFAULT 0x00005500
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R23_DEFAULT 0x00001fe4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R24_DEFAULT 0x000044fa
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R25_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R26_DEFAULT 0x00000806
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R27_DEFAULT 0x000004fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R28_DEFAULT 0x00005571
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R29_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R31_DEFAULT 0x00005027
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R0_DEFAULT 0x00001f59
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R1_DEFAULT 0x00004503
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R2_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R3_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R5_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R6_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R7_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R8_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R9_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R11_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R13_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R14_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R15_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R16_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R17_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R18_DEFAULT 0x0000a080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R19_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R20_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R22_DEFAULT 0x00000741
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R23_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R24_DEFAULT 0x0000051a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R25_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R26_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R27_DEFAULT 0x0000a0c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R29_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R30_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R31_DEFAULT 0x00000742
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R0_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R1_DEFAULT 0x00000523
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R2_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R3_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R4_DEFAULT 0x0000a200
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R6_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R7_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R8_DEFAULT 0x00000743
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R9_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R10_DEFAULT 0x0000052c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R11_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R12_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R13_DEFAULT 0x0000a220
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R14_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R15_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R16_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R17_DEFAULT 0x00000744
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R18_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R19_DEFAULT 0x00000535
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R20_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R21_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R22_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R23_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R25_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R27_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R28_DEFAULT 0x0000320d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R29_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R0_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R1_DEFAULT 0x0000866c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R2_DEFAULT 0x00004d4b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R3_DEFAULT 0x0000827c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R4_DEFAULT 0x00004d46
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R5_DEFAULT 0x00005547
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R6_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R7_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R8_DEFAULT 0x00004d50
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R9_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R10_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R11_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R12_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R13_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R14_DEFAULT 0x00004549
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R15_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R16_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R17_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R18_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R19_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R20_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R21_DEFAULT 0x0000320d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R22_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R23_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R24_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R25_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R26_DEFAULT 0x000078a5
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R27_DEFAULT 0x0000744d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R28_DEFAULT 0x00004d5e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R29_DEFAULT 0x00005567
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R30_DEFAULT 0x000078a4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R31_DEFAULT 0x0000745d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R0_DEFAULT 0x00004d62
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R1_DEFAULT 0x00005563
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R2_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R3_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R4_DEFAULT 0x00004d6c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R5_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R6_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R7_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R8_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R9_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R10_DEFAULT 0x00004565
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R11_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R12_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R13_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R15_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R16_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R17_DEFAULT 0x00001f5e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R18_DEFAULT 0x00004574
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R19_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R20_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R21_DEFAULT 0x00003636
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R22_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R23_DEFAULT 0x0000608c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R24_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R25_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R26_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R27_DEFAULT 0x0000702c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R28_DEFAULT 0x00002969
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R29_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R30_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R31_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R0_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R1_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R2_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R3_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R5_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R6_DEFAULT 0x00003060
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R7_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R8_DEFAULT 0x0000647e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R9_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R10_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R11_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R12_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R13_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R14_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R15_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R16_DEFAULT 0x00000f20
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R17_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R18_DEFAULT 0x000090a0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R19_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R20_DEFAULT 0x00000999
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R22_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R23_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R24_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R25_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R27_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R28_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R29_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R30_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R31_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R0_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R1_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R2_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R3_DEFAULT 0x00002806
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R4_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R6_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R7_DEFAULT 0x00003060
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R8_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R9_DEFAULT 0x0000647e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R10_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R11_DEFAULT 0x00003fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R12_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R13_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R14_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R15_DEFAULT 0x000000c6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R16_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R17_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R18_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R20_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R21_DEFAULT 0x00003000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R22_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R23_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R24_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R25_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R26_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R28_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R29_DEFAULT 0x0000b6b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R30_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R31_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R0_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R1_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R2_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R3_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R4_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R5_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R6_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R7_DEFAULT 0x00003fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R8_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R9_DEFAULT 0x00000084
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R10_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R11_DEFAULT 0x0000b000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R12_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R13_DEFAULT 0x00008080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R14_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R15_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R16_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R17_DEFAULT 0x000030d1
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R18_DEFAULT 0x00007410
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R19_DEFAULT 0x00004dd7
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R20_DEFAULT 0x00000711
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R22_DEFAULT 0x000055d8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R23_DEFAULT 0x00002f11
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R24_DEFAULT 0x00007010
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R25_DEFAULT 0x0000611d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R26_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R27_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R29_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R30_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R31_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R0_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R1_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R3_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R4_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R6_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R9_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R12_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R13_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R14_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R15_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R16_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R17_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R18_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R19_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R20_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R21_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R22_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R23_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R24_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R25_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R26_DEFAULT 0x00005239
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R27_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R28_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R29_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R31_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R1_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R2_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R3_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R4_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R5_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R6_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R7_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R8_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R9_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R10_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R11_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R12_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R13_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R14_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R15_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R16_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R17_DEFAULT 0x0000524b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R18_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R19_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R20_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R21_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R24_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R25_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R26_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R28_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R29_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R31_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R0_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R1_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R2_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R3_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R4_DEFAULT 0x00005255
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R6_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R7_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R9_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R10_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R12_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R13_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R15_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R16_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R17_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R18_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R19_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R20_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R21_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R22_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R23_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R25_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R27_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R28_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R29_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R30_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R31_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R1_DEFAULT 0x00005261
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R3_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R4_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R5_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R6_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R9_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R12_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R13_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R14_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R16_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R18_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R19_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R20_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R21_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R24_DEFAULT 0x00005273
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R25_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R26_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R27_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R29_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R30_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R31_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R0_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R1_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R3_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R6_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R7_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R8_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R9_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R10_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R12_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R13_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R14_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R15_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R16_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R17_DEFAULT 0x0000527d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_CMN_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_DEFAULT 0x00005000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_DEFAULT 0x00005000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_IDCODE_LO_DEFAULT 0x000004cd
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_IDCODE_HI_DEFAULT 0x00003006
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN_DEFAULT 0x00000070
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0_DEFAULT 0x00000328
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_2_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0_DEFAULT 0x00000194
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1_DEFAULT 0x0000a000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_2_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN_DEFAULT 0x000001d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RX_TERM_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT 0x00000d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT 0x00005200
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT 0x0000894a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0_DEFAULT 0x00000025
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT 0x00000d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT 0x00005200
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT 0x0000894a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0_DEFAULT 0x00000025
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1_DEFAULT 0x00000066
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC_DEFAULT 0x00000028
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC_DEFAULT 0x00000028
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG_DEFAULT 0x0000000e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_CONFIG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_SET_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R0_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R1_DEFAULT 0x00001f4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R2_DEFAULT 0x0000297c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R3_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R4_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R5_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R6_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R7_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R9_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R10_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R11_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R12_DEFAULT 0x00000750
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R13_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R14_DEFAULT 0x00000212
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R15_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R16_DEFAULT 0x00004214
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R17_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R18_DEFAULT 0x00001f50
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R19_DEFAULT 0x0000297d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R20_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R21_DEFAULT 0x00000140
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R22_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R23_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R24_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R25_DEFAULT 0x00002800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R26_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R28_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R29_DEFAULT 0x00006800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R31_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R0_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R1_DEFAULT 0x00000745
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R2_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R3_DEFAULT 0x00000227
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R4_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R5_DEFAULT 0x00004227
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R6_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R7_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R8_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R9_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R10_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R11_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R13_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R14_DEFAULT 0x00000015
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R15_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R16_DEFAULT 0x00000746
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R17_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R18_DEFAULT 0x00000236
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R19_DEFAULT 0x00001f27
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R20_DEFAULT 0x00004236
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R21_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R22_DEFAULT 0x000001b3
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R23_DEFAULT 0x00000177
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R24_DEFAULT 0x000055dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R25_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R26_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R27_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R28_DEFAULT 0x00002800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R29_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R31_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R0_DEFAULT 0x00007000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R1_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R2_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R4_DEFAULT 0x00000173
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R5_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R6_DEFAULT 0x0000024a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R7_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R8_DEFAULT 0x0000424a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R9_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R10_DEFAULT 0x000055fb
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R12_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R13_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R14_DEFAULT 0x00000174
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R15_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R16_DEFAULT 0x00000254
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R17_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R18_DEFAULT 0x00004254
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R19_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R20_DEFAULT 0x00005612
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R21_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R22_DEFAULT 0x00006c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R23_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R24_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R25_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R26_DEFAULT 0x00000179
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R27_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R28_DEFAULT 0x00000260
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R29_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R30_DEFAULT 0x00004260
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R31_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R0_DEFAULT 0x00005625
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R1_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R2_DEFAULT 0x00005555
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R3_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R4_DEFAULT 0x00001400
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R5_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R7_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R8_DEFAULT 0x00007000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R9_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R10_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R11_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R12_DEFAULT 0x00000175
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R13_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R14_DEFAULT 0x00000272
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R15_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R16_DEFAULT 0x00004272
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R17_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R18_DEFAULT 0x00005642
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R19_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R20_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R22_DEFAULT 0x00000176
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R23_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R24_DEFAULT 0x0000027c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R25_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R26_DEFAULT 0x0000427c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R27_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R28_DEFAULT 0x00005659
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R29_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R30_DEFAULT 0x00006c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R31_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R0_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R2_DEFAULT 0x0000017a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R3_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R4_DEFAULT 0x00000288
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R5_DEFAULT 0x00001f26
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R6_DEFAULT 0x00004288
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R7_DEFAULT 0x00005306
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R8_DEFAULT 0x00001973
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R9_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R10_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R11_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R12_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R13_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R14_DEFAULT 0x00001974
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R15_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R16_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R17_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R18_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R19_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R20_DEFAULT 0x00001979
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R21_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R22_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R23_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R24_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R25_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R26_DEFAULT 0x00001975
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R27_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R29_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R0_DEFAULT 0x00001976
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R1_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R3_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R4_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R6_DEFAULT 0x0000197a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R9_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R12_DEFAULT 0x00001973
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R13_DEFAULT 0x00002f4b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R14_DEFAULT 0x00001974
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R15_DEFAULT 0x00002f4c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R16_DEFAULT 0x00001979
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R17_DEFAULT 0x00002f51
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R18_DEFAULT 0x00001975
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R19_DEFAULT 0x00002f4d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R20_DEFAULT 0x00001976
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R21_DEFAULT 0x00002f4e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R22_DEFAULT 0x0000197a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R23_DEFAULT 0x00002f52
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R24_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R25_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R26_DEFAULT 0x00001f4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R27_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R29_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R0_DEFAULT 0x00001f50
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R1_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R3_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R4_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R6_DEFAULT 0x00001f42
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R9_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R12_DEFAULT 0x00001f43
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R13_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R14_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R15_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R16_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R18_DEFAULT 0x00001f44
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R19_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R20_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R21_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R24_DEFAULT 0x00001f29
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R25_DEFAULT 0x000042f1
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R26_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R27_DEFAULT 0x0000a3a0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R28_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R29_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R30_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R0_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R2_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R4_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R5_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R6_DEFAULT 0x000001b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R8_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R10_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R12_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R13_DEFAULT 0x00000749
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R14_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R15_DEFAULT 0x000002f5
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R16_DEFAULT 0x00005329
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R17_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R18_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R19_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R20_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R21_DEFAULT 0x000001b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R23_DEFAULT 0x000019b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R24_DEFAULT 0x00002f53
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R25_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R27_DEFAULT 0x000001b3
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R28_DEFAULT 0x00000077
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R29_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R31_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R1_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R3_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R5_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R6_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R7_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R9_DEFAULT 0x00008660
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R10_DEFAULT 0x00004b15
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R11_DEFAULT 0x00008270
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R12_DEFAULT 0x00004b0e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R13_DEFAULT 0x0000530f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R14_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R15_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R16_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R18_DEFAULT 0x00004b1c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R19_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R20_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R21_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R22_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R24_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R25_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R26_DEFAULT 0x00004313
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R27_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R28_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R29_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R30_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R31_DEFAULT 0x0000301d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R0_DEFAULT 0x00004325
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R1_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R2_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R3_DEFAULT 0x00003054
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R4_DEFAULT 0x00005327
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R5_DEFAULT 0x00007445
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R6_DEFAULT 0x0000430e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R7_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R8_DEFAULT 0x00005309
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R9_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R10_DEFAULT 0x00008670
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R11_DEFAULT 0x00004b2d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R12_DEFAULT 0x0000532e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R13_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R14_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R15_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R16_DEFAULT 0x0000ffe8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R17_DEFAULT 0x0000701d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R18_DEFAULT 0x00004b35
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R19_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R20_DEFAULT 0x0000532d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R21_DEFAULT 0x0000741d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R22_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R23_DEFAULT 0x0000074a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R24_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R25_DEFAULT 0x000001b4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R26_DEFAULT 0x00003323
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R27_DEFAULT 0x000001b8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R29_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R30_DEFAULT 0x0000532a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R31_DEFAULT 0x00001f2a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R0_DEFAULT 0x00004377
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R1_DEFAULT 0x0000075e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R4_DEFAULT 0x000000fe
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R5_DEFAULT 0x00001f09
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R8_DEFAULT 0x0000080c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R9_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R10_DEFAULT 0x000070cd
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R11_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R12_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R13_DEFAULT 0x00002f05
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R14_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R15_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R16_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R17_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R19_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R20_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R21_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R22_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R23_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R24_DEFAULT 0x0000435a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R25_DEFAULT 0x00005357
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R26_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R27_DEFAULT 0x00000008
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R28_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R29_DEFAULT 0x0000435c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R30_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R31_DEFAULT 0x00000600
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R0_DEFAULT 0x00001f09
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R1_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R2_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R3_DEFAULT 0x0000608d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R4_DEFAULT 0x0000700d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R5_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R6_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R7_DEFAULT 0x00002f05
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R8_DEFAULT 0x0000080f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R9_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R10_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R11_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R12_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R13_DEFAULT 0x0000436f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R14_DEFAULT 0x0000536c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R15_DEFAULT 0x00000706
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R17_DEFAULT 0x00001f0f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R18_DEFAULT 0x00004371
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R19_DEFAULT 0x00000705
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R20_DEFAULT 0x0000000c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R21_DEFAULT 0x0000070e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R23_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R24_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R25_DEFAULT 0x00000147
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R27_DEFAULT 0x000001a8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R29_DEFAULT 0x00001f6b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R30_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R31_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R0_DEFAULT 0x00000200
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R1_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R2_DEFAULT 0x00000042
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R3_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R4_DEFAULT 0x0000007e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R5_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R7_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R9_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R10_DEFAULT 0x0000792b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R11_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R12_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R13_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R15_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R16_DEFAULT 0x00003636
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R17_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R18_DEFAULT 0x0000608c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R19_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R20_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R21_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R22_DEFAULT 0x0000702c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R23_DEFAULT 0x00002969
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R24_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R25_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R26_DEFAULT 0x00001f67
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R27_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R28_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R29_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R30_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R31_DEFAULT 0x00003c02
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R0_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R1_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R2_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R3_DEFAULT 0x00007060
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R4_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R5_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R6_DEFAULT 0x00001f2a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R7_DEFAULT 0x000043a9
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R8_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R9_DEFAULT 0x00001f68
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R10_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R11_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R12_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R13_DEFAULT 0x00001f6c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R14_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R15_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R16_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R17_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R18_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R19_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R20_DEFAULT 0x00004fa0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R22_DEFAULT 0x00007828
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R23_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R24_DEFAULT 0x000036dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R25_DEFAULT 0x00001f2b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R26_DEFAULT 0x000043bc
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R27_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R28_DEFAULT 0x00001f69
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R29_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R30_DEFAULT 0x00001f6d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R31_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R0_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R1_DEFAULT 0x00007818
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R2_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R3_DEFAULT 0x0000124a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R4_DEFAULT 0x00001f2b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R5_DEFAULT 0x000043c7
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R6_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R7_DEFAULT 0x00001f6a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R8_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R9_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R10_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R11_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R12_DEFAULT 0x00002806
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R13_DEFAULT 0x00001f6e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R14_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R15_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R16_DEFAULT 0x000000c6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R17_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R18_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R19_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R20_DEFAULT 0x00003000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R22_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R23_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R24_DEFAULT 0x0000b6b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R25_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R26_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R27_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R28_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R29_DEFAULT 0x00001f6a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R30_DEFAULT 0x00002980
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R31_DEFAULT 0x00001f6e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R0_DEFAULT 0x00002960
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R1_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R2_DEFAULT 0x00000084
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R3_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R4_DEFAULT 0x0000b000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R5_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R6_DEFAULT 0x00008080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R7_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R8_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R9_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R10_DEFAULT 0x000074d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R11_DEFAULT 0x00004bef
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R12_DEFAULT 0x00000711
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R14_DEFAULT 0x000053f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R15_DEFAULT 0x00002f11
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R16_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R17_DEFAULT 0x000003ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R18_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R20_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R21_DEFAULT 0x00003c46
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R22_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R24_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R25_DEFAULT 0x00007020
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R26_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R27_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R28_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R29_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R30_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R31_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R0_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R1_DEFAULT 0x00004408
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R2_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R3_DEFAULT 0x00000fe0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R4_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R5_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R6_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R7_DEFAULT 0x0000540d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R8_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R9_DEFAULT 0x00000fc0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R10_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R11_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R12_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R13_DEFAULT 0x000030c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R14_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R15_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R16_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R17_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R18_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R19_DEFAULT 0x000030c5
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R20_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R21_DEFAULT 0x00000036
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R22_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R23_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R24_DEFAULT 0x000030dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R25_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R27_DEFAULT 0x00007435
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R28_DEFAULT 0x00004c23
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R29_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R30_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R31_DEFAULT 0x00004c38
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R0_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R2_DEFAULT 0x00005438
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R4_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R5_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R8_DEFAULT 0x0000442c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R9_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R10_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R11_DEFAULT 0x0000542e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R12_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R13_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R14_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R15_DEFAULT 0x0000703d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R16_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R17_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R18_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R19_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R20_DEFAULT 0x00004c36
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R21_DEFAULT 0x00005438
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R22_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R23_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R24_DEFAULT 0x00006082
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R25_DEFAULT 0x00006182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R26_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R27_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R29_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R31_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R0_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R1_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R2_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R3_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R4_DEFAULT 0x000030dc
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R5_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R6_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R7_DEFAULT 0x00007435
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R8_DEFAULT 0x00004c4f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R9_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R10_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R11_DEFAULT 0x00004c64
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R12_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R14_DEFAULT 0x00005464
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R16_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R17_DEFAULT 0x00001963
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R18_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R20_DEFAULT 0x00004458
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R21_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R22_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R23_DEFAULT 0x0000545a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R24_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R25_DEFAULT 0x00000040
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R26_DEFAULT 0x0000744c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R27_DEFAULT 0x0000703d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R28_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R29_DEFAULT 0x00000803
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R30_DEFAULT 0x00000100
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R31_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R0_DEFAULT 0x00004c62
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R1_DEFAULT 0x00005464
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R2_DEFAULT 0x00000802
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R3_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R4_DEFAULT 0x00006082
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R5_DEFAULT 0x00006182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R6_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R7_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R9_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R12_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R14_DEFAULT 0x00008647
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R16_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R17_DEFAULT 0x00001989
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R18_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R19_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R20_DEFAULT 0x0000601d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R21_DEFAULT 0x000030d3
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R22_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R23_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R24_DEFAULT 0x00001986
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R25_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R26_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R27_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R28_DEFAULT 0x000030d4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R29_DEFAULT 0x0000613d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R30_DEFAULT 0x000030d1
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R31_DEFAULT 0x00003025
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R0_DEFAULT 0x00006115
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R1_DEFAULT 0x00007052
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R2_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R3_DEFAULT 0x00007021
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R4_DEFAULT 0x0000743d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R5_DEFAULT 0x00004c87
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R6_DEFAULT 0x0000548d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R7_DEFAULT 0x00007414
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R8_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R9_DEFAULT 0x00007052
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R10_DEFAULT 0x000074d3
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R11_DEFAULT 0x00004c93
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R12_DEFAULT 0x00005490
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R13_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R15_DEFAULT 0x00005495
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R16_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R17_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R18_DEFAULT 0x00005495
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R19_DEFAULT 0x00000712
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R22_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R23_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R24_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R25_DEFAULT 0x00000804
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R26_DEFAULT 0x00000014
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R27_DEFAULT 0x00000805
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R28_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R29_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R30_DEFAULT 0x000003e0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R31_DEFAULT 0x0000116d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R0_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R1_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R2_DEFAULT 0x000030c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R3_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R4_DEFAULT 0x00000fe0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R5_DEFAULT 0x0000116e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R6_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R7_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R8_DEFAULT 0x000030c3
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R9_DEFAULT 0x00007420
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R10_DEFAULT 0x00004cac
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R11_DEFAULT 0x000054c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R12_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R13_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R14_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R15_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R16_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R17_DEFAULT 0x000044b5
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R18_DEFAULT 0x00007434
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R19_DEFAULT 0x00004cb5
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R20_DEFAULT 0x000054c4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R21_DEFAULT 0x00007412
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R22_DEFAULT 0x00004cb8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R23_DEFAULT 0x000054c1
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R24_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R25_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R26_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R27_DEFAULT 0x0000080e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R28_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R29_DEFAULT 0x000044c1
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R30_DEFAULT 0x000054bf
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R31_DEFAULT 0x00007453
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R0_DEFAULT 0x00004cc7
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R1_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R2_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R3_DEFAULT 0x000054c9
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R4_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R5_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R6_DEFAULT 0x000054c9
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R7_DEFAULT 0x00000714
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R9_DEFAULT 0x0000196b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R10_DEFAULT 0x00002f5a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R11_DEFAULT 0x0000196d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R12_DEFAULT 0x00002f5c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R13_DEFAULT 0x0000196c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R14_DEFAULT 0x00002f5b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R15_DEFAULT 0x0000196e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R16_DEFAULT 0x00002f5d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R17_DEFAULT 0x0000196f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R18_DEFAULT 0x00002f60
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R19_DEFAULT 0x00001970
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R20_DEFAULT 0x00002f61
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R21_DEFAULT 0x00001971
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R22_DEFAULT 0x00002f62
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R23_DEFAULT 0x00001972
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R24_DEFAULT 0x00002f63
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R25_DEFAULT 0x00000147
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R27_DEFAULT 0x0000075e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R28_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R29_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R31_DEFAULT 0x00000710
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R1_DEFAULT 0x00001f86
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R2_DEFAULT 0x000044e4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R3_DEFAULT 0x000054e1
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R4_DEFAULT 0x00000710
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R6_DEFAULT 0x0000078c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R8_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R9_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R10_DEFAULT 0x00000029
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R11_DEFAULT 0x00001fe3
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R12_DEFAULT 0x000044f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R13_DEFAULT 0x00001fe4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R14_DEFAULT 0x000044f0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R15_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R16_DEFAULT 0x00009fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R17_DEFAULT 0x00001fe3
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R18_DEFAULT 0x000044f4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R19_DEFAULT 0x000054f7
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R20_DEFAULT 0x00000806
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R21_DEFAULT 0x000004f7
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R22_DEFAULT 0x00005500
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R23_DEFAULT 0x00001fe4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R24_DEFAULT 0x000044fa
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R25_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R26_DEFAULT 0x00000806
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R27_DEFAULT 0x000004fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R28_DEFAULT 0x00005571
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R29_DEFAULT 0x0000078d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R31_DEFAULT 0x00005027
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R0_DEFAULT 0x00001f59
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R1_DEFAULT 0x00004503
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R2_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R3_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R5_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R6_DEFAULT 0x00007fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R7_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R8_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R9_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R11_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R13_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R14_DEFAULT 0x00004000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R15_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R16_DEFAULT 0x0000247e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R17_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R18_DEFAULT 0x0000a080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R19_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R20_DEFAULT 0x00000002
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R21_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R22_DEFAULT 0x00000741
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R23_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R24_DEFAULT 0x0000051a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R25_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R26_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R27_DEFAULT 0x0000a0c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R29_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R30_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R31_DEFAULT 0x00000742
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R0_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R1_DEFAULT 0x00000523
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R2_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R3_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R4_DEFAULT 0x0000a200
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R6_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R7_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R8_DEFAULT 0x00000743
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R9_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R10_DEFAULT 0x0000052c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R11_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R12_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R13_DEFAULT 0x0000a220
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R14_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R15_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R16_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R17_DEFAULT 0x00000744
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R18_DEFAULT 0x00000807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R19_DEFAULT 0x00000535
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R20_DEFAULT 0x0000553c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R21_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R22_DEFAULT 0x00002000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R23_DEFAULT 0x000001ae
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R25_DEFAULT 0x000001ac
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R27_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R28_DEFAULT 0x0000320d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R29_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R30_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R31_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R0_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R1_DEFAULT 0x0000866c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R2_DEFAULT 0x00004d4b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R3_DEFAULT 0x0000827c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R4_DEFAULT 0x00004d46
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R5_DEFAULT 0x00005547
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R6_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R7_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R8_DEFAULT 0x00004d50
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R9_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R10_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R11_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R12_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R13_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R14_DEFAULT 0x00004549
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R15_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R16_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R17_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R18_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R19_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R20_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R21_DEFAULT 0x0000320d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R22_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R23_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R24_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R25_DEFAULT 0x00009080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R26_DEFAULT 0x000078a5
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R27_DEFAULT 0x0000744d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R28_DEFAULT 0x00004d5e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R29_DEFAULT 0x00005567
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R30_DEFAULT 0x000078a4
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R31_DEFAULT 0x0000745d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R0_DEFAULT 0x00004d62
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R1_DEFAULT 0x00005563
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R2_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R3_DEFAULT 0x00007e10
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R4_DEFAULT 0x00004d6c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R5_DEFAULT 0x000031c0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R6_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R7_DEFAULT 0x00007a10
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R8_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R9_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R10_DEFAULT 0x00004565
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R11_DEFAULT 0x0000302d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R12_DEFAULT 0x000029ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R13_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R15_DEFAULT 0x0000900d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R16_DEFAULT 0x00005807
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R17_DEFAULT 0x00001f5e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R18_DEFAULT 0x00004574
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R19_DEFAULT 0x000054fd
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R20_DEFAULT 0x00000801
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R21_DEFAULT 0x00003636
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R22_DEFAULT 0x00001752
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R23_DEFAULT 0x0000608c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R24_DEFAULT 0x0000701c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R25_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R26_DEFAULT 0x00001751
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R27_DEFAULT 0x0000702c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R28_DEFAULT 0x00002969
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R29_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R30_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R31_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R0_DEFAULT 0x0000ffff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R1_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R2_DEFAULT 0x00003c06
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R3_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R5_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R6_DEFAULT 0x00003060
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R7_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R8_DEFAULT 0x0000647e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R9_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R10_DEFAULT 0x00000004
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R11_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R12_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R13_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R14_DEFAULT 0x000000c2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R15_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R16_DEFAULT 0x00000f20
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R17_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R18_DEFAULT 0x000090a0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R19_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R20_DEFAULT 0x00000999
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R21_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R22_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R23_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R24_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R25_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R27_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R28_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R29_DEFAULT 0x00008c00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R30_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R31_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R0_DEFAULT 0x00000181
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R1_DEFAULT 0x0000aaaa
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R2_DEFAULT 0x00000182
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R3_DEFAULT 0x00002806
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R4_DEFAULT 0x00000183
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R6_DEFAULT 0x00000184
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R7_DEFAULT 0x00003060
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R8_DEFAULT 0x00000185
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R9_DEFAULT 0x0000647e
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R10_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R11_DEFAULT 0x00003fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R12_DEFAULT 0x00000161
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R13_DEFAULT 0x00000209
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R14_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R15_DEFAULT 0x000000c6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R16_DEFAULT 0x00000163
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R17_DEFAULT 0x00001000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R18_DEFAULT 0x00000164
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R20_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R21_DEFAULT 0x00003000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R22_DEFAULT 0x00000166
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R23_DEFAULT 0x00007800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R24_DEFAULT 0x00000167
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R25_DEFAULT 0x00004342
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R26_DEFAULT 0x00000168
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R28_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R29_DEFAULT 0x0000b6b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R30_DEFAULT 0x0000016a
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R31_DEFAULT 0x0000001f
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R0_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R1_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R2_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R3_DEFAULT 0x000030d0
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R4_DEFAULT 0x00000180
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R5_DEFAULT 0x00007d00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R6_DEFAULT 0x00000160
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R7_DEFAULT 0x00003fff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R8_DEFAULT 0x00000162
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R9_DEFAULT 0x00000084
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R10_DEFAULT 0x00000165
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R11_DEFAULT 0x0000b000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R12_DEFAULT 0x00000169
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R13_DEFAULT 0x00008080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R14_DEFAULT 0x00008e00
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R15_DEFAULT 0x0000197b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R16_DEFAULT 0x0000618d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R17_DEFAULT 0x000030d1
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R18_DEFAULT 0x00007410
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R19_DEFAULT 0x00004dd7
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R20_DEFAULT 0x00000711
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R22_DEFAULT 0x000055d8
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R23_DEFAULT 0x00002f11
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R24_DEFAULT 0x00007010
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R25_DEFAULT 0x0000611d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R26_DEFAULT 0x000030d2
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R27_DEFAULT 0x00005806
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R28_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R29_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R30_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R31_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R0_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R1_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R3_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R4_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R6_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R9_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R12_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R13_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R14_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R15_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R16_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R17_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R18_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R19_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R20_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R21_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R22_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R23_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R24_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R25_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R26_DEFAULT 0x00005239
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R27_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R28_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R29_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R31_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R1_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R2_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R3_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R4_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R5_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R6_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R7_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R8_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R9_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R10_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R11_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R12_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R13_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R14_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R15_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R16_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R17_DEFAULT 0x0000524b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R18_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R19_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R20_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R21_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R24_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R25_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R26_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R28_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R29_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R30_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R31_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R0_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R1_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R2_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R3_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R4_DEFAULT 0x00005255
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R6_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R7_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R9_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R10_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R12_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R13_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R14_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R15_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R16_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R17_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R18_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R19_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R20_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R21_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R22_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R23_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R25_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R26_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R27_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R28_DEFAULT 0x00000016
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R29_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R30_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R31_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R0_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R1_DEFAULT 0x00005261
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R2_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R3_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R4_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R5_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R6_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R7_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R8_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R9_DEFAULT 0x00000011
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R10_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R11_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R12_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R13_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R14_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R16_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R17_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R18_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R19_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R20_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R21_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R22_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R23_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R24_DEFAULT 0x00005273
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R25_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R26_DEFAULT 0x00000010
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R27_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R29_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R30_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R31_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R0_DEFAULT 0x00000012
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R1_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R3_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R4_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R5_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R6_DEFAULT 0x00000013
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R7_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R8_DEFAULT 0x000000ff
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R9_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R10_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R11_DEFAULT 0x000001af
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R12_DEFAULT 0x00000018
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R13_DEFAULT 0x000001ad
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R14_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R15_DEFAULT 0x000001b6
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R16_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R17_DEFAULT 0x0000527d
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R8_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R9_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R10_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R11_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R12_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R13_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R14_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R15_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R16_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R17_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R18_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R19_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R20_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R21_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R22_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R23_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R24_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R25_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R26_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R27_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R28_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R29_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R30_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R31_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_CMN_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN_DEFAULT 0x00005000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN_DEFAULT 0x00000043
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN_DEFAULT 0x00005000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
+#define smnDWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_lcu_kpfifo_kpfifo3_kpfifo_dir
+#define smnKPFIFO3_PRI_TX_FIFO_HSCID_DEFAULT 0x00000000
+#define smnKPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0_DEFAULT 0x00000000
+#define smnKPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1_DEFAULT 0x00000000
+#define smnKPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2_DEFAULT 0x00000000
+#define smnKPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3_DEFAULT 0x00000000
+#define smnKPFIFO3_PCS_PMA_SOFT_RESET_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_lcu_kpnp_kpnp3_kpnp_dir
+#define smnKPNP_SNPS3_KPNP_HWSCVER_DEFAULT 0x00000000
+#define smnKPNP_SNPS3_KPNP_PHY_INFO_DEFAULT 0x00000000
+#define smnKPNP_SNPS3_KPNP_LANE_ID_DEFAULT 0x00000000
+#define smnKPNP_SNPS3_KPNP_LANE_REQ_CONTROL_DEFAULT 0x00000000
+#define smnKPNP_SNPS3_KPNP_LANE_REQ_STATUS_DEFAULT 0x00000000
+#define smnKPNP_SNPS3_KPNP_PMA_CONTROL0_DEFAULT 0x00000000
+#define smnKPNP_SNPS3_KPNP_PMA_CONTROL1_DEFAULT 0x000000b1
+#define smnKPNP_SNPS3_KPNP_PMA_CONTROL2_DEFAULT 0x00000004
+#define smnKPNP_SNPS3_KPNP_PHY_SOFT_RESET_DEFAULT 0x00000000
+#define smnKPNP_SNPS3_KPNP_LANE_SOFT_RESET_DEFAULT 0x000000ff
+#define smnKPNP_SNPS3_REG_RST_CTRL_DEFAULT 0x00000001
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf0_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf1_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf2_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf3_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf4_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf5_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf6_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf7_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf8_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf9_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf10_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf11_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf12_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf13_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf14_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf15_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: syshub_mmreg_ind_syshubind
+#define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100
+#define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
+#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
+#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000
+#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000
+#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL_DEFAULT 0x20200000
+#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL_DEFAULT 0x20200000
+#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL_DEFAULT 0x20200000
+#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL_DEFAULT 0x20200000
+#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL_DEFAULT 0x20200000
+#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL_DEFAULT 0x20200000
+#define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_SYSHUB_CG_CNTL_DEFAULT 0x00082000
+#define ixSYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_SYSHUB_HP_TIMER_DEFAULT 0x00000100
+#define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK_DEFAULT 0x00000080
+#define ixSYSHUB_MMREG_IND_SYSHUB_SCRATCH_DEFAULT 0x00000040
+#define ixSYSHUB_MMREG_IND_SYSHUB_CL_MASK_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100
+#define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL_DEFAULT 0x20200000
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL_DEFAULT 0x20200000
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL_DEFAULT 0x20200000
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL_DEFAULT 0x20200000
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL_DEFAULT 0x20200000
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL_DEFAULT 0x20200000
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL_DEFAULT 0x20200000
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL_DEFAULT 0x20200000
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL_DEFAULT 0x20200000
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL_DEFAULT 0x20200000
+#define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK_DEFAULT 0x00000080
+#define ixSYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_2_FN_MOD_BM_ISS_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_3_FN_MOD_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_4_FN_MOD_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD_DEFAULT 0x00000000
+#define ixSYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_offset.h
new file mode 100644
index 000000000000..13d4de645190
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_offset.h
@@ -0,0 +1,3649 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _nbio_6_1_OFFSET_HEADER
+#define _nbio_6_1_OFFSET_HEADER
+
+
+
+// addressBlock: nbio_pcie_pswuscfg0_cfgdecp
+// base address: 0x0
+#define cfgPSWUSCFG0_VENDOR_ID 0x0000
+#define cfgPSWUSCFG0_DEVICE_ID 0x0002
+#define cfgPSWUSCFG0_COMMAND 0x0004
+#define cfgPSWUSCFG0_STATUS 0x0006
+#define cfgPSWUSCFG0_REVISION_ID 0x0008
+#define cfgPSWUSCFG0_PROG_INTERFACE 0x0009
+#define cfgPSWUSCFG0_SUB_CLASS 0x000a
+#define cfgPSWUSCFG0_BASE_CLASS 0x000b
+#define cfgPSWUSCFG0_CACHE_LINE 0x000c
+#define cfgPSWUSCFG0_LATENCY 0x000d
+#define cfgPSWUSCFG0_HEADER 0x000e
+#define cfgPSWUSCFG0_BIST 0x000f
+#define cfgPSWUSCFG0_SUB_BUS_NUMBER_LATENCY 0x0018
+#define cfgPSWUSCFG0_IO_BASE_LIMIT 0x001c
+#define cfgPSWUSCFG0_SECONDARY_STATUS 0x001e
+#define cfgPSWUSCFG0_MEM_BASE_LIMIT 0x0020
+#define cfgPSWUSCFG0_PREF_BASE_LIMIT 0x0024
+#define cfgPSWUSCFG0_PREF_BASE_UPPER 0x0028
+#define cfgPSWUSCFG0_PREF_LIMIT_UPPER 0x002c
+#define cfgPSWUSCFG0_IO_BASE_LIMIT_HI 0x0030
+#define cfgPSWUSCFG0_CAP_PTR 0x0034
+#define cfgPSWUSCFG0_INTERRUPT_LINE 0x003c
+#define cfgPSWUSCFG0_INTERRUPT_PIN 0x003d
+#define cfgPSWUSCFG0_IRQ_BRIDGE_CNTL 0x003e
+#define cfgEXT_BRIDGE_CNTL 0x0040
+#define cfgPSWUSCFG0_VENDOR_CAP_LIST 0x0048
+#define cfgPSWUSCFG0_ADAPTER_ID_W 0x004c
+#define cfgPSWUSCFG0_PMI_CAP_LIST 0x0050
+#define cfgPSWUSCFG0_PMI_CAP 0x0052
+#define cfgPSWUSCFG0_PMI_STATUS_CNTL 0x0054
+#define cfgPSWUSCFG0_PCIE_CAP_LIST 0x0058
+#define cfgPSWUSCFG0_PCIE_CAP 0x005a
+#define cfgPSWUSCFG0_DEVICE_CAP 0x005c
+#define cfgPSWUSCFG0_DEVICE_CNTL 0x0060
+#define cfgPSWUSCFG0_DEVICE_STATUS 0x0062
+#define cfgPSWUSCFG0_LINK_CAP 0x0064
+#define cfgPSWUSCFG0_LINK_CNTL 0x0068
+#define cfgPSWUSCFG0_LINK_STATUS 0x006a
+#define cfgPSWUSCFG0_DEVICE_CAP2 0x007c
+#define cfgPSWUSCFG0_DEVICE_CNTL2 0x0080
+#define cfgPSWUSCFG0_DEVICE_STATUS2 0x0082
+#define cfgPSWUSCFG0_LINK_CAP2 0x0084
+#define cfgPSWUSCFG0_LINK_CNTL2 0x0088
+#define cfgPSWUSCFG0_LINK_STATUS2 0x008a
+#define cfgPSWUSCFG0_MSI_CAP_LIST 0x00a0
+#define cfgPSWUSCFG0_MSI_MSG_CNTL 0x00a2
+#define cfgPSWUSCFG0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgPSWUSCFG0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgPSWUSCFG0_MSI_MSG_DATA 0x00a8
+#define cfgPSWUSCFG0_MSI_MSG_DATA_64 0x00ac
+#define cfgPSWUSCFG0_SSID_CAP_LIST 0x00c0
+#define cfgPSWUSCFG0_SSID_CAP 0x00c4
+#define cfgMSI_MAP_CAP_LIST 0x00c8
+#define cfgMSI_MAP_CAP 0x00ca
+#define cfgMSI_MAP_ADDR_LO 0x00cc
+#define cfgMSI_MAP_ADDR_HI 0x00d0
+#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgPSWUSCFG0_PCIE_VC_ENH_CAP_LIST 0x0110
+#define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG1 0x0114
+#define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG2 0x0118
+#define cfgPSWUSCFG0_PCIE_PORT_VC_CNTL 0x011c
+#define cfgPSWUSCFG0_PCIE_PORT_VC_STATUS 0x011e
+#define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CAP 0x0120
+#define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CNTL 0x0124
+#define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_STATUS 0x012a
+#define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CAP 0x012c
+#define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CNTL 0x0130
+#define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_STATUS 0x0136
+#define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140
+#define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1 0x0144
+#define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2 0x0148
+#define cfgPSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgPSWUSCFG0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgPSWUSCFG0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgPSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgPSWUSCFG0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgPSWUSCFG0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgPSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgPSWUSCFG0_PCIE_HDR_LOG0 0x016c
+#define cfgPSWUSCFG0_PCIE_HDR_LOG1 0x0170
+#define cfgPSWUSCFG0_PCIE_HDR_LOG2 0x0174
+#define cfgPSWUSCFG0_PCIE_HDR_LOG3 0x0178
+#define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgPSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270
+#define cfgPSWUSCFG0_PCIE_LINK_CNTL3 0x0274
+#define cfgPSWUSCFG0_PCIE_LANE_ERROR_STATUS 0x0278
+#define cfgPSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c
+#define cfgPSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e
+#define cfgPSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280
+#define cfgPSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282
+#define cfgPSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284
+#define cfgPSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286
+#define cfgPSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288
+#define cfgPSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a
+#define cfgPSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c
+#define cfgPSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e
+#define cfgPSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290
+#define cfgPSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292
+#define cfgPSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294
+#define cfgPSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296
+#define cfgPSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298
+#define cfgPSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a
+#define cfgPSWUSCFG0_PCIE_ACS_ENH_CAP_LIST 0x02a0
+#define cfgPSWUSCFG0_PCIE_ACS_CAP 0x02a4
+#define cfgPSWUSCFG0_PCIE_ACS_CNTL 0x02a6
+#define cfgPSWUSCFG0_PCIE_MC_ENH_CAP_LIST 0x02f0
+#define cfgPSWUSCFG0_PCIE_MC_CAP 0x02f4
+#define cfgPSWUSCFG0_PCIE_MC_CNTL 0x02f6
+#define cfgPSWUSCFG0_PCIE_MC_ADDR0 0x02f8
+#define cfgPSWUSCFG0_PCIE_MC_ADDR1 0x02fc
+#define cfgPSWUSCFG0_PCIE_MC_RCV0 0x0300
+#define cfgPSWUSCFG0_PCIE_MC_RCV1 0x0304
+#define cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL0 0x0308
+#define cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL1 0x030c
+#define cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310
+#define cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314
+#define cfgPCIE_MC_OVERLAY_BAR0 0x0318
+#define cfgPCIE_MC_OVERLAY_BAR1 0x031c
+#define cfgPSWUSCFG0_PCIE_LTR_ENH_CAP_LIST 0x0320
+#define cfgPSWUSCFG0_PCIE_LTR_CAP 0x0324
+#define cfgPSWUSCFG0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgPSWUSCFG0_PCIE_ARI_CAP 0x032c
+#define cfgPSWUSCFG0_PCIE_ARI_CNTL 0x032e
+#define cfgPCIE_L1_PM_SUB_CAP_LIST 0x0370
+#define cfgPCIE_L1_PM_SUB_CAP 0x0374
+#define cfgPCIE_L1_PM_SUB_CNTL 0x0378
+#define cfgPCIE_L1_PM_SUB_CNTL2 0x037c
+#define cfgPCIE_ESM_CAP_LIST 0x03c4
+#define cfgPCIE_ESM_HEADER_1 0x03c8
+#define cfgPCIE_ESM_HEADER_2 0x03cc
+#define cfgPCIE_ESM_STATUS 0x03ce
+#define cfgPCIE_ESM_CTRL 0x03d0
+#define cfgPCIE_ESM_CAP_1 0x03d4
+#define cfgPCIE_ESM_CAP_2 0x03d8
+#define cfgPCIE_ESM_CAP_3 0x03dc
+#define cfgPCIE_ESM_CAP_4 0x03e0
+#define cfgPCIE_ESM_CAP_5 0x03e4
+#define cfgPCIE_ESM_CAP_6 0x03e8
+#define cfgPCIE_ESM_CAP_7 0x03ec
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0x0048
+#define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0x004c
+#define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0x0050
+#define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP 0x0052
+#define cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0x0054
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_0_SLOT_CAP2 0x0098
+#define cfgBIF_CFG_DEV0_EPF0_0_SLOT_CNTL2 0x009c
+#define cfgBIF_CFG_DEV0_EPF0_0_SLOT_STATUS2 0x009e
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x0110
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x0114
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x0118
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0x011c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0x011e
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x0120
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x0124
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x012a
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x012c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x0130
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x0136
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x0200
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0x0204
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0x0208
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0x020c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0x0210
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0x0214
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0x0218
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0x021c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0x0220
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0x0224
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0x0228
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0x022c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0x0230
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0x0248
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0x024c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x0250
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0x0254
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x0258
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0x025c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0x025e
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0x0274
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0x0278
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x02a0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0x02a4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0x02a6
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL 0x02c4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS 0x02c6
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0x02d0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0x02d4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0x02d6
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x02e0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP 0x02e4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL 0x02e8
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST 0x02f0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP 0x02f4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL 0x02f6
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 0x02f8
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 0x02fc
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 0x0300
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 0x0304
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 0x0308
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 0x030c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x0320
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0x0324
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0x032e
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0x0334
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0x0338
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0x033a
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0x033c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0x033e
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0x0340
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0x0346
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x0490
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x04a0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x04a4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x04a8
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x04ac
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04b0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04b4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04b8
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04bc
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x04c0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04d0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04d4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04d8
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04dc
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04e0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04e4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04e8
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04ec
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x04f0
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf1_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF1_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF1_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF1_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF1_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF1_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0x0048
+#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0x004c
+#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0x0050
+#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP 0x0052
+#define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0x0054
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CAP2 0x0098
+#define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CNTL2 0x009c
+#define cfgBIF_CFG_DEV0_EPF1_0_SLOT_STATUS2 0x009e
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST 0x0110
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1 0x0114
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2 0x0118
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL 0x011c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS 0x011e
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP 0x0120
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL 0x0124
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS 0x012a
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP 0x012c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL 0x0130
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS 0x0136
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x0200
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0x0204
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0x0208
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0x020c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0x0210
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0x0214
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0x0218
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0x021c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0x0220
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0x0224
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0x0228
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0x022c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0x0230
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0x0248
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0x024c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x0250
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0x0254
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x0258
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0x025c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0x025e
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 0x0274
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS 0x0278
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x02a0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0x02a4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0x02a6
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL 0x02c4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS 0x02c6
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0x02d0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0x02d4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0x02d6
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x02e0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP 0x02e4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL 0x02e8
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST 0x02f0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP 0x02f4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL 0x02f6
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 0x02f8
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 0x02fc
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 0x0300
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 0x0304
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 0x0308
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 0x030c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST 0x0320
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP 0x0324
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0x032e
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP 0x0334
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL 0x0338
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS 0x033a
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS 0x033c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS 0x033e
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS 0x0340
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE 0x0346
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x0490
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x04a0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x04a4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x04a8
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x04ac
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04b0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04b4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04b8
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04bc
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x04c0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04d0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04d4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04d8
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04dc
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04e0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04e4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04e8
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04ec
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x04f0
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_swds_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_SWDS0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_SWDS0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_SWDS0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_SWDS0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_SWDS0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_SWDS0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_SWDS0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_SWDS0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_SWDS0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_SWDS0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_SWDS0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY 0x0018
+#define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT 0x001c
+#define cfgBIF_CFG_DEV0_SWDS0_SECONDARY_STATUS 0x001e
+#define cfgBIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT 0x0020
+#define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT 0x0024
+#define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER 0x0028
+#define cfgBIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER 0x002c
+#define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI 0x0030
+#define cfgBIF_CFG_DEV0_SWDS0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL 0x003e
+#define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_LIST 0x0050
+#define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP 0x0052
+#define cfgBIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL 0x0054
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST 0x0058
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP 0x005a
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP 0x005c
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL 0x0060
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS 0x0062
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP 0x0064
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL 0x0068
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS 0x006a
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP 0x006c
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL 0x0070
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS 0x0072
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP2 0x007c
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL2 0x0080
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS2 0x0082
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP2 0x0084
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL2 0x0088
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS2 0x008a
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP2 0x008c
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL2 0x0090
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS2 0x0092
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP 0x00c4
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST 0x0110
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1 0x0114
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2 0x0118
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL 0x011c
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS 0x011e
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP 0x0120
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL 0x0124
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS 0x012a
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP 0x012c
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL 0x0130
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS 0x0136
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1 0x0144
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2 0x0148
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3 0x0274
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS 0x0278
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST 0x02a0
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP 0x02a4
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL 0x02a6
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf0_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CAP2 0x0098
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CNTL2 0x009c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_STATUS2 0x009e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf1_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CAP2 0x0098
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CNTL2 0x009c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_STATUS2 0x009e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf2_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CAP2 0x0098
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CNTL2 0x009c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_STATUS2 0x009e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf3_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CAP2 0x0098
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CNTL2 0x009c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_STATUS2 0x009e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf4_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CAP2 0x0098
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CNTL2 0x009c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_STATUS2 0x009e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf5_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CAP2 0x0098
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CNTL2 0x009c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_STATUS2 0x009e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf6_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CAP2 0x0098
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CNTL2 0x009c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_STATUS2 0x009e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf7_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CAP2 0x0098
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CNTL2 0x009c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_STATUS2 0x009e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf8_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CAP2 0x0098
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CNTL2 0x009c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_STATUS2 0x009e
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf9_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CAP2 0x0098
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CNTL2 0x009c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_STATUS2 0x009e
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf10_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CAP2 0x0098
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CNTL2 0x009c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_STATUS2 0x009e
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf11_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CAP2 0x0098
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CNTL2 0x009c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_STATUS2 0x009e
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf12_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CAP2 0x0098
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CNTL2 0x009c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_STATUS2 0x009e
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf13_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CAP2 0x0098
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CNTL2 0x009c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_STATUS2 0x009e
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf14_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CAP2 0x0098
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CNTL2 0x009c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_STATUS2 0x009e
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf15_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CAP2 0x0098
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CNTL2 0x009c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_STATUS2 0x009e
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_SYSPFVFDEC[0..767]
+// base address: 0x0
+#define mmMM_INDEX 0x0000
+#define mmMM_INDEX_BASE_IDX 0
+#define mmMM_DATA 0x0001
+#define mmMM_DATA_BASE_IDX 0
+#define mmMM_INDEX_HI 0x0006
+#define mmMM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_SYSDEC[0..767]
+// base address: 0x0
+#define mmSYSHUB_INDEX_OVLP 0x0008
+#define mmSYSHUB_INDEX_OVLP_BASE_IDX 0
+#define mmSYSHUB_DATA_OVLP 0x0009
+#define mmSYSHUB_DATA_OVLP_BASE_IDX 0
+#define mmPCIE_INDEX 0x000c
+#define mmPCIE_INDEX_BASE_IDX 0
+#define mmPCIE_DATA 0x000d
+#define mmPCIE_DATA_BASE_IDX 0
+#define mmPCIE_INDEX2 0x000e
+#define mmPCIE_INDEX2_BASE_IDX 0
+#define mmPCIE_DATA2 0x000f
+#define mmPCIE_DATA2_BASE_IDX 0
+#define mmSBIOS_SCRATCH_0 0x0034
+#define mmSBIOS_SCRATCH_0_BASE_IDX 1
+#define mmSBIOS_SCRATCH_1 0x0035
+#define mmSBIOS_SCRATCH_1_BASE_IDX 1
+#define mmSBIOS_SCRATCH_2 0x0036
+#define mmSBIOS_SCRATCH_2_BASE_IDX 1
+#define mmSBIOS_SCRATCH_3 0x0037
+#define mmSBIOS_SCRATCH_3_BASE_IDX 1
+#define mmBIOS_SCRATCH_0 0x0038
+#define mmBIOS_SCRATCH_0_BASE_IDX 1
+#define mmBIOS_SCRATCH_1 0x0039
+#define mmBIOS_SCRATCH_1_BASE_IDX 1
+#define mmBIOS_SCRATCH_2 0x003a
+#define mmBIOS_SCRATCH_2_BASE_IDX 1
+#define mmBIOS_SCRATCH_3 0x003b
+#define mmBIOS_SCRATCH_3_BASE_IDX 1
+#define mmBIOS_SCRATCH_4 0x003c
+#define mmBIOS_SCRATCH_4_BASE_IDX 1
+#define mmBIOS_SCRATCH_5 0x003d
+#define mmBIOS_SCRATCH_5_BASE_IDX 1
+#define mmBIOS_SCRATCH_6 0x003e
+#define mmBIOS_SCRATCH_6_BASE_IDX 1
+#define mmBIOS_SCRATCH_7 0x003f
+#define mmBIOS_SCRATCH_7_BASE_IDX 1
+#define mmBIOS_SCRATCH_8 0x0040
+#define mmBIOS_SCRATCH_8_BASE_IDX 1
+#define mmBIOS_SCRATCH_9 0x0041
+#define mmBIOS_SCRATCH_9_BASE_IDX 1
+#define mmBIOS_SCRATCH_10 0x0042
+#define mmBIOS_SCRATCH_10_BASE_IDX 1
+#define mmBIOS_SCRATCH_11 0x0043
+#define mmBIOS_SCRATCH_11_BASE_IDX 1
+#define mmBIOS_SCRATCH_12 0x0044
+#define mmBIOS_SCRATCH_12_BASE_IDX 1
+#define mmBIOS_SCRATCH_13 0x0045
+#define mmBIOS_SCRATCH_13_BASE_IDX 1
+#define mmBIOS_SCRATCH_14 0x0046
+#define mmBIOS_SCRATCH_14_BASE_IDX 1
+#define mmBIOS_SCRATCH_15 0x0047
+#define mmBIOS_SCRATCH_15_BASE_IDX 1
+#define mmBIF_RLC_INTR_CNTL 0x004c
+#define mmBIF_RLC_INTR_CNTL_BASE_IDX 1
+#define mmBIF_VCE_INTR_CNTL 0x004d
+#define mmBIF_VCE_INTR_CNTL_BASE_IDX 1
+#define mmBIF_UVD_INTR_CNTL 0x004e
+#define mmBIF_UVD_INTR_CNTL_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_ADDR0 0x006c
+#define mmGFX_MMIOREG_CAM_ADDR0_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR0 0x006d
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_ADDR1 0x006e
+#define mmGFX_MMIOREG_CAM_ADDR1_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR1 0x006f
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_ADDR2 0x0070
+#define mmGFX_MMIOREG_CAM_ADDR2_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR2 0x0071
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_ADDR3 0x0072
+#define mmGFX_MMIOREG_CAM_ADDR3_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR3 0x0073
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_ADDR4 0x0074
+#define mmGFX_MMIOREG_CAM_ADDR4_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR4 0x0075
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_ADDR5 0x0076
+#define mmGFX_MMIOREG_CAM_ADDR5_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR5 0x0077
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_ADDR6 0x0078
+#define mmGFX_MMIOREG_CAM_ADDR6_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR6 0x0079
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_ADDR7 0x007a
+#define mmGFX_MMIOREG_CAM_ADDR7_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR7 0x007b
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_CNTL 0x007c
+#define mmGFX_MMIOREG_CAM_CNTL_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_ZERO_CPL 0x007d
+#define mmGFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_ONE_CPL 0x007e
+#define mmGFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f
+#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1
+
+
+// addressBlock: nbio_nbif_syshub_mmreg_ind_syshubdec[32..39]
+// base address: 0x20
+#define mmSYSHUB_INDEX 0x0008
+#define mmSYSHUB_INDEX_BASE_IDX 0
+#define mmSYSHUB_DATA 0x0009
+#define mmSYSHUB_DATA_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif_rcc_strap_BIFDEC1[13440..14975]
+// base address: 0x3480
+#define mmRCC_DEV0_EPF0_STRAP0 0x000f
+#define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_rcc_ep_dev0_BIFDEC1[13440..14975]
+// base address: 0x3480
+#define mmEP_PCIE_SCRATCH 0x0023
+#define mmEP_PCIE_SCRATCH_BASE_IDX 2
+#define mmEP_PCIE_CNTL 0x0025
+#define mmEP_PCIE_CNTL_BASE_IDX 2
+#define mmEP_PCIE_INT_CNTL 0x0026
+#define mmEP_PCIE_INT_CNTL_BASE_IDX 2
+#define mmEP_PCIE_INT_STATUS 0x0027
+#define mmEP_PCIE_INT_STATUS_BASE_IDX 2
+#define mmEP_PCIE_RX_CNTL2 0x0028
+#define mmEP_PCIE_RX_CNTL2_BASE_IDX 2
+#define mmEP_PCIE_BUS_CNTL 0x0029
+#define mmEP_PCIE_BUS_CNTL_BASE_IDX 2
+#define mmEP_PCIE_CFG_CNTL 0x002a
+#define mmEP_PCIE_CFG_CNTL_BASE_IDX 2
+#define mmEP_PCIE_TX_LTR_CNTL 0x002c
+#define mmEP_PCIE_TX_LTR_CNTL_BASE_IDX 2
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x002d
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x002d
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x002d
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x002d
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x002e
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x002e
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x002e
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x002e
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2
+#define mmEP_PCIE_F0_DPA_CAP 0x0032
+#define mmEP_PCIE_F0_DPA_CAP_BASE_IDX 2
+#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0033
+#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2
+#define mmEP_PCIE_F0_DPA_CNTL 0x0033
+#define mmEP_PCIE_F0_DPA_CNTL_BASE_IDX 2
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0033
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0034
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0034
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0034
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0034
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0035
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0035
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0035
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2
+#define mmEP_PCIE_PME_CONTROL 0x0035
+#define mmEP_PCIE_PME_CONTROL_BASE_IDX 2
+#define mmEP_PCIEP_RESERVED 0x0036
+#define mmEP_PCIEP_RESERVED_BASE_IDX 2
+#define mmEP_PCIE_TX_CNTL 0x0038
+#define mmEP_PCIE_TX_CNTL_BASE_IDX 2
+#define mmEP_PCIE_TX_REQUESTER_ID 0x0039
+#define mmEP_PCIE_TX_REQUESTER_ID_BASE_IDX 2
+#define mmEP_PCIE_ERR_CNTL 0x003a
+#define mmEP_PCIE_ERR_CNTL_BASE_IDX 2
+#define mmEP_PCIE_RX_CNTL 0x003b
+#define mmEP_PCIE_RX_CNTL_BASE_IDX 2
+#define mmEP_PCIE_LC_SPEED_CNTL 0x003c
+#define mmEP_PCIE_LC_SPEED_CNTL_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_rcc_dwn_dev0_BIFDEC1[13440..14975]
+// base address: 0x3480
+#define mmDN_PCIE_RESERVED 0x0040
+#define mmDN_PCIE_RESERVED_BASE_IDX 2
+#define mmDN_PCIE_SCRATCH 0x0041
+#define mmDN_PCIE_SCRATCH_BASE_IDX 2
+#define mmDN_PCIE_CNTL 0x0043
+#define mmDN_PCIE_CNTL_BASE_IDX 2
+#define mmDN_PCIE_CONFIG_CNTL 0x0044
+#define mmDN_PCIE_CONFIG_CNTL_BASE_IDX 2
+#define mmDN_PCIE_RX_CNTL2 0x0045
+#define mmDN_PCIE_RX_CNTL2_BASE_IDX 2
+#define mmDN_PCIE_BUS_CNTL 0x0046
+#define mmDN_PCIE_BUS_CNTL_BASE_IDX 2
+#define mmDN_PCIE_CFG_CNTL 0x0047
+#define mmDN_PCIE_CFG_CNTL_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_rcc_dwnp_dev0_BIFDEC1[13440..14975]
+// base address: 0x3480
+#define mmPCIE_ERR_CNTL 0x004f
+#define mmPCIE_ERR_CNTL_BASE_IDX 2
+#define mmPCIE_RX_CNTL 0x0050
+#define mmPCIE_RX_CNTL_BASE_IDX 2
+#define mmPCIE_LC_SPEED_CNTL 0x0051
+#define mmPCIE_LC_SPEED_CNTL_BASE_IDX 2
+#define mmPCIE_LC_CNTL2 0x0052
+#define mmPCIE_LC_CNTL2_BASE_IDX 2
+#define mmPCIEP_STRAP_MISC 0x0053
+#define mmPCIEP_STRAP_MISC_BASE_IDX 2
+#define mmLTR_MSG_INFO_FROM_EP 0x0054
+#define mmLTR_MSG_INFO_FROM_EP_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_rcc_pf_0_BIFPFVFDEC1[13440..14975]
+// base address: 0x3480
+#define mmRCC_PF_0_0_RCC_ERR_LOG 0x0085
+#define mmRCC_PF_0_0_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_PF_0_0_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_PF_0_0_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_PF_0_0_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_PF_0_0_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_rcc_pf_0_BIFDEC1[13440..14975]
+// base address: 0x3480
+#define mmRCC_ERR_INT_CNTL 0x0086
+#define mmRCC_ERR_INT_CNTL_BASE_IDX 2
+#define mmRCC_BACO_CNTL_MISC 0x0087
+#define mmRCC_BACO_CNTL_MISC_BASE_IDX 2
+#define mmRCC_RESET_EN 0x0088
+#define mmRCC_RESET_EN_BASE_IDX 2
+#define mmRCC_VDM_SUPPORT 0x0089
+#define mmRCC_VDM_SUPPORT_BASE_IDX 2
+#define mmRCC_PEER_REG_RANGE0 0x00be
+#define mmRCC_PEER_REG_RANGE0_BASE_IDX 2
+#define mmRCC_PEER_REG_RANGE1 0x00bf
+#define mmRCC_PEER_REG_RANGE1_BASE_IDX 2
+#define mmRCC_BUS_CNTL 0x00c1
+#define mmRCC_BUS_CNTL_BASE_IDX 2
+#define mmRCC_CONFIG_CNTL 0x00c2
+#define mmRCC_CONFIG_CNTL_BASE_IDX 2
+#define mmRCC_CONFIG_F0_BASE 0x00c6
+#define mmRCC_CONFIG_F0_BASE_BASE_IDX 2
+#define mmRCC_CONFIG_APER_SIZE 0x00c7
+#define mmRCC_CONFIG_APER_SIZE_BASE_IDX 2
+#define mmRCC_CONFIG_REG_APER_SIZE 0x00c8
+#define mmRCC_CONFIG_REG_APER_SIZE_BASE_IDX 2
+#define mmRCC_XDMA_LO 0x00c9
+#define mmRCC_XDMA_LO_BASE_IDX 2
+#define mmRCC_XDMA_HI 0x00ca
+#define mmRCC_XDMA_HI_BASE_IDX 2
+#define mmRCC_FEATURES_CONTROL_MISC 0x00cb
+#define mmRCC_FEATURES_CONTROL_MISC_BASE_IDX 2
+#define mmRCC_BUSNUM_CNTL1 0x00cc
+#define mmRCC_BUSNUM_CNTL1_BASE_IDX 2
+#define mmRCC_BUSNUM_LIST0 0x00cd
+#define mmRCC_BUSNUM_LIST0_BASE_IDX 2
+#define mmRCC_BUSNUM_LIST1 0x00ce
+#define mmRCC_BUSNUM_LIST1_BASE_IDX 2
+#define mmRCC_BUSNUM_CNTL2 0x00cf
+#define mmRCC_BUSNUM_CNTL2_BASE_IDX 2
+#define mmRCC_CAPTURE_HOST_BUSNUM 0x00d0
+#define mmRCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2
+#define mmRCC_HOST_BUSNUM 0x00d1
+#define mmRCC_HOST_BUSNUM_BASE_IDX 2
+#define mmRCC_PEER0_FB_OFFSET_HI 0x00d2
+#define mmRCC_PEER0_FB_OFFSET_HI_BASE_IDX 2
+#define mmRCC_PEER0_FB_OFFSET_LO 0x00d3
+#define mmRCC_PEER0_FB_OFFSET_LO_BASE_IDX 2
+#define mmRCC_PEER1_FB_OFFSET_HI 0x00d4
+#define mmRCC_PEER1_FB_OFFSET_HI_BASE_IDX 2
+#define mmRCC_PEER1_FB_OFFSET_LO 0x00d5
+#define mmRCC_PEER1_FB_OFFSET_LO_BASE_IDX 2
+#define mmRCC_PEER2_FB_OFFSET_HI 0x00d6
+#define mmRCC_PEER2_FB_OFFSET_HI_BASE_IDX 2
+#define mmRCC_PEER2_FB_OFFSET_LO 0x00d7
+#define mmRCC_PEER2_FB_OFFSET_LO_BASE_IDX 2
+#define mmRCC_PEER3_FB_OFFSET_HI 0x00d8
+#define mmRCC_PEER3_FB_OFFSET_HI_BASE_IDX 2
+#define mmRCC_PEER3_FB_OFFSET_LO 0x00d9
+#define mmRCC_PEER3_FB_OFFSET_LO_BASE_IDX 2
+#define mmRCC_CMN_LINK_CNTL 0x00de
+#define mmRCC_CMN_LINK_CNTL_BASE_IDX 2
+#define mmRCC_EP_REQUESTERID_RESTORE 0x00df
+#define mmRCC_EP_REQUESTERID_RESTORE_BASE_IDX 2
+#define mmRCC_LTR_LSWITCH_CNTL 0x00e0
+#define mmRCC_LTR_LSWITCH_CNTL_BASE_IDX 2
+#define mmRCC_MH_ARB_CNTL 0x00e1
+#define mmRCC_MH_ARB_CNTL_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_BIFDEC1[13440..14975]
+// base address: 0x3480
+#define mmBIF_MM_INDACCESS_CNTL 0x00e6
+#define mmBIF_MM_INDACCESS_CNTL_BASE_IDX 2
+#define mmBUS_CNTL 0x00e7
+#define mmBUS_CNTL_BASE_IDX 2
+#define mmBIF_SCRATCH0 0x00e8
+#define mmBIF_SCRATCH0_BASE_IDX 2
+#define mmBIF_SCRATCH1 0x00e9
+#define mmBIF_SCRATCH1_BASE_IDX 2
+#define mmBX_RESET_EN 0x00ed
+#define mmBX_RESET_EN_BASE_IDX 2
+#define mmMM_CFGREGS_CNTL 0x00ee
+#define mmMM_CFGREGS_CNTL_BASE_IDX 2
+#define mmBX_RESET_CNTL 0x00f0
+#define mmBX_RESET_CNTL_BASE_IDX 2
+#define mmINTERRUPT_CNTL 0x00f1
+#define mmINTERRUPT_CNTL_BASE_IDX 2
+#define mmINTERRUPT_CNTL2 0x00f2
+#define mmINTERRUPT_CNTL2_BASE_IDX 2
+#define mmCLKREQB_PAD_CNTL 0x00f8
+#define mmCLKREQB_PAD_CNTL_BASE_IDX 2
+#define mmBIF_FEATURES_CONTROL_MISC 0x00fb
+#define mmBIF_FEATURES_CONTROL_MISC_BASE_IDX 2
+#define mmBIF_DOORBELL_CNTL 0x00fc
+#define mmBIF_DOORBELL_CNTL_BASE_IDX 2
+#define mmBIF_DOORBELL_INT_CNTL 0x00fd
+#define mmBIF_DOORBELL_INT_CNTL_BASE_IDX 2
+#define mmBIF_FB_EN 0x00ff
+#define mmBIF_FB_EN_BASE_IDX 2
+#define mmBIF_BUSY_DELAY_CNTR 0x0100
+#define mmBIF_BUSY_DELAY_CNTR_BASE_IDX 2
+#define mmBIF_MST_TRANS_PENDING_VF 0x0109
+#define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX 2
+#define mmBIF_SLV_TRANS_PENDING_VF 0x010a
+#define mmBIF_SLV_TRANS_PENDING_VF_BASE_IDX 2
+#define mmBACO_CNTL 0x010b
+#define mmBACO_CNTL_BASE_IDX 2
+#define mmBIF_BACO_EXIT_TIME0 0x010c
+#define mmBIF_BACO_EXIT_TIME0_BASE_IDX 2
+#define mmBIF_BACO_EXIT_TIMER1 0x010d
+#define mmBIF_BACO_EXIT_TIMER1_BASE_IDX 2
+#define mmBIF_BACO_EXIT_TIMER2 0x010e
+#define mmBIF_BACO_EXIT_TIMER2_BASE_IDX 2
+#define mmBIF_BACO_EXIT_TIMER3 0x010f
+#define mmBIF_BACO_EXIT_TIMER3_BASE_IDX 2
+#define mmBIF_BACO_EXIT_TIMER4 0x0110
+#define mmBIF_BACO_EXIT_TIMER4_BASE_IDX 2
+#define mmMEM_TYPE_CNTL 0x0111
+#define mmMEM_TYPE_CNTL_BASE_IDX 2
+#define mmSMU_BIF_VDDGFX_PWR_STATUS 0x0113
+#define mmSMU_BIF_VDDGFX_PWR_STATUS_BASE_IDX 2
+#define mmBIF_VDDGFX_GFX0_LOWER 0x0114
+#define mmBIF_VDDGFX_GFX0_LOWER_BASE_IDX 2
+#define mmBIF_VDDGFX_GFX0_UPPER 0x0115
+#define mmBIF_VDDGFX_GFX0_UPPER_BASE_IDX 2
+#define mmBIF_VDDGFX_GFX1_LOWER 0x0116
+#define mmBIF_VDDGFX_GFX1_LOWER_BASE_IDX 2
+#define mmBIF_VDDGFX_GFX1_UPPER 0x0117
+#define mmBIF_VDDGFX_GFX1_UPPER_BASE_IDX 2
+#define mmBIF_VDDGFX_GFX2_LOWER 0x0118
+#define mmBIF_VDDGFX_GFX2_LOWER_BASE_IDX 2
+#define mmBIF_VDDGFX_GFX2_UPPER 0x0119
+#define mmBIF_VDDGFX_GFX2_UPPER_BASE_IDX 2
+#define mmBIF_VDDGFX_GFX3_LOWER 0x011a
+#define mmBIF_VDDGFX_GFX3_LOWER_BASE_IDX 2
+#define mmBIF_VDDGFX_GFX3_UPPER 0x011b
+#define mmBIF_VDDGFX_GFX3_UPPER_BASE_IDX 2
+#define mmBIF_VDDGFX_GFX4_LOWER 0x011c
+#define mmBIF_VDDGFX_GFX4_LOWER_BASE_IDX 2
+#define mmBIF_VDDGFX_GFX4_UPPER 0x011d
+#define mmBIF_VDDGFX_GFX4_UPPER_BASE_IDX 2
+#define mmBIF_VDDGFX_GFX5_LOWER 0x011e
+#define mmBIF_VDDGFX_GFX5_LOWER_BASE_IDX 2
+#define mmBIF_VDDGFX_GFX5_UPPER 0x011f
+#define mmBIF_VDDGFX_GFX5_UPPER_BASE_IDX 2
+#define mmBIF_VDDGFX_RSV1_LOWER 0x0120
+#define mmBIF_VDDGFX_RSV1_LOWER_BASE_IDX 2
+#define mmBIF_VDDGFX_RSV1_UPPER 0x0121
+#define mmBIF_VDDGFX_RSV1_UPPER_BASE_IDX 2
+#define mmBIF_VDDGFX_RSV2_LOWER 0x0122
+#define mmBIF_VDDGFX_RSV2_LOWER_BASE_IDX 2
+#define mmBIF_VDDGFX_RSV2_UPPER 0x0123
+#define mmBIF_VDDGFX_RSV2_UPPER_BASE_IDX 2
+#define mmBIF_VDDGFX_RSV3_LOWER 0x0124
+#define mmBIF_VDDGFX_RSV3_LOWER_BASE_IDX 2
+#define mmBIF_VDDGFX_RSV3_UPPER 0x0125
+#define mmBIF_VDDGFX_RSV3_UPPER_BASE_IDX 2
+#define mmBIF_VDDGFX_RSV4_LOWER 0x0126
+#define mmBIF_VDDGFX_RSV4_LOWER_BASE_IDX 2
+#define mmBIF_VDDGFX_RSV4_UPPER 0x0127
+#define mmBIF_VDDGFX_RSV4_UPPER_BASE_IDX 2
+#define mmBIF_VDDGFX_FB_CMP 0x0128
+#define mmBIF_VDDGFX_FB_CMP_BASE_IDX 2
+#define mmBIF_DOORBELL_GBLAPER1_LOWER 0x0129
+#define mmBIF_DOORBELL_GBLAPER1_LOWER_BASE_IDX 2
+#define mmBIF_DOORBELL_GBLAPER1_UPPER 0x012a
+#define mmBIF_DOORBELL_GBLAPER1_UPPER_BASE_IDX 2
+#define mmBIF_DOORBELL_GBLAPER2_LOWER 0x012b
+#define mmBIF_DOORBELL_GBLAPER2_LOWER_BASE_IDX 2
+#define mmBIF_DOORBELL_GBLAPER2_UPPER 0x012c
+#define mmBIF_DOORBELL_GBLAPER2_UPPER_BASE_IDX 2
+#define mmREMAP_HDP_MEM_FLUSH_CNTL 0x012d
+#define mmREMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2
+#define mmREMAP_HDP_REG_FLUSH_CNTL 0x012e
+#define mmREMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_RB_CNTL 0x012f
+#define mmBIF_RB_CNTL_BASE_IDX 2
+#define mmBIF_RB_BASE 0x0130
+#define mmBIF_RB_BASE_BASE_IDX 2
+#define mmBIF_RB_RPTR 0x0131
+#define mmBIF_RB_RPTR_BASE_IDX 2
+#define mmBIF_RB_WPTR 0x0132
+#define mmBIF_RB_WPTR_BASE_IDX 2
+#define mmBIF_RB_WPTR_ADDR_HI 0x0133
+#define mmBIF_RB_WPTR_ADDR_HI_BASE_IDX 2
+#define mmBIF_RB_WPTR_ADDR_LO 0x0134
+#define mmBIF_RB_WPTR_ADDR_LO_BASE_IDX 2
+#define mmMAILBOX_INDEX 0x0135
+#define mmMAILBOX_INDEX_BASE_IDX 2
+#define mmBIF_UVD_GPUIOV_CFG_SIZE 0x0143
+#define mmBIF_UVD_GPUIOV_CFG_SIZE_BASE_IDX 2
+#define mmBIF_VCE_GPUIOV_CFG_SIZE 0x0144
+#define mmBIF_VCE_GPUIOV_CFG_SIZE_BASE_IDX 2
+#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x0145
+#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 2
+#define mmBIF_PERSTB_PAD_CNTL 0x0148
+#define mmBIF_PERSTB_PAD_CNTL_BASE_IDX 2
+#define mmBIF_PX_EN_PAD_CNTL 0x0149
+#define mmBIF_PX_EN_PAD_CNTL_BASE_IDX 2
+#define mmBIF_REFPADKIN_PAD_CNTL 0x014a
+#define mmBIF_REFPADKIN_PAD_CNTL_BASE_IDX 2
+#define mmBIF_CLKREQB_PAD_CNTL 0x014b
+#define mmBIF_CLKREQB_PAD_CNTL_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_PF0_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_PF0_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_PF0_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_PF0_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_PF0_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_PF0_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_PF0_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_PF0_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_PF0_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_gdc_GDCDEC[14976..15487]
+// base address: 0x3a80
+#define mmNGDC_SDP_PORT_CTRL 0x01c2
+#define mmNGDC_SDP_PORT_CTRL_BASE_IDX 2
+#define mmSHUB_REGS_IF_CTL 0x01c3
+#define mmSHUB_REGS_IF_CTL_BASE_IDX 2
+#define mmNGDC_RESERVED_0 0x01cb
+#define mmNGDC_RESERVED_0_BASE_IDX 2
+#define mmNGDC_RESERVED_1 0x01cc
+#define mmNGDC_RESERVED_1_BASE_IDX 2
+#define mmNGDC_SDP_PORT_CTRL_SOCCLK 0x01cd
+#define mmNGDC_SDP_PORT_CTRL_SOCCLK_BASE_IDX 2
+#define mmBIF_SDMA0_DOORBELL_RANGE 0x01d0
+#define mmBIF_SDMA0_DOORBELL_RANGE_BASE_IDX 2
+#define mmBIF_SDMA1_DOORBELL_RANGE 0x01d1
+#define mmBIF_SDMA1_DOORBELL_RANGE_BASE_IDX 2
+#define mmBIF_IH_DOORBELL_RANGE 0x01d2
+#define mmBIF_IH_DOORBELL_RANGE_BASE_IDX 2
+#define mmBIF_MMSCH0_DOORBELL_RANGE 0x01d3
+#define mmBIF_MMSCH0_DOORBELL_RANGE_BASE_IDX 2
+#define mmBIF_DOORBELL_FENCE_CNTL 0x01de
+#define mmBIF_DOORBELL_FENCE_CNTL_BASE_IDX 2
+#define mmS2A_MISC_CNTL 0x01df
+#define mmS2A_MISC_CNTL_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_rcc_pf_0_BIFDEC2
+// base address: 0x0
+#define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_PF_0_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_PF_0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_PF_0_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_PF_0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_PF_0_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_PF_0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_PF_0_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_PF_0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_PF_0_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_PF_0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_PF_0_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_PF_0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_PF_0_GFXMSIX_PBA 0x0800
+#define mmRCC_PF_0_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_SYSPFVFDEC[0..255]
+// base address: 0x0
+//#define mmBIF_BX_PF_MM_INDEX 0x0000
+//#define mmBIF_BX_PF_MM_DATA 0x0001
+//#define mmBIF_BX_PF_MM_INDEX_HI 0x0006
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf0_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif_rcc_dev0_epf0_vf0_BIFPFVFDEC1
+// base address: 0x0
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf1_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf2_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf3_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf4_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf5_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf6_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf7_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf8_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf9_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf10_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf11_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf12_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf13_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf14_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf15_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: syshub_mmreg_ind_syshubind
+// base address: 0x0
+#define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK 0x10000
+#define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK 0x10004
+#define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x10008
+#define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x1000c
+#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x10010
+#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x10014
+#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL 0x10018
+#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL 0x1001c
+#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL 0x10020
+#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL 0x10024
+#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL 0x10028
+#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL 0x1002c
+#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL 0x10030
+#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL 0x10034
+#define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL 0x10100
+#define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL 0x10104
+#define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL 0x10108
+#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL 0x1010c
+#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL 0x10110
+#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL 0x10114
+#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL 0x10118
+#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL 0x1011c
+#define ixSYSHUB_MMREG_IND_SYSHUB_CG_CNTL 0x10300
+#define ixSYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE 0x10308
+#define ixSYSHUB_MMREG_IND_SYSHUB_HP_TIMER 0x1030c
+#define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK 0x10310
+#define ixSYSHUB_MMREG_IND_SYSHUB_SCRATCH 0x10f00
+#define ixSYSHUB_MMREG_IND_SYSHUB_CL_MASK 0x10f04
+#define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK 0x11000
+#define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK 0x11004
+#define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 0x11008
+#define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 0x1100c
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL 0x11010
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL 0x11014
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL 0x11018
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL 0x1101c
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL 0x11020
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL 0x11024
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL 0x11028
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL 0x1102c
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL 0x11030
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL 0x11034
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL 0x11038
+#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL 0x1103c
+#define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK 0x11040
+#define ixSYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD 0x20108
+#define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS 0x30008
+#define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS 0x31008
+#define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_2_FN_MOD_BM_ISS 0x32008
+#define ixSYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD 0x40108
+#define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD 0x50008
+#define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD 0x51008
+#define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD 0x52008
+#define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_3_FN_MOD 0x53008
+#define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_4_FN_MOD 0x54008
+#define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD 0x60108
+#define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD 0x61108
+#define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD 0x62108
+#define ixSYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS 0x70008
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h
new file mode 100644
index 000000000000..a02b67943372
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h
@@ -0,0 +1,133884 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _nbio_6_1_SH_MASK_HEADER
+#define _nbio_6_1_SH_MASK_HEADER
+
+
+// addressBlock: nbio_pcie_pswuscfg0_cfgdecp
+//PSWUSCFG0_VENDOR_ID
+#define PSWUSCFG0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define PSWUSCFG0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//PSWUSCFG0_DEVICE_ID
+#define PSWUSCFG0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define PSWUSCFG0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//PSWUSCFG0_COMMAND
+#define PSWUSCFG0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define PSWUSCFG0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define PSWUSCFG0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define PSWUSCFG0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define PSWUSCFG0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define PSWUSCFG0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define PSWUSCFG0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define PSWUSCFG0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define PSWUSCFG0_COMMAND__SERR_EN__SHIFT 0x8
+#define PSWUSCFG0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define PSWUSCFG0_COMMAND__INT_DIS__SHIFT 0xa
+#define PSWUSCFG0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define PSWUSCFG0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define PSWUSCFG0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define PSWUSCFG0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define PSWUSCFG0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define PSWUSCFG0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define PSWUSCFG0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define PSWUSCFG0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define PSWUSCFG0_COMMAND__SERR_EN_MASK 0x0100L
+#define PSWUSCFG0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define PSWUSCFG0_COMMAND__INT_DIS_MASK 0x0400L
+//PSWUSCFG0_STATUS
+#define PSWUSCFG0_STATUS__INT_STATUS__SHIFT 0x3
+#define PSWUSCFG0_STATUS__CAP_LIST__SHIFT 0x4
+#define PSWUSCFG0_STATUS__PCI_66_EN__SHIFT 0x5
+#define PSWUSCFG0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define PSWUSCFG0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define PSWUSCFG0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define PSWUSCFG0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define PSWUSCFG0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define PSWUSCFG0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define PSWUSCFG0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define PSWUSCFG0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define PSWUSCFG0_STATUS__INT_STATUS_MASK 0x0008L
+#define PSWUSCFG0_STATUS__CAP_LIST_MASK 0x0010L
+#define PSWUSCFG0_STATUS__PCI_66_EN_MASK 0x0020L
+#define PSWUSCFG0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define PSWUSCFG0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define PSWUSCFG0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define PSWUSCFG0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define PSWUSCFG0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define PSWUSCFG0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define PSWUSCFG0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define PSWUSCFG0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//PSWUSCFG0_REVISION_ID
+#define PSWUSCFG0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define PSWUSCFG0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define PSWUSCFG0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define PSWUSCFG0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//PSWUSCFG0_PROG_INTERFACE
+#define PSWUSCFG0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define PSWUSCFG0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//PSWUSCFG0_SUB_CLASS
+#define PSWUSCFG0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define PSWUSCFG0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//PSWUSCFG0_BASE_CLASS
+#define PSWUSCFG0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define PSWUSCFG0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//PSWUSCFG0_CACHE_LINE
+#define PSWUSCFG0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define PSWUSCFG0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//PSWUSCFG0_LATENCY
+#define PSWUSCFG0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define PSWUSCFG0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//PSWUSCFG0_HEADER
+#define PSWUSCFG0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define PSWUSCFG0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define PSWUSCFG0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define PSWUSCFG0_HEADER__DEVICE_TYPE_MASK 0x80L
+//PSWUSCFG0_BIST
+#define PSWUSCFG0_BIST__BIST_COMP__SHIFT 0x0
+#define PSWUSCFG0_BIST__BIST_STRT__SHIFT 0x6
+#define PSWUSCFG0_BIST__BIST_CAP__SHIFT 0x7
+#define PSWUSCFG0_BIST__BIST_COMP_MASK 0x0FL
+#define PSWUSCFG0_BIST__BIST_STRT_MASK 0x40L
+#define PSWUSCFG0_BIST__BIST_CAP_MASK 0x80L
+//PSWUSCFG0_SUB_BUS_NUMBER_LATENCY
+#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//PSWUSCFG0_IO_BASE_LIMIT
+#define PSWUSCFG0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define PSWUSCFG0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define PSWUSCFG0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define PSWUSCFG0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//PSWUSCFG0_SECONDARY_STATUS
+#define PSWUSCFG0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define PSWUSCFG0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define PSWUSCFG0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define PSWUSCFG0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define PSWUSCFG0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define PSWUSCFG0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define PSWUSCFG0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define PSWUSCFG0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define PSWUSCFG0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define PSWUSCFG0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define PSWUSCFG0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define PSWUSCFG0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define PSWUSCFG0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define PSWUSCFG0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//PSWUSCFG0_MEM_BASE_LIMIT
+#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//PSWUSCFG0_PREF_BASE_LIMIT
+#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//PSWUSCFG0_PREF_BASE_UPPER
+#define PSWUSCFG0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define PSWUSCFG0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//PSWUSCFG0_PREF_LIMIT_UPPER
+#define PSWUSCFG0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define PSWUSCFG0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//PSWUSCFG0_IO_BASE_LIMIT_HI
+#define PSWUSCFG0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define PSWUSCFG0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define PSWUSCFG0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define PSWUSCFG0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//PSWUSCFG0_CAP_PTR
+#define PSWUSCFG0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define PSWUSCFG0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//PSWUSCFG0_INTERRUPT_LINE
+#define PSWUSCFG0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define PSWUSCFG0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//PSWUSCFG0_INTERRUPT_PIN
+#define PSWUSCFG0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define PSWUSCFG0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//PSWUSCFG0_IRQ_BRIDGE_CNTL
+#define PSWUSCFG0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define PSWUSCFG0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define PSWUSCFG0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define PSWUSCFG0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define PSWUSCFG0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define PSWUSCFG0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define PSWUSCFG0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define PSWUSCFG0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define PSWUSCFG0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define PSWUSCFG0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define PSWUSCFG0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define PSWUSCFG0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define PSWUSCFG0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define PSWUSCFG0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define PSWUSCFG0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define PSWUSCFG0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//EXT_BRIDGE_CNTL
+#define EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//PSWUSCFG0_VENDOR_CAP_LIST
+#define PSWUSCFG0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PSWUSCFG0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define PSWUSCFG0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define PSWUSCFG0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define PSWUSCFG0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//PSWUSCFG0_ADAPTER_ID_W
+#define PSWUSCFG0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define PSWUSCFG0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define PSWUSCFG0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//PSWUSCFG0_PMI_CAP_LIST
+#define PSWUSCFG0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PSWUSCFG0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define PSWUSCFG0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//PSWUSCFG0_PMI_CAP
+#define PSWUSCFG0_PMI_CAP__VERSION__SHIFT 0x0
+#define PSWUSCFG0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define PSWUSCFG0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define PSWUSCFG0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define PSWUSCFG0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define PSWUSCFG0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define PSWUSCFG0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define PSWUSCFG0_PMI_CAP__VERSION_MASK 0x0007L
+#define PSWUSCFG0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define PSWUSCFG0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define PSWUSCFG0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define PSWUSCFG0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define PSWUSCFG0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define PSWUSCFG0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//PSWUSCFG0_PMI_STATUS_CNTL
+#define PSWUSCFG0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define PSWUSCFG0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define PSWUSCFG0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define PSWUSCFG0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define PSWUSCFG0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define PSWUSCFG0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define PSWUSCFG0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define PSWUSCFG0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define PSWUSCFG0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define PSWUSCFG0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define PSWUSCFG0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define PSWUSCFG0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define PSWUSCFG0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define PSWUSCFG0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define PSWUSCFG0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define PSWUSCFG0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define PSWUSCFG0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define PSWUSCFG0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//PSWUSCFG0_PCIE_CAP_LIST
+#define PSWUSCFG0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PSWUSCFG0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define PSWUSCFG0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//PSWUSCFG0_PCIE_CAP
+#define PSWUSCFG0_PCIE_CAP__VERSION__SHIFT 0x0
+#define PSWUSCFG0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define PSWUSCFG0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define PSWUSCFG0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define PSWUSCFG0_PCIE_CAP__VERSION_MASK 0x000FL
+#define PSWUSCFG0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define PSWUSCFG0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define PSWUSCFG0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//PSWUSCFG0_DEVICE_CAP
+#define PSWUSCFG0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define PSWUSCFG0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define PSWUSCFG0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define PSWUSCFG0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define PSWUSCFG0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define PSWUSCFG0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define PSWUSCFG0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define PSWUSCFG0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define PSWUSCFG0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define PSWUSCFG0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define PSWUSCFG0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define PSWUSCFG0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define PSWUSCFG0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define PSWUSCFG0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define PSWUSCFG0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define PSWUSCFG0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define PSWUSCFG0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define PSWUSCFG0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//PSWUSCFG0_DEVICE_CNTL
+#define PSWUSCFG0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define PSWUSCFG0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define PSWUSCFG0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define PSWUSCFG0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define PSWUSCFG0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define PSWUSCFG0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define PSWUSCFG0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define PSWUSCFG0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define PSWUSCFG0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define PSWUSCFG0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define PSWUSCFG0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define PSWUSCFG0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define PSWUSCFG0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define PSWUSCFG0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define PSWUSCFG0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define PSWUSCFG0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define PSWUSCFG0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define PSWUSCFG0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define PSWUSCFG0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define PSWUSCFG0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define PSWUSCFG0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define PSWUSCFG0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define PSWUSCFG0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define PSWUSCFG0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//PSWUSCFG0_DEVICE_STATUS
+#define PSWUSCFG0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define PSWUSCFG0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define PSWUSCFG0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define PSWUSCFG0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define PSWUSCFG0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define PSWUSCFG0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define PSWUSCFG0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define PSWUSCFG0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define PSWUSCFG0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define PSWUSCFG0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define PSWUSCFG0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define PSWUSCFG0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//PSWUSCFG0_LINK_CAP
+#define PSWUSCFG0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define PSWUSCFG0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define PSWUSCFG0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define PSWUSCFG0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define PSWUSCFG0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define PSWUSCFG0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define PSWUSCFG0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define PSWUSCFG0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define PSWUSCFG0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define PSWUSCFG0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define PSWUSCFG0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define PSWUSCFG0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define PSWUSCFG0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define PSWUSCFG0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define PSWUSCFG0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define PSWUSCFG0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define PSWUSCFG0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define PSWUSCFG0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define PSWUSCFG0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define PSWUSCFG0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define PSWUSCFG0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define PSWUSCFG0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//PSWUSCFG0_LINK_CNTL
+#define PSWUSCFG0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define PSWUSCFG0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define PSWUSCFG0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define PSWUSCFG0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define PSWUSCFG0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define PSWUSCFG0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define PSWUSCFG0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define PSWUSCFG0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define PSWUSCFG0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define PSWUSCFG0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define PSWUSCFG0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define PSWUSCFG0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define PSWUSCFG0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define PSWUSCFG0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define PSWUSCFG0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define PSWUSCFG0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define PSWUSCFG0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define PSWUSCFG0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define PSWUSCFG0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define PSWUSCFG0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//PSWUSCFG0_LINK_STATUS
+#define PSWUSCFG0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define PSWUSCFG0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define PSWUSCFG0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define PSWUSCFG0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define PSWUSCFG0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define PSWUSCFG0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define PSWUSCFG0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define PSWUSCFG0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define PSWUSCFG0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define PSWUSCFG0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define PSWUSCFG0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define PSWUSCFG0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define PSWUSCFG0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define PSWUSCFG0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//PSWUSCFG0_DEVICE_CAP2
+#define PSWUSCFG0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define PSWUSCFG0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define PSWUSCFG0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define PSWUSCFG0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define PSWUSCFG0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define PSWUSCFG0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define PSWUSCFG0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define PSWUSCFG0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define PSWUSCFG0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define PSWUSCFG0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define PSWUSCFG0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define PSWUSCFG0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define PSWUSCFG0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define PSWUSCFG0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define PSWUSCFG0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define PSWUSCFG0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define PSWUSCFG0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define PSWUSCFG0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define PSWUSCFG0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define PSWUSCFG0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define PSWUSCFG0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define PSWUSCFG0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define PSWUSCFG0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define PSWUSCFG0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define PSWUSCFG0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define PSWUSCFG0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define PSWUSCFG0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define PSWUSCFG0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//PSWUSCFG0_DEVICE_CNTL2
+#define PSWUSCFG0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define PSWUSCFG0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define PSWUSCFG0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define PSWUSCFG0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define PSWUSCFG0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define PSWUSCFG0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define PSWUSCFG0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define PSWUSCFG0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define PSWUSCFG0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define PSWUSCFG0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define PSWUSCFG0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define PSWUSCFG0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define PSWUSCFG0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define PSWUSCFG0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define PSWUSCFG0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define PSWUSCFG0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define PSWUSCFG0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define PSWUSCFG0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define PSWUSCFG0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define PSWUSCFG0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//PSWUSCFG0_DEVICE_STATUS2
+#define PSWUSCFG0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define PSWUSCFG0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//PSWUSCFG0_LINK_CAP2
+#define PSWUSCFG0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define PSWUSCFG0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define PSWUSCFG0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define PSWUSCFG0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define PSWUSCFG0_LINK_CAP2__RESERVED__SHIFT 0x13
+#define PSWUSCFG0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define PSWUSCFG0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define PSWUSCFG0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define PSWUSCFG0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define PSWUSCFG0_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//PSWUSCFG0_LINK_CNTL2
+#define PSWUSCFG0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define PSWUSCFG0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define PSWUSCFG0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define PSWUSCFG0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define PSWUSCFG0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define PSWUSCFG0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define PSWUSCFG0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define PSWUSCFG0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define PSWUSCFG0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define PSWUSCFG0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define PSWUSCFG0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define PSWUSCFG0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define PSWUSCFG0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define PSWUSCFG0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define PSWUSCFG0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define PSWUSCFG0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//PSWUSCFG0_LINK_STATUS2
+#define PSWUSCFG0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define PSWUSCFG0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define PSWUSCFG0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define PSWUSCFG0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//PSWUSCFG0_MSI_CAP_LIST
+#define PSWUSCFG0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PSWUSCFG0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define PSWUSCFG0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//PSWUSCFG0_MSI_MSG_CNTL
+#define PSWUSCFG0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define PSWUSCFG0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define PSWUSCFG0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define PSWUSCFG0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define PSWUSCFG0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define PSWUSCFG0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define PSWUSCFG0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define PSWUSCFG0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define PSWUSCFG0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define PSWUSCFG0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//PSWUSCFG0_MSI_MSG_ADDR_LO
+#define PSWUSCFG0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define PSWUSCFG0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PSWUSCFG0_MSI_MSG_ADDR_HI
+#define PSWUSCFG0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define PSWUSCFG0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PSWUSCFG0_MSI_MSG_DATA
+#define PSWUSCFG0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define PSWUSCFG0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//PSWUSCFG0_MSI_MSG_DATA_64
+#define PSWUSCFG0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define PSWUSCFG0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//PSWUSCFG0_SSID_CAP_LIST
+#define PSWUSCFG0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PSWUSCFG0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define PSWUSCFG0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//PSWUSCFG0_SSID_CAP
+#define PSWUSCFG0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define PSWUSCFG0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define PSWUSCFG0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//MSI_MAP_CAP_LIST
+#define MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//MSI_MAP_CAP
+#define MSI_MAP_CAP__EN__SHIFT 0x0
+#define MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define MSI_MAP_CAP__EN_MASK 0x0001L
+#define MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//MSI_MAP_ADDR_LO
+#define MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//MSI_MAP_ADDR_HI
+#define MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR
+#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//PSWUSCFG0_PCIE_VENDOR_SPECIFIC1
+#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//PSWUSCFG0_PCIE_VENDOR_SPECIFIC2
+#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//PSWUSCFG0_PCIE_VC_ENH_CAP_LIST
+#define PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_PCIE_PORT_VC_CAP_REG1
+#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//PSWUSCFG0_PCIE_PORT_VC_CAP_REG2
+#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//PSWUSCFG0_PCIE_PORT_VC_CNTL
+#define PSWUSCFG0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define PSWUSCFG0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define PSWUSCFG0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define PSWUSCFG0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//PSWUSCFG0_PCIE_PORT_VC_STATUS
+#define PSWUSCFG0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define PSWUSCFG0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//PSWUSCFG0_PCIE_VC0_RESOURCE_CAP
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//PSWUSCFG0_PCIE_VC0_RESOURCE_STATUS
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define PSWUSCFG0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//PSWUSCFG0_PCIE_VC1_RESOURCE_CAP
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//PSWUSCFG0_PCIE_VC1_RESOURCE_STATUS
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define PSWUSCFG0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1
+#define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2
+#define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_PCIE_UNCORR_ERR_STATUS
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//PSWUSCFG0_PCIE_UNCORR_ERR_MASK
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//PSWUSCFG0_PCIE_CORR_ERR_STATUS
+#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//PSWUSCFG0_PCIE_CORR_ERR_MASK
+#define PSWUSCFG0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define PSWUSCFG0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define PSWUSCFG0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define PSWUSCFG0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define PSWUSCFG0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define PSWUSCFG0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define PSWUSCFG0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define PSWUSCFG0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define PSWUSCFG0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define PSWUSCFG0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define PSWUSCFG0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define PSWUSCFG0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define PSWUSCFG0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define PSWUSCFG0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define PSWUSCFG0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define PSWUSCFG0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL
+#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//PSWUSCFG0_PCIE_HDR_LOG0
+#define PSWUSCFG0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define PSWUSCFG0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//PSWUSCFG0_PCIE_HDR_LOG1
+#define PSWUSCFG0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define PSWUSCFG0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//PSWUSCFG0_PCIE_HDR_LOG2
+#define PSWUSCFG0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define PSWUSCFG0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//PSWUSCFG0_PCIE_HDR_LOG3
+#define PSWUSCFG0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define PSWUSCFG0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//PSWUSCFG0_PCIE_TLP_PREFIX_LOG0
+#define PSWUSCFG0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define PSWUSCFG0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//PSWUSCFG0_PCIE_TLP_PREFIX_LOG1
+#define PSWUSCFG0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define PSWUSCFG0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//PSWUSCFG0_PCIE_TLP_PREFIX_LOG2
+#define PSWUSCFG0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define PSWUSCFG0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//PSWUSCFG0_PCIE_TLP_PREFIX_LOG3
+#define PSWUSCFG0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define PSWUSCFG0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST
+#define PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_PCIE_LINK_CNTL3
+#define PSWUSCFG0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define PSWUSCFG0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define PSWUSCFG0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define PSWUSCFG0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define PSWUSCFG0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define PSWUSCFG0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define PSWUSCFG0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define PSWUSCFG0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//PSWUSCFG0_PCIE_LANE_ERROR_STATUS
+#define PSWUSCFG0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define PSWUSCFG0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define PSWUSCFG0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define PSWUSCFG0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST
+#define PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_PCIE_ACS_CAP
+#define PSWUSCFG0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define PSWUSCFG0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define PSWUSCFG0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define PSWUSCFG0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define PSWUSCFG0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define PSWUSCFG0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define PSWUSCFG0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define PSWUSCFG0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define PSWUSCFG0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define PSWUSCFG0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define PSWUSCFG0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define PSWUSCFG0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define PSWUSCFG0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define PSWUSCFG0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define PSWUSCFG0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define PSWUSCFG0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//PSWUSCFG0_PCIE_ACS_CNTL
+#define PSWUSCFG0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define PSWUSCFG0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define PSWUSCFG0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define PSWUSCFG0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define PSWUSCFG0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define PSWUSCFG0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define PSWUSCFG0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define PSWUSCFG0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define PSWUSCFG0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define PSWUSCFG0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define PSWUSCFG0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define PSWUSCFG0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define PSWUSCFG0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define PSWUSCFG0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//PSWUSCFG0_PCIE_MC_ENH_CAP_LIST
+#define PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_PCIE_MC_CAP
+#define PSWUSCFG0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define PSWUSCFG0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define PSWUSCFG0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define PSWUSCFG0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//PSWUSCFG0_PCIE_MC_CNTL
+#define PSWUSCFG0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define PSWUSCFG0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define PSWUSCFG0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define PSWUSCFG0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//PSWUSCFG0_PCIE_MC_ADDR0
+#define PSWUSCFG0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define PSWUSCFG0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define PSWUSCFG0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define PSWUSCFG0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//PSWUSCFG0_PCIE_MC_ADDR1
+#define PSWUSCFG0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define PSWUSCFG0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//PSWUSCFG0_PCIE_MC_RCV0
+#define PSWUSCFG0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define PSWUSCFG0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//PSWUSCFG0_PCIE_MC_RCV1
+#define PSWUSCFG0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define PSWUSCFG0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//PSWUSCFG0_PCIE_MC_BLOCK_ALL0
+#define PSWUSCFG0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define PSWUSCFG0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//PSWUSCFG0_PCIE_MC_BLOCK_ALL1
+#define PSWUSCFG0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define PSWUSCFG0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//PCIE_MC_OVERLAY_BAR0
+#define PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//PCIE_MC_OVERLAY_BAR1
+#define PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST
+#define PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_PCIE_LTR_CAP
+#define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST
+#define PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_PCIE_ARI_CAP
+#define PSWUSCFG0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define PSWUSCFG0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define PSWUSCFG0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define PSWUSCFG0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define PSWUSCFG0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define PSWUSCFG0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//PSWUSCFG0_PCIE_ARI_CNTL
+#define PSWUSCFG0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define PSWUSCFG0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define PSWUSCFG0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define PSWUSCFG0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define PSWUSCFG0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define PSWUSCFG0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//PCIE_L1_PM_SUB_CAP_LIST
+#define PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PCIE_L1_PM_SUB_CAP
+#define PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//PCIE_L1_PM_SUB_CNTL
+#define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//PCIE_L1_PM_SUB_CNTL2
+#define PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//PCIE_ESM_CAP_LIST
+#define PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PCIE_ESM_HEADER_1
+#define PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//PCIE_ESM_HEADER_2
+#define PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//PCIE_ESM_STATUS
+#define PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//PCIE_ESM_CTRL
+#define PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//PCIE_ESM_CAP_1
+#define PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//PCIE_ESM_CAP_2
+#define PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//PCIE_ESM_CAP_3
+#define PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//PCIE_ESM_CAP_4
+#define PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//PCIE_ESM_CAP_5
+#define PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//PCIE_ESM_CAP_6
+#define PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//PCIE_ESM_CAP_7
+#define PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_0_STATUS
+#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_HEADER
+#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_0_BIST
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF1_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_COMMAND
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF1_0_STATUS
+#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_LATENCY
+#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_HEADER
+#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_0_BIST
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF1_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF1_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF1_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF1_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF1_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF1_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF1_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF1_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_swds_bifcfgdecp
+//BIF_CFG_DEV0_SWDS0_VENDOR_ID
+#define BIF_CFG_DEV0_SWDS0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS0_DEVICE_ID
+#define BIF_CFG_DEV0_SWDS0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS0_COMMAND
+#define BIF_CFG_DEV0_SWDS0_COMMAND__IOEN_DN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_COMMAND__MEMEN_DN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_COMMAND__IOEN_DN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_COMMAND__MEMEN_DN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_SWDS0_STATUS
+#define BIF_CFG_DEV0_SWDS0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_SWDS0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_SWDS0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_SWDS0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_SWDS0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_REVISION_ID
+#define BIF_CFG_DEV0_SWDS0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS0_PROG_INTERFACE
+#define BIF_CFG_DEV0_SWDS0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS0_SUB_CLASS
+#define BIF_CFG_DEV0_SWDS0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS0_BASE_CLASS
+#define BIF_CFG_DEV0_SWDS0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS0_CACHE_LINE
+#define BIF_CFG_DEV0_SWDS0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS0_LATENCY
+#define BIF_CFG_DEV0_SWDS0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS0_HEADER
+#define BIF_CFG_DEV0_SWDS0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_SWDS0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_SWDS0_BIST
+#define BIF_CFG_DEV0_SWDS0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_SWDS0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_SWDS0_BASE_ADDR_1
+#define BIF_CFG_DEV0_SWDS0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT
+#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT
+#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER
+#define BIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_SWDS0_CAP_PTR
+#define BIF_CFG_DEV0_SWDS0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_SWDS0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_SWDS0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_SWDS0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_PMI_CAP
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_PCIE_CAP
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_SWDS0_DEVICE_CAP
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_SWDS0_DEVICE_CNTL
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_DEVICE_STATUS
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_SWDS0_LINK_CAP
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS0_LINK_CNTL
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_SWDS0_LINK_STATUS
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_SLOT_CAP
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIF_CFG_DEV0_SWDS0_SLOT_CNTL
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+//BIF_CFG_DEV0_SWDS0_SLOT_STATUS
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIF_CFG_DEV0_SWDS0_DEVICE_CAP2
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS0_LINK_CAP2
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_SWDS0_LINK_CNTL2
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_SWDS0_LINK_STATUS2
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_SWDS0_SLOT_CAP2
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_SLOT_CNTL2
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS0_SLOT_STATUS2
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_SSID_CAP
+#define BIF_CFG_DEV0_SWDS0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF0_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF0_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF0_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF0_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF0_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF0_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF0_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF1_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF1_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF1_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF1_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF1_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF1_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF1_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf2_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF2_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF2_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF2_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF2_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF2_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF2_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF2_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF2_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf3_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF3_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF3_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF3_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF3_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF3_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF3_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF3_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF3_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf4_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF4_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF4_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF4_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF4_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF4_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF4_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF4_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF4_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf5_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF5_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF5_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF5_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF5_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF5_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF5_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF5_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF5_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf6_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF6_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF6_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF6_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF6_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF6_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF6_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF6_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF6_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf7_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF7_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF7_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF7_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF7_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF7_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF7_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF7_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF7_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf8_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF8_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF8_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF8_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF8_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF8_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF8_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF8_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF8_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf9_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF9_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF9_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF9_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF9_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF9_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF9_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF9_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF9_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf10_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF10_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF10_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF10_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF10_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF10_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF10_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF10_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF10_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf11_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF11_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF11_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF11_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF11_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF11_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF11_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF11_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF11_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf12_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF12_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF12_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF12_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF12_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF12_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF12_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF12_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF12_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf13_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF13_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF13_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF13_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF13_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF13_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF13_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF13_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF13_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf14_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF14_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF14_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF14_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF14_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF14_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF14_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF14_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF14_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf15_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF15_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF15_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF15_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF15_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF15_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF15_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF15_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF15_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_SYSPFVFDEC[0..767]
+//MM_INDEX
+#define MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define MM_INDEX__MM_APER__SHIFT 0x1f
+#define MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define MM_INDEX__MM_APER_MASK 0x80000000L
+//MM_DATA
+#define MM_DATA__MM_DATA__SHIFT 0x0
+#define MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//MM_INDEX_HI
+#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_SYSDEC[0..767]
+//SYSHUB_INDEX_OVLP
+#define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0
+#define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK 0x003FFFFFL
+//SYSHUB_DATA_OVLP
+#define SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0
+#define SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK 0xFFFFFFFFL
+//PCIE_INDEX
+#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
+#define PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL
+//PCIE_DATA
+#define PCIE_DATA__PCIE_DATA__SHIFT 0x0
+#define PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL
+//PCIE_INDEX2
+#define PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0
+#define PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL
+//PCIE_DATA2
+#define PCIE_DATA2__PCIE_DATA2__SHIFT 0x0
+#define PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL
+//SBIOS_SCRATCH_0
+#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//SBIOS_SCRATCH_1
+#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//SBIOS_SCRATCH_2
+#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//SBIOS_SCRATCH_3
+#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_0
+#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0
+#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_1
+#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0
+#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_2
+#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
+#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_3
+#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
+#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_4
+#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0
+#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_5
+#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0
+#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_6
+#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
+#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_7
+#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0
+#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_8
+#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0
+#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_9
+#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0
+#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_10
+#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0
+#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_11
+#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0
+#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_12
+#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0
+#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_13
+#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0
+#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_14
+#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0
+#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_15
+#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0
+#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL
+//BIF_RLC_INTR_CNTL
+#define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0
+#define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK 0x00000008L
+//BIF_VCE_INTR_CNTL
+#define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0
+#define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK 0x00000008L
+//BIF_UVD_INTR_CNTL
+#define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0
+#define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK 0x00000008L
+//GFX_MMIOREG_CAM_ADDR0
+#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR0
+#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR1
+#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR1
+#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR2
+#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR2
+#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR3
+#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR3
+#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR4
+#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR4
+#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR5
+#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR5
+#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR6
+#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR6
+#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR7
+#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR7
+#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_CNTL
+#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0
+#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL
+//GFX_MMIOREG_CAM_ZERO_CPL
+#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL
+//GFX_MMIOREG_CAM_ONE_CPL
+#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL
+//GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
+#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0
+#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_syshub_mmreg_ind_syshubdec[32..39]
+//SYSHUB_INDEX
+#define SYSHUB_INDEX__INDEX__SHIFT 0x0
+#define SYSHUB_INDEX__INDEX_MASK 0xFFFFFFFFL
+//SYSHUB_DATA
+#define SYSHUB_DATA__DATA__SHIFT 0x0
+#define SYSHUB_DATA__DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_rcc_strap_BIFDEC1[13440..14975]
+//RCC_DEV0_EPF0_STRAP0
+#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
+#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
+#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
+#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
+#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif_rcc_ep_dev0_BIFDEC1[13440..14975]
+//EP_PCIE_SCRATCH
+#define EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//EP_PCIE_CNTL
+#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//EP_PCIE_INT_CNTL
+#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L
+#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L
+#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L
+#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L
+#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L
+#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L
+//EP_PCIE_INT_STATUS
+#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L
+#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L
+#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L
+#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L
+#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L
+#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L
+//EP_PCIE_RX_CNTL2
+#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+//EP_PCIE_BUS_CNTL
+#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+//EP_PCIE_CFG_CNTL
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+//EP_PCIE_TX_LTR_CNTL
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+#define EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L
+#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L
+#define EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//EP_PCIE_F0_DPA_CAP
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//EP_PCIE_F0_DPA_CNTL
+#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
+#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL
+#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//EP_PCIE_PME_CONTROL
+#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0
+#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL
+//EP_PCIEP_RESERVED
+#define EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//EP_PCIE_TX_CNTL
+#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L
+#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L
+#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L
+//EP_PCIE_TX_REQUESTER_ID
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//EP_PCIE_ERR_CNTL
+#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f
+#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L
+//EP_PCIE_RX_CNTL
+#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+//EP_PCIE_LC_SPEED_CNTL
+#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+
+
+// addressBlock: nbio_nbif_rcc_dwn_dev0_BIFDEC1[13440..14975]
+//DN_PCIE_RESERVED
+#define DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL
+//DN_PCIE_SCRATCH
+#define DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//DN_PCIE_CNTL
+#define DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7
+#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L
+#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//DN_PCIE_CONFIG_CNTL
+#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+//DN_PCIE_RX_CNTL2
+#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//DN_PCIE_BUS_CNTL
+#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8
+#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L
+//DN_PCIE_CFG_CNTL
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif_rcc_dwnp_dev0_BIFDEC1[13440..14975]
+//PCIE_ERR_CNTL
+#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+//PCIE_RX_CNTL
+#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9
+#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15
+#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L
+#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L
+#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//PCIE_LC_SPEED_CNTL
+#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+//PCIE_LC_CNTL2
+#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+//PCIEP_STRAP_MISC
+#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
+#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L
+//LTR_MSG_INFO_FROM_EP
+#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0
+#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_rcc_pf_0_BIFPFVFDEC1[13440..14975]
+//RCC_PF_0_0_RCC_ERR_LOG
+#define RCC_PF_0_0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_PF_0_0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_PF_0_0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_PF_0_0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_PF_0_0_RCC_DOORBELL_APER_EN
+#define RCC_PF_0_0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_PF_0_0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_PF_0_0_RCC_CONFIG_MEMSIZE
+#define RCC_PF_0_0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_PF_0_0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_PF_0_0_RCC_CONFIG_RESERVED
+#define RCC_PF_0_0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_PF_0_0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif_rcc_pf_0_BIFDEC1[13440..14975]
+//RCC_ERR_INT_CNTL
+#define RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0
+#define RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L
+//RCC_BACO_CNTL_MISC
+#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0
+#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1
+#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L
+#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L
+//RCC_RESET_EN
+#define RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf
+#define RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L
+//RCC_VDM_SUPPORT
+#define RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0
+#define RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1
+#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2
+#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3
+#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4
+#define RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L
+#define RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L
+#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L
+#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L
+#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L
+//RCC_PEER_REG_RANGE0
+#define RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0
+#define RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10
+#define RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL
+#define RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L
+//RCC_PEER_REG_RANGE1
+#define RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0
+#define RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10
+#define RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL
+#define RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L
+//RCC_BUS_CNTL
+#define RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
+#define RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
+#define RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
+#define RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5
+#define RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6
+#define RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7
+#define RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8
+#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc
+#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd
+#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10
+#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11
+#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12
+#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13
+#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14
+#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15
+#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18
+#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19
+#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c
+#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d
+#define RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L
+#define RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L
+#define RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L
+#define RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L
+#define RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L
+#define RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L
+#define RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L
+#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L
+#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L
+#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L
+#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L
+#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L
+#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L
+#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L
+#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L
+#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L
+#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L
+#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L
+#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L
+//RCC_CONFIG_CNTL
+#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0
+#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
+#define RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3
+#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L
+#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L
+#define RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L
+//RCC_CONFIG_F0_BASE
+#define RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0
+#define RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL
+//RCC_CONFIG_APER_SIZE
+#define RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0
+#define RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL
+//RCC_CONFIG_REG_APER_SIZE
+#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0
+#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x000FFFFFL
+//RCC_XDMA_LO
+#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0
+#define RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f
+#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL
+#define RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L
+//RCC_XDMA_HI
+#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0
+#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL
+//RCC_FEATURES_CONTROL_MISC
+#define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4
+#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5
+#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6
+#define RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7
+#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd
+#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe
+#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf
+#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10
+#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11
+#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12
+#define RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13
+#define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x00000010L
+#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x00000020L
+#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x00000040L
+#define RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L
+#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L
+#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L
+#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L
+#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L
+#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L
+#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L
+#define RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L
+//RCC_BUSNUM_CNTL1
+#define RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0
+#define RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL
+//RCC_BUSNUM_LIST0
+#define RCC_BUSNUM_LIST0__ID0__SHIFT 0x0
+#define RCC_BUSNUM_LIST0__ID1__SHIFT 0x8
+#define RCC_BUSNUM_LIST0__ID2__SHIFT 0x10
+#define RCC_BUSNUM_LIST0__ID3__SHIFT 0x18
+#define RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL
+#define RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L
+#define RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L
+#define RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L
+//RCC_BUSNUM_LIST1
+#define RCC_BUSNUM_LIST1__ID4__SHIFT 0x0
+#define RCC_BUSNUM_LIST1__ID5__SHIFT 0x8
+#define RCC_BUSNUM_LIST1__ID6__SHIFT 0x10
+#define RCC_BUSNUM_LIST1__ID7__SHIFT 0x18
+#define RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL
+#define RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L
+#define RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L
+#define RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L
+//RCC_BUSNUM_CNTL2
+#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0
+#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8
+#define RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10
+#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11
+#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL
+#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L
+#define RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L
+#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L
+//RCC_CAPTURE_HOST_BUSNUM
+#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0
+#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L
+//RCC_HOST_BUSNUM
+#define RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0
+#define RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL
+//RCC_PEER0_FB_OFFSET_HI
+#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_PEER0_FB_OFFSET_LO
+#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f
+#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L
+//RCC_PEER1_FB_OFFSET_HI
+#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_PEER1_FB_OFFSET_LO
+#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f
+#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L
+//RCC_PEER2_FB_OFFSET_HI
+#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_PEER2_FB_OFFSET_LO
+#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f
+#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L
+//RCC_PEER3_FB_OFFSET_HI
+#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_PEER3_FB_OFFSET_LO
+#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f
+#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L
+//RCC_CMN_LINK_CNTL
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2
+#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3
+#define RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L
+#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L
+#define RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L
+//RCC_EP_REQUESTERID_RESTORE
+#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0
+#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8
+#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL
+#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L
+//RCC_LTR_LSWITCH_CNTL
+#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0
+#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL
+//RCC_MH_ARB_CNTL
+#define RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0
+#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1
+#define RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L
+#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_BIFDEC1[13440..14975]
+//BIF_MM_INDACCESS_CNTL
+#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
+#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L
+//BUS_CNTL
+#define BUS_CNTL__PMI_INT_DIS_EP__SHIFT 0x3
+#define BUS_CNTL__PMI_INT_DIS_DN__SHIFT 0x4
+#define BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x5
+#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
+#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
+#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa
+#define BUS_CNTL__SET_MC_TC__SHIFT 0xd
+#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
+#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
+#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
+#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x13
+#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x14
+#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x15
+#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x16
+#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x17
+#define BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x18
+#define BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19
+#define BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT 0x1b
+#define BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT 0x1c
+#define BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d
+#define BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e
+#define BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f
+#define BUS_CNTL__PMI_INT_DIS_EP_MASK 0x00000008L
+#define BUS_CNTL__PMI_INT_DIS_DN_MASK 0x00000010L
+#define BUS_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000020L
+#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L
+#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L
+#define BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L
+#define BUS_CNTL__SET_MC_TC_MASK 0x0000E000L
+#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L
+#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L
+#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L
+#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00080000L
+#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00100000L
+#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00200000L
+#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00400000L
+#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00800000L
+#define BUS_CNTL__UR_OVRD_FOR_ECRC_EN_MASK 0x01000000L
+#define BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L
+#define BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK 0x08000000L
+#define BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK 0x10000000L
+#define BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L
+#define BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L
+#define BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L
+//BIF_SCRATCH0
+#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
+#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL
+//BIF_SCRATCH1
+#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
+#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL
+//BX_RESET_EN
+#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0
+#define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1
+#define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2
+#define BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8
+#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10
+#define BX_RESET_EN__COR_RESET_EN_MASK 0x00000001L
+#define BX_RESET_EN__REG_RESET_EN_MASK 0x00000002L
+#define BX_RESET_EN__STY_RESET_EN_MASK 0x00000004L
+#define BX_RESET_EN__FLR_TWICE_EN_MASK 0x00000100L
+#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L
+//MM_CFGREGS_CNTL
+#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
+#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6
+#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f
+#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L
+#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L
+#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L
+//BX_RESET_CNTL
+#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0
+#define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L
+//INTERRUPT_CNTL
+#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
+#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
+#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
+#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
+#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
+#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
+#define INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10
+#define INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11
+#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L
+#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L
+#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L
+#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L
+#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L
+#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L
+#define INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L
+#define INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L
+//INTERRUPT_CNTL2
+#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
+#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL
+//CLKREQB_PAD_CNTL
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L
+//BIF_FEATURES_CONTROL_MISC
+#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0
+#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
+#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
+#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3
+#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
+#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd
+#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf
+#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11
+#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12
+#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18
+#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L
+#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L
+#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L
+#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L
+#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L
+#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L
+#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L
+#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK 0x00020000L
+#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK 0x00040000L
+#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x01000000L
+//BIF_DOORBELL_CNTL
+#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0
+#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1
+#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
+#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
+#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b
+#define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L
+#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L
+#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L
+#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L
+#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L
+//BIF_DOORBELL_INT_CNTL
+#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0
+#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT 0x1
+#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
+#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT 0x11
+#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L
+#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS_MASK 0x00000002L
+#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L
+#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR_MASK 0x00020000L
+//BIF_FB_EN
+#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0
+#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
+#define BIF_FB_EN__FB_READ_EN_MASK 0x00000001L
+#define BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L
+//BIF_BUSY_DELAY_CNTR
+#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0
+#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x0000003FL
+//BIF_MST_TRANS_PENDING_VF
+#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x0000FFFFL
+//BIF_SLV_TRANS_PENDING_VF
+#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0
+#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x0000FFFFL
+//BACO_CNTL
+#define BACO_CNTL__BACO_EN__SHIFT 0x0
+#define BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x1
+#define BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2
+#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3
+#define BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5
+#define BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6
+#define BACO_CNTL__BACO_MODE__SHIFT 0x8
+#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9
+#define BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f
+#define BACO_CNTL__BACO_EN_MASK 0x00000001L
+#define BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK 0x00000002L
+#define BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L
+#define BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L
+#define BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L
+#define BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L
+#define BACO_CNTL__BACO_MODE_MASK 0x00000100L
+#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L
+#define BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L
+//BIF_BACO_EXIT_TIME0
+#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0
+#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BACO_EXIT_TIMER1
+#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0
+#define BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18
+#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR__SHIFT 0x19
+#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a
+#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b
+#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c
+#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d
+#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f
+#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL
+#define BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L
+#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR_MASK 0x02000000L
+#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L
+#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L
+#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L
+#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L
+#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L
+//BIF_BACO_EXIT_TIMER2
+#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0
+#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL
+//BIF_BACO_EXIT_TIMER3
+#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0
+#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BACO_EXIT_TIMER4
+#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0
+#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL
+//MEM_TYPE_CNTL
+#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0
+#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L
+//SMU_BIF_VDDGFX_PWR_STATUS
+#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0
+#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x00000001L
+//BIF_VDDGFX_GFX0_LOWER
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000L
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000L
+//BIF_VDDGFX_GFX0_UPPER
+#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x0003FFFCL
+//BIF_VDDGFX_GFX1_LOWER
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000L
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000L
+//BIF_VDDGFX_GFX1_UPPER
+#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x0003FFFCL
+//BIF_VDDGFX_GFX2_LOWER
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000L
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000L
+//BIF_VDDGFX_GFX2_UPPER
+#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x0003FFFCL
+//BIF_VDDGFX_GFX3_LOWER
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000L
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000L
+//BIF_VDDGFX_GFX3_UPPER
+#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x0003FFFCL
+//BIF_VDDGFX_GFX4_LOWER
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000L
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000L
+//BIF_VDDGFX_GFX4_UPPER
+#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x0003FFFCL
+//BIF_VDDGFX_GFX5_LOWER
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000L
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000L
+//BIF_VDDGFX_GFX5_UPPER
+#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x0003FFFCL
+//BIF_VDDGFX_RSV1_LOWER
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000L
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000L
+//BIF_VDDGFX_RSV1_UPPER
+#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x0003FFFCL
+//BIF_VDDGFX_RSV2_LOWER
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000L
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000L
+//BIF_VDDGFX_RSV2_UPPER
+#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x0003FFFCL
+//BIF_VDDGFX_RSV3_LOWER
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000L
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000L
+//BIF_VDDGFX_RSV3_UPPER
+#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x0003FFFCL
+//BIF_VDDGFX_RSV4_LOWER
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000L
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000L
+//BIF_VDDGFX_RSV4_UPPER
+#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x0003FFFCL
+//BIF_VDDGFX_FB_CMP
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x00000001L
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x00000002L
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x00000004L
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x00000008L
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x00000010L
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x00000020L
+//BIF_DOORBELL_GBLAPER1_LOWER
+#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2
+#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f
+#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0x00000FFCL
+#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000L
+//BIF_DOORBELL_GBLAPER1_UPPER
+#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2
+#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0x00000FFCL
+//BIF_DOORBELL_GBLAPER2_LOWER
+#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2
+#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f
+#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0x00000FFCL
+#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000L
+//BIF_DOORBELL_GBLAPER2_UPPER
+#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2
+#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0x00000FFCL
+//REMAP_HDP_MEM_FLUSH_CNTL
+#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//REMAP_HDP_REG_FLUSH_CNTL
+#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//BIF_RB_CNTL
+#define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
+#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
+#define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11
+#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L
+#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L
+#define BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L
+#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
+//BIF_RB_BASE
+#define BIF_RB_BASE__ADDR__SHIFT 0x0
+#define BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//BIF_RB_RPTR
+#define BIF_RB_RPTR__OFFSET__SHIFT 0x2
+#define BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_RB_WPTR
+#define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0
+#define BIF_RB_WPTR__OFFSET__SHIFT 0x2
+#define BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L
+#define BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_RB_WPTR_ADDR_HI
+#define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL
+//BIF_RB_WPTR_ADDR_LO
+#define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//MAILBOX_INDEX
+#define MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0
+#define MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL
+//BIF_UVD_GPUIOV_CFG_SIZE
+#define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_VCE_GPUIOV_CFG_SIZE
+#define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_GFX_SDMA_GPUIOV_CFG_SIZE
+#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_PERSTB_PAD_CNTL
+#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0
+#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL
+//BIF_PX_EN_PAD_CNTL
+#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0
+#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x000000FFL
+//BIF_REFPADKIN_PAD_CNTL
+#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0
+#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL
+//BIF_CLKREQB_PAD_CNTL
+#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0
+#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x00FFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_BIFPFVFDEC1
+//BIF_BX_PF0_BIF_BME_STATUS
+#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_PF0_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_PF0_GPU_HDP_FLUSH_REQ
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_PF0_GPU_HDP_FLUSH_DONE
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_PF0_BIF_TRANS_PENDING
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_CONTROL
+#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_PF0_MAILBOX_INT_CNTL
+#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_PF0_BIF_VMHV_MAILBOX
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif_gdc_GDCDEC[14976..15487]
+//NGDC_SDP_PORT_CTRL
+#define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0
+#define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x0000003FL
+//SHUB_REGS_IF_CTL
+#define SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0
+#define SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L
+//NGDC_RESERVED_0
+#define NGDC_RESERVED_0__RESERVED__SHIFT 0x0
+#define NGDC_RESERVED_0__RESERVED_MASK 0xFFFFFFFFL
+//NGDC_RESERVED_1
+#define NGDC_RESERVED_1__RESERVED__SHIFT 0x0
+#define NGDC_RESERVED_1__RESERVED_MASK 0xFFFFFFFFL
+//NGDC_SDP_PORT_CTRL_SOCCLK
+#define NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK__SHIFT 0x0
+#define NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_MASK 0x0000003FL
+//BIF_SDMA0_DOORBELL_RANGE
+#define BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//BIF_SDMA1_DOORBELL_RANGE
+#define BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//BIF_IH_DOORBELL_RANGE
+#define BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define BIF_IH_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define BIF_IH_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//BIF_MMSCH0_DOORBELL_RANGE
+#define BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define BIF_MMSCH0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define BIF_MMSCH0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//BIF_DOORBELL_FENCE_CNTL
+#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT 0x0
+#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE_MASK 0x00000001L
+//S2A_MISC_CNTL
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2
+#define S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK 0x00000001L
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK 0x00000002L
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK 0x00000004L
+#define S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif_rcc_pf_0_BIFDEC2
+//RCC_PF_0_GFXMSIX_VECT0_ADDR_LO
+#define RCC_PF_0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_PF_0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_PF_0_GFXMSIX_VECT0_ADDR_HI
+#define RCC_PF_0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_PF_0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_PF_0_GFXMSIX_VECT0_MSG_DATA
+#define RCC_PF_0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_PF_0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_PF_0_GFXMSIX_VECT0_CONTROL
+#define RCC_PF_0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_PF_0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_PF_0_GFXMSIX_VECT1_ADDR_LO
+#define RCC_PF_0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_PF_0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_PF_0_GFXMSIX_VECT1_ADDR_HI
+#define RCC_PF_0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_PF_0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_PF_0_GFXMSIX_VECT1_MSG_DATA
+#define RCC_PF_0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_PF_0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_PF_0_GFXMSIX_VECT1_CONTROL
+#define RCC_PF_0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_PF_0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_PF_0_GFXMSIX_VECT2_ADDR_LO
+#define RCC_PF_0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_PF_0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_PF_0_GFXMSIX_VECT2_ADDR_HI
+#define RCC_PF_0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_PF_0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_PF_0_GFXMSIX_VECT2_MSG_DATA
+#define RCC_PF_0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_PF_0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_PF_0_GFXMSIX_VECT2_CONTROL
+#define RCC_PF_0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_PF_0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_PF_0_GFXMSIX_PBA
+#define RCC_PF_0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_PF_0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_PF_0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_PF_0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_PF_0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_PF_0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif_gdc_GDCDEC
+//GDC1_NGDC_SDP_PORT_CTRL
+#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0
+#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x0000003FL
+//GDC1_SHUB_REGS_IF_CTL
+#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0
+#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L
+//GDC1_NGDC_RESERVED_0
+#define GDC1_NGDC_RESERVED_0__RESERVED__SHIFT 0x0
+#define GDC1_NGDC_RESERVED_0__RESERVED_MASK 0xFFFFFFFFL
+//GDC1_NGDC_RESERVED_1
+#define GDC1_NGDC_RESERVED_1__RESERVED__SHIFT 0x0
+#define GDC1_NGDC_RESERVED_1__RESERVED_MASK 0xFFFFFFFFL
+//GDC1_NGDC_SDP_PORT_CTRL_SOCCLK
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK__SHIFT 0x0
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_MASK 0x0000003FL
+//GDC1_BIF_SDMA0_DOORBELL_RANGE
+#define GDC1_BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC1_BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC1_BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC1_BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC1_BIF_SDMA1_DOORBELL_RANGE
+#define GDC1_BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC1_BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC1_BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC1_BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC1_BIF_IH_DOORBELL_RANGE
+#define GDC1_BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC1_BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC1_BIF_IH_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC1_BIF_IH_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC1_BIF_MMSCH0_DOORBELL_RANGE
+#define GDC1_BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC1_BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC1_BIF_MMSCH0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC1_BIF_MMSCH0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC1_BIF_DOORBELL_FENCE_CNTL
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT 0x0
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE_MASK 0x00000001L
+//GDC1_S2A_MISC_CNTL
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2
+#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK 0x00000001L
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK 0x00000002L
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK 0x00000004L
+#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif_syshub_mmreg_direct_syshubdirect
+//SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000008L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000010L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000020L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000040L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000080L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00010000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00020000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00040000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00080000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00100000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00200000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00400000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00800000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN_MASK 0x80000000L
+//SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SOCCLK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER_MASK 0x0000FFFFL
+//SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0xf
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x11
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en_MASK 0x00008000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en_MASK 0x00010000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en_MASK 0x00020000L
+//SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0xf
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x11
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en_MASK 0x00008000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en_MASK 0x00010000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en_MASK 0x00020000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L
+//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L
+//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL
+#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER_MASK 0x0000FF00L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER_MASK 0x00FF0000L
+//SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT 0x2
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT 0x3
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT 0x4
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT 0x5
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT 0x6
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT 0x7
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT 0xa
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT 0xb
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT 0xc
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT 0xd
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT 0xe
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT 0xf
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2_MASK 0x00000004L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3_MASK 0x00000008L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4_MASK 0x00000010L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5_MASK 0x00000020L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6_MASK 0x00000040L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7_MASK 0x00000080L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9_MASK 0x00000200L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10_MASK 0x00000400L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11_MASK 0x00000800L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12_MASK 0x00001000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13_MASK 0x00002000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14_MASK 0x00004000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15_MASK 0x00008000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF_MASK 0x00010000L
+//SYSHUB_MMREG_DIRECT_SYSHUB_HP_TIMER
+#define SYSHUB_MMREG_DIRECT_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER_MASK 0xFFFFFFFFL
+//SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK__SHIFT 0x2
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK__SHIFT 0xa
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK__SHIFT 0xb
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REGS_DIS_SOCCLK__SHIFT 0xc
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK__SHIFT 0xd
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK_MASK 0x000003FCL
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK_MASK 0x00000400L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK_MASK 0x00000800L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REGS_DIS_SOCCLK_MASK 0x00001000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK_MASK 0x00002000L
+//SYSHUB_MMREG_DIRECT_SYSHUB_SCRATCH
+#define SYSHUB_MMREG_DIRECT_SYSHUB_SCRATCH__SCRATCH__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
+//SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK__MP1DRAM_MASK_DIS__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK__MP1_MASK_DIS__SHIFT 0x2
+#define SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK__MP1DRAM_MASK_DIS_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK__MP1_MASK_DIS_MASK 0x00000004L
+//SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000008L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000010L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000020L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000040L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000080L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00010000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00020000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00040000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00080000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00100000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00200000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00400000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00800000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN_MASK 0x80000000L
+//SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SHUBCLK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER_MASK 0x0000FFFFL
+//SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT 0xf
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en_MASK 0x00008000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en_MASK 0x00010000L
+//SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT 0xf
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en_MASK 0x00008000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en_MASK 0x00010000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK__SHIFT 0x2
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK__SHIFT 0xa
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK__SHIFT 0xb
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REGS_DIS_SHUBCLK__SHIFT 0xc
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK_MASK 0x000003FCL
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK_MASK 0x00000400L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK_MASK 0x00000800L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REGS_DIS_SHUBCLK_MASK 0x00001000L
+//SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS
+#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS
+#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_2_FN_MOD_BM_ISS
+#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_2_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_2_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_2_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_2_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_3_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_3_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_3_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_3_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_3_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_4_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_4_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_4_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_4_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_4_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS
+#define SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L
+
+
+// addressBlock: nbio_nbif_nbif_sion_SIONDEC
+//SION_CL0_RdRsp_BurstTarget_REG0
+#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_RdRsp_BurstTarget_REG1
+#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_RdRsp_TimeSlot_REG0
+#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_RdRsp_TimeSlot_REG1
+#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_WrRsp_BurstTarget_REG0
+#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_WrRsp_BurstTarget_REG1
+#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_WrRsp_TimeSlot_REG0
+#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_WrRsp_TimeSlot_REG1
+#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_Req_BurstTarget_REG0
+#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_Req_BurstTarget_REG1
+#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_Req_TimeSlot_REG0
+#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_Req_TimeSlot_REG1
+#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_ReqPoolCredit_Alloc_REG0
+#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_ReqPoolCredit_Alloc_REG1
+#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_DataPoolCredit_Alloc_REG0
+#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_DataPoolCredit_Alloc_REG1
+#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_RdRspPoolCredit_Alloc_REG0
+#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_RdRspPoolCredit_Alloc_REG1
+#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_WrRspPoolCredit_Alloc_REG0
+#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_WrRspPoolCredit_Alloc_REG1
+#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_RdRsp_BurstTarget_REG0
+#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_RdRsp_BurstTarget_REG1
+#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_RdRsp_TimeSlot_REG0
+#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_RdRsp_TimeSlot_REG1
+#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_WrRsp_BurstTarget_REG0
+#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_WrRsp_BurstTarget_REG1
+#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_WrRsp_TimeSlot_REG0
+#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_WrRsp_TimeSlot_REG1
+#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_Req_BurstTarget_REG0
+#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_Req_BurstTarget_REG1
+#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_Req_TimeSlot_REG0
+#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_Req_TimeSlot_REG1
+#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_ReqPoolCredit_Alloc_REG0
+#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_ReqPoolCredit_Alloc_REG1
+#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_DataPoolCredit_Alloc_REG0
+#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_DataPoolCredit_Alloc_REG1
+#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_RdRspPoolCredit_Alloc_REG0
+#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_RdRspPoolCredit_Alloc_REG1
+#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_WrRspPoolCredit_Alloc_REG0
+#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_WrRspPoolCredit_Alloc_REG1
+#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_RdRsp_BurstTarget_REG0
+#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_RdRsp_BurstTarget_REG1
+#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_RdRsp_TimeSlot_REG0
+#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_RdRsp_TimeSlot_REG1
+#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_WrRsp_BurstTarget_REG0
+#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_WrRsp_BurstTarget_REG1
+#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_WrRsp_TimeSlot_REG0
+#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_WrRsp_TimeSlot_REG1
+#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_Req_BurstTarget_REG0
+#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_Req_BurstTarget_REG1
+#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_Req_TimeSlot_REG0
+#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_Req_TimeSlot_REG1
+#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_ReqPoolCredit_Alloc_REG0
+#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_ReqPoolCredit_Alloc_REG1
+#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_DataPoolCredit_Alloc_REG0
+#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_DataPoolCredit_Alloc_REG1
+#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_RdRspPoolCredit_Alloc_REG0
+#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_RdRspPoolCredit_Alloc_REG1
+#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_WrRspPoolCredit_Alloc_REG0
+#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_WrRspPoolCredit_Alloc_REG1
+#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_RdRsp_BurstTarget_REG0
+#define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_RdRsp_BurstTarget_REG1
+#define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_RdRsp_TimeSlot_REG0
+#define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_RdRsp_TimeSlot_REG1
+#define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_WrRsp_BurstTarget_REG0
+#define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_WrRsp_BurstTarget_REG1
+#define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_WrRsp_TimeSlot_REG0
+#define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_WrRsp_TimeSlot_REG1
+#define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_Req_BurstTarget_REG0
+#define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_Req_BurstTarget_REG1
+#define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_Req_TimeSlot_REG0
+#define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_Req_TimeSlot_REG1
+#define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_ReqPoolCredit_Alloc_REG0
+#define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_ReqPoolCredit_Alloc_REG1
+#define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_DataPoolCredit_Alloc_REG0
+#define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_DataPoolCredit_Alloc_REG1
+#define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_RdRspPoolCredit_Alloc_REG0
+#define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_RdRspPoolCredit_Alloc_REG1
+#define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_WrRspPoolCredit_Alloc_REG0
+#define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_WrRspPoolCredit_Alloc_REG1
+#define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL4_RdRsp_BurstTarget_REG0
+#define SION_CL4_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL4_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL4_RdRsp_BurstTarget_REG1
+#define SION_CL4_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL4_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL4_RdRsp_TimeSlot_REG0
+#define SION_CL4_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL4_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL4_RdRsp_TimeSlot_REG1
+#define SION_CL4_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL4_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL4_WrRsp_BurstTarget_REG0
+#define SION_CL4_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL4_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL4_WrRsp_BurstTarget_REG1
+#define SION_CL4_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL4_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL4_WrRsp_TimeSlot_REG0
+#define SION_CL4_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL4_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL4_WrRsp_TimeSlot_REG1
+#define SION_CL4_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL4_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL4_Req_BurstTarget_REG0
+#define SION_CL4_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL4_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL4_Req_BurstTarget_REG1
+#define SION_CL4_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL4_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL4_Req_TimeSlot_REG0
+#define SION_CL4_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL4_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL4_Req_TimeSlot_REG1
+#define SION_CL4_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL4_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL4_ReqPoolCredit_Alloc_REG0
+#define SION_CL4_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL4_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL4_ReqPoolCredit_Alloc_REG1
+#define SION_CL4_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL4_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL4_DataPoolCredit_Alloc_REG0
+#define SION_CL4_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL4_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL4_DataPoolCredit_Alloc_REG1
+#define SION_CL4_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL4_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL4_RdRspPoolCredit_Alloc_REG0
+#define SION_CL4_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL4_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL4_RdRspPoolCredit_Alloc_REG1
+#define SION_CL4_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL4_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL4_WrRspPoolCredit_Alloc_REG0
+#define SION_CL4_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL4_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL4_WrRspPoolCredit_Alloc_REG1
+#define SION_CL4_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL4_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL5_RdRsp_BurstTarget_REG0
+#define SION_CL5_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL5_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL5_RdRsp_BurstTarget_REG1
+#define SION_CL5_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL5_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL5_RdRsp_TimeSlot_REG0
+#define SION_CL5_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL5_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL5_RdRsp_TimeSlot_REG1
+#define SION_CL5_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL5_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL5_WrRsp_BurstTarget_REG0
+#define SION_CL5_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL5_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL5_WrRsp_BurstTarget_REG1
+#define SION_CL5_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL5_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL5_WrRsp_TimeSlot_REG0
+#define SION_CL5_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL5_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL5_WrRsp_TimeSlot_REG1
+#define SION_CL5_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL5_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL5_Req_BurstTarget_REG0
+#define SION_CL5_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL5_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL5_Req_BurstTarget_REG1
+#define SION_CL5_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL5_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL5_Req_TimeSlot_REG0
+#define SION_CL5_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL5_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL5_Req_TimeSlot_REG1
+#define SION_CL5_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL5_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL5_ReqPoolCredit_Alloc_REG0
+#define SION_CL5_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL5_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL5_ReqPoolCredit_Alloc_REG1
+#define SION_CL5_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL5_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL5_DataPoolCredit_Alloc_REG0
+#define SION_CL5_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL5_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL5_DataPoolCredit_Alloc_REG1
+#define SION_CL5_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL5_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL5_RdRspPoolCredit_Alloc_REG0
+#define SION_CL5_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL5_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL5_RdRspPoolCredit_Alloc_REG1
+#define SION_CL5_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL5_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL5_WrRspPoolCredit_Alloc_REG0
+#define SION_CL5_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL5_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL5_WrRspPoolCredit_Alloc_REG1
+#define SION_CL5_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL5_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CNTL_REG0
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK 0x00000400L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK 0x00000800L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK 0x00001000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK 0x00002000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK 0x00004000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK 0x00008000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK 0x00010000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK 0x00020000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK 0x00040000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK 0x00080000L
+//SION_CNTL_REG1
+#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0
+#define SION_CNTL_REG1__CG_OFF_HYSTERESIS__SHIFT 0x8
+#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD_MASK 0x000000FFL
+#define SION_CNTL_REG1__CG_OFF_HYSTERESIS_MASK 0x0000FF00L
+
+
+// addressBlock: nbio_nbif_gdc_rst_GDCRST_DEC
+//SHUB_PF_FLR_RST
+#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0
+#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1
+#define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2
+#define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3
+#define SHUB_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x4
+#define SHUB_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x5
+#define SHUB_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x6
+#define SHUB_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT 0x7
+#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L
+#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L
+#define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK 0x00000004L
+#define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK 0x00000008L
+#define SHUB_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK 0x00000010L
+#define SHUB_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK 0x00000020L
+#define SHUB_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK 0x00000040L
+#define SHUB_PF_FLR_RST__DEV0_PF7_FLR_RST_MASK 0x00000080L
+//SHUB_GFX_DRV_VPU_RST
+#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST__SHIFT 0x0
+#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST_MASK 0x00000001L
+//SHUB_LINK_RESET
+#define SHUB_LINK_RESET__LINK_RESET__SHIFT 0x0
+#define SHUB_LINK_RESET__LINK_RESET_MASK 0x00000001L
+//SHUB_PF0_VF_FLR_RST
+#define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x0
+#define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x1
+#define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x2
+#define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x3
+#define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x4
+#define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x5
+#define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x6
+#define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x7
+#define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x8
+#define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x9
+#define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0xa
+#define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0xb
+#define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0xc
+#define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0xd
+#define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0xe
+#define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0xf
+#define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x1f
+#define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST_MASK 0x00000001L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST_MASK 0x00000002L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST_MASK 0x00000004L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST_MASK 0x00000008L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST_MASK 0x00000010L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST_MASK 0x00000020L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST_MASK 0x00000040L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST_MASK 0x00000080L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST_MASK 0x00000100L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST_MASK 0x00000200L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST_MASK 0x00000400L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST_MASK 0x00000800L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST_MASK 0x00001000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST_MASK 0x00002000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST_MASK 0x00004000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST_MASK 0x00008000L
+#define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST_MASK 0x80000000L
+//SHUB_HARD_RST_CTRL
+#define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT 0x0
+#define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT 0x1
+#define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT 0x2
+#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3
+#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4
+#define SHUB_HARD_RST_CTRL__COR_RESET_EN_MASK 0x00000001L
+#define SHUB_HARD_RST_CTRL__REG_RESET_EN_MASK 0x00000002L
+#define SHUB_HARD_RST_CTRL__STY_RESET_EN_MASK 0x00000004L
+#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L
+#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L
+//SHUB_SOFT_RST_CTRL
+#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT 0x0
+#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT 0x1
+#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT 0x2
+#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3
+#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4
+#define SHUB_SOFT_RST_CTRL__COR_RESET_EN_MASK 0x00000001L
+#define SHUB_SOFT_RST_CTRL__REG_RESET_EN_MASK 0x00000002L
+#define SHUB_SOFT_RST_CTRL__STY_RESET_EN_MASK 0x00000004L
+#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L
+#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L
+//SHUB_SDP_PORT_RST
+#define SHUB_SDP_PORT_RST__SDP_PORT_RST__SHIFT 0x0
+#define SHUB_SDP_PORT_RST__SDP_PORT_RST_MASK 0x00000001L
+//SHUB_RST_MISC_TRL
+#define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_ATOMIC__SHIFT 0x0
+#define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_CYCLE__SHIFT 0x10
+#define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_ATOMIC_MASK 0x00000001L
+#define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_CYCLE_MASK 0x00FF0000L
+
+
+// addressBlock: nbio_nbif_gdc_ras_gdc_ras_regblk
+//GDC_RAS_LEAF0_CTRL
+#define GDC_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x0
+#define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x15
+#define GDC_RAS_LEAF0_CTRL__POISON_DET_EN_MASK 0x00000001L
+#define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN_MASK 0x00000010L
+#define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L
+#define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK 0x00000040L
+#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV_MASK 0x00010000L
+#define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV_MASK 0x00020000L
+#define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET_MASK 0x00040000L
+#define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET_MASK 0x00080000L
+#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT_MASK 0x00100000L
+#define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED_MASK 0x00200000L
+//GDC_RAS_LEAF1_CTRL
+#define GDC_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x0
+#define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x15
+#define GDC_RAS_LEAF1_CTRL__POISON_DET_EN_MASK 0x00000001L
+#define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN_MASK 0x00000010L
+#define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L
+#define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK 0x00000040L
+#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV_MASK 0x00010000L
+#define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV_MASK 0x00020000L
+#define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET_MASK 0x00040000L
+#define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET_MASK 0x00080000L
+#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT_MASK 0x00100000L
+#define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED_MASK 0x00200000L
+//GDC_RAS_LEAF2_CTRL
+#define GDC_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x0
+#define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x15
+#define GDC_RAS_LEAF2_CTRL__POISON_DET_EN_MASK 0x00000001L
+#define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN_MASK 0x00000010L
+#define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L
+#define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK 0x00000040L
+#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV_MASK 0x00010000L
+#define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV_MASK 0x00020000L
+#define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET_MASK 0x00040000L
+#define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET_MASK 0x00080000L
+#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT_MASK 0x00100000L
+#define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED_MASK 0x00200000L
+//GDC_RAS_LEAF3_CTRL
+#define GDC_RAS_LEAF3_CTRL__POISON_DET_EN__SHIFT 0x0
+#define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED__SHIFT 0x15
+#define GDC_RAS_LEAF3_CTRL__POISON_DET_EN_MASK 0x00000001L
+#define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN_MASK 0x00000010L
+#define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L
+#define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN_MASK 0x00000040L
+#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV_MASK 0x00010000L
+#define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV_MASK 0x00020000L
+#define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET_MASK 0x00040000L
+#define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET_MASK 0x00080000L
+#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT_MASK 0x00100000L
+#define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED_MASK 0x00200000L
+//GDC_RAS_LEAF4_CTRL
+#define GDC_RAS_LEAF4_CTRL__POISON_DET_EN__SHIFT 0x0
+#define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED__SHIFT 0x15
+#define GDC_RAS_LEAF4_CTRL__POISON_DET_EN_MASK 0x00000001L
+#define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN_MASK 0x00000010L
+#define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L
+#define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN_MASK 0x00000040L
+#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV_MASK 0x00010000L
+#define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV_MASK 0x00020000L
+#define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET_MASK 0x00040000L
+#define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET_MASK 0x00080000L
+#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT_MASK 0x00100000L
+#define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED_MASK 0x00200000L
+//GDC_RAS_LEAF5_CTRL
+#define GDC_RAS_LEAF5_CTRL__POISON_DET_EN__SHIFT 0x0
+#define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED__SHIFT 0x15
+#define GDC_RAS_LEAF5_CTRL__POISON_DET_EN_MASK 0x00000001L
+#define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN_MASK 0x00000010L
+#define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L
+#define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN_MASK 0x00000040L
+#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV_MASK 0x00010000L
+#define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV_MASK 0x00020000L
+#define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET_MASK 0x00040000L
+#define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET_MASK 0x00080000L
+#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT_MASK 0x00100000L
+#define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED_MASK 0x00200000L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_swds_bifcfgdecp
+//BIF_CFG_DEV0_SWDS1_VENDOR_ID
+#define BIF_CFG_DEV0_SWDS1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS1_DEVICE_ID
+#define BIF_CFG_DEV0_SWDS1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS1_COMMAND
+#define BIF_CFG_DEV0_SWDS1_COMMAND__IOEN_DN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_COMMAND__MEMEN_DN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_COMMAND__IOEN_DN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_COMMAND__MEMEN_DN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_SWDS1_STATUS
+#define BIF_CFG_DEV0_SWDS1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_SWDS1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_SWDS1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_SWDS1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_SWDS1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_REVISION_ID
+#define BIF_CFG_DEV0_SWDS1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS1_PROG_INTERFACE
+#define BIF_CFG_DEV0_SWDS1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS1_SUB_CLASS
+#define BIF_CFG_DEV0_SWDS1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS1_BASE_CLASS
+#define BIF_CFG_DEV0_SWDS1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS1_CACHE_LINE
+#define BIF_CFG_DEV0_SWDS1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS1_LATENCY
+#define BIF_CFG_DEV0_SWDS1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS1_HEADER
+#define BIF_CFG_DEV0_SWDS1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_SWDS1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_SWDS1_BIST
+#define BIF_CFG_DEV0_SWDS1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_SWDS1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_SWDS1_BASE_ADDR_1
+#define BIF_CFG_DEV0_SWDS1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT
+#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT
+#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER
+#define BIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_SWDS1_CAP_PTR
+#define BIF_CFG_DEV0_SWDS1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_SWDS1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_SWDS1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_SWDS1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_PMI_CAP
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_PCIE_CAP
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_SWDS1_DEVICE_CAP
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_SWDS1_DEVICE_CNTL
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_DEVICE_STATUS
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_SWDS1_LINK_CAP
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS1_LINK_CNTL
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_SWDS1_LINK_STATUS
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_SLOT_CAP
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIF_CFG_DEV0_SWDS1_SLOT_CNTL
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+//BIF_CFG_DEV0_SWDS1_SLOT_STATUS
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIF_CFG_DEV0_SWDS1_DEVICE_CAP2
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS1_LINK_CAP2
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_SWDS1_LINK_CNTL2
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_SWDS1_LINK_STATUS2
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_SWDS1_SLOT_CAP2
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_SLOT_CNTL2
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS1_SLOT_STATUS2
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_SSID_CAP
+#define BIF_CFG_DEV0_SWDS1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_SYSPFVFDEC
+//BIF_BX_PF3_MM_INDEX
+#define BIF_BX_PF3_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_PF3_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_PF3_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_PF3_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_PF3_MM_DATA
+#define BIF_BX_PF3_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_PF3_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF3_MM_INDEX_HI
+#define BIF_BX_PF3_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_PF3_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_SYSDEC
+//BIF_BX_PF1_SYSHUB_INDEX_OVLP
+#define BIF_BX_PF1_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0
+#define BIF_BX_PF1_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK 0x003FFFFFL
+//BIF_BX_PF1_SYSHUB_DATA_OVLP
+#define BIF_BX_PF1_SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0
+#define BIF_BX_PF1_SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_PCIE_INDEX
+#define BIF_BX_PF1_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
+#define BIF_BX_PF1_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_PCIE_DATA
+#define BIF_BX_PF1_PCIE_DATA__PCIE_DATA__SHIFT 0x0
+#define BIF_BX_PF1_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_PCIE_INDEX2
+#define BIF_BX_PF1_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0
+#define BIF_BX_PF1_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_PCIE_DATA2
+#define BIF_BX_PF1_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0
+#define BIF_BX_PF1_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_SBIOS_SCRATCH_0
+#define BIF_BX_PF1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX_PF1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_SBIOS_SCRATCH_1
+#define BIF_BX_PF1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX_PF1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_SBIOS_SCRATCH_2
+#define BIF_BX_PF1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX_PF1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_SBIOS_SCRATCH_3
+#define BIF_BX_PF1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX_PF1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_0
+#define BIF_BX_PF1_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_1
+#define BIF_BX_PF1_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_2
+#define BIF_BX_PF1_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_3
+#define BIF_BX_PF1_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_4
+#define BIF_BX_PF1_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_5
+#define BIF_BX_PF1_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_6
+#define BIF_BX_PF1_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_7
+#define BIF_BX_PF1_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_8
+#define BIF_BX_PF1_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_9
+#define BIF_BX_PF1_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_10
+#define BIF_BX_PF1_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_11
+#define BIF_BX_PF1_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_12
+#define BIF_BX_PF1_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_13
+#define BIF_BX_PF1_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_14
+#define BIF_BX_PF1_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_15
+#define BIF_BX_PF1_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIF_RLC_INTR_CNTL
+#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0
+#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK 0x00000008L
+//BIF_BX_PF1_BIF_VCE_INTR_CNTL
+#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0
+#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK 0x00000008L
+//BIF_BX_PF1_BIF_UVD_INTR_CNTL
+#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0
+#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK 0x00000008L
+//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_CNTL
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_rcc_strap_BIFDEC1
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif_rcc_pf_0_BIFPFVFDEC1
+//RCC_PF_0_1_RCC_ERR_LOG
+#define RCC_PF_0_1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_PF_0_1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_PF_0_1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_PF_0_1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_PF_0_1_RCC_DOORBELL_APER_EN
+#define RCC_PF_0_1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_PF_0_1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_PF_0_1_RCC_CONFIG_MEMSIZE
+#define RCC_PF_0_1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_PF_0_1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_PF_0_1_RCC_CONFIG_RESERVED
+#define RCC_PF_0_1_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_PF_0_1_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_PF_0_1_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_PF_0_1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_PF_0_1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_PF_0_1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_PF_0_1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_BIFDEC1
+//BIF_BX_PF1_BIF_MM_INDACCESS_CNTL
+#define BIF_BX_PF1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
+#define BIF_BX_PF1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L
+//BIF_BX_PF1_BUS_CNTL
+#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_EP__SHIFT 0x3
+#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_DN__SHIFT 0x4
+#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x5
+#define BIF_BX_PF1_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
+#define BIF_BX_PF1_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
+#define BIF_BX_PF1_BUS_CNTL__SET_AZ_TC__SHIFT 0xa
+#define BIF_BX_PF1_BUS_CNTL__SET_MC_TC__SHIFT 0xd
+#define BIF_BX_PF1_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
+#define BIF_BX_PF1_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
+#define BIF_BX_PF1_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
+#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x13
+#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x14
+#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x15
+#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x16
+#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x17
+#define BIF_BX_PF1_BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x18
+#define BIF_BX_PF1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19
+#define BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT 0x1b
+#define BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT 0x1c
+#define BIF_BX_PF1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d
+#define BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_EP_MASK 0x00000008L
+#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_DN_MASK 0x00000010L
+#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000020L
+#define BIF_BX_PF1_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L
+#define BIF_BX_PF1_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L
+#define BIF_BX_PF1_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L
+#define BIF_BX_PF1_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L
+#define BIF_BX_PF1_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L
+#define BIF_BX_PF1_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L
+#define BIF_BX_PF1_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L
+#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00080000L
+#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00100000L
+#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00200000L
+#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00400000L
+#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00800000L
+#define BIF_BX_PF1_BUS_CNTL__UR_OVRD_FOR_ECRC_EN_MASK 0x01000000L
+#define BIF_BX_PF1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L
+#define BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK 0x08000000L
+#define BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK 0x10000000L
+#define BIF_BX_PF1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L
+#define BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_SCRATCH0
+#define BIF_BX_PF1_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
+#define BIF_BX_PF1_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIF_SCRATCH1
+#define BIF_BX_PF1_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
+#define BIF_BX_PF1_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BX_RESET_EN
+#define BIF_BX_PF1_BX_RESET_EN__COR_RESET_EN__SHIFT 0x0
+#define BIF_BX_PF1_BX_RESET_EN__REG_RESET_EN__SHIFT 0x1
+#define BIF_BX_PF1_BX_RESET_EN__STY_RESET_EN__SHIFT 0x2
+#define BIF_BX_PF1_BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8
+#define BIF_BX_PF1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10
+#define BIF_BX_PF1_BX_RESET_EN__COR_RESET_EN_MASK 0x00000001L
+#define BIF_BX_PF1_BX_RESET_EN__REG_RESET_EN_MASK 0x00000002L
+#define BIF_BX_PF1_BX_RESET_EN__STY_RESET_EN_MASK 0x00000004L
+#define BIF_BX_PF1_BX_RESET_EN__FLR_TWICE_EN_MASK 0x00000100L
+#define BIF_BX_PF1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L
+//BIF_BX_PF1_MM_CFGREGS_CNTL
+#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
+#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6
+#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f
+#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L
+#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L
+#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L
+//BIF_BX_PF1_BX_RESET_CNTL
+#define BIF_BX_PF1_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0
+#define BIF_BX_PF1_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L
+//BIF_BX_PF1_INTERRUPT_CNTL
+#define BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
+#define BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
+#define BIF_BX_PF1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
+#define BIF_BX_PF1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
+#define BIF_BX_PF1_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
+#define BIF_BX_PF1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
+#define BIF_BX_PF1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10
+#define BIF_BX_PF1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11
+#define BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L
+#define BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L
+#define BIF_BX_PF1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L
+#define BIF_BX_PF1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L
+#define BIF_BX_PF1_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L
+#define BIF_BX_PF1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L
+#define BIF_BX_PF1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L
+#define BIF_BX_PF1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L
+//BIF_BX_PF1_INTERRUPT_CNTL2
+#define BIF_BX_PF1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
+#define BIF_BX_PF1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_CLKREQB_PAD_CNTL
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L
+//BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK 0x00020000L
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK 0x00040000L
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x01000000L
+//BIF_BX_PF1_BIF_DOORBELL_CNTL
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L
+//BIF_BX_PF1_BIF_DOORBELL_INT_CNTL
+#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0
+#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT 0x1
+#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
+#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT 0x11
+#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L
+#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR_MASK 0x00020000L
+//BIF_BX_PF1_BIF_FB_EN
+#define BIF_BX_PF1_BIF_FB_EN__FB_READ_EN__SHIFT 0x0
+#define BIF_BX_PF1_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
+#define BIF_BX_PF1_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L
+//BIF_BX_PF1_BIF_BUSY_DELAY_CNTR
+#define BIF_BX_PF1_BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0
+#define BIF_BX_PF1_BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x0000003FL
+//BIF_BX_PF1_BIF_MST_TRANS_PENDING_VF
+#define BIF_BX_PF1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_PF1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x0000FFFFL
+//BIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF
+#define BIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x0000FFFFL
+//BIF_BX_PF1_BACO_CNTL
+#define BIF_BX_PF1_BACO_CNTL__BACO_EN__SHIFT 0x0
+#define BIF_BX_PF1_BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x1
+#define BIF_BX_PF1_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2
+#define BIF_BX_PF1_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3
+#define BIF_BX_PF1_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5
+#define BIF_BX_PF1_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6
+#define BIF_BX_PF1_BACO_CNTL__BACO_MODE__SHIFT 0x8
+#define BIF_BX_PF1_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9
+#define BIF_BX_PF1_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f
+#define BIF_BX_PF1_BACO_CNTL__BACO_EN_MASK 0x00000001L
+#define BIF_BX_PF1_BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK 0x00000002L
+#define BIF_BX_PF1_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L
+#define BIF_BX_PF1_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L
+#define BIF_BX_PF1_BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L
+#define BIF_BX_PF1_BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L
+#define BIF_BX_PF1_BACO_CNTL__BACO_MODE_MASK 0x00000100L
+#define BIF_BX_PF1_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L
+#define BIF_BX_PF1_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L
+//BIF_BX_PF1_BIF_BACO_EXIT_TIME0
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BX_PF1_BIF_BACO_EXIT_TIMER1
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR__SHIFT 0x19
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR_MASK 0x02000000L
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L
+//BIF_BX_PF1_BIF_BACO_EXIT_TIMER2
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL
+//BIF_BX_PF1_BIF_BACO_EXIT_TIMER3
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BX_PF1_BIF_BACO_EXIT_TIMER4
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BX_PF1_MEM_TYPE_CNTL
+#define BIF_BX_PF1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0
+#define BIF_BX_PF1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L
+//BIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS
+#define BIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0
+#define BIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x00000001L
+//BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER
+#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER
+#define BIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER
+#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER
+#define BIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER
+#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER
+#define BIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER
+#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER
+#define BIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_VDDGFX_FB_CMP
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x00000004L
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x00000008L
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x00000010L
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x00000020L
+//BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0x00000FFCL
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0x00000FFCL
+//BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0x00000FFCL
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0x00000FFCL
+//BIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL
+#define BIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define BIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//BIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL
+#define BIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define BIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//BIF_BX_PF1_BIF_RB_CNTL
+#define BIF_BX_PF1_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define BIF_BX_PF1_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
+#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
+#define BIF_BX_PF1_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11
+#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L
+#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L
+#define BIF_BX_PF1_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L
+#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
+//BIF_BX_PF1_BIF_RB_BASE
+#define BIF_BX_PF1_BIF_RB_BASE__ADDR__SHIFT 0x0
+#define BIF_BX_PF1_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIF_RB_RPTR
+#define BIF_BX_PF1_BIF_RB_RPTR__OFFSET__SHIFT 0x2
+#define BIF_BX_PF1_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_RB_WPTR
+#define BIF_BX_PF1_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0
+#define BIF_BX_PF1_BIF_RB_WPTR__OFFSET__SHIFT 0x2
+#define BIF_BX_PF1_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_RB_WPTR_ADDR_HI
+#define BIF_BX_PF1_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define BIF_BX_PF1_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL
+//BIF_BX_PF1_BIF_RB_WPTR_ADDR_LO
+#define BIF_BX_PF1_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define BIF_BX_PF1_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//BIF_BX_PF1_MAILBOX_INDEX
+#define BIF_BX_PF1_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL
+//BIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE
+#define BIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE
+#define BIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE
+#define BIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_BX_PF1_BIF_PERSTB_PAD_CNTL
+#define BIF_BX_PF1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0
+#define BIF_BX_PF1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL
+//BIF_BX_PF1_BIF_PX_EN_PAD_CNTL
+#define BIF_BX_PF1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0
+#define BIF_BX_PF1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x000000FFL
+//BIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL
+#define BIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0
+#define BIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL
+//BIF_BX_PF1_BIF_CLKREQB_PAD_CNTL
+#define BIF_BX_PF1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0
+#define BIF_BX_PF1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x00FFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_BIFPFVFDEC1
+//BIF_BX_PF1_BIF_BME_STATUS
+#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_PF1_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_PF1_GPU_HDP_FLUSH_REQ
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_PF1_GPU_HDP_FLUSH_DONE
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_PF1_BIF_TRANS_PENDING
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_CONTROL
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_PF1_MAILBOX_INT_CNTL
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_PF1_BIF_VMHV_MAILBOX
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif_rcc_shadow_reg_shadowdec
+//SHADOW_COMMAND
+#define SHADOW_COMMAND__IOEN_UP__SHIFT 0x0
+#define SHADOW_COMMAND__MEMEN_UP__SHIFT 0x1
+#define SHADOW_COMMAND__IOEN_UP_MASK 0x0001L
+#define SHADOW_COMMAND__MEMEN_UP_MASK 0x0002L
+//SHADOW_BASE_ADDR_1
+#define SHADOW_BASE_ADDR_1__BAR1_UP__SHIFT 0x0
+#define SHADOW_BASE_ADDR_1__BAR1_UP_MASK 0xFFFFFFFFL
+//SHADOW_BASE_ADDR_2
+#define SHADOW_BASE_ADDR_2__BAR2_UP__SHIFT 0x0
+#define SHADOW_BASE_ADDR_2__BAR2_UP_MASK 0xFFFFFFFFL
+//SHADOW_SUB_BUS_NUMBER_LATENCY
+#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__SHIFT 0x8
+#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__SHIFT 0x10
+#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP_MASK 0x0000FF00L
+#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP_MASK 0x00FF0000L
+//SHADOW_IO_BASE_LIMIT
+#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__SHIFT 0x4
+#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__SHIFT 0xc
+#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP_MASK 0x00F0L
+#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP_MASK 0xF000L
+//SHADOW_MEM_BASE_LIMIT
+#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__SHIFT 0x4
+#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__SHIFT 0x14
+#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP_MASK 0x0000FFF0L
+#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP_MASK 0xFFF00000L
+//SHADOW_PREF_BASE_LIMIT
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__SHIFT 0x4
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__SHIFT 0x14
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP_MASK 0x0000FFF0L
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP_MASK 0xFFF00000L
+//SHADOW_PREF_BASE_UPPER
+#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__SHIFT 0x0
+#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP_MASK 0xFFFFFFFFL
+//SHADOW_PREF_LIMIT_UPPER
+#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__SHIFT 0x0
+#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP_MASK 0xFFFFFFFFL
+//SHADOW_IO_BASE_LIMIT_HI
+#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__SHIFT 0x0
+#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__SHIFT 0x10
+#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP_MASK 0x0000FFFFL
+#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP_MASK 0xFFFF0000L
+//SHADOW_IRQ_BRIDGE_CNTL
+#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__SHIFT 0x2
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__SHIFT 0x3
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__SHIFT 0x4
+#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__SHIFT 0x6
+#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP_MASK 0x0004L
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP_MASK 0x0008L
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP_MASK 0x0010L
+#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP_MASK 0x0040L
+//SUC_INDEX
+#define SUC_INDEX__SUC_INDEX__SHIFT 0x0
+#define SUC_INDEX__SUC_INDEX_MASK 0xFFFFFFFFL
+//SUC_DATA
+#define SUC_DATA__SUC_DATA__SHIFT 0x0
+#define SUC_DATA__SUC_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_rcc_ep_dev0_RCCPORTDEC
+//RCC_EP_DEV0_1_EP_PCIE_SCRATCH
+#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_1_EP_PCIE_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_EP_DEV0_1_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L
+//RCC_EP_DEV0_1_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L
+//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+//RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+//RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+//RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L
+//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL
+//RCC_EP_DEV0_1_EP_PCIEP_RESERVED
+#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_1_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L
+//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+
+
+// addressBlock: nbio_nbif_rcc_dwn_dev0_RCCPORTDEC
+//RCC_DWN_DEV0_1_DN_PCIE_RESERVED
+#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_1_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_1_DN_PCIE_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+//RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L
+//RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif_rcc_dwnp_dev0_RCCPORTDEC
+//RCC_DWNP_DEV0_1_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+//RCC_DWNP_DEV0_1_PCIE_RX_CNTL
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+//RCC_DWNP_DEV0_1_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
+#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L
+//RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0
+#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_rcc_strap_rcc_strap_internal
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif_bif_bx_pf_SUMDEC
+//SUM_INDEX
+#define SUM_INDEX__SUM_INDEX__SHIFT 0x0
+#define SUM_INDEX__SUM_INDEX_MASK 0xFFFFFFFFL
+//SUM_DATA
+#define SUM_DATA__SUM_DATA__SHIFT 0x0
+#define SUM_DATA__SUM_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_misc_bif_misc_regblk
+//MISC_SCRATCH
+#define MISC_SCRATCH__MISC_SCRATCH0__SHIFT 0x0
+#define MISC_SCRATCH__MISC_SCRATCH0_MASK 0xFFFFFFFFL
+//INTR_LINE_POLARITY
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT 0x0
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK 0x000000FFL
+//INTR_LINE_ENABLE
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT 0x0
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK 0x000000FFL
+//OUTSTANDING_VC_ALLOC
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT 0x0
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT 0x2
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT 0x4
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT 0x6
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT 0x8
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT 0xa
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT 0xc
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT 0xe
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT 0x10
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT 0x18
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT 0x1a
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT 0x1c
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK 0x00000003L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK 0x0000000CL
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK 0x00000030L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK 0x000000C0L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK 0x00000300L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK 0x00000C00L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK 0x00003000L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK 0x0000C000L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK 0x000F0000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK 0x03000000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK 0x0C000000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK 0xF0000000L
+//BIFC_MISC_CTRL0
+#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT 0x0
+#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT 0x1
+#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT 0x8
+#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__SHIFT 0x9
+#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT 0xa
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT 0x10
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT 0x11
+#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT 0x12
+#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT 0x13
+#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT 0x14
+#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT 0x18
+#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__SHIFT 0x19
+#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT 0x1a
+#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT 0x1b
+#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT 0x1c
+#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT 0x1f
+#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN_MASK 0x00000001L
+#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN_MASK 0x00000006L
+#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK 0x00000100L
+#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_MASK 0x00000200L
+#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK_MASK 0x00000400L
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK 0x00010000L
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK 0x00020000L
+#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK 0x00040000L
+#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK 0x00080000L
+#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK 0x00100000L
+#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK 0x01000000L
+#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS_MASK 0x02000000L
+#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK 0x04000000L
+#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK 0x08000000L
+#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK 0x10000000L
+#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK 0x80000000L
+//BIFC_MISC_CTRL1
+#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT 0x0
+#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT 0x1
+#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT 0x2
+#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT 0x3
+#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT 0x4
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT 0x5
+#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT 0x6
+#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT 0x7
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT 0x8
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT 0xa
+#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT 0xc
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT 0xd
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT 0xe
+#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT 0xf
+#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT 0x10
+#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT 0x11
+#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT 0x12
+#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT 0x13
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT 0x14
+#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT 0x18
+#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT 0x19
+#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT 0x1a
+#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT 0x1b
+#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT 0x1c
+#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK 0x00000001L
+#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK 0x00000002L
+#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK 0x00000004L
+#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK 0x00000008L
+#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK 0x00000010L
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK 0x00000020L
+#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK 0x00000040L
+#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK 0x00000080L
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK 0x00000300L
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK 0x00000C00L
+#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK 0x00001000L
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK 0x00002000L
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK 0x00004000L
+#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK 0x00008000L
+#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK 0x00010000L
+#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK 0x00020000L
+#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK 0x00040000L
+#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK 0x00080000L
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK 0x00100000L
+#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK 0x01000000L
+#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK 0x02000000L
+#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK 0x04000000L
+#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK 0x08000000L
+#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK 0x10000000L
+//BIFC_BME_ERR_LOG
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x0
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x1
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x2
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x3
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x4
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x5
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x6
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x7
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x10
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x11
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x12
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x13
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x14
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x15
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x16
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x17
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0_MASK 0x00000001L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1_MASK 0x00000002L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2_MASK 0x00000004L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3_MASK 0x00000008L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4_MASK 0x00000010L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5_MASK 0x00000020L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6_MASK 0x00000040L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7_MASK 0x00000080L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK 0x00010000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1_MASK 0x00020000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2_MASK 0x00040000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3_MASK 0x00080000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4_MASK 0x00100000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5_MASK 0x00200000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6_MASK 0x00400000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7_MASK 0x00800000L
+//BIFC_RCCBIH_BME_ERR_LOG
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x0
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x1
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x2
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x3
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x4
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x5
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x6
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x7
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x10
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x11
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x12
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x13
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x14
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x15
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x16
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x17
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00000001L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00000002L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00000004L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00000008L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4_MASK 0x00000010L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5_MASK 0x00000020L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6_MASK 0x00000040L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7_MASK 0x00000080L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00010000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00020000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00040000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00080000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4_MASK 0x00100000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5_MASK 0x00200000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6_MASK 0x00400000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7_MASK 0x00800000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK 0x30000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK 0x30000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK 0x30000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK 0x30000000L
+//NBIF_VWIRE_CTRL
+#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT 0x4
+#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT 0x8
+#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT 0x14
+#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT 0x1a
+#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK 0x000000F0L
+#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK 0x00000100L
+#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK 0x00F00000L
+#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK 0x0C000000L
+//NBIF_SMN_VWR_VCHG_DIS_CTRL
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS_MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS_MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS_MASK 0x00000004L
+//NBIF_SMN_VWR_VCHG_RST_CTRL0
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV_MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV_MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV_MASK 0x00000004L
+//NBIF_SMN_VWR_VCHG_TRIG
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG_MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG_MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG_MASK 0x00000004L
+//NBIF_SMN_VWR_WTRIG_CNTL
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT 0x0
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT 0x1
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT 0x2
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS_MASK 0x00000001L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS_MASK 0x00000002L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS_MASK 0x00000004L
+//NBIF_SMN_VWR_VCHG_DIS_CTRL_1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV_MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV_MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV_MASK 0x00000004L
+//NBIF_MGCG_CTRL_LCLK
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT 0x0
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT 0x1
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT 0x2
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT 0xa
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT 0xb
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REGS_DIS_LCLK__SHIFT 0xc
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT 0xd
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK 0x00000001L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK 0x00000002L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK 0x000003FCL
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK 0x00000400L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK 0x00000800L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REGS_DIS_LCLK_MASK 0x00001000L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK 0x00002000L
+//NBIF_DS_CTRL_LCLK
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT 0x0
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT 0x10
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK 0x00000001L
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK 0xFFFF0000L
+//SMN_MST_CNTL0
+#define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT 0x0
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT 0x8
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT 0x9
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT 0xa
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT 0xb
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT 0x10
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT 0x14
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT 0x18
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT 0x1c
+#define SMN_MST_CNTL0__SMN_ARB_MODE_MASK 0x00000003L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK 0x00000100L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK 0x00000200L
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK 0x00000400L
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK 0x00000800L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK 0x00010000L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK 0x00100000L
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK 0x01000000L
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK 0x10000000L
+//SMN_MST_EP_CNTL1
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK 0x00000080L
+//SMN_MST_EP_CNTL2
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK 0x00000080L
+//NBIF_SDP_VWR_VCHG_DIS_CTRL
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT 0x18
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK 0x01000000L
+//NBIF_SDP_VWR_VCHG_RST_CTRL0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT 0x18
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK 0x01000000L
+//NBIF_SDP_VWR_VCHG_RST_CTRL1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT 0x18
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK 0x01000000L
+//NBIF_SDP_VWR_VCHG_TRIG
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT 0x18
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK 0x01000000L
+//BME_DUMMY_CNTL_0
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT 0x0
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT 0x2
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT 0x4
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT 0x6
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT 0x8
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT 0xa
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT 0xc
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT 0xe
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK 0x00000003L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK 0x0000000CL
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK 0x00000030L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK 0x000000C0L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK 0x00000300L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK 0x00000C00L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK 0x00003000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK 0x0000C000L
+//BIFC_THT_CNTL
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT 0x0
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT 0x4
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT 0x8
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0_MASK 0x0000000FL
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0_MASK 0x000000F0L
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1_MASK 0x00000F00L
+//BIFC_HSTARB_CNTL
+#define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT 0x0
+#define BIFC_HSTARB_CNTL__SLVARB_MODE_MASK 0x00000003L
+//BIFC_GSI_CNTL
+#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT 0x0
+#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT 0x2
+#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT 0x5
+#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT 0x6
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT 0x7
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT 0x8
+#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT 0x9
+#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT 0xa
+#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT 0xc
+#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK 0x00000003L
+#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK 0x0000001CL
+#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK 0x00000020L
+#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK 0x00000040L
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK 0x00000080L
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK 0x00000100L
+#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN_MASK 0x00000200L
+#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK 0x00000C00L
+#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK 0x00003000L
+//BIFC_PCIEFUNC_CNTL
+#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT 0x0
+#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT 0x10
+#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK 0x0000FFFFL
+#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_MASK 0x00010000L
+//BIFC_SDP_CNTL_0
+#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT 0x0
+#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT 0x8
+#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT 0x10
+#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT 0x18
+#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK 0x000000FFL
+#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK 0x0000FF00L
+#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK 0x00FF0000L
+#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK 0xFF000000L
+//BIFC_SDP_CNTL_1
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT 0x0
+#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT 0x1
+#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT 0x2
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT 0x3
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x4
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x7
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK 0x00000001L
+#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK 0x00000002L
+#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK 0x00000004L
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK 0x00000008L
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000010L
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000080L
+//BIFC_PERF_CNTL_0
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT 0x0
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT 0x1
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT 0x8
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT 0x9
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT 0x10
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT 0x18
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK 0x00000001L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK 0x00000002L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK 0x00000100L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK 0x00000200L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK 0x001F0000L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK 0x1F000000L
+//BIFC_PERF_CNTL_1
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT 0x0
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT 0x1
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT 0x8
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT 0x9
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT 0x10
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT 0x18
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK 0x00000001L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK 0x00000002L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK 0x00000100L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK 0x00000200L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK 0x003F0000L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK 0x7F000000L
+//BIFC_PERF_CNT_MMIO_RD
+#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__SHIFT 0x0
+#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE_MASK 0xFFFFFFFFL
+//BIFC_PERF_CNT_MMIO_WR
+#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__SHIFT 0x0
+#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE_MASK 0xFFFFFFFFL
+//BIFC_PERF_CNT_DMA_RD
+#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__SHIFT 0x0
+#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE_MASK 0xFFFFFFFFL
+//BIFC_PERF_CNT_DMA_WR
+#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__SHIFT 0x0
+#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE_MASK 0xFFFFFFFFL
+//NBIF_REGIF_ERRSET_CTRL
+#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0
+#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L
+//SMN_MST_EP_CNTL3
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK 0x00000080L
+//SMN_MST_EP_CNTL4
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK 0x00000080L
+//SMN_MST_CNTL1
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT 0x0
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT 0x10
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK 0x00000001L
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK 0x00010000L
+//SMN_MST_EP_CNTL5
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK 0x00000080L
+//BIF_SELFRING_BUFFER_VID
+#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT 0x0
+#define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID__SHIFT 0x8
+#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK 0x000000FFL
+#define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID_MASK 0x0000FF00L
+//BIF_SELFRING_VECTOR_CNTL
+#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT 0x0
+#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT 0x1
+#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK 0x00000001L
+#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK 0x00000002L
+//BIF_GMI_WRR_WEIGHT
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT__SHIFT 0x0
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT__SHIFT 0x8
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT__SHIFT 0x10
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_MODE__SHIFT 0x1f
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT_MASK 0x000000FFL
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT_MASK 0x0000FF00L
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT_MASK 0x00FF0000L
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_MODE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif_rcc_pfc_amdgfx_RCCPFCDEC
+//RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L
+//RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L
+#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif_rcc_pfc_amdgfxaz_RCCPFCDEC
+//RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L
+//RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif_bif_rst_bif_rst_regblk
+//HARD_RST_CTRL
+#define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0
+#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1
+#define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2
+#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3
+#define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4
+#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5
+#define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6
+#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7
+#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c
+#define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d
+#define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e
+#define HARD_RST_CTRL__CORE_RST_EN__SHIFT 0x1f
+#define HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK 0x00000001L
+#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK 0x00000002L
+#define HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK 0x00000004L
+#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK 0x00000008L
+#define HARD_RST_CTRL__EP_CFG_RST_EN_MASK 0x00000010L
+#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK 0x00000020L
+#define HARD_RST_CTRL__EP_PRV_RST_EN_MASK 0x00000040L
+#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK 0x00000080L
+#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN_MASK 0x10000000L
+#define HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK 0x20000000L
+#define HARD_RST_CTRL__RELOAD_STRAP_EN_MASK 0x40000000L
+#define HARD_RST_CTRL__CORE_RST_EN_MASK 0x80000000L
+//RSMU_SOFT_RST_CTRL
+#define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0
+#define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1
+#define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2
+#define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3
+#define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4
+#define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5
+#define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6
+#define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7
+#define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c
+#define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d
+#define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e
+#define RSMU_SOFT_RST_CTRL__CORE_RST_EN__SHIFT 0x1f
+#define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN_MASK 0x00000001L
+#define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK 0x00000002L
+#define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN_MASK 0x00000004L
+#define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK 0x00000008L
+#define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN_MASK 0x00000010L
+#define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK 0x00000020L
+#define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN_MASK 0x00000040L
+#define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK 0x00000080L
+#define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN_MASK 0x10000000L
+#define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN_MASK 0x20000000L
+#define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN_MASK 0x40000000L
+#define RSMU_SOFT_RST_CTRL__CORE_RST_EN_MASK 0x80000000L
+//SELF_SOFT_RST
+#define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT 0x0
+#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT 0x1
+#define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT 0x2
+#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT 0x3
+#define SELF_SOFT_RST__EP0_CFG_RST__SHIFT 0x4
+#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT 0x5
+#define SELF_SOFT_RST__EP0_PRV_RST__SHIFT 0x6
+#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT 0x7
+#define SELF_SOFT_RST__HRPU_SDP_PORT_RST__SHIFT 0x18
+#define SELF_SOFT_RST__GSID_SDP_PORT_RST__SHIFT 0x19
+#define SELF_SOFT_RST__GMIU_SDP_PORT_RST__SHIFT 0x1a
+#define SELF_SOFT_RST__GMID_SDP_PORT_RST__SHIFT 0x1b
+#define SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT 0x1c
+#define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT 0x1d
+#define SELF_SOFT_RST__RELOAD_STRAP__SHIFT 0x1e
+#define SELF_SOFT_RST__CORE_RST__SHIFT 0x1f
+#define SELF_SOFT_RST__DSPT0_CFG_RST_MASK 0x00000001L
+#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK 0x00000002L
+#define SELF_SOFT_RST__DSPT0_PRV_RST_MASK 0x00000004L
+#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK 0x00000008L
+#define SELF_SOFT_RST__EP0_CFG_RST_MASK 0x00000010L
+#define SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK 0x00000020L
+#define SELF_SOFT_RST__EP0_PRV_RST_MASK 0x00000040L
+#define SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK 0x00000080L
+#define SELF_SOFT_RST__HRPU_SDP_PORT_RST_MASK 0x01000000L
+#define SELF_SOFT_RST__GSID_SDP_PORT_RST_MASK 0x02000000L
+#define SELF_SOFT_RST__GMIU_SDP_PORT_RST_MASK 0x04000000L
+#define SELF_SOFT_RST__GMID_SDP_PORT_RST_MASK 0x08000000L
+#define SELF_SOFT_RST__SWUS_SHADOW_RST_MASK 0x10000000L
+#define SELF_SOFT_RST__CORE_STICKY_RST_MASK 0x20000000L
+#define SELF_SOFT_RST__RELOAD_STRAP_MASK 0x40000000L
+#define SELF_SOFT_RST__CORE_RST_MASK 0x80000000L
+//BIF_GFX_DRV_VPU_RST
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT 0x0
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT 0x1
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT 0x2
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT 0x3
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT 0x4
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT 0x5
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT 0x6
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT 0x7
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK 0x00000001L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK 0x00000002L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK 0x00000004L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK 0x00000008L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK 0x00000010L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK 0x00000020L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK 0x00000040L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK 0x00000080L
+//BIF_RST_MISC_CTRL
+#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT 0x0
+#define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT 0x2
+#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT 0x4
+#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT 0x5
+#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT 0x6
+#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT 0x8
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT 0x9
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT 0xa
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT 0xd
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT 0xf
+#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x11
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT 0x17
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT 0x18
+#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK 0x00000001L
+#define BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK 0x0000000CL
+#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK 0x00000010L
+#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK 0x00000020L
+#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK 0x00000040L
+#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK 0x00000100L
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK 0x00000200L
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK 0x00001C00L
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK 0x00006000L
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK 0x00018000L
+#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0x000E0000L
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK 0x00800000L
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK 0x03000000L
+//BIF_RST_MISC_CTRL2
+#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT 0x10
+#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT 0x11
+#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT 0x12
+#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT 0x1f
+#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK 0x00010000L
+#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK 0x00020000L
+#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK 0x00040000L
+#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK 0x80000000L
+//BIF_RST_MISC_CTRL3
+#define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT 0x0
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT 0x4
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT 0x6
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT 0x7
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT 0xa
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT 0xd
+#define BIF_RST_MISC_CTRL3__RSMU_SOFT_RST_CYCLE__SHIFT 0x10
+#define BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK 0x0000000FL
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK 0x00000030L
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK 0x00000040L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK 0x00000380L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK 0x00001C00L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK 0x0000E000L
+#define BIF_RST_MISC_CTRL3__RSMU_SOFT_RST_CYCLE_MASK 0x00FF0000L
+//BIF_RST_GFXVF_FLR_IDLE
+#define BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE__SHIFT 0x0
+#define BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE__SHIFT 0x1
+#define BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE__SHIFT 0x2
+#define BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE__SHIFT 0x3
+#define BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE__SHIFT 0x4
+#define BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE__SHIFT 0x5
+#define BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE__SHIFT 0x6
+#define BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE__SHIFT 0x7
+#define BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE__SHIFT 0x8
+#define BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE__SHIFT 0x9
+#define BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE__SHIFT 0xa
+#define BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE__SHIFT 0xb
+#define BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE__SHIFT 0xc
+#define BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE__SHIFT 0xd
+#define BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE__SHIFT 0xe
+#define BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE__SHIFT 0xf
+#define BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE__SHIFT 0x1f
+#define BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE_MASK 0x00000001L
+#define BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE_MASK 0x00000002L
+#define BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE_MASK 0x00000004L
+#define BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE_MASK 0x00000008L
+#define BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE_MASK 0x00000010L
+#define BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE_MASK 0x00000020L
+#define BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE_MASK 0x00000040L
+#define BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE_MASK 0x00000080L
+#define BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE_MASK 0x00000100L
+#define BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE_MASK 0x00000200L
+#define BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE_MASK 0x00000400L
+#define BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE_MASK 0x00000800L
+#define BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE_MASK 0x00001000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE_MASK 0x00002000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE_MASK 0x00004000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE_MASK 0x00008000L
+#define BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE_MASK 0x80000000L
+//DEV0_PF0_FLR_RST_CTRL
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT 0x5
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT 0x6
+#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT 0x7
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT 0x8
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT 0x9
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT 0xa
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT 0xb
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT 0xc
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT 0xd
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT 0xe
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT 0xf
+#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT 0x1f
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN_MASK 0x00000020L
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN_MASK 0x00000040L
+#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN_MASK 0x00000080L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK 0x00000100L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK 0x00000200L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK 0x00000400L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK 0x00000800L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK 0x00001000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN_MASK 0x00002000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN_MASK 0x00004000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN_MASK 0x00008000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK 0x00010000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK 0x80000000L
+//DEV0_PF1_FLR_RST_CTRL
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF2_FLR_RST_CTRL
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF3_FLR_RST_CTRL
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF4_FLR_RST_CTRL
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF5_FLR_RST_CTRL
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF6_FLR_RST_CTRL
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF7_FLR_RST_CTRL
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//BIF_INST_RESET_INTR_STS
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT 0x0
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x1
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT 0x2
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT 0x3
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT 0x4
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK 0x00000001L
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000002L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK 0x00000004L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK 0x00000008L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK 0x00000010L
+//BIF_PF_FLR_INTR_STS
+#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT 0x0
+#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT 0x1
+#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT 0x2
+#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT 0x3
+#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__SHIFT 0x4
+#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__SHIFT 0x5
+#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__SHIFT 0x6
+#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__SHIFT 0x7
+#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK 0x00000001L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK 0x00000002L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS_MASK 0x00000004L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS_MASK 0x00000008L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS_MASK 0x00000010L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS_MASK 0x00000020L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS_MASK 0x00000040L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS_MASK 0x00000080L
+//BIF_D3HOTD0_INTR_STS
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT 0x0
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT 0x1
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT 0x2
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT 0x3
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__SHIFT 0x4
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__SHIFT 0x5
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__SHIFT 0x6
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__SHIFT 0x7
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK 0x00000001L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK 0x00000002L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS_MASK 0x00000004L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS_MASK 0x00000008L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS_MASK 0x00000010L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS_MASK 0x00000020L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS_MASK 0x00000040L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS_MASK 0x00000080L
+//BIF_POWER_INTR_STS
+#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT 0x0
+#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT 0x10
+#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK 0x00000001L
+#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK 0x00010000L
+//BIF_PF_DSTATE_INTR_STS
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT 0x0
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT 0x1
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT 0x2
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT 0x3
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT 0x4
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT 0x5
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT 0x6
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT 0x7
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK 0x00000001L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK 0x00000002L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK 0x00000004L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK 0x00000008L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK 0x00000010L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK 0x00000020L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK 0x00000040L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK 0x00000080L
+//BIF_PF0_VF_FLR_INTR_STS
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS__SHIFT 0x0
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS__SHIFT 0x1
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS__SHIFT 0x2
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS__SHIFT 0x3
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS__SHIFT 0x4
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS__SHIFT 0x5
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS__SHIFT 0x6
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS__SHIFT 0x7
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS__SHIFT 0x8
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS__SHIFT 0x9
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS__SHIFT 0xa
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS__SHIFT 0xb
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS__SHIFT 0xc
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS__SHIFT 0xd
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS__SHIFT 0xe
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS__SHIFT 0xf
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS__SHIFT 0x1f
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS_MASK 0x00000001L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS_MASK 0x00000002L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS_MASK 0x00000004L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS_MASK 0x00000008L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS_MASK 0x00000010L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS_MASK 0x00000020L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS_MASK 0x00000040L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS_MASK 0x00000080L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS_MASK 0x00000100L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS_MASK 0x00000200L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS_MASK 0x00000400L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS_MASK 0x00000800L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS_MASK 0x00001000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS_MASK 0x00002000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS_MASK 0x00004000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS_MASK 0x00008000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS_MASK 0x80000000L
+//BIF_INST_RESET_INTR_MASK
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT 0x0
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x1
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT 0x2
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT 0x3
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT 0x4
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK 0x00000001L
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000002L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK 0x00000004L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK 0x00000008L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK 0x00000010L
+//BIF_PF_FLR_INTR_MASK
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT 0x0
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT 0x1
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT 0x2
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT 0x3
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__SHIFT 0x4
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__SHIFT 0x5
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__SHIFT 0x6
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__SHIFT 0x7
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK 0x00000001L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK 0x00000002L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK_MASK 0x00000004L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK_MASK 0x00000008L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK_MASK 0x00000010L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK_MASK 0x00000020L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK_MASK 0x00000040L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK_MASK 0x00000080L
+//BIF_D3HOTD0_INTR_MASK
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT 0x0
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT 0x1
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT 0x2
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT 0x3
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__SHIFT 0x4
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__SHIFT 0x5
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__SHIFT 0x6
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__SHIFT 0x7
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK 0x00000001L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK 0x00000002L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK_MASK 0x00000004L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK_MASK 0x00000008L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK_MASK 0x00000010L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK_MASK 0x00000020L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK_MASK 0x00000040L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK_MASK 0x00000080L
+//BIF_POWER_INTR_MASK
+#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT 0x0
+#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT 0x10
+#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK 0x00000001L
+#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK 0x00010000L
+//BIF_PF_DSTATE_INTR_MASK
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT 0x0
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT 0x1
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT 0x2
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT 0x3
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT 0x4
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT 0x5
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT 0x6
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT 0x7
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK 0x00000001L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK 0x00000002L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK 0x00000004L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK 0x00000008L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK 0x00000010L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK 0x00000020L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK 0x00000040L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK 0x00000080L
+//BIF_PF0_VF_FLR_INTR_MASK
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK__SHIFT 0x0
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__SHIFT 0x1
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK__SHIFT 0x2
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK__SHIFT 0x3
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK__SHIFT 0x4
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK__SHIFT 0x5
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK__SHIFT 0x6
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK__SHIFT 0x7
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK__SHIFT 0x8
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK__SHIFT 0x9
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK__SHIFT 0xa
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK__SHIFT 0xb
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK__SHIFT 0xc
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK__SHIFT 0xd
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK__SHIFT 0xe
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK__SHIFT 0xf
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK__SHIFT 0x1f
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK_MASK 0x00000001L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK_MASK 0x00000002L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK_MASK 0x00000004L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK_MASK 0x00000008L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK_MASK 0x00000010L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK_MASK 0x00000020L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK_MASK 0x00000040L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK_MASK 0x00000080L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK_MASK 0x00000100L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK_MASK 0x00000200L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK_MASK 0x00000400L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK_MASK 0x00000800L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK_MASK 0x00001000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK_MASK 0x00002000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK_MASK 0x00004000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK_MASK 0x00008000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK_MASK 0x80000000L
+//BIF_PF_FLR_RST
+#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0
+#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1
+#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2
+#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3
+#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x4
+#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x5
+#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x6
+#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT 0x7
+#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L
+#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L
+#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK 0x00000004L
+#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK 0x00000008L
+#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK 0x00000010L
+#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK 0x00000020L
+#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK 0x00000040L
+#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST_MASK 0x00000080L
+//BIF_PF0_VF_FLR_RST
+#define BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x0
+#define BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x1
+#define BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x2
+#define BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x3
+#define BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x4
+#define BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x5
+#define BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x6
+#define BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x7
+#define BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x8
+#define BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x9
+#define BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0xa
+#define BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0xb
+#define BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0xc
+#define BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0xd
+#define BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0xe
+#define BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0xf
+#define BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x1f
+#define BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST_MASK 0x00000001L
+#define BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST_MASK 0x00000002L
+#define BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST_MASK 0x00000004L
+#define BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST_MASK 0x00000008L
+#define BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST_MASK 0x00000010L
+#define BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST_MASK 0x00000020L
+#define BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST_MASK 0x00000040L
+#define BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST_MASK 0x00000080L
+#define BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST_MASK 0x00000100L
+#define BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST_MASK 0x00000200L
+#define BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST_MASK 0x00000400L
+#define BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST_MASK 0x00000800L
+#define BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST_MASK 0x00001000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST_MASK 0x00002000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST_MASK 0x00004000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST_MASK 0x00008000L
+#define BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST_MASK 0x80000000L
+//BIF_DEV0_PF0_DSTATE_VALUE
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF1_DSTATE_VALUE
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF2_DSTATE_VALUE
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF3_DSTATE_VALUE
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF4_DSTATE_VALUE
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF5_DSTATE_VALUE
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF6_DSTATE_VALUE
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF7_DSTATE_VALUE
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE_MASK 0x00030000L
+//DEV0_PF0_D3HOTD0_RST_CTRL
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF1_D3HOTD0_RST_CTRL
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF2_D3HOTD0_RST_CTRL
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF3_D3HOTD0_RST_CTRL
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF4_D3HOTD0_RST_CTRL
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF5_D3HOTD0_RST_CTRL
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF6_D3HOTD0_RST_CTRL
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF7_D3HOTD0_RST_CTRL
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//BIF_PORT0_DSTATE_VALUE
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK 0x00030000L
+
+
+// addressBlock: nbio_nbif_bif_ras_bif_ras_regblk
+//BIF_RAS_LEAF0_CTRL
+#define BIF_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x0
+#define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x15
+#define BIF_RAS_LEAF0_CTRL__POISON_DET_EN_MASK 0x00000001L
+#define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN_MASK 0x00000010L
+#define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L
+#define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK 0x00000040L
+#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV_MASK 0x00010000L
+#define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV_MASK 0x00020000L
+#define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET_MASK 0x00040000L
+#define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET_MASK 0x00080000L
+#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT_MASK 0x00100000L
+#define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED_MASK 0x00200000L
+//BIF_RAS_LEAF1_CTRL
+#define BIF_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x0
+#define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x15
+#define BIF_RAS_LEAF1_CTRL__POISON_DET_EN_MASK 0x00000001L
+#define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN_MASK 0x00000010L
+#define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L
+#define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK 0x00000040L
+#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV_MASK 0x00010000L
+#define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV_MASK 0x00020000L
+#define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET_MASK 0x00040000L
+#define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET_MASK 0x00080000L
+#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT_MASK 0x00100000L
+#define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED_MASK 0x00200000L
+//BIF_RAS_LEAF2_CTRL
+#define BIF_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x0
+#define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x15
+#define BIF_RAS_LEAF2_CTRL__POISON_DET_EN_MASK 0x00000001L
+#define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN_MASK 0x00000010L
+#define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L
+#define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK 0x00000040L
+#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV_MASK 0x00010000L
+#define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV_MASK 0x00020000L
+#define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET_MASK 0x00040000L
+#define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET_MASK 0x00080000L
+#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT_MASK 0x00100000L
+#define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED_MASK 0x00200000L
+//BIF_RAS_MISC_CTRL
+#define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN__SHIFT 0x0
+#define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN_MASK 0x00000001L
+//BIF_IOHUB_RAS_IH_CNTL
+#define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN__SHIFT 0x0
+#define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN_MASK 0x00000001L
+//BIF_RAS_VWR_FROM_IOHUB
+#define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG__SHIFT 0x0
+#define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG_MASK 0x00000001L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_1_STATUS
+#define BIF_CFG_DEV0_EPF0_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_HEADER
+#define BIF_CFG_DEV0_EPF0_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_1_BIST
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF1_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_COMMAND
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF1_1_STATUS
+#define BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_LATENCY
+#define BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_HEADER
+#define BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_1_BIST
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF1_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF1_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF1_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF1_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF1_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF1_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF1_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF1_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF0_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF0_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF0_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF0_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF0_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF0_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF0_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF0_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF1_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF1_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF1_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF1_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF1_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF1_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF1_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF1_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf2_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF2_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF2_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF2_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF2_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF2_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF2_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF2_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF2_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf3_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF3_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF3_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF3_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF3_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF3_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF3_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF3_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF3_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf4_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF4_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF4_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF4_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF4_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF4_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF4_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF4_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF4_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf5_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF5_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF5_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF5_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF5_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF5_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF5_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF5_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF5_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf6_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF6_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF6_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF6_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF6_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF6_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF6_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF6_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF6_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf7_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF7_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF7_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF7_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF7_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF7_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF7_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF7_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF7_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf8_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF8_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF8_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF8_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF8_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF8_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF8_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF8_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF8_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf9_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF9_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF9_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF9_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF9_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF9_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF9_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF9_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF9_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf10_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF10_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF10_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF10_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF10_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF10_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF10_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF10_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF10_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf11_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF11_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF11_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF11_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF11_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF11_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF11_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF11_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF11_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf12_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF12_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF12_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF12_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF12_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF12_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF12_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF12_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF12_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf13_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF13_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF13_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF13_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF13_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF13_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF13_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF13_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF13_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf14_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF14_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF14_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF14_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF14_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF14_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF14_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF14_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF14_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf15_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF15_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF15_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF15_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF15_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_VF15_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_VF15_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF15_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF15_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif_pciemsix_amdgfx_MSIXTDEC
+//PCIEMSIX_VECT0_ADDR_LO
+#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT0_ADDR_HI
+#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT0_MSG_DATA
+#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT0_CONTROL
+#define PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT1_ADDR_LO
+#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT1_ADDR_HI
+#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT1_MSG_DATA
+#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT1_CONTROL
+#define PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT2_ADDR_LO
+#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT2_ADDR_HI
+#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT2_MSG_DATA
+#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT2_CONTROL
+#define PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT3_ADDR_LO
+#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT3_ADDR_HI
+#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT3_MSG_DATA
+#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT3_CONTROL
+#define PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT4_ADDR_LO
+#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT4_ADDR_HI
+#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT4_MSG_DATA
+#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT4_CONTROL
+#define PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT5_ADDR_LO
+#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT5_ADDR_HI
+#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT5_MSG_DATA
+#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT5_CONTROL
+#define PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT6_ADDR_LO
+#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT6_ADDR_HI
+#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT6_MSG_DATA
+#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT6_CONTROL
+#define PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT7_ADDR_LO
+#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT7_ADDR_HI
+#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT7_MSG_DATA
+#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT7_CONTROL
+#define PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT8_ADDR_LO
+#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT8_ADDR_HI
+#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT8_MSG_DATA
+#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT8_CONTROL
+#define PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT9_ADDR_LO
+#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT9_ADDR_HI
+#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT9_MSG_DATA
+#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT9_CONTROL
+#define PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT10_ADDR_LO
+#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT10_ADDR_HI
+#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT10_MSG_DATA
+#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT10_CONTROL
+#define PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT11_ADDR_LO
+#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT11_ADDR_HI
+#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT11_MSG_DATA
+#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT11_CONTROL
+#define PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT12_ADDR_LO
+#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT12_ADDR_HI
+#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT12_MSG_DATA
+#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT12_CONTROL
+#define PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT13_ADDR_LO
+#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT13_ADDR_HI
+#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT13_MSG_DATA
+#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT13_CONTROL
+#define PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT14_ADDR_LO
+#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT14_ADDR_HI
+#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT14_MSG_DATA
+#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT14_CONTROL
+#define PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT15_ADDR_LO
+#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT15_ADDR_HI
+#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT15_MSG_DATA
+#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT15_CONTROL
+#define PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT16_ADDR_LO
+#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT16_ADDR_HI
+#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT16_MSG_DATA
+#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT16_CONTROL
+#define PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT17_ADDR_LO
+#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT17_ADDR_HI
+#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT17_MSG_DATA
+#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT17_CONTROL
+#define PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT18_ADDR_LO
+#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT18_ADDR_HI
+#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT18_MSG_DATA
+#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT18_CONTROL
+#define PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT19_ADDR_LO
+#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT19_ADDR_HI
+#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT19_MSG_DATA
+#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT19_CONTROL
+#define PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT20_ADDR_LO
+#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT20_ADDR_HI
+#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT20_MSG_DATA
+#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT20_CONTROL
+#define PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT21_ADDR_LO
+#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT21_ADDR_HI
+#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT21_MSG_DATA
+#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT21_CONTROL
+#define PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT22_ADDR_LO
+#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT22_ADDR_HI
+#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT22_MSG_DATA
+#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT22_CONTROL
+#define PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT23_ADDR_LO
+#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT23_ADDR_HI
+#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT23_MSG_DATA
+#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT23_CONTROL
+#define PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT24_ADDR_LO
+#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT24_ADDR_HI
+#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT24_MSG_DATA
+#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT24_CONTROL
+#define PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT25_ADDR_LO
+#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT25_ADDR_HI
+#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT25_MSG_DATA
+#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT25_CONTROL
+#define PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT26_ADDR_LO
+#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT26_ADDR_HI
+#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT26_MSG_DATA
+#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT26_CONTROL
+#define PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT27_ADDR_LO
+#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT27_ADDR_HI
+#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT27_MSG_DATA
+#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT27_CONTROL
+#define PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT28_ADDR_LO
+#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT28_ADDR_HI
+#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT28_MSG_DATA
+#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT28_CONTROL
+#define PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT29_ADDR_LO
+#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT29_ADDR_HI
+#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT29_MSG_DATA
+#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT29_CONTROL
+#define PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT30_ADDR_LO
+#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT30_ADDR_HI
+#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT30_MSG_DATA
+#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT30_CONTROL
+#define PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT31_ADDR_LO
+#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT31_ADDR_HI
+#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT31_MSG_DATA
+#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT31_CONTROL
+#define PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L
+
+
+// addressBlock: nbio_nbif_pciemsix_amdgfx_MSIXPDEC
+//PCIEMSIX_PBA
+#define PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_pcie_pswusp0_pciedir_p
+//PCIEP_RESERVED
+#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//PCIEP_SCRATCH
+#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL
+//PCIEP_PORT_CNTL
+#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18
+#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L
+#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L
+#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L
+#define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L
+#define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L
+#define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L
+#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L
+#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L
+#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L
+#define PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L
+//PCIE_TX_CNTL
+#define PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L
+#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L
+#define PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L
+#define PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L
+#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L
+#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L
+#define PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L
+#define PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L
+#define PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L
+//PCIE_TX_REQUESTER_ID
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//PCIE_TX_VENDOR_SPECIFIC
+#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL
+//PCIE_TX_REQUEST_NUM_CNTL
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L
+//PCIE_TX_SEQ
+#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL
+#define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L
+//PCIE_TX_REPLAY
+#define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L
+#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L
+#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L
+//PCIE_TX_ACK_LATENCY_LIMIT
+#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL
+#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L
+//PCIE_TX_CREDITS_ADVT_P
+#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL
+#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L
+//PCIE_TX_CREDITS_ADVT_NP
+#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL
+#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L
+//PCIE_TX_CREDITS_ADVT_CPL
+#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL
+#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L
+//PCIE_TX_CREDITS_INIT_P
+#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL
+#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L
+//PCIE_TX_CREDITS_INIT_NP
+#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL
+#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L
+//PCIE_TX_CREDITS_INIT_CPL
+#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL
+#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L
+//PCIE_TX_CREDITS_STATUS
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L
+//PCIE_TX_CREDITS_FCU_THRESHOLD
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L
+//PCIE_P_PORT_LANE_STATUS
+#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L
+#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL
+//PCIE_FC_P
+#define PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define PCIE_FC_P__PH_CREDITS__SHIFT 0x8
+#define PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL
+#define PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L
+//PCIE_FC_NP
+#define PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
+#define PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL
+#define PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L
+//PCIE_FC_CPL
+#define PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
+#define PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL
+#define PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L
+//PSWUSP0_PCIE_ERR_CNTL
+#define PSWUSP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define PSWUSP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define PSWUSP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define PSWUSP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define PSWUSP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0xc
+#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0xd
+#define PSWUSP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define PSWUSP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define PSWUSP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define PSWUSP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define PSWUSP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define PSWUSP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define PSWUSP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L
+#define PSWUSP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L
+#define PSWUSP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L
+#define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L
+#define PSWUSP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L
+#define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L
+#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x00001000L
+#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x00002000L
+#define PSWUSP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L
+#define PSWUSP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L
+#define PSWUSP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L
+#define PSWUSP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define PSWUSP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+//PSWUSP0_PCIE_RX_CNTL
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define PSWUSP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define PSWUSP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define PSWUSP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define PSWUSP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define PSWUSP0_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//PCIE_RX_EXPECTED_SEQNUM
+#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL
+//PCIE_RX_VENDOR_SPECIFIC
+#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L
+//PCIE_RX_CNTL3
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L
+//PCIE_RX_CREDITS_ALLOCATED_P
+#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL
+#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L
+//PCIE_RX_CREDITS_ALLOCATED_NP
+#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL
+#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L
+//PCIE_RX_CREDITS_ALLOCATED_CPL
+#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL
+#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L
+//PCIEP_ERROR_INJECT_PHYSICAL
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L
+//PCIEP_ERROR_INJECT_TRANSACTION
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L
+//PCIEP_SRIOV_PRIV_CTRL
+#define PCIEP_SRIOV_PRIV_CTRL__RX_SRIOV_VF_MAPPING_MODE__SHIFT 0x0
+#define PCIEP_SRIOV_PRIV_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x2
+#define PCIEP_SRIOV_PRIV_CTRL__RX_SRIOV_VF_MAPPING_MODE_MASK 0x00000003L
+#define PCIEP_SRIOV_PRIV_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0x0000000CL
+//PCIEP_NAK_COUNTER
+#define PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0
+#define PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10
+#define PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL
+#define PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L
+//PCIE_LC_CNTL
+#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L
+#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L
+#define PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L
+#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L
+#define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L
+#define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L
+#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L
+#define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L
+#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L
+#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L
+#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L
+#define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L
+#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L
+#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L
+#define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L
+#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L
+#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L
+#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L
+#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L
+#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L
+//PCIE_LC_TRAINING_CNTL
+#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL
+#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L
+#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L
+#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L
+#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L
+#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L
+#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L
+#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L
+#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L
+#define PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L
+#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L
+#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L
+#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L
+#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L
+#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L
+#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L
+#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L
+#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L
+#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L
+#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L
+#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L
+#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L
+//PCIE_LC_LINK_WIDTH_CNTL
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L
+//PCIE_LC_N_FTS_CNTL
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L
+#define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L
+//PSWUSP0_PCIE_LC_SPEED_CNTL
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L
+//PCIE_LC_STATE0
+#define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL
+#define PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L
+#define PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L
+#define PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L
+//PCIE_LC_STATE1
+#define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL
+#define PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L
+#define PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L
+#define PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L
+//PCIE_LC_STATE2
+#define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL
+#define PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L
+#define PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L
+#define PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L
+//PCIE_LC_STATE3
+#define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL
+#define PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L
+#define PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L
+#define PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L
+//PCIE_LC_STATE4
+#define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL
+#define PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L
+#define PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L
+#define PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L
+//PCIE_LC_STATE5
+#define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL
+#define PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L
+#define PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L
+#define PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L
+//PCIE_LINK_MANAGEMENT_CNTL2
+#define PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0
+#define PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1
+#define PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2
+#define PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3
+#define PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4
+#define PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7
+#define PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb
+#define PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf
+#define PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13
+#define PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L
+#define PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L
+#define PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L
+#define PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L
+#define PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L
+#define PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L
+#define PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L
+#define PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L
+#define PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L
+//PSWUSP0_PCIE_LC_CNTL2
+#define PSWUSP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define PSWUSP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define PSWUSP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define PSWUSP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define PSWUSP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define PSWUSP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define PSWUSP0_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
+#define PSWUSP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define PSWUSP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define PSWUSP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define PSWUSP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define PSWUSP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define PSWUSP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL
+#define PSWUSP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L
+//PCIE_LC_BW_CHANGE_CNTL
+#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb
+#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L
+//PCIE_LC_CDR_CNTL
+#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL
+#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L
+#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L
+//PCIE_LC_LANE_CNTL
+#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
+#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL
+#define PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L
+//PCIE_LC_CNTL3
+#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
+#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
+#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
+#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
+#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L
+#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L
+#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L
+#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L
+#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L
+#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L
+#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L
+#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L
+#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L
+#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L
+#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L
+#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L
+#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L
+#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L
+#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L
+#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L
+#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L
+#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L
+#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L
+#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L
+#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L
+#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L
+#define PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L
+//PCIE_LC_CNTL4
+#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
+#define PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
+#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
+#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
+#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
+#define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
+#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
+#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
+#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
+#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17
+#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L
+#define PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L
+#define PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L
+#define PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L
+#define PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L
+#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L
+#define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L
+#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L
+#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L
+#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L
+#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L
+#define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L
+#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L
+#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L
+#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L
+#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L
+#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L
+#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L
+#define PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L
+#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L
+#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L
+#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L
+//PCIE_LC_CNTL5
+#define PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
+#define PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
+#define PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
+#define PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
+#define PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19
+#define PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a
+#define PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b
+#define PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c
+#define PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d
+#define PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL
+#define PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L
+#define PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L
+#define PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L
+#define PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L
+#define PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L
+#define PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L
+#define PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L
+#define PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L
+#define PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L
+//PCIE_LC_FORCE_COEFF
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
+#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
+#define PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L
+#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L
+#define PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L
+//PCIE_LC_BEST_EQ_SETTINGS
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L
+//PCIE_LC_FORCE_EQ_REQ_COEFF
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L
+//PCIE_LC_CNTL6
+#define PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5
+#define PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6
+#define PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8
+#define PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9
+#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd
+#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe
+#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10
+#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12
+#define PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13
+#define PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14
+#define PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15
+#define PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16
+#define PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17
+#define PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18
+#define PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f
+#define PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L
+#define PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L
+#define PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L
+#define PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L
+#define PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L
+#define PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L
+#define PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L
+#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L
+#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L
+#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L
+#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L
+#define PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L
+#define PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L
+#define PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L
+#define PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L
+#define PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L
+#define PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L
+#define PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L
+//PCIE_LC_CNTL7
+#define PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0
+#define PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1
+#define PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2
+#define PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3
+#define PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4
+#define PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8
+#define PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9
+#define PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc
+#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd
+#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15
+#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16
+#define PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17
+#define PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18
+#define PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a
+#define PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b
+#define PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c
+#define PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d
+#define PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e
+#define PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f
+#define PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L
+#define PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L
+#define PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L
+#define PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L
+#define PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L
+#define PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L
+#define PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L
+#define PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L
+#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L
+#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L
+#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L
+#define PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L
+#define PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L
+#define PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L
+#define PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L
+#define PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L
+#define PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L
+#define PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L
+#define PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L
+//PCIE_LINK_MANAGEMENT_STATUS
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5
+#define PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6
+#define PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8
+#define PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9
+#define PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb
+#define PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc
+#define PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L
+#define PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L
+#define PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L
+#define PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L
+#define PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L
+#define PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L
+#define PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L
+//PCIE_LINK_MANAGEMENT_MASK
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5
+#define PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6
+#define PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8
+#define PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9
+#define PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb
+#define PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc
+#define PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L
+#define PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L
+#define PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L
+#define PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L
+#define PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L
+#define PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L
+#define PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L
+//PCIE_LINK_MANAGEMENT_CNTL
+#define PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0
+#define PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3
+#define PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7
+#define PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb
+#define PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc
+#define PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd
+#define PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf
+#define PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11
+#define PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12
+#define PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13
+#define PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17
+#define PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b
+#define PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L
+#define PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L
+#define PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L
+#define PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L
+#define PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L
+#define PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L
+#define PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L
+#define PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L
+#define PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L
+#define PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L
+#define PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L
+#define PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L
+//PCIEP_STRAP_LC
+#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L
+#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL
+#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L
+#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L
+#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L
+#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L
+#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L
+#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L
+#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L
+#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L
+#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L
+//PSWUSP0_PCIEP_STRAP_MISC
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L
+//PCIE_LC_L1_PM_SUBSTATE
+#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0
+#define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1
+#define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2
+#define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3
+#define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4
+#define PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6
+#define PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8
+#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10
+#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14
+#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L
+//PCIE_LC_L1_PM_SUBSTATE2
+#define PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0
+#define PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8
+#define PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10
+#define PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL
+#define PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L
+#define PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L
+//PCIE_LC_PORT_ORDER
+#define PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0
+#define PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL
+//PCIEP_BCH_ECC_CNTL
+#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L
+#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L
+#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L
+
+
+// addressBlock: nbio_pcie_pciedir
+//PCIE_RESERVED
+#define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL
+//PCIE_SCRATCH
+#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//PCIE_RX_NUM_NAK
+#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0
+#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xFFFFFFFFL
+//PCIE_RX_NUM_NAK_GENERATED
+#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0
+#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xFFFFFFFFL
+//PCIE_CNTL
+#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1
+#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9
+#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa
+#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf
+#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10
+#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11
+#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12
+#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13
+#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14
+#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15
+#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16
+#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17
+#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f
+#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0x0000000EL
+#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x00000200L
+#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x00001C00L
+#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x00008000L
+#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x00010000L
+#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x00020000L
+#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x00040000L
+#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x00080000L
+#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x00100000L
+#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x00200000L
+#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x00400000L
+#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x00800000L
+#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000L
+//PCIE_CONFIG_CNTL
+#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x8
+#define PCIE_CONFIG_CNTL__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x9
+#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18
+#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1b
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT 0x1c
+#define PCIE_CONFIG_CNTL__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x1e
+#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0x0000000FL
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_PAYLOAD_SIZE_MODE_MASK 0x00000100L
+#define PCIE_CONFIG_CNTL__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE_MASK 0x00000600L
+#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x00010000L
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0x000E0000L
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x00100000L
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0x00E00000L
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x01000000L
+#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK 0x08000000L
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK 0x30000000L
+#define PCIE_CONFIG_CNTL__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE_MASK 0xC0000000L
+//PCIE_TX_TRACKING_ADDR_LO
+#define PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO__SHIFT 0x2
+#define PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIE_TX_TRACKING_ADDR_HI
+#define PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI__SHIFT 0x0
+#define PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIE_TX_TRACKING_CTRL_STATUS
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE__SHIFT 0x0
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT__SHIFT 0x1
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID__SHIFT 0x8
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID__SHIFT 0xf
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE_MASK 0x00000001L
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT_MASK 0x0000000EL
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID_MASK 0x00007F00L
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID_MASK 0x00008000L
+//PCIE_BW_BY_UNITID
+#define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_EN__SHIFT 0x0
+#define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID__SHIFT 0x8
+#define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_EN_MASK 0x00000001L
+#define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_MASK 0x00007F00L
+//PCIE_CNTL2
+#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0
+#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1
+#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6
+#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb
+#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc
+#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd
+#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe
+#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11
+#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12
+#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13
+#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15
+#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16
+#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17
+#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18
+#define PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d
+#define PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e
+#define PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f
+#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x00000001L
+#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x0000003EL
+#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x000007C0L
+#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x00000800L
+#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x00001000L
+#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x00002000L
+#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x00004000L
+#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x00010000L
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x00020000L
+#define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x00040000L
+#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x00080000L
+#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x00100000L
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x00200000L
+#define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x00400000L
+#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x00800000L
+#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1F000000L
+#define PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000L
+#define PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000L
+#define PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000L
+//PCIE_RX_CNTL2
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9
+#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc
+#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd
+#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10
+#define PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x00000002L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x00000004L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x00000008L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x00000010L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x00000020L
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x00000100L
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0x00000E00L
+#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x00001000L
+#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x00002000L
+#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x00004000L
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x03FF0000L
+#define PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//PCIE_TX_F0_ATTR_CNTL
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x00000003L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0x0000000CL
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x00000030L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0x000000C0L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x00000300L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0x00000C00L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x00003000L
+//PCIE_TX_SWUS_ATTR_CNTL
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P__SHIFT 0x0
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP__SHIFT 0x2
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL__SHIFT 0x4
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P__SHIFT 0x6
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP__SHIFT 0x8
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P__SHIFT 0xa
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP__SHIFT 0xc
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P_MASK 0x00000003L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP_MASK 0x0000000CL
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL_MASK 0x00000030L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P_MASK 0x000000C0L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP_MASK 0x00000300L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P_MASK 0x00000C00L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP_MASK 0x00003000L
+//PCIE_CI_CNTL
+#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
+#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3
+#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4
+#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6
+#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8
+#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc
+#define PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS__SHIFT 0x10
+#define PCIE_CI_CNTL__TX_PRIV_TLP_PREFIX_BLOCKING_DIS__SHIFT 0x11
+#define PCIE_CI_CNTL__TX_PRIV_POISONED_TLP_EGRESS_BLOCKING_DIS__SHIFT 0x12
+#define PCIE_CI_CNTL__TX_PRIV_ATOMICOP_EGRESS_BLOCKING_DIS__SHIFT 0x13
+#define PCIE_CI_CNTL__PRIV_AUTO_SLOT_PWR_LIMIT_DIS__SHIFT 0x14
+#define PCIE_CI_CNTL__TX_DISABLE_SLOT_PWR_LIMIT_MSG__SHIFT 0x15
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN__SHIFT 0x16
+#define PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN__SHIFT 0x17
+#define PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN__SHIFT 0x18
+#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x00000004L
+#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x00000008L
+#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x00000010L
+#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0x000000C0L
+#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x00000100L
+#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x00000200L
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x00000400L
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x00000800L
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x00001000L
+#define PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS_MASK 0x00010000L
+#define PCIE_CI_CNTL__TX_PRIV_TLP_PREFIX_BLOCKING_DIS_MASK 0x00020000L
+#define PCIE_CI_CNTL__TX_PRIV_POISONED_TLP_EGRESS_BLOCKING_DIS_MASK 0x00040000L
+#define PCIE_CI_CNTL__TX_PRIV_ATOMICOP_EGRESS_BLOCKING_DIS_MASK 0x00080000L
+#define PCIE_CI_CNTL__PRIV_AUTO_SLOT_PWR_LIMIT_DIS_MASK 0x00100000L
+#define PCIE_CI_CNTL__TX_DISABLE_SLOT_PWR_LIMIT_MSG_MASK 0x00200000L
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN_MASK 0x00400000L
+#define PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN_MASK 0x00800000L
+#define PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN_MASK 0x01000000L
+//PCIE_BUS_CNTL
+#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6
+#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc
+#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x00000040L
+#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x00001000L
+//PCIE_LC_STATE6
+#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0
+#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8
+#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10
+#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18
+#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x0000003FL
+#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x00003F00L
+#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x003F0000L
+#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3F000000L
+//PCIE_LC_STATE7
+#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0
+#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8
+#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10
+#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18
+#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x0000003FL
+#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x00003F00L
+#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x003F0000L
+#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3F000000L
+//PCIE_LC_STATE8
+#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0
+#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8
+#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10
+#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18
+#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x0000003FL
+#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x00003F00L
+#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x003F0000L
+#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3F000000L
+//PCIE_LC_STATE9
+#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0
+#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8
+#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10
+#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18
+#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x0000003FL
+#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x00003F00L
+#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x003F0000L
+#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3F000000L
+//PCIE_LC_STATE10
+#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0
+#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8
+#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10
+#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18
+#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x0000003FL
+#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x00003F00L
+#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x003F0000L
+#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3F000000L
+//PCIE_LC_STATE11
+#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0
+#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8
+#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10
+#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18
+#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x0000003FL
+#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x00003F00L
+#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x003F0000L
+#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3F000000L
+//PCIE_LC_STATUS1
+#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0
+#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1
+#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
+#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5
+#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x00000001L
+#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x00000002L
+#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x0000001CL
+#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0x000000E0L
+//PCIE_LC_STATUS2
+#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0
+#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10
+#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0x0000FFFFL
+#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xFFFF0000L
+//PCIE_WPR_CNTL
+#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
+#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3
+#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4
+#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5
+#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6
+#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x00000001L
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x00000002L
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x00000004L
+#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x00000008L
+#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x00000010L
+#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x00000020L
+#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x00000040L
+//PCIE_RX_LAST_TLP0
+#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0
+#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xFFFFFFFFL
+//PCIE_RX_LAST_TLP1
+#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0
+#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xFFFFFFFFL
+//PCIE_RX_LAST_TLP2
+#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0
+#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xFFFFFFFFL
+//PCIE_RX_LAST_TLP3
+#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0
+#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xFFFFFFFFL
+//PCIE_TX_LAST_TLP0
+#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0
+#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xFFFFFFFFL
+//PCIE_TX_LAST_TLP1
+#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0
+#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xFFFFFFFFL
+//PCIE_TX_LAST_TLP2
+#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0
+#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xFFFFFFFFL
+//PCIE_TX_LAST_TLP3
+#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0
+#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xFFFFFFFFL
+//PCIE_I2C_REG_ADDR_EXPAND
+#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0
+#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x0001FFFFL
+//PCIE_I2C_REG_DATA
+#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0
+#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xFFFFFFFFL
+//PCIE_CFG_CNTL
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+//PCIE_LC_PM_CNTL
+#define PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP__SHIFT 0x0
+#define PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP__SHIFT 0x4
+#define PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP__SHIFT 0x8
+#define PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP__SHIFT 0xc
+#define PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP__SHIFT 0x10
+#define PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP__SHIFT 0x14
+#define PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP__SHIFT 0x18
+#define PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP__SHIFT 0x1c
+#define PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP_MASK 0x0000000FL
+#define PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP_MASK 0x000000F0L
+#define PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP_MASK 0x00000F00L
+#define PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP_MASK 0x0000F000L
+#define PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP_MASK 0x000F0000L
+#define PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP_MASK 0x00F00000L
+#define PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP_MASK 0x0F000000L
+#define PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP_MASK 0xF0000000L
+//PCIE_LC_PORT_ORDER_CNTL
+#define PCIE_LC_PORT_ORDER_CNTL__LC_PORT_ORDER_EN__SHIFT 0x0
+#define PCIE_LC_PORT_ORDER_CNTL__LC_PORT_ORDER_EN_MASK 0x00000001L
+//PCIE_P_CNTL
+#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0
+#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1
+#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4
+#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5
+#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6
+#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7
+#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8
+#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc
+#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd
+#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe
+#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10
+#define PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS__SHIFT 0x11
+#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x00000001L
+#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x00000002L
+#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x00000010L
+#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x00000020L
+#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x00000040L
+#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x00000080L
+#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x00000100L
+#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x00001000L
+#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x00002000L
+#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0x0000C000L
+#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x00010000L
+#define PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS_MASK 0x00020000L
+//PCIE_P_BUF_STATUS
+#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0
+#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10
+#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0x0000FFFFL
+#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xFFFF0000L
+//PCIE_P_DECODER_STATUS
+#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0
+#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0x0000FFFFL
+//PCIE_P_MISC_STATUS
+#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0
+#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10
+#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0x000000FFL
+#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xFFFF0000L
+//PCIE_P_RCV_L0S_FTS_DET
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0x000000FFL
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0x0000FF00L
+//PCIE_RX_AD
+#define PCIE_RX_AD__RX_SWUS_DROP_PME_TO__SHIFT 0x0
+#define PCIE_RX_AD__RX_SWUS_DROP_UNLOCK__SHIFT 0x1
+#define PCIE_RX_AD__RX_SWUS_UR_VDM0__SHIFT 0x2
+#define PCIE_RX_AD__RX_SWUS_DROP_VDM0__SHIFT 0x3
+#define PCIE_RX_AD__RX_SWUS_DROP_VDM1__SHIFT 0x4
+#define PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS__SHIFT 0x5
+#define PCIE_RX_AD__RX_RC_DROP_VDM0__SHIFT 0x8
+#define PCIE_RX_AD__RX_RC_UR_VDM0__SHIFT 0x9
+#define PCIE_RX_AD__RX_RC_DROP_VDM1__SHIFT 0xa
+#define PCIE_RX_AD__RX_RC_UR_SSPL_MSG__SHIFT 0xb
+#define PCIE_RX_AD__RX_RC_UR_BFRC_MSG__SHIFT 0xc
+#define PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK__SHIFT 0xd
+#define PCIE_RX_AD__RX_RC_UR_ECRC_DIS__SHIFT 0xe
+#define PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE__SHIFT 0xf
+#define PCIE_RX_AD__RX_SWUS_DROP_PME_TO_MASK 0x00000001L
+#define PCIE_RX_AD__RX_SWUS_DROP_UNLOCK_MASK 0x00000002L
+#define PCIE_RX_AD__RX_SWUS_UR_VDM0_MASK 0x00000004L
+#define PCIE_RX_AD__RX_SWUS_DROP_VDM0_MASK 0x00000008L
+#define PCIE_RX_AD__RX_SWUS_DROP_VDM1_MASK 0x00000010L
+#define PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS_MASK 0x00000020L
+#define PCIE_RX_AD__RX_RC_DROP_VDM0_MASK 0x00000100L
+#define PCIE_RX_AD__RX_RC_UR_VDM0_MASK 0x00000200L
+#define PCIE_RX_AD__RX_RC_DROP_VDM1_MASK 0x00000400L
+#define PCIE_RX_AD__RX_RC_UR_SSPL_MSG_MASK 0x00000800L
+#define PCIE_RX_AD__RX_RC_UR_BFRC_MSG_MASK 0x00001000L
+#define PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK_MASK 0x00002000L
+#define PCIE_RX_AD__RX_RC_UR_ECRC_DIS_MASK 0x00004000L
+#define PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE_MASK 0x00008000L
+//PCIE_SDP_CTRL
+#define PCIE_SDP_CTRL__SDP_UNIT_ID__SHIFT 0x0
+#define PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN__SHIFT 0x4
+#define PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN__SHIFT 0x5
+#define PCIE_SDP_CTRL__CI_MSTSDP_CLKGATE_ONESIDED_ENABLE__SHIFT 0x6
+#define PCIE_SDP_CTRL__TX_RC_TPH_PRIV_DIS__SHIFT 0x7
+#define PCIE_SDP_CTRL__TX_SWUS_TPH_PRIV_DIS__SHIFT 0x8
+#define PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS__SHIFT 0x9
+#define PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS__SHIFT 0xa
+#define PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING__SHIFT 0xb
+#define PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS__SHIFT 0xc
+#define PCIE_SDP_CTRL__CI_MST_MEMR_RD_NONCONT_BE_EN__SHIFT 0xd
+#define PCIE_SDP_CTRL__CI_MSTSDP_DISCONNECT_RSP_ON_PARTIAL__SHIFT 0xe
+#define PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS__SHIFT 0xf
+#define PCIE_SDP_CTRL__SDP_UNIT_ID_MASK 0x0000000FL
+#define PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN_MASK 0x00000010L
+#define PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN_MASK 0x00000020L
+#define PCIE_SDP_CTRL__CI_MSTSDP_CLKGATE_ONESIDED_ENABLE_MASK 0x00000040L
+#define PCIE_SDP_CTRL__TX_RC_TPH_PRIV_DIS_MASK 0x00000080L
+#define PCIE_SDP_CTRL__TX_SWUS_TPH_PRIV_DIS_MASK 0x00000100L
+#define PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS_MASK 0x00000200L
+#define PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS_MASK 0x00000400L
+#define PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING_MASK 0x00000800L
+#define PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS_MASK 0x00001000L
+#define PCIE_SDP_CTRL__CI_MST_MEMR_RD_NONCONT_BE_EN_MASK 0x00002000L
+#define PCIE_SDP_CTRL__CI_MSTSDP_DISCONNECT_RSP_ON_PARTIAL_MASK 0x00004000L
+#define PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS_MASK 0x00008000L
+//PCIE_SDP_SWUS_SLV_ATTR_CTRL
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR__SHIFT 0x0
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD__SHIFT 0x2
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC__SHIFT 0x4
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR__SHIFT 0x6
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD__SHIFT 0x8
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC__SHIFT 0xa
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR__SHIFT 0xc
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD__SHIFT 0xe
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC__SHIFT 0x10
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR_MASK 0x00000003L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD_MASK 0x0000000CL
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC_MASK 0x00000030L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR_MASK 0x000000C0L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD_MASK 0x00000300L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC_MASK 0x00000C00L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR_MASK 0x00003000L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD_MASK 0x0000C000L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC_MASK 0x00030000L
+//PCIE_PERF_COUNT_CNTL
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x00000001L
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x00000002L
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x00000004L
+//PCIE_PERF_CNTL_TXCLK
+#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_TXCLK
+#define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_TXCLK
+#define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_MST_R_CLK
+#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_MST_R_CLK
+#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_MST_R_CLK
+#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_MST_C_CLK
+#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_MST_C_CLK
+#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_MST_C_CLK
+#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_SLV_R_CLK
+#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_SLV_R_CLK
+#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_SLV_R_CLK
+#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_SLV_S_C_CLK
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_SLV_S_C_CLK
+#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_SLV_S_C_CLK
+#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_SLV_NS_C_CLK
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_SLV_NS_C_CLK
+#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_SLV_NS_C_CLK
+#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_EVENT0_PORT_SEL
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0x0000000FL
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0x000000F0L
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0x00000F00L
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0x0000F000L
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0x000F0000L
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0x00F00000L
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0x0F000000L
+//PCIE_PERF_CNTL_EVENT1_PORT_SEL
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0x0000000FL
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0x000000F0L
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0x00000F00L
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0x0000F000L
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0x000F0000L
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0x00F00000L
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0x0F000000L
+//PCIE_PERF_CNTL_TXCLK2
+#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_TXCLK2
+#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_TXCLK2
+#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PRBS_CLR
+#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0
+#define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18
+#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0x0000FFFFL
+#define PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x01000000L
+//PCIE_PRBS_STATUS1
+#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0
+#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10
+#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0x0000FFFFL
+#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xFFFF0000L
+//PCIE_PRBS_STATUS2
+#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0
+#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0x0000FFFFL
+//PCIE_PRBS_FREERUN
+#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0
+#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0x0000FFFFL
+//PCIE_PRBS_MISC
+#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0
+#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1
+#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4
+#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5
+#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6
+#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8
+#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe
+#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10
+#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x00000001L
+#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0x0000000EL
+#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x00000010L
+#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x00000020L
+#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0x000000C0L
+#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x00001F00L
+#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0x0000C000L
+#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xFFFF0000L
+//PCIE_PRBS_USER_PATTERN
+#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0
+#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3FFFFFFFL
+//PCIE_PRBS_LO_BITCNT
+#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0
+#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xFFFFFFFFL
+//PCIE_PRBS_HI_BITCNT
+#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0
+#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0x000000FFL
+//PCIE_PRBS_ERRCNT_0
+#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_1
+#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_2
+#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_3
+#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_4
+#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_5
+#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_6
+#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_7
+#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_8
+#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_9
+#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_10
+#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_11
+#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_12
+#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_13
+#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_14
+#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_15
+#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xFFFFFFFFL
+//SWRST_COMMAND_STATUS
+#define SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0
+#define SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1
+#define SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10
+#define SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET__SHIFT 0x18
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY__SHIFT 0x19
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB__SHIFT 0x1a
+#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET__SHIFT 0x1b
+#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY__SHIFT 0x1c
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET__SHIFT 0x1d
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE__SHIFT 0x1e
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN__SHIFT 0x1f
+#define SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x00000001L
+#define SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x00000002L
+#define SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x00010000L
+#define SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x00020000L
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_MASK 0x01000000L
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY_MASK 0x02000000L
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB_MASK 0x04000000L
+#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_MASK 0x08000000L
+#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY_MASK 0x10000000L
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET_MASK 0x20000000L
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE_MASK 0x40000000L
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN_MASK 0x80000000L
+//SWRST_GENERAL_CONTROL
+#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0
+#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1
+#define SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2
+#define SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8
+#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9
+#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa
+#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc
+#define SWRST_GENERAL_CONTROL__BYPASS_PCS_HOLD__SHIFT 0x11
+#define SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN__SHIFT 0x18
+#define SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET__SHIFT 0x19
+#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x00000001L
+#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x00000002L
+#define SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x0000001CL
+#define SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x00000100L
+#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x00000200L
+#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x00000400L
+#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x00001000L
+#define SWRST_GENERAL_CONTROL__BYPASS_PCS_HOLD_MASK 0x00020000L
+#define SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN_MASK 0x01000000L
+#define SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET_MASK 0x02000000L
+//SWRST_COMMAND_0
+#define SWRST_COMMAND_0__PORT0_COR_RESET__SHIFT 0x0
+#define SWRST_COMMAND_0__PORT0_CFG_RESET__SHIFT 0x8
+#define SWRST_COMMAND_0__PORT1_CFG_RESET__SHIFT 0x9
+#define SWRST_COMMAND_0__PORT2_CFG_RESET__SHIFT 0xa
+#define SWRST_COMMAND_0__PORT3_CFG_RESET__SHIFT 0xb
+#define SWRST_COMMAND_0__PORT4_CFG_RESET__SHIFT 0xc
+#define SWRST_COMMAND_0__PORT5_CFG_RESET__SHIFT 0xd
+#define SWRST_COMMAND_0__PORT6_CFG_RESET__SHIFT 0xe
+#define SWRST_COMMAND_0__PORT7_CFG_RESET__SHIFT 0xf
+#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x18
+#define SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x19
+#define SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x1a
+#define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x1b
+#define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x1c
+#define SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x1d
+#define SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x1e
+#define SWRST_COMMAND_0__PORT0_COR_RESET_MASK 0x00000001L
+#define SWRST_COMMAND_0__PORT0_CFG_RESET_MASK 0x00000100L
+#define SWRST_COMMAND_0__PORT1_CFG_RESET_MASK 0x00000200L
+#define SWRST_COMMAND_0__PORT2_CFG_RESET_MASK 0x00000400L
+#define SWRST_COMMAND_0__PORT3_CFG_RESET_MASK 0x00000800L
+#define SWRST_COMMAND_0__PORT4_CFG_RESET_MASK 0x00001000L
+#define SWRST_COMMAND_0__PORT5_CFG_RESET_MASK 0x00002000L
+#define SWRST_COMMAND_0__PORT6_CFG_RESET_MASK 0x00004000L
+#define SWRST_COMMAND_0__PORT7_CFG_RESET_MASK 0x00008000L
+#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x01000000L
+#define SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x02000000L
+#define SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x04000000L
+#define SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x08000000L
+#define SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x10000000L
+#define SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x20000000L
+#define SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x40000000L
+//SWRST_COMMAND_1
+#define SWRST_COMMAND_1__RESETPCS0__SHIFT 0x0
+#define SWRST_COMMAND_1__RESETPCS1__SHIFT 0x1
+#define SWRST_COMMAND_1__RESETPCS2__SHIFT 0x2
+#define SWRST_COMMAND_1__RESETPCS3__SHIFT 0x3
+#define SWRST_COMMAND_1__RESETPCS4__SHIFT 0x4
+#define SWRST_COMMAND_1__RESETPCS5__SHIFT 0x5
+#define SWRST_COMMAND_1__RESETPCS6__SHIFT 0x6
+#define SWRST_COMMAND_1__RESETPCS7__SHIFT 0x7
+#define SWRST_COMMAND_1__RESETPCS8__SHIFT 0x8
+#define SWRST_COMMAND_1__RESETPCS9__SHIFT 0x9
+#define SWRST_COMMAND_1__RESETPCS10__SHIFT 0xa
+#define SWRST_COMMAND_1__RESETPCS11__SHIFT 0xb
+#define SWRST_COMMAND_1__RESETPCS12__SHIFT 0xc
+#define SWRST_COMMAND_1__RESETPCS13__SHIFT 0xd
+#define SWRST_COMMAND_1__RESETPCS14__SHIFT 0xe
+#define SWRST_COMMAND_1__RESETPCS15__SHIFT 0xf
+#define SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x15
+#define SWRST_COMMAND_1__RESETAXIMST__SHIFT 0x16
+#define SWRST_COMMAND_1__RESETAXISLV__SHIFT 0x17
+#define SWRST_COMMAND_1__RESETAXIINT__SHIFT 0x18
+#define SWRST_COMMAND_1__RESETPCFG__SHIFT 0x19
+#define SWRST_COMMAND_1__RESETLNCT__SHIFT 0x1a
+#define SWRST_COMMAND_1__RESETMNTR__SHIFT 0x1b
+#define SWRST_COMMAND_1__RESETHLTR__SHIFT 0x1c
+#define SWRST_COMMAND_1__RESETCPM__SHIFT 0x1d
+#define SWRST_COMMAND_1__RESETPHY0__SHIFT 0x1e
+#define SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1f
+#define SWRST_COMMAND_1__RESETPCS0_MASK 0x00000001L
+#define SWRST_COMMAND_1__RESETPCS1_MASK 0x00000002L
+#define SWRST_COMMAND_1__RESETPCS2_MASK 0x00000004L
+#define SWRST_COMMAND_1__RESETPCS3_MASK 0x00000008L
+#define SWRST_COMMAND_1__RESETPCS4_MASK 0x00000010L
+#define SWRST_COMMAND_1__RESETPCS5_MASK 0x00000020L
+#define SWRST_COMMAND_1__RESETPCS6_MASK 0x00000040L
+#define SWRST_COMMAND_1__RESETPCS7_MASK 0x00000080L
+#define SWRST_COMMAND_1__RESETPCS8_MASK 0x00000100L
+#define SWRST_COMMAND_1__RESETPCS9_MASK 0x00000200L
+#define SWRST_COMMAND_1__RESETPCS10_MASK 0x00000400L
+#define SWRST_COMMAND_1__RESETPCS11_MASK 0x00000800L
+#define SWRST_COMMAND_1__RESETPCS12_MASK 0x00001000L
+#define SWRST_COMMAND_1__RESETPCS13_MASK 0x00002000L
+#define SWRST_COMMAND_1__RESETPCS14_MASK 0x00004000L
+#define SWRST_COMMAND_1__RESETPCS15_MASK 0x00008000L
+#define SWRST_COMMAND_1__SWITCHCLK_MASK 0x00200000L
+#define SWRST_COMMAND_1__RESETAXIMST_MASK 0x00400000L
+#define SWRST_COMMAND_1__RESETAXISLV_MASK 0x00800000L
+#define SWRST_COMMAND_1__RESETAXIINT_MASK 0x01000000L
+#define SWRST_COMMAND_1__RESETPCFG_MASK 0x02000000L
+#define SWRST_COMMAND_1__RESETLNCT_MASK 0x04000000L
+#define SWRST_COMMAND_1__RESETMNTR_MASK 0x08000000L
+#define SWRST_COMMAND_1__RESETHLTR_MASK 0x10000000L
+#define SWRST_COMMAND_1__RESETCPM_MASK 0x20000000L
+#define SWRST_COMMAND_1__RESETPHY0_MASK 0x40000000L
+#define SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x80000000L
+//SWRST_CONTROL_0
+#define SWRST_CONTROL_0__PORT0_COR_RCEN__SHIFT 0x0
+#define SWRST_CONTROL_0__PORT0_CFG_RCEN__SHIFT 0x8
+#define SWRST_CONTROL_0__PORT1_CFG_RCEN__SHIFT 0x9
+#define SWRST_CONTROL_0__PORT2_CFG_RCEN__SHIFT 0xa
+#define SWRST_CONTROL_0__PORT3_CFG_RCEN__SHIFT 0xb
+#define SWRST_CONTROL_0__PORT4_CFG_RCEN__SHIFT 0xc
+#define SWRST_CONTROL_0__PORT5_CFG_RCEN__SHIFT 0xd
+#define SWRST_CONTROL_0__PORT6_CFG_RCEN__SHIFT 0xe
+#define SWRST_CONTROL_0__PORT7_CFG_RCEN__SHIFT 0xf
+#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x18
+#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x19
+#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x1a
+#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x1b
+#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x1c
+#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x1d
+#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x1e
+#define SWRST_CONTROL_0__PORT0_COR_RCEN_MASK 0x00000001L
+#define SWRST_CONTROL_0__PORT0_CFG_RCEN_MASK 0x00000100L
+#define SWRST_CONTROL_0__PORT1_CFG_RCEN_MASK 0x00000200L
+#define SWRST_CONTROL_0__PORT2_CFG_RCEN_MASK 0x00000400L
+#define SWRST_CONTROL_0__PORT3_CFG_RCEN_MASK 0x00000800L
+#define SWRST_CONTROL_0__PORT4_CFG_RCEN_MASK 0x00001000L
+#define SWRST_CONTROL_0__PORT5_CFG_RCEN_MASK 0x00002000L
+#define SWRST_CONTROL_0__PORT6_CFG_RCEN_MASK 0x00004000L
+#define SWRST_CONTROL_0__PORT7_CFG_RCEN_MASK 0x00008000L
+#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x01000000L
+#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x02000000L
+#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x04000000L
+#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x08000000L
+#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x10000000L
+#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x20000000L
+#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x40000000L
+//SWRST_CONTROL_1
+#define SWRST_CONTROL_1__PCSRESET0_RCEN__SHIFT 0x0
+#define SWRST_CONTROL_1__PCSRESET1_RCEN__SHIFT 0x1
+#define SWRST_CONTROL_1__PCSRESET2_RCEN__SHIFT 0x2
+#define SWRST_CONTROL_1__PCSRESET3_RCEN__SHIFT 0x3
+#define SWRST_CONTROL_1__PCSRESET4_RCEN__SHIFT 0x4
+#define SWRST_CONTROL_1__PCSRESET5_RCEN__SHIFT 0x5
+#define SWRST_CONTROL_1__PCSRESET6_RCEN__SHIFT 0x6
+#define SWRST_CONTROL_1__PCSRESET7_RCEN__SHIFT 0x7
+#define SWRST_CONTROL_1__PCSRESET8_RCEN__SHIFT 0x8
+#define SWRST_CONTROL_1__PCSRESET9_RCEN__SHIFT 0x9
+#define SWRST_CONTROL_1__PCSRESET10_RCEN__SHIFT 0xa
+#define SWRST_CONTROL_1__PCSRESET11_RCEN__SHIFT 0xb
+#define SWRST_CONTROL_1__PCSRESET12_RCEN__SHIFT 0xc
+#define SWRST_CONTROL_1__PCSRESET13_RCEN__SHIFT 0xd
+#define SWRST_CONTROL_1__PCSRESET14_RCEN__SHIFT 0xe
+#define SWRST_CONTROL_1__PCSRESET15_RCEN__SHIFT 0xf
+#define SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x15
+#define SWRST_CONTROL_1__RESETAXIMST_RCEN__SHIFT 0x16
+#define SWRST_CONTROL_1__RESETAXISLV_RCEN__SHIFT 0x17
+#define SWRST_CONTROL_1__RESETAXIINT_RCEN__SHIFT 0x18
+#define SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x19
+#define SWRST_CONTROL_1__RESETLNCT_RCEN__SHIFT 0x1a
+#define SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0x1b
+#define SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0x1c
+#define SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0x1d
+#define SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x1e
+#define SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1f
+#define SWRST_CONTROL_1__PCSRESET0_RCEN_MASK 0x00000001L
+#define SWRST_CONTROL_1__PCSRESET1_RCEN_MASK 0x00000002L
+#define SWRST_CONTROL_1__PCSRESET2_RCEN_MASK 0x00000004L
+#define SWRST_CONTROL_1__PCSRESET3_RCEN_MASK 0x00000008L
+#define SWRST_CONTROL_1__PCSRESET4_RCEN_MASK 0x00000010L
+#define SWRST_CONTROL_1__PCSRESET5_RCEN_MASK 0x00000020L
+#define SWRST_CONTROL_1__PCSRESET6_RCEN_MASK 0x00000040L
+#define SWRST_CONTROL_1__PCSRESET7_RCEN_MASK 0x00000080L
+#define SWRST_CONTROL_1__PCSRESET8_RCEN_MASK 0x00000100L
+#define SWRST_CONTROL_1__PCSRESET9_RCEN_MASK 0x00000200L
+#define SWRST_CONTROL_1__PCSRESET10_RCEN_MASK 0x00000400L
+#define SWRST_CONTROL_1__PCSRESET11_RCEN_MASK 0x00000800L
+#define SWRST_CONTROL_1__PCSRESET12_RCEN_MASK 0x00001000L
+#define SWRST_CONTROL_1__PCSRESET13_RCEN_MASK 0x00002000L
+#define SWRST_CONTROL_1__PCSRESET14_RCEN_MASK 0x00004000L
+#define SWRST_CONTROL_1__PCSRESET15_RCEN_MASK 0x00008000L
+#define SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x00200000L
+#define SWRST_CONTROL_1__RESETAXIMST_RCEN_MASK 0x00400000L
+#define SWRST_CONTROL_1__RESETAXISLV_RCEN_MASK 0x00800000L
+#define SWRST_CONTROL_1__RESETAXIINT_RCEN_MASK 0x01000000L
+#define SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x02000000L
+#define SWRST_CONTROL_1__RESETLNCT_RCEN_MASK 0x04000000L
+#define SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x08000000L
+#define SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x10000000L
+#define SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x20000000L
+#define SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x40000000L
+#define SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x80000000L
+//SWRST_CONTROL_2
+#define SWRST_CONTROL_2__PORT0_COR_ATEN__SHIFT 0x0
+#define SWRST_CONTROL_2__PORT0_CFG_ATEN__SHIFT 0x8
+#define SWRST_CONTROL_2__PORT1_CFG_ATEN__SHIFT 0x9
+#define SWRST_CONTROL_2__PORT2_CFG_ATEN__SHIFT 0xa
+#define SWRST_CONTROL_2__PORT3_CFG_ATEN__SHIFT 0xb
+#define SWRST_CONTROL_2__PORT4_CFG_ATEN__SHIFT 0xc
+#define SWRST_CONTROL_2__PORT5_CFG_ATEN__SHIFT 0xd
+#define SWRST_CONTROL_2__PORT6_CFG_ATEN__SHIFT 0xe
+#define SWRST_CONTROL_2__PORT7_CFG_ATEN__SHIFT 0xf
+#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x18
+#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x19
+#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x1a
+#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x1b
+#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x1c
+#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x1d
+#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x1e
+#define SWRST_CONTROL_2__PORT0_COR_ATEN_MASK 0x00000001L
+#define SWRST_CONTROL_2__PORT0_CFG_ATEN_MASK 0x00000100L
+#define SWRST_CONTROL_2__PORT1_CFG_ATEN_MASK 0x00000200L
+#define SWRST_CONTROL_2__PORT2_CFG_ATEN_MASK 0x00000400L
+#define SWRST_CONTROL_2__PORT3_CFG_ATEN_MASK 0x00000800L
+#define SWRST_CONTROL_2__PORT4_CFG_ATEN_MASK 0x00001000L
+#define SWRST_CONTROL_2__PORT5_CFG_ATEN_MASK 0x00002000L
+#define SWRST_CONTROL_2__PORT6_CFG_ATEN_MASK 0x00004000L
+#define SWRST_CONTROL_2__PORT7_CFG_ATEN_MASK 0x00008000L
+#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x01000000L
+#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x02000000L
+#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x04000000L
+#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x08000000L
+#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x10000000L
+#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x20000000L
+#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x40000000L
+//SWRST_CONTROL_3
+#define SWRST_CONTROL_3__PCSRESET0_ATEN__SHIFT 0x0
+#define SWRST_CONTROL_3__PCSRESET1_ATEN__SHIFT 0x1
+#define SWRST_CONTROL_3__PCSRESET2_ATEN__SHIFT 0x2
+#define SWRST_CONTROL_3__PCSRESET3_ATEN__SHIFT 0x3
+#define SWRST_CONTROL_3__PCSRESET4_ATEN__SHIFT 0x4
+#define SWRST_CONTROL_3__PCSRESET5_ATEN__SHIFT 0x5
+#define SWRST_CONTROL_3__PCSRESET6_ATEN__SHIFT 0x6
+#define SWRST_CONTROL_3__PCSRESET7_ATEN__SHIFT 0x7
+#define SWRST_CONTROL_3__PCSRESET8_ATEN__SHIFT 0x8
+#define SWRST_CONTROL_3__PCSRESET9_ATEN__SHIFT 0x9
+#define SWRST_CONTROL_3__PCSRESET10_ATEN__SHIFT 0xa
+#define SWRST_CONTROL_3__PCSRESET11_ATEN__SHIFT 0xb
+#define SWRST_CONTROL_3__PCSRESET12_ATEN__SHIFT 0xc
+#define SWRST_CONTROL_3__PCSRESET13_ATEN__SHIFT 0xd
+#define SWRST_CONTROL_3__PCSRESET14_ATEN__SHIFT 0xe
+#define SWRST_CONTROL_3__PCSRESET15_ATEN__SHIFT 0xf
+#define SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x15
+#define SWRST_CONTROL_3__RESETAXIMST_ATEN__SHIFT 0x16
+#define SWRST_CONTROL_3__RESETAXISLV_ATEN__SHIFT 0x17
+#define SWRST_CONTROL_3__RESETAXIINT_ATEN__SHIFT 0x18
+#define SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x19
+#define SWRST_CONTROL_3__RESETLNCT_ATEN__SHIFT 0x1a
+#define SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0x1b
+#define SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0x1c
+#define SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0x1d
+#define SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x1e
+#define SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1f
+#define SWRST_CONTROL_3__PCSRESET0_ATEN_MASK 0x00000001L
+#define SWRST_CONTROL_3__PCSRESET1_ATEN_MASK 0x00000002L
+#define SWRST_CONTROL_3__PCSRESET2_ATEN_MASK 0x00000004L
+#define SWRST_CONTROL_3__PCSRESET3_ATEN_MASK 0x00000008L
+#define SWRST_CONTROL_3__PCSRESET4_ATEN_MASK 0x00000010L
+#define SWRST_CONTROL_3__PCSRESET5_ATEN_MASK 0x00000020L
+#define SWRST_CONTROL_3__PCSRESET6_ATEN_MASK 0x00000040L
+#define SWRST_CONTROL_3__PCSRESET7_ATEN_MASK 0x00000080L
+#define SWRST_CONTROL_3__PCSRESET8_ATEN_MASK 0x00000100L
+#define SWRST_CONTROL_3__PCSRESET9_ATEN_MASK 0x00000200L
+#define SWRST_CONTROL_3__PCSRESET10_ATEN_MASK 0x00000400L
+#define SWRST_CONTROL_3__PCSRESET11_ATEN_MASK 0x00000800L
+#define SWRST_CONTROL_3__PCSRESET12_ATEN_MASK 0x00001000L
+#define SWRST_CONTROL_3__PCSRESET13_ATEN_MASK 0x00002000L
+#define SWRST_CONTROL_3__PCSRESET14_ATEN_MASK 0x00004000L
+#define SWRST_CONTROL_3__PCSRESET15_ATEN_MASK 0x00008000L
+#define SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x00200000L
+#define SWRST_CONTROL_3__RESETAXIMST_ATEN_MASK 0x00400000L
+#define SWRST_CONTROL_3__RESETAXISLV_ATEN_MASK 0x00800000L
+#define SWRST_CONTROL_3__RESETAXIINT_ATEN_MASK 0x01000000L
+#define SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x02000000L
+#define SWRST_CONTROL_3__RESETLNCT_ATEN_MASK 0x04000000L
+#define SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x08000000L
+#define SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x10000000L
+#define SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x20000000L
+#define SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x40000000L
+#define SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x80000000L
+//SWRST_CONTROL_4
+#define SWRST_CONTROL_4__PORT0_COR_WREN__SHIFT 0x0
+#define SWRST_CONTROL_4__PORT0_CFG_WREN__SHIFT 0x8
+#define SWRST_CONTROL_4__PORT1_CFG_WREN__SHIFT 0x9
+#define SWRST_CONTROL_4__PORT2_CFG_WREN__SHIFT 0xa
+#define SWRST_CONTROL_4__PORT3_CFG_WREN__SHIFT 0xb
+#define SWRST_CONTROL_4__PORT4_CFG_WREN__SHIFT 0xc
+#define SWRST_CONTROL_4__PORT5_CFG_WREN__SHIFT 0xd
+#define SWRST_CONTROL_4__PORT6_CFG_WREN__SHIFT 0xe
+#define SWRST_CONTROL_4__PORT7_CFG_WREN__SHIFT 0xf
+#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x18
+#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x19
+#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x1a
+#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x1b
+#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x1c
+#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x1d
+#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x1e
+#define SWRST_CONTROL_4__PORT0_COR_WREN_MASK 0x00000001L
+#define SWRST_CONTROL_4__PORT0_CFG_WREN_MASK 0x00000100L
+#define SWRST_CONTROL_4__PORT1_CFG_WREN_MASK 0x00000200L
+#define SWRST_CONTROL_4__PORT2_CFG_WREN_MASK 0x00000400L
+#define SWRST_CONTROL_4__PORT3_CFG_WREN_MASK 0x00000800L
+#define SWRST_CONTROL_4__PORT4_CFG_WREN_MASK 0x00001000L
+#define SWRST_CONTROL_4__PORT5_CFG_WREN_MASK 0x00002000L
+#define SWRST_CONTROL_4__PORT6_CFG_WREN_MASK 0x00004000L
+#define SWRST_CONTROL_4__PORT7_CFG_WREN_MASK 0x00008000L
+#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x01000000L
+#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x02000000L
+#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x04000000L
+#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x08000000L
+#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x10000000L
+#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x20000000L
+#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x40000000L
+//SWRST_CONTROL_5
+#define SWRST_CONTROL_5__PCSRESET0_WREN__SHIFT 0x0
+#define SWRST_CONTROL_5__PCSRESET1_WREN__SHIFT 0x1
+#define SWRST_CONTROL_5__PCSRESET2_WREN__SHIFT 0x2
+#define SWRST_CONTROL_5__PCSRESET3_WREN__SHIFT 0x3
+#define SWRST_CONTROL_5__PCSRESET4_WREN__SHIFT 0x4
+#define SWRST_CONTROL_5__PCSRESET5_WREN__SHIFT 0x5
+#define SWRST_CONTROL_5__PCSRESET6_WREN__SHIFT 0x6
+#define SWRST_CONTROL_5__PCSRESET7_WREN__SHIFT 0x7
+#define SWRST_CONTROL_5__PCSRESET8_WREN__SHIFT 0x8
+#define SWRST_CONTROL_5__PCSRESET9_WREN__SHIFT 0x9
+#define SWRST_CONTROL_5__PCSRESET10_WREN__SHIFT 0xa
+#define SWRST_CONTROL_5__PCSRESET11_WREN__SHIFT 0xb
+#define SWRST_CONTROL_5__PCSRESET12_WREN__SHIFT 0xc
+#define SWRST_CONTROL_5__PCSRESET13_WREN__SHIFT 0xd
+#define SWRST_CONTROL_5__PCSRESET14_WREN__SHIFT 0xe
+#define SWRST_CONTROL_5__PCSRESET15_WREN__SHIFT 0xf
+#define SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x15
+#define SWRST_CONTROL_5__WRRESETAXIMST_EN__SHIFT 0x16
+#define SWRST_CONTROL_5__WRRESETAXISLV_EN__SHIFT 0x17
+#define SWRST_CONTROL_5__WRRESETAXIINT_EN__SHIFT 0x18
+#define SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x19
+#define SWRST_CONTROL_5__WRRESETLNCT_EN__SHIFT 0x1a
+#define SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0x1b
+#define SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0x1c
+#define SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0x1d
+#define SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x1e
+#define SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1f
+#define SWRST_CONTROL_5__PCSRESET0_WREN_MASK 0x00000001L
+#define SWRST_CONTROL_5__PCSRESET1_WREN_MASK 0x00000002L
+#define SWRST_CONTROL_5__PCSRESET2_WREN_MASK 0x00000004L
+#define SWRST_CONTROL_5__PCSRESET3_WREN_MASK 0x00000008L
+#define SWRST_CONTROL_5__PCSRESET4_WREN_MASK 0x00000010L
+#define SWRST_CONTROL_5__PCSRESET5_WREN_MASK 0x00000020L
+#define SWRST_CONTROL_5__PCSRESET6_WREN_MASK 0x00000040L
+#define SWRST_CONTROL_5__PCSRESET7_WREN_MASK 0x00000080L
+#define SWRST_CONTROL_5__PCSRESET8_WREN_MASK 0x00000100L
+#define SWRST_CONTROL_5__PCSRESET9_WREN_MASK 0x00000200L
+#define SWRST_CONTROL_5__PCSRESET10_WREN_MASK 0x00000400L
+#define SWRST_CONTROL_5__PCSRESET11_WREN_MASK 0x00000800L
+#define SWRST_CONTROL_5__PCSRESET12_WREN_MASK 0x00001000L
+#define SWRST_CONTROL_5__PCSRESET13_WREN_MASK 0x00002000L
+#define SWRST_CONTROL_5__PCSRESET14_WREN_MASK 0x00004000L
+#define SWRST_CONTROL_5__PCSRESET15_WREN_MASK 0x00008000L
+#define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x00200000L
+#define SWRST_CONTROL_5__WRRESETAXIMST_EN_MASK 0x00400000L
+#define SWRST_CONTROL_5__WRRESETAXISLV_EN_MASK 0x00800000L
+#define SWRST_CONTROL_5__WRRESETAXIINT_EN_MASK 0x01000000L
+#define SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x02000000L
+#define SWRST_CONTROL_5__WRRESETLNCT_EN_MASK 0x04000000L
+#define SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x08000000L
+#define SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x10000000L
+#define SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x20000000L
+#define SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x40000000L
+#define SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x80000000L
+//SWRST_CONTROL_6
+#define SWRST_CONTROL_6__HOLD_TRAINING_A__SHIFT 0x0
+#define SWRST_CONTROL_6__HOLD_TRAINING_B__SHIFT 0x1
+#define SWRST_CONTROL_6__HOLD_TRAINING_C__SHIFT 0x2
+#define SWRST_CONTROL_6__HOLD_TRAINING_D__SHIFT 0x3
+#define SWRST_CONTROL_6__HOLD_TRAINING_E__SHIFT 0x4
+#define SWRST_CONTROL_6__HOLD_TRAINING_F__SHIFT 0x5
+#define SWRST_CONTROL_6__HOLD_TRAINING_G__SHIFT 0x6
+#define SWRST_CONTROL_6__HOLD_TRAINING_H__SHIFT 0x7
+#define SWRST_CONTROL_6__HOLD_TRAINING_I__SHIFT 0x8
+#define SWRST_CONTROL_6__HOLD_TRAINING_J__SHIFT 0x9
+#define SWRST_CONTROL_6__HOLD_TRAINING_K__SHIFT 0xa
+#define SWRST_CONTROL_6__HOLD_TRAINING_A_MASK 0x00000001L
+#define SWRST_CONTROL_6__HOLD_TRAINING_B_MASK 0x00000002L
+#define SWRST_CONTROL_6__HOLD_TRAINING_C_MASK 0x00000004L
+#define SWRST_CONTROL_6__HOLD_TRAINING_D_MASK 0x00000008L
+#define SWRST_CONTROL_6__HOLD_TRAINING_E_MASK 0x00000010L
+#define SWRST_CONTROL_6__HOLD_TRAINING_F_MASK 0x00000020L
+#define SWRST_CONTROL_6__HOLD_TRAINING_G_MASK 0x00000040L
+#define SWRST_CONTROL_6__HOLD_TRAINING_H_MASK 0x00000080L
+#define SWRST_CONTROL_6__HOLD_TRAINING_I_MASK 0x00000100L
+#define SWRST_CONTROL_6__HOLD_TRAINING_J_MASK 0x00000200L
+#define SWRST_CONTROL_6__HOLD_TRAINING_K_MASK 0x00000400L
+//SWRST_EP_COMMAND_0
+#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY__SHIFT 0x0
+#define SWRST_EP_COMMAND_0__EP_HOT_RESET__SHIFT 0x8
+#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET__SHIFT 0x9
+#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET__SHIFT 0xa
+#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY_MASK 0x00000001L
+#define SWRST_EP_COMMAND_0__EP_HOT_RESET_MASK 0x00000100L
+#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET_MASK 0x00000200L
+#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET_MASK 0x00000400L
+//SWRST_EP_CONTROL_0
+#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN__SHIFT 0x0
+#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN__SHIFT 0x8
+#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN__SHIFT 0x9
+#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN__SHIFT 0xa
+#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN_MASK 0x00000001L
+#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN_MASK 0x00000100L
+#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN_MASK 0x00000200L
+#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN_MASK 0x00000400L
+//CPM_CONTROL
+#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0
+#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1
+#define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2
+#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5
+#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6
+#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7
+#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8
+#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9
+#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xa
+#define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT 0xb
+#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xc
+#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xd
+#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0xe
+#define CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0xf
+#define CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x11
+#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16
+#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17
+#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE__SHIFT 0x18
+#define CPM_CONTROL__SPARE_REGS__SHIFT 0x19
+#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x00000001L
+#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x00000002L
+#define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK 0x00000004L
+#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x00000020L
+#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x00000040L
+#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x00000080L
+#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x00000100L
+#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x00000200L
+#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x00000400L
+#define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK 0x00000800L
+#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x00001000L
+#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x00002000L
+#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x00004000L
+#define CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x00008000L
+#define CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0x000E0000L
+#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x00400000L
+#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x00800000L
+#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK 0x01000000L
+#define CPM_CONTROL__SPARE_REGS_MASK 0xFE000000L
+//SMN_APERTURE_ID_A
+#define SMN_APERTURE_ID_A__SMU_APERTURE_ID__SHIFT 0x0
+#define SMN_APERTURE_ID_A__PCS_APERTURE_ID__SHIFT 0xc
+#define SMN_APERTURE_ID_A__SMU_APERTURE_ID_MASK 0x00000FFFL
+#define SMN_APERTURE_ID_A__PCS_APERTURE_ID_MASK 0x00FFF000L
+//SMN_APERTURE_ID_B
+#define SMN_APERTURE_ID_B__IOHUB_APERTURE_ID__SHIFT 0x0
+#define SMN_APERTURE_ID_B__NBIF_APERTURE_ID__SHIFT 0xc
+#define SMN_APERTURE_ID_B__IOHUB_APERTURE_ID_MASK 0x00000FFFL
+#define SMN_APERTURE_ID_B__NBIF_APERTURE_ID_MASK 0x00FFF000L
+//RSMU_MASTER_CONTROL
+#define RSMU_MASTER_CONTROL__RSMU_MASTER_MESSAGE_SEND_ENABLE__SHIFT 0x0
+#define RSMU_MASTER_CONTROL__RSMU_MASTER_MESSAGE_SEND_ENABLE_MASK 0x00000001L
+//RSMU_SLAVE_CONTROL
+#define RSMU_SLAVE_CONTROL__RSMU_SLAVE_INVALID_READ_RETURN_ZERO__SHIFT 0x0
+#define RSMU_SLAVE_CONTROL__RSMU_SLAVE_IGNORE_INVALID_CONFIG_WRITE__SHIFT 0x2
+#define RSMU_SLAVE_CONTROL__RSMU_SLAVE_INVALID_READ_RETURN_ZERO_MASK 0x00000001L
+#define RSMU_SLAVE_CONTROL__RSMU_SLAVE_IGNORE_INVALID_CONFIG_WRITE_MASK 0x00000004L
+//RSMU_POWER_GATING_CONTROL
+#define RSMU_POWER_GATING_CONTROL__CFG_PG_HYSTERESIS__SHIFT 0x0
+#define RSMU_POWER_GATING_CONTROL__CFG_PG_EN__SHIFT 0x8
+#define RSMU_POWER_GATING_CONTROL__CFG_IDLE_HYSTERESIS__SHIFT 0x9
+#define RSMU_POWER_GATING_CONTROL__CFG_PG_HYSTERESIS_MASK 0x000000FFL
+#define RSMU_POWER_GATING_CONTROL__CFG_PG_EN_MASK 0x00000100L
+#define RSMU_POWER_GATING_CONTROL__CFG_IDLE_HYSTERESIS_MASK 0x00003E00L
+//RSMU_BIOS_TIMER_CMD
+#define RSMU_BIOS_TIMER_CMD__CFG_TMR_MICROSECONDS__SHIFT 0x0
+#define RSMU_BIOS_TIMER_CMD__CFG_TMR_MICROSECONDS_MASK 0xFFFFFFFFL
+//RSMU_BIOS_TIMER_CNTL
+#define RSMU_BIOS_TIMER_CNTL__CFG_TMR_CLOCKRATE__SHIFT 0x0
+#define RSMU_BIOS_TIMER_CNTL__CFG_TMR_CLOCKRATE_MASK 0x000000FFL
+//LNCNT_CONTROL
+#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN__SHIFT 0x0
+#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN__SHIFT 0x1
+#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN__SHIFT 0x2
+#define LNCNT_CONTROL__CFG_LNC_OVRD_EN__SHIFT 0x3
+#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL__SHIFT 0x4
+#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN_MASK 0x00000001L
+#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN_MASK 0x00000002L
+#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN_MASK 0x00000004L
+#define LNCNT_CONTROL__CFG_LNC_OVRD_EN_MASK 0x00000008L
+#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL_MASK 0x00000010L
+//CFG_LNC_WINDOW_REGISTER
+#define CFG_LNC_WINDOW_REGISTER__CFG_LNC_WINDOW__SHIFT 0x0
+#define CFG_LNC_WINDOW_REGISTER__CFG_LNC_WINDOW_MASK 0x00FFFFFFL
+//LNCNT_QUAN_THRD
+#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD__SHIFT 0x0
+#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD__SHIFT 0x4
+#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD_MASK 0x00000007L
+#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD_MASK 0x00000070L
+//LNCNT_WEIGHT
+#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT__SHIFT 0x0
+#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT__SHIFT 0x10
+#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT_MASK 0x0000FFFFL
+#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT_MASK 0xFFFF0000L
+//LNC_TOTAL_WACC_REGISTER
+#define LNC_TOTAL_WACC_REGISTER__LNC_TOTAL_WACC__SHIFT 0x0
+#define LNC_TOTAL_WACC_REGISTER__LNC_TOTAL_WACC_MASK 0xFFFFFFFFL
+//LNC_BW_WACC_REGISTER
+#define LNC_BW_WACC_REGISTER__LNC_BW_WACC__SHIFT 0x0
+#define LNC_BW_WACC_REGISTER__LNC_BW_WACC_MASK 0xFFFFFFFFL
+//LNC_CMN_WACC_REGISTER
+#define LNC_CMN_WACC_REGISTER__LNC_CMN_WACC__SHIFT 0x0
+#define LNC_CMN_WACC_REGISTER__LNC_CMN_WACC_MASK 0xFFFFFFFFL
+//SMU_INT_PIN_SHARING_PORT_INDICATOR
+#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LINK_MANAGEMENT_INT_STATUS__SHIFT 0x0
+#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LTR_INT_STATUS__SHIFT 0x8
+#define SMU_INT_PIN_SHARING_PORT_INDICATOR__DPC_INT_STATUS__SHIFT 0x10
+#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LINK_MANAGEMENT_INT_STATUS_MASK 0x000000FFL
+#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LTR_INT_STATUS_MASK 0x0000FF00L
+#define SMU_INT_PIN_SHARING_PORT_INDICATOR__DPC_INT_STATUS_MASK 0x00FF0000L
+//SMU_PCIE_FENCED1_REG
+#define SMU_PCIE_FENCED1_REG__MP0_PCIE_CROSSFIRE_LOCKDOWN_EN__SHIFT 0x0
+#define SMU_PCIE_FENCED1_REG__MP0_PCIE_CROSSFIRE_LOCKDOWN_EN_MASK 0x00000001L
+//SMU_PCIE_FENCED2_REG
+
+
+// addressBlock: nbio_pipe_pcs_dwc_e12mp_phy_x4_ns0_dwc_e12mp_phy_x4_ns_UP16_dwc_e12mp_phy_x4_ns_UP16_mem_map
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_LO
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_LO__data__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_LO__data_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_HI
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_HI__data__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_HI__data_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK 0x1FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK 0x1FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_REQ_IN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_REQ_OUT__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_ACK_IN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_ACK_OUT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__BG_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__PHY_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_REQ_IN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_REQ_OUT_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_ACK_IN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_ACK_OUT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__BG_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x3FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RX_TERM_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_STAT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_STAT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK 0x7F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK 0x1E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK 0x07FCL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK 0x7F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK 0x1E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK 0x07FCL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__NC40__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__lpn_vreg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__NC40_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__lpn_vreg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__enable_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__cal_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__reset_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_right__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_left__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_vco_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_right_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_left_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_cp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__meas_vreg_vco_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__meas_vreg_l_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vreg_r_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vreg_vp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vreg_cp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_ctl_fine_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_mag_ref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__force_fine_high__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__force_fine_low__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__override_amp_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__override_amp_high__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__override_amp_low__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__atb_select__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__force_fine_high_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__force_fine_low_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__override_amp_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__override_amp_high_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__override_amp_low_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__atb_select_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__NC40__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__lpn_vreg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__NC40_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__lpn_vreg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__enable_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__cal_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__reset_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_right__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_left__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_vco_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_right_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_left_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_cp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__meas_vreg_vco_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__meas_vreg_l_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vreg_r_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vreg_vp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vreg_cp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_ctl_fine_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_mag_ref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__force_fine_high__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__force_fine_low__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__override_amp_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__override_amp_high__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__override_amp_low__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__atb_select__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__force_fine_high_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__force_fine_low_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__override_amp_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__override_amp_high_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__override_amp_low_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__atb_select_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__NC7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__NC7_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK 0x001CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__temp_meas_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__bypass_bg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__vref_sel_fastreg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__chop_en__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__NC74__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__bypass_bg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__vref_sel_fastreg_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__chop_en_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__NC74_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_CONFIG
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT__STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT__STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK 0x0C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x7E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x1F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x1F00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_ERR
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_LD_VAL_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_DATA_MSK
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK 0x7FFEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x1FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_SEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__data_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__data_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vph__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vptx__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vp__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vph_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vptx_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vp_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_gd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vdccm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vdccp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vptx__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__override_regref_0__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vreg0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vreg1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vreg_s__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_gd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vdccm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vdccp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vptx_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__override_regref_0_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vreg0_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vreg1_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vreg_s_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_vcm__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txsm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txsp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txfm__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txfp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_rxdetref__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_nbias__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_pbias__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_vcm_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txsm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txsp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txfm_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txfp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_rxdetref_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_nbias_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_pbias_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__atb_s_enable__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__atb_vboost_vref__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__atb_vboost__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__vboost_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__meas_atb_vph_half_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__atb_s_enable_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__override_vref_boost_ref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__atb_vboost_vref_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__atb_vboost_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__vboost_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__ovrd_vboost_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__iboost_code__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__iboost_code_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__override_regref_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__override_regref_1_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__nc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__osc_pmos__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__osc_nmos__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__override_rxdetref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__nc_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__osc_pmos_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__osc_nmos_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__meas_atb_bias_vptx_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__override_rxdetref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__data_rate_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__los_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__override_regref_slc_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__override_regref_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__meas_atb_rx_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_even_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__NC10__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__NC10_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__NC32__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__NC32_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__shor_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__NC0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__NC0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK 0x007EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__NC20__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__NC20_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__rx_term_gd_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__rx_term_dc_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x7E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x1F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x1F00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_ERR
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_LD_VAL_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_DATA_MSK
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK 0x7FFEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x1FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__data_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__data_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vph__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vptx__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vp__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vph_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vptx_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vp_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_gd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vdccm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vdccp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vptx__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__override_regref_0__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vreg0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vreg1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vreg_s__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_gd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vdccm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vdccp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vptx_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__override_regref_0_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vreg0_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vreg1_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vreg_s_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_vcm__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txsm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txsp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txfm__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txfp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_rxdetref__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_nbias__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_pbias__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_vcm_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txsm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txsp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txfm_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txfp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_rxdetref_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_nbias_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_pbias_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__atb_s_enable__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__atb_vboost_vref__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__atb_vboost__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__vboost_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__meas_atb_vph_half_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__atb_s_enable_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__override_vref_boost_ref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__atb_vboost_vref_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__atb_vboost_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__vboost_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__ovrd_vboost_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__iboost_code__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__iboost_code_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__override_regref_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__override_regref_1_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__nc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__osc_pmos__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__osc_nmos__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__override_rxdetref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__nc_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__osc_pmos_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__osc_nmos_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__meas_atb_bias_vptx_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__override_rxdetref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__data_rate_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__los_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__override_regref_slc_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__override_regref_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__meas_atb_rx_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_even_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__NC10__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__NC10_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__NC32__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__NC32_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__shor_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__NC0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__NC0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK 0x007EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__NC20__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__NC20_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__rx_term_gd_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__rx_term_dc_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x7E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x1F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x1F00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_ERR
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_LD_VAL_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_DATA_MSK
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK 0x7FFEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x1FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__data_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__data_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vph__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vptx__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vp__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vph_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vptx_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vp_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_gd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vdccm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vdccp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vptx__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__override_regref_0__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vreg0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vreg1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vreg_s__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_gd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vdccm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vdccp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vptx_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__override_regref_0_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vreg0_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vreg1_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vreg_s_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_vcm__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txsm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txsp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txfm__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txfp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_rxdetref__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_nbias__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_pbias__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_vcm_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txsm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txsp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txfm_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txfp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_rxdetref_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_nbias_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_pbias_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__atb_s_enable__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__atb_vboost_vref__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__atb_vboost__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__vboost_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__meas_atb_vph_half_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__atb_s_enable_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__override_vref_boost_ref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__atb_vboost_vref_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__atb_vboost_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__vboost_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__ovrd_vboost_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__iboost_code__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__iboost_code_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__override_regref_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__override_regref_1_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__nc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__osc_pmos__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__osc_nmos__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__override_rxdetref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__nc_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__osc_pmos_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__osc_nmos_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__meas_atb_bias_vptx_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__override_rxdetref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__data_rate_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__los_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__override_regref_slc_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__override_regref_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__meas_atb_rx_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_even_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__NC10__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__NC10_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__NC32__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__NC32_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__shor_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__NC0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__NC0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK 0x007EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__NC20__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__NC20_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__rx_term_gd_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__rx_term_dc_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x7E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x1F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x1F00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_ERR
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_LD_VAL_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_DATA_MSK
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK 0x7FFEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x1FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_SEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__data_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__data_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vph__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vptx__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vp__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vph_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vptx_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vp_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_gd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vdccm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vdccp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vptx__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__override_regref_0__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vreg0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vreg1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vreg_s__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_gd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vdccm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vdccp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vptx_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__override_regref_0_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vreg0_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vreg1_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vreg_s_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_vcm__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txsm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txsp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txfm__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txfp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_rxdetref__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_nbias__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_pbias__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_vcm_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txsm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txsp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txfm_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txfp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_rxdetref_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_nbias_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_pbias_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__atb_s_enable__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__atb_vboost_vref__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__atb_vboost__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__vboost_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__meas_atb_vph_half_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__atb_s_enable_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__override_vref_boost_ref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__atb_vboost_vref_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__atb_vboost_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__vboost_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__ovrd_vboost_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__iboost_code__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__iboost_code_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__override_regref_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__override_regref_1_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__nc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__osc_pmos__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__osc_nmos__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__override_rxdetref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__nc_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__osc_pmos_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__osc_nmos_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__meas_atb_bias_vptx_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__override_rxdetref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__data_rate_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__los_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__override_regref_slc_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__override_regref_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__meas_atb_rx_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_even_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__NC10__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__NC10_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__NC32__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__NC32_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__shor_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__NC0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__NC0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK 0x007EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__NC20__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__NC20_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__rx_term_gd_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__rx_term_dc_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_CMN_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK 0x0FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK 0x0FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x0380L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x03F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_SUP
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_LIN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_MAP
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_RX_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_INIT_PWRUP_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_ATT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADAPT_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x0380L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x03F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_SUP
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_LIN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_MAP
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_RX_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_INIT_PWRUP_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_ATT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADAPT_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x0380L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x03F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_SUP
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_LIN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_MAP
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_RX_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_INIT_PWRUP_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_ATT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADAPT_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x0380L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x03F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_SUP
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_LIN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_MAP
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_RX_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_INIT_PWRUP_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_ATT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADAPT_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_LO
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_LO__data__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_LO__data_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_HI
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_HI__data__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_HI__data_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK 0x1FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK 0x1FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_REQ_IN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_REQ_OUT__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_ACK_IN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_ACK_OUT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__BG_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__PHY_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_REQ_IN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_REQ_OUT_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_ACK_IN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_ACK_OUT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__BG_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x3FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RX_TERM_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_STAT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_STAT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK 0x7F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK 0x1E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK 0x07FCL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK 0x7F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK 0x1E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK 0x07FCL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__NC40__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__lpn_vreg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__NC40_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__lpn_vreg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_right__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_left__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_vco_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_right_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_left_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_cp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__meas_vreg_l_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vreg_r_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_mag_ref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__force_fine_high__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__force_fine_low__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__override_amp_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__override_amp_high__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__override_amp_low__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__atb_select__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__force_fine_high_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__force_fine_low_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__override_amp_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__override_amp_high_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__override_amp_low_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__atb_select_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__NC40__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__lpn_vreg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__NC40_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__lpn_vreg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_right__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_left__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_vco_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_right_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_left_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_cp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__meas_vreg_l_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vreg_r_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_mag_ref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__force_fine_high__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__force_fine_low__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__override_amp_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__override_amp_high__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__override_amp_low__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__atb_select__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__force_fine_high_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__force_fine_low_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__override_amp_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__override_amp_high_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__override_amp_low_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__atb_select_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__NC7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__NC7_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK 0x001CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__bypass_bg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__vref_sel_fastreg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__chop_en__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__NC74__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__bypass_bg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__vref_sel_fastreg_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__chop_en_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__NC74_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_CONFIG
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT__STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT__STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK 0x0C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x7E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x1F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x1F00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_ERR
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_LD_VAL_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_DATA_MSK
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK 0x7FFEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x1FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__data_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__data_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vph__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vptx__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vp__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vph_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vptx_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vp_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_gd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vdccm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vdccp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vptx__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__override_regref_0__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vreg0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vreg1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vreg_s__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_gd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vdccm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vdccp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vptx_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__override_regref_0_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vreg0_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vreg1_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vreg_s_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_vcm__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txsm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txsp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txfm__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txfp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_rxdetref__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_nbias__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_pbias__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_vcm_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txsm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txsp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txfm_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txfp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_rxdetref_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_nbias_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_pbias_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__atb_s_enable__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__atb_vboost_vref__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__atb_vboost__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__vboost_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__meas_atb_vph_half_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__atb_s_enable_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__override_vref_boost_ref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__atb_vboost_vref_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__atb_vboost_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__vboost_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__ovrd_vboost_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__iboost_code__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__iboost_code_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__override_regref_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__override_regref_1_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__nc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__osc_pmos__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__osc_nmos__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__override_rxdetref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__nc_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__osc_pmos_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__osc_nmos_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__meas_atb_bias_vptx_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__override_rxdetref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__data_rate_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__los_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__override_regref_slc_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__override_regref_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__meas_atb_rx_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_even_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__NC10__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__NC10_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__NC32__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__NC32_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__shor_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__NC0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__NC0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK 0x007EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__NC20__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__NC20_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__rx_term_gd_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__rx_term_dc_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_CMN_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK 0x0FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK 0x0FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x0380L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x03F0L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_SUP
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_LIN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_MAP
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_RX_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_INIT_PWRUP_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_ATT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADAPT_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+
+
+// addressBlock: nbio_pipe_pcs_lcu_pcie_pcs_prime_phyx4_pcs_prime_dir
+//DXIO_HWDID
+#define DXIO_HWDID__Hardware_Revision__SHIFT 0x0
+#define DXIO_HWDID__Hardware_Minor_Version_Number__SHIFT 0x6
+#define DXIO_HWDID__Hardware_Major_Version_Number__SHIFT 0xd
+#define DXIO_HWDID__Protocol_PCS__SHIFT 0x14
+#define DXIO_HWDID__PCS_Vendor_ID__SHIFT 0x1a
+#define DXIO_HWDID__Hardware_Revision_MASK 0x0000003FL
+#define DXIO_HWDID__Hardware_Minor_Version_Number_MASK 0x00001FC0L
+#define DXIO_HWDID__Hardware_Major_Version_Number_MASK 0x000FE000L
+#define DXIO_HWDID__Protocol_PCS_MASK 0x03F00000L
+#define DXIO_HWDID__PCS_Vendor_ID_MASK 0xFC000000L
+//DXIO_LINKAGE_LANEGRP
+#define DXIO_LINKAGE_LANEGRP__Lane_Group_Indirect_Accesses__SHIFT 0x0
+#define DXIO_LINKAGE_LANEGRP__Lane_Group_Aperture_Size__SHIFT 0x2
+#define DXIO_LINKAGE_LANEGRP__Index_Offset__SHIFT 0x6
+#define DXIO_LINKAGE_LANEGRP__Presence__SHIFT 0x14
+#define DXIO_LINKAGE_LANEGRP__Lane_Group_Indirect_Accesses_MASK 0x00000001L
+#define DXIO_LINKAGE_LANEGRP__Lane_Group_Aperture_Size_MASK 0x0000003CL
+#define DXIO_LINKAGE_LANEGRP__Index_Offset_MASK 0x000FFFC0L
+#define DXIO_LINKAGE_LANEGRP__Presence_MASK 0x0FF00000L
+//DXIO_LINKAGE_KPDMX
+#define DXIO_LINKAGE_KPDMX__Overlay__SHIFT 0x1
+#define DXIO_LINKAGE_KPDMX__Base_Offset__SHIFT 0x6
+#define DXIO_LINKAGE_KPDMX__Presence__SHIFT 0x14
+#define DXIO_LINKAGE_KPDMX__Overlay_MASK 0x00000002L
+#define DXIO_LINKAGE_KPDMX__Base_Offset_MASK 0x000FFFC0L
+#define DXIO_LINKAGE_KPDMX__Presence_MASK 0x0FF00000L
+//DXIO_LINKAGE_KPMX
+#define DXIO_LINKAGE_KPMX__Overlay__SHIFT 0x1
+#define DXIO_LINKAGE_KPMX__Frame_Size__SHIFT 0x2
+#define DXIO_LINKAGE_KPMX__Base_Offset__SHIFT 0x6
+#define DXIO_LINKAGE_KPMX__Overlay_MASK 0x00000002L
+#define DXIO_LINKAGE_KPMX__Frame_Size_MASK 0x0000003CL
+#define DXIO_LINKAGE_KPMX__Base_Offset_MASK 0x000FFFC0L
+//DXIO_LINKAGE_KPFIFO
+#define DXIO_LINKAGE_KPFIFO__Overlay__SHIFT 0x1
+#define DXIO_LINKAGE_KPFIFO__Frame_Size__SHIFT 0x2
+#define DXIO_LINKAGE_KPFIFO__Base_Offset__SHIFT 0x6
+#define DXIO_LINKAGE_KPFIFO__Overlay_MASK 0x00000002L
+#define DXIO_LINKAGE_KPFIFO__Frame_Size_MASK 0x0000003CL
+#define DXIO_LINKAGE_KPFIFO__Base_Offset_MASK 0x000FFFC0L
+//DXIO_LINKAGE_KPNP
+#define DXIO_LINKAGE_KPNP__Overlay__SHIFT 0x1
+#define DXIO_LINKAGE_KPNP__Frame_Size__SHIFT 0x2
+#define DXIO_LINKAGE_KPNP__Base_Offset__SHIFT 0x6
+#define DXIO_LINKAGE_KPNP__Overlay_MASK 0x00000002L
+#define DXIO_LINKAGE_KPNP__Frame_Size_MASK 0x0000003CL
+#define DXIO_LINKAGE_KPNP__Base_Offset_MASK 0x000FFFC0L
+//PCS_LANEGRP0_MAPPING
+#define PCS_LANEGRP0_MAPPING__Lane_Shift__SHIFT 0x0
+#define PCS_LANEGRP0_MAPPING__Target_Mux_Position__SHIFT 0x5
+#define PCS_LANEGRP0_MAPPING__Lane_Connections__SHIFT 0x10
+#define PCS_LANEGRP0_MAPPING__Lane_Shift_MASK 0x0000001FL
+#define PCS_LANEGRP0_MAPPING__Target_Mux_Position_MASK 0x000001E0L
+#define PCS_LANEGRP0_MAPPING__Lane_Connections_MASK 0xFFFF0000L
+//PCS_LANEGRP1_MAPPING
+#define PCS_LANEGRP1_MAPPING__Lane_Shift__SHIFT 0x0
+#define PCS_LANEGRP1_MAPPING__Target_Mux_Position__SHIFT 0x5
+#define PCS_LANEGRP1_MAPPING__Lane_Connections__SHIFT 0x10
+#define PCS_LANEGRP1_MAPPING__Lane_Shift_MASK 0x0000001FL
+#define PCS_LANEGRP1_MAPPING__Target_Mux_Position_MASK 0x000001E0L
+#define PCS_LANEGRP1_MAPPING__Lane_Connections_MASK 0xFFFF0000L
+//PCS_LANEGRP2_MAPPING
+#define PCS_LANEGRP2_MAPPING__Lane_Shift__SHIFT 0x0
+#define PCS_LANEGRP2_MAPPING__Target_Mux_Position__SHIFT 0x5
+#define PCS_LANEGRP2_MAPPING__Lane_Connections__SHIFT 0x10
+#define PCS_LANEGRP2_MAPPING__Lane_Shift_MASK 0x0000001FL
+#define PCS_LANEGRP2_MAPPING__Target_Mux_Position_MASK 0x000001E0L
+#define PCS_LANEGRP2_MAPPING__Lane_Connections_MASK 0xFFFF0000L
+//PCS_LANEGRP3_MAPPING
+#define PCS_LANEGRP3_MAPPING__Lane_Shift__SHIFT 0x0
+#define PCS_LANEGRP3_MAPPING__Target_Mux_Position__SHIFT 0x5
+#define PCS_LANEGRP3_MAPPING__Lane_Connections__SHIFT 0x10
+#define PCS_LANEGRP3_MAPPING__Lane_Shift_MASK 0x0000001FL
+#define PCS_LANEGRP3_MAPPING__Target_Mux_Position_MASK 0x000001E0L
+#define PCS_LANEGRP3_MAPPING__Lane_Connections_MASK 0xFFFF0000L
+//PCS_LANEGRP4_MAPPING
+#define PCS_LANEGRP4_MAPPING__Lane_Shift__SHIFT 0x0
+#define PCS_LANEGRP4_MAPPING__Target_Mux_Position__SHIFT 0x5
+#define PCS_LANEGRP4_MAPPING__Lane_Connections__SHIFT 0x10
+#define PCS_LANEGRP4_MAPPING__Lane_Shift_MASK 0x0000001FL
+#define PCS_LANEGRP4_MAPPING__Target_Mux_Position_MASK 0x000001E0L
+#define PCS_LANEGRP4_MAPPING__Lane_Connections_MASK 0xFFFF0000L
+//PCS_LANEGRP5_MAPPING
+#define PCS_LANEGRP5_MAPPING__Lane_Shift__SHIFT 0x0
+#define PCS_LANEGRP5_MAPPING__Target_Mux_Position__SHIFT 0x5
+#define PCS_LANEGRP5_MAPPING__Lane_Connections__SHIFT 0x10
+#define PCS_LANEGRP5_MAPPING__Lane_Shift_MASK 0x0000001FL
+#define PCS_LANEGRP5_MAPPING__Target_Mux_Position_MASK 0x000001E0L
+#define PCS_LANEGRP5_MAPPING__Lane_Connections_MASK 0xFFFF0000L
+//PCS_LANEGRP6_MAPPING
+#define PCS_LANEGRP6_MAPPING__Lane_Shift__SHIFT 0x0
+#define PCS_LANEGRP6_MAPPING__Target_Mux_Position__SHIFT 0x5
+#define PCS_LANEGRP6_MAPPING__Lane_Connections__SHIFT 0x10
+#define PCS_LANEGRP6_MAPPING__Lane_Shift_MASK 0x0000001FL
+#define PCS_LANEGRP6_MAPPING__Target_Mux_Position_MASK 0x000001E0L
+#define PCS_LANEGRP6_MAPPING__Lane_Connections_MASK 0xFFFF0000L
+//PCS_LANEGRP7_MAPPING
+#define PCS_LANEGRP7_MAPPING__Lane_Shift__SHIFT 0x0
+#define PCS_LANEGRP7_MAPPING__Target_Mux_Position__SHIFT 0x5
+#define PCS_LANEGRP7_MAPPING__Lane_Connections__SHIFT 0x10
+#define PCS_LANEGRP7_MAPPING__Lane_Shift_MASK 0x0000001FL
+#define PCS_LANEGRP7_MAPPING__Target_Mux_Position_MASK 0x000001E0L
+#define PCS_LANEGRP7_MAPPING__Lane_Connections_MASK 0xFFFF0000L
+//MAC_CAPABILITIES1
+#define MAC_CAPABILITIES1__Number_of_Lanes__SHIFT 0x0
+#define MAC_CAPABILITIES1__Number_of_Engines__SHIFT 0x8
+#define MAC_CAPABILITIES1__Number_of_Lanes_MASK 0x0000003FL
+#define MAC_CAPABILITIES1__Number_of_Engines_MASK 0x00003F00L
+//MAC_CAPABILITIES2
+#define MAC_CAPABILITIES2__reserved__SHIFT 0x0
+#define MAC_CAPABILITIES2__reserved_MASK 0x00000001L
+//PCS_CAPABILITIES
+#define PCS_CAPABILITIES__Number_of_Lanes__SHIFT 0x0
+#define PCS_CAPABILITIES__Number_of_Lanes_MASK 0x0000003FL
+//PCS_EXTENDED_CAP
+#define PCS_EXTENDED_CAP__Next_Capability_Pointer__SHIFT 0x2
+#define PCS_EXTENDED_CAP__Next_Capability_Pointer_MASK 0x000FFFFCL
+//PCS_APERTURE0_LOC
+#define PCS_APERTURE0_LOC__PCS_Indirect__SHIFT 0x0
+#define PCS_APERTURE0_LOC__Overlay__SHIFT 0x1
+#define PCS_APERTURE0_LOC__PCS_Aperture_Size__SHIFT 0x2
+#define PCS_APERTURE0_LOC__Aperture_Offset__SHIFT 0x6
+#define PCS_APERTURE0_LOC__PCS_Indirect_MASK 0x00000001L
+#define PCS_APERTURE0_LOC__Overlay_MASK 0x00000002L
+#define PCS_APERTURE0_LOC__PCS_Aperture_Size_MASK 0x0000003CL
+#define PCS_APERTURE0_LOC__Aperture_Offset_MASK 0x000FFFC0L
+//PCS_APERTURE0_IDX
+#define PCS_APERTURE0_IDX__PCS_Index__SHIFT 0x6
+#define PCS_APERTURE0_IDX__PCS_Index_MASK 0xFFFFFFC0L
+//PCS_APERTURE1_LOC
+#define PCS_APERTURE1_LOC__PCS_Indirect__SHIFT 0x0
+#define PCS_APERTURE1_LOC__Overlay__SHIFT 0x1
+#define PCS_APERTURE1_LOC__PCS_Aperture_Size__SHIFT 0x2
+#define PCS_APERTURE1_LOC__Aperture_Offset__SHIFT 0x6
+#define PCS_APERTURE1_LOC__PCS_Indirect_MASK 0x00000001L
+#define PCS_APERTURE1_LOC__Overlay_MASK 0x00000002L
+#define PCS_APERTURE1_LOC__PCS_Aperture_Size_MASK 0x0000003CL
+#define PCS_APERTURE1_LOC__Aperture_Offset_MASK 0x000FFFC0L
+//PCS_APERTURE1_IDX
+#define PCS_APERTURE1_IDX__PCS_Index__SHIFT 0x6
+#define PCS_APERTURE1_IDX__PCS_Index_MASK 0xFFFFFFC0L
+//PCS_APERTURE2_LOC
+#define PCS_APERTURE2_LOC__PCS_Indirect__SHIFT 0x0
+#define PCS_APERTURE2_LOC__Overlay__SHIFT 0x1
+#define PCS_APERTURE2_LOC__PCS_Aperture_Size__SHIFT 0x2
+#define PCS_APERTURE2_LOC__Aperture_Offset__SHIFT 0x6
+#define PCS_APERTURE2_LOC__PCS_Indirect_MASK 0x00000001L
+#define PCS_APERTURE2_LOC__Overlay_MASK 0x00000002L
+#define PCS_APERTURE2_LOC__PCS_Aperture_Size_MASK 0x0000003CL
+#define PCS_APERTURE2_LOC__Aperture_Offset_MASK 0x000FFFC0L
+//PCS_APERTURE2_IDX
+#define PCS_APERTURE2_IDX__PCS_Index__SHIFT 0x6
+#define PCS_APERTURE2_IDX__PCS_Index_MASK 0xFFFFFFC0L
+//PCS_APERTURE3_LOC
+#define PCS_APERTURE3_LOC__PCS_Indirect__SHIFT 0x0
+#define PCS_APERTURE3_LOC__Overlay__SHIFT 0x1
+#define PCS_APERTURE3_LOC__PCS_Aperture_Size__SHIFT 0x2
+#define PCS_APERTURE3_LOC__Aperture_Offset__SHIFT 0x6
+#define PCS_APERTURE3_LOC__PCS_Indirect_MASK 0x00000001L
+#define PCS_APERTURE3_LOC__Overlay_MASK 0x00000002L
+#define PCS_APERTURE3_LOC__PCS_Aperture_Size_MASK 0x0000003CL
+#define PCS_APERTURE3_LOC__Aperture_Offset_MASK 0x000FFFC0L
+//PCS_APERTURE3_IDX
+#define PCS_APERTURE3_IDX__PCS_Index__SHIFT 0x6
+#define PCS_APERTURE3_IDX__PCS_Index_MASK 0xFFFFFFC0L
+//DXIO_CFG_SOFT_RESET
+#define DXIO_CFG_SOFT_RESET__shadow_debug_reset0__SHIFT 0x0
+#define DXIO_CFG_SOFT_RESET__shadow_debug_reset1__SHIFT 0x1
+#define DXIO_CFG_SOFT_RESET__shadow_debug_reset2__SHIFT 0x2
+#define DXIO_CFG_SOFT_RESET__shadow_debug_reset3__SHIFT 0x3
+#define DXIO_CFG_SOFT_RESET__shadow_debug_reset4__SHIFT 0x4
+#define DXIO_CFG_SOFT_RESET__shadow_debug_reset5__SHIFT 0x5
+#define DXIO_CFG_SOFT_RESET__shadow_debug_reset6__SHIFT 0x6
+#define DXIO_CFG_SOFT_RESET__shadow_debug_reset7__SHIFT 0x7
+#define DXIO_CFG_SOFT_RESET__shadow_debug_reset0_MASK 0x00000001L
+#define DXIO_CFG_SOFT_RESET__shadow_debug_reset1_MASK 0x00000002L
+#define DXIO_CFG_SOFT_RESET__shadow_debug_reset2_MASK 0x00000004L
+#define DXIO_CFG_SOFT_RESET__shadow_debug_reset3_MASK 0x00000008L
+#define DXIO_CFG_SOFT_RESET__shadow_debug_reset4_MASK 0x00000010L
+#define DXIO_CFG_SOFT_RESET__shadow_debug_reset5_MASK 0x00000020L
+#define DXIO_CFG_SOFT_RESET__shadow_debug_reset6_MASK 0x00000040L
+#define DXIO_CFG_SOFT_RESET__shadow_debug_reset7_MASK 0x00000080L
+//KPX_LANE_DATA_SOFT_RESET1
+#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset32__SHIFT 0x0
+#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset33__SHIFT 0x1
+#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset34__SHIFT 0x2
+#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset35__SHIFT 0x3
+#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset36__SHIFT 0x4
+#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset37__SHIFT 0x5
+#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset32_MASK 0x00000001L
+#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset33_MASK 0x00000002L
+#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset34_MASK 0x00000004L
+#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset35_MASK 0x00000008L
+#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset36_MASK 0x00000010L
+#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset37_MASK 0x00000020L
+//KPX_LANE_DATA_SOFT_RESET
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset0__SHIFT 0x0
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset1__SHIFT 0x1
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset2__SHIFT 0x2
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset3__SHIFT 0x3
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset4__SHIFT 0x4
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset5__SHIFT 0x5
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset6__SHIFT 0x6
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset7__SHIFT 0x7
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset8__SHIFT 0x8
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset9__SHIFT 0x9
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset10__SHIFT 0xa
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset11__SHIFT 0xb
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset12__SHIFT 0xc
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset13__SHIFT 0xd
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset14__SHIFT 0xe
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset15__SHIFT 0xf
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset16__SHIFT 0x10
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset17__SHIFT 0x11
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset18__SHIFT 0x12
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset19__SHIFT 0x13
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset20__SHIFT 0x14
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset21__SHIFT 0x15
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset22__SHIFT 0x16
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset23__SHIFT 0x17
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset24__SHIFT 0x18
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset25__SHIFT 0x19
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset26__SHIFT 0x1a
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset27__SHIFT 0x1b
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset28__SHIFT 0x1c
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset29__SHIFT 0x1d
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset30__SHIFT 0x1e
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset31__SHIFT 0x1f
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset0_MASK 0x00000001L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset1_MASK 0x00000002L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset2_MASK 0x00000004L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset3_MASK 0x00000008L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset4_MASK 0x00000010L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset5_MASK 0x00000020L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset6_MASK 0x00000040L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset7_MASK 0x00000080L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset8_MASK 0x00000100L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset9_MASK 0x00000200L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset10_MASK 0x00000400L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset11_MASK 0x00000800L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset12_MASK 0x00001000L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset13_MASK 0x00002000L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset14_MASK 0x00004000L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset15_MASK 0x00008000L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset16_MASK 0x00010000L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset17_MASK 0x00020000L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset18_MASK 0x00040000L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset19_MASK 0x00080000L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset20_MASK 0x00100000L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset21_MASK 0x00200000L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset22_MASK 0x00400000L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset23_MASK 0x00800000L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset24_MASK 0x01000000L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset25_MASK 0x02000000L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset26_MASK 0x04000000L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset27_MASK 0x08000000L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset28_MASK 0x10000000L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset29_MASK 0x20000000L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset30_MASK 0x40000000L
+#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset31_MASK 0x80000000L
+//KPX_PMA_INFO_SOFT_RESET
+#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset0__SHIFT 0x10
+#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset1__SHIFT 0x11
+#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset2__SHIFT 0x12
+#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset3__SHIFT 0x13
+#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset4__SHIFT 0x14
+#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset5__SHIFT 0x15
+#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset6__SHIFT 0x16
+#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset7__SHIFT 0x17
+#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset0_MASK 0x00010000L
+#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset1_MASK 0x00020000L
+#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset2_MASK 0x00040000L
+#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset3_MASK 0x00080000L
+#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset4_MASK 0x00100000L
+#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset5_MASK 0x00200000L
+#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset6_MASK 0x00400000L
+#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset7_MASK 0x00800000L
+//PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET
+#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy0__SHIFT 0x0
+#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy1__SHIFT 0x1
+#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy2__SHIFT 0x2
+#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy3__SHIFT 0x3
+#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy4__SHIFT 0x4
+#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy5__SHIFT 0x5
+#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy6__SHIFT 0x6
+#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy7__SHIFT 0x7
+#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy0_MASK 0x00000001L
+#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy1_MASK 0x00000002L
+#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy2_MASK 0x00000004L
+#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy3_MASK 0x00000008L
+#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy4_MASK 0x00000010L
+#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy5_MASK 0x00000020L
+#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy6_MASK 0x00000040L
+#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy7_MASK 0x00000080L
+//PCS_SOFT_RESET
+#define PCS_SOFT_RESET__PCS_Soft_Reset__SHIFT 0x0
+#define PCS_SOFT_RESET__PCS_Soft_Reset_MASK 0x00000001L
+//PCS_LCU_CNTL
+#define PCS_LCU_CNTL__PCS_LCU_PERM_CLKGATE_EN__SHIFT 0x0
+#define PCS_LCU_CNTL__PCS_LCU_POWER_GATING__SHIFT 0x1
+#define PCS_LCU_CNTL__PCS_LCU_DYNAMIC_CLK_EN__SHIFT 0x7
+#define PCS_LCU_CNTL__PCS_LCU_DYNAMIC_CLK_TIMER__SHIFT 0x8
+#define PCS_LCU_CNTL__SMU_INITIATOR_ID__SHIFT 0x10
+#define PCS_LCU_CNTL__SMU_UNIT_ID__SHIFT 0x18
+#define PCS_LCU_CNTL__PCS_LCU_PERM_CLKGATE_EN_MASK 0x00000001L
+#define PCS_LCU_CNTL__PCS_LCU_POWER_GATING_MASK 0x00000002L
+#define PCS_LCU_CNTL__PCS_LCU_DYNAMIC_CLK_EN_MASK 0x00000080L
+#define PCS_LCU_CNTL__PCS_LCU_DYNAMIC_CLK_TIMER_MASK 0x0000FF00L
+#define PCS_LCU_CNTL__SMU_INITIATOR_ID_MASK 0x00FF0000L
+#define PCS_LCU_CNTL__SMU_UNIT_ID_MASK 0x3F000000L
+//PCS_PIPE_PER_LANE_SOFT_RESET
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane0_soft_reset__SHIFT 0x0
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane1_soft_reset__SHIFT 0x1
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane2_soft_reset__SHIFT 0x2
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane3_soft_reset__SHIFT 0x3
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane4_soft_reset__SHIFT 0x4
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane5_soft_reset__SHIFT 0x5
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane6_soft_reset__SHIFT 0x6
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane7_soft_reset__SHIFT 0x7
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane8_soft_reset__SHIFT 0x8
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane9_soft_reset__SHIFT 0x9
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane10_soft_reset__SHIFT 0xa
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane11_soft_reset__SHIFT 0xb
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane12_soft_reset__SHIFT 0xc
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane13_soft_reset__SHIFT 0xd
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane14_soft_reset__SHIFT 0xe
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane15_soft_reset__SHIFT 0xf
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane0_soft_reset_MASK 0x00000001L
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane1_soft_reset_MASK 0x00000002L
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane2_soft_reset_MASK 0x00000004L
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane3_soft_reset_MASK 0x00000008L
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane4_soft_reset_MASK 0x00000010L
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane5_soft_reset_MASK 0x00000020L
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane6_soft_reset_MASK 0x00000040L
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane7_soft_reset_MASK 0x00000080L
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane8_soft_reset_MASK 0x00000100L
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane9_soft_reset_MASK 0x00000200L
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane10_soft_reset_MASK 0x00000400L
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane11_soft_reset_MASK 0x00000800L
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane12_soft_reset_MASK 0x00001000L
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane13_soft_reset_MASK 0x00002000L
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane14_soft_reset_MASK 0x00004000L
+#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane15_soft_reset_MASK 0x00008000L
+
+
+// addressBlock: nbio_lcu_kpfifo_kpfifo0_kpfifo_dir
+//KPFIFO0_PRI_TX_FIFO_HSCID
+#define KPFIFO0_PRI_TX_FIFO_HSCID__HwRev__SHIFT 0x0
+#define KPFIFO0_PRI_TX_FIFO_HSCID__HwMinVer__SHIFT 0x6
+#define KPFIFO0_PRI_TX_FIFO_HSCID__HwMajVer__SHIFT 0xd
+#define KPFIFO0_PRI_TX_FIFO_HSCID__HwRev_MASK 0x0000003FL
+#define KPFIFO0_PRI_TX_FIFO_HSCID__HwMinVer_MASK 0x00001FC0L
+#define KPFIFO0_PRI_TX_FIFO_HSCID__HwMajVer_MASK 0x000FE000L
+//KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__LinkID__SHIFT 0x0
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__FIFORdPtrOffset__SHIFT 0x8
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__FIFODepth__SHIFT 0x10
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__FIFOBypass__SHIFT 0x18
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__FIFOInitMode__SHIFT 0x19
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__Standalone__SHIFT 0x1a
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug0__SHIFT 0x1b
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug1__SHIFT 0x1c
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug2__SHIFT 0x1d
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug3__SHIFT 0x1e
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug4__SHIFT 0x1f
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__LinkID_MASK 0x000000FFL
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__FIFORdPtrOffset_MASK 0x0000FF00L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__FIFODepth_MASK 0x00FF0000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__FIFOBypass_MASK 0x01000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__FIFOInitMode_MASK 0x02000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__Standalone_MASK 0x04000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug0_MASK 0x08000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug1_MASK 0x10000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug2_MASK 0x20000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug3_MASK 0x40000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug4_MASK 0x80000000L
+//KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__LinkID__SHIFT 0x0
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__FIFORdPtrOffset__SHIFT 0x8
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__FIFODepth__SHIFT 0x10
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__FIFOBypass__SHIFT 0x18
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__FIFOInitMode__SHIFT 0x19
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__Standalone__SHIFT 0x1a
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug0__SHIFT 0x1b
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug1__SHIFT 0x1c
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug2__SHIFT 0x1d
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug3__SHIFT 0x1e
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug4__SHIFT 0x1f
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__LinkID_MASK 0x000000FFL
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__FIFORdPtrOffset_MASK 0x0000FF00L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__FIFODepth_MASK 0x00FF0000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__FIFOBypass_MASK 0x01000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__FIFOInitMode_MASK 0x02000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__Standalone_MASK 0x04000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug0_MASK 0x08000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug1_MASK 0x10000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug2_MASK 0x20000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug3_MASK 0x40000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug4_MASK 0x80000000L
+//KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__LinkID__SHIFT 0x0
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__FIFORdPtrOffset__SHIFT 0x8
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__FIFODepth__SHIFT 0x10
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__FIFOBypass__SHIFT 0x18
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__FIFOInitMode__SHIFT 0x19
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__Standalone__SHIFT 0x1a
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug0__SHIFT 0x1b
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug1__SHIFT 0x1c
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug2__SHIFT 0x1d
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug3__SHIFT 0x1e
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug4__SHIFT 0x1f
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__LinkID_MASK 0x000000FFL
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__FIFORdPtrOffset_MASK 0x0000FF00L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__FIFODepth_MASK 0x00FF0000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__FIFOBypass_MASK 0x01000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__FIFOInitMode_MASK 0x02000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__Standalone_MASK 0x04000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug0_MASK 0x08000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug1_MASK 0x10000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug2_MASK 0x20000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug3_MASK 0x40000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug4_MASK 0x80000000L
+//KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__LinkID__SHIFT 0x0
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__FIFORdPtrOffset__SHIFT 0x8
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__FIFODepth__SHIFT 0x10
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__FIFOBypass__SHIFT 0x18
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__FIFOInitMode__SHIFT 0x19
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__Standalone__SHIFT 0x1a
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug0__SHIFT 0x1b
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug1__SHIFT 0x1c
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug2__SHIFT 0x1d
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug3__SHIFT 0x1e
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug4__SHIFT 0x1f
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__LinkID_MASK 0x000000FFL
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__FIFORdPtrOffset_MASK 0x0000FF00L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__FIFODepth_MASK 0x00FF0000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__FIFOBypass_MASK 0x01000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__FIFOInitMode_MASK 0x02000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__Standalone_MASK 0x04000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug0_MASK 0x08000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug1_MASK 0x10000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug2_MASK 0x20000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug3_MASK 0x40000000L
+#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug4_MASK 0x80000000L
+//KPFIFO0_PCS_PMA_SOFT_RESET
+#define KPFIFO0_PCS_PMA_SOFT_RESET__KPFIFO_PHY_soft_ResetPhy__SHIFT 0x0
+#define KPFIFO0_PCS_PMA_SOFT_RESET__KPFIFO_PHY_soft_ResetPhy_MASK 0x00000001L
+
+
+// addressBlock: nbio_lcu_kpnp_kpnp0_kpnp_dir
+//KPNP_SNPS0_KPNP_HWSCVER
+#define KPNP_SNPS0_KPNP_HWSCVER__hw_revision__SHIFT 0x0
+#define KPNP_SNPS0_KPNP_HWSCVER__hw_minor_version_number__SHIFT 0x6
+#define KPNP_SNPS0_KPNP_HWSCVER__hw_major_version_number__SHIFT 0xd
+#define KPNP_SNPS0_KPNP_HWSCVER__hw_revision_MASK 0x0000003FL
+#define KPNP_SNPS0_KPNP_HWSCVER__hw_minor_version_number_MASK 0x00001FC0L
+#define KPNP_SNPS0_KPNP_HWSCVER__hw_major_version_number_MASK 0x000FE000L
+//KPNP_SNPS0_KPNP_PHY_INFO
+#define KPNP_SNPS0_KPNP_PHY_INFO__HwRev__SHIFT 0x0
+#define KPNP_SNPS0_KPNP_PHY_INFO__PHYVer__SHIFT 0x6
+#define KPNP_SNPS0_KPNP_PHY_INFO__Technology__SHIFT 0xd
+#define KPNP_SNPS0_KPNP_PHY_INFO__Type__SHIFT 0x14
+#define KPNP_SNPS0_KPNP_PHY_INFO__VendorID__SHIFT 0x1a
+#define KPNP_SNPS0_KPNP_PHY_INFO__HwRev_MASK 0x0000003FL
+#define KPNP_SNPS0_KPNP_PHY_INFO__PHYVer_MASK 0x00001FC0L
+#define KPNP_SNPS0_KPNP_PHY_INFO__Technology_MASK 0x000FE000L
+#define KPNP_SNPS0_KPNP_PHY_INFO__Type_MASK 0x03F00000L
+#define KPNP_SNPS0_KPNP_PHY_INFO__VendorID_MASK 0xFC000000L
+//KPNP_SNPS0_KPNP_LANE_ID
+#define KPNP_SNPS0_KPNP_LANE_ID__NodeStartLane__SHIFT 0x0
+#define KPNP_SNPS0_KPNP_LANE_ID__NodeEndLane__SHIFT 0x8
+#define KPNP_SNPS0_KPNP_LANE_ID__NodeStartLane_MASK 0x000000FFL
+#define KPNP_SNPS0_KPNP_LANE_ID__NodeEndLane_MASK 0x0000FF00L
+//KPNP_SNPS0_KPNP_LANE_REQ_CONTROL
+#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln0TxReq__SHIFT 0x0
+#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln0RxReq__SHIFT 0x1
+#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln1TxReq__SHIFT 0x2
+#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln1RxReq__SHIFT 0x3
+#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln2TxReq__SHIFT 0x4
+#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln2RxReq__SHIFT 0x5
+#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln3TxReq__SHIFT 0x6
+#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln3RxReq__SHIFT 0x7
+#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln0TxReq_MASK 0x00000001L
+#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln0RxReq_MASK 0x00000002L
+#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln1TxReq_MASK 0x00000004L
+#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln1RxReq_MASK 0x00000008L
+#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln2TxReq_MASK 0x00000010L
+#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln2RxReq_MASK 0x00000020L
+#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln3TxReq_MASK 0x00000040L
+#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln3RxReq_MASK 0x00000080L
+//KPNP_SNPS0_KPNP_LANE_REQ_STATUS
+#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln0TxAck__SHIFT 0x0
+#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln0RxAck__SHIFT 0x1
+#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln1TxAck__SHIFT 0x2
+#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln1RxAck__SHIFT 0x3
+#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln2TxAck__SHIFT 0x4
+#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln2RxAck__SHIFT 0x5
+#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln3TxAck__SHIFT 0x6
+#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln3RxAck__SHIFT 0x7
+#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln0TxAck_MASK 0x00000001L
+#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln0RxAck_MASK 0x00000002L
+#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln1TxAck_MASK 0x00000004L
+#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln1RxAck_MASK 0x00000008L
+#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln2TxAck_MASK 0x00000010L
+#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln2RxAck_MASK 0x00000020L
+#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln3TxAck_MASK 0x00000040L
+#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln3RxAck_MASK 0x00000080L
+//KPNP_SNPS0_KPNP_PMA_CONTROL0
+#define KPNP_SNPS0_KPNP_PMA_CONTROL0__ref_use_pad__SHIFT 0x0
+#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln0_Tx_Disable__SHIFT 0x10
+#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln0_Rx_Disable__SHIFT 0x11
+#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln1_Tx_Disable__SHIFT 0x12
+#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln1_Rx_Disable__SHIFT 0x13
+#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln2_Tx_Disable__SHIFT 0x14
+#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln2_Rx_Disable__SHIFT 0x15
+#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln3_Tx_Disable__SHIFT 0x16
+#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln3_Rx_Disable__SHIFT 0x17
+#define KPNP_SNPS0_KPNP_PMA_CONTROL0__ref_use_pad_MASK 0x00000001L
+#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln0_Tx_Disable_MASK 0x00010000L
+#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln0_Rx_Disable_MASK 0x00020000L
+#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln1_Tx_Disable_MASK 0x00040000L
+#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln1_Rx_Disable_MASK 0x00080000L
+#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln2_Tx_Disable_MASK 0x00100000L
+#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln2_Rx_Disable_MASK 0x00200000L
+#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln3_Tx_Disable_MASK 0x00400000L
+#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln3_Rx_Disable_MASK 0x00800000L
+//KPNP_SNPS0_KPNP_PMA_CONTROL1
+#define KPNP_SNPS0_KPNP_PMA_CONTROL1__rx_vref_ctrl__SHIFT 0x0
+#define KPNP_SNPS0_KPNP_PMA_CONTROL1__tx_vboost_lvl__SHIFT 0x5
+#define KPNP_SNPS0_KPNP_PMA_CONTROL1__rx_vref_ctrl_MASK 0x0000001FL
+#define KPNP_SNPS0_KPNP_PMA_CONTROL1__tx_vboost_lvl_MASK 0x000000E0L
+//KPNP_SNPS0_KPNP_PMA_CONTROL2
+#define KPNP_SNPS0_KPNP_PMA_CONTROL2__Staggering_Disable__SHIFT 0x0
+#define KPNP_SNPS0_KPNP_PMA_CONTROL2__Staggering_Mode__SHIFT 0x1
+#define KPNP_SNPS0_KPNP_PMA_CONTROL2__Staggering_Time_Resolution__SHIFT 0x2
+#define KPNP_SNPS0_KPNP_PMA_CONTROL2__Staggering_Disable_MASK 0x00000001L
+#define KPNP_SNPS0_KPNP_PMA_CONTROL2__Staggering_Mode_MASK 0x00000002L
+#define KPNP_SNPS0_KPNP_PMA_CONTROL2__Staggering_Time_Resolution_MASK 0x0000001CL
+//KPNP_SNPS0_KPNP_PHY_SOFT_RESET
+#define KPNP_SNPS0_KPNP_PHY_SOFT_RESET__Phy_Soft_Reset__SHIFT 0x0
+#define KPNP_SNPS0_KPNP_PHY_SOFT_RESET__Phy_Soft_Reset_MASK 0x00000001L
+//KPNP_SNPS0_KPNP_LANE_SOFT_RESET
+#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln0_Tx_Soft_Reset__SHIFT 0x0
+#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln0_Rx_Soft_Reset__SHIFT 0x1
+#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln1_Tx_Soft_Reset__SHIFT 0x2
+#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln1_Rx_Soft_Reset__SHIFT 0x3
+#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln2_Tx_Soft_Reset__SHIFT 0x4
+#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln2_Rx_Soft_Reset__SHIFT 0x5
+#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln3_Tx_Soft_Reset__SHIFT 0x6
+#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln3_Rx_Soft_Reset__SHIFT 0x7
+#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln0_Tx_Soft_Reset_MASK 0x00000001L
+#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln0_Rx_Soft_Reset_MASK 0x00000002L
+#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln1_Tx_Soft_Reset_MASK 0x00000004L
+#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln1_Rx_Soft_Reset_MASK 0x00000008L
+#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln2_Tx_Soft_Reset_MASK 0x00000010L
+#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln2_Rx_Soft_Reset_MASK 0x00000020L
+#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln3_Tx_Soft_Reset_MASK 0x00000040L
+#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln3_Rx_Soft_Reset_MASK 0x00000080L
+//KPNP_SNPS0_REG_RST_CTRL
+#define KPNP_SNPS0_REG_RST_CTRL__reset_regs_when_dxio_phy_rst__SHIFT 0x0
+#define KPNP_SNPS0_REG_RST_CTRL__reset_regs_when_dxio_phy_rst_MASK 0x00000001L
+
+
+// addressBlock: nbio_pipe_pcs_pcs_core0_dir
+//PCS_PCIEX16_IP_IDENTITY
+#define PCS_PCIEX16_IP_IDENTITY__IP_IDENTITY__SHIFT 0x0
+#define PCS_PCIEX16_IP_IDENTITY__IP_IDENTITY_MASK 0xFFFFFFFFL
+//PCS_PCIEX16_GLOBAL_CONTROL0
+#define PCS_PCIEX16_GLOBAL_CONTROL0__InitHardware__SHIFT 0x0
+#define PCS_PCIEX16_GLOBAL_CONTROL0__InitComplete__SHIFT 0x1
+#define PCS_PCIEX16_GLOBAL_CONTROL0__EIDetectorCycle__SHIFT 0x2
+#define PCS_PCIEX16_GLOBAL_CONTROL0__EIDetectorOnTime__SHIFT 0x4
+#define PCS_PCIEX16_GLOBAL_CONTROL0__VoltageDimmingEnDuringEIDetectorOnTime__SHIFT 0xe
+#define PCS_PCIEX16_GLOBAL_CONTROL0__VoltageDimmingEnDuringEIDetectorOffTime__SHIFT 0xf
+#define PCS_PCIEX16_GLOBAL_CONTROL0__VoltageDimmingTransitionTime__SHIFT 0x10
+#define PCS_PCIEX16_GLOBAL_CONTROL0__EIDetectorOffTime__SHIFT 0x14
+#define PCS_PCIEX16_GLOBAL_CONTROL0__InitHardware_MASK 0x00000001L
+#define PCS_PCIEX16_GLOBAL_CONTROL0__InitComplete_MASK 0x00000002L
+#define PCS_PCIEX16_GLOBAL_CONTROL0__EIDetectorCycle_MASK 0x00000004L
+#define PCS_PCIEX16_GLOBAL_CONTROL0__EIDetectorOnTime_MASK 0x00003FF0L
+#define PCS_PCIEX16_GLOBAL_CONTROL0__VoltageDimmingEnDuringEIDetectorOnTime_MASK 0x00004000L
+#define PCS_PCIEX16_GLOBAL_CONTROL0__VoltageDimmingEnDuringEIDetectorOffTime_MASK 0x00008000L
+#define PCS_PCIEX16_GLOBAL_CONTROL0__VoltageDimmingTransitionTime_MASK 0x000F0000L
+#define PCS_PCIEX16_GLOBAL_CONTROL0__EIDetectorOffTime_MASK 0x3FF00000L
+//PCS_PCIEX16_GLOBAL_CONTROL1
+#define PCS_PCIEX16_GLOBAL_CONTROL1__DefaultPCLKFrequency__SHIFT 0x0
+#define PCS_PCIEX16_GLOBAL_CONTROL1__DefaultMaximumLinkRate__SHIFT 0x2
+#define PCS_PCIEX16_GLOBAL_CONTROL1__MasterPLL__SHIFT 0x4
+#define PCS_PCIEX16_GLOBAL_CONTROL1__MasterPLLAuto__SHIFT 0x8
+#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxActivePowerGating__SHIFT 0x9
+#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxActivePowerGating__SHIFT 0xa
+#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxInactivePowerGating__SHIFT 0xb
+#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxInactivePowerGating__SHIFT 0xc
+#define PCS_PCIEX16_GLOBAL_CONTROL1__EnableTxSSClkGating__SHIFT 0xd
+#define PCS_PCIEX16_GLOBAL_CONTROL1__EnableMaxPClkGating__SHIFT 0xe
+#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxPS2__SHIFT 0x10
+#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxPS3__SHIFT 0x11
+#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxPS2__SHIFT 0x12
+#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxPS3__SHIFT 0x13
+#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowPLLShutdownRxPS2__SHIFT 0x15
+#define PCS_PCIEX16_GLOBAL_CONTROL1__PLLActiveAbovePS4__SHIFT 0x18
+#define PCS_PCIEX16_GLOBAL_CONTROL1__PLLActiveInPS4__SHIFT 0x19
+#define PCS_PCIEX16_GLOBAL_CONTROL1__DisableRxPS4__SHIFT 0x1a
+#define PCS_PCIEX16_GLOBAL_CONTROL1__DisableTxPS4__SHIFT 0x1b
+#define PCS_PCIEX16_GLOBAL_CONTROL1__DisableTxPS4inRxPS3__SHIFT 0x1c
+#define PCS_PCIEX16_GLOBAL_CONTROL1__RemapSATAP6TOP5__SHIFT 0x1d
+#define PCS_PCIEX16_GLOBAL_CONTROL1__FarEndAnalogLoopbackEnable__SHIFT 0x1f
+#define PCS_PCIEX16_GLOBAL_CONTROL1__DefaultPCLKFrequency_MASK 0x00000003L
+#define PCS_PCIEX16_GLOBAL_CONTROL1__DefaultMaximumLinkRate_MASK 0x0000000CL
+#define PCS_PCIEX16_GLOBAL_CONTROL1__MasterPLL_MASK 0x000000F0L
+#define PCS_PCIEX16_GLOBAL_CONTROL1__MasterPLLAuto_MASK 0x00000100L
+#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxActivePowerGating_MASK 0x00000200L
+#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxActivePowerGating_MASK 0x00000400L
+#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxInactivePowerGating_MASK 0x00000800L
+#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxInactivePowerGating_MASK 0x00001000L
+#define PCS_PCIEX16_GLOBAL_CONTROL1__EnableTxSSClkGating_MASK 0x00002000L
+#define PCS_PCIEX16_GLOBAL_CONTROL1__EnableMaxPClkGating_MASK 0x00004000L
+#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxPS2_MASK 0x00010000L
+#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxPS3_MASK 0x00020000L
+#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxPS2_MASK 0x00040000L
+#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxPS3_MASK 0x00080000L
+#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowPLLShutdownRxPS2_MASK 0x00200000L
+#define PCS_PCIEX16_GLOBAL_CONTROL1__PLLActiveAbovePS4_MASK 0x01000000L
+#define PCS_PCIEX16_GLOBAL_CONTROL1__PLLActiveInPS4_MASK 0x02000000L
+#define PCS_PCIEX16_GLOBAL_CONTROL1__DisableRxPS4_MASK 0x04000000L
+#define PCS_PCIEX16_GLOBAL_CONTROL1__DisableTxPS4_MASK 0x08000000L
+#define PCS_PCIEX16_GLOBAL_CONTROL1__DisableTxPS4inRxPS3_MASK 0x10000000L
+#define PCS_PCIEX16_GLOBAL_CONTROL1__RemapSATAP6TOP5_MASK 0x20000000L
+#define PCS_PCIEX16_GLOBAL_CONTROL1__FarEndAnalogLoopbackEnable_MASK 0x80000000L
+//PCS_PCIEX16_GLOBAL_CONTROL2
+#define PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYReceiverOntime__SHIFT 0x0
+#define PCS_PCIEX16_GLOBAL_CONTROL2__ElasticFIFONominalHalfOffset__SHIFT 0xc
+#define PCS_PCIEX16_GLOBAL_CONTROL2__AllowFrequencyVetting__SHIFT 0xe
+#define PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYReferenceClockFrequency__SHIFT 0x10
+#define PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYReferenceClockFrequencyStatus__SHIFT 0x11
+#define PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYFifoInitWaitTime__SHIFT 0x12
+#define PCS_PCIEX16_GLOBAL_CONTROL2__MinimumNumberofEISymbols__SHIFT 0x14
+#define PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYReceiverOntime_MASK 0x000003FFL
+#define PCS_PCIEX16_GLOBAL_CONTROL2__ElasticFIFONominalHalfOffset_MASK 0x00003000L
+#define PCS_PCIEX16_GLOBAL_CONTROL2__AllowFrequencyVetting_MASK 0x00004000L
+#define PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYReferenceClockFrequency_MASK 0x00010000L
+#define PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYReferenceClockFrequencyStatus_MASK 0x00020000L
+#define PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYFifoInitWaitTime_MASK 0x000C0000L
+#define PCS_PCIEX16_GLOBAL_CONTROL2__MinimumNumberofEISymbols_MASK 0x00300000L
+//PCS_PCIEX16_GLOBAL_CONTROL3
+#define PCS_PCIEX16_GLOBAL_CONTROL3__SERDESPHYPLLTransitionTime__SHIFT 0x0
+#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowBypassingTxRdy__SHIFT 0x10
+#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowBypassingRxRdy__SHIFT 0x11
+#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowBypassingRxStandbyRxRdy__SHIFT 0x12
+#define PCS_PCIEX16_GLOBAL_CONTROL3__DisableMultiLaneBinding__SHIFT 0x13
+#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowDummyAckOnClockSwitchRequest__SHIFT 0x14
+#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowDummyAckOnGateUngatePCLKRequest__SHIFT 0x18
+#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowDummyAckOnSpeedChangeRequest__SHIFT 0x19
+#define PCS_PCIEX16_GLOBAL_CONTROL3__SERDESPHYPLLTransitionTime_MASK 0x0000003FL
+#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowBypassingTxRdy_MASK 0x00010000L
+#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowBypassingRxRdy_MASK 0x00020000L
+#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowBypassingRxStandbyRxRdy_MASK 0x00040000L
+#define PCS_PCIEX16_GLOBAL_CONTROL3__DisableMultiLaneBinding_MASK 0x00080000L
+#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowDummyAckOnClockSwitchRequest_MASK 0x00100000L
+#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowDummyAckOnGateUngatePCLKRequest_MASK 0x01000000L
+#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowDummyAckOnSpeedChangeRequest_MASK 0x02000000L
+//PCS_PCIEX16_GLOBAL_CONTROL4
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_EN__SHIFT 0x0
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_TEST_MODE__SHIFT 0x1
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_8BIT_SEL__SHIFT 0x5
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_COMMA_NUM__SHIFT 0x6
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_LOCK_CNT__SHIFT 0x8
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_FREERUN__SHIFT 0xd
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_DATA_RATE__SHIFT 0xe
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_LANE_SELECT__SHIFT 0x10
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_POLARITY_EN__SHIFT 0x14
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_CLR__SHIFT 0x15
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_DATA_WIDTH__SHIFT 0x16
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_BYPASS_SYMALIGN__SHIFT 0x18
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_RESERVED__SHIFT 0x19
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_EN_MASK 0x00000001L
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_TEST_MODE_MASK 0x0000000EL
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_USER_PATTERN_TOGGLE_MASK 0x00000010L
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_8BIT_SEL_MASK 0x00000020L
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_COMMA_NUM_MASK 0x000000C0L
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_LOCK_CNT_MASK 0x00001F00L
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_FREERUN_MASK 0x00002000L
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_DATA_RATE_MASK 0x0000C000L
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_LANE_SELECT_MASK 0x000F0000L
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_POLARITY_EN_MASK 0x00100000L
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_CLR_MASK 0x00200000L
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_DATA_WIDTH_MASK 0x00C00000L
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_BYPASS_SYMALIGN_MASK 0x01000000L
+#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_RESERVED_MASK 0xFE000000L
+//PCS_PCIEX16_GLOBAL_CONTROL5
+#define PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_CHK_ERR_MASK__SHIFT 0x0
+#define PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_LOCKED__SHIFT 0x8
+#define PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_ERRSTAT__SHIFT 0x10
+#define PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_BITCNT_DONE__SHIFT 0x18
+#define PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_CHK_ERR_MASK_MASK 0x000000FFL
+#define PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_LOCKED_MASK 0x0000FF00L
+#define PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_ERRSTAT_MASK 0x00FF0000L
+#define PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_BITCNT_DONE_MASK 0xFF000000L
+//PCS_PCIEX16_GLOBAL_CONTROL6
+#define PCS_PCIEX16_GLOBAL_CONTROL6__PRBS_USER_PATTERN__SHIFT 0x0
+#define PCS_PCIEX16_GLOBAL_CONTROL6__PRBS_USER_PATTERN_MASK 0x3FFFFFFFL
+//PCS_PCIEX16_GLOBAL_CONTROL7
+#define PCS_PCIEX16_GLOBAL_CONTROL7__PRBS_BITCNT__SHIFT 0x0
+#define PCS_PCIEX16_GLOBAL_CONTROL7__PRBS_BITCNT_MASK 0xFFFFFFFFL
+//PCS_PCIEX16_GLOBAL_CONTROL8
+#define PCS_PCIEX16_GLOBAL_CONTROL8__PRBS_REGS_ERRCNT__SHIFT 0x0
+#define PCS_PCIEX16_GLOBAL_CONTROL8__PRBS_REGS_ERRCNT_MASK 0xFFFFFFFFL
+//PCS_PCIEX16_LANE0_CONTROL
+#define PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_LogicalLinkNumber__SHIFT 0x0
+#define PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_MasterPLLMask__SHIFT 0x4
+#define PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_EnablePClkGating__SHIFT 0x5
+#define PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_LFPSPolarity__SHIFT 0x10
+#define PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_LogicalLinkNumber_MASK 0x0000000FL
+#define PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_MasterPLLMask_MASK 0x00000010L
+#define PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_EnablePClkGating_MASK 0x00000020L
+#define PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_LFPSPolarity_MASK 0x00010000L
+//PCS_PCIEX16_LANE1_CONTROL
+#define PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_LogicalLinkNumber__SHIFT 0x0
+#define PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_MasterPLLMask__SHIFT 0x4
+#define PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_EnablePClkGating__SHIFT 0x5
+#define PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_LFPSPolarity__SHIFT 0x10
+#define PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_LogicalLinkNumber_MASK 0x0000000FL
+#define PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_MasterPLLMask_MASK 0x00000010L
+#define PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_EnablePClkGating_MASK 0x00000020L
+#define PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_LFPSPolarity_MASK 0x00010000L
+//PCS_PCIEX16_LANE2_CONTROL
+#define PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_LogicalLinkNumber__SHIFT 0x0
+#define PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_MasterPLLMask__SHIFT 0x4
+#define PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_EnablePClkGating__SHIFT 0x5
+#define PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_LFPSPolarity__SHIFT 0x10
+#define PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_LogicalLinkNumber_MASK 0x0000000FL
+#define PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_MasterPLLMask_MASK 0x00000010L
+#define PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_EnablePClkGating_MASK 0x00000020L
+#define PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_LFPSPolarity_MASK 0x00010000L
+//PCS_PCIEX16_LANE3_CONTROL
+#define PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_LogicalLinkNumber__SHIFT 0x0
+#define PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_MasterPLLMask__SHIFT 0x4
+#define PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_EnablePClkGating__SHIFT 0x5
+#define PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_LFPSPolarity__SHIFT 0x10
+#define PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_LogicalLinkNumber_MASK 0x0000000FL
+#define PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_MasterPLLMask_MASK 0x00000010L
+#define PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_EnablePClkGating_MASK 0x00000020L
+#define PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_LFPSPolarity_MASK 0x00010000L
+//PCS_PCIEX16_LANE4_CONTROL
+#define PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_LogicalLinkNumber__SHIFT 0x0
+#define PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_MasterPLLMask__SHIFT 0x4
+#define PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_EnablePClkGating__SHIFT 0x5
+#define PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_LFPSPolarity__SHIFT 0x10
+#define PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_LogicalLinkNumber_MASK 0x0000000FL
+#define PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_MasterPLLMask_MASK 0x00000010L
+#define PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_EnablePClkGating_MASK 0x00000020L
+#define PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_LFPSPolarity_MASK 0x00010000L
+//PCS_PCIEX16_LANE5_CONTROL
+#define PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_LogicalLinkNumber__SHIFT 0x0
+#define PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_MasterPLLMask__SHIFT 0x4
+#define PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_EnablePClkGating__SHIFT 0x5
+#define PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_LFPSPolarity__SHIFT 0x10
+#define PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_LogicalLinkNumber_MASK 0x0000000FL
+#define PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_MasterPLLMask_MASK 0x00000010L
+#define PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_EnablePClkGating_MASK 0x00000020L
+#define PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_LFPSPolarity_MASK 0x00010000L
+//PCS_PCIEX16_LANE6_CONTROL
+#define PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_LogicalLinkNumber__SHIFT 0x0
+#define PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_MasterPLLMask__SHIFT 0x4
+#define PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_EnablePClkGating__SHIFT 0x5
+#define PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_LFPSPolarity__SHIFT 0x10
+#define PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_LogicalLinkNumber_MASK 0x0000000FL
+#define PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_MasterPLLMask_MASK 0x00000010L
+#define PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_EnablePClkGating_MASK 0x00000020L
+#define PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_LFPSPolarity_MASK 0x00010000L
+//PCS_PCIEX16_LANE7_CONTROL
+#define PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_LogicalLinkNumber__SHIFT 0x0
+#define PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_MasterPLLMask__SHIFT 0x4
+#define PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_EnablePClkGating__SHIFT 0x5
+#define PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_LFPSPolarity__SHIFT 0x10
+#define PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_LogicalLinkNumber_MASK 0x0000000FL
+#define PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_MasterPLLMask_MASK 0x00000010L
+#define PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_EnablePClkGating_MASK 0x00000020L
+#define PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_LFPSPolarity_MASK 0x00010000L
+//PCS_PCIEX16_LANE8_CONTROL
+#define PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_LogicalLinkNumber__SHIFT 0x0
+#define PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_MasterPLLMask__SHIFT 0x4
+#define PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_EnablePClkGating__SHIFT 0x5
+#define PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_LFPSPolarity__SHIFT 0x10
+#define PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_LogicalLinkNumber_MASK 0x0000000FL
+#define PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_MasterPLLMask_MASK 0x00000010L
+#define PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_EnablePClkGating_MASK 0x00000020L
+#define PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_LFPSPolarity_MASK 0x00010000L
+//PCS_PCIEX16_LANE9_CONTROL
+#define PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_LogicalLinkNumber__SHIFT 0x0
+#define PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_MasterPLLMask__SHIFT 0x4
+#define PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_EnablePClkGating__SHIFT 0x5
+#define PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_LFPSPolarity__SHIFT 0x10
+#define PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_LogicalLinkNumber_MASK 0x0000000FL
+#define PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_MasterPLLMask_MASK 0x00000010L
+#define PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_EnablePClkGating_MASK 0x00000020L
+#define PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_LFPSPolarity_MASK 0x00010000L
+//PCS_PCIEX16_LANE10_CONTROL
+#define PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_LogicalLinkNumber__SHIFT 0x0
+#define PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_MasterPLLMask__SHIFT 0x4
+#define PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_EnablePClkGating__SHIFT 0x5
+#define PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_LFPSPolarity__SHIFT 0x10
+#define PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_LogicalLinkNumber_MASK 0x0000000FL
+#define PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_MasterPLLMask_MASK 0x00000010L
+#define PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_EnablePClkGating_MASK 0x00000020L
+#define PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_LFPSPolarity_MASK 0x00010000L
+//PCS_PCIEX16_LANE11_CONTROL
+#define PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_LogicalLinkNumber__SHIFT 0x0
+#define PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_MasterPLLMask__SHIFT 0x4
+#define PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_EnablePClkGating__SHIFT 0x5
+#define PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_LFPSPolarity__SHIFT 0x10
+#define PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_LogicalLinkNumber_MASK 0x0000000FL
+#define PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_MasterPLLMask_MASK 0x00000010L
+#define PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_EnablePClkGating_MASK 0x00000020L
+#define PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_LFPSPolarity_MASK 0x00010000L
+//PCS_PCIEX16_LANE12_CONTROL
+#define PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_LogicalLinkNumber__SHIFT 0x0
+#define PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_MasterPLLMask__SHIFT 0x4
+#define PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_EnablePClkGating__SHIFT 0x5
+#define PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_LFPSPolarity__SHIFT 0x10
+#define PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_LogicalLinkNumber_MASK 0x0000000FL
+#define PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_MasterPLLMask_MASK 0x00000010L
+#define PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_EnablePClkGating_MASK 0x00000020L
+#define PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_LFPSPolarity_MASK 0x00010000L
+//PCS_PCIEX16_LANE13_CONTROL
+#define PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_LogicalLinkNumber__SHIFT 0x0
+#define PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_MasterPLLMask__SHIFT 0x4
+#define PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_EnablePClkGating__SHIFT 0x5
+#define PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_LFPSPolarity__SHIFT 0x10
+#define PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_LogicalLinkNumber_MASK 0x0000000FL
+#define PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_MasterPLLMask_MASK 0x00000010L
+#define PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_EnablePClkGating_MASK 0x00000020L
+#define PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_LFPSPolarity_MASK 0x00010000L
+//PCS_PCIEX16_LANE14_CONTROL
+#define PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_LogicalLinkNumber__SHIFT 0x0
+#define PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_MasterPLLMask__SHIFT 0x4
+#define PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_EnablePClkGating__SHIFT 0x5
+#define PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_LFPSPolarity__SHIFT 0x10
+#define PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_LogicalLinkNumber_MASK 0x0000000FL
+#define PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_MasterPLLMask_MASK 0x00000010L
+#define PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_EnablePClkGating_MASK 0x00000020L
+#define PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_LFPSPolarity_MASK 0x00010000L
+//PCS_PCIEX16_LANE15_CONTROL
+#define PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_LogicalLinkNumber__SHIFT 0x0
+#define PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_MasterPLLMask__SHIFT 0x4
+#define PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_EnablePClkGating__SHIFT 0x5
+#define PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_LFPSPolarity__SHIFT 0x10
+#define PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_LogicalLinkNumber_MASK 0x0000000FL
+#define PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_MasterPLLMask_MASK 0x00000010L
+#define PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_EnablePClkGating_MASK 0x00000020L
+#define PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_LFPSPolarity_MASK 0x00010000L
+//PCS_PCIEX16_GLOBAL_CONTROL9
+#define PCS_PCIEX16_GLOBAL_CONTROL9__FullSwing__SHIFT 0x0
+#define PCS_PCIEX16_GLOBAL_CONTROL9__LowFrequency__SHIFT 0x8
+#define PCS_PCIEX16_GLOBAL_CONTROL9__FullSwing_MASK 0x0000003FL
+#define PCS_PCIEX16_GLOBAL_CONTROL9__LowFrequency_MASK 0x00003F00L
+//PCS_PCIEX16_GLOBAL_CONTROL10
+#define PCS_PCIEX16_GLOBAL_CONTROL10__CoarseFreqCheckSymbols__SHIFT 0x0
+#define PCS_PCIEX16_GLOBAL_CONTROL10__CoarseFreqTolerance__SHIFT 0x8
+#define PCS_PCIEX16_GLOBAL_CONTROL10__AllowPointerSlipInterval__SHIFT 0x10
+#define PCS_PCIEX16_GLOBAL_CONTROL10__CoarseFreqCheckSymbols_MASK 0x0000007FL
+#define PCS_PCIEX16_GLOBAL_CONTROL10__CoarseFreqTolerance_MASK 0x00001F00L
+#define PCS_PCIEX16_GLOBAL_CONTROL10__AllowPointerSlipInterval_MASK 0x00FF0000L
+//PCS_PCIEX16_GLOBAL_CONTROL11
+#define PCS_PCIEX16_GLOBAL_CONTROL11__FrequencyVettingTimeout__SHIFT 0x0
+#define PCS_PCIEX16_GLOBAL_CONTROL11__FrequencyVettingEn__SHIFT 0x9
+#define PCS_PCIEX16_GLOBAL_CONTROL11__ErrorActionRst__SHIFT 0x10
+#define PCS_PCIEX16_GLOBAL_CONTROL11__ErrorActionRRC__SHIFT 0x11
+#define PCS_PCIEX16_GLOBAL_CONTROL11__ReceiverResetCycleEn__SHIFT 0x12
+#define PCS_PCIEX16_GLOBAL_CONTROL11__SymAlignBypassEn__SHIFT 0x13
+#define PCS_PCIEX16_GLOBAL_CONTROL11__FrequencyVettingTimeout_MASK 0x000000FFL
+#define PCS_PCIEX16_GLOBAL_CONTROL11__FrequencyVettingEn_MASK 0x00000200L
+#define PCS_PCIEX16_GLOBAL_CONTROL11__ErrorActionRst_MASK 0x00010000L
+#define PCS_PCIEX16_GLOBAL_CONTROL11__ErrorActionRRC_MASK 0x00020000L
+#define PCS_PCIEX16_GLOBAL_CONTROL11__ReceiverResetCycleEn_MASK 0x00040000L
+#define PCS_PCIEX16_GLOBAL_CONTROL11__SymAlignBypassEn_MASK 0x00080000L
+//PCS_PCIEX16_GLOBAL_CONTROL12
+#define PCS_PCIEX16_GLOBAL_CONTROL12__ErrorAccumulatorLowThreshold_8b10b__SHIFT 0x0
+#define PCS_PCIEX16_GLOBAL_CONTROL12__ErrorAccumulatorHighThreshold_8b10b__SHIFT 0x10
+#define PCS_PCIEX16_GLOBAL_CONTROL12__DisparityErrorEn_8b10b__SHIFT 0x1e
+#define PCS_PCIEX16_GLOBAL_CONTROL12__CodeErrorEn_8b10b__SHIFT 0x1f
+#define PCS_PCIEX16_GLOBAL_CONTROL12__ErrorAccumulatorLowThreshold_8b10b_MASK 0x00000FFFL
+#define PCS_PCIEX16_GLOBAL_CONTROL12__ErrorAccumulatorHighThreshold_8b10b_MASK 0x0FFF0000L
+#define PCS_PCIEX16_GLOBAL_CONTROL12__DisparityErrorEn_8b10b_MASK 0x40000000L
+#define PCS_PCIEX16_GLOBAL_CONTROL12__CodeErrorEn_8b10b_MASK 0x80000000L
+//PCS_PCIEX16_GLOBAL_CONTROL13
+#define PCS_PCIEX16_GLOBAL_CONTROL13__ErrorAccumulatorIncrement_8b10b__SHIFT 0x0
+#define PCS_PCIEX16_GLOBAL_CONTROL13__ErrorAccumulatorDecrement_8b10b__SHIFT 0x8
+#define PCS_PCIEX16_GLOBAL_CONTROL13__ErrorTimeout__SHIFT 0x10
+#define PCS_PCIEX16_GLOBAL_CONTROL13__Adjust_8b10b_AlignTimeout__SHIFT 0x1c
+#define PCS_PCIEX16_GLOBAL_CONTROL13__ErrorAccumulatorIncrement_8b10b_MASK 0x0000001FL
+#define PCS_PCIEX16_GLOBAL_CONTROL13__ErrorAccumulatorDecrement_8b10b_MASK 0x00001F00L
+#define PCS_PCIEX16_GLOBAL_CONTROL13__ErrorTimeout_MASK 0x00FF0000L
+#define PCS_PCIEX16_GLOBAL_CONTROL13__Adjust_8b10b_AlignTimeout_MASK 0xF0000000L
+//PCS_PCIEX16_GLOBAL_CONTROL14
+#define PCS_PCIEX16_GLOBAL_CONTROL14__USBOnesZeros__SHIFT 0x0
+#define PCS_PCIEX16_GLOBAL_CONTROL14__EnableBCHCodeInSKPOS__SHIFT 0x5
+#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_Enable__SHIFT 0x10
+#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_DisparityErrorEnable__SHIFT 0x11
+#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_DecodeErrorEnable__SHIFT 0x12
+#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_LFSRErrorEnable__SHIFT 0x13
+#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_LaneSelect__SHIFT 0x14
+#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_LastErrorCount__SHIFT 0x18
+#define PCS_PCIEX16_GLOBAL_CONTROL14__USBOnesZeros_MASK 0x0000001FL
+#define PCS_PCIEX16_GLOBAL_CONTROL14__EnableBCHCodeInSKPOS_MASK 0x00000020L
+#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_Enable_MASK 0x00010000L
+#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_DisparityErrorEnable_MASK 0x00020000L
+#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_DecodeErrorEnable_MASK 0x00040000L
+#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_LFSRErrorEnable_MASK 0x00080000L
+#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_LaneSelect_MASK 0x00F00000L
+#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_LastErrorCount_MASK 0xFF000000L
+//PCS_PCIEX16_GLOBAL_CONTROL15
+#define PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalHalfMidPointMode1__SHIFT 0x0
+#define PCS_PCIEX16_GLOBAL_CONTROL15__OverrideElasticFIFOControlSettings__SHIFT 0x5
+#define PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalHalfHighThresholdMode1__SHIFT 0x8
+#define PCS_PCIEX16_GLOBAL_CONTROL15__ElasticBufferProjectedWritePointerOffset__SHIFT 0xd
+#define PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalHalfLowThresholdMode1__SHIFT 0x10
+#define PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalEmptyHighThresholdMode1__SHIFT 0x18
+#define PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalHalfMidPointMode1_MASK 0x0000001FL
+#define PCS_PCIEX16_GLOBAL_CONTROL15__OverrideElasticFIFOControlSettings_MASK 0x00000020L
+#define PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalHalfHighThresholdMode1_MASK 0x00001F00L
+#define PCS_PCIEX16_GLOBAL_CONTROL15__ElasticBufferProjectedWritePointerOffset_MASK 0x0000E000L
+#define PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalHalfLowThresholdMode1_MASK 0x001F0000L
+#define PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalEmptyHighThresholdMode1_MASK 0x1F000000L
+//PCS_PCIEX16_GLOBAL_CONTROL16
+#define PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalHalfMidPointMode2__SHIFT 0x0
+#define PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalHalfHighThresholdMode2__SHIFT 0x8
+#define PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalLowHighThresholdMode2__SHIFT 0x10
+#define PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalEmptyHighThresholdMode2__SHIFT 0x18
+#define PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalHalfMidPointMode2_MASK 0x0000001FL
+#define PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalHalfHighThresholdMode2_MASK 0x00001F00L
+#define PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalLowHighThresholdMode2_MASK 0x001F0000L
+#define PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalEmptyHighThresholdMode2_MASK 0x1F000000L
+//PCS_PCIEX16_GLOBAL_CONTROL17
+#define PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_CHK_ERR_MASK__SHIFT 0x0
+#define PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_LOCKED__SHIFT 0x8
+#define PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_ERRSTAT__SHIFT 0x10
+#define PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_BITCNT_DONE__SHIFT 0x18
+#define PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_CHK_ERR_MASK_MASK 0x000000FFL
+#define PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_LOCKED_MASK 0x0000FF00L
+#define PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_ERRSTAT_MASK 0x00FF0000L
+#define PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_BITCNT_DONE_MASK 0xFF000000L
+
+
+// addressBlock: nbio_pipe_pcs_pcs_pciex16_gaskt_pcs_pciex16_gaskt_dir
+//PCS_GLOBAL_CONTROL17
+#define PCS_GLOBAL_CONTROL17__refclk_range1__SHIFT 0x0
+#define PCS_GLOBAL_CONTROL17__refclk_div2_en1__SHIFT 0x4
+#define PCS_GLOBAL_CONTROL17__refclk_range1_MASK 0x00000007L
+#define PCS_GLOBAL_CONTROL17__refclk_div2_en1_MASK 0x00000010L
+//PCS_GLOBAL_CONTROL18
+#define PCS_GLOBAL_CONTROL18__refclk_range2__SHIFT 0x0
+#define PCS_GLOBAL_CONTROL18__refclk_div2_en2__SHIFT 0x4
+#define PCS_GLOBAL_CONTROL18__refclk_range2_MASK 0x00000007L
+#define PCS_GLOBAL_CONTROL18__refclk_div2_en2_MASK 0x00000010L
+//PCS_GLOBAL_CONTROL19
+#define PCS_GLOBAL_CONTROL19__mplla_multiplier1__SHIFT 0x0
+#define PCS_GLOBAL_CONTROL19__mplla_bandwidth1__SHIFT 0x8
+#define PCS_GLOBAL_CONTROL19__mplla_div8_clk_en1__SHIFT 0x13
+#define PCS_GLOBAL_CONTROL19__mplla_div10_clk_en1__SHIFT 0x14
+#define PCS_GLOBAL_CONTROL19__mplla_refclk_div2_en1__SHIFT 0x18
+#define PCS_GLOBAL_CONTROL19__mplla_init_cal_disable1__SHIFT 0x1b
+#define PCS_GLOBAL_CONTROL19__mplla_force_en1__SHIFT 0x1c
+#define PCS_GLOBAL_CONTROL19__mplla_multiplier1_MASK 0x000000FFL
+#define PCS_GLOBAL_CONTROL19__mplla_bandwidth1_MASK 0x0007FF00L
+#define PCS_GLOBAL_CONTROL19__mplla_div8_clk_en1_MASK 0x00080000L
+#define PCS_GLOBAL_CONTROL19__mplla_div10_clk_en1_MASK 0x00100000L
+#define PCS_GLOBAL_CONTROL19__mplla_refclk_div2_en1_MASK 0x01000000L
+#define PCS_GLOBAL_CONTROL19__mplla_init_cal_disable1_MASK 0x08000000L
+#define PCS_GLOBAL_CONTROL19__mplla_force_en1_MASK 0x10000000L
+//PCS_GLOBAL_CONTROL20
+#define PCS_GLOBAL_CONTROL20__mplla_multiplier2__SHIFT 0x0
+#define PCS_GLOBAL_CONTROL20__mplla_bandwidth2__SHIFT 0x8
+#define PCS_GLOBAL_CONTROL20__mplla_div8_clk_en2__SHIFT 0x13
+#define PCS_GLOBAL_CONTROL20__mplla_div10_clk_en2__SHIFT 0x14
+#define PCS_GLOBAL_CONTROL20__mplla_refclk_div2_en2__SHIFT 0x18
+#define PCS_GLOBAL_CONTROL20__mplla_init_cal_disable2__SHIFT 0x1b
+#define PCS_GLOBAL_CONTROL20__mplla_force_en2__SHIFT 0x1c
+#define PCS_GLOBAL_CONTROL20__mplla_multiplier2_MASK 0x000000FFL
+#define PCS_GLOBAL_CONTROL20__mplla_bandwidth2_MASK 0x0007FF00L
+#define PCS_GLOBAL_CONTROL20__mplla_div8_clk_en2_MASK 0x00080000L
+#define PCS_GLOBAL_CONTROL20__mplla_div10_clk_en2_MASK 0x00100000L
+#define PCS_GLOBAL_CONTROL20__mplla_refclk_div2_en2_MASK 0x01000000L
+#define PCS_GLOBAL_CONTROL20__mplla_init_cal_disable2_MASK 0x08000000L
+#define PCS_GLOBAL_CONTROL20__mplla_force_en2_MASK 0x10000000L
+//PCS_GLOBAL_CONTROL21
+#define PCS_GLOBAL_CONTROL21__mpllb_multiplier1__SHIFT 0x0
+#define PCS_GLOBAL_CONTROL21__mpllb_bandwidth1__SHIFT 0x8
+#define PCS_GLOBAL_CONTROL21__mpllb_div8_clk_en1__SHIFT 0x13
+#define PCS_GLOBAL_CONTROL21__mpllb_div10_clk_en1__SHIFT 0x14
+#define PCS_GLOBAL_CONTROL21__mpllb_refclk_div2_en1__SHIFT 0x18
+#define PCS_GLOBAL_CONTROL21__mpllb_init_cal_disable1__SHIFT 0x1b
+#define PCS_GLOBAL_CONTROL21__mpllb_force_en1__SHIFT 0x1c
+#define PCS_GLOBAL_CONTROL21__mpllb_multiplier1_MASK 0x000000FFL
+#define PCS_GLOBAL_CONTROL21__mpllb_bandwidth1_MASK 0x0007FF00L
+#define PCS_GLOBAL_CONTROL21__mpllb_div8_clk_en1_MASK 0x00080000L
+#define PCS_GLOBAL_CONTROL21__mpllb_div10_clk_en1_MASK 0x00100000L
+#define PCS_GLOBAL_CONTROL21__mpllb_refclk_div2_en1_MASK 0x01000000L
+#define PCS_GLOBAL_CONTROL21__mpllb_init_cal_disable1_MASK 0x08000000L
+#define PCS_GLOBAL_CONTROL21__mpllb_force_en1_MASK 0x10000000L
+//PCS_GLOBAL_CONTROL22
+#define PCS_GLOBAL_CONTROL22__mpllb_multiplier2__SHIFT 0x0
+#define PCS_GLOBAL_CONTROL22__mpllb_bandwidth2__SHIFT 0x8
+#define PCS_GLOBAL_CONTROL22__mpllb_div8_clk_en2__SHIFT 0x13
+#define PCS_GLOBAL_CONTROL22__mpllb_div10_clk_en2__SHIFT 0x14
+#define PCS_GLOBAL_CONTROL22__mpllb_refclk_div2_en2__SHIFT 0x18
+#define PCS_GLOBAL_CONTROL22__mpllb_init_cal_disable2__SHIFT 0x1b
+#define PCS_GLOBAL_CONTROL22__mpllb_force_en2__SHIFT 0x1c
+#define PCS_GLOBAL_CONTROL22__mpllb_multiplier2_MASK 0x000000FFL
+#define PCS_GLOBAL_CONTROL22__mpllb_bandwidth2_MASK 0x0007FF00L
+#define PCS_GLOBAL_CONTROL22__mpllb_div8_clk_en2_MASK 0x00080000L
+#define PCS_GLOBAL_CONTROL22__mpllb_div10_clk_en2_MASK 0x00100000L
+#define PCS_GLOBAL_CONTROL22__mpllb_refclk_div2_en2_MASK 0x01000000L
+#define PCS_GLOBAL_CONTROL22__mpllb_init_cal_disable2_MASK 0x08000000L
+#define PCS_GLOBAL_CONTROL22__mpllb_force_en2_MASK 0x10000000L
+//PCS_GLOBAL_CONTROL23
+#define PCS_GLOBAL_CONTROL23__txX_iboost_lvl1__SHIFT 0x0
+#define PCS_GLOBAL_CONTROL23__tx_vboost_lvl1__SHIFT 0x4
+#define PCS_GLOBAL_CONTROL23__txX_vboost_en1__SHIFT 0x7
+#define PCS_GLOBAL_CONTROL23__txX_iboost_lvl2__SHIFT 0x8
+#define PCS_GLOBAL_CONTROL23__tx_vboost_lvl2__SHIFT 0xc
+#define PCS_GLOBAL_CONTROL23__txX_vboost_en2__SHIFT 0xf
+#define PCS_GLOBAL_CONTROL23__txX_iboost_lvl3__SHIFT 0x10
+#define PCS_GLOBAL_CONTROL23__tx_vboost_lvl3__SHIFT 0x14
+#define PCS_GLOBAL_CONTROL23__txX_vboost_en3__SHIFT 0x17
+#define PCS_GLOBAL_CONTROL23__rxX_cdr_vco_lowfreq1__SHIFT 0x18
+#define PCS_GLOBAL_CONTROL23__rxX_cdr_vco_lowfreq2__SHIFT 0x19
+#define PCS_GLOBAL_CONTROL23__rxX_cdr_vco_lowfreq3__SHIFT 0x1a
+#define PCS_GLOBAL_CONTROL23__rxX_cdr_ssc_en__SHIFT 0x1b
+#define PCS_GLOBAL_CONTROL23__rxX_term_acdc__SHIFT 0x1c
+#define PCS_GLOBAL_CONTROL23__txX_iboost_lvl1_MASK 0x0000000FL
+#define PCS_GLOBAL_CONTROL23__tx_vboost_lvl1_MASK 0x00000070L
+#define PCS_GLOBAL_CONTROL23__txX_vboost_en1_MASK 0x00000080L
+#define PCS_GLOBAL_CONTROL23__txX_iboost_lvl2_MASK 0x00000F00L
+#define PCS_GLOBAL_CONTROL23__tx_vboost_lvl2_MASK 0x00007000L
+#define PCS_GLOBAL_CONTROL23__txX_vboost_en2_MASK 0x00008000L
+#define PCS_GLOBAL_CONTROL23__txX_iboost_lvl3_MASK 0x000F0000L
+#define PCS_GLOBAL_CONTROL23__tx_vboost_lvl3_MASK 0x00700000L
+#define PCS_GLOBAL_CONTROL23__txX_vboost_en3_MASK 0x00800000L
+#define PCS_GLOBAL_CONTROL23__rxX_cdr_vco_lowfreq1_MASK 0x01000000L
+#define PCS_GLOBAL_CONTROL23__rxX_cdr_vco_lowfreq2_MASK 0x02000000L
+#define PCS_GLOBAL_CONTROL23__rxX_cdr_vco_lowfreq3_MASK 0x04000000L
+#define PCS_GLOBAL_CONTROL23__rxX_cdr_ssc_en_MASK 0x08000000L
+#define PCS_GLOBAL_CONTROL23__rxX_term_acdc_MASK 0x10000000L
+//PCS_GLOBAL_CONTROL24
+#define PCS_GLOBAL_CONTROL24__rxX_eq_vga1_gain_gen1__SHIFT 0x0
+#define PCS_GLOBAL_CONTROL24__rxX_eq_vga2_gain_gen1__SHIFT 0x4
+#define PCS_GLOBAL_CONTROL24__rxX_eq_dfe_tap_gen1__SHIFT 0x10
+#define PCS_GLOBAL_CONTROL24__rxX_eq_att_lvl_gen1__SHIFT 0x18
+#define PCS_GLOBAL_CONTROL24__rxX_adapt_afe_en_gen1__SHIFT 0x1c
+#define PCS_GLOBAL_CONTROL24__rxX_adapt_dfe_en_gen1__SHIFT 0x1d
+#define PCS_GLOBAL_CONTROL24__rxX_eq_vga1_gain_gen1_MASK 0x0000000FL
+#define PCS_GLOBAL_CONTROL24__rxX_eq_vga2_gain_gen1_MASK 0x000000F0L
+#define PCS_GLOBAL_CONTROL24__rxX_eq_dfe_tap_gen1_MASK 0x00FF0000L
+#define PCS_GLOBAL_CONTROL24__rxX_eq_att_lvl_gen1_MASK 0x07000000L
+#define PCS_GLOBAL_CONTROL24__rxX_adapt_afe_en_gen1_MASK 0x10000000L
+#define PCS_GLOBAL_CONTROL24__rxX_adapt_dfe_en_gen1_MASK 0x20000000L
+//PCS_GLOBAL_CONTROL25
+#define PCS_GLOBAL_CONTROL25__rxX_eq_vga1_gain_gen2__SHIFT 0x0
+#define PCS_GLOBAL_CONTROL25__rxX_eq_vga2_gain_gen2__SHIFT 0x4
+#define PCS_GLOBAL_CONTROL25__rxX_eq_dfe_tap_gen2__SHIFT 0x10
+#define PCS_GLOBAL_CONTROL25__rxX_eq_att_lvl_gen2__SHIFT 0x18
+#define PCS_GLOBAL_CONTROL25__rxX_adapt_afe_en_gen2__SHIFT 0x1c
+#define PCS_GLOBAL_CONTROL25__rxX_adapt_dfe_en_gen2__SHIFT 0x1d
+#define PCS_GLOBAL_CONTROL25__rxX_eq_vga1_gain_gen2_MASK 0x0000000FL
+#define PCS_GLOBAL_CONTROL25__rxX_eq_vga2_gain_gen2_MASK 0x000000F0L
+#define PCS_GLOBAL_CONTROL25__rxX_eq_dfe_tap_gen2_MASK 0x00FF0000L
+#define PCS_GLOBAL_CONTROL25__rxX_eq_att_lvl_gen2_MASK 0x07000000L
+#define PCS_GLOBAL_CONTROL25__rxX_adapt_afe_en_gen2_MASK 0x10000000L
+#define PCS_GLOBAL_CONTROL25__rxX_adapt_dfe_en_gen2_MASK 0x20000000L
+//PCS_GLOBAL_CONTROL26
+#define PCS_GLOBAL_CONTROL26__rxX_eq_vga1_gain_gen3__SHIFT 0x0
+#define PCS_GLOBAL_CONTROL26__rxX_eq_vga2_gain_gen3__SHIFT 0x4
+#define PCS_GLOBAL_CONTROL26__rxX_eq_dfe_tap_gen3__SHIFT 0x10
+#define PCS_GLOBAL_CONTROL26__rxX_eq_att_lvl_gen3__SHIFT 0x18
+#define PCS_GLOBAL_CONTROL26__rxX_adapt_afe_en_gen3__SHIFT 0x1c
+#define PCS_GLOBAL_CONTROL26__rxX_adapt_dfe_en_gen3__SHIFT 0x1d
+#define PCS_GLOBAL_CONTROL26__rxX_eq_vga1_gain_gen3_MASK 0x0000000FL
+#define PCS_GLOBAL_CONTROL26__rxX_eq_vga2_gain_gen3_MASK 0x000000F0L
+#define PCS_GLOBAL_CONTROL26__rxX_eq_dfe_tap_gen3_MASK 0x00FF0000L
+#define PCS_GLOBAL_CONTROL26__rxX_eq_att_lvl_gen3_MASK 0x07000000L
+#define PCS_GLOBAL_CONTROL26__rxX_adapt_afe_en_gen3_MASK 0x10000000L
+#define PCS_GLOBAL_CONTROL26__rxX_adapt_dfe_en_gen3_MASK 0x20000000L
+//PCS_GLOBAL_CONTROL27
+#define PCS_GLOBAL_CONTROL27__rxX_vco_ld_val1__SHIFT 0x0
+#define PCS_GLOBAL_CONTROL27__rxX_ref_ld_val1__SHIFT 0x10
+#define PCS_GLOBAL_CONTROL27__rx_vref_ctrl1__SHIFT 0x18
+#define PCS_GLOBAL_CONTROL27__rxX_vco_ld_val1_MASK 0x00001FFFL
+#define PCS_GLOBAL_CONTROL27__rxX_ref_ld_val1_MASK 0x003F0000L
+#define PCS_GLOBAL_CONTROL27__rx_vref_ctrl1_MASK 0x1F000000L
+//PCS_GLOBAL_CONTROL28
+#define PCS_GLOBAL_CONTROL28__rxX_vco_ld_val2__SHIFT 0x0
+#define PCS_GLOBAL_CONTROL28__rxX_ref_ld_val2__SHIFT 0x10
+#define PCS_GLOBAL_CONTROL28__rx_vref_ctrl2__SHIFT 0x18
+#define PCS_GLOBAL_CONTROL28__rxX_vco_ld_val2_MASK 0x00001FFFL
+#define PCS_GLOBAL_CONTROL28__rxX_ref_ld_val2_MASK 0x003F0000L
+#define PCS_GLOBAL_CONTROL28__rx_vref_ctrl2_MASK 0x1F000000L
+//PCS_GLOBAL_CONTROL29
+#define PCS_GLOBAL_CONTROL29__rxX_vco_ld_val3__SHIFT 0x0
+#define PCS_GLOBAL_CONTROL29__rxX_ref_ld_val3__SHIFT 0x10
+#define PCS_GLOBAL_CONTROL29__rx_vref_ctrl3__SHIFT 0x18
+#define PCS_GLOBAL_CONTROL29__rxX_vco_ld_val3_MASK 0x00001FFFL
+#define PCS_GLOBAL_CONTROL29__rxX_ref_ld_val3_MASK 0x003F0000L
+#define PCS_GLOBAL_CONTROL29__rx_vref_ctrl3_MASK 0x1F000000L
+//PCS_GLOBAL_CONTROL30
+#define PCS_GLOBAL_CONTROL30__MPLLAInformationUpdate__SHIFT 0x0
+#define PCS_GLOBAL_CONTROL30__MPLLBInformationUpdate__SHIFT 0x1
+#define PCS_GLOBAL_CONTROL30__MPLLAControlOverride__SHIFT 0x2
+#define PCS_GLOBAL_CONTROL30__MPLLBControlOverride__SHIFT 0x3
+#define PCS_GLOBAL_CONTROL30__MPLLAControlOverrideValue__SHIFT 0x4
+#define PCS_GLOBAL_CONTROL30__MPLLBControlOverrideValue__SHIFT 0x5
+#define PCS_GLOBAL_CONTROL30__TransmitterInformationUpdate__SHIFT 0x6
+#define PCS_GLOBAL_CONTROL30__ReceiverInformationUpdate__SHIFT 0x7
+#define PCS_GLOBAL_CONTROL30__ReferenceClockInformationUpdate__SHIFT 0x8
+#define PCS_GLOBAL_CONTROL30__ReferenceClockControlOverride__SHIFT 0x9
+#define PCS_GLOBAL_CONTROL30__ReferenceClockControlOverrideValue__SHIFT 0xa
+#define PCS_GLOBAL_CONTROL30__PowerManagerInterruptPriority__SHIFT 0xb
+#define PCS_GLOBAL_CONTROL30__PLLSetupChangeAlgorithm__SHIFT 0xc
+#define PCS_GLOBAL_CONTROL30__MPLLAInformationUpdate_MASK 0x00000001L
+#define PCS_GLOBAL_CONTROL30__MPLLBInformationUpdate_MASK 0x00000002L
+#define PCS_GLOBAL_CONTROL30__MPLLAControlOverride_MASK 0x00000004L
+#define PCS_GLOBAL_CONTROL30__MPLLBControlOverride_MASK 0x00000008L
+#define PCS_GLOBAL_CONTROL30__MPLLAControlOverrideValue_MASK 0x00000010L
+#define PCS_GLOBAL_CONTROL30__MPLLBControlOverrideValue_MASK 0x00000020L
+#define PCS_GLOBAL_CONTROL30__TransmitterInformationUpdate_MASK 0x00000040L
+#define PCS_GLOBAL_CONTROL30__ReceiverInformationUpdate_MASK 0x00000080L
+#define PCS_GLOBAL_CONTROL30__ReferenceClockInformationUpdate_MASK 0x00000100L
+#define PCS_GLOBAL_CONTROL30__ReferenceClockControlOverride_MASK 0x00000200L
+#define PCS_GLOBAL_CONTROL30__ReferenceClockControlOverrideValue_MASK 0x00000400L
+#define PCS_GLOBAL_CONTROL30__PowerManagerInterruptPriority_MASK 0x00000800L
+#define PCS_GLOBAL_CONTROL30__PLLSetupChangeAlgorithm_MASK 0x00001000L
+//PCS_STATUS1
+#define PCS_STATUS1__LowPriorityInterrupt0Done__SHIFT 0x0
+#define PCS_STATUS1__HighPriorityInterrupt1Done__SHIFT 0x1
+#define PCS_STATUS1__LowPriorityInterrupt2Done__SHIFT 0x2
+#define PCS_STATUS1__LowPriorityInterrupt0Done_MASK 0x00000001L
+#define PCS_STATUS1__HighPriorityInterrupt1Done_MASK 0x00000002L
+#define PCS_STATUS1__LowPriorityInterrupt2Done_MASK 0x00000004L
+//PCS_LANE0_CNTRL1
+#define PCS_LANE0_CNTRL1__rxX_los_threshold_lane0__SHIFT 0x0
+#define PCS_LANE0_CNTRL1__laneX_tx2rx_ser_lb_en_lane0__SHIFT 0x10
+#define PCS_LANE0_CNTRL1__rxX_los_threshold_lane0_MASK 0x00000007L
+#define PCS_LANE0_CNTRL1__laneX_tx2rx_ser_lb_en_lane0_MASK 0x00010000L
+//PCS_LANE1_CNTRL1
+#define PCS_LANE1_CNTRL1__rxX_los_threshold_lane1__SHIFT 0x0
+#define PCS_LANE1_CNTRL1__laneX_tx2rx_ser_lb_en_lane1__SHIFT 0x10
+#define PCS_LANE1_CNTRL1__rxX_los_threshold_lane1_MASK 0x00000007L
+#define PCS_LANE1_CNTRL1__laneX_tx2rx_ser_lb_en_lane1_MASK 0x00010000L
+//PCS_LANE2_CNTRL1
+#define PCS_LANE2_CNTRL1__rxX_los_threshold_lane2__SHIFT 0x0
+#define PCS_LANE2_CNTRL1__laneX_tx2rx_ser_lb_en_lane2__SHIFT 0x10
+#define PCS_LANE2_CNTRL1__rxX_los_threshold_lane2_MASK 0x00000007L
+#define PCS_LANE2_CNTRL1__laneX_tx2rx_ser_lb_en_lane2_MASK 0x00010000L
+//PCS_LANE3_CNTRL1
+#define PCS_LANE3_CNTRL1__rxX_los_threshold_lane3__SHIFT 0x0
+#define PCS_LANE3_CNTRL1__laneX_tx2rx_ser_lb_en_lane3__SHIFT 0x10
+#define PCS_LANE3_CNTRL1__rxX_los_threshold_lane3_MASK 0x00000007L
+#define PCS_LANE3_CNTRL1__laneX_tx2rx_ser_lb_en_lane3_MASK 0x00010000L
+//PCS_LANE4_CNTRL1
+#define PCS_LANE4_CNTRL1__rxX_los_threshold_lane4__SHIFT 0x0
+#define PCS_LANE4_CNTRL1__laneX_tx2rx_ser_lb_en_lane4__SHIFT 0x10
+#define PCS_LANE4_CNTRL1__rxX_los_threshold_lane4_MASK 0x00000007L
+#define PCS_LANE4_CNTRL1__laneX_tx2rx_ser_lb_en_lane4_MASK 0x00010000L
+//PCS_LANE5_CNTRL1
+#define PCS_LANE5_CNTRL1__rxX_los_threshold_lane5__SHIFT 0x0
+#define PCS_LANE5_CNTRL1__laneX_tx2rx_ser_lb_en_lane5__SHIFT 0x10
+#define PCS_LANE5_CNTRL1__rxX_los_threshold_lane5_MASK 0x00000007L
+#define PCS_LANE5_CNTRL1__laneX_tx2rx_ser_lb_en_lane5_MASK 0x00010000L
+//PCS_LANE6_CNTRL1
+#define PCS_LANE6_CNTRL1__rxX_los_threshold_lane6__SHIFT 0x0
+#define PCS_LANE6_CNTRL1__laneX_tx2rx_ser_lb_en_lane6__SHIFT 0x10
+#define PCS_LANE6_CNTRL1__rxX_los_threshold_lane6_MASK 0x00000007L
+#define PCS_LANE6_CNTRL1__laneX_tx2rx_ser_lb_en_lane6_MASK 0x00010000L
+//PCS_LANE7_CNTRL1
+#define PCS_LANE7_CNTRL1__rxX_los_threshold_lane7__SHIFT 0x0
+#define PCS_LANE7_CNTRL1__laneX_tx2rx_ser_lb_en_lane7__SHIFT 0x10
+#define PCS_LANE7_CNTRL1__rxX_los_threshold_lane7_MASK 0x00000007L
+#define PCS_LANE7_CNTRL1__laneX_tx2rx_ser_lb_en_lane7_MASK 0x00010000L
+//PCS_LANE8_CNTRL1
+#define PCS_LANE8_CNTRL1__rxX_los_threshold_lane8__SHIFT 0x0
+#define PCS_LANE8_CNTRL1__laneX_tx2rx_ser_lb_en_lane8__SHIFT 0x10
+#define PCS_LANE8_CNTRL1__rxX_los_threshold_lane8_MASK 0x00000007L
+#define PCS_LANE8_CNTRL1__laneX_tx2rx_ser_lb_en_lane8_MASK 0x00010000L
+//PCS_LANE9_CNTRL1
+#define PCS_LANE9_CNTRL1__rxX_los_threshold_lane9__SHIFT 0x0
+#define PCS_LANE9_CNTRL1__laneX_tx2rx_ser_lb_en_lane9__SHIFT 0x10
+#define PCS_LANE9_CNTRL1__rxX_los_threshold_lane9_MASK 0x00000007L
+#define PCS_LANE9_CNTRL1__laneX_tx2rx_ser_lb_en_lane9_MASK 0x00010000L
+//PCS_LANE10_CNTRL1
+#define PCS_LANE10_CNTRL1__rxX_los_threshold_lane10__SHIFT 0x0
+#define PCS_LANE10_CNTRL1__laneX_tx2rx_ser_lb_en_lane10__SHIFT 0x10
+#define PCS_LANE10_CNTRL1__rxX_los_threshold_lane10_MASK 0x00000007L
+#define PCS_LANE10_CNTRL1__laneX_tx2rx_ser_lb_en_lane10_MASK 0x00010000L
+//PCS_LANE11_CNTRL1
+#define PCS_LANE11_CNTRL1__rxX_los_threshold_lane11__SHIFT 0x0
+#define PCS_LANE11_CNTRL1__laneX_tx2rx_ser_lb_en_lane11__SHIFT 0x10
+#define PCS_LANE11_CNTRL1__rxX_los_threshold_lane11_MASK 0x00000007L
+#define PCS_LANE11_CNTRL1__laneX_tx2rx_ser_lb_en_lane11_MASK 0x00010000L
+//PCS_LANE12_CNTRL1
+#define PCS_LANE12_CNTRL1__rxX_los_threshold_lane12__SHIFT 0x0
+#define PCS_LANE12_CNTRL1__laneX_tx2rx_ser_lb_en_lane12__SHIFT 0x10
+#define PCS_LANE12_CNTRL1__rxX_los_threshold_lane12_MASK 0x00000007L
+#define PCS_LANE12_CNTRL1__laneX_tx2rx_ser_lb_en_lane12_MASK 0x00010000L
+//PCS_LANE13_CNTRL1
+#define PCS_LANE13_CNTRL1__rxX_los_threshold_lane13__SHIFT 0x0
+#define PCS_LANE13_CNTRL1__laneX_tx2rx_ser_lb_en_lane13__SHIFT 0x10
+#define PCS_LANE13_CNTRL1__rxX_los_threshold_lane13_MASK 0x00000007L
+#define PCS_LANE13_CNTRL1__laneX_tx2rx_ser_lb_en_lane13_MASK 0x00010000L
+//PCS_LANE14_CNTRL1
+#define PCS_LANE14_CNTRL1__rxX_los_threshold_lane14__SHIFT 0x0
+#define PCS_LANE14_CNTRL1__laneX_tx2rx_ser_lb_en_lane14__SHIFT 0x10
+#define PCS_LANE14_CNTRL1__rxX_los_threshold_lane14_MASK 0x00000007L
+#define PCS_LANE14_CNTRL1__laneX_tx2rx_ser_lb_en_lane14_MASK 0x00010000L
+//PCS_LANE15_CNTRL1
+#define PCS_LANE15_CNTRL1__rxX_los_threshold_lane15__SHIFT 0x0
+#define PCS_LANE15_CNTRL1__laneX_tx2rx_ser_lb_en_lane15__SHIFT 0x10
+#define PCS_LANE15_CNTRL1__rxX_los_threshold_lane15_MASK 0x00000007L
+#define PCS_LANE15_CNTRL1__laneX_tx2rx_ser_lb_en_lane15_MASK 0x00010000L
+//PCS_LANE0_COEFF1
+#define PCS_LANE0_COEFF1__TxCoefficientPreCursor_lane0_gen1__SHIFT 0x0
+#define PCS_LANE0_COEFF1__TxCoefficientMainCursor_lane0_gen1__SHIFT 0x8
+#define PCS_LANE0_COEFF1__TxCoefficientPostCursor_lane0_gen1__SHIFT 0x10
+#define PCS_LANE0_COEFF1__rxX_eq_ctle_boost_lane0_gen1__SHIFT 0x18
+#define PCS_LANE0_COEFF1__rxX_eq_ctle_pole_lane0_gen1__SHIFT 0x1d
+#define PCS_LANE0_COEFF1__TxCoefficientPreCursor_lane0_gen1_MASK 0x0000003FL
+#define PCS_LANE0_COEFF1__TxCoefficientMainCursor_lane0_gen1_MASK 0x00003F00L
+#define PCS_LANE0_COEFF1__TxCoefficientPostCursor_lane0_gen1_MASK 0x003F0000L
+#define PCS_LANE0_COEFF1__rxX_eq_ctle_boost_lane0_gen1_MASK 0x1F000000L
+#define PCS_LANE0_COEFF1__rxX_eq_ctle_pole_lane0_gen1_MASK 0xE0000000L
+//PCS_LANE1_COEFF1
+#define PCS_LANE1_COEFF1__TxCoefficientPreCursor_lane1_gen1__SHIFT 0x0
+#define PCS_LANE1_COEFF1__TxCoefficientMainCursor_lane1_gen1__SHIFT 0x8
+#define PCS_LANE1_COEFF1__TxCoefficientPostCursor_lane1_gen1__SHIFT 0x10
+#define PCS_LANE1_COEFF1__rxX_eq_ctle_boost_lane1_gen1__SHIFT 0x18
+#define PCS_LANE1_COEFF1__rxX_eq_ctle_pole_lane1_gen1__SHIFT 0x1d
+#define PCS_LANE1_COEFF1__TxCoefficientPreCursor_lane1_gen1_MASK 0x0000003FL
+#define PCS_LANE1_COEFF1__TxCoefficientMainCursor_lane1_gen1_MASK 0x00003F00L
+#define PCS_LANE1_COEFF1__TxCoefficientPostCursor_lane1_gen1_MASK 0x003F0000L
+#define PCS_LANE1_COEFF1__rxX_eq_ctle_boost_lane1_gen1_MASK 0x1F000000L
+#define PCS_LANE1_COEFF1__rxX_eq_ctle_pole_lane1_gen1_MASK 0xE0000000L
+//PCS_LANE2_COEFF1
+#define PCS_LANE2_COEFF1__TxCoefficientPreCursor_lane2_gen1__SHIFT 0x0
+#define PCS_LANE2_COEFF1__TxCoefficientMainCursor_lane2_gen1__SHIFT 0x8
+#define PCS_LANE2_COEFF1__TxCoefficientPostCursor_lane2_gen1__SHIFT 0x10
+#define PCS_LANE2_COEFF1__rxX_eq_ctle_boost_lane2_gen1__SHIFT 0x18
+#define PCS_LANE2_COEFF1__rxX_eq_ctle_pole_lane2_gen1__SHIFT 0x1d
+#define PCS_LANE2_COEFF1__TxCoefficientPreCursor_lane2_gen1_MASK 0x0000003FL
+#define PCS_LANE2_COEFF1__TxCoefficientMainCursor_lane2_gen1_MASK 0x00003F00L
+#define PCS_LANE2_COEFF1__TxCoefficientPostCursor_lane2_gen1_MASK 0x003F0000L
+#define PCS_LANE2_COEFF1__rxX_eq_ctle_boost_lane2_gen1_MASK 0x1F000000L
+#define PCS_LANE2_COEFF1__rxX_eq_ctle_pole_lane2_gen1_MASK 0xE0000000L
+//PCS_LANE3_COEFF1
+#define PCS_LANE3_COEFF1__TxCoefficientPreCursor_lane3_gen1__SHIFT 0x0
+#define PCS_LANE3_COEFF1__TxCoefficientMainCursor_lane3_gen1__SHIFT 0x8
+#define PCS_LANE3_COEFF1__TxCoefficientPostCursor_lane3_gen1__SHIFT 0x10
+#define PCS_LANE3_COEFF1__rxX_eq_ctle_boost_lane3_gen1__SHIFT 0x18
+#define PCS_LANE3_COEFF1__rxX_eq_ctle_pole_lane3_gen1__SHIFT 0x1d
+#define PCS_LANE3_COEFF1__TxCoefficientPreCursor_lane3_gen1_MASK 0x0000003FL
+#define PCS_LANE3_COEFF1__TxCoefficientMainCursor_lane3_gen1_MASK 0x00003F00L
+#define PCS_LANE3_COEFF1__TxCoefficientPostCursor_lane3_gen1_MASK 0x003F0000L
+#define PCS_LANE3_COEFF1__rxX_eq_ctle_boost_lane3_gen1_MASK 0x1F000000L
+#define PCS_LANE3_COEFF1__rxX_eq_ctle_pole_lane3_gen1_MASK 0xE0000000L
+//PCS_LANE4_COEFF1
+#define PCS_LANE4_COEFF1__TxCoefficientPreCursor_lane4_gen1__SHIFT 0x0
+#define PCS_LANE4_COEFF1__TxCoefficientMainCursor_lane4_gen1__SHIFT 0x8
+#define PCS_LANE4_COEFF1__TxCoefficientPostCursor_lane4_gen1__SHIFT 0x10
+#define PCS_LANE4_COEFF1__rxX_eq_ctle_boost_lane4_gen1__SHIFT 0x18
+#define PCS_LANE4_COEFF1__rxX_eq_ctle_pole_lane4_gen1__SHIFT 0x1d
+#define PCS_LANE4_COEFF1__TxCoefficientPreCursor_lane4_gen1_MASK 0x0000003FL
+#define PCS_LANE4_COEFF1__TxCoefficientMainCursor_lane4_gen1_MASK 0x00003F00L
+#define PCS_LANE4_COEFF1__TxCoefficientPostCursor_lane4_gen1_MASK 0x003F0000L
+#define PCS_LANE4_COEFF1__rxX_eq_ctle_boost_lane4_gen1_MASK 0x1F000000L
+#define PCS_LANE4_COEFF1__rxX_eq_ctle_pole_lane4_gen1_MASK 0xE0000000L
+//PCS_LANE5_COEFF1
+#define PCS_LANE5_COEFF1__TxCoefficientPreCursor_lane5_gen1__SHIFT 0x0
+#define PCS_LANE5_COEFF1__TxCoefficientMainCursor_lane5_gen1__SHIFT 0x8
+#define PCS_LANE5_COEFF1__TxCoefficientPostCursor_lane5_gen1__SHIFT 0x10
+#define PCS_LANE5_COEFF1__rxX_eq_ctle_boost_lane5_gen1__SHIFT 0x18
+#define PCS_LANE5_COEFF1__rxX_eq_ctle_pole_lane5_gen1__SHIFT 0x1d
+#define PCS_LANE5_COEFF1__TxCoefficientPreCursor_lane5_gen1_MASK 0x0000003FL
+#define PCS_LANE5_COEFF1__TxCoefficientMainCursor_lane5_gen1_MASK 0x00003F00L
+#define PCS_LANE5_COEFF1__TxCoefficientPostCursor_lane5_gen1_MASK 0x003F0000L
+#define PCS_LANE5_COEFF1__rxX_eq_ctle_boost_lane5_gen1_MASK 0x1F000000L
+#define PCS_LANE5_COEFF1__rxX_eq_ctle_pole_lane5_gen1_MASK 0xE0000000L
+//PCS_LANE6_COEFF1
+#define PCS_LANE6_COEFF1__TxCoefficientPreCursor_lane6_gen1__SHIFT 0x0
+#define PCS_LANE6_COEFF1__TxCoefficientMainCursor_lane6_gen1__SHIFT 0x8
+#define PCS_LANE6_COEFF1__TxCoefficientPostCursor_lane6_gen1__SHIFT 0x10
+#define PCS_LANE6_COEFF1__rxX_eq_ctle_boost_lane6_gen1__SHIFT 0x18
+#define PCS_LANE6_COEFF1__rxX_eq_ctle_pole_lane6_gen1__SHIFT 0x1d
+#define PCS_LANE6_COEFF1__TxCoefficientPreCursor_lane6_gen1_MASK 0x0000003FL
+#define PCS_LANE6_COEFF1__TxCoefficientMainCursor_lane6_gen1_MASK 0x00003F00L
+#define PCS_LANE6_COEFF1__TxCoefficientPostCursor_lane6_gen1_MASK 0x003F0000L
+#define PCS_LANE6_COEFF1__rxX_eq_ctle_boost_lane6_gen1_MASK 0x1F000000L
+#define PCS_LANE6_COEFF1__rxX_eq_ctle_pole_lane6_gen1_MASK 0xE0000000L
+//PCS_LANE7_COEFF1
+#define PCS_LANE7_COEFF1__TxCoefficientPreCursor_lane7_gen1__SHIFT 0x0
+#define PCS_LANE7_COEFF1__TxCoefficientMainCursor_lane7_gen1__SHIFT 0x8
+#define PCS_LANE7_COEFF1__TxCoefficientPostCursor_lane7_gen1__SHIFT 0x10
+#define PCS_LANE7_COEFF1__rxX_eq_ctle_boost_lane7_gen1__SHIFT 0x18
+#define PCS_LANE7_COEFF1__rxX_eq_ctle_pole_lane7_gen1__SHIFT 0x1d
+#define PCS_LANE7_COEFF1__TxCoefficientPreCursor_lane7_gen1_MASK 0x0000003FL
+#define PCS_LANE7_COEFF1__TxCoefficientMainCursor_lane7_gen1_MASK 0x00003F00L
+#define PCS_LANE7_COEFF1__TxCoefficientPostCursor_lane7_gen1_MASK 0x003F0000L
+#define PCS_LANE7_COEFF1__rxX_eq_ctle_boost_lane7_gen1_MASK 0x1F000000L
+#define PCS_LANE7_COEFF1__rxX_eq_ctle_pole_lane7_gen1_MASK 0xE0000000L
+//PCS_LANE8_COEFF1
+#define PCS_LANE8_COEFF1__TxCoefficientPreCursor_lane8_gen1__SHIFT 0x0
+#define PCS_LANE8_COEFF1__TxCoefficientMainCursor_lane8_gen1__SHIFT 0x8
+#define PCS_LANE8_COEFF1__TxCoefficientPostCursor_lane8_gen1__SHIFT 0x10
+#define PCS_LANE8_COEFF1__rxX_eq_ctle_boost_lane8_gen1__SHIFT 0x18
+#define PCS_LANE8_COEFF1__rxX_eq_ctle_pole_lane8_gen1__SHIFT 0x1d
+#define PCS_LANE8_COEFF1__TxCoefficientPreCursor_lane8_gen1_MASK 0x0000003FL
+#define PCS_LANE8_COEFF1__TxCoefficientMainCursor_lane8_gen1_MASK 0x00003F00L
+#define PCS_LANE8_COEFF1__TxCoefficientPostCursor_lane8_gen1_MASK 0x003F0000L
+#define PCS_LANE8_COEFF1__rxX_eq_ctle_boost_lane8_gen1_MASK 0x1F000000L
+#define PCS_LANE8_COEFF1__rxX_eq_ctle_pole_lane8_gen1_MASK 0xE0000000L
+//PCS_LANE9_COEFF1
+#define PCS_LANE9_COEFF1__TxCoefficientPreCursor_lane9_gen1__SHIFT 0x0
+#define PCS_LANE9_COEFF1__TxCoefficientMainCursor_lane9_gen1__SHIFT 0x8
+#define PCS_LANE9_COEFF1__TxCoefficientPostCursor_lane9_gen1__SHIFT 0x10
+#define PCS_LANE9_COEFF1__rxX_eq_ctle_boost_lane9_gen1__SHIFT 0x18
+#define PCS_LANE9_COEFF1__rxX_eq_ctle_pole_lane9_gen1__SHIFT 0x1d
+#define PCS_LANE9_COEFF1__TxCoefficientPreCursor_lane9_gen1_MASK 0x0000003FL
+#define PCS_LANE9_COEFF1__TxCoefficientMainCursor_lane9_gen1_MASK 0x00003F00L
+#define PCS_LANE9_COEFF1__TxCoefficientPostCursor_lane9_gen1_MASK 0x003F0000L
+#define PCS_LANE9_COEFF1__rxX_eq_ctle_boost_lane9_gen1_MASK 0x1F000000L
+#define PCS_LANE9_COEFF1__rxX_eq_ctle_pole_lane9_gen1_MASK 0xE0000000L
+//PCS_LANE10_COEFF1
+#define PCS_LANE10_COEFF1__TxCoefficientPreCursor_lane10_gen1__SHIFT 0x0
+#define PCS_LANE10_COEFF1__TxCoefficientMainCursor_lane10_gen1__SHIFT 0x8
+#define PCS_LANE10_COEFF1__TxCoefficientPostCursor_lane10_gen1__SHIFT 0x10
+#define PCS_LANE10_COEFF1__rxX_eq_ctle_boost_lane10_gen1__SHIFT 0x18
+#define PCS_LANE10_COEFF1__rxX_eq_ctle_pole_lane10_gen1__SHIFT 0x1d
+#define PCS_LANE10_COEFF1__TxCoefficientPreCursor_lane10_gen1_MASK 0x0000003FL
+#define PCS_LANE10_COEFF1__TxCoefficientMainCursor_lane10_gen1_MASK 0x00003F00L
+#define PCS_LANE10_COEFF1__TxCoefficientPostCursor_lane10_gen1_MASK 0x003F0000L
+#define PCS_LANE10_COEFF1__rxX_eq_ctle_boost_lane10_gen1_MASK 0x1F000000L
+#define PCS_LANE10_COEFF1__rxX_eq_ctle_pole_lane10_gen1_MASK 0xE0000000L
+//PCS_LANE11_COEFF1
+#define PCS_LANE11_COEFF1__TxCoefficientPreCursor_lane11_gen1__SHIFT 0x0
+#define PCS_LANE11_COEFF1__TxCoefficientMainCursor_lane11_gen1__SHIFT 0x8
+#define PCS_LANE11_COEFF1__TxCoefficientPostCursor_lane11_gen1__SHIFT 0x10
+#define PCS_LANE11_COEFF1__rxX_eq_ctle_boost_lane11_gen1__SHIFT 0x18
+#define PCS_LANE11_COEFF1__rxX_eq_ctle_pole_lane11_gen1__SHIFT 0x1d
+#define PCS_LANE11_COEFF1__TxCoefficientPreCursor_lane11_gen1_MASK 0x0000003FL
+#define PCS_LANE11_COEFF1__TxCoefficientMainCursor_lane11_gen1_MASK 0x00003F00L
+#define PCS_LANE11_COEFF1__TxCoefficientPostCursor_lane11_gen1_MASK 0x003F0000L
+#define PCS_LANE11_COEFF1__rxX_eq_ctle_boost_lane11_gen1_MASK 0x1F000000L
+#define PCS_LANE11_COEFF1__rxX_eq_ctle_pole_lane11_gen1_MASK 0xE0000000L
+//PCS_LANE12_COEFF1
+#define PCS_LANE12_COEFF1__TxCoefficientPreCursor_lane12_gen1__SHIFT 0x0
+#define PCS_LANE12_COEFF1__TxCoefficientMainCursor_lane12_gen1__SHIFT 0x8
+#define PCS_LANE12_COEFF1__TxCoefficientPostCursor_lane12_gen1__SHIFT 0x10
+#define PCS_LANE12_COEFF1__rxX_eq_ctle_boost_lane12_gen1__SHIFT 0x18
+#define PCS_LANE12_COEFF1__rxX_eq_ctle_pole_lane12_gen1__SHIFT 0x1d
+#define PCS_LANE12_COEFF1__TxCoefficientPreCursor_lane12_gen1_MASK 0x0000003FL
+#define PCS_LANE12_COEFF1__TxCoefficientMainCursor_lane12_gen1_MASK 0x00003F00L
+#define PCS_LANE12_COEFF1__TxCoefficientPostCursor_lane12_gen1_MASK 0x003F0000L
+#define PCS_LANE12_COEFF1__rxX_eq_ctle_boost_lane12_gen1_MASK 0x1F000000L
+#define PCS_LANE12_COEFF1__rxX_eq_ctle_pole_lane12_gen1_MASK 0xE0000000L
+//PCS_LANE13_COEFF1
+#define PCS_LANE13_COEFF1__TxCoefficientPreCursor_lane13_gen1__SHIFT 0x0
+#define PCS_LANE13_COEFF1__TxCoefficientMainCursor_lane13_gen1__SHIFT 0x8
+#define PCS_LANE13_COEFF1__TxCoefficientPostCursor_lane13_gen1__SHIFT 0x10
+#define PCS_LANE13_COEFF1__rxX_eq_ctle_boost_lane13_gen1__SHIFT 0x18
+#define PCS_LANE13_COEFF1__rxX_eq_ctle_pole_lane13_gen1__SHIFT 0x1d
+#define PCS_LANE13_COEFF1__TxCoefficientPreCursor_lane13_gen1_MASK 0x0000003FL
+#define PCS_LANE13_COEFF1__TxCoefficientMainCursor_lane13_gen1_MASK 0x00003F00L
+#define PCS_LANE13_COEFF1__TxCoefficientPostCursor_lane13_gen1_MASK 0x003F0000L
+#define PCS_LANE13_COEFF1__rxX_eq_ctle_boost_lane13_gen1_MASK 0x1F000000L
+#define PCS_LANE13_COEFF1__rxX_eq_ctle_pole_lane13_gen1_MASK 0xE0000000L
+//PCS_LANE14_COEFF1
+#define PCS_LANE14_COEFF1__TxCoefficientPreCursor_lane14_gen1__SHIFT 0x0
+#define PCS_LANE14_COEFF1__TxCoefficientMainCursor_lane14_gen1__SHIFT 0x8
+#define PCS_LANE14_COEFF1__TxCoefficientPostCursor_lane14_gen1__SHIFT 0x10
+#define PCS_LANE14_COEFF1__rxX_eq_ctle_boost_lane14_gen1__SHIFT 0x18
+#define PCS_LANE14_COEFF1__rxX_eq_ctle_pole_lane14_gen1__SHIFT 0x1d
+#define PCS_LANE14_COEFF1__TxCoefficientPreCursor_lane14_gen1_MASK 0x0000003FL
+#define PCS_LANE14_COEFF1__TxCoefficientMainCursor_lane14_gen1_MASK 0x00003F00L
+#define PCS_LANE14_COEFF1__TxCoefficientPostCursor_lane14_gen1_MASK 0x003F0000L
+#define PCS_LANE14_COEFF1__rxX_eq_ctle_boost_lane14_gen1_MASK 0x1F000000L
+#define PCS_LANE14_COEFF1__rxX_eq_ctle_pole_lane14_gen1_MASK 0xE0000000L
+//PCS_LANE15_COEFF1
+#define PCS_LANE15_COEFF1__TxCoefficientPreCursor_lane15_gen1__SHIFT 0x0
+#define PCS_LANE15_COEFF1__TxCoefficientMainCursor_lane15_gen1__SHIFT 0x8
+#define PCS_LANE15_COEFF1__TxCoefficientPostCursor_lane15_gen1__SHIFT 0x10
+#define PCS_LANE15_COEFF1__rxX_eq_ctle_boost_lane15_gen1__SHIFT 0x18
+#define PCS_LANE15_COEFF1__rxX_eq_ctle_pole_lane15_gen1__SHIFT 0x1d
+#define PCS_LANE15_COEFF1__TxCoefficientPreCursor_lane15_gen1_MASK 0x0000003FL
+#define PCS_LANE15_COEFF1__TxCoefficientMainCursor_lane15_gen1_MASK 0x00003F00L
+#define PCS_LANE15_COEFF1__TxCoefficientPostCursor_lane15_gen1_MASK 0x003F0000L
+#define PCS_LANE15_COEFF1__rxX_eq_ctle_boost_lane15_gen1_MASK 0x1F000000L
+#define PCS_LANE15_COEFF1__rxX_eq_ctle_pole_lane15_gen1_MASK 0xE0000000L
+//PCS_LANE0_COEFF2
+#define PCS_LANE0_COEFF2__TxCoefficientPreCursor_lane0_gen2__SHIFT 0x0
+#define PCS_LANE0_COEFF2__TxCoefficientMainCursor_lane0_gen2__SHIFT 0x8
+#define PCS_LANE0_COEFF2__TxCoefficientPostCursor_lane0_gen2__SHIFT 0x10
+#define PCS_LANE0_COEFF2__rxX_eq_ctle_boost_lane0_gen2__SHIFT 0x18
+#define PCS_LANE0_COEFF2__rxX_eq_ctle_pole_lane0_gen2__SHIFT 0x1d
+#define PCS_LANE0_COEFF2__TxCoefficientPreCursor_lane0_gen2_MASK 0x0000003FL
+#define PCS_LANE0_COEFF2__TxCoefficientMainCursor_lane0_gen2_MASK 0x00003F00L
+#define PCS_LANE0_COEFF2__TxCoefficientPostCursor_lane0_gen2_MASK 0x003F0000L
+#define PCS_LANE0_COEFF2__rxX_eq_ctle_boost_lane0_gen2_MASK 0x1F000000L
+#define PCS_LANE0_COEFF2__rxX_eq_ctle_pole_lane0_gen2_MASK 0xE0000000L
+//PCS_LANE1_COEFF2
+#define PCS_LANE1_COEFF2__TxCoefficientPreCursor_lane1_gen2__SHIFT 0x0
+#define PCS_LANE1_COEFF2__TxCoefficientMainCursor_lane1_gen2__SHIFT 0x8
+#define PCS_LANE1_COEFF2__TxCoefficientPostCursor_lane1_gen2__SHIFT 0x10
+#define PCS_LANE1_COEFF2__rxX_eq_ctle_boost_lane1_gen2__SHIFT 0x18
+#define PCS_LANE1_COEFF2__rxX_eq_ctle_pole_lane1_gen2__SHIFT 0x1d
+#define PCS_LANE1_COEFF2__TxCoefficientPreCursor_lane1_gen2_MASK 0x0000003FL
+#define PCS_LANE1_COEFF2__TxCoefficientMainCursor_lane1_gen2_MASK 0x00003F00L
+#define PCS_LANE1_COEFF2__TxCoefficientPostCursor_lane1_gen2_MASK 0x003F0000L
+#define PCS_LANE1_COEFF2__rxX_eq_ctle_boost_lane1_gen2_MASK 0x1F000000L
+#define PCS_LANE1_COEFF2__rxX_eq_ctle_pole_lane1_gen2_MASK 0xE0000000L
+//PCS_LANE2_COEFF2
+#define PCS_LANE2_COEFF2__TxCoefficientPreCursor_lane2_gen2__SHIFT 0x0
+#define PCS_LANE2_COEFF2__TxCoefficientMainCursor_lane2_gen2__SHIFT 0x8
+#define PCS_LANE2_COEFF2__TxCoefficientPostCursor_lane2_gen2__SHIFT 0x10
+#define PCS_LANE2_COEFF2__rxX_eq_ctle_boost_lane2_gen2__SHIFT 0x18
+#define PCS_LANE2_COEFF2__rxX_eq_ctle_pole_lane2_gen2__SHIFT 0x1d
+#define PCS_LANE2_COEFF2__TxCoefficientPreCursor_lane2_gen2_MASK 0x0000003FL
+#define PCS_LANE2_COEFF2__TxCoefficientMainCursor_lane2_gen2_MASK 0x00003F00L
+#define PCS_LANE2_COEFF2__TxCoefficientPostCursor_lane2_gen2_MASK 0x003F0000L
+#define PCS_LANE2_COEFF2__rxX_eq_ctle_boost_lane2_gen2_MASK 0x1F000000L
+#define PCS_LANE2_COEFF2__rxX_eq_ctle_pole_lane2_gen2_MASK 0xE0000000L
+//PCS_LANE3_COEFF2
+#define PCS_LANE3_COEFF2__TxCoefficientPreCursor_lane3_gen2__SHIFT 0x0
+#define PCS_LANE3_COEFF2__TxCoefficientMainCursor_lane3_gen2__SHIFT 0x8
+#define PCS_LANE3_COEFF2__TxCoefficientPostCursor_lane3_gen2__SHIFT 0x10
+#define PCS_LANE3_COEFF2__rxX_eq_ctle_boost_lane3_gen2__SHIFT 0x18
+#define PCS_LANE3_COEFF2__rxX_eq_ctle_pole_lane3_gen2__SHIFT 0x1d
+#define PCS_LANE3_COEFF2__TxCoefficientPreCursor_lane3_gen2_MASK 0x0000003FL
+#define PCS_LANE3_COEFF2__TxCoefficientMainCursor_lane3_gen2_MASK 0x00003F00L
+#define PCS_LANE3_COEFF2__TxCoefficientPostCursor_lane3_gen2_MASK 0x003F0000L
+#define PCS_LANE3_COEFF2__rxX_eq_ctle_boost_lane3_gen2_MASK 0x1F000000L
+#define PCS_LANE3_COEFF2__rxX_eq_ctle_pole_lane3_gen2_MASK 0xE0000000L
+//PCS_LANE4_COEFF2
+#define PCS_LANE4_COEFF2__TxCoefficientPreCursor_lane4_gen2__SHIFT 0x0
+#define PCS_LANE4_COEFF2__TxCoefficientMainCursor_lane4_gen2__SHIFT 0x8
+#define PCS_LANE4_COEFF2__TxCoefficientPostCursor_lane4_gen2__SHIFT 0x10
+#define PCS_LANE4_COEFF2__rxX_eq_ctle_boost_lane4_gen2__SHIFT 0x18
+#define PCS_LANE4_COEFF2__rxX_eq_ctle_pole_lane4_gen2__SHIFT 0x1d
+#define PCS_LANE4_COEFF2__TxCoefficientPreCursor_lane4_gen2_MASK 0x0000003FL
+#define PCS_LANE4_COEFF2__TxCoefficientMainCursor_lane4_gen2_MASK 0x00003F00L
+#define PCS_LANE4_COEFF2__TxCoefficientPostCursor_lane4_gen2_MASK 0x003F0000L
+#define PCS_LANE4_COEFF2__rxX_eq_ctle_boost_lane4_gen2_MASK 0x1F000000L
+#define PCS_LANE4_COEFF2__rxX_eq_ctle_pole_lane4_gen2_MASK 0xE0000000L
+//PCS_LANE5_COEFF2
+#define PCS_LANE5_COEFF2__TxCoefficientPreCursor_lane5_gen2__SHIFT 0x0
+#define PCS_LANE5_COEFF2__TxCoefficientMainCursor_lane5_gen2__SHIFT 0x8
+#define PCS_LANE5_COEFF2__TxCoefficientPostCursor_lane5_gen2__SHIFT 0x10
+#define PCS_LANE5_COEFF2__rxX_eq_ctle_boost_lane5_gen2__SHIFT 0x18
+#define PCS_LANE5_COEFF2__rxX_eq_ctle_pole_lane5_gen2__SHIFT 0x1d
+#define PCS_LANE5_COEFF2__TxCoefficientPreCursor_lane5_gen2_MASK 0x0000003FL
+#define PCS_LANE5_COEFF2__TxCoefficientMainCursor_lane5_gen2_MASK 0x00003F00L
+#define PCS_LANE5_COEFF2__TxCoefficientPostCursor_lane5_gen2_MASK 0x003F0000L
+#define PCS_LANE5_COEFF2__rxX_eq_ctle_boost_lane5_gen2_MASK 0x1F000000L
+#define PCS_LANE5_COEFF2__rxX_eq_ctle_pole_lane5_gen2_MASK 0xE0000000L
+//PCS_LANE6_COEFF2
+#define PCS_LANE6_COEFF2__TxCoefficientPreCursor_lane6_gen2__SHIFT 0x0
+#define PCS_LANE6_COEFF2__TxCoefficientMainCursor_lane6_gen2__SHIFT 0x8
+#define PCS_LANE6_COEFF2__TxCoefficientPostCursor_lane6_gen2__SHIFT 0x10
+#define PCS_LANE6_COEFF2__rxX_eq_ctle_boost_lane6_gen2__SHIFT 0x18
+#define PCS_LANE6_COEFF2__rxX_eq_ctle_pole_lane6_gen2__SHIFT 0x1d
+#define PCS_LANE6_COEFF2__TxCoefficientPreCursor_lane6_gen2_MASK 0x0000003FL
+#define PCS_LANE6_COEFF2__TxCoefficientMainCursor_lane6_gen2_MASK 0x00003F00L
+#define PCS_LANE6_COEFF2__TxCoefficientPostCursor_lane6_gen2_MASK 0x003F0000L
+#define PCS_LANE6_COEFF2__rxX_eq_ctle_boost_lane6_gen2_MASK 0x1F000000L
+#define PCS_LANE6_COEFF2__rxX_eq_ctle_pole_lane6_gen2_MASK 0xE0000000L
+//PCS_LANE7_COEFF2
+#define PCS_LANE7_COEFF2__TxCoefficientPreCursor_lane7_gen2__SHIFT 0x0
+#define PCS_LANE7_COEFF2__TxCoefficientMainCursor_lane7_gen2__SHIFT 0x8
+#define PCS_LANE7_COEFF2__TxCoefficientPostCursor_lane7_gen2__SHIFT 0x10
+#define PCS_LANE7_COEFF2__rxX_eq_ctle_boost_lane7_gen2__SHIFT 0x18
+#define PCS_LANE7_COEFF2__rxX_eq_ctle_pole_lane7_gen2__SHIFT 0x1d
+#define PCS_LANE7_COEFF2__TxCoefficientPreCursor_lane7_gen2_MASK 0x0000003FL
+#define PCS_LANE7_COEFF2__TxCoefficientMainCursor_lane7_gen2_MASK 0x00003F00L
+#define PCS_LANE7_COEFF2__TxCoefficientPostCursor_lane7_gen2_MASK 0x003F0000L
+#define PCS_LANE7_COEFF2__rxX_eq_ctle_boost_lane7_gen2_MASK 0x1F000000L
+#define PCS_LANE7_COEFF2__rxX_eq_ctle_pole_lane7_gen2_MASK 0xE0000000L
+//PCS_LANE8_COEFF2
+#define PCS_LANE8_COEFF2__TxCoefficientPreCursor_lane8_gen2__SHIFT 0x0
+#define PCS_LANE8_COEFF2__TxCoefficientMainCursor_lane8_gen2__SHIFT 0x8
+#define PCS_LANE8_COEFF2__TxCoefficientPostCursor_lane8_gen2__SHIFT 0x10
+#define PCS_LANE8_COEFF2__rxX_eq_ctle_boost_lane8_gen2__SHIFT 0x18
+#define PCS_LANE8_COEFF2__rxX_eq_ctle_pole_lane8_gen2__SHIFT 0x1d
+#define PCS_LANE8_COEFF2__TxCoefficientPreCursor_lane8_gen2_MASK 0x0000003FL
+#define PCS_LANE8_COEFF2__TxCoefficientMainCursor_lane8_gen2_MASK 0x00003F00L
+#define PCS_LANE8_COEFF2__TxCoefficientPostCursor_lane8_gen2_MASK 0x003F0000L
+#define PCS_LANE8_COEFF2__rxX_eq_ctle_boost_lane8_gen2_MASK 0x1F000000L
+#define PCS_LANE8_COEFF2__rxX_eq_ctle_pole_lane8_gen2_MASK 0xE0000000L
+//PCS_LANE9_COEFF2
+#define PCS_LANE9_COEFF2__TxCoefficientPreCursor_lane9_gen2__SHIFT 0x0
+#define PCS_LANE9_COEFF2__TxCoefficientMainCursor_lane9_gen2__SHIFT 0x8
+#define PCS_LANE9_COEFF2__TxCoefficientPostCursor_lane9_gen2__SHIFT 0x10
+#define PCS_LANE9_COEFF2__rxX_eq_ctle_boost_lane9_gen2__SHIFT 0x18
+#define PCS_LANE9_COEFF2__rxX_eq_ctle_pole_lane9_gen2__SHIFT 0x1d
+#define PCS_LANE9_COEFF2__TxCoefficientPreCursor_lane9_gen2_MASK 0x0000003FL
+#define PCS_LANE9_COEFF2__TxCoefficientMainCursor_lane9_gen2_MASK 0x00003F00L
+#define PCS_LANE9_COEFF2__TxCoefficientPostCursor_lane9_gen2_MASK 0x003F0000L
+#define PCS_LANE9_COEFF2__rxX_eq_ctle_boost_lane9_gen2_MASK 0x1F000000L
+#define PCS_LANE9_COEFF2__rxX_eq_ctle_pole_lane9_gen2_MASK 0xE0000000L
+//PCS_LANE10_COEFF2
+#define PCS_LANE10_COEFF2__TxCoefficientPreCursor_lane10_gen2__SHIFT 0x0
+#define PCS_LANE10_COEFF2__TxCoefficientMainCursor_lane10_gen2__SHIFT 0x8
+#define PCS_LANE10_COEFF2__TxCoefficientPostCursor_lane10_gen2__SHIFT 0x10
+#define PCS_LANE10_COEFF2__rxX_eq_ctle_boost_lane10_gen2__SHIFT 0x18
+#define PCS_LANE10_COEFF2__rxX_eq_ctle_pole_lane10_gen2__SHIFT 0x1d
+#define PCS_LANE10_COEFF2__TxCoefficientPreCursor_lane10_gen2_MASK 0x0000003FL
+#define PCS_LANE10_COEFF2__TxCoefficientMainCursor_lane10_gen2_MASK 0x00003F00L
+#define PCS_LANE10_COEFF2__TxCoefficientPostCursor_lane10_gen2_MASK 0x003F0000L
+#define PCS_LANE10_COEFF2__rxX_eq_ctle_boost_lane10_gen2_MASK 0x1F000000L
+#define PCS_LANE10_COEFF2__rxX_eq_ctle_pole_lane10_gen2_MASK 0xE0000000L
+//PCS_LANE11_COEFF2
+#define PCS_LANE11_COEFF2__TxCoefficientPreCursor_lane11_gen2__SHIFT 0x0
+#define PCS_LANE11_COEFF2__TxCoefficientMainCursor_lane11_gen2__SHIFT 0x8
+#define PCS_LANE11_COEFF2__TxCoefficientPostCursor_lane11_gen2__SHIFT 0x10
+#define PCS_LANE11_COEFF2__rxX_eq_ctle_boost_lane11_gen2__SHIFT 0x18
+#define PCS_LANE11_COEFF2__rxX_eq_ctle_pole_lane11_gen2__SHIFT 0x1d
+#define PCS_LANE11_COEFF2__TxCoefficientPreCursor_lane11_gen2_MASK 0x0000003FL
+#define PCS_LANE11_COEFF2__TxCoefficientMainCursor_lane11_gen2_MASK 0x00003F00L
+#define PCS_LANE11_COEFF2__TxCoefficientPostCursor_lane11_gen2_MASK 0x003F0000L
+#define PCS_LANE11_COEFF2__rxX_eq_ctle_boost_lane11_gen2_MASK 0x1F000000L
+#define PCS_LANE11_COEFF2__rxX_eq_ctle_pole_lane11_gen2_MASK 0xE0000000L
+//PCS_LANE12_COEFF2
+#define PCS_LANE12_COEFF2__TxCoefficientPreCursor_lane12_gen2__SHIFT 0x0
+#define PCS_LANE12_COEFF2__TxCoefficientMainCursor_lane12_gen2__SHIFT 0x8
+#define PCS_LANE12_COEFF2__TxCoefficientPostCursor_lane12_gen2__SHIFT 0x10
+#define PCS_LANE12_COEFF2__rxX_eq_ctle_boost_lane12_gen2__SHIFT 0x18
+#define PCS_LANE12_COEFF2__rxX_eq_ctle_pole_lane12_gen2__SHIFT 0x1d
+#define PCS_LANE12_COEFF2__TxCoefficientPreCursor_lane12_gen2_MASK 0x0000003FL
+#define PCS_LANE12_COEFF2__TxCoefficientMainCursor_lane12_gen2_MASK 0x00003F00L
+#define PCS_LANE12_COEFF2__TxCoefficientPostCursor_lane12_gen2_MASK 0x003F0000L
+#define PCS_LANE12_COEFF2__rxX_eq_ctle_boost_lane12_gen2_MASK 0x1F000000L
+#define PCS_LANE12_COEFF2__rxX_eq_ctle_pole_lane12_gen2_MASK 0xE0000000L
+//PCS_LANE13_COEFF2
+#define PCS_LANE13_COEFF2__TxCoefficientPreCursor_lane13_gen2__SHIFT 0x0
+#define PCS_LANE13_COEFF2__TxCoefficientMainCursor_lane13_gen2__SHIFT 0x8
+#define PCS_LANE13_COEFF2__TxCoefficientPostCursor_lane13_gen2__SHIFT 0x10
+#define PCS_LANE13_COEFF2__rxX_eq_ctle_boost_lane13_gen2__SHIFT 0x18
+#define PCS_LANE13_COEFF2__rxX_eq_ctle_pole_lane13_gen2__SHIFT 0x1d
+#define PCS_LANE13_COEFF2__TxCoefficientPreCursor_lane13_gen2_MASK 0x0000003FL
+#define PCS_LANE13_COEFF2__TxCoefficientMainCursor_lane13_gen2_MASK 0x00003F00L
+#define PCS_LANE13_COEFF2__TxCoefficientPostCursor_lane13_gen2_MASK 0x003F0000L
+#define PCS_LANE13_COEFF2__rxX_eq_ctle_boost_lane13_gen2_MASK 0x1F000000L
+#define PCS_LANE13_COEFF2__rxX_eq_ctle_pole_lane13_gen2_MASK 0xE0000000L
+//PCS_LANE14_COEFF2
+#define PCS_LANE14_COEFF2__TxCoefficientPreCursor_lane14_gen2__SHIFT 0x0
+#define PCS_LANE14_COEFF2__TxCoefficientMainCursor_lane14_gen2__SHIFT 0x8
+#define PCS_LANE14_COEFF2__TxCoefficientPostCursor_lane14_gen2__SHIFT 0x10
+#define PCS_LANE14_COEFF2__rxX_eq_ctle_boost_lane14_gen2__SHIFT 0x18
+#define PCS_LANE14_COEFF2__rxX_eq_ctle_pole_lane14_gen2__SHIFT 0x1d
+#define PCS_LANE14_COEFF2__TxCoefficientPreCursor_lane14_gen2_MASK 0x0000003FL
+#define PCS_LANE14_COEFF2__TxCoefficientMainCursor_lane14_gen2_MASK 0x00003F00L
+#define PCS_LANE14_COEFF2__TxCoefficientPostCursor_lane14_gen2_MASK 0x003F0000L
+#define PCS_LANE14_COEFF2__rxX_eq_ctle_boost_lane14_gen2_MASK 0x1F000000L
+#define PCS_LANE14_COEFF2__rxX_eq_ctle_pole_lane14_gen2_MASK 0xE0000000L
+//PCS_LANE15_COEFF2
+#define PCS_LANE15_COEFF2__TxCoefficientPreCursor_lane15_gen2__SHIFT 0x0
+#define PCS_LANE15_COEFF2__TxCoefficientMainCursor_lane15_gen2__SHIFT 0x8
+#define PCS_LANE15_COEFF2__TxCoefficientPostCursor_lane15_gen2__SHIFT 0x10
+#define PCS_LANE15_COEFF2__rxX_eq_ctle_boost_lane15_gen2__SHIFT 0x18
+#define PCS_LANE15_COEFF2__rxX_eq_ctle_pole_lane15_gen2__SHIFT 0x1d
+#define PCS_LANE15_COEFF2__TxCoefficientPreCursor_lane15_gen2_MASK 0x0000003FL
+#define PCS_LANE15_COEFF2__TxCoefficientMainCursor_lane15_gen2_MASK 0x00003F00L
+#define PCS_LANE15_COEFF2__TxCoefficientPostCursor_lane15_gen2_MASK 0x003F0000L
+#define PCS_LANE15_COEFF2__rxX_eq_ctle_boost_lane15_gen2_MASK 0x1F000000L
+#define PCS_LANE15_COEFF2__rxX_eq_ctle_pole_lane15_gen2_MASK 0xE0000000L
+//PCS_LANE0_COEFF3
+#define PCS_LANE0_COEFF3__TxCoefficientPreCursor_lane0_gen3__SHIFT 0x0
+#define PCS_LANE0_COEFF3__TxCoefficientMainCursor_lane0_gen3__SHIFT 0x8
+#define PCS_LANE0_COEFF3__TxCoefficientPostCursor_lane0_gen3__SHIFT 0x10
+#define PCS_LANE0_COEFF3__rxX_eq_ctle_boost_lane0_gen3__SHIFT 0x18
+#define PCS_LANE0_COEFF3__rxX_eq_ctle_pole_lane0_gen3__SHIFT 0x1d
+#define PCS_LANE0_COEFF3__TxCoefficientPreCursor_lane0_gen3_MASK 0x0000003FL
+#define PCS_LANE0_COEFF3__TxCoefficientMainCursor_lane0_gen3_MASK 0x00003F00L
+#define PCS_LANE0_COEFF3__TxCoefficientPostCursor_lane0_gen3_MASK 0x003F0000L
+#define PCS_LANE0_COEFF3__rxX_eq_ctle_boost_lane0_gen3_MASK 0x1F000000L
+#define PCS_LANE0_COEFF3__rxX_eq_ctle_pole_lane0_gen3_MASK 0xE0000000L
+//PCS_LANE1_COEFF3
+#define PCS_LANE1_COEFF3__TxCoefficientPreCursor_lane1_gen3__SHIFT 0x0
+#define PCS_LANE1_COEFF3__TxCoefficientMainCursor_lane1_gen3__SHIFT 0x8
+#define PCS_LANE1_COEFF3__TxCoefficientPostCursor_lane1_gen3__SHIFT 0x10
+#define PCS_LANE1_COEFF3__rxX_eq_ctle_boost_lane1_gen3__SHIFT 0x18
+#define PCS_LANE1_COEFF3__rxX_eq_ctle_pole_lane1_gen3__SHIFT 0x1d
+#define PCS_LANE1_COEFF3__TxCoefficientPreCursor_lane1_gen3_MASK 0x0000003FL
+#define PCS_LANE1_COEFF3__TxCoefficientMainCursor_lane1_gen3_MASK 0x00003F00L
+#define PCS_LANE1_COEFF3__TxCoefficientPostCursor_lane1_gen3_MASK 0x003F0000L
+#define PCS_LANE1_COEFF3__rxX_eq_ctle_boost_lane1_gen3_MASK 0x1F000000L
+#define PCS_LANE1_COEFF3__rxX_eq_ctle_pole_lane1_gen3_MASK 0xE0000000L
+//PCS_LANE2_COEFF3
+#define PCS_LANE2_COEFF3__TxCoefficientPreCursor_lane2_gen3__SHIFT 0x0
+#define PCS_LANE2_COEFF3__TxCoefficientMainCursor_lane2_gen3__SHIFT 0x8
+#define PCS_LANE2_COEFF3__TxCoefficientPostCursor_lane2_gen3__SHIFT 0x10
+#define PCS_LANE2_COEFF3__rxX_eq_ctle_boost_lane2_gen3__SHIFT 0x18
+#define PCS_LANE2_COEFF3__rxX_eq_ctle_pole_lane2_gen3__SHIFT 0x1d
+#define PCS_LANE2_COEFF3__TxCoefficientPreCursor_lane2_gen3_MASK 0x0000003FL
+#define PCS_LANE2_COEFF3__TxCoefficientMainCursor_lane2_gen3_MASK 0x00003F00L
+#define PCS_LANE2_COEFF3__TxCoefficientPostCursor_lane2_gen3_MASK 0x003F0000L
+#define PCS_LANE2_COEFF3__rxX_eq_ctle_boost_lane2_gen3_MASK 0x1F000000L
+#define PCS_LANE2_COEFF3__rxX_eq_ctle_pole_lane2_gen3_MASK 0xE0000000L
+//PCS_LANE3_COEFF3
+#define PCS_LANE3_COEFF3__TxCoefficientPreCursor_lane3_gen3__SHIFT 0x0
+#define PCS_LANE3_COEFF3__TxCoefficientMainCursor_lane3_gen3__SHIFT 0x8
+#define PCS_LANE3_COEFF3__TxCoefficientPostCursor_lane3_gen3__SHIFT 0x10
+#define PCS_LANE3_COEFF3__rxX_eq_ctle_boost_lane3_gen3__SHIFT 0x18
+#define PCS_LANE3_COEFF3__rxX_eq_ctle_pole_lane3_gen3__SHIFT 0x1d
+#define PCS_LANE3_COEFF3__TxCoefficientPreCursor_lane3_gen3_MASK 0x0000003FL
+#define PCS_LANE3_COEFF3__TxCoefficientMainCursor_lane3_gen3_MASK 0x00003F00L
+#define PCS_LANE3_COEFF3__TxCoefficientPostCursor_lane3_gen3_MASK 0x003F0000L
+#define PCS_LANE3_COEFF3__rxX_eq_ctle_boost_lane3_gen3_MASK 0x1F000000L
+#define PCS_LANE3_COEFF3__rxX_eq_ctle_pole_lane3_gen3_MASK 0xE0000000L
+//PCS_LANE4_COEFF3
+#define PCS_LANE4_COEFF3__TxCoefficientPreCursor_lane4_gen3__SHIFT 0x0
+#define PCS_LANE4_COEFF3__TxCoefficientMainCursor_lane4_gen3__SHIFT 0x8
+#define PCS_LANE4_COEFF3__TxCoefficientPostCursor_lane4_gen3__SHIFT 0x10
+#define PCS_LANE4_COEFF3__rxX_eq_ctle_boost_lane4_gen3__SHIFT 0x18
+#define PCS_LANE4_COEFF3__rxX_eq_ctle_pole_lane4_gen3__SHIFT 0x1d
+#define PCS_LANE4_COEFF3__TxCoefficientPreCursor_lane4_gen3_MASK 0x0000003FL
+#define PCS_LANE4_COEFF3__TxCoefficientMainCursor_lane4_gen3_MASK 0x00003F00L
+#define PCS_LANE4_COEFF3__TxCoefficientPostCursor_lane4_gen3_MASK 0x003F0000L
+#define PCS_LANE4_COEFF3__rxX_eq_ctle_boost_lane4_gen3_MASK 0x1F000000L
+#define PCS_LANE4_COEFF3__rxX_eq_ctle_pole_lane4_gen3_MASK 0xE0000000L
+//PCS_LANE5_COEFF3
+#define PCS_LANE5_COEFF3__TxCoefficientPreCursor_lane5_gen3__SHIFT 0x0
+#define PCS_LANE5_COEFF3__TxCoefficientMainCursor_lane5_gen3__SHIFT 0x8
+#define PCS_LANE5_COEFF3__TxCoefficientPostCursor_lane5_gen3__SHIFT 0x10
+#define PCS_LANE5_COEFF3__rxX_eq_ctle_boost_lane5_gen3__SHIFT 0x18
+#define PCS_LANE5_COEFF3__rxX_eq_ctle_pole_lane5_gen3__SHIFT 0x1d
+#define PCS_LANE5_COEFF3__TxCoefficientPreCursor_lane5_gen3_MASK 0x0000003FL
+#define PCS_LANE5_COEFF3__TxCoefficientMainCursor_lane5_gen3_MASK 0x00003F00L
+#define PCS_LANE5_COEFF3__TxCoefficientPostCursor_lane5_gen3_MASK 0x003F0000L
+#define PCS_LANE5_COEFF3__rxX_eq_ctle_boost_lane5_gen3_MASK 0x1F000000L
+#define PCS_LANE5_COEFF3__rxX_eq_ctle_pole_lane5_gen3_MASK 0xE0000000L
+//PCS_LANE6_COEFF3
+#define PCS_LANE6_COEFF3__TxCoefficientPreCursor_lane6_gen3__SHIFT 0x0
+#define PCS_LANE6_COEFF3__TxCoefficientMainCursor_lane6_gen3__SHIFT 0x8
+#define PCS_LANE6_COEFF3__TxCoefficientPostCursor_lane6_gen3__SHIFT 0x10
+#define PCS_LANE6_COEFF3__rxX_eq_ctle_boost_lane6_gen3__SHIFT 0x18
+#define PCS_LANE6_COEFF3__rxX_eq_ctle_pole_lane6_gen3__SHIFT 0x1d
+#define PCS_LANE6_COEFF3__TxCoefficientPreCursor_lane6_gen3_MASK 0x0000003FL
+#define PCS_LANE6_COEFF3__TxCoefficientMainCursor_lane6_gen3_MASK 0x00003F00L
+#define PCS_LANE6_COEFF3__TxCoefficientPostCursor_lane6_gen3_MASK 0x003F0000L
+#define PCS_LANE6_COEFF3__rxX_eq_ctle_boost_lane6_gen3_MASK 0x1F000000L
+#define PCS_LANE6_COEFF3__rxX_eq_ctle_pole_lane6_gen3_MASK 0xE0000000L
+//PCS_LANE7_COEFF3
+#define PCS_LANE7_COEFF3__TxCoefficientPreCursor_lane7_gen3__SHIFT 0x0
+#define PCS_LANE7_COEFF3__TxCoefficientMainCursor_lane7_gen3__SHIFT 0x8
+#define PCS_LANE7_COEFF3__TxCoefficientPostCursor_lane7_gen3__SHIFT 0x10
+#define PCS_LANE7_COEFF3__rxX_eq_ctle_boost_lane7_gen3__SHIFT 0x18
+#define PCS_LANE7_COEFF3__rxX_eq_ctle_pole_lane7_gen3__SHIFT 0x1d
+#define PCS_LANE7_COEFF3__TxCoefficientPreCursor_lane7_gen3_MASK 0x0000003FL
+#define PCS_LANE7_COEFF3__TxCoefficientMainCursor_lane7_gen3_MASK 0x00003F00L
+#define PCS_LANE7_COEFF3__TxCoefficientPostCursor_lane7_gen3_MASK 0x003F0000L
+#define PCS_LANE7_COEFF3__rxX_eq_ctle_boost_lane7_gen3_MASK 0x1F000000L
+#define PCS_LANE7_COEFF3__rxX_eq_ctle_pole_lane7_gen3_MASK 0xE0000000L
+//PCS_LANE8_COEFF3
+#define PCS_LANE8_COEFF3__TxCoefficientPreCursor_lane8_gen3__SHIFT 0x0
+#define PCS_LANE8_COEFF3__TxCoefficientMainCursor_lane8_gen3__SHIFT 0x8
+#define PCS_LANE8_COEFF3__TxCoefficientPostCursor_lane8_gen3__SHIFT 0x10
+#define PCS_LANE8_COEFF3__rxX_eq_ctle_boost_lane8_gen3__SHIFT 0x18
+#define PCS_LANE8_COEFF3__rxX_eq_ctle_pole_lane8_gen3__SHIFT 0x1d
+#define PCS_LANE8_COEFF3__TxCoefficientPreCursor_lane8_gen3_MASK 0x0000003FL
+#define PCS_LANE8_COEFF3__TxCoefficientMainCursor_lane8_gen3_MASK 0x00003F00L
+#define PCS_LANE8_COEFF3__TxCoefficientPostCursor_lane8_gen3_MASK 0x003F0000L
+#define PCS_LANE8_COEFF3__rxX_eq_ctle_boost_lane8_gen3_MASK 0x1F000000L
+#define PCS_LANE8_COEFF3__rxX_eq_ctle_pole_lane8_gen3_MASK 0xE0000000L
+//PCS_LANE9_COEFF3
+#define PCS_LANE9_COEFF3__TxCoefficientPreCursor_lane9_gen3__SHIFT 0x0
+#define PCS_LANE9_COEFF3__TxCoefficientMainCursor_lane9_gen3__SHIFT 0x8
+#define PCS_LANE9_COEFF3__TxCoefficientPostCursor_lane9_gen3__SHIFT 0x10
+#define PCS_LANE9_COEFF3__rxX_eq_ctle_boost_lane9_gen3__SHIFT 0x18
+#define PCS_LANE9_COEFF3__rxX_eq_ctle_pole_lane9_gen3__SHIFT 0x1d
+#define PCS_LANE9_COEFF3__TxCoefficientPreCursor_lane9_gen3_MASK 0x0000003FL
+#define PCS_LANE9_COEFF3__TxCoefficientMainCursor_lane9_gen3_MASK 0x00003F00L
+#define PCS_LANE9_COEFF3__TxCoefficientPostCursor_lane9_gen3_MASK 0x003F0000L
+#define PCS_LANE9_COEFF3__rxX_eq_ctle_boost_lane9_gen3_MASK 0x1F000000L
+#define PCS_LANE9_COEFF3__rxX_eq_ctle_pole_lane9_gen3_MASK 0xE0000000L
+//PCS_LANE10_COEFF3
+#define PCS_LANE10_COEFF3__TxCoefficientPreCursor_lane10_gen3__SHIFT 0x0
+#define PCS_LANE10_COEFF3__TxCoefficientMainCursor_lane10_gen3__SHIFT 0x8
+#define PCS_LANE10_COEFF3__TxCoefficientPostCursor_lane10_gen3__SHIFT 0x10
+#define PCS_LANE10_COEFF3__rxX_eq_ctle_boost_lane10_gen3__SHIFT 0x18
+#define PCS_LANE10_COEFF3__rxX_eq_ctle_pole_lane10_gen3__SHIFT 0x1d
+#define PCS_LANE10_COEFF3__TxCoefficientPreCursor_lane10_gen3_MASK 0x0000003FL
+#define PCS_LANE10_COEFF3__TxCoefficientMainCursor_lane10_gen3_MASK 0x00003F00L
+#define PCS_LANE10_COEFF3__TxCoefficientPostCursor_lane10_gen3_MASK 0x003F0000L
+#define PCS_LANE10_COEFF3__rxX_eq_ctle_boost_lane10_gen3_MASK 0x1F000000L
+#define PCS_LANE10_COEFF3__rxX_eq_ctle_pole_lane10_gen3_MASK 0xE0000000L
+//PCS_LANE11_COEFF3
+#define PCS_LANE11_COEFF3__TxCoefficientPreCursor_lane11_gen3__SHIFT 0x0
+#define PCS_LANE11_COEFF3__TxCoefficientMainCursor_lane11_gen3__SHIFT 0x8
+#define PCS_LANE11_COEFF3__TxCoefficientPostCursor_lane11_gen3__SHIFT 0x10
+#define PCS_LANE11_COEFF3__rxX_eq_ctle_boost_lane11_gen3__SHIFT 0x18
+#define PCS_LANE11_COEFF3__rxX_eq_ctle_pole_lane11_gen3__SHIFT 0x1d
+#define PCS_LANE11_COEFF3__TxCoefficientPreCursor_lane11_gen3_MASK 0x0000003FL
+#define PCS_LANE11_COEFF3__TxCoefficientMainCursor_lane11_gen3_MASK 0x00003F00L
+#define PCS_LANE11_COEFF3__TxCoefficientPostCursor_lane11_gen3_MASK 0x003F0000L
+#define PCS_LANE11_COEFF3__rxX_eq_ctle_boost_lane11_gen3_MASK 0x1F000000L
+#define PCS_LANE11_COEFF3__rxX_eq_ctle_pole_lane11_gen3_MASK 0xE0000000L
+//PCS_LANE12_COEFF3
+#define PCS_LANE12_COEFF3__TxCoefficientPreCursor_lane12_gen3__SHIFT 0x0
+#define PCS_LANE12_COEFF3__TxCoefficientMainCursor_lane12_gen3__SHIFT 0x8
+#define PCS_LANE12_COEFF3__TxCoefficientPostCursor_lane12_gen3__SHIFT 0x10
+#define PCS_LANE12_COEFF3__rxX_eq_ctle_boost_lane12_gen3__SHIFT 0x18
+#define PCS_LANE12_COEFF3__rxX_eq_ctle_pole_lane12_gen3__SHIFT 0x1d
+#define PCS_LANE12_COEFF3__TxCoefficientPreCursor_lane12_gen3_MASK 0x0000003FL
+#define PCS_LANE12_COEFF3__TxCoefficientMainCursor_lane12_gen3_MASK 0x00003F00L
+#define PCS_LANE12_COEFF3__TxCoefficientPostCursor_lane12_gen3_MASK 0x003F0000L
+#define PCS_LANE12_COEFF3__rxX_eq_ctle_boost_lane12_gen3_MASK 0x1F000000L
+#define PCS_LANE12_COEFF3__rxX_eq_ctle_pole_lane12_gen3_MASK 0xE0000000L
+//PCS_LANE13_COEFF3
+#define PCS_LANE13_COEFF3__TxCoefficientPreCursor_lane13_gen3__SHIFT 0x0
+#define PCS_LANE13_COEFF3__TxCoefficientMainCursor_lane13_gen3__SHIFT 0x8
+#define PCS_LANE13_COEFF3__TxCoefficientPostCursor_lane13_gen3__SHIFT 0x10
+#define PCS_LANE13_COEFF3__rxX_eq_ctle_boost_lane13_gen3__SHIFT 0x18
+#define PCS_LANE13_COEFF3__rxX_eq_ctle_pole_lane13_gen3__SHIFT 0x1d
+#define PCS_LANE13_COEFF3__TxCoefficientPreCursor_lane13_gen3_MASK 0x0000003FL
+#define PCS_LANE13_COEFF3__TxCoefficientMainCursor_lane13_gen3_MASK 0x00003F00L
+#define PCS_LANE13_COEFF3__TxCoefficientPostCursor_lane13_gen3_MASK 0x003F0000L
+#define PCS_LANE13_COEFF3__rxX_eq_ctle_boost_lane13_gen3_MASK 0x1F000000L
+#define PCS_LANE13_COEFF3__rxX_eq_ctle_pole_lane13_gen3_MASK 0xE0000000L
+//PCS_LANE14_COEFF3
+#define PCS_LANE14_COEFF3__TxCoefficientPreCursor_lane14_gen3__SHIFT 0x0
+#define PCS_LANE14_COEFF3__TxCoefficientMainCursor_lane14_gen3__SHIFT 0x8
+#define PCS_LANE14_COEFF3__TxCoefficientPostCursor_lane14_gen3__SHIFT 0x10
+#define PCS_LANE14_COEFF3__rxX_eq_ctle_boost_lane14_gen3__SHIFT 0x18
+#define PCS_LANE14_COEFF3__rxX_eq_ctle_pole_lane14_gen3__SHIFT 0x1d
+#define PCS_LANE14_COEFF3__TxCoefficientPreCursor_lane14_gen3_MASK 0x0000003FL
+#define PCS_LANE14_COEFF3__TxCoefficientMainCursor_lane14_gen3_MASK 0x00003F00L
+#define PCS_LANE14_COEFF3__TxCoefficientPostCursor_lane14_gen3_MASK 0x003F0000L
+#define PCS_LANE14_COEFF3__rxX_eq_ctle_boost_lane14_gen3_MASK 0x1F000000L
+#define PCS_LANE14_COEFF3__rxX_eq_ctle_pole_lane14_gen3_MASK 0xE0000000L
+//PCS_LANE15_COEFF3
+#define PCS_LANE15_COEFF3__TxCoefficientPreCursor_lane15_gen3__SHIFT 0x0
+#define PCS_LANE15_COEFF3__TxCoefficientMainCursor_lane15_gen3__SHIFT 0x8
+#define PCS_LANE15_COEFF3__TxCoefficientPostCursor_lane15_gen3__SHIFT 0x10
+#define PCS_LANE15_COEFF3__rxX_eq_ctle_boost_lane15_gen3__SHIFT 0x18
+#define PCS_LANE15_COEFF3__rxX_eq_ctle_pole_lane15_gen3__SHIFT 0x1d
+#define PCS_LANE15_COEFF3__TxCoefficientPreCursor_lane15_gen3_MASK 0x0000003FL
+#define PCS_LANE15_COEFF3__TxCoefficientMainCursor_lane15_gen3_MASK 0x00003F00L
+#define PCS_LANE15_COEFF3__TxCoefficientPostCursor_lane15_gen3_MASK 0x003F0000L
+#define PCS_LANE15_COEFF3__rxX_eq_ctle_boost_lane15_gen3_MASK 0x1F000000L
+#define PCS_LANE15_COEFF3__rxX_eq_ctle_pole_lane15_gen3_MASK 0xE0000000L
+
+
+// addressBlock: nbio_pipe_pcs_dwc_e12mp_phy_x4_ns1_dwc_e12mp_phy_x4_ns_UP16_dwc_e12mp_phy_x4_ns_UP16_mem_map
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_IDCODE_LO
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_IDCODE_LO__data__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_IDCODE_LO__data_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_IDCODE_HI
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_IDCODE_HI__data__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_IDCODE_HI__data_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK 0x1FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK 0x1FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_REQ_IN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_REQ_OUT__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_ACK_IN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_ACK_OUT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__BG_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__PHY_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_REQ_IN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_REQ_OUT_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_ACK_IN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_ACK_OUT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__BG_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x3FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RX_TERM_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_STAT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_STAT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK 0x7F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK 0x1E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK 0x07FCL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK 0x7F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK 0x1E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK 0x07FCL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__NC40__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__lpn_vreg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__NC40_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__lpn_vreg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__enable_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__cal_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__reset_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_right__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_left__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_vco_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_right_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_left_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_cp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__meas_vreg_vco_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__meas_vreg_l_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vreg_r_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vreg_vp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vreg_cp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_ctl_fine_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_mag_ref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__force_fine_high__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__force_fine_low__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__override_amp_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__override_amp_high__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__override_amp_low__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__atb_select__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__force_fine_high_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__force_fine_low_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__override_amp_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__override_amp_high_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__override_amp_low_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__atb_select_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__NC40__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__lpn_vreg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__NC40_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__lpn_vreg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__enable_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__cal_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__reset_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_right__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_left__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_vco_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_right_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_left_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_cp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__meas_vreg_vco_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__meas_vreg_l_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vreg_r_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vreg_vp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vreg_cp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_ctl_fine_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_mag_ref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__force_fine_high__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__force_fine_low__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__override_amp_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__override_amp_high__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__override_amp_low__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__atb_select__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__force_fine_high_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__force_fine_low_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__override_amp_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__override_amp_high_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__override_amp_low_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__atb_select_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__NC7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__NC7_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK 0x001CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__temp_meas_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__bypass_bg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__vref_sel_fastreg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__chop_en__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__NC74__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__bypass_bg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__vref_sel_fastreg_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__chop_en_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__NC74_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_CONFIG
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT__STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT__STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK 0x0C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x7E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x1F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x1F00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_ERR
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_LD_VAL_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_DATA_MSK
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK 0x7FFEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x1FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_SEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__data_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__data_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vph__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vptx__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vp__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vph_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vptx_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vp_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_gd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vdccm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vdccp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vptx__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__override_regref_0__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vreg0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vreg1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vreg_s__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_gd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vdccm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vdccp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vptx_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__override_regref_0_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vreg0_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vreg1_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vreg_s_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_vcm__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txsm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txsp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txfm__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txfp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_rxdetref__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_nbias__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_pbias__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_vcm_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txsm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txsp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txfm_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txfp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_rxdetref_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_nbias_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_pbias_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__atb_s_enable__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__atb_vboost_vref__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__atb_vboost__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__vboost_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__meas_atb_vph_half_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__atb_s_enable_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__override_vref_boost_ref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__atb_vboost_vref_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__atb_vboost_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__vboost_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__ovrd_vboost_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__iboost_code__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__iboost_code_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__override_regref_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__override_regref_1_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__nc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__osc_pmos__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__osc_nmos__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__override_rxdetref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__nc_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__osc_pmos_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__osc_nmos_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__meas_atb_bias_vptx_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__override_rxdetref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__data_rate_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__los_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__override_regref_slc_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__override_regref_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__meas_atb_rx_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_even_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__NC10__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__NC10_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__NC32__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__NC32_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__shor_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__NC0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__NC0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK 0x007EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__NC20__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__NC20_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__rx_term_gd_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__rx_term_dc_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x7E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x1F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x1F00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_ERR
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_LD_VAL_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_DATA_MSK
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK 0x7FFEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x1FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__data_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__data_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vph__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vptx__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vp__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vph_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vptx_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vp_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_gd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vdccm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vdccp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vptx__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__override_regref_0__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vreg0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vreg1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vreg_s__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_gd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vdccm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vdccp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vptx_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__override_regref_0_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vreg0_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vreg1_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vreg_s_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_vcm__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txsm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txsp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txfm__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txfp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_rxdetref__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_nbias__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_pbias__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_vcm_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txsm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txsp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txfm_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txfp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_rxdetref_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_nbias_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_pbias_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__atb_s_enable__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__atb_vboost_vref__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__atb_vboost__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__vboost_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__meas_atb_vph_half_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__atb_s_enable_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__override_vref_boost_ref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__atb_vboost_vref_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__atb_vboost_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__vboost_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__ovrd_vboost_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__iboost_code__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__iboost_code_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__override_regref_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__override_regref_1_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__nc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__osc_pmos__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__osc_nmos__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__override_rxdetref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__nc_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__osc_pmos_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__osc_nmos_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__meas_atb_bias_vptx_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__override_rxdetref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__data_rate_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__los_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__override_regref_slc_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__override_regref_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__meas_atb_rx_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_even_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__NC10__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__NC10_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__NC32__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__NC32_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__shor_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__NC0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__NC0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK 0x007EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__NC20__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__NC20_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__rx_term_gd_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__rx_term_dc_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x7E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x1F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x1F00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_ERR
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_LD_VAL_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_DATA_MSK
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK 0x7FFEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x1FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__data_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__data_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vph__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vptx__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vp__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vph_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vptx_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vp_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_gd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vdccm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vdccp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vptx__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__override_regref_0__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vreg0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vreg1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vreg_s__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_gd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vdccm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vdccp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vptx_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__override_regref_0_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vreg0_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vreg1_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vreg_s_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_vcm__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txsm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txsp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txfm__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txfp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_rxdetref__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_nbias__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_pbias__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_vcm_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txsm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txsp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txfm_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txfp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_rxdetref_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_nbias_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_pbias_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__atb_s_enable__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__atb_vboost_vref__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__atb_vboost__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__vboost_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__meas_atb_vph_half_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__atb_s_enable_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__override_vref_boost_ref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__atb_vboost_vref_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__atb_vboost_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__vboost_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__ovrd_vboost_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__iboost_code__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__iboost_code_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__override_regref_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__override_regref_1_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__nc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__osc_pmos__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__osc_nmos__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__override_rxdetref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__nc_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__osc_pmos_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__osc_nmos_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__meas_atb_bias_vptx_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__override_rxdetref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__data_rate_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__los_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__override_regref_slc_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__override_regref_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__meas_atb_rx_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_even_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__NC10__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__NC10_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__NC32__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__NC32_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__shor_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__NC0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__NC0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK 0x007EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__NC20__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__NC20_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__rx_term_gd_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__rx_term_dc_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x7E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x1F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x1F00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_ERR
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_LD_VAL_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_DATA_MSK
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK 0x7FFEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x1FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_SEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__data_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__data_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vph__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vptx__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vp__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vph_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vptx_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vp_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_gd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vdccm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vdccp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vptx__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__override_regref_0__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vreg0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vreg1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vreg_s__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_gd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vdccm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vdccp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vptx_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__override_regref_0_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vreg0_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vreg1_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vreg_s_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_vcm__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txsm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txsp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txfm__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txfp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_rxdetref__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_nbias__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_pbias__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_vcm_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txsm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txsp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txfm_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txfp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_rxdetref_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_nbias_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_pbias_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__atb_s_enable__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__atb_vboost_vref__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__atb_vboost__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__vboost_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__meas_atb_vph_half_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__atb_s_enable_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__override_vref_boost_ref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__atb_vboost_vref_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__atb_vboost_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__vboost_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__ovrd_vboost_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__iboost_code__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__iboost_code_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__override_regref_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__override_regref_1_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__nc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__osc_pmos__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__osc_nmos__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__override_rxdetref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__nc_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__osc_pmos_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__osc_nmos_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__meas_atb_bias_vptx_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__override_rxdetref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__data_rate_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__los_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__override_regref_slc_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__override_regref_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__meas_atb_rx_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_even_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__NC10__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__NC10_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__NC32__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__NC32_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__shor_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__NC0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__NC0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK 0x007EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__NC20__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__NC20_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__rx_term_gd_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__rx_term_dc_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_CMN_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK 0x0FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK 0x0FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x0380L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x03F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_SUP
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_LIN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_MAP
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_RX_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_INIT_PWRUP_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_ATT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADAPT_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x0380L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x03F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_SUP
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_LIN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_MAP
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_RX_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_INIT_PWRUP_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_ATT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADAPT_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x0380L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x03F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_SUP
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_LIN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_MAP
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_RX_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_INIT_PWRUP_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_ATT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADAPT_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x0380L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x03F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_SUP
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_LIN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_MAP
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_RX_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_INIT_PWRUP_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_ATT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADAPT_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_IDCODE_LO
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_IDCODE_LO__data__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_IDCODE_LO__data_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_IDCODE_HI
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_IDCODE_HI__data__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_IDCODE_HI__data_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK 0x1FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK 0x1FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_REQ_IN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_REQ_OUT__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_ACK_IN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_ACK_OUT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__BG_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__PHY_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_REQ_IN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_REQ_OUT_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_ACK_IN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_ACK_OUT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__BG_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x3FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RX_TERM_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_STAT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_STAT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK 0x7F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK 0x1E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK 0x07FCL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK 0x7F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK 0x1E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK 0x07FCL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__NC40__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__lpn_vreg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__NC40_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__lpn_vreg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_right__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_left__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_vco_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_right_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_left_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_cp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__meas_vreg_l_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vreg_r_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_mag_ref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__force_fine_high__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__force_fine_low__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__override_amp_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__override_amp_high__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__override_amp_low__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__atb_select__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__force_fine_high_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__force_fine_low_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__override_amp_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__override_amp_high_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__override_amp_low_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__atb_select_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__NC40__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__lpn_vreg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__NC40_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__lpn_vreg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_right__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_left__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_vco_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_right_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_left_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_cp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__meas_vreg_l_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vreg_r_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_mag_ref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__force_fine_high__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__force_fine_low__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__override_amp_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__override_amp_high__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__override_amp_low__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__atb_select__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__force_fine_high_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__force_fine_low_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__override_amp_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__override_amp_high_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__override_amp_low_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__atb_select_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__NC7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__NC7_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK 0x001CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__bypass_bg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__vref_sel_fastreg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__chop_en__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__NC74__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__bypass_bg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__vref_sel_fastreg_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__chop_en_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__NC74_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_CONFIG
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT__STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT__STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK 0x0C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x7E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x1F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x1F00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_ERR
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_LD_VAL_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_DATA_MSK
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK 0x7FFEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x1FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__data_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__data_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vph__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vptx__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vp__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vph_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vptx_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vp_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_gd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vdccm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vdccp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vptx__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__override_regref_0__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vreg0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vreg1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vreg_s__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_gd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vdccm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vdccp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vptx_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__override_regref_0_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vreg0_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vreg1_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vreg_s_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_vcm__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txsm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txsp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txfm__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txfp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_rxdetref__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_nbias__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_pbias__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_vcm_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txsm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txsp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txfm_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txfp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_rxdetref_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_nbias_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_pbias_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__atb_s_enable__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__atb_vboost_vref__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__atb_vboost__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__vboost_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__meas_atb_vph_half_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__atb_s_enable_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__override_vref_boost_ref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__atb_vboost_vref_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__atb_vboost_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__vboost_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__ovrd_vboost_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__iboost_code__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__iboost_code_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__override_regref_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__override_regref_1_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__nc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__osc_pmos__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__osc_nmos__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__override_rxdetref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__nc_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__osc_pmos_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__osc_nmos_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__meas_atb_bias_vptx_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__override_rxdetref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__data_rate_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__los_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__override_regref_slc_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__override_regref_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__meas_atb_rx_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_even_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__NC10__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__NC10_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__NC32__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__NC32_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__shor_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__NC0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__NC0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK 0x007EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__NC20__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__NC20_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__rx_term_gd_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__rx_term_dc_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_CMN_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK 0x0FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK 0x0FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x0380L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x03F0L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_SUP
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_LIN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_MAP
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_RX_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_INIT_PWRUP_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_ATT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADAPT_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+
+
+// addressBlock: nbio_lcu_kpfifo_kpfifo1_kpfifo_dir
+//KPFIFO1_PRI_TX_FIFO_HSCID
+#define KPFIFO1_PRI_TX_FIFO_HSCID__HwRev__SHIFT 0x0
+#define KPFIFO1_PRI_TX_FIFO_HSCID__HwMinVer__SHIFT 0x6
+#define KPFIFO1_PRI_TX_FIFO_HSCID__HwMajVer__SHIFT 0xd
+#define KPFIFO1_PRI_TX_FIFO_HSCID__HwRev_MASK 0x0000003FL
+#define KPFIFO1_PRI_TX_FIFO_HSCID__HwMinVer_MASK 0x00001FC0L
+#define KPFIFO1_PRI_TX_FIFO_HSCID__HwMajVer_MASK 0x000FE000L
+//KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__LinkID__SHIFT 0x0
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__FIFORdPtrOffset__SHIFT 0x8
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__FIFODepth__SHIFT 0x10
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__FIFOBypass__SHIFT 0x18
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__FIFOInitMode__SHIFT 0x19
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__Standalone__SHIFT 0x1a
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug0__SHIFT 0x1b
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug1__SHIFT 0x1c
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug2__SHIFT 0x1d
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug3__SHIFT 0x1e
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug4__SHIFT 0x1f
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__LinkID_MASK 0x000000FFL
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__FIFORdPtrOffset_MASK 0x0000FF00L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__FIFODepth_MASK 0x00FF0000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__FIFOBypass_MASK 0x01000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__FIFOInitMode_MASK 0x02000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__Standalone_MASK 0x04000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug0_MASK 0x08000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug1_MASK 0x10000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug2_MASK 0x20000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug3_MASK 0x40000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug4_MASK 0x80000000L
+//KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__LinkID__SHIFT 0x0
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__FIFORdPtrOffset__SHIFT 0x8
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__FIFODepth__SHIFT 0x10
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__FIFOBypass__SHIFT 0x18
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__FIFOInitMode__SHIFT 0x19
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__Standalone__SHIFT 0x1a
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug0__SHIFT 0x1b
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug1__SHIFT 0x1c
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug2__SHIFT 0x1d
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug3__SHIFT 0x1e
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug4__SHIFT 0x1f
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__LinkID_MASK 0x000000FFL
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__FIFORdPtrOffset_MASK 0x0000FF00L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__FIFODepth_MASK 0x00FF0000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__FIFOBypass_MASK 0x01000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__FIFOInitMode_MASK 0x02000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__Standalone_MASK 0x04000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug0_MASK 0x08000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug1_MASK 0x10000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug2_MASK 0x20000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug3_MASK 0x40000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug4_MASK 0x80000000L
+//KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__LinkID__SHIFT 0x0
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__FIFORdPtrOffset__SHIFT 0x8
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__FIFODepth__SHIFT 0x10
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__FIFOBypass__SHIFT 0x18
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__FIFOInitMode__SHIFT 0x19
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__Standalone__SHIFT 0x1a
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug0__SHIFT 0x1b
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug1__SHIFT 0x1c
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug2__SHIFT 0x1d
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug3__SHIFT 0x1e
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug4__SHIFT 0x1f
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__LinkID_MASK 0x000000FFL
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__FIFORdPtrOffset_MASK 0x0000FF00L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__FIFODepth_MASK 0x00FF0000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__FIFOBypass_MASK 0x01000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__FIFOInitMode_MASK 0x02000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__Standalone_MASK 0x04000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug0_MASK 0x08000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug1_MASK 0x10000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug2_MASK 0x20000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug3_MASK 0x40000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug4_MASK 0x80000000L
+//KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__LinkID__SHIFT 0x0
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__FIFORdPtrOffset__SHIFT 0x8
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__FIFODepth__SHIFT 0x10
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__FIFOBypass__SHIFT 0x18
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__FIFOInitMode__SHIFT 0x19
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__Standalone__SHIFT 0x1a
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug0__SHIFT 0x1b
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug1__SHIFT 0x1c
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug2__SHIFT 0x1d
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug3__SHIFT 0x1e
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug4__SHIFT 0x1f
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__LinkID_MASK 0x000000FFL
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__FIFORdPtrOffset_MASK 0x0000FF00L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__FIFODepth_MASK 0x00FF0000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__FIFOBypass_MASK 0x01000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__FIFOInitMode_MASK 0x02000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__Standalone_MASK 0x04000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug0_MASK 0x08000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug1_MASK 0x10000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug2_MASK 0x20000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug3_MASK 0x40000000L
+#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug4_MASK 0x80000000L
+//KPFIFO1_PCS_PMA_SOFT_RESET
+#define KPFIFO1_PCS_PMA_SOFT_RESET__KPFIFO_PHY_soft_ResetPhy__SHIFT 0x0
+#define KPFIFO1_PCS_PMA_SOFT_RESET__KPFIFO_PHY_soft_ResetPhy_MASK 0x00000001L
+
+
+// addressBlock: nbio_lcu_kpnp_kpnp1_kpnp_dir
+//KPNP_SNPS1_KPNP_HWSCVER
+#define KPNP_SNPS1_KPNP_HWSCVER__hw_revision__SHIFT 0x0
+#define KPNP_SNPS1_KPNP_HWSCVER__hw_minor_version_number__SHIFT 0x6
+#define KPNP_SNPS1_KPNP_HWSCVER__hw_major_version_number__SHIFT 0xd
+#define KPNP_SNPS1_KPNP_HWSCVER__hw_revision_MASK 0x0000003FL
+#define KPNP_SNPS1_KPNP_HWSCVER__hw_minor_version_number_MASK 0x00001FC0L
+#define KPNP_SNPS1_KPNP_HWSCVER__hw_major_version_number_MASK 0x000FE000L
+//KPNP_SNPS1_KPNP_PHY_INFO
+#define KPNP_SNPS1_KPNP_PHY_INFO__HwRev__SHIFT 0x0
+#define KPNP_SNPS1_KPNP_PHY_INFO__PHYVer__SHIFT 0x6
+#define KPNP_SNPS1_KPNP_PHY_INFO__Technology__SHIFT 0xd
+#define KPNP_SNPS1_KPNP_PHY_INFO__Type__SHIFT 0x14
+#define KPNP_SNPS1_KPNP_PHY_INFO__VendorID__SHIFT 0x1a
+#define KPNP_SNPS1_KPNP_PHY_INFO__HwRev_MASK 0x0000003FL
+#define KPNP_SNPS1_KPNP_PHY_INFO__PHYVer_MASK 0x00001FC0L
+#define KPNP_SNPS1_KPNP_PHY_INFO__Technology_MASK 0x000FE000L
+#define KPNP_SNPS1_KPNP_PHY_INFO__Type_MASK 0x03F00000L
+#define KPNP_SNPS1_KPNP_PHY_INFO__VendorID_MASK 0xFC000000L
+//KPNP_SNPS1_KPNP_LANE_ID
+#define KPNP_SNPS1_KPNP_LANE_ID__NodeStartLane__SHIFT 0x0
+#define KPNP_SNPS1_KPNP_LANE_ID__NodeEndLane__SHIFT 0x8
+#define KPNP_SNPS1_KPNP_LANE_ID__NodeStartLane_MASK 0x000000FFL
+#define KPNP_SNPS1_KPNP_LANE_ID__NodeEndLane_MASK 0x0000FF00L
+//KPNP_SNPS1_KPNP_LANE_REQ_CONTROL
+#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln0TxReq__SHIFT 0x0
+#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln0RxReq__SHIFT 0x1
+#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln1TxReq__SHIFT 0x2
+#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln1RxReq__SHIFT 0x3
+#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln2TxReq__SHIFT 0x4
+#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln2RxReq__SHIFT 0x5
+#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln3TxReq__SHIFT 0x6
+#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln3RxReq__SHIFT 0x7
+#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln0TxReq_MASK 0x00000001L
+#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln0RxReq_MASK 0x00000002L
+#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln1TxReq_MASK 0x00000004L
+#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln1RxReq_MASK 0x00000008L
+#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln2TxReq_MASK 0x00000010L
+#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln2RxReq_MASK 0x00000020L
+#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln3TxReq_MASK 0x00000040L
+#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln3RxReq_MASK 0x00000080L
+//KPNP_SNPS1_KPNP_LANE_REQ_STATUS
+#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln0TxAck__SHIFT 0x0
+#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln0RxAck__SHIFT 0x1
+#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln1TxAck__SHIFT 0x2
+#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln1RxAck__SHIFT 0x3
+#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln2TxAck__SHIFT 0x4
+#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln2RxAck__SHIFT 0x5
+#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln3TxAck__SHIFT 0x6
+#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln3RxAck__SHIFT 0x7
+#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln0TxAck_MASK 0x00000001L
+#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln0RxAck_MASK 0x00000002L
+#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln1TxAck_MASK 0x00000004L
+#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln1RxAck_MASK 0x00000008L
+#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln2TxAck_MASK 0x00000010L
+#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln2RxAck_MASK 0x00000020L
+#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln3TxAck_MASK 0x00000040L
+#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln3RxAck_MASK 0x00000080L
+//KPNP_SNPS1_KPNP_PMA_CONTROL0
+#define KPNP_SNPS1_KPNP_PMA_CONTROL0__ref_use_pad__SHIFT 0x0
+#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln0_Tx_Disable__SHIFT 0x10
+#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln0_Rx_Disable__SHIFT 0x11
+#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln1_Tx_Disable__SHIFT 0x12
+#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln1_Rx_Disable__SHIFT 0x13
+#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln2_Tx_Disable__SHIFT 0x14
+#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln2_Rx_Disable__SHIFT 0x15
+#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln3_Tx_Disable__SHIFT 0x16
+#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln3_Rx_Disable__SHIFT 0x17
+#define KPNP_SNPS1_KPNP_PMA_CONTROL0__ref_use_pad_MASK 0x00000001L
+#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln0_Tx_Disable_MASK 0x00010000L
+#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln0_Rx_Disable_MASK 0x00020000L
+#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln1_Tx_Disable_MASK 0x00040000L
+#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln1_Rx_Disable_MASK 0x00080000L
+#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln2_Tx_Disable_MASK 0x00100000L
+#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln2_Rx_Disable_MASK 0x00200000L
+#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln3_Tx_Disable_MASK 0x00400000L
+#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln3_Rx_Disable_MASK 0x00800000L
+//KPNP_SNPS1_KPNP_PMA_CONTROL1
+#define KPNP_SNPS1_KPNP_PMA_CONTROL1__rx_vref_ctrl__SHIFT 0x0
+#define KPNP_SNPS1_KPNP_PMA_CONTROL1__tx_vboost_lvl__SHIFT 0x5
+#define KPNP_SNPS1_KPNP_PMA_CONTROL1__rx_vref_ctrl_MASK 0x0000001FL
+#define KPNP_SNPS1_KPNP_PMA_CONTROL1__tx_vboost_lvl_MASK 0x000000E0L
+//KPNP_SNPS1_KPNP_PMA_CONTROL2
+#define KPNP_SNPS1_KPNP_PMA_CONTROL2__Staggering_Disable__SHIFT 0x0
+#define KPNP_SNPS1_KPNP_PMA_CONTROL2__Staggering_Mode__SHIFT 0x1
+#define KPNP_SNPS1_KPNP_PMA_CONTROL2__Staggering_Time_Resolution__SHIFT 0x2
+#define KPNP_SNPS1_KPNP_PMA_CONTROL2__Staggering_Disable_MASK 0x00000001L
+#define KPNP_SNPS1_KPNP_PMA_CONTROL2__Staggering_Mode_MASK 0x00000002L
+#define KPNP_SNPS1_KPNP_PMA_CONTROL2__Staggering_Time_Resolution_MASK 0x0000001CL
+//KPNP_SNPS1_KPNP_PHY_SOFT_RESET
+#define KPNP_SNPS1_KPNP_PHY_SOFT_RESET__Phy_Soft_Reset__SHIFT 0x0
+#define KPNP_SNPS1_KPNP_PHY_SOFT_RESET__Phy_Soft_Reset_MASK 0x00000001L
+//KPNP_SNPS1_KPNP_LANE_SOFT_RESET
+#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln0_Tx_Soft_Reset__SHIFT 0x0
+#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln0_Rx_Soft_Reset__SHIFT 0x1
+#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln1_Tx_Soft_Reset__SHIFT 0x2
+#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln1_Rx_Soft_Reset__SHIFT 0x3
+#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln2_Tx_Soft_Reset__SHIFT 0x4
+#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln2_Rx_Soft_Reset__SHIFT 0x5
+#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln3_Tx_Soft_Reset__SHIFT 0x6
+#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln3_Rx_Soft_Reset__SHIFT 0x7
+#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln0_Tx_Soft_Reset_MASK 0x00000001L
+#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln0_Rx_Soft_Reset_MASK 0x00000002L
+#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln1_Tx_Soft_Reset_MASK 0x00000004L
+#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln1_Rx_Soft_Reset_MASK 0x00000008L
+#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln2_Tx_Soft_Reset_MASK 0x00000010L
+#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln2_Rx_Soft_Reset_MASK 0x00000020L
+#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln3_Tx_Soft_Reset_MASK 0x00000040L
+#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln3_Rx_Soft_Reset_MASK 0x00000080L
+//KPNP_SNPS1_REG_RST_CTRL
+#define KPNP_SNPS1_REG_RST_CTRL__reset_regs_when_dxio_phy_rst__SHIFT 0x0
+#define KPNP_SNPS1_REG_RST_CTRL__reset_regs_when_dxio_phy_rst_MASK 0x00000001L
+
+
+// addressBlock: nbio_pipe_pcs_dwc_e12mp_phy_x4_ns2_dwc_e12mp_phy_x4_ns_UP16_dwc_e12mp_phy_x4_ns_UP16_mem_map
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_IDCODE_LO
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_IDCODE_LO__data__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_IDCODE_LO__data_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_IDCODE_HI
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_IDCODE_HI__data__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_IDCODE_HI__data_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK 0x1FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK 0x1FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_REQ_IN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_REQ_OUT__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_ACK_IN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_ACK_OUT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__BG_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__PHY_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_REQ_IN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_REQ_OUT_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_ACK_IN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_ACK_OUT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__BG_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x3FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RX_TERM_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_STAT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_STAT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK 0x7F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK 0x1E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK 0x07FCL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK 0x7F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK 0x1E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK 0x07FCL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__NC40__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__lpn_vreg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__NC40_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__lpn_vreg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__enable_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__cal_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__reset_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_right__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_left__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_vco_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_right_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_left_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_cp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__meas_vreg_vco_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__meas_vreg_l_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vreg_r_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vreg_vp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vreg_cp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_ctl_fine_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_mag_ref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__force_fine_high__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__force_fine_low__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__override_amp_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__override_amp_high__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__override_amp_low__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__atb_select__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__force_fine_high_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__force_fine_low_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__override_amp_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__override_amp_high_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__override_amp_low_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__atb_select_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__NC40__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__lpn_vreg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__NC40_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__lpn_vreg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__enable_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__cal_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__reset_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_right__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_left__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_vco_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_right_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_left_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_cp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__meas_vreg_vco_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__meas_vreg_l_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vreg_r_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vreg_vp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vreg_cp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_ctl_fine_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_mag_ref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__force_fine_high__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__force_fine_low__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__override_amp_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__override_amp_high__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__override_amp_low__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__atb_select__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__force_fine_high_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__force_fine_low_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__override_amp_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__override_amp_high_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__override_amp_low_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__atb_select_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__NC7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__NC7_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK 0x001CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__temp_meas_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__bypass_bg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__vref_sel_fastreg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__chop_en__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__NC74__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__bypass_bg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__vref_sel_fastreg_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__chop_en_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__NC74_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_CONFIG
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT__STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT__STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK 0x0C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x7E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x1F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x1F00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_ERR
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_LD_VAL_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_DATA_MSK
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK 0x7FFEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x1FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_SEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__data_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__data_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vph__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vptx__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vp__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vph_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vptx_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vp_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_gd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vdccm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vdccp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vptx__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__override_regref_0__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vreg0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vreg1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vreg_s__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_gd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vdccm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vdccp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vptx_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__override_regref_0_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vreg0_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vreg1_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vreg_s_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_vcm__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txsm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txsp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txfm__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txfp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_rxdetref__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_nbias__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_pbias__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_vcm_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txsm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txsp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txfm_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txfp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_rxdetref_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_nbias_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_pbias_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__atb_s_enable__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__atb_vboost_vref__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__atb_vboost__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__vboost_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__meas_atb_vph_half_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__atb_s_enable_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__override_vref_boost_ref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__atb_vboost_vref_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__atb_vboost_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__vboost_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__ovrd_vboost_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__iboost_code__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__iboost_code_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__override_regref_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__override_regref_1_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__nc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__osc_pmos__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__osc_nmos__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__override_rxdetref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__nc_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__osc_pmos_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__osc_nmos_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__meas_atb_bias_vptx_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__override_rxdetref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__data_rate_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__los_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__override_regref_slc_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__override_regref_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__meas_atb_rx_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_even_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__NC10__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__NC10_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__NC32__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__NC32_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__shor_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__NC0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__NC0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK 0x007EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__NC20__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__NC20_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__rx_term_gd_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__rx_term_dc_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x7E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x1F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x1F00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_ERR
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_LD_VAL_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_DATA_MSK
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK 0x7FFEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x1FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__data_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__data_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vph__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vptx__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vp__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vph_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vptx_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vp_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_gd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vdccm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vdccp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vptx__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__override_regref_0__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vreg0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vreg1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vreg_s__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_gd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vdccm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vdccp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vptx_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__override_regref_0_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vreg0_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vreg1_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vreg_s_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_vcm__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txsm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txsp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txfm__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txfp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_rxdetref__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_nbias__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_pbias__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_vcm_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txsm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txsp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txfm_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txfp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_rxdetref_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_nbias_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_pbias_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__atb_s_enable__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__atb_vboost_vref__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__atb_vboost__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__vboost_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__meas_atb_vph_half_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__atb_s_enable_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__override_vref_boost_ref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__atb_vboost_vref_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__atb_vboost_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__vboost_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__ovrd_vboost_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__iboost_code__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__iboost_code_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__override_regref_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__override_regref_1_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__nc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__osc_pmos__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__osc_nmos__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__override_rxdetref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__nc_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__osc_pmos_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__osc_nmos_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__meas_atb_bias_vptx_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__override_rxdetref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__data_rate_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__los_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__override_regref_slc_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__override_regref_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__meas_atb_rx_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_even_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__NC10__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__NC10_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__NC32__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__NC32_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__shor_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__NC0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__NC0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK 0x007EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__NC20__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__NC20_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__rx_term_gd_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__rx_term_dc_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x7E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x1F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x1F00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_ERR
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_LD_VAL_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_DATA_MSK
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK 0x7FFEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x1FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__data_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__data_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vph__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vptx__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vp__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vph_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vptx_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vp_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_gd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vdccm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vdccp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vptx__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__override_regref_0__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vreg0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vreg1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vreg_s__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_gd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vdccm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vdccp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vptx_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__override_regref_0_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vreg0_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vreg1_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vreg_s_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_vcm__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txsm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txsp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txfm__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txfp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_rxdetref__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_nbias__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_pbias__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_vcm_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txsm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txsp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txfm_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txfp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_rxdetref_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_nbias_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_pbias_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__atb_s_enable__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__atb_vboost_vref__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__atb_vboost__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__vboost_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__meas_atb_vph_half_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__atb_s_enable_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__override_vref_boost_ref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__atb_vboost_vref_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__atb_vboost_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__vboost_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__ovrd_vboost_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__iboost_code__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__iboost_code_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__override_regref_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__override_regref_1_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__nc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__osc_pmos__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__osc_nmos__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__override_rxdetref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__nc_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__osc_pmos_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__osc_nmos_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__meas_atb_bias_vptx_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__override_rxdetref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__data_rate_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__los_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__override_regref_slc_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__override_regref_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__meas_atb_rx_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_even_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__NC10__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__NC10_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__NC32__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__NC32_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__shor_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__NC0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__NC0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK 0x007EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__NC20__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__NC20_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__rx_term_gd_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__rx_term_dc_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x7E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x1F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x1F00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_ERR
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_LD_VAL_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_DATA_MSK
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK 0x7FFEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x1FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_SEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__data_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__data_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vph__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vptx__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vp__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vph_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vptx_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vp_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_gd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vdccm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vdccp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vptx__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__override_regref_0__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vreg0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vreg1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vreg_s__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_gd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vdccm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vdccp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vptx_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__override_regref_0_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vreg0_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vreg1_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vreg_s_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_vcm__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txsm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txsp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txfm__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txfp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_rxdetref__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_nbias__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_pbias__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_vcm_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txsm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txsp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txfm_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txfp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_rxdetref_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_nbias_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_pbias_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__atb_s_enable__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__atb_vboost_vref__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__atb_vboost__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__vboost_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__meas_atb_vph_half_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__atb_s_enable_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__override_vref_boost_ref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__atb_vboost_vref_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__atb_vboost_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__vboost_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__ovrd_vboost_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__iboost_code__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__iboost_code_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__override_regref_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__override_regref_1_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__nc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__osc_pmos__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__osc_nmos__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__override_rxdetref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__nc_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__osc_pmos_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__osc_nmos_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__meas_atb_bias_vptx_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__override_rxdetref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__data_rate_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__los_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__override_regref_slc_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__override_regref_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__meas_atb_rx_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_even_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__NC10__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__NC10_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__NC32__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__NC32_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__shor_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__NC0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__NC0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK 0x007EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__NC20__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__NC20_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__rx_term_gd_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__rx_term_dc_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_CMN_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK 0x0FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK 0x0FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x0380L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x03F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_SUP
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_LIN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_MAP
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_RX_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_INIT_PWRUP_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_ATT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADAPT_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x0380L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x03F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_SUP
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_LIN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_MAP
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_RX_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_INIT_PWRUP_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_ATT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADAPT_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x0380L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x03F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_SUP
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_LIN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_MAP
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_RX_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_INIT_PWRUP_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_ATT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADAPT_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x0380L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x03F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_SUP
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_LIN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_MAP
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_RX_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_INIT_PWRUP_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_ATT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADAPT_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_IDCODE_LO
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_IDCODE_LO__data__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_IDCODE_LO__data_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_IDCODE_HI
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_IDCODE_HI__data__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_IDCODE_HI__data_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK 0x1FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK 0x1FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_REQ_IN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_REQ_OUT__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_ACK_IN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_ACK_OUT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__BG_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__PHY_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_REQ_IN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_REQ_OUT_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_ACK_IN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_ACK_OUT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__BG_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x3FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RX_TERM_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_STAT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_STAT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK 0x7F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK 0x1E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK 0x07FCL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK 0x7F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK 0x1E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK 0x07FCL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__NC40__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__lpn_vreg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__NC40_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__lpn_vreg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_right__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_left__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_vco_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_right_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_left_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_cp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__meas_vreg_l_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vreg_r_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_mag_ref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__force_fine_high__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__force_fine_low__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__override_amp_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__override_amp_high__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__override_amp_low__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__atb_select__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__force_fine_high_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__force_fine_low_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__override_amp_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__override_amp_high_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__override_amp_low_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__atb_select_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__NC40__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__lpn_vreg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__NC40_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__lpn_vreg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_right__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_left__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_vco_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_right_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_left_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_cp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__meas_vreg_l_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vreg_r_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_mag_ref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__force_fine_high__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__force_fine_low__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__override_amp_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__override_amp_high__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__override_amp_low__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__atb_select__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__force_fine_high_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__force_fine_low_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__override_amp_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__override_amp_high_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__override_amp_low_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__atb_select_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__NC7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__NC7_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK 0x001CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__bypass_bg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__vref_sel_fastreg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__chop_en__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__NC74__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__bypass_bg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__vref_sel_fastreg_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__chop_en_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__NC74_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_CONFIG
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT__STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT__STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK 0x0C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x7E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x1F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x1F00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_ERR
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_LD_VAL_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_DATA_MSK
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK 0x7FFEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x1FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__data_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__data_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vph__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vptx__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vp__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vph_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vptx_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vp_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_gd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vdccm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vdccp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vptx__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__override_regref_0__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vreg0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vreg1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vreg_s__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_gd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vdccm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vdccp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vptx_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__override_regref_0_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vreg0_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vreg1_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vreg_s_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_vcm__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txsm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txsp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txfm__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txfp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_rxdetref__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_nbias__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_pbias__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_vcm_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txsm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txsp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txfm_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txfp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_rxdetref_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_nbias_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_pbias_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__atb_s_enable__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__atb_vboost_vref__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__atb_vboost__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__vboost_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__meas_atb_vph_half_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__atb_s_enable_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__override_vref_boost_ref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__atb_vboost_vref_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__atb_vboost_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__vboost_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__ovrd_vboost_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__iboost_code__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__iboost_code_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__override_regref_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__override_regref_1_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__nc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__osc_pmos__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__osc_nmos__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__override_rxdetref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__nc_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__osc_pmos_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__osc_nmos_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__meas_atb_bias_vptx_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__override_rxdetref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__data_rate_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__los_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__override_regref_slc_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__override_regref_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__meas_atb_rx_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_even_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__NC10__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__NC10_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__NC32__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__NC32_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__shor_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__NC0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__NC0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK 0x007EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__NC20__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__NC20_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__rx_term_gd_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__rx_term_dc_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_CMN_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK 0x0FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK 0x0FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x0380L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x03F0L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_SUP
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_LIN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_MAP
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_RX_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_INIT_PWRUP_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_ATT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADAPT_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+
+
+// addressBlock: nbio_lcu_kpfifo_kpfifo2_kpfifo_dir
+//KPFIFO2_PRI_TX_FIFO_HSCID
+#define KPFIFO2_PRI_TX_FIFO_HSCID__HwRev__SHIFT 0x0
+#define KPFIFO2_PRI_TX_FIFO_HSCID__HwMinVer__SHIFT 0x6
+#define KPFIFO2_PRI_TX_FIFO_HSCID__HwMajVer__SHIFT 0xd
+#define KPFIFO2_PRI_TX_FIFO_HSCID__HwRev_MASK 0x0000003FL
+#define KPFIFO2_PRI_TX_FIFO_HSCID__HwMinVer_MASK 0x00001FC0L
+#define KPFIFO2_PRI_TX_FIFO_HSCID__HwMajVer_MASK 0x000FE000L
+//KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__LinkID__SHIFT 0x0
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__FIFORdPtrOffset__SHIFT 0x8
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__FIFODepth__SHIFT 0x10
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__FIFOBypass__SHIFT 0x18
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__FIFOInitMode__SHIFT 0x19
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__Standalone__SHIFT 0x1a
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug0__SHIFT 0x1b
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug1__SHIFT 0x1c
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug2__SHIFT 0x1d
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug3__SHIFT 0x1e
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug4__SHIFT 0x1f
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__LinkID_MASK 0x000000FFL
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__FIFORdPtrOffset_MASK 0x0000FF00L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__FIFODepth_MASK 0x00FF0000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__FIFOBypass_MASK 0x01000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__FIFOInitMode_MASK 0x02000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__Standalone_MASK 0x04000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug0_MASK 0x08000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug1_MASK 0x10000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug2_MASK 0x20000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug3_MASK 0x40000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug4_MASK 0x80000000L
+//KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__LinkID__SHIFT 0x0
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__FIFORdPtrOffset__SHIFT 0x8
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__FIFODepth__SHIFT 0x10
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__FIFOBypass__SHIFT 0x18
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__FIFOInitMode__SHIFT 0x19
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__Standalone__SHIFT 0x1a
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug0__SHIFT 0x1b
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug1__SHIFT 0x1c
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug2__SHIFT 0x1d
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug3__SHIFT 0x1e
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug4__SHIFT 0x1f
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__LinkID_MASK 0x000000FFL
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__FIFORdPtrOffset_MASK 0x0000FF00L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__FIFODepth_MASK 0x00FF0000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__FIFOBypass_MASK 0x01000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__FIFOInitMode_MASK 0x02000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__Standalone_MASK 0x04000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug0_MASK 0x08000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug1_MASK 0x10000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug2_MASK 0x20000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug3_MASK 0x40000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug4_MASK 0x80000000L
+//KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__LinkID__SHIFT 0x0
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__FIFORdPtrOffset__SHIFT 0x8
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__FIFODepth__SHIFT 0x10
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__FIFOBypass__SHIFT 0x18
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__FIFOInitMode__SHIFT 0x19
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__Standalone__SHIFT 0x1a
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug0__SHIFT 0x1b
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug1__SHIFT 0x1c
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug2__SHIFT 0x1d
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug3__SHIFT 0x1e
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug4__SHIFT 0x1f
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__LinkID_MASK 0x000000FFL
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__FIFORdPtrOffset_MASK 0x0000FF00L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__FIFODepth_MASK 0x00FF0000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__FIFOBypass_MASK 0x01000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__FIFOInitMode_MASK 0x02000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__Standalone_MASK 0x04000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug0_MASK 0x08000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug1_MASK 0x10000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug2_MASK 0x20000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug3_MASK 0x40000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug4_MASK 0x80000000L
+//KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__LinkID__SHIFT 0x0
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__FIFORdPtrOffset__SHIFT 0x8
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__FIFODepth__SHIFT 0x10
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__FIFOBypass__SHIFT 0x18
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__FIFOInitMode__SHIFT 0x19
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__Standalone__SHIFT 0x1a
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug0__SHIFT 0x1b
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug1__SHIFT 0x1c
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug2__SHIFT 0x1d
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug3__SHIFT 0x1e
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug4__SHIFT 0x1f
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__LinkID_MASK 0x000000FFL
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__FIFORdPtrOffset_MASK 0x0000FF00L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__FIFODepth_MASK 0x00FF0000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__FIFOBypass_MASK 0x01000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__FIFOInitMode_MASK 0x02000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__Standalone_MASK 0x04000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug0_MASK 0x08000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug1_MASK 0x10000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug2_MASK 0x20000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug3_MASK 0x40000000L
+#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug4_MASK 0x80000000L
+//KPFIFO2_PCS_PMA_SOFT_RESET
+#define KPFIFO2_PCS_PMA_SOFT_RESET__KPFIFO_PHY_soft_ResetPhy__SHIFT 0x0
+#define KPFIFO2_PCS_PMA_SOFT_RESET__KPFIFO_PHY_soft_ResetPhy_MASK 0x00000001L
+
+
+// addressBlock: nbio_lcu_kpnp_kpnp2_kpnp_dir
+//KPNP_SNPS2_KPNP_HWSCVER
+#define KPNP_SNPS2_KPNP_HWSCVER__hw_revision__SHIFT 0x0
+#define KPNP_SNPS2_KPNP_HWSCVER__hw_minor_version_number__SHIFT 0x6
+#define KPNP_SNPS2_KPNP_HWSCVER__hw_major_version_number__SHIFT 0xd
+#define KPNP_SNPS2_KPNP_HWSCVER__hw_revision_MASK 0x0000003FL
+#define KPNP_SNPS2_KPNP_HWSCVER__hw_minor_version_number_MASK 0x00001FC0L
+#define KPNP_SNPS2_KPNP_HWSCVER__hw_major_version_number_MASK 0x000FE000L
+//KPNP_SNPS2_KPNP_PHY_INFO
+#define KPNP_SNPS2_KPNP_PHY_INFO__HwRev__SHIFT 0x0
+#define KPNP_SNPS2_KPNP_PHY_INFO__PHYVer__SHIFT 0x6
+#define KPNP_SNPS2_KPNP_PHY_INFO__Technology__SHIFT 0xd
+#define KPNP_SNPS2_KPNP_PHY_INFO__Type__SHIFT 0x14
+#define KPNP_SNPS2_KPNP_PHY_INFO__VendorID__SHIFT 0x1a
+#define KPNP_SNPS2_KPNP_PHY_INFO__HwRev_MASK 0x0000003FL
+#define KPNP_SNPS2_KPNP_PHY_INFO__PHYVer_MASK 0x00001FC0L
+#define KPNP_SNPS2_KPNP_PHY_INFO__Technology_MASK 0x000FE000L
+#define KPNP_SNPS2_KPNP_PHY_INFO__Type_MASK 0x03F00000L
+#define KPNP_SNPS2_KPNP_PHY_INFO__VendorID_MASK 0xFC000000L
+//KPNP_SNPS2_KPNP_LANE_ID
+#define KPNP_SNPS2_KPNP_LANE_ID__NodeStartLane__SHIFT 0x0
+#define KPNP_SNPS2_KPNP_LANE_ID__NodeEndLane__SHIFT 0x8
+#define KPNP_SNPS2_KPNP_LANE_ID__NodeStartLane_MASK 0x000000FFL
+#define KPNP_SNPS2_KPNP_LANE_ID__NodeEndLane_MASK 0x0000FF00L
+//KPNP_SNPS2_KPNP_LANE_REQ_CONTROL
+#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln0TxReq__SHIFT 0x0
+#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln0RxReq__SHIFT 0x1
+#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln1TxReq__SHIFT 0x2
+#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln1RxReq__SHIFT 0x3
+#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln2TxReq__SHIFT 0x4
+#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln2RxReq__SHIFT 0x5
+#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln3TxReq__SHIFT 0x6
+#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln3RxReq__SHIFT 0x7
+#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln0TxReq_MASK 0x00000001L
+#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln0RxReq_MASK 0x00000002L
+#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln1TxReq_MASK 0x00000004L
+#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln1RxReq_MASK 0x00000008L
+#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln2TxReq_MASK 0x00000010L
+#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln2RxReq_MASK 0x00000020L
+#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln3TxReq_MASK 0x00000040L
+#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln3RxReq_MASK 0x00000080L
+//KPNP_SNPS2_KPNP_LANE_REQ_STATUS
+#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln0TxAck__SHIFT 0x0
+#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln0RxAck__SHIFT 0x1
+#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln1TxAck__SHIFT 0x2
+#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln1RxAck__SHIFT 0x3
+#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln2TxAck__SHIFT 0x4
+#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln2RxAck__SHIFT 0x5
+#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln3TxAck__SHIFT 0x6
+#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln3RxAck__SHIFT 0x7
+#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln0TxAck_MASK 0x00000001L
+#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln0RxAck_MASK 0x00000002L
+#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln1TxAck_MASK 0x00000004L
+#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln1RxAck_MASK 0x00000008L
+#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln2TxAck_MASK 0x00000010L
+#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln2RxAck_MASK 0x00000020L
+#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln3TxAck_MASK 0x00000040L
+#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln3RxAck_MASK 0x00000080L
+//KPNP_SNPS2_KPNP_PMA_CONTROL0
+#define KPNP_SNPS2_KPNP_PMA_CONTROL0__ref_use_pad__SHIFT 0x0
+#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln0_Tx_Disable__SHIFT 0x10
+#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln0_Rx_Disable__SHIFT 0x11
+#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln1_Tx_Disable__SHIFT 0x12
+#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln1_Rx_Disable__SHIFT 0x13
+#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln2_Tx_Disable__SHIFT 0x14
+#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln2_Rx_Disable__SHIFT 0x15
+#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln3_Tx_Disable__SHIFT 0x16
+#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln3_Rx_Disable__SHIFT 0x17
+#define KPNP_SNPS2_KPNP_PMA_CONTROL0__ref_use_pad_MASK 0x00000001L
+#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln0_Tx_Disable_MASK 0x00010000L
+#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln0_Rx_Disable_MASK 0x00020000L
+#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln1_Tx_Disable_MASK 0x00040000L
+#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln1_Rx_Disable_MASK 0x00080000L
+#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln2_Tx_Disable_MASK 0x00100000L
+#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln2_Rx_Disable_MASK 0x00200000L
+#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln3_Tx_Disable_MASK 0x00400000L
+#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln3_Rx_Disable_MASK 0x00800000L
+//KPNP_SNPS2_KPNP_PMA_CONTROL1
+#define KPNP_SNPS2_KPNP_PMA_CONTROL1__rx_vref_ctrl__SHIFT 0x0
+#define KPNP_SNPS2_KPNP_PMA_CONTROL1__tx_vboost_lvl__SHIFT 0x5
+#define KPNP_SNPS2_KPNP_PMA_CONTROL1__rx_vref_ctrl_MASK 0x0000001FL
+#define KPNP_SNPS2_KPNP_PMA_CONTROL1__tx_vboost_lvl_MASK 0x000000E0L
+//KPNP_SNPS2_KPNP_PMA_CONTROL2
+#define KPNP_SNPS2_KPNP_PMA_CONTROL2__Staggering_Disable__SHIFT 0x0
+#define KPNP_SNPS2_KPNP_PMA_CONTROL2__Staggering_Mode__SHIFT 0x1
+#define KPNP_SNPS2_KPNP_PMA_CONTROL2__Staggering_Time_Resolution__SHIFT 0x2
+#define KPNP_SNPS2_KPNP_PMA_CONTROL2__Staggering_Disable_MASK 0x00000001L
+#define KPNP_SNPS2_KPNP_PMA_CONTROL2__Staggering_Mode_MASK 0x00000002L
+#define KPNP_SNPS2_KPNP_PMA_CONTROL2__Staggering_Time_Resolution_MASK 0x0000001CL
+//KPNP_SNPS2_KPNP_PHY_SOFT_RESET
+#define KPNP_SNPS2_KPNP_PHY_SOFT_RESET__Phy_Soft_Reset__SHIFT 0x0
+#define KPNP_SNPS2_KPNP_PHY_SOFT_RESET__Phy_Soft_Reset_MASK 0x00000001L
+//KPNP_SNPS2_KPNP_LANE_SOFT_RESET
+#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln0_Tx_Soft_Reset__SHIFT 0x0
+#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln0_Rx_Soft_Reset__SHIFT 0x1
+#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln1_Tx_Soft_Reset__SHIFT 0x2
+#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln1_Rx_Soft_Reset__SHIFT 0x3
+#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln2_Tx_Soft_Reset__SHIFT 0x4
+#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln2_Rx_Soft_Reset__SHIFT 0x5
+#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln3_Tx_Soft_Reset__SHIFT 0x6
+#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln3_Rx_Soft_Reset__SHIFT 0x7
+#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln0_Tx_Soft_Reset_MASK 0x00000001L
+#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln0_Rx_Soft_Reset_MASK 0x00000002L
+#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln1_Tx_Soft_Reset_MASK 0x00000004L
+#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln1_Rx_Soft_Reset_MASK 0x00000008L
+#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln2_Tx_Soft_Reset_MASK 0x00000010L
+#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln2_Rx_Soft_Reset_MASK 0x00000020L
+#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln3_Tx_Soft_Reset_MASK 0x00000040L
+#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln3_Rx_Soft_Reset_MASK 0x00000080L
+//KPNP_SNPS2_REG_RST_CTRL
+#define KPNP_SNPS2_REG_RST_CTRL__reset_regs_when_dxio_phy_rst__SHIFT 0x0
+#define KPNP_SNPS2_REG_RST_CTRL__reset_regs_when_dxio_phy_rst_MASK 0x00000001L
+
+
+// addressBlock: nbio_pipe_pcs_dwc_e12mp_phy_x4_ns3_dwc_e12mp_phy_x4_ns_UP16_dwc_e12mp_phy_x4_ns_UP16_mem_map
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_IDCODE_LO
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_IDCODE_LO__data__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_IDCODE_LO__data_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_IDCODE_HI
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_IDCODE_HI__data__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_IDCODE_HI__data_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK 0x1FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK 0x1FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_REQ_IN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_REQ_OUT__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_ACK_IN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_ACK_OUT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__BG_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__PHY_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_REQ_IN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_REQ_OUT_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_ACK_IN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_ACK_OUT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__BG_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x3FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RX_TERM_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_STAT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_STAT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK 0x7F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK 0x1E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK 0x07FCL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK 0x7F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK 0x1E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK 0x07FCL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__NC40__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__lpn_vreg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__NC40_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__lpn_vreg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__enable_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__cal_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__reset_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_right__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_left__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_vco_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_right_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_left_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_cp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__meas_vreg_vco_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__meas_vreg_l_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vreg_r_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vreg_vp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vreg_cp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_ctl_fine_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_mag_ref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__force_fine_high__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__force_fine_low__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__override_amp_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__override_amp_high__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__override_amp_low__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__atb_select__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__force_fine_high_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__force_fine_low_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__override_amp_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__override_amp_high_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__override_amp_low_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__atb_select_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__NC40__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__lpn_vreg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__NC40_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__lpn_vreg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__enable_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__cal_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__reset_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_right__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_left__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_vco_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_right_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_left_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_cp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__meas_vreg_vco_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__meas_vreg_l_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vreg_r_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vreg_vp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vreg_cp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_ctl_fine_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_mag_ref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__force_fine_high__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__force_fine_low__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__override_amp_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__override_amp_high__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__override_amp_low__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__atb_select__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__force_fine_high_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__force_fine_low_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__override_amp_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__override_amp_high_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__override_amp_low_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__atb_select_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__NC7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__NC7_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK 0x001CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__temp_meas_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__bypass_bg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__vref_sel_fastreg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__chop_en__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__NC74__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__bypass_bg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__vref_sel_fastreg_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__chop_en_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__NC74_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_CONFIG
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT__STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT__STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK 0x0C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x7E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x1F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x1F00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_ERR
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_LD_VAL_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_DATA_MSK
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK 0x7FFEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x1FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_SEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__data_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__data_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vph__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vptx__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vp__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vph_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vptx_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vp_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_gd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vdccm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vdccp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vptx__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__override_regref_0__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vreg0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vreg1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vreg_s__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_gd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vdccm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vdccp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vptx_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__override_regref_0_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vreg0_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vreg1_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vreg_s_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_vcm__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txsm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txsp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txfm__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txfp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_rxdetref__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_nbias__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_pbias__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_vcm_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txsm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txsp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txfm_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txfp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_rxdetref_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_nbias_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_pbias_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__atb_s_enable__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__atb_vboost_vref__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__atb_vboost__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__vboost_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__meas_atb_vph_half_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__atb_s_enable_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__override_vref_boost_ref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__atb_vboost_vref_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__atb_vboost_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__vboost_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__ovrd_vboost_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__iboost_code__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__iboost_code_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__override_regref_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__override_regref_1_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__nc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__osc_pmos__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__osc_nmos__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__override_rxdetref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__nc_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__osc_pmos_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__osc_nmos_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__meas_atb_bias_vptx_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__override_rxdetref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__data_rate_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__los_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__override_regref_slc_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__override_regref_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__meas_atb_rx_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_even_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__NC10__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__NC10_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__NC32__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__NC32_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__shor_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__NC0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__NC0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK 0x007EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__NC20__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__NC20_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__rx_term_gd_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__rx_term_dc_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x7E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x1F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x1F00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_ERR
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_LD_VAL_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_DATA_MSK
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK 0x7FFEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x1FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__data_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__data_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vph__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vptx__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vp__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vph_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vptx_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vp_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_gd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vdccm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vdccp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vptx__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__override_regref_0__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vreg0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vreg1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vreg_s__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_gd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vdccm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vdccp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vptx_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__override_regref_0_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vreg0_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vreg1_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vreg_s_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_vcm__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txsm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txsp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txfm__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txfp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_rxdetref__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_nbias__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_pbias__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_vcm_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txsm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txsp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txfm_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txfp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_rxdetref_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_nbias_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_pbias_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__atb_s_enable__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__atb_vboost_vref__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__atb_vboost__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__vboost_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__meas_atb_vph_half_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__atb_s_enable_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__override_vref_boost_ref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__atb_vboost_vref_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__atb_vboost_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__vboost_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__ovrd_vboost_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__iboost_code__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__iboost_code_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__override_regref_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__override_regref_1_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__nc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__osc_pmos__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__osc_nmos__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__override_rxdetref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__nc_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__osc_pmos_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__osc_nmos_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__meas_atb_bias_vptx_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__override_rxdetref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__data_rate_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__los_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__override_regref_slc_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__override_regref_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__meas_atb_rx_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_even_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__NC10__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__NC10_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__NC32__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__NC32_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__shor_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__NC0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__NC0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK 0x007EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__NC20__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__NC20_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__rx_term_gd_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__rx_term_dc_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x7E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x1F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x1F00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_ERR
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_LD_VAL_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_DATA_MSK
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK 0x7FFEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x1FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__data_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__data_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vph__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vptx__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vp__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vph_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vptx_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vp_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_gd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vdccm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vdccp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vptx__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__override_regref_0__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vreg0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vreg1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vreg_s__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_gd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vdccm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vdccp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vptx_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__override_regref_0_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vreg0_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vreg1_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vreg_s_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_vcm__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txsm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txsp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txfm__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txfp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_rxdetref__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_nbias__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_pbias__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_vcm_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txsm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txsp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txfm_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txfp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_rxdetref_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_nbias_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_pbias_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__atb_s_enable__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__atb_vboost_vref__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__atb_vboost__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__vboost_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__meas_atb_vph_half_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__atb_s_enable_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__override_vref_boost_ref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__atb_vboost_vref_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__atb_vboost_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__vboost_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__ovrd_vboost_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__iboost_code__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__iboost_code_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__override_regref_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__override_regref_1_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__nc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__osc_pmos__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__osc_nmos__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__override_rxdetref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__nc_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__osc_pmos_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__osc_nmos_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__meas_atb_bias_vptx_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__override_rxdetref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__data_rate_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__los_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__override_regref_slc_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__override_regref_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__meas_atb_rx_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_even_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__NC10__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__NC10_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__NC32__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__NC32_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__shor_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__NC0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__NC0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK 0x007EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__NC20__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__NC20_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__rx_term_gd_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__rx_term_dc_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x7E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x1F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x1F00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_ERR
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_LD_VAL_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_DATA_MSK
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK 0x7FFEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x1FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_SEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__data_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__data_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vph__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vptx__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vp__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vph_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vptx_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vp_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_gd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vdccm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vdccp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vptx__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__override_regref_0__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vreg0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vreg1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vreg_s__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_gd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vdccm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vdccp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vptx_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__override_regref_0_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vreg0_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vreg1_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vreg_s_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_vcm__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txsm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txsp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txfm__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txfp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_rxdetref__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_nbias__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_pbias__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_vcm_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txsm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txsp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txfm_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txfp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_rxdetref_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_nbias_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_pbias_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__atb_s_enable__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__atb_vboost_vref__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__atb_vboost__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__vboost_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__meas_atb_vph_half_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__atb_s_enable_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__override_vref_boost_ref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__atb_vboost_vref_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__atb_vboost_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__vboost_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__ovrd_vboost_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__iboost_code__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__iboost_code_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__override_regref_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__override_regref_1_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__nc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__osc_pmos__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__osc_nmos__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__override_rxdetref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__nc_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__osc_pmos_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__osc_nmos_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__meas_atb_bias_vptx_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__override_rxdetref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__data_rate_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__los_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__override_regref_slc_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__override_regref_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__meas_atb_rx_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_even_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__NC10__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__NC10_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__NC32__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__NC32_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__shor_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__NC0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__NC0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK 0x007EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__NC20__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__NC20_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__rx_term_gd_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__rx_term_dc_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_CMN_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK 0x0FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK 0x0FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x0380L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x03F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_SUP
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_LIN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_MAP
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_RX_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_INIT_PWRUP_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_ATT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADAPT_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x0380L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x03F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_SUP
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_LIN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_MAP
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_RX_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_INIT_PWRUP_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_ATT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADAPT_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x0380L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x03F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_SUP
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_LIN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_MAP
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_RX_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_INIT_PWRUP_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_ATT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADAPT_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x0380L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x03F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_SUP
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_LIN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_MAP
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_RX_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_INIT_PWRUP_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_ATT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADAPT_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_IDCODE_LO
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_IDCODE_LO__data__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_IDCODE_LO__data_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_IDCODE_HI
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_IDCODE_HI__data__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_IDCODE_HI__data_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK 0x1FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK 0x1FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK 0x000EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK 0x1FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_REQ_IN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_REQ_OUT__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_ACK_IN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_ACK_OUT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__BG_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__PHY_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_REQ_IN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_REQ_OUT_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_ACK_IN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_ACK_OUT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__BG_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK 0x3FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RX_TERM_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_STAT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_STAT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK 0x7F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK 0x1E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK 0x07FCL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK 0x7F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK 0x1E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK 0x07FCL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__NC40__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__lpn_vreg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__NC40_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__lpn_vreg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_right__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_left__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_vco_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_right_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_left_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_cp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__meas_vreg_l_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vreg_r_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_mag_ref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__force_fine_high__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__force_fine_low__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__override_amp_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__override_amp_high__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__override_amp_low__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__atb_select__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__force_fine_high_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__force_fine_low_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__override_amp_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__override_amp_high_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__override_amp_low_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__atb_select_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__NC40__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__lpn_vreg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__NC40_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__lpn_vreg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_right__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_left__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_vco_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_right_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_left_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_cp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__meas_vreg_l_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vreg_r_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_mag_ref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__force_fine_high__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__force_fine_low__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__override_amp_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__override_amp_high__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__override_amp_low__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__atb_select__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__force_fine_high_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__force_fine_low_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__override_amp_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__override_amp_high_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__override_amp_low_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__atb_select_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__NC7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__NC7_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__NC76__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK 0x001CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__NC76_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__bypass_bg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__vref_sel_fastreg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__chop_en__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__NC74__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__bypass_bg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__vref_sel_fastreg_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__chop_en_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__NC74_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_CONFIG
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT__STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT__STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK 0x0C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_SET_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK 0x7E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK 0x1F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK 0x0FC0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK 0x0600L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK 0x0070L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK 0x3F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK 0x7FE0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK 0x1F00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK 0x00C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK 0x01E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL__MODE_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_ERR
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_ERR__OV14_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK 0x07FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK 0x0700L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK 0x0F80L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK 0x7C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK 0x01C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK 0x0E00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_LD_VAL_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_DATA_MSK
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK 0x3C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK 0x003EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK 0x07C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK 0x03C0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK 0x0180L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK 0x1800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK 0x0038L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK 0x7FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK 0x7FFEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK 0x3FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK 0x1FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK 0x03E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK 0x6000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK 0x00F8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK 0x0FF0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__data_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__data_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vph__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vptx__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vp__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vph_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vptx_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vp_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_gd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vdccm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vdccp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vptx__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__override_regref_0__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vreg0__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vreg1__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vreg_s__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_gd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vdccm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vdccp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vptx_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__override_regref_0_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vreg0_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vreg1_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vreg_s_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_vcm__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txsm__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txsp__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txfm__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txfp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_rxdetref__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_nbias__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_pbias__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_vcm_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txsm_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txsp_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txfm_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txfp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_rxdetref_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_nbias_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_pbias_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__atb_s_enable__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__atb_vboost_vref__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__atb_vboost__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__vboost_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__meas_atb_vph_half_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__atb_s_enable_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__override_vref_boost_ref_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__atb_vboost_vref_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__atb_vboost_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__vboost_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__ovrd_vboost_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK 0x00FEL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__iboost_code__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__iboost_code_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__override_regref_1__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__override_regref_1_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__nc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__osc_pmos__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__osc_nmos__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__override_rxdetref__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__nc_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__osc_pmos_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__osc_nmos_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__meas_atb_bias_vptx_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__override_rxdetref_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__data_rate_reg_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__los_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__override_regref_slc_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__override_regref_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__meas_atb_rx_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_even_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__NC10__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__NC10_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__NC32__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__NC32_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__shor_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__NC0__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__NC0_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK 0x007EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK 0x007CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__NC20__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__NC20_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__rx_term_gd_en_reg_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__rx_term_dc_en_reg_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK 0x00F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R10
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R11
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R12
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R13
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R14
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R15
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R16
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R17
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R18
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R19
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R20
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R21
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R22
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R23
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R24
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R25
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R26
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R27
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R28
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R29
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R30
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R31
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_CMN_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK 0x0FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK 0x0FF8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK 0x7000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK 0x00E0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK 0x0F00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK 0x0380L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK 0x000CL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK 0x0030L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK 0x03F0L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK 0x0006L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK 0x0018L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK 0x0060L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK 0x0078L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK 0x0780L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK 0x0007L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK 0x07F8L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK 0x0003L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK 0x07FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK 0xC000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK 0xF800L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_SUP
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_LIN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_MAP
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK 0x007FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK 0xFF80L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_RX_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_INIT_PWRUP_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_ATT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK 0x00FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK 0xFF00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_VGA
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK 0x03FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK 0x1C00L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK 0x1FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK 0xE000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADAPT_DONE
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT 0xb
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT 0xd
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT 0xe
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT 0xf
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK 0x0400L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK 0x0800L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK 0x1000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK 0x2000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK 0x4000L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK 0x8000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT 0xc
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK 0x0FFFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK 0xF000L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK 0x000FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL_MASK 0xFFFFL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK 0x0010L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK 0x0020L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK 0xFFC0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK 0xFFF8L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT 0x3
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT 0x4
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK 0x0004L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK 0x0008L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK 0xFFF0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT 0x6
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT 0x7
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT 0x8
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT 0xa
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK 0x003FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK 0x0040L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK 0x0080L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK 0x0100L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK 0x0200L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK 0xFC00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK 0x001EL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT 0x2
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK 0x0002L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK 0xFFFCL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT 0x9
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK 0x01FFL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK 0xFE00L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT 0x5
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK 0x001FL
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK 0xFFE0L
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT 0x0
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT 0x1
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK 0x0001L
+#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK 0xFFFEL
+
+
+// addressBlock: nbio_lcu_kpfifo_kpfifo3_kpfifo_dir
+//KPFIFO3_PRI_TX_FIFO_HSCID
+#define KPFIFO3_PRI_TX_FIFO_HSCID__HwRev__SHIFT 0x0
+#define KPFIFO3_PRI_TX_FIFO_HSCID__HwMinVer__SHIFT 0x6
+#define KPFIFO3_PRI_TX_FIFO_HSCID__HwMajVer__SHIFT 0xd
+#define KPFIFO3_PRI_TX_FIFO_HSCID__HwRev_MASK 0x0000003FL
+#define KPFIFO3_PRI_TX_FIFO_HSCID__HwMinVer_MASK 0x00001FC0L
+#define KPFIFO3_PRI_TX_FIFO_HSCID__HwMajVer_MASK 0x000FE000L
+//KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__LinkID__SHIFT 0x0
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__FIFORdPtrOffset__SHIFT 0x8
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__FIFODepth__SHIFT 0x10
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__FIFOBypass__SHIFT 0x18
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__FIFOInitMode__SHIFT 0x19
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__Standalone__SHIFT 0x1a
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug0__SHIFT 0x1b
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug1__SHIFT 0x1c
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug2__SHIFT 0x1d
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug3__SHIFT 0x1e
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug4__SHIFT 0x1f
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__LinkID_MASK 0x000000FFL
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__FIFORdPtrOffset_MASK 0x0000FF00L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__FIFODepth_MASK 0x00FF0000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__FIFOBypass_MASK 0x01000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__FIFOInitMode_MASK 0x02000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__Standalone_MASK 0x04000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug0_MASK 0x08000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug1_MASK 0x10000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug2_MASK 0x20000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug3_MASK 0x40000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug4_MASK 0x80000000L
+//KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__LinkID__SHIFT 0x0
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__FIFORdPtrOffset__SHIFT 0x8
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__FIFODepth__SHIFT 0x10
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__FIFOBypass__SHIFT 0x18
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__FIFOInitMode__SHIFT 0x19
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__Standalone__SHIFT 0x1a
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug0__SHIFT 0x1b
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug1__SHIFT 0x1c
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug2__SHIFT 0x1d
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug3__SHIFT 0x1e
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug4__SHIFT 0x1f
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__LinkID_MASK 0x000000FFL
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__FIFORdPtrOffset_MASK 0x0000FF00L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__FIFODepth_MASK 0x00FF0000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__FIFOBypass_MASK 0x01000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__FIFOInitMode_MASK 0x02000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__Standalone_MASK 0x04000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug0_MASK 0x08000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug1_MASK 0x10000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug2_MASK 0x20000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug3_MASK 0x40000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug4_MASK 0x80000000L
+//KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__LinkID__SHIFT 0x0
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__FIFORdPtrOffset__SHIFT 0x8
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__FIFODepth__SHIFT 0x10
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__FIFOBypass__SHIFT 0x18
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__FIFOInitMode__SHIFT 0x19
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__Standalone__SHIFT 0x1a
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug0__SHIFT 0x1b
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug1__SHIFT 0x1c
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug2__SHIFT 0x1d
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug3__SHIFT 0x1e
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug4__SHIFT 0x1f
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__LinkID_MASK 0x000000FFL
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__FIFORdPtrOffset_MASK 0x0000FF00L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__FIFODepth_MASK 0x00FF0000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__FIFOBypass_MASK 0x01000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__FIFOInitMode_MASK 0x02000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__Standalone_MASK 0x04000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug0_MASK 0x08000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug1_MASK 0x10000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug2_MASK 0x20000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug3_MASK 0x40000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug4_MASK 0x80000000L
+//KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__LinkID__SHIFT 0x0
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__FIFORdPtrOffset__SHIFT 0x8
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__FIFODepth__SHIFT 0x10
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__FIFOBypass__SHIFT 0x18
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__FIFOInitMode__SHIFT 0x19
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__Standalone__SHIFT 0x1a
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug0__SHIFT 0x1b
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug1__SHIFT 0x1c
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug2__SHIFT 0x1d
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug3__SHIFT 0x1e
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug4__SHIFT 0x1f
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__LinkID_MASK 0x000000FFL
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__FIFORdPtrOffset_MASK 0x0000FF00L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__FIFODepth_MASK 0x00FF0000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__FIFOBypass_MASK 0x01000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__FIFOInitMode_MASK 0x02000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__Standalone_MASK 0x04000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug0_MASK 0x08000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug1_MASK 0x10000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug2_MASK 0x20000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug3_MASK 0x40000000L
+#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug4_MASK 0x80000000L
+//KPFIFO3_PCS_PMA_SOFT_RESET
+#define KPFIFO3_PCS_PMA_SOFT_RESET__KPFIFO_PHY_soft_ResetPhy__SHIFT 0x0
+#define KPFIFO3_PCS_PMA_SOFT_RESET__KPFIFO_PHY_soft_ResetPhy_MASK 0x00000001L
+
+
+// addressBlock: nbio_lcu_kpnp_kpnp3_kpnp_dir
+//KPNP_SNPS3_KPNP_HWSCVER
+#define KPNP_SNPS3_KPNP_HWSCVER__hw_revision__SHIFT 0x0
+#define KPNP_SNPS3_KPNP_HWSCVER__hw_minor_version_number__SHIFT 0x6
+#define KPNP_SNPS3_KPNP_HWSCVER__hw_major_version_number__SHIFT 0xd
+#define KPNP_SNPS3_KPNP_HWSCVER__hw_revision_MASK 0x0000003FL
+#define KPNP_SNPS3_KPNP_HWSCVER__hw_minor_version_number_MASK 0x00001FC0L
+#define KPNP_SNPS3_KPNP_HWSCVER__hw_major_version_number_MASK 0x000FE000L
+//KPNP_SNPS3_KPNP_PHY_INFO
+#define KPNP_SNPS3_KPNP_PHY_INFO__HwRev__SHIFT 0x0
+#define KPNP_SNPS3_KPNP_PHY_INFO__PHYVer__SHIFT 0x6
+#define KPNP_SNPS3_KPNP_PHY_INFO__Technology__SHIFT 0xd
+#define KPNP_SNPS3_KPNP_PHY_INFO__Type__SHIFT 0x14
+#define KPNP_SNPS3_KPNP_PHY_INFO__VendorID__SHIFT 0x1a
+#define KPNP_SNPS3_KPNP_PHY_INFO__HwRev_MASK 0x0000003FL
+#define KPNP_SNPS3_KPNP_PHY_INFO__PHYVer_MASK 0x00001FC0L
+#define KPNP_SNPS3_KPNP_PHY_INFO__Technology_MASK 0x000FE000L
+#define KPNP_SNPS3_KPNP_PHY_INFO__Type_MASK 0x03F00000L
+#define KPNP_SNPS3_KPNP_PHY_INFO__VendorID_MASK 0xFC000000L
+//KPNP_SNPS3_KPNP_LANE_ID
+#define KPNP_SNPS3_KPNP_LANE_ID__NodeStartLane__SHIFT 0x0
+#define KPNP_SNPS3_KPNP_LANE_ID__NodeEndLane__SHIFT 0x8
+#define KPNP_SNPS3_KPNP_LANE_ID__NodeStartLane_MASK 0x000000FFL
+#define KPNP_SNPS3_KPNP_LANE_ID__NodeEndLane_MASK 0x0000FF00L
+//KPNP_SNPS3_KPNP_LANE_REQ_CONTROL
+#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln0TxReq__SHIFT 0x0
+#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln0RxReq__SHIFT 0x1
+#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln1TxReq__SHIFT 0x2
+#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln1RxReq__SHIFT 0x3
+#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln2TxReq__SHIFT 0x4
+#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln2RxReq__SHIFT 0x5
+#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln3TxReq__SHIFT 0x6
+#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln3RxReq__SHIFT 0x7
+#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln0TxReq_MASK 0x00000001L
+#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln0RxReq_MASK 0x00000002L
+#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln1TxReq_MASK 0x00000004L
+#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln1RxReq_MASK 0x00000008L
+#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln2TxReq_MASK 0x00000010L
+#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln2RxReq_MASK 0x00000020L
+#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln3TxReq_MASK 0x00000040L
+#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln3RxReq_MASK 0x00000080L
+//KPNP_SNPS3_KPNP_LANE_REQ_STATUS
+#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln0TxAck__SHIFT 0x0
+#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln0RxAck__SHIFT 0x1
+#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln1TxAck__SHIFT 0x2
+#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln1RxAck__SHIFT 0x3
+#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln2TxAck__SHIFT 0x4
+#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln2RxAck__SHIFT 0x5
+#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln3TxAck__SHIFT 0x6
+#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln3RxAck__SHIFT 0x7
+#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln0TxAck_MASK 0x00000001L
+#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln0RxAck_MASK 0x00000002L
+#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln1TxAck_MASK 0x00000004L
+#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln1RxAck_MASK 0x00000008L
+#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln2TxAck_MASK 0x00000010L
+#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln2RxAck_MASK 0x00000020L
+#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln3TxAck_MASK 0x00000040L
+#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln3RxAck_MASK 0x00000080L
+//KPNP_SNPS3_KPNP_PMA_CONTROL0
+#define KPNP_SNPS3_KPNP_PMA_CONTROL0__ref_use_pad__SHIFT 0x0
+#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln0_Tx_Disable__SHIFT 0x10
+#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln0_Rx_Disable__SHIFT 0x11
+#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln1_Tx_Disable__SHIFT 0x12
+#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln1_Rx_Disable__SHIFT 0x13
+#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln2_Tx_Disable__SHIFT 0x14
+#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln2_Rx_Disable__SHIFT 0x15
+#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln3_Tx_Disable__SHIFT 0x16
+#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln3_Rx_Disable__SHIFT 0x17
+#define KPNP_SNPS3_KPNP_PMA_CONTROL0__ref_use_pad_MASK 0x00000001L
+#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln0_Tx_Disable_MASK 0x00010000L
+#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln0_Rx_Disable_MASK 0x00020000L
+#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln1_Tx_Disable_MASK 0x00040000L
+#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln1_Rx_Disable_MASK 0x00080000L
+#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln2_Tx_Disable_MASK 0x00100000L
+#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln2_Rx_Disable_MASK 0x00200000L
+#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln3_Tx_Disable_MASK 0x00400000L
+#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln3_Rx_Disable_MASK 0x00800000L
+//KPNP_SNPS3_KPNP_PMA_CONTROL1
+#define KPNP_SNPS3_KPNP_PMA_CONTROL1__rx_vref_ctrl__SHIFT 0x0
+#define KPNP_SNPS3_KPNP_PMA_CONTROL1__tx_vboost_lvl__SHIFT 0x5
+#define KPNP_SNPS3_KPNP_PMA_CONTROL1__rx_vref_ctrl_MASK 0x0000001FL
+#define KPNP_SNPS3_KPNP_PMA_CONTROL1__tx_vboost_lvl_MASK 0x000000E0L
+//KPNP_SNPS3_KPNP_PMA_CONTROL2
+#define KPNP_SNPS3_KPNP_PMA_CONTROL2__Staggering_Disable__SHIFT 0x0
+#define KPNP_SNPS3_KPNP_PMA_CONTROL2__Staggering_Mode__SHIFT 0x1
+#define KPNP_SNPS3_KPNP_PMA_CONTROL2__Staggering_Time_Resolution__SHIFT 0x2
+#define KPNP_SNPS3_KPNP_PMA_CONTROL2__Staggering_Disable_MASK 0x00000001L
+#define KPNP_SNPS3_KPNP_PMA_CONTROL2__Staggering_Mode_MASK 0x00000002L
+#define KPNP_SNPS3_KPNP_PMA_CONTROL2__Staggering_Time_Resolution_MASK 0x0000001CL
+//KPNP_SNPS3_KPNP_PHY_SOFT_RESET
+#define KPNP_SNPS3_KPNP_PHY_SOFT_RESET__Phy_Soft_Reset__SHIFT 0x0
+#define KPNP_SNPS3_KPNP_PHY_SOFT_RESET__Phy_Soft_Reset_MASK 0x00000001L
+//KPNP_SNPS3_KPNP_LANE_SOFT_RESET
+#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln0_Tx_Soft_Reset__SHIFT 0x0
+#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln0_Rx_Soft_Reset__SHIFT 0x1
+#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln1_Tx_Soft_Reset__SHIFT 0x2
+#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln1_Rx_Soft_Reset__SHIFT 0x3
+#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln2_Tx_Soft_Reset__SHIFT 0x4
+#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln2_Rx_Soft_Reset__SHIFT 0x5
+#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln3_Tx_Soft_Reset__SHIFT 0x6
+#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln3_Rx_Soft_Reset__SHIFT 0x7
+#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln0_Tx_Soft_Reset_MASK 0x00000001L
+#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln0_Rx_Soft_Reset_MASK 0x00000002L
+#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln1_Tx_Soft_Reset_MASK 0x00000004L
+#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln1_Rx_Soft_Reset_MASK 0x00000008L
+#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln2_Tx_Soft_Reset_MASK 0x00000010L
+#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln2_Rx_Soft_Reset_MASK 0x00000020L
+#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln3_Tx_Soft_Reset_MASK 0x00000040L
+#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln3_Rx_Soft_Reset_MASK 0x00000080L
+//KPNP_SNPS3_REG_RST_CTRL
+#define KPNP_SNPS3_REG_RST_CTRL__reset_regs_when_dxio_phy_rst__SHIFT 0x0
+#define KPNP_SNPS3_REG_RST_CTRL__reset_regs_when_dxio_phy_rst_MASK 0x00000001L
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf0_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF0_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF0_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf1_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF1_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF1_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf2_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF2_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF2_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf3_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF3_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF3_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf4_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF4_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF4_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf5_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF5_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF5_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf6_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF6_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF6_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf7_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF7_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF7_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf8_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF8_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF8_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF8_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf9_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF9_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF9_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF9_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf10_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF10_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF10_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF10_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf11_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF11_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF11_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF11_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf12_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF12_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF12_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF12_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf13_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF13_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF13_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF13_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf14_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF14_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF14_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF14_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf15_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF15_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF15_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF15_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: syshub_mmreg_ind_syshubind
+//SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000008L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000010L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000020L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000040L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000080L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00010000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00020000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00040000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00080000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00100000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00200000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00400000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00800000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN_MASK 0x80000000L
+//SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER_MASK 0x0000FFFFL
+//SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0xf
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x10
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x11
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en_MASK 0x00008000L
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en_MASK 0x00010000L
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en_MASK 0x00020000L
+//SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0xf
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x10
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x11
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en_MASK 0x00008000L
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en_MASK 0x00010000L
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en_MASK 0x00020000L
+//SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L
+//SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L
+//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_IND_SYSHUB_CG_CNTL
+#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT 0x8
+#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT 0x10
+#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER_MASK 0x0000FF00L
+#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER_MASK 0x00FF0000L
+//SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT 0x1
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT 0x2
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT 0x3
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT 0x4
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT 0x5
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT 0x6
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT 0x7
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT 0x8
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT 0x9
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT 0xa
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT 0xb
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT 0xc
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT 0xd
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT 0xe
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT 0xf
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT 0x10
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2_MASK 0x00000004L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3_MASK 0x00000008L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4_MASK 0x00000010L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5_MASK 0x00000020L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6_MASK 0x00000040L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7_MASK 0x00000080L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9_MASK 0x00000200L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10_MASK 0x00000400L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11_MASK 0x00000800L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12_MASK 0x00001000L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13_MASK 0x00002000L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14_MASK 0x00004000L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15_MASK 0x00008000L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF_MASK 0x00010000L
+//SYSHUB_MMREG_IND_SYSHUB_HP_TIMER
+#define SYSHUB_MMREG_IND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER_MASK 0xFFFFFFFFL
+//SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK__SHIFT 0x1
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK__SHIFT 0x2
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK__SHIFT 0xa
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK__SHIFT 0xb
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REGS_DIS_SOCCLK__SHIFT 0xc
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK__SHIFT 0xd
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK_MASK 0x000003FCL
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK_MASK 0x00000400L
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK_MASK 0x00000800L
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REGS_DIS_SOCCLK_MASK 0x00001000L
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK_MASK 0x00002000L
+//SYSHUB_MMREG_IND_SYSHUB_SCRATCH
+#define SYSHUB_MMREG_IND_SYSHUB_SCRATCH__SCRATCH__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
+//SYSHUB_MMREG_IND_SYSHUB_CL_MASK
+#define SYSHUB_MMREG_IND_SYSHUB_CL_MASK__MP1DRAM_MASK_DIS__SHIFT 0x1
+#define SYSHUB_MMREG_IND_SYSHUB_CL_MASK__MP1_MASK_DIS__SHIFT 0x2
+#define SYSHUB_MMREG_IND_SYSHUB_CL_MASK__MP1DRAM_MASK_DIS_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_SYSHUB_CL_MASK__MP1_MASK_DIS_MASK 0x00000004L
+//SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000008L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000010L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000020L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000040L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000080L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00010000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00020000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00040000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00080000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00100000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00200000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00400000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00800000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN_MASK 0x80000000L
+//SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER_MASK 0x0000FFFFL
+//SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT 0xf
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT 0x10
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en_MASK 0x00008000L
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en_MASK 0x00010000L
+//SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT 0xf
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT 0x10
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en_MASK 0x00008000L
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en_MASK 0x00010000L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK__SHIFT 0x1
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK__SHIFT 0x2
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK__SHIFT 0xa
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK__SHIFT 0xb
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REGS_DIS_SHUBCLK__SHIFT 0xc
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK_MASK 0x000003FCL
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK_MASK 0x00000400L
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK_MASK 0x00000800L
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REGS_DIS_SHUBCLK_MASK 0x00001000L
+//SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS
+#define SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS
+#define SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_0_AMIB_2_FN_MOD_BM_ISS
+#define SYSHUB_MMREG_IND_NIC400_0_AMIB_2_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_0_AMIB_2_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_0_AMIB_2_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_0_AMIB_2_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_1_AMIB_3_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_3_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_3_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_3_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_3_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_1_AMIB_4_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_4_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_4_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_4_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_4_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS
+#define SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h
new file mode 100644
index 000000000000..1fddd0f5aaa2
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _osssys_4_0_DEFAULT_HEADER
+#define _osssys_4_0_DEFAULT_HEADER
+
+
+// addressBlock: osssys_osssysdec
+#define mmIH_VMID_0_LUT_DEFAULT 0x00000000
+#define mmIH_VMID_1_LUT_DEFAULT 0x00000000
+#define mmIH_VMID_2_LUT_DEFAULT 0x00000000
+#define mmIH_VMID_3_LUT_DEFAULT 0x00000000
+#define mmIH_VMID_4_LUT_DEFAULT 0x00000000
+#define mmIH_VMID_5_LUT_DEFAULT 0x00000000
+#define mmIH_VMID_6_LUT_DEFAULT 0x00000000
+#define mmIH_VMID_7_LUT_DEFAULT 0x00000000
+#define mmIH_VMID_8_LUT_DEFAULT 0x00000000
+#define mmIH_VMID_9_LUT_DEFAULT 0x00000000
+#define mmIH_VMID_10_LUT_DEFAULT 0x00000000
+#define mmIH_VMID_11_LUT_DEFAULT 0x00000000
+#define mmIH_VMID_12_LUT_DEFAULT 0x00000000
+#define mmIH_VMID_13_LUT_DEFAULT 0x00000000
+#define mmIH_VMID_14_LUT_DEFAULT 0x00000000
+#define mmIH_VMID_15_LUT_DEFAULT 0x00000000
+#define mmIH_VMID_0_LUT_MM_DEFAULT 0x00000000
+#define mmIH_VMID_1_LUT_MM_DEFAULT 0x00000000
+#define mmIH_VMID_2_LUT_MM_DEFAULT 0x00000000
+#define mmIH_VMID_3_LUT_MM_DEFAULT 0x00000000
+#define mmIH_VMID_4_LUT_MM_DEFAULT 0x00000000
+#define mmIH_VMID_5_LUT_MM_DEFAULT 0x00000000
+#define mmIH_VMID_6_LUT_MM_DEFAULT 0x00000000
+#define mmIH_VMID_7_LUT_MM_DEFAULT 0x00000000
+#define mmIH_VMID_8_LUT_MM_DEFAULT 0x00000000
+#define mmIH_VMID_9_LUT_MM_DEFAULT 0x00000000
+#define mmIH_VMID_10_LUT_MM_DEFAULT 0x00000000
+#define mmIH_VMID_11_LUT_MM_DEFAULT 0x00000000
+#define mmIH_VMID_12_LUT_MM_DEFAULT 0x00000000
+#define mmIH_VMID_13_LUT_MM_DEFAULT 0x00000000
+#define mmIH_VMID_14_LUT_MM_DEFAULT 0x00000000
+#define mmIH_VMID_15_LUT_MM_DEFAULT 0x00000000
+#define mmIH_COOKIE_0_DEFAULT 0x00000000
+#define mmIH_COOKIE_1_DEFAULT 0x00000000
+#define mmIH_COOKIE_2_DEFAULT 0x00000000
+#define mmIH_COOKIE_3_DEFAULT 0x00000000
+#define mmIH_COOKIE_4_DEFAULT 0x00000000
+#define mmIH_COOKIE_5_DEFAULT 0x00000000
+#define mmIH_COOKIE_6_DEFAULT 0x00000000
+#define mmIH_COOKIE_7_DEFAULT 0x00000000
+#define mmIH_REGISTER_LAST_PART0_DEFAULT 0x00000000
+#define mmSEM_REQ_INPUT_0_DEFAULT 0x00000000
+#define mmSEM_REQ_INPUT_1_DEFAULT 0x00000000
+#define mmSEM_REQ_INPUT_2_DEFAULT 0x00000000
+#define mmSEM_REQ_INPUT_3_DEFAULT 0x00000000
+#define mmSEM_REGISTER_LAST_PART0_DEFAULT 0x00000000
+#define mmIH_RB_CNTL_DEFAULT 0x10610000
+#define mmIH_RB_BASE_DEFAULT 0x00000000
+#define mmIH_RB_BASE_HI_DEFAULT 0x00000000
+#define mmIH_RB_RPTR_DEFAULT 0x00000000
+#define mmIH_RB_WPTR_DEFAULT 0x00000000
+#define mmIH_RB_WPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmIH_RB_WPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmIH_DOORBELL_RPTR_DEFAULT 0x00000000
+#define mmIH_RB_CNTL_RING1_DEFAULT 0x10410000
+#define mmIH_RB_BASE_RING1_DEFAULT 0x00000000
+#define mmIH_RB_BASE_HI_RING1_DEFAULT 0x00000000
+#define mmIH_RB_RPTR_RING1_DEFAULT 0x00000000
+#define mmIH_RB_WPTR_RING1_DEFAULT 0x00000000
+#define mmIH_DOORBELL_RPTR_RING1_DEFAULT 0x00000000
+#define mmIH_RB_CNTL_RING2_DEFAULT 0x10410000
+#define mmIH_RB_BASE_RING2_DEFAULT 0x00000000
+#define mmIH_RB_BASE_HI_RING2_DEFAULT 0x00000000
+#define mmIH_RB_RPTR_RING2_DEFAULT 0x00000000
+#define mmIH_RB_WPTR_RING2_DEFAULT 0x00000000
+#define mmIH_DOORBELL_RPTR_RING2_DEFAULT 0x00000000
+#define mmIH_VERSION_DEFAULT 0x00000400
+#define mmIH_CNTL_DEFAULT 0x01000000
+#define mmIH_CNTL2_DEFAULT 0x000000ff
+#define mmIH_STATUS_DEFAULT 0x00040847
+#define mmIH_PERFMON_CNTL_DEFAULT 0x00000000
+#define mmIH_PERFCOUNTER0_RESULT_DEFAULT 0x00000000
+#define mmIH_PERFCOUNTER1_RESULT_DEFAULT 0x00000000
+#define mmIH_DSM_MATCH_VALUE_BIT_31_0_DEFAULT 0x00000000
+#define mmIH_DSM_MATCH_VALUE_BIT_63_32_DEFAULT 0x00000000
+#define mmIH_DSM_MATCH_VALUE_BIT_95_64_DEFAULT 0x00000000
+#define mmIH_DSM_MATCH_FIELD_CONTROL_DEFAULT 0x0000007f
+#define mmIH_DSM_MATCH_DATA_CONTROL_DEFAULT 0x0fffffff
+#define mmIH_DSM_MATCH_FCN_ID_DEFAULT 0x00000000
+#define mmIH_LIMIT_INT_RATE_CNTL_DEFAULT 0x00000000
+#define mmIH_VF_RB_STATUS_DEFAULT 0x00000000
+#define mmIH_VF_RB_STATUS2_DEFAULT 0x00000000
+#define mmIH_VF_RB1_STATUS_DEFAULT 0x00000000
+#define mmIH_VF_RB1_STATUS2_DEFAULT 0x00000000
+#define mmIH_VF_RB2_STATUS_DEFAULT 0x00000000
+#define mmIH_VF_RB2_STATUS2_DEFAULT 0x00000000
+#define mmIH_INT_FLOOD_CNTL_DEFAULT 0x00000000
+#define mmIH_RB0_INT_FLOOD_STATUS_DEFAULT 0x00000000
+#define mmIH_RB1_INT_FLOOD_STATUS_DEFAULT 0x00000000
+#define mmIH_RB2_INT_FLOOD_STATUS_DEFAULT 0x00000000
+#define mmIH_INT_FLOOD_STATUS_DEFAULT 0x00000000
+#define mmIH_STORM_CLIENT_LIST_CNTL_DEFAULT 0x00000000
+#define mmIH_CLK_CTRL_DEFAULT 0x00000000
+#define mmIH_INT_FLAGS_DEFAULT 0x00000000
+#define mmIH_LAST_INT_INFO0_DEFAULT 0x00000000
+#define mmIH_LAST_INT_INFO1_DEFAULT 0x00000000
+#define mmIH_LAST_INT_INFO2_DEFAULT 0x00000000
+#define mmIH_SCRATCH_DEFAULT 0x00000000
+#define mmIH_CLIENT_CREDIT_ERROR_DEFAULT 0x00000000
+#define mmIH_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000
+#define mmIH_COOKIE_REC_VIOLATION_LOG_DEFAULT 0x00000000
+#define mmIH_CREDIT_STATUS_DEFAULT 0xfffffffe
+#define mmIH_MMHUB_ERROR_DEFAULT 0x00000000
+#define mmIH_REGISTER_LAST_PART2_DEFAULT 0x00000000
+#define mmSEM_CLK_CTRL_DEFAULT 0x00000100
+#define mmSEM_UTC_CREDIT_DEFAULT 0x00000510
+#define mmSEM_UTC_CONFIG_DEFAULT 0x00000020
+#define mmSEM_UTCL2_TRAN_EN_LUT_DEFAULT 0x800000ff
+#define mmSEM_MCIF_CONFIG_DEFAULT 0x00001040
+#define mmSEM_PERFMON_CNTL_DEFAULT 0x00000000
+#define mmSEM_PERFCOUNTER0_RESULT_DEFAULT 0x00000000
+#define mmSEM_PERFCOUNTER1_RESULT_DEFAULT 0x00000000
+#define mmSEM_STATUS_DEFAULT 0x80f90003
+#define mmSEM_MAILBOX_CLIENTCONFIG_DEFAULT 0x00fac688
+#define mmSEM_MAILBOX_DEFAULT 0x00000000
+#define mmSEM_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmSEM_CHICKEN_BITS_DEFAULT 0x00084ad6
+#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA_DEFAULT 0x00000008
+#define mmSEM_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000
+#define mmSEM_OUTSTANDING_THRESHOLD_DEFAULT 0x00000010
+#define mmSEM_REGISTER_LAST_PART2_DEFAULT 0x00000000
+#define mmIH_ACTIVE_FCN_ID_DEFAULT 0x00000000
+#define mmIH_VIRT_RESET_REQ_DEFAULT 0x00000000
+#define mmIH_CLIENT_CFG_DEFAULT 0x0000001f
+#define mmIH_CLIENT_CFG_INDEX_DEFAULT 0x00000000
+#define mmIH_CLIENT_CFG_DATA_DEFAULT 0x00000000
+#define mmIH_CID_REMAP_INDEX_DEFAULT 0x00000000
+#define mmIH_CID_REMAP_DATA_DEFAULT 0x00000000
+#define mmIH_CHICKEN_DEFAULT 0x00000000
+#define mmIH_MMHUB_CNTL_DEFAULT 0x00000001
+#define mmIH_REGISTER_LAST_PART1_DEFAULT 0x00000000
+#define mmSEM_ACTIVE_FCN_ID_DEFAULT 0x00000000
+#define mmSEM_VIRT_RESET_REQ_DEFAULT 0x00000000
+#define mmSEM_RESP_SDMA0_DEFAULT 0x0004950c
+#define mmSEM_RESP_SDMA1_DEFAULT 0x0004958c
+#define mmSEM_RESP_UVD_DEFAULT 0x0004860c
+#define mmSEM_RESP_VCE_0_DEFAULT 0x0004900c
+#define mmSEM_RESP_ACP_DEFAULT 0x0004870c
+#define mmSEM_RESP_ISP_DEFAULT 0x00000000
+#define mmSEM_RESP_VCE_1_DEFAULT 0x0004908c
+#define mmSEM_RESP_VP8_DEFAULT 0x00000000
+#define mmSEM_RESP_GC_DEFAULT 0x0004858c
+#define mmSEM_CID_REMAP_INDEX_DEFAULT 0x00000000
+#define mmSEM_CID_REMAP_DATA_DEFAULT 0x00000000
+#define mmSEM_ATOMIC_OP_LUT_DEFAULT 0x040a102f
+#define mmSEM_EDC_CONFIG_DEFAULT 0x00000002
+#define mmSEM_CHICKEN_BITS2_DEFAULT 0x00000000
+#define mmSEM_MMHUB_CNTL_DEFAULT 0x00000000
+#define mmSEM_REGISTER_LAST_PART1_DEFAULT 0x00000000
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_offset.h
new file mode 100644
index 000000000000..96ab3fe89620
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_offset.h
@@ -0,0 +1,327 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _osssys_4_0_OFFSET_HEADER
+#define _osssys_4_0_OFFSET_HEADER
+
+
+
+// addressBlock: osssys_osssysdec
+// base address: 0x4280
+#define mmIH_VMID_0_LUT 0x0000
+#define mmIH_VMID_0_LUT_BASE_IDX 0
+#define mmIH_VMID_1_LUT 0x0001
+#define mmIH_VMID_1_LUT_BASE_IDX 0
+#define mmIH_VMID_2_LUT 0x0002
+#define mmIH_VMID_2_LUT_BASE_IDX 0
+#define mmIH_VMID_3_LUT 0x0003
+#define mmIH_VMID_3_LUT_BASE_IDX 0
+#define mmIH_VMID_4_LUT 0x0004
+#define mmIH_VMID_4_LUT_BASE_IDX 0
+#define mmIH_VMID_5_LUT 0x0005
+#define mmIH_VMID_5_LUT_BASE_IDX 0
+#define mmIH_VMID_6_LUT 0x0006
+#define mmIH_VMID_6_LUT_BASE_IDX 0
+#define mmIH_VMID_7_LUT 0x0007
+#define mmIH_VMID_7_LUT_BASE_IDX 0
+#define mmIH_VMID_8_LUT 0x0008
+#define mmIH_VMID_8_LUT_BASE_IDX 0
+#define mmIH_VMID_9_LUT 0x0009
+#define mmIH_VMID_9_LUT_BASE_IDX 0
+#define mmIH_VMID_10_LUT 0x000a
+#define mmIH_VMID_10_LUT_BASE_IDX 0
+#define mmIH_VMID_11_LUT 0x000b
+#define mmIH_VMID_11_LUT_BASE_IDX 0
+#define mmIH_VMID_12_LUT 0x000c
+#define mmIH_VMID_12_LUT_BASE_IDX 0
+#define mmIH_VMID_13_LUT 0x000d
+#define mmIH_VMID_13_LUT_BASE_IDX 0
+#define mmIH_VMID_14_LUT 0x000e
+#define mmIH_VMID_14_LUT_BASE_IDX 0
+#define mmIH_VMID_15_LUT 0x000f
+#define mmIH_VMID_15_LUT_BASE_IDX 0
+#define mmIH_VMID_0_LUT_MM 0x0010
+#define mmIH_VMID_0_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_1_LUT_MM 0x0011
+#define mmIH_VMID_1_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_2_LUT_MM 0x0012
+#define mmIH_VMID_2_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_3_LUT_MM 0x0013
+#define mmIH_VMID_3_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_4_LUT_MM 0x0014
+#define mmIH_VMID_4_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_5_LUT_MM 0x0015
+#define mmIH_VMID_5_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_6_LUT_MM 0x0016
+#define mmIH_VMID_6_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_7_LUT_MM 0x0017
+#define mmIH_VMID_7_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_8_LUT_MM 0x0018
+#define mmIH_VMID_8_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_9_LUT_MM 0x0019
+#define mmIH_VMID_9_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_10_LUT_MM 0x001a
+#define mmIH_VMID_10_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_11_LUT_MM 0x001b
+#define mmIH_VMID_11_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_12_LUT_MM 0x001c
+#define mmIH_VMID_12_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_13_LUT_MM 0x001d
+#define mmIH_VMID_13_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_14_LUT_MM 0x001e
+#define mmIH_VMID_14_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_15_LUT_MM 0x001f
+#define mmIH_VMID_15_LUT_MM_BASE_IDX 0
+#define mmIH_COOKIE_0 0x0020
+#define mmIH_COOKIE_0_BASE_IDX 0
+#define mmIH_COOKIE_1 0x0021
+#define mmIH_COOKIE_1_BASE_IDX 0
+#define mmIH_COOKIE_2 0x0022
+#define mmIH_COOKIE_2_BASE_IDX 0
+#define mmIH_COOKIE_3 0x0023
+#define mmIH_COOKIE_3_BASE_IDX 0
+#define mmIH_COOKIE_4 0x0024
+#define mmIH_COOKIE_4_BASE_IDX 0
+#define mmIH_COOKIE_5 0x0025
+#define mmIH_COOKIE_5_BASE_IDX 0
+#define mmIH_COOKIE_6 0x0026
+#define mmIH_COOKIE_6_BASE_IDX 0
+#define mmIH_COOKIE_7 0x0027
+#define mmIH_COOKIE_7_BASE_IDX 0
+#define mmIH_REGISTER_LAST_PART0 0x003f
+#define mmIH_REGISTER_LAST_PART0_BASE_IDX 0
+#define mmSEM_REQ_INPUT_0 0x0040
+#define mmSEM_REQ_INPUT_0_BASE_IDX 0
+#define mmSEM_REQ_INPUT_1 0x0041
+#define mmSEM_REQ_INPUT_1_BASE_IDX 0
+#define mmSEM_REQ_INPUT_2 0x0042
+#define mmSEM_REQ_INPUT_2_BASE_IDX 0
+#define mmSEM_REQ_INPUT_3 0x0043
+#define mmSEM_REQ_INPUT_3_BASE_IDX 0
+#define mmSEM_REGISTER_LAST_PART0 0x007f
+#define mmSEM_REGISTER_LAST_PART0_BASE_IDX 0
+#define mmIH_RB_CNTL 0x0080
+#define mmIH_RB_CNTL_BASE_IDX 0
+#define mmIH_RB_BASE 0x0081
+#define mmIH_RB_BASE_BASE_IDX 0
+#define mmIH_RB_BASE_HI 0x0082
+#define mmIH_RB_BASE_HI_BASE_IDX 0
+#define mmIH_RB_RPTR 0x0083
+#define mmIH_RB_RPTR_BASE_IDX 0
+#define mmIH_RB_WPTR 0x0084
+#define mmIH_RB_WPTR_BASE_IDX 0
+#define mmIH_RB_WPTR_ADDR_HI 0x0085
+#define mmIH_RB_WPTR_ADDR_HI_BASE_IDX 0
+#define mmIH_RB_WPTR_ADDR_LO 0x0086
+#define mmIH_RB_WPTR_ADDR_LO_BASE_IDX 0
+#define mmIH_DOORBELL_RPTR 0x0087
+#define mmIH_DOORBELL_RPTR_BASE_IDX 0
+#define mmIH_RB_CNTL_RING1 0x0088
+#define mmIH_RB_CNTL_RING1_BASE_IDX 0
+#define mmIH_RB_BASE_RING1 0x0089
+#define mmIH_RB_BASE_RING1_BASE_IDX 0
+#define mmIH_RB_BASE_HI_RING1 0x008a
+#define mmIH_RB_BASE_HI_RING1_BASE_IDX 0
+#define mmIH_RB_RPTR_RING1 0x008b
+#define mmIH_RB_RPTR_RING1_BASE_IDX 0
+#define mmIH_RB_WPTR_RING1 0x008c
+#define mmIH_RB_WPTR_RING1_BASE_IDX 0
+#define mmIH_DOORBELL_RPTR_RING1 0x008f
+#define mmIH_DOORBELL_RPTR_RING1_BASE_IDX 0
+#define mmIH_RB_CNTL_RING2 0x0090
+#define mmIH_RB_CNTL_RING2_BASE_IDX 0
+#define mmIH_RB_BASE_RING2 0x0091
+#define mmIH_RB_BASE_RING2_BASE_IDX 0
+#define mmIH_RB_BASE_HI_RING2 0x0092
+#define mmIH_RB_BASE_HI_RING2_BASE_IDX 0
+#define mmIH_RB_RPTR_RING2 0x0093
+#define mmIH_RB_RPTR_RING2_BASE_IDX 0
+#define mmIH_RB_WPTR_RING2 0x0094
+#define mmIH_RB_WPTR_RING2_BASE_IDX 0
+#define mmIH_DOORBELL_RPTR_RING2 0x0097
+#define mmIH_DOORBELL_RPTR_RING2_BASE_IDX 0
+#define mmIH_VERSION 0x0098
+#define mmIH_VERSION_BASE_IDX 0
+#define mmIH_CNTL 0x00c0
+#define mmIH_CNTL_BASE_IDX 0
+#define mmIH_CNTL2 0x00c1
+#define mmIH_CNTL2_BASE_IDX 0
+#define mmIH_STATUS 0x00c2
+#define mmIH_STATUS_BASE_IDX 0
+#define mmIH_PERFMON_CNTL 0x00c3
+#define mmIH_PERFMON_CNTL_BASE_IDX 0
+#define mmIH_PERFCOUNTER0_RESULT 0x00c4
+#define mmIH_PERFCOUNTER0_RESULT_BASE_IDX 0
+#define mmIH_PERFCOUNTER1_RESULT 0x00c5
+#define mmIH_PERFCOUNTER1_RESULT_BASE_IDX 0
+#define mmIH_DSM_MATCH_VALUE_BIT_31_0 0x00c7
+#define mmIH_DSM_MATCH_VALUE_BIT_31_0_BASE_IDX 0
+#define mmIH_DSM_MATCH_VALUE_BIT_63_32 0x00c8
+#define mmIH_DSM_MATCH_VALUE_BIT_63_32_BASE_IDX 0
+#define mmIH_DSM_MATCH_VALUE_BIT_95_64 0x00c9
+#define mmIH_DSM_MATCH_VALUE_BIT_95_64_BASE_IDX 0
+#define mmIH_DSM_MATCH_FIELD_CONTROL 0x00ca
+#define mmIH_DSM_MATCH_FIELD_CONTROL_BASE_IDX 0
+#define mmIH_DSM_MATCH_DATA_CONTROL 0x00cb
+#define mmIH_DSM_MATCH_DATA_CONTROL_BASE_IDX 0
+#define mmIH_DSM_MATCH_FCN_ID 0x00cc
+#define mmIH_DSM_MATCH_FCN_ID_BASE_IDX 0
+#define mmIH_LIMIT_INT_RATE_CNTL 0x00cd
+#define mmIH_LIMIT_INT_RATE_CNTL_BASE_IDX 0
+#define mmIH_VF_RB_STATUS 0x00ce
+#define mmIH_VF_RB_STATUS_BASE_IDX 0
+#define mmIH_VF_RB_STATUS2 0x00cf
+#define mmIH_VF_RB_STATUS2_BASE_IDX 0
+#define mmIH_VF_RB1_STATUS 0x00d0
+#define mmIH_VF_RB1_STATUS_BASE_IDX 0
+#define mmIH_VF_RB1_STATUS2 0x00d1
+#define mmIH_VF_RB1_STATUS2_BASE_IDX 0
+#define mmIH_VF_RB2_STATUS 0x00d2
+#define mmIH_VF_RB2_STATUS_BASE_IDX 0
+#define mmIH_VF_RB2_STATUS2 0x00d3
+#define mmIH_VF_RB2_STATUS2_BASE_IDX 0
+#define mmIH_INT_FLOOD_CNTL 0x00d5
+#define mmIH_INT_FLOOD_CNTL_BASE_IDX 0
+#define mmIH_RB0_INT_FLOOD_STATUS 0x00d6
+#define mmIH_RB0_INT_FLOOD_STATUS_BASE_IDX 0
+#define mmIH_RB1_INT_FLOOD_STATUS 0x00d7
+#define mmIH_RB1_INT_FLOOD_STATUS_BASE_IDX 0
+#define mmIH_RB2_INT_FLOOD_STATUS 0x00d8
+#define mmIH_RB2_INT_FLOOD_STATUS_BASE_IDX 0
+#define mmIH_INT_FLOOD_STATUS 0x00d9
+#define mmIH_INT_FLOOD_STATUS_BASE_IDX 0
+#define mmIH_STORM_CLIENT_LIST_CNTL 0x00da
+#define mmIH_STORM_CLIENT_LIST_CNTL_BASE_IDX 0
+#define mmIH_CLK_CTRL 0x00db
+#define mmIH_CLK_CTRL_BASE_IDX 0
+#define mmIH_INT_FLAGS 0x00dc
+#define mmIH_INT_FLAGS_BASE_IDX 0
+#define mmIH_LAST_INT_INFO0 0x00dd
+#define mmIH_LAST_INT_INFO0_BASE_IDX 0
+#define mmIH_LAST_INT_INFO1 0x00de
+#define mmIH_LAST_INT_INFO1_BASE_IDX 0
+#define mmIH_LAST_INT_INFO2 0x00df
+#define mmIH_LAST_INT_INFO2_BASE_IDX 0
+#define mmIH_SCRATCH 0x00e0
+#define mmIH_SCRATCH_BASE_IDX 0
+#define mmIH_CLIENT_CREDIT_ERROR 0x00e1
+#define mmIH_CLIENT_CREDIT_ERROR_BASE_IDX 0
+#define mmIH_GPU_IOV_VIOLATION_LOG 0x00e2
+#define mmIH_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
+#define mmIH_COOKIE_REC_VIOLATION_LOG 0x00e3
+#define mmIH_COOKIE_REC_VIOLATION_LOG_BASE_IDX 0
+#define mmIH_CREDIT_STATUS 0x00e4
+#define mmIH_CREDIT_STATUS_BASE_IDX 0
+#define mmIH_MMHUB_ERROR 0x00e5
+#define mmIH_MMHUB_ERROR_BASE_IDX 0
+#define mmIH_REGISTER_LAST_PART2 0x00ff
+#define mmIH_REGISTER_LAST_PART2_BASE_IDX 0
+#define mmSEM_CLK_CTRL 0x0100
+#define mmSEM_CLK_CTRL_BASE_IDX 0
+#define mmSEM_UTC_CREDIT 0x0101
+#define mmSEM_UTC_CREDIT_BASE_IDX 0
+#define mmSEM_UTC_CONFIG 0x0102
+#define mmSEM_UTC_CONFIG_BASE_IDX 0
+#define mmSEM_UTCL2_TRAN_EN_LUT 0x0103
+#define mmSEM_UTCL2_TRAN_EN_LUT_BASE_IDX 0
+#define mmSEM_MCIF_CONFIG 0x0104
+#define mmSEM_MCIF_CONFIG_BASE_IDX 0
+#define mmSEM_PERFMON_CNTL 0x0105
+#define mmSEM_PERFMON_CNTL_BASE_IDX 0
+#define mmSEM_PERFCOUNTER0_RESULT 0x0106
+#define mmSEM_PERFCOUNTER0_RESULT_BASE_IDX 0
+#define mmSEM_PERFCOUNTER1_RESULT 0x0107
+#define mmSEM_PERFCOUNTER1_RESULT_BASE_IDX 0
+#define mmSEM_STATUS 0x0108
+#define mmSEM_STATUS_BASE_IDX 0
+#define mmSEM_MAILBOX_CLIENTCONFIG 0x0109
+#define mmSEM_MAILBOX_CLIENTCONFIG_BASE_IDX 0
+#define mmSEM_MAILBOX 0x010a
+#define mmSEM_MAILBOX_BASE_IDX 0
+#define mmSEM_MAILBOX_CONTROL 0x010b
+#define mmSEM_MAILBOX_CONTROL_BASE_IDX 0
+#define mmSEM_CHICKEN_BITS 0x010c
+#define mmSEM_CHICKEN_BITS_BASE_IDX 0
+#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0x010d
+#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA_BASE_IDX 0
+#define mmSEM_GPU_IOV_VIOLATION_LOG 0x010e
+#define mmSEM_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
+#define mmSEM_OUTSTANDING_THRESHOLD 0x010f
+#define mmSEM_OUTSTANDING_THRESHOLD_BASE_IDX 0
+#define mmSEM_REGISTER_LAST_PART2 0x017f
+#define mmSEM_REGISTER_LAST_PART2_BASE_IDX 0
+#define mmIH_ACTIVE_FCN_ID 0x0180
+#define mmIH_ACTIVE_FCN_ID_BASE_IDX 0
+#define mmIH_VIRT_RESET_REQ 0x0181
+#define mmIH_VIRT_RESET_REQ_BASE_IDX 0
+#define mmIH_CLIENT_CFG 0x0184
+#define mmIH_CLIENT_CFG_BASE_IDX 0
+#define mmIH_CLIENT_CFG_INDEX 0x0188
+#define mmIH_CLIENT_CFG_INDEX_BASE_IDX 0
+#define mmIH_CLIENT_CFG_DATA 0x0189
+#define mmIH_CLIENT_CFG_DATA_BASE_IDX 0
+#define mmIH_CID_REMAP_INDEX 0x018a
+#define mmIH_CID_REMAP_INDEX_BASE_IDX 0
+#define mmIH_CID_REMAP_DATA 0x018b
+#define mmIH_CID_REMAP_DATA_BASE_IDX 0
+#define mmIH_CHICKEN 0x018c
+#define mmIH_CHICKEN_BASE_IDX 0
+#define mmIH_MMHUB_CNTL 0x018d
+#define mmIH_MMHUB_CNTL_BASE_IDX 0
+#define mmIH_REGISTER_LAST_PART1 0x019f
+#define mmIH_REGISTER_LAST_PART1_BASE_IDX 0
+#define mmSEM_ACTIVE_FCN_ID 0x01a0
+#define mmSEM_ACTIVE_FCN_ID_BASE_IDX 0
+#define mmSEM_VIRT_RESET_REQ 0x01a1
+#define mmSEM_VIRT_RESET_REQ_BASE_IDX 0
+#define mmSEM_RESP_SDMA0 0x01a4
+#define mmSEM_RESP_SDMA0_BASE_IDX 0
+#define mmSEM_RESP_SDMA1 0x01a5
+#define mmSEM_RESP_SDMA1_BASE_IDX 0
+#define mmSEM_RESP_UVD 0x01a6
+#define mmSEM_RESP_UVD_BASE_IDX 0
+#define mmSEM_RESP_VCE_0 0x01a7
+#define mmSEM_RESP_VCE_0_BASE_IDX 0
+#define mmSEM_RESP_ACP 0x01a8
+#define mmSEM_RESP_ACP_BASE_IDX 0
+#define mmSEM_RESP_ISP 0x01a9
+#define mmSEM_RESP_ISP_BASE_IDX 0
+#define mmSEM_RESP_VCE_1 0x01aa
+#define mmSEM_RESP_VCE_1_BASE_IDX 0
+#define mmSEM_RESP_VP8 0x01ab
+#define mmSEM_RESP_VP8_BASE_IDX 0
+#define mmSEM_RESP_GC 0x01ac
+#define mmSEM_RESP_GC_BASE_IDX 0
+#define mmSEM_CID_REMAP_INDEX 0x01b0
+#define mmSEM_CID_REMAP_INDEX_BASE_IDX 0
+#define mmSEM_CID_REMAP_DATA 0x01b1
+#define mmSEM_CID_REMAP_DATA_BASE_IDX 0
+#define mmSEM_ATOMIC_OP_LUT 0x01b2
+#define mmSEM_ATOMIC_OP_LUT_BASE_IDX 0
+#define mmSEM_EDC_CONFIG 0x01b3
+#define mmSEM_EDC_CONFIG_BASE_IDX 0
+#define mmSEM_CHICKEN_BITS2 0x01b4
+#define mmSEM_CHICKEN_BITS2_BASE_IDX 0
+#define mmSEM_MMHUB_CNTL 0x01b5
+#define mmSEM_MMHUB_CNTL_BASE_IDX 0
+#define mmSEM_REGISTER_LAST_PART1 0x01bf
+#define mmSEM_REGISTER_LAST_PART1_BASE_IDX 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h
new file mode 100644
index 000000000000..1ee3a2329ee4
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h
@@ -0,0 +1,1196 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _osssys_4_0_SH_MASK_HEADER
+#define _osssys_4_0_SH_MASK_HEADER
+
+
+// addressBlock: osssys_osssysdec
+//IH_VMID_0_LUT
+#define IH_VMID_0_LUT__PASID__SHIFT 0x0
+#define IH_VMID_0_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_1_LUT
+#define IH_VMID_1_LUT__PASID__SHIFT 0x0
+#define IH_VMID_1_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_2_LUT
+#define IH_VMID_2_LUT__PASID__SHIFT 0x0
+#define IH_VMID_2_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_3_LUT
+#define IH_VMID_3_LUT__PASID__SHIFT 0x0
+#define IH_VMID_3_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_4_LUT
+#define IH_VMID_4_LUT__PASID__SHIFT 0x0
+#define IH_VMID_4_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_5_LUT
+#define IH_VMID_5_LUT__PASID__SHIFT 0x0
+#define IH_VMID_5_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_6_LUT
+#define IH_VMID_6_LUT__PASID__SHIFT 0x0
+#define IH_VMID_6_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_7_LUT
+#define IH_VMID_7_LUT__PASID__SHIFT 0x0
+#define IH_VMID_7_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_8_LUT
+#define IH_VMID_8_LUT__PASID__SHIFT 0x0
+#define IH_VMID_8_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_9_LUT
+#define IH_VMID_9_LUT__PASID__SHIFT 0x0
+#define IH_VMID_9_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_10_LUT
+#define IH_VMID_10_LUT__PASID__SHIFT 0x0
+#define IH_VMID_10_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_11_LUT
+#define IH_VMID_11_LUT__PASID__SHIFT 0x0
+#define IH_VMID_11_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_12_LUT
+#define IH_VMID_12_LUT__PASID__SHIFT 0x0
+#define IH_VMID_12_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_13_LUT
+#define IH_VMID_13_LUT__PASID__SHIFT 0x0
+#define IH_VMID_13_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_14_LUT
+#define IH_VMID_14_LUT__PASID__SHIFT 0x0
+#define IH_VMID_14_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_15_LUT
+#define IH_VMID_15_LUT__PASID__SHIFT 0x0
+#define IH_VMID_15_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_0_LUT_MM
+#define IH_VMID_0_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_0_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_1_LUT_MM
+#define IH_VMID_1_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_1_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_2_LUT_MM
+#define IH_VMID_2_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_2_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_3_LUT_MM
+#define IH_VMID_3_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_3_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_4_LUT_MM
+#define IH_VMID_4_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_4_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_5_LUT_MM
+#define IH_VMID_5_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_5_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_6_LUT_MM
+#define IH_VMID_6_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_6_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_7_LUT_MM
+#define IH_VMID_7_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_7_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_8_LUT_MM
+#define IH_VMID_8_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_8_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_9_LUT_MM
+#define IH_VMID_9_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_9_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_10_LUT_MM
+#define IH_VMID_10_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_10_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_11_LUT_MM
+#define IH_VMID_11_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_11_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_12_LUT_MM
+#define IH_VMID_12_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_12_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_13_LUT_MM
+#define IH_VMID_13_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_13_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_14_LUT_MM
+#define IH_VMID_14_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_14_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_15_LUT_MM
+#define IH_VMID_15_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_15_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_COOKIE_0
+#define IH_COOKIE_0__CLIENT_ID__SHIFT 0x0
+#define IH_COOKIE_0__SOURCE_ID__SHIFT 0x8
+#define IH_COOKIE_0__RING_ID__SHIFT 0x10
+#define IH_COOKIE_0__VM_ID__SHIFT 0x18
+#define IH_COOKIE_0__RESERVED__SHIFT 0x1c
+#define IH_COOKIE_0__VMID_TYPE__SHIFT 0x1f
+#define IH_COOKIE_0__CLIENT_ID_MASK 0x000000FFL
+#define IH_COOKIE_0__SOURCE_ID_MASK 0x0000FF00L
+#define IH_COOKIE_0__RING_ID_MASK 0x00FF0000L
+#define IH_COOKIE_0__VM_ID_MASK 0x0F000000L
+#define IH_COOKIE_0__RESERVED_MASK 0x70000000L
+#define IH_COOKIE_0__VMID_TYPE_MASK 0x80000000L
+//IH_COOKIE_1
+#define IH_COOKIE_1__TIMESTAMP_31_0__SHIFT 0x0
+#define IH_COOKIE_1__TIMESTAMP_31_0_MASK 0xFFFFFFFFL
+//IH_COOKIE_2
+#define IH_COOKIE_2__TIMESTAMP_47_32__SHIFT 0x0
+#define IH_COOKIE_2__RESERVED__SHIFT 0x10
+#define IH_COOKIE_2__TIMESTAMP_SRC__SHIFT 0x1f
+#define IH_COOKIE_2__TIMESTAMP_47_32_MASK 0x0000FFFFL
+#define IH_COOKIE_2__RESERVED_MASK 0x7FFF0000L
+#define IH_COOKIE_2__TIMESTAMP_SRC_MASK 0x80000000L
+//IH_COOKIE_3
+#define IH_COOKIE_3__PAS_ID__SHIFT 0x0
+#define IH_COOKIE_3__RESERVED__SHIFT 0x10
+#define IH_COOKIE_3__PASID_SRC__SHIFT 0x1f
+#define IH_COOKIE_3__PAS_ID_MASK 0x0000FFFFL
+#define IH_COOKIE_3__RESERVED_MASK 0x7FFF0000L
+#define IH_COOKIE_3__PASID_SRC_MASK 0x80000000L
+//IH_COOKIE_4
+#define IH_COOKIE_4__CONTEXT_ID_31_0__SHIFT 0x0
+#define IH_COOKIE_4__CONTEXT_ID_31_0_MASK 0xFFFFFFFFL
+//IH_COOKIE_5
+#define IH_COOKIE_5__CONTEXT_ID_63_32__SHIFT 0x0
+#define IH_COOKIE_5__CONTEXT_ID_63_32_MASK 0xFFFFFFFFL
+//IH_COOKIE_6
+#define IH_COOKIE_6__CONTEXT_ID_95_64__SHIFT 0x0
+#define IH_COOKIE_6__CONTEXT_ID_95_64_MASK 0xFFFFFFFFL
+//IH_COOKIE_7
+#define IH_COOKIE_7__CONTEXT_ID_128_96__SHIFT 0x0
+#define IH_COOKIE_7__CONTEXT_ID_128_96_MASK 0xFFFFFFFFL
+//IH_REGISTER_LAST_PART0
+#define IH_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0
+#define IH_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL
+//SEM_REQ_INPUT_0
+#define SEM_REQ_INPUT_0__DATA__SHIFT 0x0
+#define SEM_REQ_INPUT_0__DATA_MASK 0xFFFFFFFFL
+//SEM_REQ_INPUT_1
+#define SEM_REQ_INPUT_1__DATA__SHIFT 0x0
+#define SEM_REQ_INPUT_1__DATA_MASK 0xFFFFFFFFL
+//SEM_REQ_INPUT_2
+#define SEM_REQ_INPUT_2__DATA__SHIFT 0x0
+#define SEM_REQ_INPUT_2__DATA_MASK 0xFFFFFFFFL
+//SEM_REQ_INPUT_3
+#define SEM_REQ_INPUT_3__DATA__SHIFT 0x0
+#define SEM_REQ_INPUT_3__DATA_MASK 0xFFFFFFFFL
+//SEM_REGISTER_LAST_PART0
+#define SEM_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0
+#define SEM_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL
+//IH_RB_CNTL
+#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7
+#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
+#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x9
+#define IH_RB_CNTL__FULL_DRAIN_CLEAR__SHIFT 0xa
+#define IH_RB_CNTL__RB_USED_INT_THRESHOLD__SHIFT 0xc
+#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10
+#define IH_RB_CNTL__ENABLE_INTR__SHIFT 0x11
+#define IH_RB_CNTL__MC_SWAP__SHIFT 0x12
+#define IH_RB_CNTL__MC_SNOOP__SHIFT 0x14
+#define IH_RB_CNTL__RPTR_REARM__SHIFT 0x15
+#define IH_RB_CNTL__MC_RO__SHIFT 0x16
+#define IH_RB_CNTL__MC_VMID__SHIFT 0x18
+#define IH_RB_CNTL__MC_SPACE__SHIFT 0x1c
+#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define IH_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x00000080L
+#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L
+#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L
+#define IH_RB_CNTL__FULL_DRAIN_CLEAR_MASK 0x00000400L
+#define IH_RB_CNTL__RB_USED_INT_THRESHOLD_MASK 0x0000F000L
+#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L
+#define IH_RB_CNTL__ENABLE_INTR_MASK 0x00020000L
+#define IH_RB_CNTL__MC_SWAP_MASK 0x000C0000L
+#define IH_RB_CNTL__MC_SNOOP_MASK 0x00100000L
+#define IH_RB_CNTL__RPTR_REARM_MASK 0x00200000L
+#define IH_RB_CNTL__MC_RO_MASK 0x00400000L
+#define IH_RB_CNTL__MC_VMID_MASK 0x0F000000L
+#define IH_RB_CNTL__MC_SPACE_MASK 0x70000000L
+#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
+//IH_RB_BASE
+#define IH_RB_BASE__ADDR__SHIFT 0x0
+#define IH_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//IH_RB_BASE_HI
+#define IH_RB_BASE_HI__ADDR__SHIFT 0x0
+#define IH_RB_BASE_HI__ADDR_MASK 0x000000FFL
+//IH_RB_RPTR
+#define IH_RB_RPTR__OFFSET__SHIFT 0x2
+#define IH_RB_RPTR__OFFSET_MASK 0x0003FFFCL
+//IH_RB_WPTR
+#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0
+#define IH_RB_WPTR__OFFSET__SHIFT 0x2
+#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12
+#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13
+#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L
+#define IH_RB_WPTR__OFFSET_MASK 0x0003FFFCL
+#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x00040000L
+#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x00080000L
+//IH_RB_WPTR_ADDR_HI
+#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x0000FFFFL
+//IH_RB_WPTR_ADDR_LO
+#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//IH_DOORBELL_RPTR
+#define IH_DOORBELL_RPTR__OFFSET__SHIFT 0x0
+#define IH_DOORBELL_RPTR__ENABLE__SHIFT 0x1c
+#define IH_DOORBELL_RPTR__OFFSET_MASK 0x03FFFFFFL
+#define IH_DOORBELL_RPTR__ENABLE_MASK 0x10000000L
+//IH_RB_CNTL_RING1
+#define IH_RB_CNTL_RING1__RB_ENABLE__SHIFT 0x0
+#define IH_RB_CNTL_RING1__RB_SIZE__SHIFT 0x1
+#define IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE__SHIFT 0x7
+#define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE__SHIFT 0x9
+#define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR__SHIFT 0xa
+#define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD__SHIFT 0xc
+#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE__SHIFT 0x10
+#define IH_RB_CNTL_RING1__MC_SWAP__SHIFT 0x12
+#define IH_RB_CNTL_RING1__MC_SNOOP__SHIFT 0x14
+#define IH_RB_CNTL_RING1__MC_RO__SHIFT 0x16
+#define IH_RB_CNTL_RING1__MC_VMID__SHIFT 0x18
+#define IH_RB_CNTL_RING1__MC_SPACE__SHIFT 0x1c
+#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define IH_RB_CNTL_RING1__RB_ENABLE_MASK 0x00000001L
+#define IH_RB_CNTL_RING1__RB_SIZE_MASK 0x0000003EL
+#define IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE_MASK 0x00000080L
+#define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L
+#define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR_MASK 0x00000400L
+#define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD_MASK 0x0000F000L
+#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L
+#define IH_RB_CNTL_RING1__MC_SWAP_MASK 0x000C0000L
+#define IH_RB_CNTL_RING1__MC_SNOOP_MASK 0x00100000L
+#define IH_RB_CNTL_RING1__MC_RO_MASK 0x00400000L
+#define IH_RB_CNTL_RING1__MC_VMID_MASK 0x0F000000L
+#define IH_RB_CNTL_RING1__MC_SPACE_MASK 0x70000000L
+#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
+//IH_RB_BASE_RING1
+#define IH_RB_BASE_RING1__ADDR__SHIFT 0x0
+#define IH_RB_BASE_RING1__ADDR_MASK 0xFFFFFFFFL
+//IH_RB_BASE_HI_RING1
+#define IH_RB_BASE_HI_RING1__ADDR__SHIFT 0x0
+#define IH_RB_BASE_HI_RING1__ADDR_MASK 0x000000FFL
+//IH_RB_RPTR_RING1
+#define IH_RB_RPTR_RING1__OFFSET__SHIFT 0x2
+#define IH_RB_RPTR_RING1__OFFSET_MASK 0x0003FFFCL
+//IH_RB_WPTR_RING1
+#define IH_RB_WPTR_RING1__RB_OVERFLOW__SHIFT 0x0
+#define IH_RB_WPTR_RING1__OFFSET__SHIFT 0x2
+#define IH_RB_WPTR_RING1__RB_LEFT_NONE__SHIFT 0x12
+#define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW__SHIFT 0x13
+#define IH_RB_WPTR_RING1__RB_OVERFLOW_MASK 0x00000001L
+#define IH_RB_WPTR_RING1__OFFSET_MASK 0x0003FFFCL
+#define IH_RB_WPTR_RING1__RB_LEFT_NONE_MASK 0x00040000L
+#define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW_MASK 0x00080000L
+//IH_DOORBELL_RPTR_RING1
+#define IH_DOORBELL_RPTR_RING1__OFFSET__SHIFT 0x0
+#define IH_DOORBELL_RPTR_RING1__ENABLE__SHIFT 0x1c
+#define IH_DOORBELL_RPTR_RING1__OFFSET_MASK 0x03FFFFFFL
+#define IH_DOORBELL_RPTR_RING1__ENABLE_MASK 0x10000000L
+//IH_RB_CNTL_RING2
+#define IH_RB_CNTL_RING2__RB_ENABLE__SHIFT 0x0
+#define IH_RB_CNTL_RING2__RB_SIZE__SHIFT 0x1
+#define IH_RB_CNTL_RING2__RB_GPU_TS_ENABLE__SHIFT 0x7
+#define IH_RB_CNTL_RING2__RB_FULL_DRAIN_ENABLE__SHIFT 0x9
+#define IH_RB_CNTL_RING2__FULL_DRAIN_CLEAR__SHIFT 0xa
+#define IH_RB_CNTL_RING2__RB_USED_INT_THRESHOLD__SHIFT 0xc
+#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_ENABLE__SHIFT 0x10
+#define IH_RB_CNTL_RING2__MC_SWAP__SHIFT 0x12
+#define IH_RB_CNTL_RING2__MC_SNOOP__SHIFT 0x14
+#define IH_RB_CNTL_RING2__MC_RO__SHIFT 0x16
+#define IH_RB_CNTL_RING2__MC_VMID__SHIFT 0x18
+#define IH_RB_CNTL_RING2__MC_SPACE__SHIFT 0x1c
+#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define IH_RB_CNTL_RING2__RB_ENABLE_MASK 0x00000001L
+#define IH_RB_CNTL_RING2__RB_SIZE_MASK 0x0000003EL
+#define IH_RB_CNTL_RING2__RB_GPU_TS_ENABLE_MASK 0x00000080L
+#define IH_RB_CNTL_RING2__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L
+#define IH_RB_CNTL_RING2__FULL_DRAIN_CLEAR_MASK 0x00000400L
+#define IH_RB_CNTL_RING2__RB_USED_INT_THRESHOLD_MASK 0x0000F000L
+#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L
+#define IH_RB_CNTL_RING2__MC_SWAP_MASK 0x000C0000L
+#define IH_RB_CNTL_RING2__MC_SNOOP_MASK 0x00100000L
+#define IH_RB_CNTL_RING2__MC_RO_MASK 0x00400000L
+#define IH_RB_CNTL_RING2__MC_VMID_MASK 0x0F000000L
+#define IH_RB_CNTL_RING2__MC_SPACE_MASK 0x70000000L
+#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
+//IH_RB_BASE_RING2
+#define IH_RB_BASE_RING2__ADDR__SHIFT 0x0
+#define IH_RB_BASE_RING2__ADDR_MASK 0xFFFFFFFFL
+//IH_RB_BASE_HI_RING2
+#define IH_RB_BASE_HI_RING2__ADDR__SHIFT 0x0
+#define IH_RB_BASE_HI_RING2__ADDR_MASK 0x000000FFL
+//IH_RB_RPTR_RING2
+#define IH_RB_RPTR_RING2__OFFSET__SHIFT 0x2
+#define IH_RB_RPTR_RING2__OFFSET_MASK 0x0003FFFCL
+//IH_RB_WPTR_RING2
+#define IH_RB_WPTR_RING2__RB_OVERFLOW__SHIFT 0x0
+#define IH_RB_WPTR_RING2__OFFSET__SHIFT 0x2
+#define IH_RB_WPTR_RING2__RB_LEFT_NONE__SHIFT 0x12
+#define IH_RB_WPTR_RING2__RB_MAY_OVERFLOW__SHIFT 0x13
+#define IH_RB_WPTR_RING2__RB_OVERFLOW_MASK 0x00000001L
+#define IH_RB_WPTR_RING2__OFFSET_MASK 0x0003FFFCL
+#define IH_RB_WPTR_RING2__RB_LEFT_NONE_MASK 0x00040000L
+#define IH_RB_WPTR_RING2__RB_MAY_OVERFLOW_MASK 0x00080000L
+//IH_DOORBELL_RPTR_RING2
+#define IH_DOORBELL_RPTR_RING2__OFFSET__SHIFT 0x0
+#define IH_DOORBELL_RPTR_RING2__ENABLE__SHIFT 0x1c
+#define IH_DOORBELL_RPTR_RING2__OFFSET_MASK 0x03FFFFFFL
+#define IH_DOORBELL_RPTR_RING2__ENABLE_MASK 0x10000000L
+//IH_VERSION
+#define IH_VERSION__MINVER__SHIFT 0x0
+#define IH_VERSION__MAJVER__SHIFT 0x8
+#define IH_VERSION__REV__SHIFT 0x10
+#define IH_VERSION__MINVER_MASK 0x0000007FL
+#define IH_VERSION__MAJVER_MASK 0x00007F00L
+#define IH_VERSION__REV_MASK 0x003F0000L
+//IH_CNTL
+#define IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x0
+#define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL__SHIFT 0x6
+#define IH_CNTL__IH_FIFO_HIGHWATER__SHIFT 0x8
+#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14
+#define IH_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x0000001FL
+#define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL_MASK 0x000000C0L
+#define IH_CNTL__IH_FIFO_HIGHWATER_MASK 0x00007F00L
+#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01F00000L
+//IH_CNTL2
+#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT__SHIFT 0x0
+#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE__SHIFT 0x8
+#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT_MASK 0x000000FFL
+#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE_MASK 0x00000100L
+//IH_STATUS
+#define IH_STATUS__IDLE__SHIFT 0x0
+#define IH_STATUS__INPUT_IDLE__SHIFT 0x1
+#define IH_STATUS__BUFFER_IDLE__SHIFT 0x2
+#define IH_STATUS__RB_FULL__SHIFT 0x3
+#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4
+#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5
+#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6
+#define IH_STATUS__MC_WR_STALL__SHIFT 0x7
+#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8
+#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9
+#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa
+#define IH_STATUS__SWITCH_READY__SHIFT 0xb
+#define IH_STATUS__RB1_FULL__SHIFT 0xc
+#define IH_STATUS__RB1_FULL_DRAIN__SHIFT 0xd
+#define IH_STATUS__RB1_OVERFLOW__SHIFT 0xe
+#define IH_STATUS__RB2_FULL__SHIFT 0xf
+#define IH_STATUS__RB2_FULL_DRAIN__SHIFT 0x10
+#define IH_STATUS__RB2_OVERFLOW__SHIFT 0x11
+#define IH_STATUS__SELF_INT_GEN_IDLE__SHIFT 0x12
+#define IH_STATUS__IDLE_MASK 0x00000001L
+#define IH_STATUS__INPUT_IDLE_MASK 0x00000002L
+#define IH_STATUS__BUFFER_IDLE_MASK 0x00000004L
+#define IH_STATUS__RB_FULL_MASK 0x00000008L
+#define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L
+#define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L
+#define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L
+#define IH_STATUS__MC_WR_STALL_MASK 0x00000080L
+#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L
+#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L
+#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L
+#define IH_STATUS__SWITCH_READY_MASK 0x00000800L
+#define IH_STATUS__RB1_FULL_MASK 0x00001000L
+#define IH_STATUS__RB1_FULL_DRAIN_MASK 0x00002000L
+#define IH_STATUS__RB1_OVERFLOW_MASK 0x00004000L
+#define IH_STATUS__RB2_FULL_MASK 0x00008000L
+#define IH_STATUS__RB2_FULL_DRAIN_MASK 0x00010000L
+#define IH_STATUS__RB2_OVERFLOW_MASK 0x00020000L
+#define IH_STATUS__SELF_INT_GEN_IDLE_MASK 0x00040000L
+//IH_PERFMON_CNTL
+#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0
+#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1
+#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x10
+#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x11
+#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0x12
+#define IH_PERFMON_CNTL__ENABLE0_MASK 0x00000001L
+#define IH_PERFMON_CNTL__CLEAR0_MASK 0x00000002L
+#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x000007FCL
+#define IH_PERFMON_CNTL__ENABLE1_MASK 0x00010000L
+#define IH_PERFMON_CNTL__CLEAR1_MASK 0x00020000L
+#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0x07FC0000L
+//IH_PERFCOUNTER0_RESULT
+#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
+//IH_PERFCOUNTER1_RESULT
+#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
+//IH_DSM_MATCH_VALUE_BIT_31_0
+#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0
+#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xFFFFFFFFL
+//IH_DSM_MATCH_VALUE_BIT_63_32
+#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0
+#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xFFFFFFFFL
+//IH_DSM_MATCH_VALUE_BIT_95_64
+#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0
+#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xFFFFFFFFL
+//IH_DSM_MATCH_FIELD_CONTROL
+#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0
+#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x1
+#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2
+#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3
+#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4
+#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5
+#define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN__SHIFT 0x6
+#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x00000001L
+#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x00000002L
+#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x00000004L
+#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x00000008L
+#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x00000010L
+#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x00000020L
+#define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN_MASK 0x00000040L
+//IH_DSM_MATCH_DATA_CONTROL
+#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0
+#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0x0FFFFFFFL
+//IH_DSM_MATCH_FCN_ID
+#define IH_DSM_MATCH_FCN_ID__PF_VF__SHIFT 0x0
+#define IH_DSM_MATCH_FCN_ID__VF_ID__SHIFT 0x1
+#define IH_DSM_MATCH_FCN_ID__PF_VF_MASK 0x00000001L
+#define IH_DSM_MATCH_FCN_ID__VF_ID_MASK 0x0000001EL
+//IH_LIMIT_INT_RATE_CNTL
+#define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE__SHIFT 0x0
+#define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL__SHIFT 0x1
+#define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD__SHIFT 0x5
+#define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY__SHIFT 0x11
+#define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT__SHIFT 0x15
+#define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE_MASK 0x00000001L
+#define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL_MASK 0x0000001EL
+#define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD_MASK 0x0000FFE0L
+#define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY_MASK 0x001E0000L
+#define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT_MASK 0xFFE00000L
+//IH_VF_RB_STATUS
+#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0
+#define IH_VF_RB_STATUS__RB_OVERFLOW_VF__SHIFT 0x10
+#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL
+#define IH_VF_RB_STATUS__RB_OVERFLOW_VF_MASK 0xFFFF0000L
+//IH_VF_RB_STATUS2
+#define IH_VF_RB_STATUS2__RB_FULL_VF__SHIFT 0x0
+#define IH_VF_RB_STATUS2__BIF_INTERRUPT_LINE_VF__SHIFT 0x10
+#define IH_VF_RB_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL
+#define IH_VF_RB_STATUS2__BIF_INTERRUPT_LINE_VF_MASK 0xFFFF0000L
+//IH_VF_RB1_STATUS
+#define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0
+#define IH_VF_RB1_STATUS__RB_OVERFLOW_VF__SHIFT 0x10
+#define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL
+#define IH_VF_RB1_STATUS__RB_OVERFLOW_VF_MASK 0xFFFF0000L
+//IH_VF_RB1_STATUS2
+#define IH_VF_RB1_STATUS2__RB_FULL_VF__SHIFT 0x0
+#define IH_VF_RB1_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL
+//IH_VF_RB2_STATUS
+#define IH_VF_RB2_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0
+#define IH_VF_RB2_STATUS__RB_OVERFLOW_VF__SHIFT 0x10
+#define IH_VF_RB2_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL
+#define IH_VF_RB2_STATUS__RB_OVERFLOW_VF_MASK 0xFFFF0000L
+//IH_VF_RB2_STATUS2
+#define IH_VF_RB2_STATUS2__RB_FULL_VF__SHIFT 0x0
+#define IH_VF_RB2_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL
+//IH_INT_FLOOD_CNTL
+#define IH_INT_FLOOD_CNTL__HIGHWATER__SHIFT 0x0
+#define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE__SHIFT 0x3
+#define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS__SHIFT 0x4
+#define IH_INT_FLOOD_CNTL__HIGHWATER_MASK 0x00000007L
+#define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE_MASK 0x00000008L
+#define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS_MASK 0x00000010L
+//IH_RB0_INT_FLOOD_STATUS
+#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0
+#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f
+#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL
+#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L
+//IH_RB1_INT_FLOOD_STATUS
+#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0
+#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f
+#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL
+#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L
+//IH_RB2_INT_FLOOD_STATUS
+#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0
+#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f
+#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL
+#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L
+//IH_INT_FLOOD_STATUS
+#define IH_INT_FLOOD_STATUS__INT_DROP_CNT__SHIFT 0x0
+#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID__SHIFT 0x8
+#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID__SHIFT 0x10
+#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID__SHIFT 0x18
+#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF__SHIFT 0x1c
+#define IH_INT_FLOOD_STATUS__INT_DROPPED__SHIFT 0x1e
+#define IH_INT_FLOOD_STATUS__INT_DROP_CNT_MASK 0x000000FFL
+#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID_MASK 0x0000FF00L
+#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID_MASK 0x00FF0000L
+#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID_MASK 0x0F000000L
+#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_MASK 0x10000000L
+#define IH_INT_FLOOD_STATUS__INT_DROPPED_MASK 0x40000000L
+//IH_STORM_CLIENT_LIST_CNTL
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT__SHIFT 0x1
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT__SHIFT 0x2
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT__SHIFT 0x3
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT__SHIFT 0x4
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT__SHIFT 0x5
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT__SHIFT 0x6
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT__SHIFT 0x7
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT__SHIFT 0x8
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT__SHIFT 0x9
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT__SHIFT 0xa
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT__SHIFT 0xb
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT__SHIFT 0xc
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT__SHIFT 0xd
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT__SHIFT 0xe
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT__SHIFT 0xf
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT__SHIFT 0x10
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT__SHIFT 0x11
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT__SHIFT 0x12
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT__SHIFT 0x13
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT__SHIFT 0x14
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT__SHIFT 0x15
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT__SHIFT 0x16
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT__SHIFT 0x17
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT__SHIFT 0x18
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT__SHIFT 0x19
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT__SHIFT 0x1a
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT__SHIFT 0x1b
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT__SHIFT 0x1c
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT__SHIFT 0x1d
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT__SHIFT 0x1e
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT__SHIFT 0x1f
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT_MASK 0x00000002L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT_MASK 0x00000004L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT_MASK 0x00000008L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT_MASK 0x00000010L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT_MASK 0x00000020L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT_MASK 0x00000040L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT_MASK 0x00000080L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT_MASK 0x00000100L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT_MASK 0x00000200L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT_MASK 0x00000400L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT_MASK 0x00000800L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT_MASK 0x00001000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT_MASK 0x00002000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT_MASK 0x00004000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT_MASK 0x00008000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT_MASK 0x00010000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT_MASK 0x00020000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT_MASK 0x00040000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT_MASK 0x00080000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT_MASK 0x00100000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT_MASK 0x00200000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT_MASK 0x00400000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT_MASK 0x00800000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT_MASK 0x01000000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT_MASK 0x02000000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT_MASK 0x04000000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT_MASK 0x08000000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT_MASK 0x10000000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT_MASK 0x20000000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT_MASK 0x40000000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT_MASK 0x80000000L
+//IH_CLK_CTRL
+#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE__SHIFT 0x1b
+#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE__SHIFT 0x1c
+#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE__SHIFT 0x1d
+#define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1e
+#define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f
+#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE_MASK 0x08000000L
+#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE_MASK 0x10000000L
+#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE_MASK 0x20000000L
+#define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE_MASK 0x40000000L
+#define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L
+//IH_INT_FLAGS
+#define IH_INT_FLAGS__CLIENT_0_FLAG__SHIFT 0x0
+#define IH_INT_FLAGS__CLIENT_1_FLAG__SHIFT 0x1
+#define IH_INT_FLAGS__CLIENT_2_FLAG__SHIFT 0x2
+#define IH_INT_FLAGS__CLIENT_3_FLAG__SHIFT 0x3
+#define IH_INT_FLAGS__CLIENT_4_FLAG__SHIFT 0x4
+#define IH_INT_FLAGS__CLIENT_5_FLAG__SHIFT 0x5
+#define IH_INT_FLAGS__CLIENT_6_FLAG__SHIFT 0x6
+#define IH_INT_FLAGS__CLIENT_7_FLAG__SHIFT 0x7
+#define IH_INT_FLAGS__CLIENT_8_FLAG__SHIFT 0x8
+#define IH_INT_FLAGS__CLIENT_9_FLAG__SHIFT 0x9
+#define IH_INT_FLAGS__CLIENT_10_FLAG__SHIFT 0xa
+#define IH_INT_FLAGS__CLIENT_11_FLAG__SHIFT 0xb
+#define IH_INT_FLAGS__CLIENT_12_FLAG__SHIFT 0xc
+#define IH_INT_FLAGS__CLIENT_13_FLAG__SHIFT 0xd
+#define IH_INT_FLAGS__CLIENT_14_FLAG__SHIFT 0xe
+#define IH_INT_FLAGS__CLIENT_15_FLAG__SHIFT 0xf
+#define IH_INT_FLAGS__CLIENT_16_FLAG__SHIFT 0x10
+#define IH_INT_FLAGS__CLIENT_17_FLAG__SHIFT 0x11
+#define IH_INT_FLAGS__CLIENT_18_FLAG__SHIFT 0x12
+#define IH_INT_FLAGS__CLIENT_19_FLAG__SHIFT 0x13
+#define IH_INT_FLAGS__CLIENT_20_FLAG__SHIFT 0x14
+#define IH_INT_FLAGS__CLIENT_21_FLAG__SHIFT 0x15
+#define IH_INT_FLAGS__CLIENT_22_FLAG__SHIFT 0x16
+#define IH_INT_FLAGS__CLIENT_23_FLAG__SHIFT 0x17
+#define IH_INT_FLAGS__CLIENT_24_FLAG__SHIFT 0x18
+#define IH_INT_FLAGS__CLIENT_25_FLAG__SHIFT 0x19
+#define IH_INT_FLAGS__CLIENT_26_FLAG__SHIFT 0x1a
+#define IH_INT_FLAGS__CLIENT_27_FLAG__SHIFT 0x1b
+#define IH_INT_FLAGS__CLIENT_28_FLAG__SHIFT 0x1c
+#define IH_INT_FLAGS__CLIENT_29_FLAG__SHIFT 0x1d
+#define IH_INT_FLAGS__CLIENT_30_FLAG__SHIFT 0x1e
+#define IH_INT_FLAGS__CLIENT_31_FLAG__SHIFT 0x1f
+#define IH_INT_FLAGS__CLIENT_0_FLAG_MASK 0x00000001L
+#define IH_INT_FLAGS__CLIENT_1_FLAG_MASK 0x00000002L
+#define IH_INT_FLAGS__CLIENT_2_FLAG_MASK 0x00000004L
+#define IH_INT_FLAGS__CLIENT_3_FLAG_MASK 0x00000008L
+#define IH_INT_FLAGS__CLIENT_4_FLAG_MASK 0x00000010L
+#define IH_INT_FLAGS__CLIENT_5_FLAG_MASK 0x00000020L
+#define IH_INT_FLAGS__CLIENT_6_FLAG_MASK 0x00000040L
+#define IH_INT_FLAGS__CLIENT_7_FLAG_MASK 0x00000080L
+#define IH_INT_FLAGS__CLIENT_8_FLAG_MASK 0x00000100L
+#define IH_INT_FLAGS__CLIENT_9_FLAG_MASK 0x00000200L
+#define IH_INT_FLAGS__CLIENT_10_FLAG_MASK 0x00000400L
+#define IH_INT_FLAGS__CLIENT_11_FLAG_MASK 0x00000800L
+#define IH_INT_FLAGS__CLIENT_12_FLAG_MASK 0x00001000L
+#define IH_INT_FLAGS__CLIENT_13_FLAG_MASK 0x00002000L
+#define IH_INT_FLAGS__CLIENT_14_FLAG_MASK 0x00004000L
+#define IH_INT_FLAGS__CLIENT_15_FLAG_MASK 0x00008000L
+#define IH_INT_FLAGS__CLIENT_16_FLAG_MASK 0x00010000L
+#define IH_INT_FLAGS__CLIENT_17_FLAG_MASK 0x00020000L
+#define IH_INT_FLAGS__CLIENT_18_FLAG_MASK 0x00040000L
+#define IH_INT_FLAGS__CLIENT_19_FLAG_MASK 0x00080000L
+#define IH_INT_FLAGS__CLIENT_20_FLAG_MASK 0x00100000L
+#define IH_INT_FLAGS__CLIENT_21_FLAG_MASK 0x00200000L
+#define IH_INT_FLAGS__CLIENT_22_FLAG_MASK 0x00400000L
+#define IH_INT_FLAGS__CLIENT_23_FLAG_MASK 0x00800000L
+#define IH_INT_FLAGS__CLIENT_24_FLAG_MASK 0x01000000L
+#define IH_INT_FLAGS__CLIENT_25_FLAG_MASK 0x02000000L
+#define IH_INT_FLAGS__CLIENT_26_FLAG_MASK 0x04000000L
+#define IH_INT_FLAGS__CLIENT_27_FLAG_MASK 0x08000000L
+#define IH_INT_FLAGS__CLIENT_28_FLAG_MASK 0x10000000L
+#define IH_INT_FLAGS__CLIENT_29_FLAG_MASK 0x20000000L
+#define IH_INT_FLAGS__CLIENT_30_FLAG_MASK 0x40000000L
+#define IH_INT_FLAGS__CLIENT_31_FLAG_MASK 0x80000000L
+//IH_LAST_INT_INFO0
+#define IH_LAST_INT_INFO0__CLIENT_ID__SHIFT 0x0
+#define IH_LAST_INT_INFO0__SOURCE_ID__SHIFT 0x8
+#define IH_LAST_INT_INFO0__RING_ID__SHIFT 0x10
+#define IH_LAST_INT_INFO0__VM_ID__SHIFT 0x18
+#define IH_LAST_INT_INFO0__VMID_TYPE__SHIFT 0x1f
+#define IH_LAST_INT_INFO0__CLIENT_ID_MASK 0x000000FFL
+#define IH_LAST_INT_INFO0__SOURCE_ID_MASK 0x0000FF00L
+#define IH_LAST_INT_INFO0__RING_ID_MASK 0x00FF0000L
+#define IH_LAST_INT_INFO0__VM_ID_MASK 0x0F000000L
+#define IH_LAST_INT_INFO0__VMID_TYPE_MASK 0x80000000L
+//IH_LAST_INT_INFO1
+#define IH_LAST_INT_INFO1__CONTEXT_ID__SHIFT 0x0
+#define IH_LAST_INT_INFO1__CONTEXT_ID_MASK 0xFFFFFFFFL
+//IH_LAST_INT_INFO2
+#define IH_LAST_INT_INFO2__PAS_ID__SHIFT 0x0
+#define IH_LAST_INT_INFO2__VF_ID__SHIFT 0x10
+#define IH_LAST_INT_INFO2__VF__SHIFT 0x14
+#define IH_LAST_INT_INFO2__PAS_ID_MASK 0x0000FFFFL
+#define IH_LAST_INT_INFO2__VF_ID_MASK 0x000F0000L
+#define IH_LAST_INT_INFO2__VF_MASK 0x00100000L
+//IH_SCRATCH
+#define IH_SCRATCH__DATA__SHIFT 0x0
+#define IH_SCRATCH__DATA_MASK 0xFFFFFFFFL
+//IH_CLIENT_CREDIT_ERROR
+#define IH_CLIENT_CREDIT_ERROR__CLEAR__SHIFT 0x0
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR__SHIFT 0x1
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR__SHIFT 0x2
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR__SHIFT 0x3
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR__SHIFT 0x4
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR__SHIFT 0x5
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR__SHIFT 0x6
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR__SHIFT 0x7
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR__SHIFT 0x8
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR__SHIFT 0x9
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR__SHIFT 0xa
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR__SHIFT 0xb
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR__SHIFT 0xc
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR__SHIFT 0xd
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR__SHIFT 0xe
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR__SHIFT 0xf
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR__SHIFT 0x10
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR__SHIFT 0x11
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR__SHIFT 0x12
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR__SHIFT 0x13
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR__SHIFT 0x14
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR__SHIFT 0x15
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR__SHIFT 0x16
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR__SHIFT 0x17
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR__SHIFT 0x18
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR__SHIFT 0x19
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR__SHIFT 0x1a
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR__SHIFT 0x1b
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR__SHIFT 0x1c
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR__SHIFT 0x1d
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR__SHIFT 0x1e
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR__SHIFT 0x1f
+#define IH_CLIENT_CREDIT_ERROR__CLEAR_MASK 0x00000001L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR_MASK 0x00000002L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR_MASK 0x00000004L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR_MASK 0x00000008L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR_MASK 0x00000010L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR_MASK 0x00000020L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR_MASK 0x00000040L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR_MASK 0x00000080L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR_MASK 0x00000100L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR_MASK 0x00000200L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR_MASK 0x00000400L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR_MASK 0x00000800L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR_MASK 0x00001000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR_MASK 0x00002000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR_MASK 0x00004000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR_MASK 0x00008000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR_MASK 0x00010000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR_MASK 0x00020000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR_MASK 0x00040000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR_MASK 0x00080000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR_MASK 0x00100000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR_MASK 0x00200000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR_MASK 0x00400000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR_MASK 0x00800000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR_MASK 0x01000000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR_MASK 0x02000000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR_MASK 0x04000000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR_MASK 0x08000000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR_MASK 0x10000000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR_MASK 0x20000000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR_MASK 0x40000000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR_MASK 0x80000000L
+//IH_GPU_IOV_VIOLATION_LOG
+#define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
+#define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1
+#define IH_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2
+#define IH_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12
+#define IH_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13
+#define IH_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x14
+#define IH_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18
+#define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
+#define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L
+#define IH_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL
+#define IH_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L
+#define IH_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L
+#define IH_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x00F00000L
+#define IH_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L
+//IH_COOKIE_REC_VIOLATION_LOG
+#define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
+#define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID__SHIFT 0x10
+#define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18
+#define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
+#define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID_MASK 0x00FF0000L
+#define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L
+//IH_CREDIT_STATUS
+#define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED__SHIFT 0x1
+#define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED__SHIFT 0x2
+#define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED__SHIFT 0x3
+#define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED__SHIFT 0x4
+#define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED__SHIFT 0x5
+#define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED__SHIFT 0x6
+#define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED__SHIFT 0x7
+#define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED__SHIFT 0x8
+#define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED__SHIFT 0x9
+#define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED__SHIFT 0xa
+#define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED__SHIFT 0xb
+#define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED__SHIFT 0xc
+#define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED__SHIFT 0xd
+#define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED__SHIFT 0xe
+#define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED__SHIFT 0xf
+#define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED__SHIFT 0x10
+#define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED__SHIFT 0x11
+#define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED__SHIFT 0x12
+#define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED__SHIFT 0x13
+#define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED__SHIFT 0x14
+#define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED__SHIFT 0x15
+#define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED__SHIFT 0x16
+#define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED__SHIFT 0x17
+#define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED__SHIFT 0x18
+#define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED__SHIFT 0x19
+#define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED__SHIFT 0x1a
+#define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED__SHIFT 0x1b
+#define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED__SHIFT 0x1c
+#define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED__SHIFT 0x1d
+#define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED__SHIFT 0x1e
+#define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED__SHIFT 0x1f
+#define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED_MASK 0x00000002L
+#define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED_MASK 0x00000004L
+#define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED_MASK 0x00000008L
+#define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED_MASK 0x00000010L
+#define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED_MASK 0x00000020L
+#define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED_MASK 0x00000040L
+#define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED_MASK 0x00000080L
+#define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED_MASK 0x00000100L
+#define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED_MASK 0x00000200L
+#define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED_MASK 0x00000400L
+#define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED_MASK 0x00000800L
+#define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED_MASK 0x00001000L
+#define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED_MASK 0x00002000L
+#define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED_MASK 0x00004000L
+#define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED_MASK 0x00008000L
+#define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED_MASK 0x00010000L
+#define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED_MASK 0x00020000L
+#define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED_MASK 0x00040000L
+#define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED_MASK 0x00080000L
+#define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED_MASK 0x00100000L
+#define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED_MASK 0x00200000L
+#define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED_MASK 0x00400000L
+#define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED_MASK 0x00800000L
+#define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED_MASK 0x01000000L
+#define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED_MASK 0x02000000L
+#define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED_MASK 0x04000000L
+#define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED_MASK 0x08000000L
+#define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED_MASK 0x10000000L
+#define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED_MASK 0x20000000L
+#define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED_MASK 0x40000000L
+#define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED_MASK 0x80000000L
+//IH_MMHUB_ERROR
+#define IH_MMHUB_ERROR__IH_BRESP_01__SHIFT 0x1
+#define IH_MMHUB_ERROR__IH_BRESP_10__SHIFT 0x2
+#define IH_MMHUB_ERROR__IH_BRESP_11__SHIFT 0x3
+#define IH_MMHUB_ERROR__IH_BUSER_NACK_01__SHIFT 0x5
+#define IH_MMHUB_ERROR__IH_BUSER_NACK_10__SHIFT 0x6
+#define IH_MMHUB_ERROR__IH_BUSER_NACK_11__SHIFT 0x7
+#define IH_MMHUB_ERROR__IH_BRESP_01_MASK 0x00000002L
+#define IH_MMHUB_ERROR__IH_BRESP_10_MASK 0x00000004L
+#define IH_MMHUB_ERROR__IH_BRESP_11_MASK 0x00000008L
+#define IH_MMHUB_ERROR__IH_BUSER_NACK_01_MASK 0x00000020L
+#define IH_MMHUB_ERROR__IH_BUSER_NACK_10_MASK 0x00000040L
+#define IH_MMHUB_ERROR__IH_BUSER_NACK_11_MASK 0x00000080L
+//IH_REGISTER_LAST_PART2
+#define IH_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0
+#define IH_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL
+//SEM_CLK_CTRL
+#define SEM_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SEM_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SEM_CLK_CTRL__RESERVED__SHIFT 0xc
+#define SEM_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define SEM_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define SEM_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define SEM_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define SEM_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define SEM_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define SEM_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define SEM_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SEM_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define SEM_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define SEM_CLK_CTRL__RESERVED_MASK 0x00FFF000L
+#define SEM_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define SEM_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define SEM_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define SEM_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define SEM_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define SEM_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define SEM_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define SEM_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//SEM_UTC_CREDIT
+#define SEM_UTC_CREDIT__UTCL2_CREDIT__SHIFT 0x0
+#define SEM_UTC_CREDIT__WATERMARK__SHIFT 0x8
+#define SEM_UTC_CREDIT__UTCL2_CREDIT_MASK 0x0000001FL
+#define SEM_UTC_CREDIT__WATERMARK_MASK 0x00000F00L
+//SEM_UTC_CONFIG
+#define SEM_UTC_CONFIG__USE_MTYPE__SHIFT 0x0
+#define SEM_UTC_CONFIG__FORCE_SNOOP__SHIFT 0x3
+#define SEM_UTC_CONFIG__FORCE_GCC__SHIFT 0x4
+#define SEM_UTC_CONFIG__USE_PT_SNOOP__SHIFT 0x5
+#define SEM_UTC_CONFIG__USE_MTYPE_MASK 0x00000007L
+#define SEM_UTC_CONFIG__FORCE_SNOOP_MASK 0x00000008L
+#define SEM_UTC_CONFIG__FORCE_GCC_MASK 0x00000010L
+#define SEM_UTC_CONFIG__USE_PT_SNOOP_MASK 0x00000020L
+//SEM_UTCL2_TRAN_EN_LUT
+#define SEM_UTCL2_TRAN_EN_LUT__SDMA0_UTCL2_EN__SHIFT 0x0
+#define SEM_UTCL2_TRAN_EN_LUT__SDMA1_UTCL2_EN__SHIFT 0x1
+#define SEM_UTCL2_TRAN_EN_LUT__UVD_UTCL2_EN__SHIFT 0x2
+#define SEM_UTCL2_TRAN_EN_LUT__VCE0_UTCL2_EN__SHIFT 0x3
+#define SEM_UTCL2_TRAN_EN_LUT__ACP_UTCL2_EN__SHIFT 0x4
+#define SEM_UTCL2_TRAN_EN_LUT__ISP_UTCL2_EN__SHIFT 0x5
+#define SEM_UTCL2_TRAN_EN_LUT__VCE1_UTCL2_EN__SHIFT 0x6
+#define SEM_UTCL2_TRAN_EN_LUT__VP8_UTCL2_EN__SHIFT 0x7
+#define SEM_UTCL2_TRAN_EN_LUT__RESERVED__SHIFT 0x8
+#define SEM_UTCL2_TRAN_EN_LUT__CP_UTCL2_EN__SHIFT 0x1f
+#define SEM_UTCL2_TRAN_EN_LUT__SDMA0_UTCL2_EN_MASK 0x00000001L
+#define SEM_UTCL2_TRAN_EN_LUT__SDMA1_UTCL2_EN_MASK 0x00000002L
+#define SEM_UTCL2_TRAN_EN_LUT__UVD_UTCL2_EN_MASK 0x00000004L
+#define SEM_UTCL2_TRAN_EN_LUT__VCE0_UTCL2_EN_MASK 0x00000008L
+#define SEM_UTCL2_TRAN_EN_LUT__ACP_UTCL2_EN_MASK 0x00000010L
+#define SEM_UTCL2_TRAN_EN_LUT__ISP_UTCL2_EN_MASK 0x00000020L
+#define SEM_UTCL2_TRAN_EN_LUT__VCE1_UTCL2_EN_MASK 0x00000040L
+#define SEM_UTCL2_TRAN_EN_LUT__VP8_UTCL2_EN_MASK 0x00000080L
+#define SEM_UTCL2_TRAN_EN_LUT__RESERVED_MASK 0x7FFFFF00L
+#define SEM_UTCL2_TRAN_EN_LUT__CP_UTCL2_EN_MASK 0x80000000L
+//SEM_MCIF_CONFIG
+#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0
+#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2
+#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8
+#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x00000003L
+#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0x000000FCL
+#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x00003F00L
+//SEM_PERFMON_CNTL
+#define SEM_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
+#define SEM_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
+#define SEM_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define SEM_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
+#define SEM_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb
+#define SEM_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
+#define SEM_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L
+#define SEM_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L
+#define SEM_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL
+#define SEM_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L
+#define SEM_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L
+#define SEM_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L
+//SEM_PERFCOUNTER0_RESULT
+#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
+//SEM_PERFCOUNTER1_RESULT
+#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
+//SEM_STATUS
+#define SEM_STATUS__SEM_IDLE__SHIFT 0x0
+#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1
+#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2
+#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3
+#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4
+#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5
+#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6
+#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7
+#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8
+#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9
+#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa
+#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb
+#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc
+#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd
+#define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe
+#define SEM_STATUS__ATC_REQ_PENDING__SHIFT 0xf
+#define SEM_STATUS__OUTSTANDING_CLEAN__SHIFT 0x10
+#define SEM_STATUS__INVREQ_FLUSH_VF_MISMATCH__SHIFT 0x11
+#define SEM_STATUS__INVREQ_NONFLUSH_VF_MISMATCH__SHIFT 0x12
+#define SEM_STATUS__INVREQ_CNT_IDLE__SHIFT 0x13
+#define SEM_STATUS__ENTRYLIST_IDLE__SHIFT 0x14
+#define SEM_STATUS__MIF_IDLE__SHIFT 0x15
+#define SEM_STATUS__REGISTER_IDLE__SHIFT 0x16
+#define SEM_STATUS__ATCL2_INVREQ_IDLE__SHIFT 0x17
+#define SEM_STATUS__SWITCH_READY__SHIFT 0x1f
+#define SEM_STATUS__SEM_IDLE_MASK 0x00000001L
+#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x00000002L
+#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x00000004L
+#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x00000008L
+#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x00000010L
+#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x00000020L
+#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x00000040L
+#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x00000080L
+#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x00000100L
+#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x00000200L
+#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x00000400L
+#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x00000800L
+#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x00001000L
+#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x00002000L
+#define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x00004000L
+#define SEM_STATUS__ATC_REQ_PENDING_MASK 0x00008000L
+#define SEM_STATUS__OUTSTANDING_CLEAN_MASK 0x00010000L
+#define SEM_STATUS__INVREQ_FLUSH_VF_MISMATCH_MASK 0x00020000L
+#define SEM_STATUS__INVREQ_NONFLUSH_VF_MISMATCH_MASK 0x00040000L
+#define SEM_STATUS__INVREQ_CNT_IDLE_MASK 0x00080000L
+#define SEM_STATUS__ENTRYLIST_IDLE_MASK 0x00100000L
+#define SEM_STATUS__MIF_IDLE_MASK 0x00200000L
+#define SEM_STATUS__REGISTER_IDLE_MASK 0x00400000L
+#define SEM_STATUS__ATCL2_INVREQ_IDLE_MASK 0x00800000L
+#define SEM_STATUS__SWITCH_READY_MASK 0x80000000L
+//SEM_MAILBOX_CLIENTCONFIG
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc
+#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12
+#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x00000007L
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x00000038L
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x000001C0L
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0x00000E00L
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x00007000L
+#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x00038000L
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x001C0000L
+#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0x00E00000L
+//SEM_MAILBOX
+#define SEM_MAILBOX__HOSTPORT__SHIFT 0x0
+#define SEM_MAILBOX__RESERVED__SHIFT 0x10
+#define SEM_MAILBOX__HOSTPORT_MASK 0x0000FFFFL
+#define SEM_MAILBOX__RESERVED_MASK 0xFFFF0000L
+//SEM_MAILBOX_CONTROL
+#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x0
+#define SEM_MAILBOX_CONTROL__RESERVED__SHIFT 0x10
+#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0x0000FFFFL
+#define SEM_MAILBOX_CONTROL__RESERVED_MASK 0xFFFF0000L
+//SEM_CHICKEN_BITS
+#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0
+#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1
+#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2
+#define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3
+#define SEM_CHICKEN_BITS__PHY_TRAN_EN__SHIFT 0x6
+#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN__SHIFT 0x7
+#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8
+#define SEM_CHICKEN_BITS__OUTSTANDING_CLEAN_COUNTER_INDEX__SHIFT 0xa
+#define SEM_CHICKEN_BITS__ATCL2_BUS_ID__SHIFT 0xc
+#define SEM_CHICKEN_BITS__ATOMIC_EN__SHIFT 0xe
+#define SEM_CHICKEN_BITS__EXTERNAL_ATOMIC_CHECK__SHIFT 0xf
+#define SEM_CHICKEN_BITS__CLEAR_MAILBOX__SHIFT 0x10
+#define SEM_CHICKEN_BITS__INVACK_AFTER_OUTSTANDING_CLEAN__SHIFT 0x12
+#define SEM_CHICKEN_BITS__UTC_TAG_CONFLICT_CHECK__SHIFT 0x13
+#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x00000001L
+#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x00000002L
+#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x00000004L
+#define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x00000018L
+#define SEM_CHICKEN_BITS__PHY_TRAN_EN_MASK 0x00000040L
+#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN_MASK 0x00000080L
+#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0x00000300L
+#define SEM_CHICKEN_BITS__OUTSTANDING_CLEAN_COUNTER_INDEX_MASK 0x00000C00L
+#define SEM_CHICKEN_BITS__ATCL2_BUS_ID_MASK 0x00003000L
+#define SEM_CHICKEN_BITS__ATOMIC_EN_MASK 0x00004000L
+#define SEM_CHICKEN_BITS__EXTERNAL_ATOMIC_CHECK_MASK 0x00008000L
+#define SEM_CHICKEN_BITS__CLEAR_MAILBOX_MASK 0x00030000L
+#define SEM_CHICKEN_BITS__INVACK_AFTER_OUTSTANDING_CLEAN_MASK 0x00040000L
+#define SEM_CHICKEN_BITS__UTC_TAG_CONFLICT_CHECK_MASK 0x00080000L
+//SEM_MAILBOX_CLIENTCONFIG_EXTRA
+#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0
+#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x0000000FL
+//SEM_GPU_IOV_VIOLATION_LOG
+#define SEM_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
+#define SEM_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1
+#define SEM_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2
+#define SEM_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12
+#define SEM_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13
+#define SEM_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x14
+#define SEM_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18
+#define SEM_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
+#define SEM_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L
+#define SEM_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL
+#define SEM_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L
+#define SEM_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L
+#define SEM_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x00F00000L
+#define SEM_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L
+//SEM_OUTSTANDING_THRESHOLD
+#define SEM_OUTSTANDING_THRESHOLD__VALUE__SHIFT 0x0
+#define SEM_OUTSTANDING_THRESHOLD__VALUE_MASK 0x000000FFL
+//SEM_REGISTER_LAST_PART2
+#define SEM_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0
+#define SEM_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL
+//IH_ACTIVE_FCN_ID
+#define IH_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0
+#define IH_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
+#define IH_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f
+#define IH_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL
+#define IH_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L
+#define IH_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L
+//IH_VIRT_RESET_REQ
+#define IH_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define IH_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define IH_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
+#define IH_VIRT_RESET_REQ__PF_MASK 0x80000000L
+//IH_CLIENT_CFG
+#define IH_CLIENT_CFG__TOTAL_CLIENT_NUM__SHIFT 0x0
+#define IH_CLIENT_CFG__TOTAL_CLIENT_NUM_MASK 0x0000001FL
+//IH_CLIENT_CFG_INDEX
+#define IH_CLIENT_CFG_INDEX__INDEX__SHIFT 0x0
+#define IH_CLIENT_CFG_INDEX__INDEX_MASK 0x0000001FL
+//IH_CLIENT_CFG_DATA
+#define IH_CLIENT_CFG_DATA__CREDIT_RETURN_ADDR__SHIFT 0x0
+#define IH_CLIENT_CFG_DATA__CLIENT_TYPE__SHIFT 0x12
+#define IH_CLIENT_CFG_DATA__RING_ID__SHIFT 0x14
+#define IH_CLIENT_CFG_DATA__VF_RB_SELECT__SHIFT 0x16
+#define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID__SHIFT 0x18
+#define IH_CLIENT_CFG_DATA__CREDIT_RETURN_ADDR_MASK 0x0001FFFFL
+#define IH_CLIENT_CFG_DATA__CLIENT_TYPE_MASK 0x000C0000L
+#define IH_CLIENT_CFG_DATA__RING_ID_MASK 0x00300000L
+#define IH_CLIENT_CFG_DATA__VF_RB_SELECT_MASK 0x00C00000L
+#define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID_MASK 0x01000000L
+//IH_CID_REMAP_INDEX
+#define IH_CID_REMAP_INDEX__INDEX__SHIFT 0x0
+#define IH_CID_REMAP_INDEX__INDEX_MASK 0x00000003L
+//IH_CID_REMAP_DATA
+#define IH_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0
+#define IH_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8
+#define IH_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x10
+#define IH_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL
+#define IH_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0000FF00L
+#define IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0x00FF0000L
+//IH_CHICKEN
+#define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x0
+#define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L
+//IH_MMHUB_CNTL
+#define IH_MMHUB_CNTL__UNITID__SHIFT 0x0
+#define IH_MMHUB_CNTL__IV_TLVL__SHIFT 0x8
+#define IH_MMHUB_CNTL__WPTR_WB_TLVL__SHIFT 0xc
+#define IH_MMHUB_CNTL__UNITID_MASK 0x0000003FL
+#define IH_MMHUB_CNTL__IV_TLVL_MASK 0x00000700L
+#define IH_MMHUB_CNTL__WPTR_WB_TLVL_MASK 0x00007000L
+//IH_REGISTER_LAST_PART1
+#define IH_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0
+#define IH_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL
+//SEM_ACTIVE_FCN_ID
+#define SEM_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define SEM_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define SEM_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
+#define SEM_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//SEM_VIRT_RESET_REQ
+#define SEM_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define SEM_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define SEM_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
+#define SEM_VIRT_RESET_REQ__PF_MASK 0x80000000L
+//SEM_RESP_SDMA0
+#define SEM_RESP_SDMA0__ADDR__SHIFT 0x2
+#define SEM_RESP_SDMA0__ADDR_MASK 0x000FFFFCL
+//SEM_RESP_SDMA1
+#define SEM_RESP_SDMA1__ADDR__SHIFT 0x2
+#define SEM_RESP_SDMA1__ADDR_MASK 0x000FFFFCL
+//SEM_RESP_UVD
+#define SEM_RESP_UVD__ADDR__SHIFT 0x2
+#define SEM_RESP_UVD__ADDR_MASK 0x000FFFFCL
+//SEM_RESP_VCE_0
+#define SEM_RESP_VCE_0__ADDR__SHIFT 0x2
+#define SEM_RESP_VCE_0__ADDR_MASK 0x000FFFFCL
+//SEM_RESP_ACP
+#define SEM_RESP_ACP__ADDR__SHIFT 0x2
+#define SEM_RESP_ACP__ADDR_MASK 0x000FFFFCL
+//SEM_RESP_ISP
+#define SEM_RESP_ISP__ADDR__SHIFT 0x2
+#define SEM_RESP_ISP__ADDR_MASK 0x000FFFFCL
+//SEM_RESP_VCE_1
+#define SEM_RESP_VCE_1__ADDR__SHIFT 0x2
+#define SEM_RESP_VCE_1__ADDR_MASK 0x000FFFFCL
+//SEM_RESP_VP8
+#define SEM_RESP_VP8__ADDR__SHIFT 0x2
+#define SEM_RESP_VP8__ADDR_MASK 0x000FFFFCL
+//SEM_RESP_GC
+#define SEM_RESP_GC__ADDR__SHIFT 0x2
+#define SEM_RESP_GC__ADDR_MASK 0x000FFFFCL
+//SEM_CID_REMAP_INDEX
+#define SEM_CID_REMAP_INDEX__INDEX__SHIFT 0x0
+#define SEM_CID_REMAP_INDEX__INDEX_MASK 0x00000003L
+//SEM_CID_REMAP_DATA
+#define SEM_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0
+#define SEM_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8
+#define SEM_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x10
+#define SEM_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL
+#define SEM_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0000FF00L
+#define SEM_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0x00FF0000L
+//SEM_ATOMIC_OP_LUT
+#define SEM_ATOMIC_OP_LUT__SIGNAL_NORMAL__SHIFT 0x0
+#define SEM_ATOMIC_OP_LUT__SIGNAL_WRITE1__SHIFT 0x7
+#define SEM_ATOMIC_OP_LUT__WAIT_NORMAL__SHIFT 0xe
+#define SEM_ATOMIC_OP_LUT__WAIT_CHECK0__SHIFT 0x15
+#define SEM_ATOMIC_OP_LUT__SIGNAL_NORMAL_MASK 0x0000007FL
+#define SEM_ATOMIC_OP_LUT__SIGNAL_WRITE1_MASK 0x00003F80L
+#define SEM_ATOMIC_OP_LUT__WAIT_NORMAL_MASK 0x001FC000L
+#define SEM_ATOMIC_OP_LUT__WAIT_CHECK0_MASK 0x0FE00000L
+//SEM_EDC_CONFIG
+#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
+//SEM_CHICKEN_BITS2
+#define SEM_CHICKEN_BITS2__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x0
+#define SEM_CHICKEN_BITS2__MM_CLIENT_USE_CONFIG_VFID__SHIFT 0x1
+#define SEM_CHICKEN_BITS2__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L
+#define SEM_CHICKEN_BITS2__MM_CLIENT_USE_CONFIG_VFID_MASK 0x00000002L
+//SEM_MMHUB_CNTL
+#define SEM_MMHUB_CNTL__UNIT_ID__SHIFT 0x0
+#define SEM_MMHUB_CNTL__TLVL_VALUE__SHIFT 0x8
+#define SEM_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL
+#define SEM_MMHUB_CNTL__TLVL_VALUE_MASK 0x00000700L
+//SEM_REGISTER_LAST_PART1
+#define SEM_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0
+#define SEM_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h
new file mode 100644
index 000000000000..afd15bd6a41a
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h
@@ -0,0 +1,286 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _sdma0_4_0_DEFAULT_HEADER
+#define _sdma0_4_0_DEFAULT_HEADER
+
+
+// addressBlock: sdma0_sdma0dec
+#define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
+#define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
+#define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
+#define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
+#define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
+#define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
+#define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000
+#define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
+#define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff
+#define mmSDMA0_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff
+#define mmSDMA0_CONTEXT_REG_TYPE3_DEFAULT 0x00000000
+#define mmSDMA0_PUB_REG_TYPE0_DEFAULT 0x3c000000
+#define mmSDMA0_PUB_REG_TYPE1_DEFAULT 0x30003882
+#define mmSDMA0_PUB_REG_TYPE2_DEFAULT 0x0fc6e880
+#define mmSDMA0_PUB_REG_TYPE3_DEFAULT 0x00000000
+#define mmSDMA0_MMHUB_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000
+#define mmSDMA0_POWER_CNTL_DEFAULT 0x0003c000
+#define mmSDMA0_CLK_CTRL_DEFAULT 0xff000100
+#define mmSDMA0_CNTL_DEFAULT 0x00000002
+#define mmSDMA0_CHICKEN_BITS_DEFAULT 0x00831f07
+#define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00100012
+#define mmSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012
+#define mmSDMA0_RB_RPTR_FETCH_HI_DEFAULT 0x00000000
+#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000
+#define mmSDMA0_IB_OFFSET_FETCH_DEFAULT 0x00000000
+#define mmSDMA0_PROGRAM_DEFAULT 0x00000000
+#define mmSDMA0_STATUS_REG_DEFAULT 0x46dee557
+#define mmSDMA0_STATUS1_REG_DEFAULT 0x000003ff
+#define mmSDMA0_RD_BURST_CNTL_DEFAULT 0x00000003
+#define mmSDMA0_HBM_PAGE_CONFIG_DEFAULT 0x00000000
+#define mmSDMA0_UCODE_CHECKSUM_DEFAULT 0x00000000
+#define mmSDMA0_F32_CNTL_DEFAULT 0x00000001
+#define mmSDMA0_FREEZE_DEFAULT 0x00000000
+#define mmSDMA0_PHASE0_QUANTUM_DEFAULT 0x00010002
+#define mmSDMA0_PHASE1_QUANTUM_DEFAULT 0x00010002
+#define mmSDMA_POWER_GATING_DEFAULT 0x00000000
+#define mmSDMA_PGFSM_CONFIG_DEFAULT 0x00000000
+#define mmSDMA_PGFSM_WRITE_DEFAULT 0x00000000
+#define mmSDMA_PGFSM_READ_DEFAULT 0x00000000
+#define mmSDMA0_EDC_CONFIG_DEFAULT 0x00000002
+#define mmSDMA0_BA_THRESHOLD_DEFAULT 0x03ff03ff
+#define mmSDMA0_ID_DEFAULT 0x00000001
+#define mmSDMA0_VERSION_DEFAULT 0x00000400
+#define mmSDMA0_EDC_COUNTER_DEFAULT 0x00000000
+#define mmSDMA0_EDC_COUNTER_CLEAR_DEFAULT 0x00000000
+#define mmSDMA0_STATUS2_REG_DEFAULT 0x00000000
+#define mmSDMA0_ATOMIC_CNTL_DEFAULT 0x00000200
+#define mmSDMA0_ATOMIC_PREOP_LO_DEFAULT 0x00000000
+#define mmSDMA0_ATOMIC_PREOP_HI_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_CNTL_DEFAULT 0xd0003019
+#define mmSDMA0_UTCL1_WATERMK_DEFAULT 0xfffbe1fe
+#define mmSDMA0_UTCL1_RD_STATUS_DEFAULT 0x201001ff
+#define mmSDMA0_UTCL1_WR_STATUS_DEFAULT 0x503001ff
+#define mmSDMA0_UTCL1_INV0_DEFAULT 0x00000600
+#define mmSDMA0_UTCL1_INV1_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_INV2_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_RD_XNACK0_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_RD_XNACK1_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_WR_XNACK0_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_WR_XNACK1_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_TIMEOUT_DEFAULT 0x00010001
+#define mmSDMA0_UTCL1_PAGE_DEFAULT 0x000003e0
+#define mmSDMA0_POWER_CNTL_IDLE_DEFAULT 0x06060200
+#define mmSDMA0_RELAX_ORDERING_LUT_DEFAULT 0xc0000006
+#define mmSDMA0_CHICKEN_BITS_2_DEFAULT 0x00000005
+#define mmSDMA0_STATUS3_REG_DEFAULT 0x00100000
+#define mmSDMA0_PHYSICAL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_PHYSICAL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_PHASE2_QUANTUM_DEFAULT 0x00010002
+#define mmSDMA0_ERROR_LOG_DEFAULT 0x0000000f
+#define mmSDMA0_PUB_DUMMY_REG0_DEFAULT 0x00000000
+#define mmSDMA0_PUB_DUMMY_REG1_DEFAULT 0x00000000
+#define mmSDMA0_PUB_DUMMY_REG2_DEFAULT 0x00000000
+#define mmSDMA0_PUB_DUMMY_REG3_DEFAULT 0x00000000
+#define mmSDMA0_F32_COUNTER_DEFAULT 0x00000000
+#define mmSDMA0_UNBREAKABLE_DEFAULT 0x00000000
+#define mmSDMA0_PERFMON_CNTL_DEFAULT 0x000ff7fd
+#define mmSDMA0_PERFCOUNTER0_RESULT_DEFAULT 0x00000000
+#define mmSDMA0_PERFCOUNTER1_RESULT_DEFAULT 0x00000000
+#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000
+#define mmSDMA0_CRD_CNTL_DEFAULT 0x000085c0
+#define mmSDMA0_MMHUB_TRUSTLVL_DEFAULT 0x00000000
+#define mmSDMA0_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000
+#define mmSDMA0_ULV_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000
+#define mmSDMA0_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_CNTL_DEFAULT 0x00040000
+#define mmSDMA0_GFX_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_GFX_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA0_GFX_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_GFX_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_GFX_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA0_GFX_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA0_GFX_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_GFX_CONTEXT_STATUS_DEFAULT 0x00000005
+#define mmSDMA0_GFX_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA0_GFX_CONTEXT_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_GFX_STATUS_DEFAULT 0x00000000
+#define mmSDMA0_GFX_DOORBELL_LOG_DEFAULT 0x00000000
+#define mmSDMA0_GFX_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA0_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_GFX_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_GFX_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA0_GFX_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA0_GFX_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA0_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_CNTL_DEFAULT 0x00040000
+#define mmSDMA0_PAGE_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA0_PAGE_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA0_PAGE_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_STATUS_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_DOORBELL_LOG_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_CNTL_DEFAULT 0x00040000
+#define mmSDMA0_RLC0_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA0_RLC0_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA0_RLC0_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_STATUS_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_DOORBELL_LOG_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_CNTL_DEFAULT 0x00040000
+#define mmSDMA0_RLC1_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA0_RLC1_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA0_RLC1_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_STATUS_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_DOORBELL_LOG_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h
new file mode 100644
index 000000000000..b100c4e5f1ca
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h
@@ -0,0 +1,547 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _sdma0_4_0_OFFSET_HEADER
+#define _sdma0_4_0_OFFSET_HEADER
+
+
+
+// addressBlock: sdma0_sdma0dec
+// base address: 0x4980
+#define mmSDMA0_UCODE_ADDR 0x0000
+#define mmSDMA0_UCODE_ADDR_BASE_IDX 0
+#define mmSDMA0_UCODE_DATA 0x0001
+#define mmSDMA0_UCODE_DATA_BASE_IDX 0
+#define mmSDMA0_VM_CNTL 0x0004
+#define mmSDMA0_VM_CNTL_BASE_IDX 0
+#define mmSDMA0_VM_CTX_LO 0x0005
+#define mmSDMA0_VM_CTX_LO_BASE_IDX 0
+#define mmSDMA0_VM_CTX_HI 0x0006
+#define mmSDMA0_VM_CTX_HI_BASE_IDX 0
+#define mmSDMA0_ACTIVE_FCN_ID 0x0007
+#define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX 0
+#define mmSDMA0_VM_CTX_CNTL 0x0008
+#define mmSDMA0_VM_CTX_CNTL_BASE_IDX 0
+#define mmSDMA0_VIRT_RESET_REQ 0x0009
+#define mmSDMA0_VIRT_RESET_REQ_BASE_IDX 0
+#define mmSDMA0_VF_ENABLE 0x000a
+#define mmSDMA0_VF_ENABLE_BASE_IDX 0
+#define mmSDMA0_CONTEXT_REG_TYPE0 0x000b
+#define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX 0
+#define mmSDMA0_CONTEXT_REG_TYPE1 0x000c
+#define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX 0
+#define mmSDMA0_CONTEXT_REG_TYPE2 0x000d
+#define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX 0
+#define mmSDMA0_CONTEXT_REG_TYPE3 0x000e
+#define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX 0
+#define mmSDMA0_PUB_REG_TYPE0 0x000f
+#define mmSDMA0_PUB_REG_TYPE0_BASE_IDX 0
+#define mmSDMA0_PUB_REG_TYPE1 0x0010
+#define mmSDMA0_PUB_REG_TYPE1_BASE_IDX 0
+#define mmSDMA0_PUB_REG_TYPE2 0x0011
+#define mmSDMA0_PUB_REG_TYPE2_BASE_IDX 0
+#define mmSDMA0_PUB_REG_TYPE3 0x0012
+#define mmSDMA0_PUB_REG_TYPE3_BASE_IDX 0
+#define mmSDMA0_MMHUB_CNTL 0x0013
+#define mmSDMA0_MMHUB_CNTL_BASE_IDX 0
+#define mmSDMA0_CONTEXT_GROUP_BOUNDARY 0x0019
+#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0
+#define mmSDMA0_POWER_CNTL 0x001a
+#define mmSDMA0_POWER_CNTL_BASE_IDX 0
+#define mmSDMA0_CLK_CTRL 0x001b
+#define mmSDMA0_CLK_CTRL_BASE_IDX 0
+#define mmSDMA0_CNTL 0x001c
+#define mmSDMA0_CNTL_BASE_IDX 0
+#define mmSDMA0_CHICKEN_BITS 0x001d
+#define mmSDMA0_CHICKEN_BITS_BASE_IDX 0
+#define mmSDMA0_GB_ADDR_CONFIG 0x001e
+#define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX 0
+#define mmSDMA0_GB_ADDR_CONFIG_READ 0x001f
+#define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0
+#define mmSDMA0_RB_RPTR_FETCH_HI 0x0020
+#define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0
+#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021
+#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0
+#define mmSDMA0_RB_RPTR_FETCH 0x0022
+#define mmSDMA0_RB_RPTR_FETCH_BASE_IDX 0
+#define mmSDMA0_IB_OFFSET_FETCH 0x0023
+#define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX 0
+#define mmSDMA0_PROGRAM 0x0024
+#define mmSDMA0_PROGRAM_BASE_IDX 0
+#define mmSDMA0_STATUS_REG 0x0025
+#define mmSDMA0_STATUS_REG_BASE_IDX 0
+#define mmSDMA0_STATUS1_REG 0x0026
+#define mmSDMA0_STATUS1_REG_BASE_IDX 0
+#define mmSDMA0_RD_BURST_CNTL 0x0027
+#define mmSDMA0_RD_BURST_CNTL_BASE_IDX 0
+#define mmSDMA0_HBM_PAGE_CONFIG 0x0028
+#define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0
+#define mmSDMA0_UCODE_CHECKSUM 0x0029
+#define mmSDMA0_UCODE_CHECKSUM_BASE_IDX 0
+#define mmSDMA0_F32_CNTL 0x002a
+#define mmSDMA0_F32_CNTL_BASE_IDX 0
+#define mmSDMA0_FREEZE 0x002b
+#define mmSDMA0_FREEZE_BASE_IDX 0
+#define mmSDMA0_PHASE0_QUANTUM 0x002c
+#define mmSDMA0_PHASE0_QUANTUM_BASE_IDX 0
+#define mmSDMA0_PHASE1_QUANTUM 0x002d
+#define mmSDMA0_PHASE1_QUANTUM_BASE_IDX 0
+#define mmSDMA_POWER_GATING 0x002e
+#define mmSDMA_POWER_GATING_BASE_IDX 0
+#define mmSDMA_PGFSM_CONFIG 0x002f
+#define mmSDMA_PGFSM_CONFIG_BASE_IDX 0
+#define mmSDMA_PGFSM_WRITE 0x0030
+#define mmSDMA_PGFSM_WRITE_BASE_IDX 0
+#define mmSDMA_PGFSM_READ 0x0031
+#define mmSDMA_PGFSM_READ_BASE_IDX 0
+#define mmSDMA0_EDC_CONFIG 0x0032
+#define mmSDMA0_EDC_CONFIG_BASE_IDX 0
+#define mmSDMA0_BA_THRESHOLD 0x0033
+#define mmSDMA0_BA_THRESHOLD_BASE_IDX 0
+#define mmSDMA0_ID 0x0034
+#define mmSDMA0_ID_BASE_IDX 0
+#define mmSDMA0_VERSION 0x0035
+#define mmSDMA0_VERSION_BASE_IDX 0
+#define mmSDMA0_EDC_COUNTER 0x0036
+#define mmSDMA0_EDC_COUNTER_BASE_IDX 0
+#define mmSDMA0_EDC_COUNTER_CLEAR 0x0037
+#define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0
+#define mmSDMA0_STATUS2_REG 0x0038
+#define mmSDMA0_STATUS2_REG_BASE_IDX 0
+#define mmSDMA0_ATOMIC_CNTL 0x0039
+#define mmSDMA0_ATOMIC_CNTL_BASE_IDX 0
+#define mmSDMA0_ATOMIC_PREOP_LO 0x003a
+#define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0
+#define mmSDMA0_ATOMIC_PREOP_HI 0x003b
+#define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0
+#define mmSDMA0_UTCL1_CNTL 0x003c
+#define mmSDMA0_UTCL1_CNTL_BASE_IDX 0
+#define mmSDMA0_UTCL1_WATERMK 0x003d
+#define mmSDMA0_UTCL1_WATERMK_BASE_IDX 0
+#define mmSDMA0_UTCL1_RD_STATUS 0x003e
+#define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX 0
+#define mmSDMA0_UTCL1_WR_STATUS 0x003f
+#define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX 0
+#define mmSDMA0_UTCL1_INV0 0x0040
+#define mmSDMA0_UTCL1_INV0_BASE_IDX 0
+#define mmSDMA0_UTCL1_INV1 0x0041
+#define mmSDMA0_UTCL1_INV1_BASE_IDX 0
+#define mmSDMA0_UTCL1_INV2 0x0042
+#define mmSDMA0_UTCL1_INV2_BASE_IDX 0
+#define mmSDMA0_UTCL1_RD_XNACK0 0x0043
+#define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0
+#define mmSDMA0_UTCL1_RD_XNACK1 0x0044
+#define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0
+#define mmSDMA0_UTCL1_WR_XNACK0 0x0045
+#define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0
+#define mmSDMA0_UTCL1_WR_XNACK1 0x0046
+#define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0
+#define mmSDMA0_UTCL1_TIMEOUT 0x0047
+#define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX 0
+#define mmSDMA0_UTCL1_PAGE 0x0048
+#define mmSDMA0_UTCL1_PAGE_BASE_IDX 0
+#define mmSDMA0_POWER_CNTL_IDLE 0x0049
+#define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX 0
+#define mmSDMA0_RELAX_ORDERING_LUT 0x004a
+#define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0
+#define mmSDMA0_CHICKEN_BITS_2 0x004b
+#define mmSDMA0_CHICKEN_BITS_2_BASE_IDX 0
+#define mmSDMA0_STATUS3_REG 0x004c
+#define mmSDMA0_STATUS3_REG_BASE_IDX 0
+#define mmSDMA0_PHYSICAL_ADDR_LO 0x004d
+#define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_PHYSICAL_ADDR_HI 0x004e
+#define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_PHASE2_QUANTUM 0x004f
+#define mmSDMA0_PHASE2_QUANTUM_BASE_IDX 0
+#define mmSDMA0_ERROR_LOG 0x0050
+#define mmSDMA0_ERROR_LOG_BASE_IDX 0
+#define mmSDMA0_PUB_DUMMY_REG0 0x0051
+#define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX 0
+#define mmSDMA0_PUB_DUMMY_REG1 0x0052
+#define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX 0
+#define mmSDMA0_PUB_DUMMY_REG2 0x0053
+#define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX 0
+#define mmSDMA0_PUB_DUMMY_REG3 0x0054
+#define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX 0
+#define mmSDMA0_F32_COUNTER 0x0055
+#define mmSDMA0_F32_COUNTER_BASE_IDX 0
+#define mmSDMA0_UNBREAKABLE 0x0056
+#define mmSDMA0_UNBREAKABLE_BASE_IDX 0
+#define mmSDMA0_PERFMON_CNTL 0x0057
+#define mmSDMA0_PERFMON_CNTL_BASE_IDX 0
+#define mmSDMA0_PERFCOUNTER0_RESULT 0x0058
+#define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX 0
+#define mmSDMA0_PERFCOUNTER1_RESULT 0x0059
+#define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX 0
+#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE 0x005a
+#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0
+#define mmSDMA0_CRD_CNTL 0x005b
+#define mmSDMA0_CRD_CNTL_BASE_IDX 0
+#define mmSDMA0_MMHUB_TRUSTLVL 0x005c
+#define mmSDMA0_MMHUB_TRUSTLVL_BASE_IDX 0
+#define mmSDMA0_GPU_IOV_VIOLATION_LOG 0x005d
+#define mmSDMA0_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
+#define mmSDMA0_ULV_CNTL 0x005e
+#define mmSDMA0_ULV_CNTL_BASE_IDX 0
+#define mmSDMA0_EA_DBIT_ADDR_DATA 0x0060
+#define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0
+#define mmSDMA0_EA_DBIT_ADDR_INDEX 0x0061
+#define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0
+#define mmSDMA0_GFX_RB_CNTL 0x0080
+#define mmSDMA0_GFX_RB_CNTL_BASE_IDX 0
+#define mmSDMA0_GFX_RB_BASE 0x0081
+#define mmSDMA0_GFX_RB_BASE_BASE_IDX 0
+#define mmSDMA0_GFX_RB_BASE_HI 0x0082
+#define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_GFX_RB_RPTR 0x0083
+#define mmSDMA0_GFX_RB_RPTR_BASE_IDX 0
+#define mmSDMA0_GFX_RB_RPTR_HI 0x0084
+#define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA0_GFX_RB_WPTR 0x0085
+#define mmSDMA0_GFX_RB_WPTR_BASE_IDX 0
+#define mmSDMA0_GFX_RB_WPTR_HI 0x0086
+#define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087
+#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088
+#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089
+#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_GFX_IB_CNTL 0x008a
+#define mmSDMA0_GFX_IB_CNTL_BASE_IDX 0
+#define mmSDMA0_GFX_IB_RPTR 0x008b
+#define mmSDMA0_GFX_IB_RPTR_BASE_IDX 0
+#define mmSDMA0_GFX_IB_OFFSET 0x008c
+#define mmSDMA0_GFX_IB_OFFSET_BASE_IDX 0
+#define mmSDMA0_GFX_IB_BASE_LO 0x008d
+#define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA0_GFX_IB_BASE_HI 0x008e
+#define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_GFX_IB_SIZE 0x008f
+#define mmSDMA0_GFX_IB_SIZE_BASE_IDX 0
+#define mmSDMA0_GFX_SKIP_CNTL 0x0090
+#define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA0_GFX_CONTEXT_STATUS 0x0091
+#define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA0_GFX_DOORBELL 0x0092
+#define mmSDMA0_GFX_DOORBELL_BASE_IDX 0
+#define mmSDMA0_GFX_CONTEXT_CNTL 0x0093
+#define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0
+#define mmSDMA0_GFX_STATUS 0x00a8
+#define mmSDMA0_GFX_STATUS_BASE_IDX 0
+#define mmSDMA0_GFX_DOORBELL_LOG 0x00a9
+#define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX 0
+#define mmSDMA0_GFX_WATERMARK 0x00aa
+#define mmSDMA0_GFX_WATERMARK_BASE_IDX 0
+#define mmSDMA0_GFX_DOORBELL_OFFSET 0x00ab
+#define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA0_GFX_CSA_ADDR_LO 0x00ac
+#define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_GFX_CSA_ADDR_HI 0x00ad
+#define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_GFX_IB_SUB_REMAIN 0x00af
+#define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA0_GFX_PREEMPT 0x00b0
+#define mmSDMA0_GFX_PREEMPT_BASE_IDX 0
+#define mmSDMA0_GFX_DUMMY_REG 0x00b1
+#define mmSDMA0_GFX_DUMMY_REG_BASE_IDX 0
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_GFX_RB_AQL_CNTL 0x00b4
+#define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5
+#define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA0 0x00c0
+#define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA1 0x00c1
+#define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA2 0x00c2
+#define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA3 0x00c3
+#define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA4 0x00c4
+#define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA5 0x00c5
+#define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA6 0x00c6
+#define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA7 0x00c7
+#define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA8 0x00c8
+#define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_CNTL 0x00c9
+#define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_CNTL 0x00e0
+#define mmSDMA0_PAGE_RB_CNTL_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_BASE 0x00e1
+#define mmSDMA0_PAGE_RB_BASE_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_BASE_HI 0x00e2
+#define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_RPTR 0x00e3
+#define mmSDMA0_PAGE_RB_RPTR_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_RPTR_HI 0x00e4
+#define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_WPTR 0x00e5
+#define mmSDMA0_PAGE_RB_WPTR_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_WPTR_HI 0x00e6
+#define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00e7
+#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI 0x00e8
+#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO 0x00e9
+#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_PAGE_IB_CNTL 0x00ea
+#define mmSDMA0_PAGE_IB_CNTL_BASE_IDX 0
+#define mmSDMA0_PAGE_IB_RPTR 0x00eb
+#define mmSDMA0_PAGE_IB_RPTR_BASE_IDX 0
+#define mmSDMA0_PAGE_IB_OFFSET 0x00ec
+#define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX 0
+#define mmSDMA0_PAGE_IB_BASE_LO 0x00ed
+#define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA0_PAGE_IB_BASE_HI 0x00ee
+#define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_PAGE_IB_SIZE 0x00ef
+#define mmSDMA0_PAGE_IB_SIZE_BASE_IDX 0
+#define mmSDMA0_PAGE_SKIP_CNTL 0x00f0
+#define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA0_PAGE_CONTEXT_STATUS 0x00f1
+#define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA0_PAGE_DOORBELL 0x00f2
+#define mmSDMA0_PAGE_DOORBELL_BASE_IDX 0
+#define mmSDMA0_PAGE_STATUS 0x0108
+#define mmSDMA0_PAGE_STATUS_BASE_IDX 0
+#define mmSDMA0_PAGE_DOORBELL_LOG 0x0109
+#define mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX 0
+#define mmSDMA0_PAGE_WATERMARK 0x010a
+#define mmSDMA0_PAGE_WATERMARK_BASE_IDX 0
+#define mmSDMA0_PAGE_DOORBELL_OFFSET 0x010b
+#define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA0_PAGE_CSA_ADDR_LO 0x010c
+#define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_PAGE_CSA_ADDR_HI 0x010d
+#define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_PAGE_IB_SUB_REMAIN 0x010f
+#define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA0_PAGE_PREEMPT 0x0110
+#define mmSDMA0_PAGE_PREEMPT_BASE_IDX 0
+#define mmSDMA0_PAGE_DUMMY_REG 0x0111
+#define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112
+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113
+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_AQL_CNTL 0x0114
+#define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA0_PAGE_MINOR_PTR_UPDATE 0x0115
+#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA0 0x0120
+#define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA1 0x0121
+#define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA2 0x0122
+#define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA3 0x0123
+#define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA4 0x0124
+#define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA5 0x0125
+#define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA6 0x0126
+#define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA7 0x0127
+#define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA8 0x0128
+#define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_CNTL 0x0129
+#define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_CNTL 0x0140
+#define mmSDMA0_RLC0_RB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_BASE 0x0141
+#define mmSDMA0_RLC0_RB_BASE_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_BASE_HI 0x0142
+#define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_RPTR 0x0143
+#define mmSDMA0_RLC0_RB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_RPTR_HI 0x0144
+#define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_WPTR 0x0145
+#define mmSDMA0_RLC0_RB_WPTR_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_WPTR_HI 0x0146
+#define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0147
+#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0148
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0149
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC0_IB_CNTL 0x014a
+#define mmSDMA0_RLC0_IB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC0_IB_RPTR 0x014b
+#define mmSDMA0_RLC0_IB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC0_IB_OFFSET 0x014c
+#define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC0_IB_BASE_LO 0x014d
+#define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA0_RLC0_IB_BASE_HI 0x014e
+#define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC0_IB_SIZE 0x014f
+#define mmSDMA0_RLC0_IB_SIZE_BASE_IDX 0
+#define mmSDMA0_RLC0_SKIP_CNTL 0x0150
+#define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC0_CONTEXT_STATUS 0x0151
+#define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC0_DOORBELL 0x0152
+#define mmSDMA0_RLC0_DOORBELL_BASE_IDX 0
+#define mmSDMA0_RLC0_STATUS 0x0168
+#define mmSDMA0_RLC0_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC0_DOORBELL_LOG 0x0169
+#define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX 0
+#define mmSDMA0_RLC0_WATERMARK 0x016a
+#define mmSDMA0_RLC0_WATERMARK_BASE_IDX 0
+#define mmSDMA0_RLC0_DOORBELL_OFFSET 0x016b
+#define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC0_CSA_ADDR_LO 0x016c
+#define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC0_CSA_ADDR_HI 0x016d
+#define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x016f
+#define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA0_RLC0_PREEMPT 0x0170
+#define mmSDMA0_RLC0_PREEMPT_BASE_IDX 0
+#define mmSDMA0_RLC0_DUMMY_REG 0x0171
+#define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_AQL_CNTL 0x0174
+#define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0175
+#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA0 0x0180
+#define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA1 0x0181
+#define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA2 0x0182
+#define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA3 0x0183
+#define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA4 0x0184
+#define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA5 0x0185
+#define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA6 0x0186
+#define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA7 0x0187
+#define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA8 0x0188
+#define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_CNTL 0x0189
+#define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_CNTL 0x01a0
+#define mmSDMA0_RLC1_RB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_BASE 0x01a1
+#define mmSDMA0_RLC1_RB_BASE_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_BASE_HI 0x01a2
+#define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_RPTR 0x01a3
+#define mmSDMA0_RLC1_RB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_RPTR_HI 0x01a4
+#define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_WPTR 0x01a5
+#define mmSDMA0_RLC1_RB_WPTR_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_WPTR_HI 0x01a6
+#define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x01a7
+#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x01a8
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x01a9
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC1_IB_CNTL 0x01aa
+#define mmSDMA0_RLC1_IB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC1_IB_RPTR 0x01ab
+#define mmSDMA0_RLC1_IB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC1_IB_OFFSET 0x01ac
+#define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC1_IB_BASE_LO 0x01ad
+#define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA0_RLC1_IB_BASE_HI 0x01ae
+#define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC1_IB_SIZE 0x01af
+#define mmSDMA0_RLC1_IB_SIZE_BASE_IDX 0
+#define mmSDMA0_RLC1_SKIP_CNTL 0x01b0
+#define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC1_CONTEXT_STATUS 0x01b1
+#define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC1_DOORBELL 0x01b2
+#define mmSDMA0_RLC1_DOORBELL_BASE_IDX 0
+#define mmSDMA0_RLC1_STATUS 0x01c8
+#define mmSDMA0_RLC1_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC1_DOORBELL_LOG 0x01c9
+#define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX 0
+#define mmSDMA0_RLC1_WATERMARK 0x01ca
+#define mmSDMA0_RLC1_WATERMARK_BASE_IDX 0
+#define mmSDMA0_RLC1_DOORBELL_OFFSET 0x01cb
+#define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC1_CSA_ADDR_LO 0x01cc
+#define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC1_CSA_ADDR_HI 0x01cd
+#define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x01cf
+#define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA0_RLC1_PREEMPT 0x01d0
+#define mmSDMA0_RLC1_PREEMPT_BASE_IDX 0
+#define mmSDMA0_RLC1_DUMMY_REG 0x01d1
+#define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_AQL_CNTL 0x01d4
+#define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC1_MINOR_PTR_UPDATE 0x01d5
+#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA0 0x01e0
+#define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA1 0x01e1
+#define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA2 0x01e2
+#define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA3 0x01e3
+#define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA4 0x01e4
+#define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA5 0x01e5
+#define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA6 0x01e6
+#define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA7 0x01e7
+#define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA8 0x01e8
+#define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_CNTL 0x01e9
+#define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h
new file mode 100644
index 000000000000..412ae457f7e0
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h
@@ -0,0 +1,1852 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _sdma0_4_0_SH_MASK_HEADER
+#define _sdma0_4_0_SH_MASK_HEADER
+
+
+// addressBlock: sdma0_sdma0dec
+//SDMA0_UCODE_ADDR
+#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0
+#define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL
+//SDMA0_UCODE_DATA
+#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
+#define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_VM_CNTL
+#define SDMA0_VM_CNTL__CMD__SHIFT 0x0
+#define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL
+//SDMA0_VM_CTX_LO
+#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2
+#define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_VM_CTX_HI
+#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0
+#define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_ACTIVE_FCN_ID
+#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
+#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
+#define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L
+#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//SDMA0_VM_CTX_CNTL
+#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0
+#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4
+#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L
+#define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L
+//SDMA0_VIRT_RESET_REQ
+#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
+#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L
+//SDMA0_VF_ENABLE
+#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
+//SDMA0_CONTEXT_REG_TYPE0
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L
+//SDMA0_CONTEXT_REG_TYPE1
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd
+#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15
+#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L
+#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L
+#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L
+//SDMA0_CONTEXT_REG_TYPE2
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9
+#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L
+#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L
+//SDMA0_CONTEXT_REG_TYPE3
+#define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0
+#define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL
+//SDMA0_PUB_REG_TYPE0
+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0
+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1
+#define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6
+#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9
+#define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12
+#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13
+#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19
+#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d
+#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e
+#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f
+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L
+#define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L
+#define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L
+#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L
+//SDMA0_PUB_REG_TYPE1
+#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0
+#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1
+#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2
+#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3
+#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4
+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5
+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6
+#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7
+#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8
+#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9
+#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa
+#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb
+#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc
+#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd
+#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe
+#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf
+#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10
+#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11
+#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12
+#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15
+#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16
+#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17
+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b
+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c
+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d
+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e
+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f
+#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L
+#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L
+#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L
+#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L
+#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L
+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L
+//SDMA0_PUB_REG_TYPE2
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8
+#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9
+#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa
+#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb
+#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf
+#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14
+#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a
+#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b
+#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL__SHIFT 0x1c
+#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
+#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e
+#define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL_MASK 0x10000000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L
+#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L
+#define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L
+//SDMA0_PUB_REG_TYPE3
+#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0
+#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1
+#define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2
+#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L
+#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L
+#define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL
+//SDMA0_MMHUB_CNTL
+#define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0
+#define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL
+//SDMA0_CONTEXT_GROUP_BOUNDARY
+#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0
+#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL
+//SDMA0_POWER_CNTL
+#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0
+#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1
+#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2
+#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
+#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
+#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
+#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
+#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
+#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L
+#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L
+#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L
+#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L
+#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L
+#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L
+#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L
+#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L
+//SDMA0_CLK_CTRL
+#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//SDMA0_CNTL
+#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0
+#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1
+#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
+#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
+#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
+#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
+#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
+#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
+#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
+#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
+#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L
+#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L
+#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L
+#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L
+#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L
+#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L
+#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L
+#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L
+#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L
+#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L
+//SDMA0_CHICKEN_BITS
+#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
+#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
+#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
+#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8
+#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
+#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
+#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11
+#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
+#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
+#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19
+#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
+#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
+#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
+#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L
+#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L
+#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L
+#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L
+#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L
+#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L
+#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L
+#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L
+#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L
+#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L
+#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L
+#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L
+#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L
+//SDMA0_GB_ADDR_CONFIG
+#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA0_GB_ADDR_CONFIG_READ
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
+#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
+#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA0_RB_RPTR_FETCH_HI
+#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL
+#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
+#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL
+//SDMA0_RB_RPTR_FETCH
+#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
+#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL
+//SDMA0_IB_OFFSET_FETCH
+#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
+#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL
+//SDMA0_PROGRAM
+#define SDMA0_PROGRAM__STREAM__SHIFT 0x0
+#define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL
+//SDMA0_STATUS_REG
+#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0
+#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
+#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
+#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3
+#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
+#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
+#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
+#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
+#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
+#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9
+#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
+#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
+#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc
+#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
+#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe
+#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
+#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
+#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
+#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
+#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
+#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
+#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
+#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
+#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
+#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
+#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
+#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
+#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e
+#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
+#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L
+#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L
+#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L
+#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L
+#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L
+#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L
+#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L
+#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L
+#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L
+#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L
+#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L
+#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L
+#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L
+#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L
+#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L
+#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L
+#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L
+#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L
+#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L
+#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L
+#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L
+#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L
+#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L
+#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L
+#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L
+#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L
+#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L
+#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L
+#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L
+//SDMA0_STATUS1_REG
+#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
+#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
+#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
+#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
+#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
+#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
+#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
+#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
+#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
+#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
+#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
+#define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf
+#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
+#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
+#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L
+#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L
+#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L
+#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L
+#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L
+#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L
+#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L
+#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L
+#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L
+#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L
+#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L
+#define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L
+#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L
+#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L
+//SDMA0_RD_BURST_CNTL
+#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
+#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L
+//SDMA0_HBM_PAGE_CONFIG
+#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0
+#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L
+//SDMA0_UCODE_CHECKSUM
+#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0
+#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL
+//SDMA0_F32_CNTL
+#define SDMA0_F32_CNTL__HALT__SHIFT 0x0
+#define SDMA0_F32_CNTL__STEP__SHIFT 0x1
+#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L
+#define SDMA0_F32_CNTL__STEP_MASK 0x00000002L
+//SDMA0_FREEZE
+#define SDMA0_FREEZE__PREEMPT__SHIFT 0x0
+#define SDMA0_FREEZE__FREEZE__SHIFT 0x4
+#define SDMA0_FREEZE__FROZEN__SHIFT 0x5
+#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6
+#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L
+#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L
+#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L
+#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L
+//SDMA0_PHASE0_QUANTUM
+#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA0_PHASE1_QUANTUM
+#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA_POWER_GATING
+#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0
+#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1
+#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2
+#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3
+#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4
+#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L
+#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L
+#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L
+#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L
+#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L
+//SDMA_PGFSM_CONFIG
+#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
+#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
+#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
+#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
+#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
+#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc
+#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd
+#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
+#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
+#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL
+#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L
+#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L
+#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L
+#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L
+#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L
+#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L
+#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L
+#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L
+//SDMA_PGFSM_WRITE
+#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0
+#define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL
+//SDMA_PGFSM_READ
+#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0
+#define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL
+//SDMA0_EDC_CONFIG
+#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
+#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
+#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L
+//SDMA0_BA_THRESHOLD
+#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0
+#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
+#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL
+#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L
+//SDMA0_ID
+#define SDMA0_ID__DEVICE_ID__SHIFT 0x0
+#define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL
+//SDMA0_VERSION
+#define SDMA0_VERSION__MINVER__SHIFT 0x0
+#define SDMA0_VERSION__MAJVER__SHIFT 0x8
+#define SDMA0_VERSION__REV__SHIFT 0x10
+#define SDMA0_VERSION__MINVER_MASK 0x0000007FL
+#define SDMA0_VERSION__MAJVER_MASK 0x00007F00L
+#define SDMA0_VERSION__REV_MASK 0x003F0000L
+//SDMA0_EDC_COUNTER
+#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0
+#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1
+#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2
+#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3
+#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4
+#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5
+#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe
+#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf
+#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10
+#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L
+#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L
+#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L
+#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L
+#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L
+#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L
+#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L
+#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L
+#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L
+//SDMA0_EDC_COUNTER_CLEAR
+#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0
+#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L
+//SDMA0_STATUS2_REG
+#define SDMA0_STATUS2_REG__ID__SHIFT 0x0
+#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
+#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10
+#define SDMA0_STATUS2_REG__ID_MASK 0x00000003L
+#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL
+#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L
+//SDMA0_ATOMIC_CNTL
+#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
+#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
+#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL
+#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L
+//SDMA0_ATOMIC_PREOP_LO
+#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
+#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL
+//SDMA0_ATOMIC_PREOP_HI
+#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
+#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL
+//SDMA0_UTCL1_CNTL
+#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0
+#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1
+#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb
+#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe
+#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
+#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
+#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L
+#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL
+#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L
+#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L
+#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L
+#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L
+//SDMA0_UTCL1_WATERMK
+#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0
+#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
+#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12
+#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a
+#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL
+#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L
+#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L
+#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L
+//SDMA0_UTCL1_RD_STATUS
+#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12
+#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13
+#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14
+#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15
+#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16
+#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a
+#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
+#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e
+#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f
+#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
+#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
+#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
+#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
+#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
+#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
+#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L
+#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L
+#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L
+#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L
+#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L
+#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L
+#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L
+#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L
+#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L
+//SDMA0_UTCL1_WR_STATUS
+#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12
+#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13
+#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14
+#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15
+#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16
+#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19
+#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c
+#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
+#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e
+#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f
+#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
+#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
+#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
+#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
+#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
+#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
+#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L
+#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L
+#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L
+#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L
+#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L
+#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L
+#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L
+#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L
+#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L
+#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L
+//SDMA0_UTCL1_INV0
+#define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0
+#define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1
+#define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2
+#define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3
+#define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4
+#define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5
+#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6
+#define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7
+#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8
+#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9
+#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
+#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb
+#define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc
+#define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c
+#define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L
+#define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L
+#define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L
+#define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L
+#define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L
+#define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L
+#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L
+#define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L
+#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L
+#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L
+#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L
+#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L
+#define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L
+#define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L
+//SDMA0_UTCL1_INV1
+#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0
+#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA0_UTCL1_INV2
+#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0
+#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL
+//SDMA0_UTCL1_RD_XNACK0
+#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA0_UTCL1_RD_XNACK1
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA0_UTCL1_WR_XNACK0
+#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA0_UTCL1_WR_XNACK1
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA0_UTCL1_TIMEOUT
+#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
+#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
+#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL
+#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L
+//SDMA0_UTCL1_PAGE
+#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0
+#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1
+#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6
+#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9
+#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L
+#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL
+#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L
+#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L
+//SDMA0_POWER_CNTL_IDLE
+#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
+#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
+#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
+#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL
+#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L
+#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L
+//SDMA0_RELAX_ORDERING_LUT
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0
+#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1
+#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4
+#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6
+#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8
+#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9
+#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
+#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb
+#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc
+#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe
+#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b
+#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c
+#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
+#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e
+#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L
+#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L
+#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L
+#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L
+#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L
+#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L
+#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L
+#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L
+#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L
+#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L
+#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L
+#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L
+#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L
+#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L
+#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L
+//SDMA0_CHICKEN_BITS_2
+#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0
+#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL
+//SDMA0_STATUS3_REG
+#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0
+#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10
+#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14
+#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL
+#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L
+#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L
+//SDMA0_PHYSICAL_ADDR_LO
+#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0
+#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1
+#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2
+#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc
+#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L
+#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L
+#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L
+#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L
+//SDMA0_PHYSICAL_ADDR_HI
+#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL
+//SDMA0_PHASE2_QUANTUM
+#define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA0_ERROR_LOG
+#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0
+#define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10
+#define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL
+#define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L
+//SDMA0_PUB_DUMMY_REG0
+#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0
+#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_PUB_DUMMY_REG1
+#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0
+#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_PUB_DUMMY_REG2
+#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0
+#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_PUB_DUMMY_REG3
+#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0
+#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_F32_COUNTER
+#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0
+#define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_UNBREAKABLE
+#define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0
+#define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L
+//SDMA0_PERFMON_CNTL
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
+#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb
+#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L
+#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L
+#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L
+//SDMA0_PERFCOUNTER0_RESULT
+#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
+//SDMA0_PERFCOUNTER1_RESULT
+#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
+//SDMA0_PERFCOUNTER_TAG_DELAY_RANGE
+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0
+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe
+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c
+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL
+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L
+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L
+//SDMA0_CRD_CNTL
+#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7
+#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
+#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L
+#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L
+//SDMA0_MMHUB_TRUSTLVL
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L
+#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L
+//SDMA0_GPU_IOV_VIOLATION_LOG
+#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
+#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1
+#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2
+#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12
+#define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13
+#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14
+#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18
+#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
+#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L
+#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL
+#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L
+#define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L
+#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L
+#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L
+//SDMA0_ULV_CNTL
+#define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0
+#define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
+#define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e
+#define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f
+#define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL
+#define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L
+#define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L
+#define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L
+//SDMA0_EA_DBIT_ADDR_DATA
+#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0
+#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_EA_DBIT_ADDR_INDEX
+#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0
+#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L
+//SDMA0_GFX_RB_CNTL
+#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL
+#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA0_GFX_RB_BASE
+#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_BASE_HI
+#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_GFX_RB_RPTR
+#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_RPTR_HI
+#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_WPTR
+#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_WPTR_HI
+#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_WPTR_POLL_CNTL
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_GFX_RB_RPTR_ADDR_HI
+#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_RPTR_ADDR_LO
+#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_GFX_IB_CNTL
+#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_GFX_IB_RPTR
+#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_GFX_IB_OFFSET
+#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_GFX_IB_BASE_LO
+#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_GFX_IB_BASE_HI
+#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_GFX_IB_SIZE
+#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_GFX_SKIP_CNTL
+#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
+//SDMA0_GFX_CONTEXT_STATUS
+#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_GFX_DOORBELL
+#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_GFX_CONTEXT_CNTL
+#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
+#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L
+//SDMA0_GFX_STATUS
+#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_GFX_DOORBELL_LOG
+#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA0_GFX_WATERMARK
+#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_GFX_DOORBELL_OFFSET
+#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_GFX_CSA_ADDR_LO
+#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_GFX_CSA_ADDR_HI
+#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_GFX_IB_SUB_REMAIN
+#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA0_GFX_PREEMPT
+#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_GFX_DUMMY_REG
+#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_GFX_RB_AQL_CNTL
+#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA0_GFX_MINOR_PTR_UPDATE
+#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_GFX_MIDCMD_DATA0
+#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA1
+#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA2
+#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA3
+#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA4
+#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA5
+#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA6
+#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA7
+#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA8
+#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_CNTL
+#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_PAGE_RB_CNTL
+#define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL
+#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA0_PAGE_RB_BASE
+#define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_BASE_HI
+#define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_PAGE_RB_RPTR
+#define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_RPTR_HI
+#define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_WPTR
+#define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_WPTR_HI
+#define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_WPTR_POLL_CNTL
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_PAGE_RB_RPTR_ADDR_HI
+#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_RPTR_ADDR_LO
+#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_PAGE_IB_CNTL
+#define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_PAGE_IB_RPTR
+#define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_PAGE_IB_OFFSET
+#define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_PAGE_IB_BASE_LO
+#define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_PAGE_IB_BASE_HI
+#define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_IB_SIZE
+#define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_PAGE_SKIP_CNTL
+#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
+//SDMA0_PAGE_CONTEXT_STATUS
+#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_PAGE_DOORBELL
+#define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_PAGE_STATUS
+#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_PAGE_DOORBELL_LOG
+#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA0_PAGE_WATERMARK
+#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_PAGE_DOORBELL_OFFSET
+#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_PAGE_CSA_ADDR_LO
+#define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_PAGE_CSA_ADDR_HI
+#define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_IB_SUB_REMAIN
+#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA0_PAGE_PREEMPT
+#define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_PAGE_DUMMY_REG
+#define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_PAGE_RB_AQL_CNTL
+#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA0_PAGE_MINOR_PTR_UPDATE
+#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_PAGE_MIDCMD_DATA0
+#define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA1
+#define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA2
+#define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA3
+#define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA4
+#define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA5
+#define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA6
+#define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA7
+#define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA8
+#define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_CNTL
+#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_RLC0_RB_CNTL
+#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL
+#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA0_RLC0_RB_BASE
+#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_BASE_HI
+#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_RLC0_RB_RPTR
+#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_RPTR_HI
+#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_WPTR
+#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_WPTR_HI
+#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_WPTR_POLL_CNTL
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_RLC0_RB_RPTR_ADDR_HI
+#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_RPTR_ADDR_LO
+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC0_IB_CNTL
+#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_RLC0_IB_RPTR
+#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC0_IB_OFFSET
+#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC0_IB_BASE_LO
+#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_RLC0_IB_BASE_HI
+#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_IB_SIZE
+#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC0_SKIP_CNTL
+#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
+//SDMA0_RLC0_CONTEXT_STATUS
+#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_RLC0_DOORBELL
+#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_RLC0_STATUS
+#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_RLC0_DOORBELL_LOG
+#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA0_RLC0_WATERMARK
+#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_RLC0_DOORBELL_OFFSET
+#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_RLC0_CSA_ADDR_LO
+#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC0_CSA_ADDR_HI
+#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_IB_SUB_REMAIN
+#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA0_RLC0_PREEMPT
+#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_RLC0_DUMMY_REG
+#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC0_RB_AQL_CNTL
+#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA0_RLC0_MINOR_PTR_UPDATE
+#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_RLC0_MIDCMD_DATA0
+#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA1
+#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA2
+#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA3
+#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA4
+#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA5
+#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA6
+#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA7
+#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA8
+#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_CNTL
+#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_RLC1_RB_CNTL
+#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL
+#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA0_RLC1_RB_BASE
+#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_BASE_HI
+#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_RLC1_RB_RPTR
+#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_RPTR_HI
+#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_WPTR
+#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_WPTR_HI
+#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_WPTR_POLL_CNTL
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_RLC1_RB_RPTR_ADDR_HI
+#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_RPTR_ADDR_LO
+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC1_IB_CNTL
+#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_RLC1_IB_RPTR
+#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC1_IB_OFFSET
+#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC1_IB_BASE_LO
+#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_RLC1_IB_BASE_HI
+#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_IB_SIZE
+#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC1_SKIP_CNTL
+#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
+//SDMA0_RLC1_CONTEXT_STATUS
+#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_RLC1_DOORBELL
+#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_RLC1_STATUS
+#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_RLC1_DOORBELL_LOG
+#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA0_RLC1_WATERMARK
+#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_RLC1_DOORBELL_OFFSET
+#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_RLC1_CSA_ADDR_LO
+#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC1_CSA_ADDR_HI
+#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_IB_SUB_REMAIN
+#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA0_RLC1_PREEMPT
+#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_RLC1_DUMMY_REG
+#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC1_RB_AQL_CNTL
+#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA0_RLC1_MINOR_PTR_UPDATE
+#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_RLC1_MIDCMD_DATA0
+#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA1
+#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA2
+#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA3
+#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA4
+#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA5
+#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA6
+#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA7
+#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA8
+#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_CNTL
+#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h
new file mode 100644
index 000000000000..85c5c5e3ce7d
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h
@@ -0,0 +1,282 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _sdma1_4_0_DEFAULT_HEADER
+#define _sdma1_4_0_DEFAULT_HEADER
+
+
+// addressBlock: sdma1_sdma1dec
+#define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000
+#define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000
+#define mmSDMA1_VM_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000
+#define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000
+#define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000
+#define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000
+#define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000
+#define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
+#define mmSDMA1_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff
+#define mmSDMA1_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff
+#define mmSDMA1_CONTEXT_REG_TYPE3_DEFAULT 0x00000000
+#define mmSDMA1_PUB_REG_TYPE0_DEFAULT 0x3c000000
+#define mmSDMA1_PUB_REG_TYPE1_DEFAULT 0x30003882
+#define mmSDMA1_PUB_REG_TYPE2_DEFAULT 0x0fc6e880
+#define mmSDMA1_PUB_REG_TYPE3_DEFAULT 0x00000000
+#define mmSDMA1_MMHUB_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000
+#define mmSDMA1_POWER_CNTL_DEFAULT 0x0003c000
+#define mmSDMA1_CLK_CTRL_DEFAULT 0xff000100
+#define mmSDMA1_CNTL_DEFAULT 0x00000002
+#define mmSDMA1_CHICKEN_BITS_DEFAULT 0x00831f07
+#define mmSDMA1_GB_ADDR_CONFIG_DEFAULT 0x00100012
+#define mmSDMA1_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012
+#define mmSDMA1_RB_RPTR_FETCH_HI_DEFAULT 0x00000000
+#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RB_RPTR_FETCH_DEFAULT 0x00000000
+#define mmSDMA1_IB_OFFSET_FETCH_DEFAULT 0x00000000
+#define mmSDMA1_PROGRAM_DEFAULT 0x00000000
+#define mmSDMA1_STATUS_REG_DEFAULT 0x46dee557
+#define mmSDMA1_STATUS1_REG_DEFAULT 0x000003ff
+#define mmSDMA1_RD_BURST_CNTL_DEFAULT 0x00000003
+#define mmSDMA1_HBM_PAGE_CONFIG_DEFAULT 0x00000000
+#define mmSDMA1_UCODE_CHECKSUM_DEFAULT 0x00000000
+#define mmSDMA1_F32_CNTL_DEFAULT 0x00000001
+#define mmSDMA1_FREEZE_DEFAULT 0x00000000
+#define mmSDMA1_PHASE0_QUANTUM_DEFAULT 0x00010002
+#define mmSDMA1_PHASE1_QUANTUM_DEFAULT 0x00010002
+#define mmSDMA1_EDC_CONFIG_DEFAULT 0x00000002
+#define mmSDMA1_BA_THRESHOLD_DEFAULT 0x03ff03ff
+#define mmSDMA1_ID_DEFAULT 0x00000001
+#define mmSDMA1_VERSION_DEFAULT 0x00000400
+#define mmSDMA1_EDC_COUNTER_DEFAULT 0x00000000
+#define mmSDMA1_EDC_COUNTER_CLEAR_DEFAULT 0x00000000
+#define mmSDMA1_STATUS2_REG_DEFAULT 0x00000001
+#define mmSDMA1_ATOMIC_CNTL_DEFAULT 0x00000200
+#define mmSDMA1_ATOMIC_PREOP_LO_DEFAULT 0x00000000
+#define mmSDMA1_ATOMIC_PREOP_HI_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_CNTL_DEFAULT 0xd0003019
+#define mmSDMA1_UTCL1_WATERMK_DEFAULT 0xfffbe1fe
+#define mmSDMA1_UTCL1_RD_STATUS_DEFAULT 0x201001ff
+#define mmSDMA1_UTCL1_WR_STATUS_DEFAULT 0x503001ff
+#define mmSDMA1_UTCL1_INV0_DEFAULT 0x00000600
+#define mmSDMA1_UTCL1_INV1_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_INV2_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_RD_XNACK0_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_RD_XNACK1_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_WR_XNACK0_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_WR_XNACK1_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_TIMEOUT_DEFAULT 0x00010001
+#define mmSDMA1_UTCL1_PAGE_DEFAULT 0x000003e0
+#define mmSDMA1_POWER_CNTL_IDLE_DEFAULT 0x06060200
+#define mmSDMA1_RELAX_ORDERING_LUT_DEFAULT 0xc0000006
+#define mmSDMA1_CHICKEN_BITS_2_DEFAULT 0x00000005
+#define mmSDMA1_STATUS3_REG_DEFAULT 0x00100000
+#define mmSDMA1_PHYSICAL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_PHYSICAL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_PHASE2_QUANTUM_DEFAULT 0x00010002
+#define mmSDMA1_ERROR_LOG_DEFAULT 0x0000000f
+#define mmSDMA1_PUB_DUMMY_REG0_DEFAULT 0x00000000
+#define mmSDMA1_PUB_DUMMY_REG1_DEFAULT 0x00000000
+#define mmSDMA1_PUB_DUMMY_REG2_DEFAULT 0x00000000
+#define mmSDMA1_PUB_DUMMY_REG3_DEFAULT 0x00000000
+#define mmSDMA1_F32_COUNTER_DEFAULT 0x00000000
+#define mmSDMA1_UNBREAKABLE_DEFAULT 0x00000000
+#define mmSDMA1_PERFMON_CNTL_DEFAULT 0x000ff7fd
+#define mmSDMA1_PERFCOUNTER0_RESULT_DEFAULT 0x00000000
+#define mmSDMA1_PERFCOUNTER1_RESULT_DEFAULT 0x00000000
+#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000
+#define mmSDMA1_CRD_CNTL_DEFAULT 0x000085c0
+#define mmSDMA1_MMHUB_TRUSTLVL_DEFAULT 0x00000000
+#define mmSDMA1_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000
+#define mmSDMA1_ULV_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000
+#define mmSDMA1_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_CNTL_DEFAULT 0x00040000
+#define mmSDMA1_GFX_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_GFX_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA1_GFX_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_GFX_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_GFX_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA1_GFX_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA1_GFX_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_GFX_CONTEXT_STATUS_DEFAULT 0x00000005
+#define mmSDMA1_GFX_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA1_GFX_CONTEXT_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_GFX_STATUS_DEFAULT 0x00000000
+#define mmSDMA1_GFX_DOORBELL_LOG_DEFAULT 0x00000000
+#define mmSDMA1_GFX_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA1_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_GFX_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_GFX_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA1_GFX_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA1_GFX_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA1_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_CNTL_DEFAULT 0x00040000
+#define mmSDMA1_PAGE_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA1_PAGE_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA1_PAGE_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_STATUS_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_DOORBELL_LOG_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_CNTL_DEFAULT 0x00040000
+#define mmSDMA1_RLC0_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA1_RLC0_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA1_RLC0_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_STATUS_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_DOORBELL_LOG_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_CNTL_DEFAULT 0x00040000
+#define mmSDMA1_RLC1_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA1_RLC1_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA1_RLC1_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_STATUS_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_DOORBELL_LOG_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h
new file mode 100644
index 000000000000..92150d6b65b8
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h
@@ -0,0 +1,539 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _sdma1_4_0_OFFSET_HEADER
+#define _sdma1_4_0_OFFSET_HEADER
+
+
+
+// addressBlock: sdma1_sdma1dec
+// base address: 0x5180
+#define mmSDMA1_UCODE_ADDR 0x0000
+#define mmSDMA1_UCODE_ADDR_BASE_IDX 0
+#define mmSDMA1_UCODE_DATA 0x0001
+#define mmSDMA1_UCODE_DATA_BASE_IDX 0
+#define mmSDMA1_VM_CNTL 0x0004
+#define mmSDMA1_VM_CNTL_BASE_IDX 0
+#define mmSDMA1_VM_CTX_LO 0x0005
+#define mmSDMA1_VM_CTX_LO_BASE_IDX 0
+#define mmSDMA1_VM_CTX_HI 0x0006
+#define mmSDMA1_VM_CTX_HI_BASE_IDX 0
+#define mmSDMA1_ACTIVE_FCN_ID 0x0007
+#define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX 0
+#define mmSDMA1_VM_CTX_CNTL 0x0008
+#define mmSDMA1_VM_CTX_CNTL_BASE_IDX 0
+#define mmSDMA1_VIRT_RESET_REQ 0x0009
+#define mmSDMA1_VIRT_RESET_REQ_BASE_IDX 0
+#define mmSDMA1_VF_ENABLE 0x000a
+#define mmSDMA1_VF_ENABLE_BASE_IDX 0
+#define mmSDMA1_CONTEXT_REG_TYPE0 0x000b
+#define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX 0
+#define mmSDMA1_CONTEXT_REG_TYPE1 0x000c
+#define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX 0
+#define mmSDMA1_CONTEXT_REG_TYPE2 0x000d
+#define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX 0
+#define mmSDMA1_CONTEXT_REG_TYPE3 0x000e
+#define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX 0
+#define mmSDMA1_PUB_REG_TYPE0 0x000f
+#define mmSDMA1_PUB_REG_TYPE0_BASE_IDX 0
+#define mmSDMA1_PUB_REG_TYPE1 0x0010
+#define mmSDMA1_PUB_REG_TYPE1_BASE_IDX 0
+#define mmSDMA1_PUB_REG_TYPE2 0x0011
+#define mmSDMA1_PUB_REG_TYPE2_BASE_IDX 0
+#define mmSDMA1_PUB_REG_TYPE3 0x0012
+#define mmSDMA1_PUB_REG_TYPE3_BASE_IDX 0
+#define mmSDMA1_MMHUB_CNTL 0x0013
+#define mmSDMA1_MMHUB_CNTL_BASE_IDX 0
+#define mmSDMA1_CONTEXT_GROUP_BOUNDARY 0x0019
+#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0
+#define mmSDMA1_POWER_CNTL 0x001a
+#define mmSDMA1_POWER_CNTL_BASE_IDX 0
+#define mmSDMA1_CLK_CTRL 0x001b
+#define mmSDMA1_CLK_CTRL_BASE_IDX 0
+#define mmSDMA1_CNTL 0x001c
+#define mmSDMA1_CNTL_BASE_IDX 0
+#define mmSDMA1_CHICKEN_BITS 0x001d
+#define mmSDMA1_CHICKEN_BITS_BASE_IDX 0
+#define mmSDMA1_GB_ADDR_CONFIG 0x001e
+#define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX 0
+#define mmSDMA1_GB_ADDR_CONFIG_READ 0x001f
+#define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0
+#define mmSDMA1_RB_RPTR_FETCH_HI 0x0020
+#define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0
+#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0021
+#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0
+#define mmSDMA1_RB_RPTR_FETCH 0x0022
+#define mmSDMA1_RB_RPTR_FETCH_BASE_IDX 0
+#define mmSDMA1_IB_OFFSET_FETCH 0x0023
+#define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX 0
+#define mmSDMA1_PROGRAM 0x0024
+#define mmSDMA1_PROGRAM_BASE_IDX 0
+#define mmSDMA1_STATUS_REG 0x0025
+#define mmSDMA1_STATUS_REG_BASE_IDX 0
+#define mmSDMA1_STATUS1_REG 0x0026
+#define mmSDMA1_STATUS1_REG_BASE_IDX 0
+#define mmSDMA1_RD_BURST_CNTL 0x0027
+#define mmSDMA1_RD_BURST_CNTL_BASE_IDX 0
+#define mmSDMA1_HBM_PAGE_CONFIG 0x0028
+#define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0
+#define mmSDMA1_UCODE_CHECKSUM 0x0029
+#define mmSDMA1_UCODE_CHECKSUM_BASE_IDX 0
+#define mmSDMA1_F32_CNTL 0x002a
+#define mmSDMA1_F32_CNTL_BASE_IDX 0
+#define mmSDMA1_FREEZE 0x002b
+#define mmSDMA1_FREEZE_BASE_IDX 0
+#define mmSDMA1_PHASE0_QUANTUM 0x002c
+#define mmSDMA1_PHASE0_QUANTUM_BASE_IDX 0
+#define mmSDMA1_PHASE1_QUANTUM 0x002d
+#define mmSDMA1_PHASE1_QUANTUM_BASE_IDX 0
+#define mmSDMA1_EDC_CONFIG 0x0032
+#define mmSDMA1_EDC_CONFIG_BASE_IDX 0
+#define mmSDMA1_BA_THRESHOLD 0x0033
+#define mmSDMA1_BA_THRESHOLD_BASE_IDX 0
+#define mmSDMA1_ID 0x0034
+#define mmSDMA1_ID_BASE_IDX 0
+#define mmSDMA1_VERSION 0x0035
+#define mmSDMA1_VERSION_BASE_IDX 0
+#define mmSDMA1_EDC_COUNTER 0x0036
+#define mmSDMA1_EDC_COUNTER_BASE_IDX 0
+#define mmSDMA1_EDC_COUNTER_CLEAR 0x0037
+#define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX 0
+#define mmSDMA1_STATUS2_REG 0x0038
+#define mmSDMA1_STATUS2_REG_BASE_IDX 0
+#define mmSDMA1_ATOMIC_CNTL 0x0039
+#define mmSDMA1_ATOMIC_CNTL_BASE_IDX 0
+#define mmSDMA1_ATOMIC_PREOP_LO 0x003a
+#define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0
+#define mmSDMA1_ATOMIC_PREOP_HI 0x003b
+#define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0
+#define mmSDMA1_UTCL1_CNTL 0x003c
+#define mmSDMA1_UTCL1_CNTL_BASE_IDX 0
+#define mmSDMA1_UTCL1_WATERMK 0x003d
+#define mmSDMA1_UTCL1_WATERMK_BASE_IDX 0
+#define mmSDMA1_UTCL1_RD_STATUS 0x003e
+#define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX 0
+#define mmSDMA1_UTCL1_WR_STATUS 0x003f
+#define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX 0
+#define mmSDMA1_UTCL1_INV0 0x0040
+#define mmSDMA1_UTCL1_INV0_BASE_IDX 0
+#define mmSDMA1_UTCL1_INV1 0x0041
+#define mmSDMA1_UTCL1_INV1_BASE_IDX 0
+#define mmSDMA1_UTCL1_INV2 0x0042
+#define mmSDMA1_UTCL1_INV2_BASE_IDX 0
+#define mmSDMA1_UTCL1_RD_XNACK0 0x0043
+#define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0
+#define mmSDMA1_UTCL1_RD_XNACK1 0x0044
+#define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0
+#define mmSDMA1_UTCL1_WR_XNACK0 0x0045
+#define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0
+#define mmSDMA1_UTCL1_WR_XNACK1 0x0046
+#define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0
+#define mmSDMA1_UTCL1_TIMEOUT 0x0047
+#define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX 0
+#define mmSDMA1_UTCL1_PAGE 0x0048
+#define mmSDMA1_UTCL1_PAGE_BASE_IDX 0
+#define mmSDMA1_POWER_CNTL_IDLE 0x0049
+#define mmSDMA1_POWER_CNTL_IDLE_BASE_IDX 0
+#define mmSDMA1_RELAX_ORDERING_LUT 0x004a
+#define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0
+#define mmSDMA1_CHICKEN_BITS_2 0x004b
+#define mmSDMA1_CHICKEN_BITS_2_BASE_IDX 0
+#define mmSDMA1_STATUS3_REG 0x004c
+#define mmSDMA1_STATUS3_REG_BASE_IDX 0
+#define mmSDMA1_PHYSICAL_ADDR_LO 0x004d
+#define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_PHYSICAL_ADDR_HI 0x004e
+#define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_PHASE2_QUANTUM 0x004f
+#define mmSDMA1_PHASE2_QUANTUM_BASE_IDX 0
+#define mmSDMA1_ERROR_LOG 0x0050
+#define mmSDMA1_ERROR_LOG_BASE_IDX 0
+#define mmSDMA1_PUB_DUMMY_REG0 0x0051
+#define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX 0
+#define mmSDMA1_PUB_DUMMY_REG1 0x0052
+#define mmSDMA1_PUB_DUMMY_REG1_BASE_IDX 0
+#define mmSDMA1_PUB_DUMMY_REG2 0x0053
+#define mmSDMA1_PUB_DUMMY_REG2_BASE_IDX 0
+#define mmSDMA1_PUB_DUMMY_REG3 0x0054
+#define mmSDMA1_PUB_DUMMY_REG3_BASE_IDX 0
+#define mmSDMA1_F32_COUNTER 0x0055
+#define mmSDMA1_F32_COUNTER_BASE_IDX 0
+#define mmSDMA1_UNBREAKABLE 0x0056
+#define mmSDMA1_UNBREAKABLE_BASE_IDX 0
+#define mmSDMA1_PERFMON_CNTL 0x0057
+#define mmSDMA1_PERFMON_CNTL_BASE_IDX 0
+#define mmSDMA1_PERFCOUNTER0_RESULT 0x0058
+#define mmSDMA1_PERFCOUNTER0_RESULT_BASE_IDX 0
+#define mmSDMA1_PERFCOUNTER1_RESULT 0x0059
+#define mmSDMA1_PERFCOUNTER1_RESULT_BASE_IDX 0
+#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE 0x005a
+#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0
+#define mmSDMA1_CRD_CNTL 0x005b
+#define mmSDMA1_CRD_CNTL_BASE_IDX 0
+#define mmSDMA1_MMHUB_TRUSTLVL 0x005c
+#define mmSDMA1_MMHUB_TRUSTLVL_BASE_IDX 0
+#define mmSDMA1_GPU_IOV_VIOLATION_LOG 0x005d
+#define mmSDMA1_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
+#define mmSDMA1_ULV_CNTL 0x005e
+#define mmSDMA1_ULV_CNTL_BASE_IDX 0
+#define mmSDMA1_EA_DBIT_ADDR_DATA 0x0060
+#define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0
+#define mmSDMA1_EA_DBIT_ADDR_INDEX 0x0061
+#define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0
+#define mmSDMA1_GFX_RB_CNTL 0x0080
+#define mmSDMA1_GFX_RB_CNTL_BASE_IDX 0
+#define mmSDMA1_GFX_RB_BASE 0x0081
+#define mmSDMA1_GFX_RB_BASE_BASE_IDX 0
+#define mmSDMA1_GFX_RB_BASE_HI 0x0082
+#define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_GFX_RB_RPTR 0x0083
+#define mmSDMA1_GFX_RB_RPTR_BASE_IDX 0
+#define mmSDMA1_GFX_RB_RPTR_HI 0x0084
+#define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA1_GFX_RB_WPTR 0x0085
+#define mmSDMA1_GFX_RB_WPTR_BASE_IDX 0
+#define mmSDMA1_GFX_RB_WPTR_HI 0x0086
+#define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087
+#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x0088
+#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x0089
+#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_GFX_IB_CNTL 0x008a
+#define mmSDMA1_GFX_IB_CNTL_BASE_IDX 0
+#define mmSDMA1_GFX_IB_RPTR 0x008b
+#define mmSDMA1_GFX_IB_RPTR_BASE_IDX 0
+#define mmSDMA1_GFX_IB_OFFSET 0x008c
+#define mmSDMA1_GFX_IB_OFFSET_BASE_IDX 0
+#define mmSDMA1_GFX_IB_BASE_LO 0x008d
+#define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA1_GFX_IB_BASE_HI 0x008e
+#define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_GFX_IB_SIZE 0x008f
+#define mmSDMA1_GFX_IB_SIZE_BASE_IDX 0
+#define mmSDMA1_GFX_SKIP_CNTL 0x0090
+#define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA1_GFX_CONTEXT_STATUS 0x0091
+#define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA1_GFX_DOORBELL 0x0092
+#define mmSDMA1_GFX_DOORBELL_BASE_IDX 0
+#define mmSDMA1_GFX_CONTEXT_CNTL 0x0093
+#define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX 0
+#define mmSDMA1_GFX_STATUS 0x00a8
+#define mmSDMA1_GFX_STATUS_BASE_IDX 0
+#define mmSDMA1_GFX_DOORBELL_LOG 0x00a9
+#define mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX 0
+#define mmSDMA1_GFX_WATERMARK 0x00aa
+#define mmSDMA1_GFX_WATERMARK_BASE_IDX 0
+#define mmSDMA1_GFX_DOORBELL_OFFSET 0x00ab
+#define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA1_GFX_CSA_ADDR_LO 0x00ac
+#define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_GFX_CSA_ADDR_HI 0x00ad
+#define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_GFX_IB_SUB_REMAIN 0x00af
+#define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA1_GFX_PREEMPT 0x00b0
+#define mmSDMA1_GFX_PREEMPT_BASE_IDX 0
+#define mmSDMA1_GFX_DUMMY_REG 0x00b1
+#define mmSDMA1_GFX_DUMMY_REG_BASE_IDX 0
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_GFX_RB_AQL_CNTL 0x00b4
+#define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA1_GFX_MINOR_PTR_UPDATE 0x00b5
+#define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA0 0x00c0
+#define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA1 0x00c1
+#define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA2 0x00c2
+#define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA3 0x00c3
+#define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA4 0x00c4
+#define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA5 0x00c5
+#define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA6 0x00c6
+#define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA7 0x00c7
+#define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA8 0x00c8
+#define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_CNTL 0x00c9
+#define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_CNTL 0x00e0
+#define mmSDMA1_PAGE_RB_CNTL_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_BASE 0x00e1
+#define mmSDMA1_PAGE_RB_BASE_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_BASE_HI 0x00e2
+#define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_RPTR 0x00e3
+#define mmSDMA1_PAGE_RB_RPTR_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_RPTR_HI 0x00e4
+#define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_WPTR 0x00e5
+#define mmSDMA1_PAGE_RB_WPTR_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_WPTR_HI 0x00e6
+#define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x00e7
+#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI 0x00e8
+#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO 0x00e9
+#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_PAGE_IB_CNTL 0x00ea
+#define mmSDMA1_PAGE_IB_CNTL_BASE_IDX 0
+#define mmSDMA1_PAGE_IB_RPTR 0x00eb
+#define mmSDMA1_PAGE_IB_RPTR_BASE_IDX 0
+#define mmSDMA1_PAGE_IB_OFFSET 0x00ec
+#define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX 0
+#define mmSDMA1_PAGE_IB_BASE_LO 0x00ed
+#define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA1_PAGE_IB_BASE_HI 0x00ee
+#define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_PAGE_IB_SIZE 0x00ef
+#define mmSDMA1_PAGE_IB_SIZE_BASE_IDX 0
+#define mmSDMA1_PAGE_SKIP_CNTL 0x00f0
+#define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA1_PAGE_CONTEXT_STATUS 0x00f1
+#define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA1_PAGE_DOORBELL 0x00f2
+#define mmSDMA1_PAGE_DOORBELL_BASE_IDX 0
+#define mmSDMA1_PAGE_STATUS 0x0108
+#define mmSDMA1_PAGE_STATUS_BASE_IDX 0
+#define mmSDMA1_PAGE_DOORBELL_LOG 0x0109
+#define mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX 0
+#define mmSDMA1_PAGE_WATERMARK 0x010a
+#define mmSDMA1_PAGE_WATERMARK_BASE_IDX 0
+#define mmSDMA1_PAGE_DOORBELL_OFFSET 0x010b
+#define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA1_PAGE_CSA_ADDR_LO 0x010c
+#define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_PAGE_CSA_ADDR_HI 0x010d
+#define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_PAGE_IB_SUB_REMAIN 0x010f
+#define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA1_PAGE_PREEMPT 0x0110
+#define mmSDMA1_PAGE_PREEMPT_BASE_IDX 0
+#define mmSDMA1_PAGE_DUMMY_REG 0x0111
+#define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112
+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113
+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_AQL_CNTL 0x0114
+#define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA1_PAGE_MINOR_PTR_UPDATE 0x0115
+#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA0 0x0120
+#define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA1 0x0121
+#define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA2 0x0122
+#define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA3 0x0123
+#define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA4 0x0124
+#define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA5 0x0125
+#define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA6 0x0126
+#define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA7 0x0127
+#define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA8 0x0128
+#define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_CNTL 0x0129
+#define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_CNTL 0x0140
+#define mmSDMA1_RLC0_RB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_BASE 0x0141
+#define mmSDMA1_RLC0_RB_BASE_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_BASE_HI 0x0142
+#define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_RPTR 0x0143
+#define mmSDMA1_RLC0_RB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_RPTR_HI 0x0144
+#define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_WPTR 0x0145
+#define mmSDMA1_RLC0_RB_WPTR_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_WPTR_HI 0x0146
+#define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0147
+#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x0148
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x0149
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC0_IB_CNTL 0x014a
+#define mmSDMA1_RLC0_IB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC0_IB_RPTR 0x014b
+#define mmSDMA1_RLC0_IB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC0_IB_OFFSET 0x014c
+#define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC0_IB_BASE_LO 0x014d
+#define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA1_RLC0_IB_BASE_HI 0x014e
+#define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC0_IB_SIZE 0x014f
+#define mmSDMA1_RLC0_IB_SIZE_BASE_IDX 0
+#define mmSDMA1_RLC0_SKIP_CNTL 0x0150
+#define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC0_CONTEXT_STATUS 0x0151
+#define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC0_DOORBELL 0x0152
+#define mmSDMA1_RLC0_DOORBELL_BASE_IDX 0
+#define mmSDMA1_RLC0_STATUS 0x0168
+#define mmSDMA1_RLC0_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC0_DOORBELL_LOG 0x0169
+#define mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX 0
+#define mmSDMA1_RLC0_WATERMARK 0x016a
+#define mmSDMA1_RLC0_WATERMARK_BASE_IDX 0
+#define mmSDMA1_RLC0_DOORBELL_OFFSET 0x016b
+#define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC0_CSA_ADDR_LO 0x016c
+#define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC0_CSA_ADDR_HI 0x016d
+#define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x016f
+#define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA1_RLC0_PREEMPT 0x0170
+#define mmSDMA1_RLC0_PREEMPT_BASE_IDX 0
+#define mmSDMA1_RLC0_DUMMY_REG 0x0171
+#define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_AQL_CNTL 0x0174
+#define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC0_MINOR_PTR_UPDATE 0x0175
+#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA0 0x0180
+#define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA1 0x0181
+#define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA2 0x0182
+#define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA3 0x0183
+#define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA4 0x0184
+#define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA5 0x0185
+#define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA6 0x0186
+#define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA7 0x0187
+#define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA8 0x0188
+#define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_CNTL 0x0189
+#define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_CNTL 0x01a0
+#define mmSDMA1_RLC1_RB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_BASE 0x01a1
+#define mmSDMA1_RLC1_RB_BASE_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_BASE_HI 0x01a2
+#define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_RPTR 0x01a3
+#define mmSDMA1_RLC1_RB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_RPTR_HI 0x01a4
+#define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_WPTR 0x01a5
+#define mmSDMA1_RLC1_RB_WPTR_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_WPTR_HI 0x01a6
+#define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x01a7
+#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x01a8
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x01a9
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC1_IB_CNTL 0x01aa
+#define mmSDMA1_RLC1_IB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC1_IB_RPTR 0x01ab
+#define mmSDMA1_RLC1_IB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC1_IB_OFFSET 0x01ac
+#define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC1_IB_BASE_LO 0x01ad
+#define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA1_RLC1_IB_BASE_HI 0x01ae
+#define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC1_IB_SIZE 0x01af
+#define mmSDMA1_RLC1_IB_SIZE_BASE_IDX 0
+#define mmSDMA1_RLC1_SKIP_CNTL 0x01b0
+#define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC1_CONTEXT_STATUS 0x01b1
+#define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC1_DOORBELL 0x01b2
+#define mmSDMA1_RLC1_DOORBELL_BASE_IDX 0
+#define mmSDMA1_RLC1_STATUS 0x01c8
+#define mmSDMA1_RLC1_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC1_DOORBELL_LOG 0x01c9
+#define mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX 0
+#define mmSDMA1_RLC1_WATERMARK 0x01ca
+#define mmSDMA1_RLC1_WATERMARK_BASE_IDX 0
+#define mmSDMA1_RLC1_DOORBELL_OFFSET 0x01cb
+#define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC1_CSA_ADDR_LO 0x01cc
+#define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC1_CSA_ADDR_HI 0x01cd
+#define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x01cf
+#define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA1_RLC1_PREEMPT 0x01d0
+#define mmSDMA1_RLC1_PREEMPT_BASE_IDX 0
+#define mmSDMA1_RLC1_DUMMY_REG 0x01d1
+#define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_AQL_CNTL 0x01d4
+#define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC1_MINOR_PTR_UPDATE 0x01d5
+#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA0 0x01e0
+#define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA1 0x01e1
+#define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA2 0x01e2
+#define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA3 0x01e3
+#define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA4 0x01e4
+#define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA5 0x01e5
+#define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA6 0x01e6
+#define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA7 0x01e7
+#define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA8 0x01e8
+#define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_CNTL 0x01e9
+#define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h
new file mode 100644
index 000000000000..25decdf96d16
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h
@@ -0,0 +1,1810 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _sdma1_4_0_SH_MASK_HEADER
+#define _sdma1_4_0_SH_MASK_HEADER
+
+
+// addressBlock: sdma1_sdma1dec
+//SDMA1_UCODE_ADDR
+#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0
+#define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001FFFL
+//SDMA1_UCODE_DATA
+#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0
+#define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_VM_CNTL
+#define SDMA1_VM_CNTL__CMD__SHIFT 0x0
+#define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL
+//SDMA1_VM_CTX_LO
+#define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2
+#define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_VM_CTX_HI
+#define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0
+#define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_ACTIVE_FCN_ID
+#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
+#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
+#define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L
+#define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//SDMA1_VM_CTX_CNTL
+#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0
+#define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4
+#define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L
+#define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000F0L
+//SDMA1_VIRT_RESET_REQ
+#define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define SDMA1_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
+#define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L
+//SDMA1_VF_ENABLE
+#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
+//SDMA1_CONTEXT_REG_TYPE0
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT 0x4
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x5
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT 0x6
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x00000001L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x00000002L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x00000004L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x00000008L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK 0x00000010L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x00000020L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK 0x00000040L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x00000400L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x00000800L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x00001000L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x00002000L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x00004000L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x00008000L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x00010000L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x00020000L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x00040000L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x00080000L
+//SDMA1_CONTEXT_REG_TYPE1
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT 0x8
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT 0xb
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd
+#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT 0x14
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT 0x15
+#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK 0x00000100L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x00000200L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x00000400L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK 0x00000800L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x00001000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x00002000L
+#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x00008000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x00010000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x00020000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK 0x00100000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L
+#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L
+//SDMA1_CONTEXT_REG_TYPE2
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9
+#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x00000001L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x00000002L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x00000004L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x00000008L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x00000010L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x00000020L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x00000040L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x00000080L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x00000100L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x00000200L
+#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L
+//SDMA1_CONTEXT_REG_TYPE3
+#define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0
+#define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL
+//SDMA1_PUB_REG_TYPE0
+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0
+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1
+#define SDMA1_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL__SHIFT 0x4
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO__SHIFT 0x5
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI__SHIFT 0x6
+#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID__SHIFT 0x7
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL__SHIFT 0x8
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ__SHIFT 0x9
+#define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0__SHIFT 0xb
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1__SHIFT 0xc
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2__SHIFT 0xd
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3__SHIFT 0xe
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0__SHIFT 0xf
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1__SHIFT 0x10
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2__SHIFT 0x11
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3__SHIFT 0x12
+#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL__SHIFT 0x13
+#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19
+#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x1a
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x1b
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x1c
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d
+#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT 0x1e
+#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT 0x1f
+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L
+#define SDMA1_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL_MASK 0x00000010L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO_MASK 0x00000020L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI_MASK 0x00000040L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID_MASK 0x00000080L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL_MASK 0x00000100L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ_MASK 0x00000200L
+#define SDMA1_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0_MASK 0x00000800L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1_MASK 0x00001000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2_MASK 0x00002000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3_MASK 0x00004000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0_MASK 0x00008000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1_MASK 0x00010000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2_MASK 0x00020000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3_MASK 0x00040000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL_MASK 0x00080000L
+#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x04000000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x08000000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10000000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20000000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK 0x40000000L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK 0x80000000L
+//SDMA1_PUB_REG_TYPE1
+#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT 0x0
+#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1
+#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT 0x2
+#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT 0x3
+#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT 0x4
+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT 0x5
+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT 0x6
+#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL__SHIFT 0x7
+#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT 0x8
+#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT 0x9
+#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa
+#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT 0xb
+#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM__SHIFT 0xc
+#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM__SHIFT 0xd
+#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe
+#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf
+#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10
+#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11
+#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT 0x12
+#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT 0x13
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT 0x14
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT 0x15
+#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT 0x16
+#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT 0x17
+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x18
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x19
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x1a
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0x1b
+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT 0x1c
+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d
+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS__SHIFT 0x1e
+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS__SHIFT 0x1f
+#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK 0x00000001L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK 0x00000004L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK 0x00000008L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK 0x00000010L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK 0x00000020L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK 0x00000040L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL_MASK 0x00000080L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK 0x00000100L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK 0x00000200L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL_MASK 0x00000400L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK 0x00000800L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM_MASK 0x00001000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM_MASK 0x00002000L
+#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L
+#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L
+#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L
+#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK 0x00040000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK 0x00080000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK 0x00100000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK 0x00200000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK 0x00400000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK 0x00800000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x01000000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x02000000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x04000000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x08000000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK 0x10000000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK 0x20000000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS_MASK 0x40000000L
+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS_MASK 0x80000000L
+//SDMA1_PUB_REG_TYPE2
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT 0x0
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT 0x1
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT 0x2
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT 0x3
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT 0x4
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT 0x5
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT 0x6
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT__SHIFT 0x7
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE__SHIFT 0x8
+#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE__SHIFT 0x9
+#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa
+#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT 0xb
+#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT 0xc
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT 0xd
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT 0xe
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM__SHIFT 0xf
+#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT 0x10
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT 0x11
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT 0x12
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT 0x13
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT 0x14
+#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT 0x15
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE__SHIFT 0x16
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL__SHIFT 0x17
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x18
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x19
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a
+#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT 0x1b
+#define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL__SHIFT 0x1c
+#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
+#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL__SHIFT 0x1e
+#define SDMA1_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK 0x00000001L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK 0x00000002L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK 0x00000004L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK 0x00000008L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK 0x00000010L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK 0x00000020L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK 0x00000040L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT_MASK 0x00000080L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE_MASK 0x00000100L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE_MASK 0x00000200L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK 0x00000400L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK 0x00000800L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK 0x00001000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK 0x00002000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK 0x00004000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM_MASK 0x00008000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK 0x00010000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK 0x00020000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK 0x00040000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK 0x00080000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK 0x00100000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK 0x00200000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE_MASK 0x00400000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL_MASK 0x00800000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT_MASK 0x01000000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT_MASK 0x02000000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK 0x08000000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL_MASK 0x10000000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L
+#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL_MASK 0x40000000L
+#define SDMA1_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L
+//SDMA1_PUB_REG_TYPE3
+#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT 0x0
+#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT 0x1
+#define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT 0x2
+#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK 0x00000001L
+#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK 0x00000002L
+#define SDMA1_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL
+//SDMA1_MMHUB_CNTL
+#define SDMA1_MMHUB_CNTL__UNIT_ID__SHIFT 0x0
+#define SDMA1_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL
+//SDMA1_CONTEXT_GROUP_BOUNDARY
+#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0
+#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL
+//SDMA1_POWER_CNTL
+#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
+#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
+#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
+#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
+#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
+#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L
+#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L
+#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L
+#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L
+#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L
+//SDMA1_CLK_CTRL
+#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define SDMA1_CLK_CTRL__RESERVED_MASK 0x00FFF000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//SDMA1_CNTL
+#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0
+#define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1
+#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
+#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
+#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
+#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
+#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
+#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
+#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
+#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
+#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L
+#define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L
+#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L
+#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L
+#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L
+#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L
+#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L
+#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L
+#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L
+#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L
+//SDMA1_CHICKEN_BITS
+#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
+#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
+#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
+#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8
+#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
+#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
+#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11
+#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
+#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
+#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19
+#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
+#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
+#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
+#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L
+#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L
+#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L
+#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L
+#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L
+#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L
+#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L
+#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L
+#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L
+#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L
+#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L
+#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L
+#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L
+//SDMA1_GB_ADDR_CONFIG
+#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA1_GB_ADDR_CONFIG_READ
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
+#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
+#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA1_RB_RPTR_FETCH_HI
+#define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_SEM_WAIT_FAIL_TIMER_CNTL
+#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
+#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL
+//SDMA1_RB_RPTR_FETCH
+#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
+#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL
+//SDMA1_IB_OFFSET_FETCH
+#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
+#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL
+//SDMA1_PROGRAM
+#define SDMA1_PROGRAM__STREAM__SHIFT 0x0
+#define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL
+//SDMA1_STATUS_REG
+#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0
+#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
+#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2
+#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3
+#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
+#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
+#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
+#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
+#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
+#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9
+#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
+#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
+#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc
+#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
+#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe
+#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
+#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
+#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
+#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
+#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
+#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
+#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
+#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
+#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
+#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a
+#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
+#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
+#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e
+#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
+#define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L
+#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L
+#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L
+#define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L
+#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L
+#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L
+#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L
+#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L
+#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L
+#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L
+#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L
+#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L
+#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L
+#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L
+#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L
+#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L
+#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L
+#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L
+#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L
+#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L
+#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L
+#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L
+#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L
+#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L
+#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L
+#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L
+#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L
+#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L
+#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L
+//SDMA1_STATUS1_REG
+#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
+#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
+#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
+#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
+#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
+#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
+#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
+#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
+#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
+#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
+#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
+#define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf
+#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
+#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
+#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L
+#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L
+#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L
+#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L
+#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L
+#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L
+#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L
+#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L
+#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L
+#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L
+#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L
+#define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L
+#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L
+#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L
+//SDMA1_RD_BURST_CNTL
+#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
+#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L
+//SDMA1_HBM_PAGE_CONFIG
+#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0
+#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L
+//SDMA1_UCODE_CHECKSUM
+#define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0
+#define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL
+//SDMA1_F32_CNTL
+#define SDMA1_F32_CNTL__HALT__SHIFT 0x0
+#define SDMA1_F32_CNTL__STEP__SHIFT 0x1
+#define SDMA1_F32_CNTL__HALT_MASK 0x00000001L
+#define SDMA1_F32_CNTL__STEP_MASK 0x00000002L
+//SDMA1_FREEZE
+#define SDMA1_FREEZE__PREEMPT__SHIFT 0x0
+#define SDMA1_FREEZE__FREEZE__SHIFT 0x4
+#define SDMA1_FREEZE__FROZEN__SHIFT 0x5
+#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6
+#define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L
+#define SDMA1_FREEZE__FREEZE_MASK 0x00000010L
+#define SDMA1_FREEZE__FROZEN_MASK 0x00000020L
+#define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L
+//SDMA1_PHASE0_QUANTUM
+#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA1_PHASE1_QUANTUM
+#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA1_EDC_CONFIG
+#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
+#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
+#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L
+//SDMA1_BA_THRESHOLD
+#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0
+#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
+#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL
+#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L
+//SDMA1_ID
+#define SDMA1_ID__DEVICE_ID__SHIFT 0x0
+#define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL
+//SDMA1_VERSION
+#define SDMA1_VERSION__MINVER__SHIFT 0x0
+#define SDMA1_VERSION__MAJVER__SHIFT 0x8
+#define SDMA1_VERSION__REV__SHIFT 0x10
+#define SDMA1_VERSION__MINVER_MASK 0x0000007FL
+#define SDMA1_VERSION__MAJVER_MASK 0x00007F00L
+#define SDMA1_VERSION__REV_MASK 0x003F0000L
+//SDMA1_EDC_COUNTER
+#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0
+#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1
+#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2
+#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3
+#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4
+#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5
+#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe
+#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf
+#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10
+#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L
+#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L
+#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L
+#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L
+#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L
+#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L
+#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L
+#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L
+#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L
+//SDMA1_EDC_COUNTER_CLEAR
+#define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0
+#define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L
+//SDMA1_STATUS2_REG
+#define SDMA1_STATUS2_REG__ID__SHIFT 0x0
+#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
+#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10
+#define SDMA1_STATUS2_REG__ID_MASK 0x00000003L
+#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL
+#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L
+//SDMA1_ATOMIC_CNTL
+#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
+#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
+#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL
+#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L
+//SDMA1_ATOMIC_PREOP_LO
+#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
+#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL
+//SDMA1_ATOMIC_PREOP_HI
+#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
+#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL
+//SDMA1_UTCL1_CNTL
+#define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0
+#define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1
+#define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb
+#define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe
+#define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
+#define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
+#define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L
+#define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL
+#define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L
+#define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L
+#define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L
+#define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L
+//SDMA1_UTCL1_WATERMK
+#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0
+#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
+#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12
+#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a
+#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL
+#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L
+#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L
+#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L
+//SDMA1_UTCL1_RD_STATUS
+#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12
+#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13
+#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14
+#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15
+#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16
+#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a
+#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
+#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e
+#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f
+#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
+#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
+#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
+#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
+#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
+#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
+#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L
+#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L
+#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L
+#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L
+#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L
+#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L
+#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L
+#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L
+#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L
+//SDMA1_UTCL1_WR_STATUS
+#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12
+#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13
+#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14
+#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15
+#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16
+#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19
+#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c
+#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
+#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e
+#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f
+#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
+#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
+#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
+#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
+#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
+#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
+#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L
+#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L
+#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L
+#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L
+#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L
+#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L
+#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L
+#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L
+#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L
+#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L
+//SDMA1_UTCL1_INV0
+#define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0
+#define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1
+#define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2
+#define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3
+#define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4
+#define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5
+#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6
+#define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7
+#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8
+#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9
+#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
+#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb
+#define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc
+#define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c
+#define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L
+#define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L
+#define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L
+#define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L
+#define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L
+#define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L
+#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L
+#define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L
+#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L
+#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L
+#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L
+#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L
+#define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L
+#define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L
+//SDMA1_UTCL1_INV1
+#define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0
+#define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA1_UTCL1_INV2
+#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0
+#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL
+//SDMA1_UTCL1_RD_XNACK0
+#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA1_UTCL1_RD_XNACK1
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA1_UTCL1_WR_XNACK0
+#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA1_UTCL1_WR_XNACK1
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA1_UTCL1_TIMEOUT
+#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
+#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
+#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL
+#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L
+//SDMA1_UTCL1_PAGE
+#define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0
+#define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1
+#define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6
+#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9
+#define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L
+#define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL
+#define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L
+#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L
+//SDMA1_POWER_CNTL_IDLE
+#define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
+#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
+#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
+#define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL
+#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L
+#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L
+//SDMA1_RELAX_ORDERING_LUT
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0
+#define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1
+#define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4
+#define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6
+#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8
+#define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9
+#define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
+#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb
+#define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc
+#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe
+#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b
+#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c
+#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
+#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e
+#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L
+#define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L
+#define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L
+#define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L
+#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L
+#define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L
+#define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L
+#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L
+#define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L
+#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L
+#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L
+#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L
+#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L
+#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L
+#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L
+//SDMA1_CHICKEN_BITS_2
+#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0
+#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL
+//SDMA1_STATUS3_REG
+#define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0
+#define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10
+#define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14
+#define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL
+#define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L
+#define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L
+//SDMA1_PHYSICAL_ADDR_LO
+#define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0
+#define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1
+#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2
+#define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc
+#define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L
+#define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L
+#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L
+#define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L
+//SDMA1_PHYSICAL_ADDR_HI
+#define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL
+//SDMA1_PHASE2_QUANTUM
+#define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA1_ERROR_LOG
+#define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0
+#define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10
+#define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL
+#define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L
+//SDMA1_PUB_DUMMY_REG0
+#define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0
+#define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_PUB_DUMMY_REG1
+#define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0
+#define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_PUB_DUMMY_REG2
+#define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0
+#define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_PUB_DUMMY_REG3
+#define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0
+#define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_F32_COUNTER
+#define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0
+#define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_UNBREAKABLE
+#define SDMA1_UNBREAKABLE__VALUE__SHIFT 0x0
+#define SDMA1_UNBREAKABLE__VALUE_MASK 0x00000001L
+//SDMA1_PERFMON_CNTL
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
+#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb
+#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L
+#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L
+#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L
+//SDMA1_PERFCOUNTER0_RESULT
+#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
+//SDMA1_PERFCOUNTER1_RESULT
+#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
+//SDMA1_PERFCOUNTER_TAG_DELAY_RANGE
+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0
+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe
+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c
+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL
+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L
+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L
+//SDMA1_CRD_CNTL
+#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7
+#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
+#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L
+#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L
+//SDMA1_MMHUB_TRUSTLVL
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L
+#define SDMA1_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L
+//SDMA1_GPU_IOV_VIOLATION_LOG
+#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
+#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1
+#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2
+#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12
+#define SDMA1_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13
+#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14
+#define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18
+#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
+#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L
+#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL
+#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L
+#define SDMA1_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L
+#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L
+#define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L
+//SDMA1_ULV_CNTL
+#define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT 0x0
+#define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
+#define SDMA1_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e
+#define SDMA1_ULV_CNTL__ULV_STATUS__SHIFT 0x1f
+#define SDMA1_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL
+#define SDMA1_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L
+#define SDMA1_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L
+#define SDMA1_ULV_CNTL__ULV_STATUS_MASK 0x80000000L
+//SDMA1_EA_DBIT_ADDR_DATA
+#define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0
+#define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_EA_DBIT_ADDR_INDEX
+#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0
+#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L
+//SDMA1_GFX_RB_CNTL
+#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL
+#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA1_GFX_RB_BASE
+#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_BASE_HI
+#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_GFX_RB_RPTR
+#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_RPTR_HI
+#define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_WPTR
+#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_WPTR_HI
+#define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_WPTR_POLL_CNTL
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_GFX_RB_RPTR_ADDR_HI
+#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_RPTR_ADDR_LO
+#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_GFX_IB_CNTL
+#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_GFX_IB_RPTR
+#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_GFX_IB_OFFSET
+#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_GFX_IB_BASE_LO
+#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_GFX_IB_BASE_HI
+#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_GFX_IB_SIZE
+#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_GFX_SKIP_CNTL
+#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
+//SDMA1_GFX_CONTEXT_STATUS
+#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_GFX_DOORBELL
+#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_GFX_CONTEXT_CNTL
+#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
+#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L
+//SDMA1_GFX_STATUS
+#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_GFX_DOORBELL_LOG
+#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA1_GFX_WATERMARK
+#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_GFX_DOORBELL_OFFSET
+#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_GFX_CSA_ADDR_LO
+#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_GFX_CSA_ADDR_HI
+#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_GFX_IB_SUB_REMAIN
+#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA1_GFX_PREEMPT
+#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_GFX_DUMMY_REG
+#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_GFX_RB_AQL_CNTL
+#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA1_GFX_MINOR_PTR_UPDATE
+#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_GFX_MIDCMD_DATA0
+#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA1
+#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA2
+#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA3
+#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA4
+#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA5
+#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA6
+#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA7
+#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA8
+#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_CNTL
+#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_PAGE_RB_CNTL
+#define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL
+#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA1_PAGE_RB_BASE
+#define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_BASE_HI
+#define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_PAGE_RB_RPTR
+#define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_RPTR_HI
+#define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_WPTR
+#define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_WPTR_HI
+#define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_WPTR_POLL_CNTL
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_PAGE_RB_RPTR_ADDR_HI
+#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_RPTR_ADDR_LO
+#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_PAGE_IB_CNTL
+#define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_PAGE_IB_RPTR
+#define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_PAGE_IB_OFFSET
+#define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_PAGE_IB_BASE_LO
+#define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_PAGE_IB_BASE_HI
+#define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_IB_SIZE
+#define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_PAGE_SKIP_CNTL
+#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
+//SDMA1_PAGE_CONTEXT_STATUS
+#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_PAGE_DOORBELL
+#define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_PAGE_STATUS
+#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_PAGE_DOORBELL_LOG
+#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA1_PAGE_WATERMARK
+#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_PAGE_DOORBELL_OFFSET
+#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_PAGE_CSA_ADDR_LO
+#define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_PAGE_CSA_ADDR_HI
+#define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_IB_SUB_REMAIN
+#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA1_PAGE_PREEMPT
+#define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_PAGE_DUMMY_REG
+#define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_PAGE_RB_AQL_CNTL
+#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA1_PAGE_MINOR_PTR_UPDATE
+#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_PAGE_MIDCMD_DATA0
+#define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA1
+#define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA2
+#define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA3
+#define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA4
+#define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA5
+#define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA6
+#define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA7
+#define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA8
+#define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_CNTL
+#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_RLC0_RB_CNTL
+#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL
+#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA1_RLC0_RB_BASE
+#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_BASE_HI
+#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_RLC0_RB_RPTR
+#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_RPTR_HI
+#define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_WPTR
+#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_WPTR_HI
+#define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_WPTR_POLL_CNTL
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_RLC0_RB_RPTR_ADDR_HI
+#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_RPTR_ADDR_LO
+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC0_IB_CNTL
+#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_RLC0_IB_RPTR
+#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC0_IB_OFFSET
+#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC0_IB_BASE_LO
+#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_RLC0_IB_BASE_HI
+#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_IB_SIZE
+#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC0_SKIP_CNTL
+#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
+//SDMA1_RLC0_CONTEXT_STATUS
+#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_RLC0_DOORBELL
+#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_RLC0_STATUS
+#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_RLC0_DOORBELL_LOG
+#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA1_RLC0_WATERMARK
+#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_RLC0_DOORBELL_OFFSET
+#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_RLC0_CSA_ADDR_LO
+#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC0_CSA_ADDR_HI
+#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_IB_SUB_REMAIN
+#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA1_RLC0_PREEMPT
+#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_RLC0_DUMMY_REG
+#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC0_RB_AQL_CNTL
+#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA1_RLC0_MINOR_PTR_UPDATE
+#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_RLC0_MIDCMD_DATA0
+#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA1
+#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA2
+#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA3
+#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA4
+#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA5
+#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA6
+#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA7
+#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA8
+#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_CNTL
+#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_RLC1_RB_CNTL
+#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL
+#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA1_RLC1_RB_BASE
+#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_BASE_HI
+#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_RLC1_RB_RPTR
+#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_RPTR_HI
+#define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_WPTR
+#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_WPTR_HI
+#define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_WPTR_POLL_CNTL
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_RLC1_RB_RPTR_ADDR_HI
+#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_RPTR_ADDR_LO
+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC1_IB_CNTL
+#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_RLC1_IB_RPTR
+#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC1_IB_OFFSET
+#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC1_IB_BASE_LO
+#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_RLC1_IB_BASE_HI
+#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_IB_SIZE
+#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC1_SKIP_CNTL
+#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
+//SDMA1_RLC1_CONTEXT_STATUS
+#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_RLC1_DOORBELL
+#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_RLC1_STATUS
+#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_RLC1_DOORBELL_LOG
+#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA1_RLC1_WATERMARK
+#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_RLC1_DOORBELL_OFFSET
+#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_RLC1_CSA_ADDR_LO
+#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC1_CSA_ADDR_HI
+#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_IB_SUB_REMAIN
+#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA1_RLC1_PREEMPT
+#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_RLC1_DUMMY_REG
+#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC1_RB_AQL_CNTL
+#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA1_RLC1_MINOR_PTR_UPDATE
+#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_RLC1_MIDCMD_DATA0
+#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA1
+#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA2
+#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA3
+#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA4
+#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA5
+#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA6
+#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA7
+#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA8
+#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_CNTL
+#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h
new file mode 100644
index 000000000000..5c186c2e8739
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _smuio_9_0_DEFAULT_HEADER
+#define _smuio_9_0_DEFAULT_HEADER
+
+
+// addressBlock: smuio_smuio_SmuSmuioDec
+#define mmROM_CNTL_DEFAULT 0x00000000
+#define mmROM_STATUS_DEFAULT 0x00000000
+#define mmCGTT_ROM_CLK_CTRL0_DEFAULT 0xc0000100
+#define mmROM_INDEX_DEFAULT 0x00000000
+#define mmROM_DATA_DEFAULT 0x00000000
+#define mmROM_START_DEFAULT 0x00000000
+#define mmROM_SW_CNTL_DEFAULT 0x00000000
+#define mmROM_SW_STATUS_DEFAULT 0x00000000
+#define mmROM_SW_COMMAND_DEFAULT 0x00000000
+#define mmROM_SW_DATA_1_DEFAULT 0x00000000
+#define mmROM_SW_DATA_2_DEFAULT 0x00000000
+#define mmROM_SW_DATA_3_DEFAULT 0x00000000
+#define mmROM_SW_DATA_4_DEFAULT 0x00000000
+#define mmROM_SW_DATA_5_DEFAULT 0x00000000
+#define mmROM_SW_DATA_6_DEFAULT 0x00000000
+#define mmROM_SW_DATA_7_DEFAULT 0x00000000
+#define mmROM_SW_DATA_8_DEFAULT 0x00000000
+#define mmROM_SW_DATA_9_DEFAULT 0x00000000
+#define mmROM_SW_DATA_10_DEFAULT 0x00000000
+#define mmROM_SW_DATA_11_DEFAULT 0x00000000
+#define mmROM_SW_DATA_12_DEFAULT 0x00000000
+#define mmROM_SW_DATA_13_DEFAULT 0x00000000
+#define mmROM_SW_DATA_14_DEFAULT 0x00000000
+#define mmROM_SW_DATA_15_DEFAULT 0x00000000
+#define mmROM_SW_DATA_16_DEFAULT 0x00000000
+#define mmROM_SW_DATA_17_DEFAULT 0x00000000
+#define mmROM_SW_DATA_18_DEFAULT 0x00000000
+#define mmROM_SW_DATA_19_DEFAULT 0x00000000
+#define mmROM_SW_DATA_20_DEFAULT 0x00000000
+#define mmROM_SW_DATA_21_DEFAULT 0x00000000
+#define mmROM_SW_DATA_22_DEFAULT 0x00000000
+#define mmROM_SW_DATA_23_DEFAULT 0x00000000
+#define mmROM_SW_DATA_24_DEFAULT 0x00000000
+#define mmROM_SW_DATA_25_DEFAULT 0x00000000
+#define mmROM_SW_DATA_26_DEFAULT 0x00000000
+#define mmROM_SW_DATA_27_DEFAULT 0x00000000
+#define mmROM_SW_DATA_28_DEFAULT 0x00000000
+#define mmROM_SW_DATA_29_DEFAULT 0x00000000
+#define mmROM_SW_DATA_30_DEFAULT 0x00000000
+#define mmROM_SW_DATA_31_DEFAULT 0x00000000
+#define mmROM_SW_DATA_32_DEFAULT 0x00000000
+#define mmROM_SW_DATA_33_DEFAULT 0x00000000
+#define mmROM_SW_DATA_34_DEFAULT 0x00000000
+#define mmROM_SW_DATA_35_DEFAULT 0x00000000
+#define mmROM_SW_DATA_36_DEFAULT 0x00000000
+#define mmROM_SW_DATA_37_DEFAULT 0x00000000
+#define mmROM_SW_DATA_38_DEFAULT 0x00000000
+#define mmROM_SW_DATA_39_DEFAULT 0x00000000
+#define mmROM_SW_DATA_40_DEFAULT 0x00000000
+#define mmROM_SW_DATA_41_DEFAULT 0x00000000
+#define mmROM_SW_DATA_42_DEFAULT 0x00000000
+#define mmROM_SW_DATA_43_DEFAULT 0x00000000
+#define mmROM_SW_DATA_44_DEFAULT 0x00000000
+#define mmROM_SW_DATA_45_DEFAULT 0x00000000
+#define mmROM_SW_DATA_46_DEFAULT 0x00000000
+#define mmROM_SW_DATA_47_DEFAULT 0x00000000
+#define mmROM_SW_DATA_48_DEFAULT 0x00000000
+#define mmROM_SW_DATA_49_DEFAULT 0x00000000
+#define mmROM_SW_DATA_50_DEFAULT 0x00000000
+#define mmROM_SW_DATA_51_DEFAULT 0x00000000
+#define mmROM_SW_DATA_52_DEFAULT 0x00000000
+#define mmROM_SW_DATA_53_DEFAULT 0x00000000
+#define mmROM_SW_DATA_54_DEFAULT 0x00000000
+#define mmROM_SW_DATA_55_DEFAULT 0x00000000
+#define mmROM_SW_DATA_56_DEFAULT 0x00000000
+#define mmROM_SW_DATA_57_DEFAULT 0x00000000
+#define mmROM_SW_DATA_58_DEFAULT 0x00000000
+#define mmROM_SW_DATA_59_DEFAULT 0x00000000
+#define mmROM_SW_DATA_60_DEFAULT 0x00000000
+#define mmROM_SW_DATA_61_DEFAULT 0x00000000
+#define mmROM_SW_DATA_62_DEFAULT 0x00000000
+#define mmROM_SW_DATA_63_DEFAULT 0x00000000
+#define mmROM_SW_DATA_64_DEFAULT 0x00000000
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_offset.h
new file mode 100644
index 000000000000..c1006fe58daa
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_offset.h
@@ -0,0 +1,175 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _smuio_9_0_OFFSET_HEADER
+#define _smuio_9_0_OFFSET_HEADER
+
+
+
+// addressBlock: smuio_smuio_SmuSmuioDec
+// base address: 0x5a000
+#define mmROM_CNTL 0x0024
+#define mmROM_CNTL_BASE_IDX 0
+#define mmROM_STATUS 0x0026
+#define mmROM_STATUS_BASE_IDX 0
+#define mmCGTT_ROM_CLK_CTRL0 0x0027
+#define mmCGTT_ROM_CLK_CTRL0_BASE_IDX 0
+#define mmROM_INDEX 0x0028
+#define mmROM_INDEX_BASE_IDX 0
+#define mmROM_DATA 0x0029
+#define mmROM_DATA_BASE_IDX 0
+#define mmROM_START 0x002a
+#define mmROM_START_BASE_IDX 0
+#define mmROM_SW_CNTL 0x002b
+#define mmROM_SW_CNTL_BASE_IDX 0
+#define mmROM_SW_STATUS 0x002c
+#define mmROM_SW_STATUS_BASE_IDX 0
+#define mmROM_SW_COMMAND 0x002d
+#define mmROM_SW_COMMAND_BASE_IDX 0
+#define mmROM_SW_DATA_1 0x002e
+#define mmROM_SW_DATA_1_BASE_IDX 0
+#define mmROM_SW_DATA_2 0x002f
+#define mmROM_SW_DATA_2_BASE_IDX 0
+#define mmROM_SW_DATA_3 0x0030
+#define mmROM_SW_DATA_3_BASE_IDX 0
+#define mmROM_SW_DATA_4 0x0031
+#define mmROM_SW_DATA_4_BASE_IDX 0
+#define mmROM_SW_DATA_5 0x0032
+#define mmROM_SW_DATA_5_BASE_IDX 0
+#define mmROM_SW_DATA_6 0x0033
+#define mmROM_SW_DATA_6_BASE_IDX 0
+#define mmROM_SW_DATA_7 0x0034
+#define mmROM_SW_DATA_7_BASE_IDX 0
+#define mmROM_SW_DATA_8 0x0035
+#define mmROM_SW_DATA_8_BASE_IDX 0
+#define mmROM_SW_DATA_9 0x0036
+#define mmROM_SW_DATA_9_BASE_IDX 0
+#define mmROM_SW_DATA_10 0x0037
+#define mmROM_SW_DATA_10_BASE_IDX 0
+#define mmROM_SW_DATA_11 0x0038
+#define mmROM_SW_DATA_11_BASE_IDX 0
+#define mmROM_SW_DATA_12 0x0039
+#define mmROM_SW_DATA_12_BASE_IDX 0
+#define mmROM_SW_DATA_13 0x003a
+#define mmROM_SW_DATA_13_BASE_IDX 0
+#define mmROM_SW_DATA_14 0x003b
+#define mmROM_SW_DATA_14_BASE_IDX 0
+#define mmROM_SW_DATA_15 0x003c
+#define mmROM_SW_DATA_15_BASE_IDX 0
+#define mmROM_SW_DATA_16 0x003d
+#define mmROM_SW_DATA_16_BASE_IDX 0
+#define mmROM_SW_DATA_17 0x003e
+#define mmROM_SW_DATA_17_BASE_IDX 0
+#define mmROM_SW_DATA_18 0x003f
+#define mmROM_SW_DATA_18_BASE_IDX 0
+#define mmROM_SW_DATA_19 0x0040
+#define mmROM_SW_DATA_19_BASE_IDX 0
+#define mmROM_SW_DATA_20 0x0041
+#define mmROM_SW_DATA_20_BASE_IDX 0
+#define mmROM_SW_DATA_21 0x0042
+#define mmROM_SW_DATA_21_BASE_IDX 0
+#define mmROM_SW_DATA_22 0x0043
+#define mmROM_SW_DATA_22_BASE_IDX 0
+#define mmROM_SW_DATA_23 0x0044
+#define mmROM_SW_DATA_23_BASE_IDX 0
+#define mmROM_SW_DATA_24 0x0045
+#define mmROM_SW_DATA_24_BASE_IDX 0
+#define mmROM_SW_DATA_25 0x0046
+#define mmROM_SW_DATA_25_BASE_IDX 0
+#define mmROM_SW_DATA_26 0x0047
+#define mmROM_SW_DATA_26_BASE_IDX 0
+#define mmROM_SW_DATA_27 0x0048
+#define mmROM_SW_DATA_27_BASE_IDX 0
+#define mmROM_SW_DATA_28 0x0049
+#define mmROM_SW_DATA_28_BASE_IDX 0
+#define mmROM_SW_DATA_29 0x004a
+#define mmROM_SW_DATA_29_BASE_IDX 0
+#define mmROM_SW_DATA_30 0x004b
+#define mmROM_SW_DATA_30_BASE_IDX 0
+#define mmROM_SW_DATA_31 0x004c
+#define mmROM_SW_DATA_31_BASE_IDX 0
+#define mmROM_SW_DATA_32 0x004d
+#define mmROM_SW_DATA_32_BASE_IDX 0
+#define mmROM_SW_DATA_33 0x004e
+#define mmROM_SW_DATA_33_BASE_IDX 0
+#define mmROM_SW_DATA_34 0x004f
+#define mmROM_SW_DATA_34_BASE_IDX 0
+#define mmROM_SW_DATA_35 0x0050
+#define mmROM_SW_DATA_35_BASE_IDX 0
+#define mmROM_SW_DATA_36 0x0051
+#define mmROM_SW_DATA_36_BASE_IDX 0
+#define mmROM_SW_DATA_37 0x0052
+#define mmROM_SW_DATA_37_BASE_IDX 0
+#define mmROM_SW_DATA_38 0x0053
+#define mmROM_SW_DATA_38_BASE_IDX 0
+#define mmROM_SW_DATA_39 0x0054
+#define mmROM_SW_DATA_39_BASE_IDX 0
+#define mmROM_SW_DATA_40 0x0055
+#define mmROM_SW_DATA_40_BASE_IDX 0
+#define mmROM_SW_DATA_41 0x0056
+#define mmROM_SW_DATA_41_BASE_IDX 0
+#define mmROM_SW_DATA_42 0x0057
+#define mmROM_SW_DATA_42_BASE_IDX 0
+#define mmROM_SW_DATA_43 0x0058
+#define mmROM_SW_DATA_43_BASE_IDX 0
+#define mmROM_SW_DATA_44 0x0059
+#define mmROM_SW_DATA_44_BASE_IDX 0
+#define mmROM_SW_DATA_45 0x005a
+#define mmROM_SW_DATA_45_BASE_IDX 0
+#define mmROM_SW_DATA_46 0x005b
+#define mmROM_SW_DATA_46_BASE_IDX 0
+#define mmROM_SW_DATA_47 0x005c
+#define mmROM_SW_DATA_47_BASE_IDX 0
+#define mmROM_SW_DATA_48 0x005d
+#define mmROM_SW_DATA_48_BASE_IDX 0
+#define mmROM_SW_DATA_49 0x005e
+#define mmROM_SW_DATA_49_BASE_IDX 0
+#define mmROM_SW_DATA_50 0x005f
+#define mmROM_SW_DATA_50_BASE_IDX 0
+#define mmROM_SW_DATA_51 0x0060
+#define mmROM_SW_DATA_51_BASE_IDX 0
+#define mmROM_SW_DATA_52 0x0061
+#define mmROM_SW_DATA_52_BASE_IDX 0
+#define mmROM_SW_DATA_53 0x0062
+#define mmROM_SW_DATA_53_BASE_IDX 0
+#define mmROM_SW_DATA_54 0x0063
+#define mmROM_SW_DATA_54_BASE_IDX 0
+#define mmROM_SW_DATA_55 0x0064
+#define mmROM_SW_DATA_55_BASE_IDX 0
+#define mmROM_SW_DATA_56 0x0065
+#define mmROM_SW_DATA_56_BASE_IDX 0
+#define mmROM_SW_DATA_57 0x0066
+#define mmROM_SW_DATA_57_BASE_IDX 0
+#define mmROM_SW_DATA_58 0x0067
+#define mmROM_SW_DATA_58_BASE_IDX 0
+#define mmROM_SW_DATA_59 0x0068
+#define mmROM_SW_DATA_59_BASE_IDX 0
+#define mmROM_SW_DATA_60 0x0069
+#define mmROM_SW_DATA_60_BASE_IDX 0
+#define mmROM_SW_DATA_61 0x006a
+#define mmROM_SW_DATA_61_BASE_IDX 0
+#define mmROM_SW_DATA_62 0x006b
+#define mmROM_SW_DATA_62_BASE_IDX 0
+#define mmROM_SW_DATA_63 0x006c
+#define mmROM_SW_DATA_63_BASE_IDX 0
+#define mmROM_SW_DATA_64 0x006d
+#define mmROM_SW_DATA_64_BASE_IDX 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h
new file mode 100644
index 000000000000..a0be5c9bfc10
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h
@@ -0,0 +1,258 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _smuio_9_0_SH_MASK_HEADER
+#define _smuio_9_0_SH_MASK_HEADER
+
+
+// addressBlock: smuio_smuio_SmuSmuioDec
+//ROM_CNTL
+#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x0
+#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x00000001L
+//ROM_STATUS
+#define ROM_STATUS__ROM_BUSY__SHIFT 0x0
+#define ROM_STATUS__ROM_BUSY_MASK 0x00000001L
+//CGTT_ROM_CLK_CTRL0
+#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
+#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
+#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
+//ROM_INDEX
+#define ROM_INDEX__ROM_INDEX__SHIFT 0x0
+#define ROM_INDEX__ROM_INDEX_MASK 0x00FFFFFFL
+//ROM_DATA
+#define ROM_DATA__ROM_DATA__SHIFT 0x0
+#define ROM_DATA__ROM_DATA_MASK 0xFFFFFFFFL
+//ROM_START
+#define ROM_START__ROM_START__SHIFT 0x0
+#define ROM_START__ROM_START_MASK 0x00FFFFFFL
+//ROM_SW_CNTL
+#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0
+#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10
+#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12
+#define ROM_SW_CNTL__DATA_SIZE_MASK 0x0000FFFFL
+#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x00030000L
+#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x00040000L
+//ROM_SW_STATUS
+#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0
+#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x00000001L
+//ROM_SW_COMMAND
+#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0
+#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8
+#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0x000000FFL
+#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xFFFFFF00L
+//ROM_SW_DATA_1
+#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_2
+#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_3
+#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_4
+#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_5
+#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_6
+#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_7
+#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_8
+#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_9
+#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_10
+#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_11
+#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_12
+#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_13
+#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_14
+#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_15
+#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_16
+#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_17
+#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_18
+#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_19
+#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_20
+#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_21
+#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_22
+#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_23
+#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_24
+#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_25
+#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_26
+#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_27
+#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_28
+#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_29
+#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_30
+#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_31
+#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_32
+#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_33
+#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_34
+#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_35
+#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_36
+#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_37
+#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_38
+#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_39
+#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_40
+#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_41
+#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_42
+#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_43
+#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_44
+#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_45
+#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_46
+#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_47
+#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_48
+#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_49
+#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_50
+#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_51
+#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_52
+#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_53
+#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_54
+#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_55
+#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_56
+#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_57
+#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_58
+#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_59
+#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_60
+#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_61
+#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_62
+#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_63
+#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_64
+#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xFFFFFFFFL
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h
new file mode 100644
index 000000000000..0cbae8bafbf2
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h
@@ -0,0 +1,194 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _thm_9_0_DEFAULT_HEADER
+#define _thm_9_0_DEFAULT_HEADER
+
+
+// addressBlock: thm_thm_SmuThmDec
+#define mmTHM_TCON_CUR_TMP_DEFAULT 0x00000000
+#define mmTHM_TCON_HTC_DEFAULT 0x00004000
+#define mmTHM_TCON_THERM_TRIP_DEFAULT 0x00000001
+#define mmTHM_GPIO_PROCHOT_CTRL_DEFAULT 0x000000f9
+#define mmTHM_GPIO_THERMTRIP_CTRL_DEFAULT 0x001000f9
+#define mmTHM_GPIO_PWM_CTRL_DEFAULT 0x000000f9
+#define mmTHM_GPIO_TACHIN_CTRL_DEFAULT 0x000000f9
+#define mmTHM_GPIO_PUMPOUT_CTRL_DEFAULT 0x000000f9
+#define mmTHM_GPIO_PUMPIN_CTRL_DEFAULT 0x000000f9
+#define mmTHM_THERMAL_INT_ENA_DEFAULT 0x00000000
+#define mmTHM_THERMAL_INT_CTRL_DEFAULT 0x0fff0078
+#define mmTHM_THERMAL_INT_STATUS_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL0_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL1_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL2_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL3_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL4_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL5_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL6_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL7_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL8_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL9_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL10_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL11_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL12_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL13_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL14_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL15_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR0_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR1_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR2_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR3_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR4_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR5_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR6_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR7_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR8_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR9_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR10_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR11_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR12_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR13_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR14_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR15_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_INT_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_DEBUG_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL0_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL1_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL2_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL3_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL4_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL5_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL6_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL7_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL8_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL9_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL10_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL11_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL12_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL13_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL14_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL15_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR0_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR1_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR2_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR3_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR4_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR5_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR6_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR7_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR8_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR9_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR10_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR11_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR12_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR13_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR14_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR15_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_INT_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_DEBUG_DEFAULT 0x00000000
+#define mmTHM_DIE1_TEMP_DEFAULT 0x00000000
+#define mmTHM_DIE2_TEMP_DEFAULT 0x00000000
+#define mmTHM_DIE3_TEMP_DEFAULT 0x00000000
+#define mmCG_MULT_THERMAL_CTRL_DEFAULT 0x08400001
+#define mmCG_MULT_THERMAL_STATUS_DEFAULT 0x00000000
+#define mmTHM_TMON0_COEFF_DEFAULT 0x00024068
+#define mmTHM_TMON1_COEFF_DEFAULT 0x00024068
+#define mmCG_FDO_CTRL0_DEFAULT 0x0000642c
+#define mmCG_FDO_CTRL1_DEFAULT 0x001e1f7d
+#define mmCG_FDO_CTRL2_DEFAULT 0x02bf0228
+#define mmCG_TACH_CTRL_DEFAULT 0x00008002
+#define mmCG_TACH_STATUS_DEFAULT 0x00000000
+#define mmCG_THERMAL_STATUS_DEFAULT 0x00000000
+#define mmCG_PUMP_CTRL0_DEFAULT 0x0000642c
+#define mmCG_PUMP_CTRL1_DEFAULT 0x001e1f7d
+#define mmCG_PUMP_CTRL2_DEFAULT 0x02bf0228
+#define mmCG_PUMP_TACH_CTRL_DEFAULT 0x00008002
+#define mmCG_PUMP_TACH_STATUS_DEFAULT 0x00000000
+#define mmCG_PUMP_STATUS_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL0_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL1_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL2_DEFAULT 0x00000060
+#define mmTHM_TCON_LOCAL3_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL4_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL5_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL6_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL7_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL8_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL9_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL10_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL11_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL12_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL13_DEFAULT 0x00000000
+#define mmTHM_BACO_CNTL_DEFAULT 0x00000004
+#define mmTHM_BACO_TIMING0_DEFAULT 0x80a06050
+#define mmTHM_BACO_TIMING1_DEFAULT 0x1020f070
+#define mmXTAL_CNTL_DEFAULT 0x00006010
+#define mmSBTSI_REMOTE_TEMP_DEFAULT 0x00000000
+#define mmSBRMI_CONTROL_DEFAULT 0x00000000
+#define mmSBRMI_COMMAND_DEFAULT 0x00000000
+#define mmSBRMI_WRITE_DATA0_DEFAULT 0x00000000
+#define mmSBRMI_WRITE_DATA1_DEFAULT 0x00000000
+#define mmSBRMI_WRITE_DATA2_DEFAULT 0x00000000
+#define mmSBRMI_READ_DATA0_DEFAULT 0x00000000
+#define mmSBRMI_READ_DATA1_DEFAULT 0x00000000
+#define mmSBRMI_CORE_EN_NUMBER_DEFAULT 0x00000010
+#define mmSBRMI_CORE_EN_STATUS0_DEFAULT 0x00000000
+#define mmSBRMI_CORE_EN_STATUS1_DEFAULT 0x00000000
+#define mmSBRMI_APIC_STATUS0_DEFAULT 0x00000000
+#define mmSBRMI_APIC_STATUS1_DEFAULT 0x00000000
+#define mmSBRMI_MCE_STATUS0_DEFAULT 0x00000000
+#define mmSBRMI_MCE_STATUS1_DEFAULT 0x00000000
+#define mmSMBUS_CNTL0_DEFAULT 0x00030082
+#define mmSMBUS_CNTL1_DEFAULT 0x0000063f
+#define mmSMBUS_BLKWR_CMD_CTRL0_DEFAULT 0x12110201
+#define mmSMBUS_BLKWR_CMD_CTRL1_DEFAULT 0x0003005a
+#define mmSMBUS_BLKRD_CMD_CTRL0_DEFAULT 0x00001303
+#define mmSMBUS_BLKRD_CMD_CTRL1_DEFAULT 0x00000000
+#define mmSMBUS_TIMING_CNTL0_DEFAULT 0x028a4f5c
+#define mmSMBUS_TIMING_CNTL1_DEFAULT 0x08036927
+#define mmSMBUS_TIMING_CNTL2_DEFAULT 0x0021e548
+#define mmSMBUS_TRIGGER_CNTL_DEFAULT 0x00000000
+#define mmSMBUS_UDID_CNTL0_DEFAULT 0x7fffffff
+#define mmSMBUS_UDID_CNTL1_DEFAULT 0x00000000
+#define mmSMBUS_UDID_CNTL2_DEFAULT 0x00000043
+#define mmSMBUS_BACO_DUMMY_DEFAULT 0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE0_LOW_DEFAULT 0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE0_HIGH_DEFAULT 0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE1_LOW_DEFAULT 0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE1_HIGH_DEFAULT 0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE2_LOW_DEFAULT 0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE2_HIGH_DEFAULT 0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE3_LOW_DEFAULT 0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE3_HIGH_DEFAULT 0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE4_LOW_DEFAULT 0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE4_HIGH_DEFAULT 0x00000000
+#define mmTHM_GPIO_MACO_EN_CTRL_DEFAULT 0x000000f9
+#define mmTHM_BACO_TIMING2_DEFAULT 0x00903040
+#define mmTHM_BACO_TIMING_DEFAULT 0x00000a8c
+#define mmTHM_TMON0_REMOTE_START_DEFAULT 0x00000000
+#define mmTHM_TMON0_REMOTE_END_DEFAULT 0x00000000
+#define mmTHM_TMON1_REMOTE_START_DEFAULT 0x00000000
+#define mmTHM_TMON1_REMOTE_END_DEFAULT 0x00000000
+#define mmTHM_TMON2_REMOTE_START_DEFAULT 0x00000000
+#define mmTHM_TMON2_REMOTE_END_DEFAULT 0x00000000
+#define mmTHM_TMON3_REMOTE_START_DEFAULT 0x00000000
+#define mmTHM_TMON3_REMOTE_END_DEFAULT 0x00000000
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_offset.h
new file mode 100644
index 000000000000..3053fd34d216
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_offset.h
@@ -0,0 +1,363 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _thm_9_0_OFFSET_HEADER
+#define _thm_9_0_OFFSET_HEADER
+
+
+
+// addressBlock: thm_thm_SmuThmDec
+// base address: 0x59800
+#define mmTHM_TCON_CUR_TMP 0x0000
+#define mmTHM_TCON_CUR_TMP_BASE_IDX 0
+#define mmTHM_TCON_HTC 0x0001
+#define mmTHM_TCON_HTC_BASE_IDX 0
+#define mmTHM_TCON_THERM_TRIP 0x0002
+#define mmTHM_TCON_THERM_TRIP_BASE_IDX 0
+#define mmTHM_GPIO_PROCHOT_CTRL 0x0004
+#define mmTHM_GPIO_PROCHOT_CTRL_BASE_IDX 0
+#define mmTHM_GPIO_THERMTRIP_CTRL 0x0005
+#define mmTHM_GPIO_THERMTRIP_CTRL_BASE_IDX 0
+#define mmTHM_GPIO_PWM_CTRL 0x0006
+#define mmTHM_GPIO_PWM_CTRL_BASE_IDX 0
+#define mmTHM_GPIO_TACHIN_CTRL 0x0007
+#define mmTHM_GPIO_TACHIN_CTRL_BASE_IDX 0
+#define mmTHM_GPIO_PUMPOUT_CTRL 0x0008
+#define mmTHM_GPIO_PUMPOUT_CTRL_BASE_IDX 0
+#define mmTHM_GPIO_PUMPIN_CTRL 0x0009
+#define mmTHM_GPIO_PUMPIN_CTRL_BASE_IDX 0
+#define mmTHM_THERMAL_INT_ENA 0x000a
+#define mmTHM_THERMAL_INT_ENA_BASE_IDX 0
+#define mmTHM_THERMAL_INT_CTRL 0x000b
+#define mmTHM_THERMAL_INT_CTRL_BASE_IDX 0
+#define mmTHM_THERMAL_INT_STATUS 0x000c
+#define mmTHM_THERMAL_INT_STATUS_BASE_IDX 0
+#define mmTHM_TMON0_RDIL0_DATA 0x000d
+#define mmTHM_TMON0_RDIL0_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIL1_DATA 0x000e
+#define mmTHM_TMON0_RDIL1_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIL2_DATA 0x000f
+#define mmTHM_TMON0_RDIL2_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIL3_DATA 0x0010
+#define mmTHM_TMON0_RDIL3_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIL4_DATA 0x0011
+#define mmTHM_TMON0_RDIL4_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIL5_DATA 0x0012
+#define mmTHM_TMON0_RDIL5_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIL6_DATA 0x0013
+#define mmTHM_TMON0_RDIL6_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIL7_DATA 0x0014
+#define mmTHM_TMON0_RDIL7_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIL8_DATA 0x0015
+#define mmTHM_TMON0_RDIL8_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIL9_DATA 0x0016
+#define mmTHM_TMON0_RDIL9_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIL10_DATA 0x0017
+#define mmTHM_TMON0_RDIL10_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIL11_DATA 0x0018
+#define mmTHM_TMON0_RDIL11_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIL12_DATA 0x0019
+#define mmTHM_TMON0_RDIL12_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIL13_DATA 0x001a
+#define mmTHM_TMON0_RDIL13_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIL14_DATA 0x001b
+#define mmTHM_TMON0_RDIL14_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIL15_DATA 0x001c
+#define mmTHM_TMON0_RDIL15_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIR0_DATA 0x001d
+#define mmTHM_TMON0_RDIR0_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIR1_DATA 0x001e
+#define mmTHM_TMON0_RDIR1_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIR2_DATA 0x001f
+#define mmTHM_TMON0_RDIR2_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIR3_DATA 0x0020
+#define mmTHM_TMON0_RDIR3_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIR4_DATA 0x0021
+#define mmTHM_TMON0_RDIR4_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIR5_DATA 0x0022
+#define mmTHM_TMON0_RDIR5_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIR6_DATA 0x0023
+#define mmTHM_TMON0_RDIR6_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIR7_DATA 0x0024
+#define mmTHM_TMON0_RDIR7_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIR8_DATA 0x0025
+#define mmTHM_TMON0_RDIR8_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIR9_DATA 0x0026
+#define mmTHM_TMON0_RDIR9_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIR10_DATA 0x0027
+#define mmTHM_TMON0_RDIR10_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIR11_DATA 0x0028
+#define mmTHM_TMON0_RDIR11_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIR12_DATA 0x0029
+#define mmTHM_TMON0_RDIR12_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIR13_DATA 0x002a
+#define mmTHM_TMON0_RDIR13_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIR14_DATA 0x002b
+#define mmTHM_TMON0_RDIR14_DATA_BASE_IDX 0
+#define mmTHM_TMON0_RDIR15_DATA 0x002c
+#define mmTHM_TMON0_RDIR15_DATA_BASE_IDX 0
+#define mmTHM_TMON0_INT_DATA 0x002d
+#define mmTHM_TMON0_INT_DATA_BASE_IDX 0
+#define mmTHM_TMON0_DEBUG 0x0030
+#define mmTHM_TMON0_DEBUG_BASE_IDX 0
+#define mmTHM_TMON1_RDIL0_DATA 0x0031
+#define mmTHM_TMON1_RDIL0_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIL1_DATA 0x0032
+#define mmTHM_TMON1_RDIL1_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIL2_DATA 0x0033
+#define mmTHM_TMON1_RDIL2_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIL3_DATA 0x0034
+#define mmTHM_TMON1_RDIL3_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIL4_DATA 0x0035
+#define mmTHM_TMON1_RDIL4_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIL5_DATA 0x0036
+#define mmTHM_TMON1_RDIL5_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIL6_DATA 0x0037
+#define mmTHM_TMON1_RDIL6_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIL7_DATA 0x0038
+#define mmTHM_TMON1_RDIL7_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIL8_DATA 0x0039
+#define mmTHM_TMON1_RDIL8_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIL9_DATA 0x003a
+#define mmTHM_TMON1_RDIL9_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIL10_DATA 0x003b
+#define mmTHM_TMON1_RDIL10_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIL11_DATA 0x003c
+#define mmTHM_TMON1_RDIL11_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIL12_DATA 0x003d
+#define mmTHM_TMON1_RDIL12_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIL13_DATA 0x003e
+#define mmTHM_TMON1_RDIL13_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIL14_DATA 0x003f
+#define mmTHM_TMON1_RDIL14_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIL15_DATA 0x0040
+#define mmTHM_TMON1_RDIL15_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIR0_DATA 0x0041
+#define mmTHM_TMON1_RDIR0_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIR1_DATA 0x0042
+#define mmTHM_TMON1_RDIR1_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIR2_DATA 0x0043
+#define mmTHM_TMON1_RDIR2_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIR3_DATA 0x0044
+#define mmTHM_TMON1_RDIR3_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIR4_DATA 0x0045
+#define mmTHM_TMON1_RDIR4_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIR5_DATA 0x0046
+#define mmTHM_TMON1_RDIR5_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIR6_DATA 0x0047
+#define mmTHM_TMON1_RDIR6_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIR7_DATA 0x0048
+#define mmTHM_TMON1_RDIR7_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIR8_DATA 0x0049
+#define mmTHM_TMON1_RDIR8_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIR9_DATA 0x004a
+#define mmTHM_TMON1_RDIR9_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIR10_DATA 0x004b
+#define mmTHM_TMON1_RDIR10_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIR11_DATA 0x004c
+#define mmTHM_TMON1_RDIR11_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIR12_DATA 0x004d
+#define mmTHM_TMON1_RDIR12_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIR13_DATA 0x004e
+#define mmTHM_TMON1_RDIR13_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIR14_DATA 0x004f
+#define mmTHM_TMON1_RDIR14_DATA_BASE_IDX 0
+#define mmTHM_TMON1_RDIR15_DATA 0x0050
+#define mmTHM_TMON1_RDIR15_DATA_BASE_IDX 0
+#define mmTHM_TMON1_INT_DATA 0x0051
+#define mmTHM_TMON1_INT_DATA_BASE_IDX 0
+#define mmTHM_TMON1_DEBUG 0x0054
+#define mmTHM_TMON1_DEBUG_BASE_IDX 0
+#define mmTHM_DIE1_TEMP 0x0055
+#define mmTHM_DIE1_TEMP_BASE_IDX 0
+#define mmTHM_DIE2_TEMP 0x0056
+#define mmTHM_DIE2_TEMP_BASE_IDX 0
+#define mmTHM_DIE3_TEMP 0x0057
+#define mmTHM_DIE3_TEMP_BASE_IDX 0
+#define mmCG_MULT_THERMAL_CTRL 0x0059
+#define mmCG_MULT_THERMAL_CTRL_BASE_IDX 0
+#define mmCG_MULT_THERMAL_STATUS 0x005a
+#define mmCG_MULT_THERMAL_STATUS_BASE_IDX 0
+#define mmTHM_TMON0_COEFF 0x005e
+#define mmTHM_TMON0_COEFF_BASE_IDX 0
+#define mmTHM_TMON1_COEFF 0x005f
+#define mmTHM_TMON1_COEFF_BASE_IDX 0
+#define mmCG_FDO_CTRL0 0x0062
+#define mmCG_FDO_CTRL0_BASE_IDX 0
+#define mmCG_FDO_CTRL1 0x0063
+#define mmCG_FDO_CTRL1_BASE_IDX 0
+#define mmCG_FDO_CTRL2 0x0064
+#define mmCG_FDO_CTRL2_BASE_IDX 0
+#define mmCG_TACH_CTRL 0x0065
+#define mmCG_TACH_CTRL_BASE_IDX 0
+#define mmCG_TACH_STATUS 0x0066
+#define mmCG_TACH_STATUS_BASE_IDX 0
+#define mmCG_THERMAL_STATUS 0x0067
+#define mmCG_THERMAL_STATUS_BASE_IDX 0
+#define mmCG_PUMP_CTRL0 0x0068
+#define mmCG_PUMP_CTRL0_BASE_IDX 0
+#define mmCG_PUMP_CTRL1 0x0069
+#define mmCG_PUMP_CTRL1_BASE_IDX 0
+#define mmCG_PUMP_CTRL2 0x006a
+#define mmCG_PUMP_CTRL2_BASE_IDX 0
+#define mmCG_PUMP_TACH_CTRL 0x006b
+#define mmCG_PUMP_TACH_CTRL_BASE_IDX 0
+#define mmCG_PUMP_TACH_STATUS 0x006c
+#define mmCG_PUMP_TACH_STATUS_BASE_IDX 0
+#define mmCG_PUMP_STATUS 0x006d
+#define mmCG_PUMP_STATUS_BASE_IDX 0
+#define mmTHM_TCON_LOCAL0 0x006e
+#define mmTHM_TCON_LOCAL0_BASE_IDX 0
+#define mmTHM_TCON_LOCAL1 0x006f
+#define mmTHM_TCON_LOCAL1_BASE_IDX 0
+#define mmTHM_TCON_LOCAL2 0x0070
+#define mmTHM_TCON_LOCAL2_BASE_IDX 0
+#define mmTHM_TCON_LOCAL3 0x0071
+#define mmTHM_TCON_LOCAL3_BASE_IDX 0
+#define mmTHM_TCON_LOCAL4 0x0072
+#define mmTHM_TCON_LOCAL4_BASE_IDX 0
+#define mmTHM_TCON_LOCAL5 0x0073
+#define mmTHM_TCON_LOCAL5_BASE_IDX 0
+#define mmTHM_TCON_LOCAL6 0x0074
+#define mmTHM_TCON_LOCAL6_BASE_IDX 0
+#define mmTHM_TCON_LOCAL7 0x0075
+#define mmTHM_TCON_LOCAL7_BASE_IDX 0
+#define mmTHM_TCON_LOCAL8 0x0076
+#define mmTHM_TCON_LOCAL8_BASE_IDX 0
+#define mmTHM_TCON_LOCAL9 0x0077
+#define mmTHM_TCON_LOCAL9_BASE_IDX 0
+#define mmTHM_TCON_LOCAL10 0x0078
+#define mmTHM_TCON_LOCAL10_BASE_IDX 0
+#define mmTHM_TCON_LOCAL11 0x0079
+#define mmTHM_TCON_LOCAL11_BASE_IDX 0
+#define mmTHM_TCON_LOCAL12 0x007a
+#define mmTHM_TCON_LOCAL12_BASE_IDX 0
+#define mmTHM_TCON_LOCAL13 0x007b
+#define mmTHM_TCON_LOCAL13_BASE_IDX 0
+#define mmTHM_BACO_CNTL 0x007c
+#define mmTHM_BACO_CNTL_BASE_IDX 0
+#define mmTHM_BACO_TIMING0 0x007d
+#define mmTHM_BACO_TIMING0_BASE_IDX 0
+#define mmTHM_BACO_TIMING1 0x007e
+#define mmTHM_BACO_TIMING1_BASE_IDX 0
+#define mmXTAL_CNTL 0x007f
+#define mmXTAL_CNTL_BASE_IDX 0
+#define mmSBTSI_REMOTE_TEMP 0x008a
+#define mmSBTSI_REMOTE_TEMP_BASE_IDX 0
+#define mmSBRMI_CONTROL 0x008b
+#define mmSBRMI_CONTROL_BASE_IDX 0
+#define mmSBRMI_COMMAND 0x008c
+#define mmSBRMI_COMMAND_BASE_IDX 0
+#define mmSBRMI_WRITE_DATA0 0x008d
+#define mmSBRMI_WRITE_DATA0_BASE_IDX 0
+#define mmSBRMI_WRITE_DATA1 0x008e
+#define mmSBRMI_WRITE_DATA1_BASE_IDX 0
+#define mmSBRMI_WRITE_DATA2 0x008f
+#define mmSBRMI_WRITE_DATA2_BASE_IDX 0
+#define mmSBRMI_READ_DATA0 0x0090
+#define mmSBRMI_READ_DATA0_BASE_IDX 0
+#define mmSBRMI_READ_DATA1 0x0091
+#define mmSBRMI_READ_DATA1_BASE_IDX 0
+#define mmSBRMI_CORE_EN_NUMBER 0x0092
+#define mmSBRMI_CORE_EN_NUMBER_BASE_IDX 0
+#define mmSBRMI_CORE_EN_STATUS0 0x0093
+#define mmSBRMI_CORE_EN_STATUS0_BASE_IDX 0
+#define mmSBRMI_CORE_EN_STATUS1 0x0094
+#define mmSBRMI_CORE_EN_STATUS1_BASE_IDX 0
+#define mmSBRMI_APIC_STATUS0 0x0095
+#define mmSBRMI_APIC_STATUS0_BASE_IDX 0
+#define mmSBRMI_APIC_STATUS1 0x0096
+#define mmSBRMI_APIC_STATUS1_BASE_IDX 0
+#define mmSBRMI_MCE_STATUS0 0x0097
+#define mmSBRMI_MCE_STATUS0_BASE_IDX 0
+#define mmSBRMI_MCE_STATUS1 0x0098
+#define mmSBRMI_MCE_STATUS1_BASE_IDX 0
+#define mmSMBUS_CNTL0 0x0099
+#define mmSMBUS_CNTL0_BASE_IDX 0
+#define mmSMBUS_CNTL1 0x009a
+#define mmSMBUS_CNTL1_BASE_IDX 0
+#define mmSMBUS_BLKWR_CMD_CTRL0 0x009b
+#define mmSMBUS_BLKWR_CMD_CTRL0_BASE_IDX 0
+#define mmSMBUS_BLKWR_CMD_CTRL1 0x009c
+#define mmSMBUS_BLKWR_CMD_CTRL1_BASE_IDX 0
+#define mmSMBUS_BLKRD_CMD_CTRL0 0x009d
+#define mmSMBUS_BLKRD_CMD_CTRL0_BASE_IDX 0
+#define mmSMBUS_BLKRD_CMD_CTRL1 0x009e
+#define mmSMBUS_BLKRD_CMD_CTRL1_BASE_IDX 0
+#define mmSMBUS_TIMING_CNTL0 0x009f
+#define mmSMBUS_TIMING_CNTL0_BASE_IDX 0
+#define mmSMBUS_TIMING_CNTL1 0x00a0
+#define mmSMBUS_TIMING_CNTL1_BASE_IDX 0
+#define mmSMBUS_TIMING_CNTL2 0x00a1
+#define mmSMBUS_TIMING_CNTL2_BASE_IDX 0
+#define mmSMBUS_TRIGGER_CNTL 0x00a2
+#define mmSMBUS_TRIGGER_CNTL_BASE_IDX 0
+#define mmSMBUS_UDID_CNTL0 0x00a3
+#define mmSMBUS_UDID_CNTL0_BASE_IDX 0
+#define mmSMBUS_UDID_CNTL1 0x00a4
+#define mmSMBUS_UDID_CNTL1_BASE_IDX 0
+#define mmSMBUS_UDID_CNTL2 0x00a5
+#define mmSMBUS_UDID_CNTL2_BASE_IDX 0
+#define mmSMBUS_BACO_DUMMY 0x00a8
+#define mmSMBUS_BACO_DUMMY_BASE_IDX 0
+#define mmSMBUS_BACO_ADDR_RANGE0_LOW 0x00a9
+#define mmSMBUS_BACO_ADDR_RANGE0_LOW_BASE_IDX 0
+#define mmSMBUS_BACO_ADDR_RANGE0_HIGH 0x00aa
+#define mmSMBUS_BACO_ADDR_RANGE0_HIGH_BASE_IDX 0
+#define mmSMBUS_BACO_ADDR_RANGE1_LOW 0x00ab
+#define mmSMBUS_BACO_ADDR_RANGE1_LOW_BASE_IDX 0
+#define mmSMBUS_BACO_ADDR_RANGE1_HIGH 0x00ac
+#define mmSMBUS_BACO_ADDR_RANGE1_HIGH_BASE_IDX 0
+#define mmSMBUS_BACO_ADDR_RANGE2_LOW 0x00ad
+#define mmSMBUS_BACO_ADDR_RANGE2_LOW_BASE_IDX 0
+#define mmSMBUS_BACO_ADDR_RANGE2_HIGH 0x00ae
+#define mmSMBUS_BACO_ADDR_RANGE2_HIGH_BASE_IDX 0
+#define mmSMBUS_BACO_ADDR_RANGE3_LOW 0x00af
+#define mmSMBUS_BACO_ADDR_RANGE3_LOW_BASE_IDX 0
+#define mmSMBUS_BACO_ADDR_RANGE3_HIGH 0x00b0
+#define mmSMBUS_BACO_ADDR_RANGE3_HIGH_BASE_IDX 0
+#define mmSMBUS_BACO_ADDR_RANGE4_LOW 0x00b1
+#define mmSMBUS_BACO_ADDR_RANGE4_LOW_BASE_IDX 0
+#define mmSMBUS_BACO_ADDR_RANGE4_HIGH 0x00b2
+#define mmSMBUS_BACO_ADDR_RANGE4_HIGH_BASE_IDX 0
+#define mmTHM_GPIO_MACO_EN_CTRL 0x00bd
+#define mmTHM_GPIO_MACO_EN_CTRL_BASE_IDX 0
+#define mmTHM_BACO_TIMING2 0x00bf
+#define mmTHM_BACO_TIMING2_BASE_IDX 0
+#define mmTHM_BACO_TIMING 0x00c0
+#define mmTHM_BACO_TIMING_BASE_IDX 0
+#define mmTHM_TMON0_REMOTE_START 0x0100
+#define mmTHM_TMON0_REMOTE_START_BASE_IDX 0
+#define mmTHM_TMON0_REMOTE_END 0x013f
+#define mmTHM_TMON0_REMOTE_END_BASE_IDX 0
+#define mmTHM_TMON1_REMOTE_START 0x0140
+#define mmTHM_TMON1_REMOTE_START_BASE_IDX 0
+#define mmTHM_TMON1_REMOTE_END 0x017f
+#define mmTHM_TMON1_REMOTE_END_BASE_IDX 0
+#define mmTHM_TMON2_REMOTE_START 0x0180
+#define mmTHM_TMON2_REMOTE_START_BASE_IDX 0
+#define mmTHM_TMON2_REMOTE_END 0x01bf
+#define mmTHM_TMON2_REMOTE_END_BASE_IDX 0
+#define mmTHM_TMON3_REMOTE_START 0x01c0
+#define mmTHM_TMON3_REMOTE_START_BASE_IDX 0
+#define mmTHM_TMON3_REMOTE_END 0x01ff
+#define mmTHM_TMON3_REMOTE_END_BASE_IDX 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_sh_mask.h
new file mode 100644
index 000000000000..f0306c5e3da3
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_sh_mask.h
@@ -0,0 +1,1314 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _thm_9_0_SH_MASK_HEADER
+#define _thm_9_0_SH_MASK_HEADER
+
+
+// addressBlock: thm_thm_SmuThmDec
+//THM_TCON_CUR_TMP
+#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0
+#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5
+#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7
+#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8
+#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10
+#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12
+#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13
+#define THM_TCON_CUR_TMP__MCM_EN__SHIFT 0x14
+#define THM_TCON_CUR_TMP__CUR_TEMP__SHIFT 0x15
+#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK 0x0000001FL
+#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK 0x00000060L
+#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK 0x00000080L
+#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK 0x00001F00L
+#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK 0x00030000L
+#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK 0x00040000L
+#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK 0x00080000L
+#define THM_TCON_CUR_TMP__MCM_EN_MASK 0x00100000L
+#define THM_TCON_CUR_TMP__CUR_TEMP_MASK 0xFFE00000L
+//THM_TCON_HTC
+#define THM_TCON_HTC__HTC_EN__SHIFT 0x0
+#define THM_TCON_HTC__EXTERNAL_PROCHOT__SHIFT 0x2
+#define THM_TCON_HTC__INTERNAL_PROCHOT__SHIFT 0x3
+#define THM_TCON_HTC__HTC_ACTIVE__SHIFT 0x4
+#define THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT 0x5
+#define THM_TCON_HTC__HTC_DIAG__SHIFT 0x8
+#define THM_TCON_HTC__DIS_PROCHOT_PIN__SHIFT 0x9
+#define THM_TCON_HTC__HTC_TO_IH_EN__SHIFT 0xa
+#define THM_TCON_HTC__PROCHOT_TO_IH_EN__SHIFT 0xb
+#define THM_TCON_HTC__PROCHOT_EVENT_SRC__SHIFT 0xc
+#define THM_TCON_HTC__HTC_TMP_LMT__SHIFT 0x10
+#define THM_TCON_HTC__HTC_HYST_LMT__SHIFT 0x17
+#define THM_TCON_HTC__HTC_SLEW_SEL__SHIFT 0x1b
+#define THM_TCON_HTC__HTC_EN_MASK 0x00000001L
+#define THM_TCON_HTC__EXTERNAL_PROCHOT_MASK 0x00000004L
+#define THM_TCON_HTC__INTERNAL_PROCHOT_MASK 0x00000008L
+#define THM_TCON_HTC__HTC_ACTIVE_MASK 0x00000010L
+#define THM_TCON_HTC__HTC_ACTIVE_LOG_MASK 0x00000020L
+#define THM_TCON_HTC__HTC_DIAG_MASK 0x00000100L
+#define THM_TCON_HTC__DIS_PROCHOT_PIN_MASK 0x00000200L
+#define THM_TCON_HTC__HTC_TO_IH_EN_MASK 0x00000400L
+#define THM_TCON_HTC__PROCHOT_TO_IH_EN_MASK 0x00000800L
+#define THM_TCON_HTC__PROCHOT_EVENT_SRC_MASK 0x00007000L
+#define THM_TCON_HTC__HTC_TMP_LMT_MASK 0x007F0000L
+#define THM_TCON_HTC__HTC_HYST_LMT_MASK 0x07800000L
+#define THM_TCON_HTC__HTC_SLEW_SEL_MASK 0x18000000L
+//THM_TCON_THERM_TRIP
+#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY__SHIFT 0x0
+#define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1
+#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED__SHIFT 0x2
+#define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT 0x3
+#define THM_TCON_THERM_TRIP__RSVD2__SHIFT 0x4
+#define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT 0x5
+#define THM_TCON_THERM_TRIP__THERM_TP_LMT__SHIFT 0x6
+#define THM_TCON_THERM_TRIP__RSVD3__SHIFT 0xe
+#define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT 0x1f
+#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY_MASK 0x00000001L
+#define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x00000002L
+#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED_MASK 0x00000004L
+#define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK 0x00000008L
+#define THM_TCON_THERM_TRIP__RSVD2_MASK 0x00000010L
+#define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK 0x00000020L
+#define THM_TCON_THERM_TRIP__THERM_TP_LMT_MASK 0x00003FC0L
+#define THM_TCON_THERM_TRIP__RSVD3_MASK 0x7FFFC000L
+#define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000L
+//THM_GPIO_PROCHOT_CTRL
+#define THM_GPIO_PROCHOT_CTRL__TXIMPSEL__SHIFT 0x0
+#define THM_GPIO_PROCHOT_CTRL__PD__SHIFT 0x1
+#define THM_GPIO_PROCHOT_CTRL__PU__SHIFT 0x2
+#define THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT 0x3
+#define THM_GPIO_PROCHOT_CTRL__S0__SHIFT 0x4
+#define THM_GPIO_PROCHOT_CTRL__S1__SHIFT 0x5
+#define THM_GPIO_PROCHOT_CTRL__RXEN__SHIFT 0x6
+#define THM_GPIO_PROCHOT_CTRL__RXSEL0__SHIFT 0x7
+#define THM_GPIO_PROCHOT_CTRL__RXSEL1__SHIFT 0x8
+#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT 0x10
+#define THM_GPIO_PROCHOT_CTRL__OE__SHIFT 0x11
+#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE__SHIFT 0x12
+#define THM_GPIO_PROCHOT_CTRL__A__SHIFT 0x13
+#define THM_GPIO_PROCHOT_CTRL__Y__SHIFT 0x1f
+#define THM_GPIO_PROCHOT_CTRL__TXIMPSEL_MASK 0x00000001L
+#define THM_GPIO_PROCHOT_CTRL__PD_MASK 0x00000002L
+#define THM_GPIO_PROCHOT_CTRL__PU_MASK 0x00000004L
+#define THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK 0x00000008L
+#define THM_GPIO_PROCHOT_CTRL__S0_MASK 0x00000010L
+#define THM_GPIO_PROCHOT_CTRL__S1_MASK 0x00000020L
+#define THM_GPIO_PROCHOT_CTRL__RXEN_MASK 0x00000040L
+#define THM_GPIO_PROCHOT_CTRL__RXSEL0_MASK 0x00000080L
+#define THM_GPIO_PROCHOT_CTRL__RXSEL1_MASK 0x00000100L
+#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK 0x00010000L
+#define THM_GPIO_PROCHOT_CTRL__OE_MASK 0x00020000L
+#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE_MASK 0x00040000L
+#define THM_GPIO_PROCHOT_CTRL__A_MASK 0x00080000L
+#define THM_GPIO_PROCHOT_CTRL__Y_MASK 0x80000000L
+//THM_GPIO_THERMTRIP_CTRL
+#define THM_GPIO_THERMTRIP_CTRL__TXIMPSEL__SHIFT 0x0
+#define THM_GPIO_THERMTRIP_CTRL__PD__SHIFT 0x1
+#define THM_GPIO_THERMTRIP_CTRL__PU__SHIFT 0x2
+#define THM_GPIO_THERMTRIP_CTRL__SCHMEN__SHIFT 0x3
+#define THM_GPIO_THERMTRIP_CTRL__S0__SHIFT 0x4
+#define THM_GPIO_THERMTRIP_CTRL__S1__SHIFT 0x5
+#define THM_GPIO_THERMTRIP_CTRL__RXEN__SHIFT 0x6
+#define THM_GPIO_THERMTRIP_CTRL__RXSEL0__SHIFT 0x7
+#define THM_GPIO_THERMTRIP_CTRL__RXSEL1__SHIFT 0x8
+#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE__SHIFT 0x10
+#define THM_GPIO_THERMTRIP_CTRL__OE__SHIFT 0x11
+#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE__SHIFT 0x12
+#define THM_GPIO_THERMTRIP_CTRL__A__SHIFT 0x13
+#define THM_GPIO_THERMTRIP_CTRL__CTFEN__SHIFT 0x14
+#define THM_GPIO_THERMTRIP_CTRL__Y__SHIFT 0x1f
+#define THM_GPIO_THERMTRIP_CTRL__TXIMPSEL_MASK 0x00000001L
+#define THM_GPIO_THERMTRIP_CTRL__PD_MASK 0x00000002L
+#define THM_GPIO_THERMTRIP_CTRL__PU_MASK 0x00000004L
+#define THM_GPIO_THERMTRIP_CTRL__SCHMEN_MASK 0x00000008L
+#define THM_GPIO_THERMTRIP_CTRL__S0_MASK 0x00000010L
+#define THM_GPIO_THERMTRIP_CTRL__S1_MASK 0x00000020L
+#define THM_GPIO_THERMTRIP_CTRL__RXEN_MASK 0x00000040L
+#define THM_GPIO_THERMTRIP_CTRL__RXSEL0_MASK 0x00000080L
+#define THM_GPIO_THERMTRIP_CTRL__RXSEL1_MASK 0x00000100L
+#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE_MASK 0x00010000L
+#define THM_GPIO_THERMTRIP_CTRL__OE_MASK 0x00020000L
+#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE_MASK 0x00040000L
+#define THM_GPIO_THERMTRIP_CTRL__A_MASK 0x00080000L
+#define THM_GPIO_THERMTRIP_CTRL__CTFEN_MASK 0x00100000L
+#define THM_GPIO_THERMTRIP_CTRL__Y_MASK 0x80000000L
+//THM_GPIO_PWM_CTRL
+#define THM_GPIO_PWM_CTRL__TXIMPSEL__SHIFT 0x0
+#define THM_GPIO_PWM_CTRL__PD__SHIFT 0x1
+#define THM_GPIO_PWM_CTRL__PU__SHIFT 0x2
+#define THM_GPIO_PWM_CTRL__SCHMEN__SHIFT 0x3
+#define THM_GPIO_PWM_CTRL__S0__SHIFT 0x4
+#define THM_GPIO_PWM_CTRL__S1__SHIFT 0x5
+#define THM_GPIO_PWM_CTRL__RXEN__SHIFT 0x6
+#define THM_GPIO_PWM_CTRL__RXSEL0__SHIFT 0x7
+#define THM_GPIO_PWM_CTRL__RXSEL1__SHIFT 0x8
+#define THM_GPIO_PWM_CTRL__OE_OVERRIDE__SHIFT 0x10
+#define THM_GPIO_PWM_CTRL__OE__SHIFT 0x11
+#define THM_GPIO_PWM_CTRL__A_OVERRIDE__SHIFT 0x12
+#define THM_GPIO_PWM_CTRL__A__SHIFT 0x13
+#define THM_GPIO_PWM_CTRL__Y__SHIFT 0x1f
+#define THM_GPIO_PWM_CTRL__TXIMPSEL_MASK 0x00000001L
+#define THM_GPIO_PWM_CTRL__PD_MASK 0x00000002L
+#define THM_GPIO_PWM_CTRL__PU_MASK 0x00000004L
+#define THM_GPIO_PWM_CTRL__SCHMEN_MASK 0x00000008L
+#define THM_GPIO_PWM_CTRL__S0_MASK 0x00000010L
+#define THM_GPIO_PWM_CTRL__S1_MASK 0x00000020L
+#define THM_GPIO_PWM_CTRL__RXEN_MASK 0x00000040L
+#define THM_GPIO_PWM_CTRL__RXSEL0_MASK 0x00000080L
+#define THM_GPIO_PWM_CTRL__RXSEL1_MASK 0x00000100L
+#define THM_GPIO_PWM_CTRL__OE_OVERRIDE_MASK 0x00010000L
+#define THM_GPIO_PWM_CTRL__OE_MASK 0x00020000L
+#define THM_GPIO_PWM_CTRL__A_OVERRIDE_MASK 0x00040000L
+#define THM_GPIO_PWM_CTRL__A_MASK 0x00080000L
+#define THM_GPIO_PWM_CTRL__Y_MASK 0x80000000L
+//THM_GPIO_TACHIN_CTRL
+#define THM_GPIO_TACHIN_CTRL__TXIMPSEL__SHIFT 0x0
+#define THM_GPIO_TACHIN_CTRL__PD__SHIFT 0x1
+#define THM_GPIO_TACHIN_CTRL__PU__SHIFT 0x2
+#define THM_GPIO_TACHIN_CTRL__SCHMEN__SHIFT 0x3
+#define THM_GPIO_TACHIN_CTRL__S0__SHIFT 0x4
+#define THM_GPIO_TACHIN_CTRL__S1__SHIFT 0x5
+#define THM_GPIO_TACHIN_CTRL__RXEN__SHIFT 0x6
+#define THM_GPIO_TACHIN_CTRL__RXSEL0__SHIFT 0x7
+#define THM_GPIO_TACHIN_CTRL__RXSEL1__SHIFT 0x8
+#define THM_GPIO_TACHIN_CTRL__OE_OVERRIDE__SHIFT 0x10
+#define THM_GPIO_TACHIN_CTRL__OE__SHIFT 0x11
+#define THM_GPIO_TACHIN_CTRL__A_OVERRIDE__SHIFT 0x12
+#define THM_GPIO_TACHIN_CTRL__A__SHIFT 0x13
+#define THM_GPIO_TACHIN_CTRL__Y__SHIFT 0x1f
+#define THM_GPIO_TACHIN_CTRL__TXIMPSEL_MASK 0x00000001L
+#define THM_GPIO_TACHIN_CTRL__PD_MASK 0x00000002L
+#define THM_GPIO_TACHIN_CTRL__PU_MASK 0x00000004L
+#define THM_GPIO_TACHIN_CTRL__SCHMEN_MASK 0x00000008L
+#define THM_GPIO_TACHIN_CTRL__S0_MASK 0x00000010L
+#define THM_GPIO_TACHIN_CTRL__S1_MASK 0x00000020L
+#define THM_GPIO_TACHIN_CTRL__RXEN_MASK 0x00000040L
+#define THM_GPIO_TACHIN_CTRL__RXSEL0_MASK 0x00000080L
+#define THM_GPIO_TACHIN_CTRL__RXSEL1_MASK 0x00000100L
+#define THM_GPIO_TACHIN_CTRL__OE_OVERRIDE_MASK 0x00010000L
+#define THM_GPIO_TACHIN_CTRL__OE_MASK 0x00020000L
+#define THM_GPIO_TACHIN_CTRL__A_OVERRIDE_MASK 0x00040000L
+#define THM_GPIO_TACHIN_CTRL__A_MASK 0x00080000L
+#define THM_GPIO_TACHIN_CTRL__Y_MASK 0x80000000L
+//THM_GPIO_PUMPOUT_CTRL
+#define THM_GPIO_PUMPOUT_CTRL__TXIMPSEL__SHIFT 0x0
+#define THM_GPIO_PUMPOUT_CTRL__PD__SHIFT 0x1
+#define THM_GPIO_PUMPOUT_CTRL__PU__SHIFT 0x2
+#define THM_GPIO_PUMPOUT_CTRL__SCHMEN__SHIFT 0x3
+#define THM_GPIO_PUMPOUT_CTRL__S0__SHIFT 0x4
+#define THM_GPIO_PUMPOUT_CTRL__S1__SHIFT 0x5
+#define THM_GPIO_PUMPOUT_CTRL__RXEN__SHIFT 0x6
+#define THM_GPIO_PUMPOUT_CTRL__RXSEL0__SHIFT 0x7
+#define THM_GPIO_PUMPOUT_CTRL__RXSEL1__SHIFT 0x8
+#define THM_GPIO_PUMPOUT_CTRL__OE_OVERRIDE__SHIFT 0x10
+#define THM_GPIO_PUMPOUT_CTRL__OE__SHIFT 0x11
+#define THM_GPIO_PUMPOUT_CTRL__A_OVERRIDE__SHIFT 0x12
+#define THM_GPIO_PUMPOUT_CTRL__A__SHIFT 0x13
+#define THM_GPIO_PUMPOUT_CTRL__Y__SHIFT 0x1f
+#define THM_GPIO_PUMPOUT_CTRL__TXIMPSEL_MASK 0x00000001L
+#define THM_GPIO_PUMPOUT_CTRL__PD_MASK 0x00000002L
+#define THM_GPIO_PUMPOUT_CTRL__PU_MASK 0x00000004L
+#define THM_GPIO_PUMPOUT_CTRL__SCHMEN_MASK 0x00000008L
+#define THM_GPIO_PUMPOUT_CTRL__S0_MASK 0x00000010L
+#define THM_GPIO_PUMPOUT_CTRL__S1_MASK 0x00000020L
+#define THM_GPIO_PUMPOUT_CTRL__RXEN_MASK 0x00000040L
+#define THM_GPIO_PUMPOUT_CTRL__RXSEL0_MASK 0x00000080L
+#define THM_GPIO_PUMPOUT_CTRL__RXSEL1_MASK 0x00000100L
+#define THM_GPIO_PUMPOUT_CTRL__OE_OVERRIDE_MASK 0x00010000L
+#define THM_GPIO_PUMPOUT_CTRL__OE_MASK 0x00020000L
+#define THM_GPIO_PUMPOUT_CTRL__A_OVERRIDE_MASK 0x00040000L
+#define THM_GPIO_PUMPOUT_CTRL__A_MASK 0x00080000L
+#define THM_GPIO_PUMPOUT_CTRL__Y_MASK 0x80000000L
+//THM_GPIO_PUMPIN_CTRL
+#define THM_GPIO_PUMPIN_CTRL__TXIMPSEL__SHIFT 0x0
+#define THM_GPIO_PUMPIN_CTRL__PD__SHIFT 0x1
+#define THM_GPIO_PUMPIN_CTRL__PU__SHIFT 0x2
+#define THM_GPIO_PUMPIN_CTRL__SCHMEN__SHIFT 0x3
+#define THM_GPIO_PUMPIN_CTRL__S0__SHIFT 0x4
+#define THM_GPIO_PUMPIN_CTRL__S1__SHIFT 0x5
+#define THM_GPIO_PUMPIN_CTRL__RXEN__SHIFT 0x6
+#define THM_GPIO_PUMPIN_CTRL__RXSEL0__SHIFT 0x7
+#define THM_GPIO_PUMPIN_CTRL__RXSEL1__SHIFT 0x8
+#define THM_GPIO_PUMPIN_CTRL__OE_OVERRIDE__SHIFT 0x10
+#define THM_GPIO_PUMPIN_CTRL__OE__SHIFT 0x11
+#define THM_GPIO_PUMPIN_CTRL__A_OVERRIDE__SHIFT 0x12
+#define THM_GPIO_PUMPIN_CTRL__A__SHIFT 0x13
+#define THM_GPIO_PUMPIN_CTRL__Y__SHIFT 0x1f
+#define THM_GPIO_PUMPIN_CTRL__TXIMPSEL_MASK 0x00000001L
+#define THM_GPIO_PUMPIN_CTRL__PD_MASK 0x00000002L
+#define THM_GPIO_PUMPIN_CTRL__PU_MASK 0x00000004L
+#define THM_GPIO_PUMPIN_CTRL__SCHMEN_MASK 0x00000008L
+#define THM_GPIO_PUMPIN_CTRL__S0_MASK 0x00000010L
+#define THM_GPIO_PUMPIN_CTRL__S1_MASK 0x00000020L
+#define THM_GPIO_PUMPIN_CTRL__RXEN_MASK 0x00000040L
+#define THM_GPIO_PUMPIN_CTRL__RXSEL0_MASK 0x00000080L
+#define THM_GPIO_PUMPIN_CTRL__RXSEL1_MASK 0x00000100L
+#define THM_GPIO_PUMPIN_CTRL__OE_OVERRIDE_MASK 0x00010000L
+#define THM_GPIO_PUMPIN_CTRL__OE_MASK 0x00020000L
+#define THM_GPIO_PUMPIN_CTRL__A_OVERRIDE_MASK 0x00040000L
+#define THM_GPIO_PUMPIN_CTRL__A_MASK 0x00080000L
+#define THM_GPIO_PUMPIN_CTRL__Y_MASK 0x80000000L
+//THM_THERMAL_INT_ENA
+#define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
+#define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
+#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
+#define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3
+#define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4
+#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5
+#define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x00000001L
+#define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x00000002L
+#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x00000004L
+#define THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x00000008L
+#define THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x00000010L
+#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x00000020L
+//THM_THERMAL_INT_CTRL
+#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0
+#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8
+#define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD__SHIFT 0x10
+#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18
+#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19
+#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a
+#define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK__SHIFT 0x1b
+#define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT 0x1c
+#define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT 0x1d
+#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0x000000FFL
+#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0x0000FF00L
+#define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD_MASK 0x00FF0000L
+#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x01000000L
+#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x02000000L
+#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x04000000L
+#define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK_MASK 0x08000000L
+#define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK 0x10000000L
+#define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK 0xE0000000L
+//THM_THERMAL_INT_STATUS
+#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0
+#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1
+#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2
+#define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT__SHIFT 0x3
+#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x00000001L
+#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x00000002L
+#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x00000004L
+#define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT_MASK 0x00000008L
+//THM_TMON0_RDIL0_DATA
+#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL0_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL1_DATA
+#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL1_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL2_DATA
+#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL2_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL3_DATA
+#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL3_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL4_DATA
+#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL4_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL5_DATA
+#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL5_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL6_DATA
+#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL6_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL7_DATA
+#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL7_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL8_DATA
+#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL8_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL9_DATA
+#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL9_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL10_DATA
+#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL10_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL11_DATA
+#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL11_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL12_DATA
+#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL12_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL13_DATA
+#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL13_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL14_DATA
+#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL14_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL15_DATA
+#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL15_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR0_DATA
+#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR0_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR1_DATA
+#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR1_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR2_DATA
+#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR2_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR3_DATA
+#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR3_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR4_DATA
+#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR4_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR5_DATA
+#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR5_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR6_DATA
+#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR6_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR7_DATA
+#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR7_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR8_DATA
+#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR8_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR9_DATA
+#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR9_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR10_DATA
+#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR10_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR11_DATA
+#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR11_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR12_DATA
+#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR12_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR13_DATA
+#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR13_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR14_DATA
+#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR14_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR15_DATA
+#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR15_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_INT_DATA
+#define THM_TMON0_INT_DATA__Z__SHIFT 0x0
+#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_INT_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_INT_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_INT_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_DEBUG
+#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0
+#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5
+#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x0000001FL
+#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0x0000FFE0L
+//THM_TMON1_RDIL0_DATA
+#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL0_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL1_DATA
+#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL1_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL2_DATA
+#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL2_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL3_DATA
+#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL3_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL4_DATA
+#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL4_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL5_DATA
+#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL5_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL6_DATA
+#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL6_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL7_DATA
+#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL7_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL8_DATA
+#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL8_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL9_DATA
+#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL9_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL10_DATA
+#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL10_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL11_DATA
+#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL11_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL12_DATA
+#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL12_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL13_DATA
+#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL13_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL14_DATA
+#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL14_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL15_DATA
+#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL15_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR0_DATA
+#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR0_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR1_DATA
+#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR1_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR2_DATA
+#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR2_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR3_DATA
+#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR3_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR4_DATA
+#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR4_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR5_DATA
+#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR5_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR6_DATA
+#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR6_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR7_DATA
+#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR7_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR8_DATA
+#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR8_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR9_DATA
+#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR9_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR10_DATA
+#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR10_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR11_DATA
+#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR11_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR12_DATA
+#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR12_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR13_DATA
+#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR13_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR14_DATA
+#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR14_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR15_DATA
+#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR15_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_INT_DATA
+#define THM_TMON1_INT_DATA__Z__SHIFT 0x0
+#define THM_TMON1_INT_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_INT_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_INT_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_INT_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_INT_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_DEBUG
+#define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT 0x0
+#define THM_TMON1_DEBUG__DEBUG_Z__SHIFT 0x5
+#define THM_TMON1_DEBUG__DEBUG_RDI_MASK 0x0000001FL
+#define THM_TMON1_DEBUG__DEBUG_Z_MASK 0x0000FFE0L
+//THM_DIE1_TEMP
+#define THM_DIE1_TEMP__TEMP__SHIFT 0x0
+#define THM_DIE1_TEMP__VALID__SHIFT 0xb
+#define THM_DIE1_TEMP__TEMP_MASK 0x000007FFL
+#define THM_DIE1_TEMP__VALID_MASK 0x00000800L
+//THM_DIE2_TEMP
+#define THM_DIE2_TEMP__TEMP__SHIFT 0x0
+#define THM_DIE2_TEMP__VALID__SHIFT 0xb
+#define THM_DIE2_TEMP__TEMP_MASK 0x000007FFL
+#define THM_DIE2_TEMP__VALID_MASK 0x00000800L
+//THM_DIE3_TEMP
+#define THM_DIE3_TEMP__TEMP__SHIFT 0x0
+#define THM_DIE3_TEMP__VALID__SHIFT 0xb
+#define THM_DIE3_TEMP__TEMP_MASK 0x000007FFL
+#define THM_DIE3_TEMP__VALID_MASK 0x00000800L
+//CG_MULT_THERMAL_CTRL
+#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0
+#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4
+#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9
+#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14
+#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0x0000000FL
+#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0x000001F0L
+#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x00000200L
+#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0x0FF00000L
+//CG_MULT_THERMAL_STATUS
+#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0
+#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9
+#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x000001FFL
+#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x0003FE00L
+//THM_TMON0_COEFF
+#define THM_TMON0_COEFF__C_OFFSET__SHIFT 0x0
+#define THM_TMON0_COEFF__D__SHIFT 0xb
+#define THM_TMON0_COEFF__C_OFFSET_MASK 0x000007FFL
+#define THM_TMON0_COEFF__D_MASK 0x0003F800L
+//THM_TMON1_COEFF
+#define THM_TMON1_COEFF__C_OFFSET__SHIFT 0x0
+#define THM_TMON1_COEFF__D__SHIFT 0xb
+#define THM_TMON1_COEFF__C_OFFSET_MASK 0x000007FFL
+#define THM_TMON1_COEFF__D_MASK 0x0003F800L
+//CG_FDO_CTRL0
+#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0
+#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8
+#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10
+#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17
+#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18
+#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0x000000FFL
+#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0x0000FF00L
+#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x00010000L
+#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x007E0000L
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x00800000L
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xFF000000L
+//CG_FDO_CTRL1
+#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0
+#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8
+#define CG_FDO_CTRL1__M__SHIFT 0x10
+#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18
+#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0x000000FFL
+#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0x0000FF00L
+#define CG_FDO_CTRL1__M_MASK 0x00FF0000L
+#define CG_FDO_CTRL1__RESERVED_MASK 0x3F000000L
+//CG_FDO_CTRL2
+#define CG_FDO_CTRL2__TMIN__SHIFT 0x0
+#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8
+#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb
+#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe
+#define CG_FDO_CTRL2__TMAX__SHIFT 0x11
+#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19
+#define CG_FDO_CTRL2__TMIN_MASK 0x000000FFL
+#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x00000700L
+#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x00003800L
+#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x0001C000L
+#define CG_FDO_CTRL2__TMAX_MASK 0x01FE0000L
+#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xFE000000L
+//CG_TACH_CTRL
+#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0
+#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3
+#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x00000007L
+#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L
+//CG_TACH_STATUS
+#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0
+#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xFFFFFFFFL
+//CG_THERMAL_STATUS
+#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9
+#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x0001FE00L
+//CG_PUMP_CTRL0
+#define CG_PUMP_CTRL0__PUMP_STATIC_DUTY__SHIFT 0x0
+#define CG_PUMP_CTRL0__PUMP_SPINUP_DUTY__SHIFT 0x8
+#define CG_PUMP_CTRL0__PUMP_PWM_MANUAL__SHIFT 0x10
+#define CG_PUMP_CTRL0__PUMP_PWM_HYSTER__SHIFT 0x11
+#define CG_PUMP_CTRL0__PUMP_PWM_RAMP_EN__SHIFT 0x17
+#define CG_PUMP_CTRL0__PUMP_PWM_RAMP__SHIFT 0x18
+#define CG_PUMP_CTRL0__PUMP_STATIC_DUTY_MASK 0x000000FFL
+#define CG_PUMP_CTRL0__PUMP_SPINUP_DUTY_MASK 0x0000FF00L
+#define CG_PUMP_CTRL0__PUMP_PWM_MANUAL_MASK 0x00010000L
+#define CG_PUMP_CTRL0__PUMP_PWM_HYSTER_MASK 0x007E0000L
+#define CG_PUMP_CTRL0__PUMP_PWM_RAMP_EN_MASK 0x00800000L
+#define CG_PUMP_CTRL0__PUMP_PWM_RAMP_MASK 0xFF000000L
+//CG_PUMP_CTRL1
+#define CG_PUMP_CTRL1__PMAX_DUTY100__SHIFT 0x0
+#define CG_PUMP_CTRL1__PMIN_DUTY__SHIFT 0x8
+#define CG_PUMP_CTRL1__M__SHIFT 0x10
+#define CG_PUMP_CTRL1__RESERVED__SHIFT 0x18
+#define CG_PUMP_CTRL1__PMAX_DUTY100_MASK 0x000000FFL
+#define CG_PUMP_CTRL1__PMIN_DUTY_MASK 0x0000FF00L
+#define CG_PUMP_CTRL1__M_MASK 0x00FF0000L
+#define CG_PUMP_CTRL1__RESERVED_MASK 0x3F000000L
+//CG_PUMP_CTRL2
+#define CG_PUMP_CTRL2__TMIN__SHIFT 0x0
+#define CG_PUMP_CTRL2__PUMP_SPINUP_TIME__SHIFT 0x8
+#define CG_PUMP_CTRL2__PUMP_PWM_MODE__SHIFT 0xb
+#define CG_PUMP_CTRL2__TMIN_HYSTER__SHIFT 0xe
+#define CG_PUMP_CTRL2__TMAX__SHIFT 0x11
+#define CG_PUMP_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19
+#define CG_PUMP_CTRL2__TMIN_MASK 0x000000FFL
+#define CG_PUMP_CTRL2__PUMP_SPINUP_TIME_MASK 0x00000700L
+#define CG_PUMP_CTRL2__PUMP_PWM_MODE_MASK 0x00003800L
+#define CG_PUMP_CTRL2__TMIN_HYSTER_MASK 0x0001C000L
+#define CG_PUMP_CTRL2__TMAX_MASK 0x01FE0000L
+#define CG_PUMP_CTRL2__TACH_PWM_RESP_RATE_MASK 0xFE000000L
+//CG_PUMP_TACH_CTRL
+#define CG_PUMP_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0
+#define CG_PUMP_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3
+#define CG_PUMP_TACH_CTRL__EDGE_PER_REV_MASK 0x00000007L
+#define CG_PUMP_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L
+//CG_PUMP_TACH_STATUS
+#define CG_PUMP_TACH_STATUS__TACH_PERIOD__SHIFT 0x0
+#define CG_PUMP_TACH_STATUS__TACH_PERIOD_MASK 0xFFFFFFFFL
+//CG_PUMP_STATUS
+#define CG_PUMP_STATUS__PUMP_PWM_DUTY__SHIFT 0x9
+#define CG_PUMP_STATUS__PUMP_PWM_DUTY_MASK 0x0001FE00L
+//THM_TCON_LOCAL0
+#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis__SHIFT 0x1
+#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis__SHIFT 0x2
+#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis_MASK 0x00000002L
+#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis_MASK 0x00000004L
+//THM_TCON_LOCAL1
+#define THM_TCON_LOCAL1__Turn_Off_TMON0__SHIFT 0x0
+#define THM_TCON_LOCAL1__Turn_Off_TMON1__SHIFT 0x1
+#define THM_TCON_LOCAL1__PowerDownTmon0__SHIFT 0x4
+#define THM_TCON_LOCAL1__PowerDownTmon1__SHIFT 0x5
+#define THM_TCON_LOCAL1__Turn_Off_TMON0_MASK 0x00000001L
+#define THM_TCON_LOCAL1__Turn_Off_TMON1_MASK 0x00000002L
+#define THM_TCON_LOCAL1__PowerDownTmon0_MASK 0x00000010L
+#define THM_TCON_LOCAL1__PowerDownTmon1_MASK 0x00000020L
+//THM_TCON_LOCAL2
+#define THM_TCON_LOCAL2__TMON_init_delay__SHIFT 0x0
+#define THM_TCON_LOCAL2__TMON_pwrup_stagger_time__SHIFT 0x2
+#define THM_TCON_LOCAL2__short_stagger_count__SHIFT 0x5
+#define THM_TCON_LOCAL2__sbtsi_use_corrected__SHIFT 0x6
+#define THM_TCON_LOCAL2__temp_read_skip_scale__SHIFT 0xa
+#define THM_TCON_LOCAL2__skip_scale_correction__SHIFT 0xb
+#define THM_TCON_LOCAL2__TMON_init_delay_MASK 0x00000003L
+#define THM_TCON_LOCAL2__TMON_pwrup_stagger_time_MASK 0x0000000CL
+#define THM_TCON_LOCAL2__short_stagger_count_MASK 0x00000020L
+#define THM_TCON_LOCAL2__sbtsi_use_corrected_MASK 0x00000040L
+#define THM_TCON_LOCAL2__temp_read_skip_scale_MASK 0x00000400L
+#define THM_TCON_LOCAL2__skip_scale_correction_MASK 0x00000800L
+//THM_TCON_LOCAL3
+#define THM_TCON_LOCAL3__Global_TMAX__SHIFT 0x0
+#define THM_TCON_LOCAL3__Global_TMAX_MASK 0x000007FFL
+//THM_TCON_LOCAL4
+#define THM_TCON_LOCAL4__Global_TMAX_ID__SHIFT 0x0
+#define THM_TCON_LOCAL4__Global_TMAX_ID_MASK 0x000000FFL
+//THM_TCON_LOCAL5
+#define THM_TCON_LOCAL5__Global_TMIN__SHIFT 0x0
+#define THM_TCON_LOCAL5__Global_TMIN_MASK 0x000007FFL
+//THM_TCON_LOCAL6
+#define THM_TCON_LOCAL6__Global_TMIN_ID__SHIFT 0x0
+#define THM_TCON_LOCAL6__Global_TMIN_ID_MASK 0x000000FFL
+//THM_TCON_LOCAL7
+#define THM_TCON_LOCAL7__THERMID__SHIFT 0x0
+#define THM_TCON_LOCAL7__THERMID_MASK 0x000000FFL
+//THM_TCON_LOCAL8
+#define THM_TCON_LOCAL8__THERMMAX__SHIFT 0x0
+#define THM_TCON_LOCAL8__THERMMAX_MASK 0x000007FFL
+//THM_TCON_LOCAL9
+#define THM_TCON_LOCAL9__Tj_Max_TMON0__SHIFT 0x0
+#define THM_TCON_LOCAL9__Tj_Max_TMON0_MASK 0x000007FFL
+//THM_TCON_LOCAL10
+#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID__SHIFT 0x0
+#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID_MASK 0x000000FFL
+//THM_TCON_LOCAL11
+#define THM_TCON_LOCAL11__Tj_Max_TMON1__SHIFT 0x0
+#define THM_TCON_LOCAL11__Tj_Max_TMON1_MASK 0x000007FFL
+//THM_TCON_LOCAL12
+#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID__SHIFT 0x0
+#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID_MASK 0x000000FFL
+//THM_TCON_LOCAL13
+#define THM_TCON_LOCAL13__boot_done__SHIFT 0x0
+#define THM_TCON_LOCAL13__boot_done_MASK 0x00000001L
+//THM_BACO_CNTL
+#define THM_BACO_CNTL__BACO_MODE__SHIFT 0x0
+#define THM_BACO_CNTL__BACO_ISO_EN__SHIFT 0x1
+#define THM_BACO_CNTL__BACO_PWROKRAW_CNTL__SHIFT 0x2
+#define THM_BACO_CNTL__BACO_RESET_EN__SHIFT 0x3
+#define THM_BACO_CNTL__BACO_SOC_VDCI_RESET__SHIFT 0x4
+#define THM_BACO_CNTL__BACO_SMNCLK_MUX__SHIFT 0x5
+#define THM_BACO_CNTL__BACO_SOC_REFCLK_OFF__SHIFT 0x6
+#define THM_BACO_CNTL__BACO_AEB_ISO_EN__SHIFT 0x7
+#define THM_BACO_CNTL__BACO_EXIT__SHIFT 0x8
+#define THM_BACO_CNTL__BACO_ANA_ISO_EN__SHIFT 0x9
+#define THM_BACO_CNTL__BACO_SB_AXI_FENCE__SHIFT 0x1e
+#define THM_BACO_CNTL__SOC_DOMAIN_IDLE__SHIFT 0x1f
+#define THM_BACO_CNTL__BACO_MODE_MASK 0x00000001L
+#define THM_BACO_CNTL__BACO_ISO_EN_MASK 0x00000002L
+#define THM_BACO_CNTL__BACO_PWROKRAW_CNTL_MASK 0x00000004L
+#define THM_BACO_CNTL__BACO_RESET_EN_MASK 0x00000008L
+#define THM_BACO_CNTL__BACO_SOC_VDCI_RESET_MASK 0x00000010L
+#define THM_BACO_CNTL__BACO_SMNCLK_MUX_MASK 0x00000020L
+#define THM_BACO_CNTL__BACO_SOC_REFCLK_OFF_MASK 0x00000040L
+#define THM_BACO_CNTL__BACO_AEB_ISO_EN_MASK 0x00000080L
+#define THM_BACO_CNTL__BACO_EXIT_MASK 0x00000100L
+#define THM_BACO_CNTL__BACO_ANA_ISO_EN_MASK 0x00000200L
+#define THM_BACO_CNTL__BACO_SB_AXI_FENCE_MASK 0x40000000L
+#define THM_BACO_CNTL__SOC_DOMAIN_IDLE_MASK 0x80000000L
+//THM_BACO_TIMING0
+#define THM_BACO_TIMING0__BACO_ISO_EXIT_CNT__SHIFT 0x0
+#define THM_BACO_TIMING0__BACO_PWROKRAW_EXIT_CNT__SHIFT 0x8
+#define THM_BACO_TIMING0__BACO_RESET_EXIT_CNT__SHIFT 0x10
+#define THM_BACO_TIMING0__BACO_VDCI_RESET_EXIT_CNT__SHIFT 0x18
+#define THM_BACO_TIMING0__BACO_ISO_EXIT_CNT_MASK 0x000000FFL
+#define THM_BACO_TIMING0__BACO_PWROKRAW_EXIT_CNT_MASK 0x0000FF00L
+#define THM_BACO_TIMING0__BACO_RESET_EXIT_CNT_MASK 0x00FF0000L
+#define THM_BACO_TIMING0__BACO_VDCI_RESET_EXIT_CNT_MASK 0xFF000000L
+//THM_BACO_TIMING1
+#define THM_BACO_TIMING1__BACO_SMNCLK_EXIT_CNT__SHIFT 0x0
+#define THM_BACO_TIMING1__BACO_FENCE_EXIT_CNT__SHIFT 0x8
+#define THM_BACO_TIMING1__BACO_REFCLK_EXIT_CNT__SHIFT 0x10
+#define THM_BACO_TIMING1__BACO_MODE_EXIT_CNT__SHIFT 0x18
+#define THM_BACO_TIMING1__BACO_SMNCLK_EXIT_CNT_MASK 0x000000FFL
+#define THM_BACO_TIMING1__BACO_FENCE_EXIT_CNT_MASK 0x0000FF00L
+#define THM_BACO_TIMING1__BACO_REFCLK_EXIT_CNT_MASK 0x00FF0000L
+#define THM_BACO_TIMING1__BACO_MODE_EXIT_CNT_MASK 0xFF000000L
+//XTAL_CNTL
+#define XTAL_CNTL__PCIE_REFCLK_SWITCH__SHIFT 0x0
+#define XTAL_CNTL__CORE_XTAL_CLKGEN_CLKEN__SHIFT 0x4
+#define XTAL_CNTL__CORE_XTAL_PWDN__SHIFT 0x8
+#define XTAL_CNTL__OSC_GAIN_EN__SHIFT 0xc
+#define XTAL_CNTL__PCIE_REFCLK_SWITCH_MASK 0x00000001L
+#define XTAL_CNTL__CORE_XTAL_CLKGEN_CLKEN_MASK 0x00000010L
+#define XTAL_CNTL__CORE_XTAL_PWDN_MASK 0x00000100L
+#define XTAL_CNTL__OSC_GAIN_EN_MASK 0x00007000L
+//SBTSI_REMOTE_TEMP
+#define SBTSI_REMOTE_TEMP__RemoteTcenSensor__SHIFT 0x0
+#define SBTSI_REMOTE_TEMP__RemoteTcenSensorId__SHIFT 0xb
+#define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid__SHIFT 0x13
+#define SBTSI_REMOTE_TEMP__RemoteTcenSensor_MASK 0x000007FFL
+#define SBTSI_REMOTE_TEMP__RemoteTcenSensorId_MASK 0x0007F800L
+#define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid_MASK 0x00080000L
+//SBRMI_CONTROL
+#define SBRMI_CONTROL__READ_CMD_INT_DIS__SHIFT 0x0
+#define SBRMI_CONTROL__DPD__SHIFT 0x1
+#define SBRMI_CONTROL__DbrdySts__SHIFT 0x2
+#define SBRMI_CONTROL__READ_CMD_INT_DIS_MASK 0x00000001L
+#define SBRMI_CONTROL__DPD_MASK 0x00000002L
+#define SBRMI_CONTROL__DbrdySts_MASK 0x00000004L
+//SBRMI_COMMAND
+#define SBRMI_COMMAND__Command__SHIFT 0x0
+#define SBRMI_COMMAND__WrDataLen__SHIFT 0x8
+#define SBRMI_COMMAND__RdDataLen__SHIFT 0x10
+#define SBRMI_COMMAND__CommandSent__SHIFT 0x18
+#define SBRMI_COMMAND__CommandNotSupported__SHIFT 0x19
+#define SBRMI_COMMAND__CommandAborted__SHIFT 0x1a
+#define SBRMI_COMMAND__Status__SHIFT 0x1c
+#define SBRMI_COMMAND__Command_MASK 0x000000FFL
+#define SBRMI_COMMAND__WrDataLen_MASK 0x0000FF00L
+#define SBRMI_COMMAND__RdDataLen_MASK 0x00FF0000L
+#define SBRMI_COMMAND__CommandSent_MASK 0x01000000L
+#define SBRMI_COMMAND__CommandNotSupported_MASK 0x02000000L
+#define SBRMI_COMMAND__CommandAborted_MASK 0x04000000L
+#define SBRMI_COMMAND__Status_MASK 0xF0000000L
+//SBRMI_WRITE_DATA0
+#define SBRMI_WRITE_DATA0__WrByte0__SHIFT 0x0
+#define SBRMI_WRITE_DATA0__WrByte1__SHIFT 0x8
+#define SBRMI_WRITE_DATA0__WrByte2__SHIFT 0x10
+#define SBRMI_WRITE_DATA0__WrByte3__SHIFT 0x18
+#define SBRMI_WRITE_DATA0__WrByte0_MASK 0x000000FFL
+#define SBRMI_WRITE_DATA0__WrByte1_MASK 0x0000FF00L
+#define SBRMI_WRITE_DATA0__WrByte2_MASK 0x00FF0000L
+#define SBRMI_WRITE_DATA0__WrByte3_MASK 0xFF000000L
+//SBRMI_WRITE_DATA1
+#define SBRMI_WRITE_DATA1__WrByte4__SHIFT 0x0
+#define SBRMI_WRITE_DATA1__WrByte5__SHIFT 0x8
+#define SBRMI_WRITE_DATA1__WrByte6__SHIFT 0x10
+#define SBRMI_WRITE_DATA1__WrByte7__SHIFT 0x18
+#define SBRMI_WRITE_DATA1__WrByte4_MASK 0x000000FFL
+#define SBRMI_WRITE_DATA1__WrByte5_MASK 0x0000FF00L
+#define SBRMI_WRITE_DATA1__WrByte6_MASK 0x00FF0000L
+#define SBRMI_WRITE_DATA1__WrByte7_MASK 0xFF000000L
+//SBRMI_WRITE_DATA2
+#define SBRMI_WRITE_DATA2__WrByte8__SHIFT 0x0
+#define SBRMI_WRITE_DATA2__WrByte9__SHIFT 0x8
+#define SBRMI_WRITE_DATA2__WrByte10__SHIFT 0x10
+#define SBRMI_WRITE_DATA2__WrByte11__SHIFT 0x18
+#define SBRMI_WRITE_DATA2__WrByte8_MASK 0x000000FFL
+#define SBRMI_WRITE_DATA2__WrByte9_MASK 0x0000FF00L
+#define SBRMI_WRITE_DATA2__WrByte10_MASK 0x00FF0000L
+#define SBRMI_WRITE_DATA2__WrByte11_MASK 0xFF000000L
+//SBRMI_READ_DATA0
+#define SBRMI_READ_DATA0__RdByte0__SHIFT 0x0
+#define SBRMI_READ_DATA0__RdByte1__SHIFT 0x8
+#define SBRMI_READ_DATA0__RdByte2__SHIFT 0x10
+#define SBRMI_READ_DATA0__RdByte3__SHIFT 0x18
+#define SBRMI_READ_DATA0__RdByte0_MASK 0x000000FFL
+#define SBRMI_READ_DATA0__RdByte1_MASK 0x0000FF00L
+#define SBRMI_READ_DATA0__RdByte2_MASK 0x00FF0000L
+#define SBRMI_READ_DATA0__RdByte3_MASK 0xFF000000L
+//SBRMI_READ_DATA1
+#define SBRMI_READ_DATA1__RdByte4__SHIFT 0x0
+#define SBRMI_READ_DATA1__RdByte5__SHIFT 0x8
+#define SBRMI_READ_DATA1__RdByte6__SHIFT 0x10
+#define SBRMI_READ_DATA1__RdByte7__SHIFT 0x18
+#define SBRMI_READ_DATA1__RdByte4_MASK 0x000000FFL
+#define SBRMI_READ_DATA1__RdByte5_MASK 0x0000FF00L
+#define SBRMI_READ_DATA1__RdByte6_MASK 0x00FF0000L
+#define SBRMI_READ_DATA1__RdByte7_MASK 0xFF000000L
+//SBRMI_CORE_EN_NUMBER
+#define SBRMI_CORE_EN_NUMBER__EnabledCoreNum__SHIFT 0x0
+#define SBRMI_CORE_EN_NUMBER__EnabledCoreNum_MASK 0x0000007FL
+//SBRMI_CORE_EN_STATUS0
+#define SBRMI_CORE_EN_STATUS0__CoreEnStat0__SHIFT 0x0
+#define SBRMI_CORE_EN_STATUS0__CoreEnStat0_MASK 0xFFFFFFFFL
+//SBRMI_CORE_EN_STATUS1
+#define SBRMI_CORE_EN_STATUS1__CoreEnStat1__SHIFT 0x0
+#define SBRMI_CORE_EN_STATUS1__CoreEnStat1_MASK 0xFFFFFFFFL
+//SBRMI_APIC_STATUS0
+#define SBRMI_APIC_STATUS0__APICStat0__SHIFT 0x0
+#define SBRMI_APIC_STATUS0__APICStat0_MASK 0xFFFFFFFFL
+//SBRMI_APIC_STATUS1
+#define SBRMI_APIC_STATUS1__APICStat1__SHIFT 0x0
+#define SBRMI_APIC_STATUS1__APICStat1_MASK 0xFFFFFFFFL
+//SBRMI_MCE_STATUS0
+#define SBRMI_MCE_STATUS0__MceStat0__SHIFT 0x0
+#define SBRMI_MCE_STATUS0__MceStat0_MASK 0xFFFFFFFFL
+//SBRMI_MCE_STATUS1
+#define SBRMI_MCE_STATUS1__MceStat1__SHIFT 0x0
+#define SBRMI_MCE_STATUS1__MceStat1_MASK 0xFFFFFFFFL
+//SMBUS_CNTL0
+#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE__SHIFT 0x0
+#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR__SHIFT 0x1
+#define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE__SHIFT 0x8
+#define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES__SHIFT 0x10
+#define SMBUS_CNTL0__THM_READY__SHIFT 0x14
+#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE_MASK 0x00000001L
+#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_MASK 0x000000FEL
+#define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE_MASK 0x0000FF00L
+#define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES_MASK 0x00070000L
+#define SMBUS_CNTL0__THM_READY_MASK 0x00100000L
+//SMBUS_CNTL1
+#define SMBUS_CNTL1__SMB_TIMEOUT_EN__SHIFT 0x0
+#define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN__SHIFT 0x1
+#define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN__SHIFT 0x9
+#define SMBUS_CNTL1__SMB_TIMEOUT_EN_MASK 0x00000001L
+#define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN_MASK 0x000001FEL
+#define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN_MASK 0x0001FE00L
+//SMBUS_BLKWR_CMD_CTRL0
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0__SHIFT 0x0
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1__SHIFT 0x8
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2__SHIFT 0x10
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3__SHIFT 0x18
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0_MASK 0x000000FFL
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1_MASK 0x0000FF00L
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2_MASK 0x00FF0000L
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3_MASK 0xFF000000L
+//SMBUS_BLKWR_CMD_CTRL1
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4__SHIFT 0x0
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5__SHIFT 0x8
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6__SHIFT 0x10
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7__SHIFT 0x18
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4_MASK 0x000000FFL
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5_MASK 0x0000FF00L
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6_MASK 0x00FF0000L
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7_MASK 0xFF000000L
+//SMBUS_BLKRD_CMD_CTRL0
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0__SHIFT 0x0
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1__SHIFT 0x8
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2__SHIFT 0x10
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3__SHIFT 0x18
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0_MASK 0x000000FFL
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1_MASK 0x0000FF00L
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2_MASK 0x00FF0000L
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3_MASK 0xFF000000L
+//SMBUS_BLKRD_CMD_CTRL1
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4__SHIFT 0x0
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5__SHIFT 0x8
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6__SHIFT 0x10
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7__SHIFT 0x18
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4_MASK 0x000000FFL
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5_MASK 0x0000FF00L
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6_MASK 0x00FF0000L
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7_MASK 0xFF000000L
+//SMBUS_TIMING_CNTL0
+#define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN__SHIFT 0x0
+#define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN__SHIFT 0x16
+#define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN_MASK 0x003FFFFFL
+#define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN_MASK 0x3FC00000L
+//SMBUS_TIMING_CNTL1
+#define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN__SHIFT 0x0
+#define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN__SHIFT 0x5
+#define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN__SHIFT 0xb
+#define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN__SHIFT 0x14
+#define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN_MASK 0x0000001FL
+#define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN_MASK 0x000007E0L
+#define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN_MASK 0x000FF800L
+#define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN_MASK 0x3FF00000L
+//SMBUS_TIMING_CNTL2
+#define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN__SHIFT 0x0
+#define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN__SHIFT 0xd
+#define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN_MASK 0x00001FFFL
+#define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN_MASK 0x07FFE000L
+//SMBUS_TRIGGER_CNTL
+#define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER__SHIFT 0x0
+#define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER__SHIFT 0x8
+#define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER_MASK 0x00000001L
+#define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER_MASK 0x00000100L
+//SMBUS_UDID_CNTL0
+#define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED__SHIFT 0x0
+#define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN__SHIFT 0x1f
+#define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED_MASK 0x7FFFFFFFL
+#define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN_MASK 0x80000000L
+//SMBUS_UDID_CNTL1
+#define SMBUS_UDID_CNTL1__SMB_UDID_31_0__SHIFT 0x0
+#define SMBUS_UDID_CNTL1__SMB_UDID_31_0_MASK 0xFFFFFFFFL
+//SMBUS_UDID_CNTL2
+#define SMBUS_UDID_CNTL2__PEC_SUPPORTED__SHIFT 0x0
+#define SMBUS_UDID_CNTL2__UDID_VERSION__SHIFT 0x1
+#define SMBUS_UDID_CNTL2__SMBUS_VERSION__SHIFT 0x4
+#define SMBUS_UDID_CNTL2__OEM__SHIFT 0x8
+#define SMBUS_UDID_CNTL2__ASF__SHIFT 0x9
+#define SMBUS_UDID_CNTL2__IPMI__SHIFT 0xa
+#define SMBUS_UDID_CNTL2__PEC_SUPPORTED_MASK 0x00000001L
+#define SMBUS_UDID_CNTL2__UDID_VERSION_MASK 0x0000000EL
+#define SMBUS_UDID_CNTL2__SMBUS_VERSION_MASK 0x000000F0L
+#define SMBUS_UDID_CNTL2__OEM_MASK 0x00000100L
+#define SMBUS_UDID_CNTL2__ASF_MASK 0x00000200L
+#define SMBUS_UDID_CNTL2__IPMI_MASK 0x00000400L
+//SMBUS_BACO_DUMMY
+#define SMBUS_BACO_DUMMY__BACO_DUMMY_DATA__SHIFT 0x0
+#define SMBUS_BACO_DUMMY__BACO_DUMMY_DATA_MASK 0xFFFFFFFFL
+//SMBUS_BACO_ADDR_RANGE0_LOW
+#define SMBUS_BACO_ADDR_RANGE0_LOW__BACO_ADDR_RANGE0_LOW__SHIFT 0x0
+#define SMBUS_BACO_ADDR_RANGE0_LOW__BACO_ADDR_RANGE0_LOW_MASK 0x000FFFFFL
+//SMBUS_BACO_ADDR_RANGE0_HIGH
+#define SMBUS_BACO_ADDR_RANGE0_HIGH__BACO_ADDR_RANGE0_HIGH__SHIFT 0x0
+#define SMBUS_BACO_ADDR_RANGE0_HIGH__BACO_ADDR_RANGE0_HIGH_MASK 0x000FFFFFL
+//SMBUS_BACO_ADDR_RANGE1_LOW
+#define SMBUS_BACO_ADDR_RANGE1_LOW__BACO_ADDR_RANGE1_LOW__SHIFT 0x0
+#define SMBUS_BACO_ADDR_RANGE1_LOW__BACO_ADDR_RANGE1_LOW_MASK 0x000FFFFFL
+//SMBUS_BACO_ADDR_RANGE1_HIGH
+#define SMBUS_BACO_ADDR_RANGE1_HIGH__BACO_ADDR_RANGE1_HIGH__SHIFT 0x0
+#define SMBUS_BACO_ADDR_RANGE1_HIGH__BACO_ADDR_RANGE1_HIGH_MASK 0x000FFFFFL
+//SMBUS_BACO_ADDR_RANGE2_LOW
+#define SMBUS_BACO_ADDR_RANGE2_LOW__BACO_ADDR_RANGE2_LOW__SHIFT 0x0
+#define SMBUS_BACO_ADDR_RANGE2_LOW__BACO_ADDR_RANGE2_LOW_MASK 0x000FFFFFL
+//SMBUS_BACO_ADDR_RANGE2_HIGH
+#define SMBUS_BACO_ADDR_RANGE2_HIGH__BACO_ADDR_RANGE2_HIGH__SHIFT 0x0
+#define SMBUS_BACO_ADDR_RANGE2_HIGH__BACO_ADDR_RANGE2_HIGH_MASK 0x000FFFFFL
+//SMBUS_BACO_ADDR_RANGE3_LOW
+#define SMBUS_BACO_ADDR_RANGE3_LOW__BACO_ADDR_RANGE3_LOW__SHIFT 0x0
+#define SMBUS_BACO_ADDR_RANGE3_LOW__BACO_ADDR_RANGE3_LOW_MASK 0x000FFFFFL
+//SMBUS_BACO_ADDR_RANGE3_HIGH
+#define SMBUS_BACO_ADDR_RANGE3_HIGH__BACO_ADDR_RANGE3_HIGH__SHIFT 0x0
+#define SMBUS_BACO_ADDR_RANGE3_HIGH__BACO_ADDR_RANGE3_HIGH_MASK 0x000FFFFFL
+//SMBUS_BACO_ADDR_RANGE4_LOW
+#define SMBUS_BACO_ADDR_RANGE4_LOW__BACO_ADDR_RANGE4_LOW__SHIFT 0x0
+#define SMBUS_BACO_ADDR_RANGE4_LOW__BACO_ADDR_RANGE4_LOW_MASK 0x000FFFFFL
+//SMBUS_BACO_ADDR_RANGE4_HIGH
+#define SMBUS_BACO_ADDR_RANGE4_HIGH__BACO_ADDR_RANGE4_HIGH__SHIFT 0x0
+#define SMBUS_BACO_ADDR_RANGE4_HIGH__BACO_ADDR_RANGE4_HIGH_MASK 0x000FFFFFL
+//THM_GPIO_MACO_EN_CTRL
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_TXIMPSEL__SHIFT 0x0
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PD__SHIFT 0x1
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PU__SHIFT 0x2
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_SCHMEN__SHIFT 0x3
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S0__SHIFT 0x4
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S1__SHIFT 0x5
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXEN__SHIFT 0x6
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL0__SHIFT 0x7
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL1__SHIFT 0x8
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_OVERRIDE__SHIFT 0x10
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE__SHIFT 0x11
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_OVERRIDE__SHIFT 0x12
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A__SHIFT 0x13
+#define THM_GPIO_MACO_EN_CTRL__Y__SHIFT 0x1f
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_TXIMPSEL_MASK 0x00000001L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PD_MASK 0x00000002L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PU_MASK 0x00000004L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_SCHMEN_MASK 0x00000008L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S0_MASK 0x00000010L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S1_MASK 0x00000020L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXEN_MASK 0x00000040L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL0_MASK 0x00000080L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL1_MASK 0x00000100L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_OVERRIDE_MASK 0x00010000L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_MASK 0x00020000L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_OVERRIDE_MASK 0x00040000L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_MASK 0x00080000L
+#define THM_GPIO_MACO_EN_CTRL__Y_MASK 0x80000000L
+//THM_BACO_TIMING2
+#define THM_BACO_TIMING2__BACO_AEB_ISO_EXIT_CNT__SHIFT 0x0
+#define THM_BACO_TIMING2__BACO_ANA_ISO_EXIT_CNT__SHIFT 0x8
+#define THM_BACO_TIMING2__BACO_EXIT_CNT__SHIFT 0x10
+#define THM_BACO_TIMING2__BACO_AEB_ISO_EXIT_CNT_MASK 0x000000FFL
+#define THM_BACO_TIMING2__BACO_ANA_ISO_EXIT_CNT_MASK 0x0000FF00L
+#define THM_BACO_TIMING2__BACO_EXIT_CNT_MASK 0x00FF0000L
+//THM_BACO_TIMING
+#define THM_BACO_TIMING__BACO_RESET_DELAY__SHIFT 0x0
+#define THM_BACO_TIMING__BACO_RESET_DELAY_MASK 0x0000FFFFL
+//THM_TMON0_REMOTE_START
+#define THM_TMON0_REMOTE_START__DATA__SHIFT 0x0
+#define THM_TMON0_REMOTE_START__DATA_MASK 0xFFFFFFFFL
+//THM_TMON0_REMOTE_END
+#define THM_TMON0_REMOTE_END__DATA__SHIFT 0x0
+#define THM_TMON0_REMOTE_END__DATA_MASK 0xFFFFFFFFL
+//THM_TMON1_REMOTE_START
+#define THM_TMON1_REMOTE_START__DATA__SHIFT 0x0
+#define THM_TMON1_REMOTE_START__DATA_MASK 0xFFFFFFFFL
+//THM_TMON1_REMOTE_END
+#define THM_TMON1_REMOTE_END__DATA__SHIFT 0x0
+#define THM_TMON1_REMOTE_END__DATA_MASK 0xFFFFFFFFL
+//THM_TMON2_REMOTE_START
+#define THM_TMON2_REMOTE_START__DATA__SHIFT 0x0
+#define THM_TMON2_REMOTE_START__DATA_MASK 0xFFFFFFFFL
+//THM_TMON2_REMOTE_END
+#define THM_TMON2_REMOTE_END__DATA__SHIFT 0x0
+#define THM_TMON2_REMOTE_END__DATA_MASK 0xFFFFFFFFL
+//THM_TMON3_REMOTE_START
+#define THM_TMON3_REMOTE_START__DATA__SHIFT 0x0
+#define THM_TMON3_REMOTE_START__DATA_MASK 0xFFFFFFFFL
+//THM_TMON3_REMOTE_END
+#define THM_TMON3_REMOTE_END__DATA__SHIFT 0x0
+#define THM_TMON3_REMOTE_END__DATA_MASK 0xFFFFFFFFL
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h
new file mode 100644
index 000000000000..48963caac534
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _uvd_7_0_DEFAULT_HEADER
+#define _uvd_7_0_DEFAULT_HEADER
+
+
+// addressBlock: uvd0_uvd_pg_dec
+#define mmUVD_POWER_STATUS_DEFAULT 0x00000000
+#define mmUVD_DPG_RBC_RB_CNTL_DEFAULT 0x01000101
+#define mmUVD_DPG_RBC_RB_BASE_LOW_DEFAULT 0x00000000
+#define mmUVD_DPG_RBC_RB_BASE_HIGH_DEFAULT 0x00000000
+#define mmUVD_DPG_RBC_RB_WPTR_CNTL_DEFAULT 0x00000000
+#define mmUVD_DPG_RBC_RB_RPTR_DEFAULT 0x00000000
+#define mmUVD_DPG_RBC_RB_WPTR_DEFAULT 0x00000000
+#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_DEFAULT 0x00000000
+#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_DEFAULT 0x00000000
+#define mmUVD_DPG_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000
+
+
+// addressBlock: uvd0_uvdnpdec
+#define mmUVD_JPEG_ADDR_CONFIG_DEFAULT 0x22010010
+#define mmUVD_GPCOM_VCPU_CMD_DEFAULT 0x00000000
+#define mmUVD_GPCOM_VCPU_DATA0_DEFAULT 0x00000000
+#define mmUVD_GPCOM_VCPU_DATA1_DEFAULT 0x00000000
+#define mmUVD_UDEC_ADDR_CONFIG_DEFAULT 0x22010010
+#define mmUVD_UDEC_DB_ADDR_CONFIG_DEFAULT 0x22010010
+#define mmUVD_UDEC_DBW_ADDR_CONFIG_DEFAULT 0x22010010
+#define mmUVD_SUVD_CGC_GATE_DEFAULT 0x00000000
+#define mmUVD_SUVD_CGC_CTRL_DEFAULT 0x00000000
+#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_DEFAULT 0x00000000
+#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_DEFAULT 0x00000000
+#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_DEFAULT 0x00000000
+#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_DEFAULT 0x00000000
+#define mmUVD_POWER_STATUS_U_DEFAULT 0x00000000
+#define mmUVD_NO_OP_DEFAULT 0x00000000
+#define mmUVD_GP_SCRATCH8_DEFAULT 0x00000000
+#define mmUVD_RB_BASE_LO2_DEFAULT 0x00000000
+#define mmUVD_RB_BASE_HI2_DEFAULT 0x00000000
+#define mmUVD_RB_SIZE2_DEFAULT 0x00000000
+#define mmUVD_RB_RPTR2_DEFAULT 0x00000000
+#define mmUVD_RB_WPTR2_DEFAULT 0x00000000
+#define mmUVD_RB_BASE_LO_DEFAULT 0x00000000
+#define mmUVD_RB_BASE_HI_DEFAULT 0x00000000
+#define mmUVD_RB_SIZE_DEFAULT 0x00000000
+#define mmUVD_RB_RPTR_DEFAULT 0x00000000
+#define mmUVD_RB_WPTR_DEFAULT 0x00000000
+#define mmUVD_JRBC_RB_RPTR_DEFAULT 0x00000000
+#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_DEFAULT 0x00000000
+#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_DEFAULT 0x00000000
+#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_DEFAULT 0x00000000
+#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_DEFAULT 0x00000000
+#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_DEFAULT 0x00000000
+#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_DEFAULT 0x00000000
+
+
+// addressBlock: uvd0_uvddec
+#define mmUVD_SEMA_CNTL_DEFAULT 0x00000003
+#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_DEFAULT 0x00000000
+#define mmUVD_JRBC_RB_WPTR_DEFAULT 0x00000000
+#define mmUVD_RB_RPTR3_DEFAULT 0x00000000
+#define mmUVD_RB_WPTR3_DEFAULT 0x00000000
+#define mmUVD_RB_BASE_LO3_DEFAULT 0x00000000
+#define mmUVD_RB_BASE_HI3_DEFAULT 0x00000000
+#define mmUVD_RB_SIZE3_DEFAULT 0x00000000
+#define mmJPEG_CGC_GATE_DEFAULT 0x00300000
+#define mmUVD_CTX_INDEX_DEFAULT 0x00000000
+#define mmUVD_CTX_DATA_DEFAULT 0x00000000
+#define mmUVD_CGC_GATE_DEFAULT 0x000fffff
+#define mmUVD_CGC_CTRL_DEFAULT 0x1fff018d
+#define mmUVD_GP_SCRATCH4_DEFAULT 0x00000000
+#define mmUVD_LMI_CTRL2_DEFAULT 0x003e0000
+#define mmUVD_MASTINT_EN_DEFAULT 0x00000000
+#define mmJPEG_CGC_CTRL_DEFAULT 0x0000018d
+#define mmUVD_LMI_CTRL_DEFAULT 0x00104340
+#define mmUVD_LMI_VM_CTRL_DEFAULT 0x00000000
+#define mmUVD_LMI_SWAP_CNTL_DEFAULT 0x00000000
+#define mmUVD_MP_SWAP_CNTL_DEFAULT 0x00000000
+#define mmUVD_MPC_SET_MUXA0_DEFAULT 0x00002040
+#define mmUVD_MPC_SET_MUXA1_DEFAULT 0x00000000
+#define mmUVD_MPC_SET_MUXB0_DEFAULT 0x00002040
+#define mmUVD_MPC_SET_MUXB1_DEFAULT 0x00000000
+#define mmUVD_MPC_SET_MUX_DEFAULT 0x00000088
+#define mmUVD_MPC_SET_ALU_DEFAULT 0x00000000
+#define mmUVD_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000
+#define mmUVD_VCPU_CACHE_SIZE0_DEFAULT 0x00000000
+#define mmUVD_VCPU_CACHE_OFFSET1_DEFAULT 0x00000000
+#define mmUVD_VCPU_CACHE_SIZE1_DEFAULT 0x00000000
+#define mmUVD_VCPU_CACHE_OFFSET2_DEFAULT 0x00000000
+#define mmUVD_VCPU_CACHE_SIZE2_DEFAULT 0x00000000
+#define mmUVD_VCPU_CNTL_DEFAULT 0x0ff20000
+#define mmUVD_SOFT_RESET_DEFAULT 0x00000008
+#define mmUVD_LMI_RBC_IB_VMID_DEFAULT 0x00000000
+#define mmUVD_RBC_IB_SIZE_DEFAULT 0x00000000
+#define mmUVD_LMI_RBC_RB_VMID_DEFAULT 0x00000000
+#define mmUVD_RBC_RB_RPTR_DEFAULT 0x00000000
+#define mmUVD_RBC_RB_WPTR_DEFAULT 0x00000000
+#define mmUVD_RBC_RB_WPTR_CNTL_DEFAULT 0x00000000
+#define mmUVD_RBC_RB_CNTL_DEFAULT 0x01000101
+#define mmUVD_RBC_RB_RPTR_ADDR_DEFAULT 0x00000000
+#define mmUVD_STATUS_DEFAULT 0x00000000
+#define mmUVD_SEMA_TIMEOUT_STATUS_DEFAULT 0x00000000
+#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_DEFAULT 0x02000000
+#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_DEFAULT 0x02000000
+#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_DEFAULT 0x02000000
+#define mmUVD_CONTEXT_ID_DEFAULT 0x00000000
+#define mmUVD_CONTEXT_ID2_DEFAULT 0x00000000
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_offset.h
new file mode 100644
index 000000000000..07aceffb108a
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_offset.h
@@ -0,0 +1,222 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _uvd_7_0_OFFSET_HEADER
+#define _uvd_7_0_OFFSET_HEADER
+
+
+
+// addressBlock: uvd0_uvd_pg_dec
+// base address: 0x1fb00
+#define mmUVD_POWER_STATUS 0x00c4
+#define mmUVD_POWER_STATUS_BASE_IDX 1
+#define mmUVD_DPG_RBC_RB_CNTL 0x00cb
+#define mmUVD_DPG_RBC_RB_CNTL_BASE_IDX 1
+#define mmUVD_DPG_RBC_RB_BASE_LOW 0x00cc
+#define mmUVD_DPG_RBC_RB_BASE_LOW_BASE_IDX 1
+#define mmUVD_DPG_RBC_RB_BASE_HIGH 0x00cd
+#define mmUVD_DPG_RBC_RB_BASE_HIGH_BASE_IDX 1
+#define mmUVD_DPG_RBC_RB_WPTR_CNTL 0x00ce
+#define mmUVD_DPG_RBC_RB_WPTR_CNTL_BASE_IDX 1
+#define mmUVD_DPG_RBC_RB_RPTR 0x00cf
+#define mmUVD_DPG_RBC_RB_RPTR_BASE_IDX 1
+#define mmUVD_DPG_RBC_RB_WPTR 0x00d0
+#define mmUVD_DPG_RBC_RB_WPTR_BASE_IDX 1
+#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x00e5
+#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x00e6
+#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_DPG_VCPU_CACHE_OFFSET0 0x00e7
+#define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1
+
+
+// addressBlock: uvd0_uvdnpdec
+// base address: 0x20000
+#define mmUVD_JPEG_ADDR_CONFIG 0x021f
+#define mmUVD_JPEG_ADDR_CONFIG_BASE_IDX 1
+#define mmUVD_GPCOM_VCPU_CMD 0x03c3
+#define mmUVD_GPCOM_VCPU_CMD_BASE_IDX 1
+#define mmUVD_GPCOM_VCPU_DATA0 0x03c4
+#define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX 1
+#define mmUVD_GPCOM_VCPU_DATA1 0x03c5
+#define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX 1
+#define mmUVD_UDEC_ADDR_CONFIG 0x03d3
+#define mmUVD_UDEC_ADDR_CONFIG_BASE_IDX 1
+#define mmUVD_UDEC_DB_ADDR_CONFIG 0x03d4
+#define mmUVD_UDEC_DB_ADDR_CONFIG_BASE_IDX 1
+#define mmUVD_UDEC_DBW_ADDR_CONFIG 0x03d5
+#define mmUVD_UDEC_DBW_ADDR_CONFIG_BASE_IDX 1
+#define mmUVD_SUVD_CGC_GATE 0x03e4
+#define mmUVD_SUVD_CGC_GATE_BASE_IDX 1
+#define mmUVD_SUVD_CGC_CTRL 0x03e6
+#define mmUVD_SUVD_CGC_CTRL_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x03ec
+#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x03ed
+#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x03f0
+#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x03f1
+#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_POWER_STATUS_U 0x03fd
+#define mmUVD_POWER_STATUS_U_BASE_IDX 1
+#define mmUVD_NO_OP 0x03ff
+#define mmUVD_NO_OP_BASE_IDX 1
+#define mmUVD_GP_SCRATCH8 0x040a
+#define mmUVD_GP_SCRATCH8_BASE_IDX 1
+#define mmUVD_RB_BASE_LO2 0x0421
+#define mmUVD_RB_BASE_LO2_BASE_IDX 1
+#define mmUVD_RB_BASE_HI2 0x0422
+#define mmUVD_RB_BASE_HI2_BASE_IDX 1
+#define mmUVD_RB_SIZE2 0x0423
+#define mmUVD_RB_SIZE2_BASE_IDX 1
+#define mmUVD_RB_RPTR2 0x0424
+#define mmUVD_RB_RPTR2_BASE_IDX 1
+#define mmUVD_RB_WPTR2 0x0425
+#define mmUVD_RB_WPTR2_BASE_IDX 1
+#define mmUVD_RB_BASE_LO 0x0426
+#define mmUVD_RB_BASE_LO_BASE_IDX 1
+#define mmUVD_RB_BASE_HI 0x0427
+#define mmUVD_RB_BASE_HI_BASE_IDX 1
+#define mmUVD_RB_SIZE 0x0428
+#define mmUVD_RB_SIZE_BASE_IDX 1
+#define mmUVD_RB_RPTR 0x0429
+#define mmUVD_RB_RPTR_BASE_IDX 1
+#define mmUVD_RB_WPTR 0x042a
+#define mmUVD_RB_WPTR_BASE_IDX 1
+#define mmUVD_JRBC_RB_RPTR 0x0457
+#define mmUVD_JRBC_RB_RPTR_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x045e
+#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x045f
+#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x0466
+#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x0467
+#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x0468
+#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x0469
+#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX 1
+
+
+// addressBlock: uvd0_uvddec
+// base address: 0x20c00
+#define mmUVD_SEMA_CNTL 0x0500
+#define mmUVD_SEMA_CNTL_BASE_IDX 1
+#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0503
+#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_JRBC_RB_WPTR 0x0509
+#define mmUVD_JRBC_RB_WPTR_BASE_IDX 1
+#define mmUVD_RB_RPTR3 0x051b
+#define mmUVD_RB_RPTR3_BASE_IDX 1
+#define mmUVD_RB_WPTR3 0x051c
+#define mmUVD_RB_WPTR3_BASE_IDX 1
+#define mmUVD_RB_BASE_LO3 0x051d
+#define mmUVD_RB_BASE_LO3_BASE_IDX 1
+#define mmUVD_RB_BASE_HI3 0x051e
+#define mmUVD_RB_BASE_HI3_BASE_IDX 1
+#define mmUVD_RB_SIZE3 0x051f
+#define mmUVD_RB_SIZE3_BASE_IDX 1
+#define mmJPEG_CGC_GATE 0x0526
+#define mmJPEG_CGC_GATE_BASE_IDX 1
+#define mmUVD_CTX_INDEX 0x0528
+#define mmUVD_CTX_INDEX_BASE_IDX 1
+#define mmUVD_CTX_DATA 0x0529
+#define mmUVD_CTX_DATA_BASE_IDX 1
+#define mmUVD_CGC_GATE 0x052a
+#define mmUVD_CGC_GATE_BASE_IDX 1
+#define mmUVD_CGC_CTRL 0x052c
+#define mmUVD_CGC_CTRL_BASE_IDX 1
+#define mmUVD_GP_SCRATCH4 0x0538
+#define mmUVD_GP_SCRATCH4_BASE_IDX 1
+#define mmUVD_LMI_CTRL2 0x053d
+#define mmUVD_LMI_CTRL2_BASE_IDX 1
+#define mmUVD_MASTINT_EN 0x0540
+#define mmUVD_MASTINT_EN_BASE_IDX 1
+#define mmJPEG_CGC_CTRL 0x0565
+#define mmJPEG_CGC_CTRL_BASE_IDX 1
+#define mmUVD_LMI_CTRL 0x0566
+#define mmUVD_LMI_CTRL_BASE_IDX 1
+#define mmUVD_LMI_VM_CTRL 0x0568
+#define mmUVD_LMI_VM_CTRL_BASE_IDX 1
+#define mmUVD_LMI_SWAP_CNTL 0x056d
+#define mmUVD_LMI_SWAP_CNTL_BASE_IDX 1
+#define mmUVD_MP_SWAP_CNTL 0x056f
+#define mmUVD_MP_SWAP_CNTL_BASE_IDX 1
+#define mmUVD_MPC_SET_MUXA0 0x0579
+#define mmUVD_MPC_SET_MUXA0_BASE_IDX 1
+#define mmUVD_MPC_SET_MUXA1 0x057a
+#define mmUVD_MPC_SET_MUXA1_BASE_IDX 1
+#define mmUVD_MPC_SET_MUXB0 0x057b
+#define mmUVD_MPC_SET_MUXB0_BASE_IDX 1
+#define mmUVD_MPC_SET_MUXB1 0x057c
+#define mmUVD_MPC_SET_MUXB1_BASE_IDX 1
+#define mmUVD_MPC_SET_MUX 0x057d
+#define mmUVD_MPC_SET_MUX_BASE_IDX 1
+#define mmUVD_MPC_SET_ALU 0x057e
+#define mmUVD_MPC_SET_ALU_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_OFFSET0 0x0582
+#define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_SIZE0 0x0583
+#define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_OFFSET1 0x0584
+#define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_SIZE1 0x0585
+#define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_OFFSET2 0x0586
+#define mmUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_SIZE2 0x0587
+#define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX 1
+#define mmUVD_VCPU_CNTL 0x0598
+#define mmUVD_VCPU_CNTL_BASE_IDX 1
+#define mmUVD_SOFT_RESET 0x05a0
+#define mmUVD_SOFT_RESET_BASE_IDX 1
+#define mmUVD_LMI_RBC_IB_VMID 0x05a1
+#define mmUVD_LMI_RBC_IB_VMID_BASE_IDX 1
+#define mmUVD_RBC_IB_SIZE 0x05a2
+#define mmUVD_RBC_IB_SIZE_BASE_IDX 1
+#define mmUVD_RBC_RB_RPTR 0x05a4
+#define mmUVD_RBC_RB_RPTR_BASE_IDX 1
+#define mmUVD_RBC_RB_WPTR 0x05a5
+#define mmUVD_RBC_RB_WPTR_BASE_IDX 1
+#define mmUVD_RBC_RB_WPTR_CNTL 0x05a6
+#define mmUVD_RBC_RB_WPTR_CNTL_BASE_IDX 1
+#define mmUVD_RBC_RB_CNTL 0x05a9
+#define mmUVD_RBC_RB_CNTL_BASE_IDX 1
+#define mmUVD_RBC_RB_RPTR_ADDR 0x05aa
+#define mmUVD_RBC_RB_RPTR_ADDR_BASE_IDX 1
+#define mmUVD_STATUS 0x05af
+#define mmUVD_STATUS_BASE_IDX 1
+#define mmUVD_SEMA_TIMEOUT_STATUS 0x05b0
+#define mmUVD_SEMA_TIMEOUT_STATUS_BASE_IDX 1
+#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x05b1
+#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1
+#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x05b2
+#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX 1
+#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x05b3
+#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1
+#define mmUVD_CONTEXT_ID 0x05bd
+#define mmUVD_CONTEXT_ID_BASE_IDX 1
+#define mmUVD_CONTEXT_ID2 0x05bf
+#define mmUVD_CONTEXT_ID2_BASE_IDX 1
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h
new file mode 100644
index 000000000000..b427f73bd536
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h
@@ -0,0 +1,811 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _uvd_7_0_SH_MASK_HEADER
+#define _uvd_7_0_SH_MASK_HEADER
+
+
+// addressBlock: uvd0_uvd_pg_dec
+//UVD_POWER_STATUS
+#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0
+#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2
+#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT__SHIFT 0x3
+#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT__SHIFT 0x4
+#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT__SHIFT 0x5
+#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE__SHIFT 0x6
+#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8
+#define UVD_POWER_STATUS__PAUSE_DPG_REQ__SHIFT 0x9
+#define UVD_POWER_STATUS__PAUSE_DPG_ACK__SHIFT 0xa
+#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L
+#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L
+#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT_MASK 0x00000008L
+#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT_MASK 0x00000010L
+#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT_MASK 0x00000020L
+#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE_MASK 0x000000C0L
+#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L
+#define UVD_POWER_STATUS__PAUSE_DPG_REQ_MASK 0x00000200L
+#define UVD_POWER_STATUS__PAUSE_DPG_ACK_MASK 0x00000400L
+//UVD_DPG_RBC_RB_CNTL
+#define UVD_DPG_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0
+#define UVD_DPG_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8
+#define UVD_DPG_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10
+#define UVD_DPG_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14
+#define UVD_DPG_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18
+#define UVD_DPG_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c
+#define UVD_DPG_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL
+#define UVD_DPG_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L
+#define UVD_DPG_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L
+#define UVD_DPG_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L
+#define UVD_DPG_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L
+#define UVD_DPG_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L
+//UVD_DPG_RBC_RB_BASE_LOW
+#define UVD_DPG_RBC_RB_BASE_LOW__RB_BASE_LOW__SHIFT 0x0
+#define UVD_DPG_RBC_RB_BASE_LOW__RB_BASE_LOW_MASK 0xFFFFFFFFL
+//UVD_DPG_RBC_RB_BASE_HIGH
+#define UVD_DPG_RBC_RB_BASE_HIGH__RB_BASE_HIGH__SHIFT 0x0
+#define UVD_DPG_RBC_RB_BASE_HIGH__RB_BASE_HIGH_MASK 0xFFFFFFFFL
+//UVD_DPG_RBC_RB_WPTR_CNTL
+#define UVD_DPG_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0
+#define UVD_DPG_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL
+//UVD_DPG_RBC_RB_RPTR
+#define UVD_DPG_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define UVD_DPG_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
+//UVD_DPG_RBC_RB_WPTR
+#define UVD_DPG_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define UVD_DPG_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
+//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW
+#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH
+#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_DPG_VCPU_CACHE_OFFSET0
+#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
+#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL
+
+
+// addressBlock: uvd0_uvdnpdec
+//UVD_JPEG_ADDR_CONFIG
+#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define UVD_JPEG_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
+#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_JPEG_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15
+#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_JPEG_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a
+#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_JPEG_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f
+#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define UVD_JPEG_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
+#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define UVD_JPEG_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
+#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L
+#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
+#define UVD_JPEG_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L
+#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
+#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
+#define UVD_JPEG_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L
+//UVD_GPCOM_VCPU_CMD
+#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0
+#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1
+#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f
+#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L
+#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL
+#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L
+//UVD_GPCOM_VCPU_DATA0
+#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0
+#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL
+//UVD_GPCOM_VCPU_DATA1
+#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0
+#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL
+//UVD_UDEC_ADDR_CONFIG
+#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define UVD_UDEC_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
+#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_UDEC_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15
+#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_UDEC_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a
+#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_UDEC_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f
+#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define UVD_UDEC_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
+#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define UVD_UDEC_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
+#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L
+#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
+#define UVD_UDEC_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L
+#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
+#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
+#define UVD_UDEC_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L
+//UVD_UDEC_DB_ADDR_CONFIG
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define UVD_UDEC_DB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
+#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15
+#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a
+#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_UDEC_DB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define UVD_UDEC_DB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
+#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L
+#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L
+#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
+#define UVD_UDEC_DB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L
+//UVD_UDEC_DBW_ADDR_CONFIG
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define UVD_UDEC_DBW_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
+#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15
+#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a
+#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_UDEC_DBW_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define UVD_UDEC_DBW_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
+#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L
+#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L
+#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
+#define UVD_UDEC_DBW_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L
+//UVD_SUVD_CGC_GATE
+#define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0
+#define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1
+#define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2
+#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3
+#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4
+#define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
+#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6
+#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7
+#define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8
+#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9
+#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
+#define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb
+#define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc
+#define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd
+#define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
+#define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf
+#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10
+#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11
+#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12
+#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L
+#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L
+#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L
+#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L
+#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L
+#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L
+#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L
+#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L
+#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L
+#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L
+#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L
+#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L
+#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L
+#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L
+#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L
+#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L
+#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L
+#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L
+#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L
+//UVD_SUVD_CGC_CTRL
+#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0
+#define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1
+#define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2
+#define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3
+#define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4
+#define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
+#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6
+#define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7
+#define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8
+#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L
+#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L
+#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L
+#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L
+#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L
+#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L
+#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L
+#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L
+#define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L
+//UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_POWER_STATUS_U
+#define UVD_POWER_STATUS_U__UVD_POWER_STATUS__SHIFT 0x0
+#define UVD_POWER_STATUS_U__UVD_POWER_STATUS_MASK 0x00000003L
+//UVD_NO_OP
+#define UVD_NO_OP__NO_OP__SHIFT 0x0
+#define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH8
+#define UVD_GP_SCRATCH8__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL
+//UVD_RB_BASE_LO2
+#define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6
+#define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L
+//UVD_RB_BASE_HI2
+#define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0
+#define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL
+//UVD_RB_SIZE2
+#define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4
+#define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L
+//UVD_RB_RPTR2
+#define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4
+#define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L
+//UVD_RB_WPTR2
+#define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4
+#define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L
+//UVD_RB_BASE_LO
+#define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6
+#define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L
+//UVD_RB_BASE_HI
+#define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL
+//UVD_RB_SIZE
+#define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4
+#define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L
+//UVD_RB_RPTR
+#define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
+//UVD_RB_WPTR
+#define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
+//UVD_JRBC_RB_RPTR
+#define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
+//UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_RBC_IB_64BIT_BAR_HIGH
+#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_RBC_IB_64BIT_BAR_LOW
+#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_RBC_RB_64BIT_BAR_HIGH
+#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_RBC_RB_64BIT_BAR_LOW
+#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+
+
+// addressBlock: uvd0_uvddec
+//UVD_SEMA_CNTL
+#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0
+#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1
+#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L
+#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L
+//UVD_LMI_JRBC_RB_64BIT_BAR_LOW
+#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_JRBC_RB_WPTR
+#define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
+//UVD_RB_RPTR3
+#define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4
+#define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L
+//UVD_RB_WPTR3
+#define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4
+#define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L
+//UVD_RB_BASE_LO3
+#define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6
+#define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L
+//UVD_RB_BASE_HI3
+#define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0
+#define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL
+//UVD_RB_SIZE3
+#define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4
+#define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L
+//JPEG_CGC_GATE
+#define JPEG_CGC_GATE__JPEG__SHIFT 0x14
+#define JPEG_CGC_GATE__JPEG2__SHIFT 0x15
+#define JPEG_CGC_GATE__JPEG_MASK 0x00100000L
+#define JPEG_CGC_GATE__JPEG2_MASK 0x00200000L
+//UVD_CTX_INDEX
+#define UVD_CTX_INDEX__INDEX__SHIFT 0x0
+#define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL
+//UVD_CTX_DATA
+#define UVD_CTX_DATA__DATA__SHIFT 0x0
+#define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL
+//UVD_CGC_GATE
+#define UVD_CGC_GATE__SYS__SHIFT 0x0
+#define UVD_CGC_GATE__UDEC__SHIFT 0x1
+#define UVD_CGC_GATE__MPEG2__SHIFT 0x2
+#define UVD_CGC_GATE__REGS__SHIFT 0x3
+#define UVD_CGC_GATE__RBC__SHIFT 0x4
+#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5
+#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6
+#define UVD_CGC_GATE__IDCT__SHIFT 0x7
+#define UVD_CGC_GATE__MPRD__SHIFT 0x8
+#define UVD_CGC_GATE__MPC__SHIFT 0x9
+#define UVD_CGC_GATE__LBSI__SHIFT 0xa
+#define UVD_CGC_GATE__LRBBM__SHIFT 0xb
+#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc
+#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd
+#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe
+#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf
+#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10
+#define UVD_CGC_GATE__WCB__SHIFT 0x11
+#define UVD_CGC_GATE__VCPU__SHIFT 0x12
+#define UVD_CGC_GATE__SCPU__SHIFT 0x13
+#define UVD_CGC_GATE__SYS_MASK 0x00000001L
+#define UVD_CGC_GATE__UDEC_MASK 0x00000002L
+#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L
+#define UVD_CGC_GATE__REGS_MASK 0x00000008L
+#define UVD_CGC_GATE__RBC_MASK 0x00000010L
+#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L
+#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L
+#define UVD_CGC_GATE__IDCT_MASK 0x00000080L
+#define UVD_CGC_GATE__MPRD_MASK 0x00000100L
+#define UVD_CGC_GATE__MPC_MASK 0x00000200L
+#define UVD_CGC_GATE__LBSI_MASK 0x00000400L
+#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L
+#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L
+#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L
+#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L
+#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L
+#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L
+#define UVD_CGC_GATE__WCB_MASK 0x00020000L
+#define UVD_CGC_GATE__VCPU_MASK 0x00040000L
+#define UVD_CGC_GATE__SCPU_MASK 0x00080000L
+//UVD_CGC_CTRL
+#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
+#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2
+#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6
+#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb
+#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc
+#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
+#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe
+#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf
+#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
+#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11
+#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12
+#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13
+#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14
+#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15
+#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16
+#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17
+#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18
+#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19
+#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a
+#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b
+#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c
+#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d
+#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e
+#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L
+#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL
+#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L
+#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L
+#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L
+#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L
+#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L
+#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L
+#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L
+#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L
+#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L
+#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L
+#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L
+#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L
+#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L
+#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L
+#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L
+#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L
+#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L
+#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L
+#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L
+#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L
+#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000L
+//UVD_GP_SCRATCH4
+#define UVD_GP_SCRATCH4__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL
+//UVD_LMI_CTRL2
+#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0
+#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1
+#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2
+#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3
+#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7
+#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
+#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9
+#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb
+#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L
+#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L
+#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L
+#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L
+#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L
+#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L
+#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L
+#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L
+//UVD_MASTINT_EN
+#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0
+#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1
+#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2
+#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4
+#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L
+#define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L
+#define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L
+#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L
+//JPEG_CGC_CTRL
+#define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
+#define JPEG_CGC_CTRL__JPEG2_MODE__SHIFT 0x1
+#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2
+#define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6
+#define JPEG_CGC_CTRL__JPEG_MODE__SHIFT 0x1f
+#define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L
+#define JPEG_CGC_CTRL__JPEG2_MODE_MASK 0x00000002L
+#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL
+#define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L
+#define JPEG_CGC_CTRL__JPEG_MODE_MASK 0x80000000L
+//UVD_LMI_CTRL
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8
+#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9
+#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb
+#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc
+#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd
+#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe
+#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf
+#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15
+#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16
+#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17
+#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18
+#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19
+#define UVD_LMI_CTRL__RFU__SHIFT 0x1b
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L
+#define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L
+#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L
+#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L
+#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L
+#define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L
+#define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L
+#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L
+#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L
+#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L
+#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L
+#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L
+#define UVD_LMI_CTRL__RFU_MASK 0xF8000000L
+//UVD_LMI_SWAP_CNTL
+#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
+#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
+#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4
+#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6
+#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8
+#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa
+#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc
+#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe
+#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10
+#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12
+#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16
+#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18
+#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a
+#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c
+#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e
+#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L
+#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL
+#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L
+#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000C0L
+#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L
+#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000C00L
+#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L
+#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000C000L
+#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L
+#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000C0000L
+#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0x00C00000L
+#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L
+#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L
+#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L
+#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L
+//UVD_MP_SWAP_CNTL
+#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0
+#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2
+#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4
+#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6
+#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8
+#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa
+#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc
+#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe
+#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10
+#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12
+#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14
+#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16
+#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18
+#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a
+#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c
+#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e
+#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L
+#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000CL
+#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L
+#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000C0L
+#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L
+#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000C00L
+#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L
+#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000C000L
+#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L
+#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000C0000L
+#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L
+#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00C00000L
+#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L
+#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0C000000L
+#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L
+#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xC0000000L
+//UVD_MPC_SET_MUXA0
+#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0
+#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6
+#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc
+#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12
+#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18
+#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL
+#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L
+#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L
+#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L
+#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L
+//UVD_MPC_SET_MUXA1
+#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0
+#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6
+#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc
+#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL
+#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L
+#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L
+//UVD_MPC_SET_MUXB0
+#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0
+#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
+#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc
+#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12
+#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18
+#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL
+#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L
+#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L
+#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L
+#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L
+//UVD_MPC_SET_MUXB1
+#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0
+#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6
+#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc
+#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL
+#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L
+#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L
+//UVD_MPC_SET_MUX
+#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0
+#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3
+#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6
+#define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L
+#define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L
+#define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L
+//UVD_MPC_SET_ALU
+#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0
+#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4
+#define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L
+#define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L
+//UVD_VCPU_CACHE_OFFSET0
+#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL
+//UVD_VCPU_CACHE_SIZE0
+#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_OFFSET1
+#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x01FFFFFFL
+//UVD_VCPU_CACHE_SIZE1
+#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_OFFSET2
+#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x01FFFFFFL
+//UVD_VCPU_CACHE_SIZE2
+#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL
+//UVD_VCPU_CNTL
+#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9
+#define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L
+//UVD_SOFT_RESET
+#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0
+#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1
+#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2
+#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3
+#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4
+#define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5
+#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6
+#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7
+#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8
+#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
+#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd
+#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe
+#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf
+#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10
+#define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11
+#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12
+#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13
+#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14
+#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15
+#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16
+#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a
+#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b
+#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c
+#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d
+#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e
+#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f
+#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L
+#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L
+#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L
+#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L
+#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L
+#define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x00000020L
+#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L
+#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L
+#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L
+#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L
+#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L
+#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L
+#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L
+#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L
+#define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L
+#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L
+#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L
+#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L
+#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L
+#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L
+#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L
+#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L
+#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L
+#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L
+#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L
+#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L
+//UVD_LMI_RBC_IB_VMID
+#define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0
+#define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL
+//UVD_RBC_IB_SIZE
+#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4
+#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L
+//UVD_RBC_RB_RPTR
+#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
+//UVD_RBC_RB_WPTR
+#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
+//UVD_RBC_RB_WPTR_CNTL
+#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0
+#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL
+//UVD_RBC_RB_CNTL
+#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0
+#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8
+#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10
+#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14
+#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18
+#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c
+#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL
+#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L
+#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L
+#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L
+#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L
+#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L
+//UVD_RBC_RB_RPTR_ADDR
+#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0
+#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL
+//UVD_STATUS
+#define UVD_STATUS__RBC_BUSY__SHIFT 0x0
+#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1
+#define UVD_STATUS__AVP_BUSY__SHIFT 0x8
+#define UVD_STATUS__IDCT_BUSY__SHIFT 0x9
+#define UVD_STATUS__IDCT_CTL_ACK__SHIFT 0xb
+#define UVD_STATUS__UVD_CTL_ACK__SHIFT 0xc
+#define UVD_STATUS__AVP_BLOCK_ACK__SHIFT 0xd
+#define UVD_STATUS__IDCT_BLOCK_ACK__SHIFT 0xe
+#define UVD_STATUS__UVD_BLOCK_ACK__SHIFT 0xf
+#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10
+#define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f
+#define UVD_STATUS__RBC_BUSY_MASK 0x00000001L
+#define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL
+#define UVD_STATUS__AVP_BUSY_MASK 0x00000100L
+#define UVD_STATUS__IDCT_BUSY_MASK 0x00000200L
+#define UVD_STATUS__IDCT_CTL_ACK_MASK 0x00000800L
+#define UVD_STATUS__UVD_CTL_ACK_MASK 0x00001000L
+#define UVD_STATUS__AVP_BLOCK_ACK_MASK 0x00002000L
+#define UVD_STATUS__IDCT_BLOCK_ACK_MASK 0x00004000L
+#define UVD_STATUS__UVD_BLOCK_ACK_MASK 0x00008000L
+#define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L
+#define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L
+//UVD_SEMA_TIMEOUT_STATUS
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L
+//UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
+//UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
+//UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
+//UVD_CONTEXT_ID
+#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0
+#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL
+//UVD_CONTEXT_ID2
+#define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0
+#define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_default.h
new file mode 100644
index 000000000000..c2a46c7c448c
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_default.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _vce_4_0_DEFAULT_HEADER
+#define _vce_4_0_DEFAULT_HEADER
+
+
+// addressBlock: vce0_vce_dec
+#define mmVCE_STATUS_DEFAULT 0x00000000
+#define mmVCE_VCPU_CNTL_DEFAULT 0x00200000
+#define mmVCE_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000
+#define mmVCE_VCPU_CACHE_SIZE0_DEFAULT 0x00000000
+#define mmVCE_VCPU_CACHE_OFFSET1_DEFAULT 0x00000000
+#define mmVCE_VCPU_CACHE_SIZE1_DEFAULT 0x00000000
+#define mmVCE_VCPU_CACHE_OFFSET2_DEFAULT 0x00000000
+#define mmVCE_VCPU_CACHE_SIZE2_DEFAULT 0x00000000
+#define mmVCE_VCPU_CACHE_OFFSET3_DEFAULT 0x00000000
+#define mmVCE_VCPU_CACHE_SIZE3_DEFAULT 0x00000000
+#define mmVCE_VCPU_CACHE_OFFSET4_DEFAULT 0x00000000
+#define mmVCE_VCPU_CACHE_SIZE4_DEFAULT 0x00000000
+#define mmVCE_VCPU_CACHE_OFFSET5_DEFAULT 0x00000000
+#define mmVCE_VCPU_CACHE_SIZE5_DEFAULT 0x00000000
+#define mmVCE_VCPU_CACHE_OFFSET6_DEFAULT 0x00000000
+#define mmVCE_VCPU_CACHE_SIZE6_DEFAULT 0x00000000
+#define mmVCE_VCPU_CACHE_OFFSET7_DEFAULT 0x00000000
+#define mmVCE_VCPU_CACHE_SIZE7_DEFAULT 0x00000000
+#define mmVCE_VCPU_CACHE_OFFSET8_DEFAULT 0x00000000
+#define mmVCE_VCPU_CACHE_SIZE8_DEFAULT 0x00000000
+#define mmVCE_SOFT_RESET_DEFAULT 0x00000001
+#define mmVCE_RB_BASE_LO2_DEFAULT 0x00000000
+#define mmVCE_RB_BASE_HI2_DEFAULT 0x00000000
+#define mmVCE_RB_SIZE2_DEFAULT 0x00000000
+#define mmVCE_RB_RPTR2_DEFAULT 0x00000000
+#define mmVCE_RB_WPTR2_DEFAULT 0x00000000
+#define mmVCE_RB_BASE_LO_DEFAULT 0x00000000
+#define mmVCE_RB_BASE_HI_DEFAULT 0x00000000
+#define mmVCE_RB_SIZE_DEFAULT 0x00000000
+#define mmVCE_RB_RPTR_DEFAULT 0x00000000
+#define mmVCE_RB_WPTR_DEFAULT 0x00000000
+#define mmVCE_RB_ARB_CTRL_DEFAULT 0x00010000
+#define mmVCE_CLOCK_GATING_A_DEFAULT 0x00000040
+#define mmVCE_CLOCK_GATING_B_DEFAULT 0x01ef0100
+#define mmVCE_RB_BASE_LO3_DEFAULT 0x00000000
+#define mmVCE_RB_BASE_HI3_DEFAULT 0x00000000
+#define mmVCE_RB_SIZE3_DEFAULT 0x00000000
+#define mmVCE_RB_RPTR3_DEFAULT 0x00000000
+#define mmVCE_RB_WPTR3_DEFAULT 0x00000000
+#define mmVCE_SYS_INT_EN_DEFAULT 0x00000000
+#define mmVCE_SYS_INT_ACK_DEFAULT 0x00000000
+#define mmVCE_SYS_INT_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: vce0_ctl_dec
+#define mmVCE_UENC_CLOCK_GATING_DEFAULT 0xffc00040
+#define mmVCE_UENC_REG_CLOCK_GATING_DEFAULT 0x000007ff
+#define mmVCE_UENC_CLOCK_GATING_2_DEFAULT 0x00010000
+
+
+// addressBlock: vce0_vce_sclk_dec
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR_DEFAULT 0x00000000
+#define mmVCE_LMI_CTRL2_DEFAULT 0x00000000
+#define mmVCE_LMI_SWAP_CNTL3_DEFAULT 0x00000000
+#define mmVCE_LMI_CTRL_DEFAULT 0x00104000
+#define mmVCE_LMI_STATUS_DEFAULT 0x00003f7f
+#define mmVCE_LMI_VM_CTRL_DEFAULT 0x00000000
+#define mmVCE_LMI_SWAP_CNTL_DEFAULT 0x00000000
+#define mmVCE_LMI_SWAP_CNTL1_DEFAULT 0x00000000
+#define mmVCE_LMI_SWAP_CNTL2_DEFAULT 0x00000000
+#define mmVCE_LMI_CACHE_CTRL_DEFAULT 0x00000000
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0_DEFAULT 0x00000000
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1_DEFAULT 0x00000000
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2_DEFAULT 0x00000000
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3_DEFAULT 0x00000000
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4_DEFAULT 0x00000000
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5_DEFAULT 0x00000000
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6_DEFAULT 0x00000000
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7_DEFAULT 0x00000000
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0_DEFAULT 0x00000000
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1_DEFAULT 0x00000000
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2_DEFAULT 0x00000000
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3_DEFAULT 0x00000000
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4_DEFAULT 0x00000000
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5_DEFAULT 0x00000000
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6_DEFAULT 0x00000000
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7_DEFAULT 0x00000000
+
+
+// addressBlock: vce0_mmsch_dec
+#define mmVCE_MMSCH_VF_VMID_DEFAULT 0x00000000
+#define mmVCE_MMSCH_VF_CTX_ADDR_LO_DEFAULT 0x00000000
+#define mmVCE_MMSCH_VF_CTX_ADDR_HI_DEFAULT 0x00000000
+#define mmVCE_MMSCH_VF_CTX_SIZE_DEFAULT 0x00000000
+#define mmVCE_MMSCH_VF_GPCOM_ADDR_LO_DEFAULT 0x00000000
+#define mmVCE_MMSCH_VF_GPCOM_ADDR_HI_DEFAULT 0x00000000
+#define mmVCE_MMSCH_VF_GPCOM_SIZE_DEFAULT 0x00000000
+#define mmVCE_MMSCH_VF_MAILBOX_HOST_DEFAULT 0x00000000
+#define mmVCE_MMSCH_VF_MAILBOX_RESP_DEFAULT 0x00000000
+
+
+// addressBlock: vce0_vce_rb_pg_dec
+#define mmVCE_HW_VERSION_DEFAULT 0x00000000
+
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h
new file mode 100644
index 000000000000..109303e1b08d
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h
@@ -0,0 +1,208 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _vce_4_0_OFFSET_HEADER
+#define _vce_4_0_OFFSET_HEADER
+
+
+
+// addressBlock: vce0_vce_dec
+// base address: 0x22000
+#define mmVCE_STATUS 0x0a01
+#define mmVCE_STATUS_BASE_IDX 0
+#define mmVCE_VCPU_CNTL 0x0a05
+#define mmVCE_VCPU_CNTL_BASE_IDX 0
+#define mmVCE_VCPU_CACHE_OFFSET0 0x0a09
+#define mmVCE_VCPU_CACHE_OFFSET0_BASE_IDX 0
+#define mmVCE_VCPU_CACHE_SIZE0 0x0a0a
+#define mmVCE_VCPU_CACHE_SIZE0_BASE_IDX 0
+#define mmVCE_VCPU_CACHE_OFFSET1 0x0a0b
+#define mmVCE_VCPU_CACHE_OFFSET1_BASE_IDX 0
+#define mmVCE_VCPU_CACHE_SIZE1 0x0a0c
+#define mmVCE_VCPU_CACHE_SIZE1_BASE_IDX 0
+#define mmVCE_VCPU_CACHE_OFFSET2 0x0a0d
+#define mmVCE_VCPU_CACHE_OFFSET2_BASE_IDX 0
+#define mmVCE_VCPU_CACHE_SIZE2 0x0a0e
+#define mmVCE_VCPU_CACHE_SIZE2_BASE_IDX 0
+#define mmVCE_VCPU_CACHE_OFFSET3 0x0a0f
+#define mmVCE_VCPU_CACHE_OFFSET3_BASE_IDX 0
+#define mmVCE_VCPU_CACHE_SIZE3 0x0a10
+#define mmVCE_VCPU_CACHE_SIZE3_BASE_IDX 0
+#define mmVCE_VCPU_CACHE_OFFSET4 0x0a11
+#define mmVCE_VCPU_CACHE_OFFSET4_BASE_IDX 0
+#define mmVCE_VCPU_CACHE_SIZE4 0x0a12
+#define mmVCE_VCPU_CACHE_SIZE4_BASE_IDX 0
+#define mmVCE_VCPU_CACHE_OFFSET5 0x0a13
+#define mmVCE_VCPU_CACHE_OFFSET5_BASE_IDX 0
+#define mmVCE_VCPU_CACHE_SIZE5 0x0a14
+#define mmVCE_VCPU_CACHE_SIZE5_BASE_IDX 0
+#define mmVCE_VCPU_CACHE_OFFSET6 0x0a15
+#define mmVCE_VCPU_CACHE_OFFSET6_BASE_IDX 0
+#define mmVCE_VCPU_CACHE_SIZE6 0x0a16
+#define mmVCE_VCPU_CACHE_SIZE6_BASE_IDX 0
+#define mmVCE_VCPU_CACHE_OFFSET7 0x0a17
+#define mmVCE_VCPU_CACHE_OFFSET7_BASE_IDX 0
+#define mmVCE_VCPU_CACHE_SIZE7 0x0a18
+#define mmVCE_VCPU_CACHE_SIZE7_BASE_IDX 0
+#define mmVCE_VCPU_CACHE_OFFSET8 0x0a19
+#define mmVCE_VCPU_CACHE_OFFSET8_BASE_IDX 0
+#define mmVCE_VCPU_CACHE_SIZE8 0x0a1a
+#define mmVCE_VCPU_CACHE_SIZE8_BASE_IDX 0
+#define mmVCE_SOFT_RESET 0x0a48
+#define mmVCE_SOFT_RESET_BASE_IDX 0
+#define mmVCE_RB_BASE_LO2 0x0a5b
+#define mmVCE_RB_BASE_LO2_BASE_IDX 0
+#define mmVCE_RB_BASE_HI2 0x0a5c
+#define mmVCE_RB_BASE_HI2_BASE_IDX 0
+#define mmVCE_RB_SIZE2 0x0a5d
+#define mmVCE_RB_SIZE2_BASE_IDX 0
+#define mmVCE_RB_RPTR2 0x0a5e
+#define mmVCE_RB_RPTR2_BASE_IDX 0
+#define mmVCE_RB_WPTR2 0x0a5f
+#define mmVCE_RB_WPTR2_BASE_IDX 0
+#define mmVCE_RB_BASE_LO 0x0a60
+#define mmVCE_RB_BASE_LO_BASE_IDX 0
+#define mmVCE_RB_BASE_HI 0x0a61
+#define mmVCE_RB_BASE_HI_BASE_IDX 0
+#define mmVCE_RB_SIZE 0x0a62
+#define mmVCE_RB_SIZE_BASE_IDX 0
+#define mmVCE_RB_RPTR 0x0a63
+#define mmVCE_RB_RPTR_BASE_IDX 0
+#define mmVCE_RB_WPTR 0x0a64
+#define mmVCE_RB_WPTR_BASE_IDX 0
+#define mmVCE_RB_ARB_CTRL 0x0a9f
+#define mmVCE_RB_ARB_CTRL_BASE_IDX 0
+#define mmVCE_CLOCK_GATING_A 0x0abe
+#define mmVCE_CLOCK_GATING_A_BASE_IDX 0
+#define mmVCE_CLOCK_GATING_B 0x0abf
+#define mmVCE_CLOCK_GATING_B_BASE_IDX 0
+#define mmVCE_RB_BASE_LO3 0x0ad4
+#define mmVCE_RB_BASE_LO3_BASE_IDX 0
+#define mmVCE_RB_BASE_HI3 0x0ad5
+#define mmVCE_RB_BASE_HI3_BASE_IDX 0
+#define mmVCE_RB_SIZE3 0x0ad6
+#define mmVCE_RB_SIZE3_BASE_IDX 0
+#define mmVCE_RB_RPTR3 0x0ad7
+#define mmVCE_RB_RPTR3_BASE_IDX 0
+#define mmVCE_RB_WPTR3 0x0ad8
+#define mmVCE_RB_WPTR3_BASE_IDX 0
+#define mmVCE_SYS_INT_EN 0x0b00
+#define mmVCE_SYS_INT_EN_BASE_IDX 0
+#define mmVCE_SYS_INT_ACK 0x0b01
+#define mmVCE_SYS_INT_ACK_BASE_IDX 0
+#define mmVCE_SYS_INT_STATUS 0x0b01
+#define mmVCE_SYS_INT_STATUS_BASE_IDX 0
+
+
+// addressBlock: vce0_ctl_dec
+// base address: 0x22780
+#define mmVCE_UENC_CLOCK_GATING 0x0bef
+#define mmVCE_UENC_CLOCK_GATING_BASE_IDX 0
+#define mmVCE_UENC_REG_CLOCK_GATING 0x0bf0
+#define mmVCE_UENC_REG_CLOCK_GATING_BASE_IDX 0
+#define mmVCE_UENC_CLOCK_GATING_2 0x0c10
+#define mmVCE_UENC_CLOCK_GATING_2_BASE_IDX 0
+
+
+// addressBlock: vce0_vce_sclk_dec
+// base address: 0x23700
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x0fcc
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR_BASE_IDX 0
+#define mmVCE_LMI_CTRL2 0x0fcf
+#define mmVCE_LMI_CTRL2_BASE_IDX 0
+#define mmVCE_LMI_SWAP_CNTL3 0x0fd0
+#define mmVCE_LMI_SWAP_CNTL3_BASE_IDX 0
+#define mmVCE_LMI_CTRL 0x0fd6
+#define mmVCE_LMI_CTRL_BASE_IDX 0
+#define mmVCE_LMI_STATUS 0x0fd7
+#define mmVCE_LMI_STATUS_BASE_IDX 0
+#define mmVCE_LMI_VM_CTRL 0x0fd8
+#define mmVCE_LMI_VM_CTRL_BASE_IDX 0
+#define mmVCE_LMI_SWAP_CNTL 0x0fdd
+#define mmVCE_LMI_SWAP_CNTL_BASE_IDX 0
+#define mmVCE_LMI_SWAP_CNTL1 0x0fde
+#define mmVCE_LMI_SWAP_CNTL1_BASE_IDX 0
+#define mmVCE_LMI_SWAP_CNTL2 0x0fe2
+#define mmVCE_LMI_SWAP_CNTL2_BASE_IDX 0
+#define mmVCE_LMI_CACHE_CTRL 0x0fec
+#define mmVCE_LMI_CACHE_CTRL_BASE_IDX 0
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0 0x1086
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0_BASE_IDX 0
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1 0x1087
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1_BASE_IDX 0
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2 0x1088
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2_BASE_IDX 0
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3 0x1089
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3_BASE_IDX 0
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4 0x108a
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4_BASE_IDX 0
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5 0x108b
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5_BASE_IDX 0
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6 0x108c
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6_BASE_IDX 0
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7 0x108d
+#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7_BASE_IDX 0
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x1096
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0_BASE_IDX 0
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x1097
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1_BASE_IDX 0
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0x1098
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2_BASE_IDX 0
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3 0x1099
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3_BASE_IDX 0
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4 0x109a
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4_BASE_IDX 0
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5 0x109b
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5_BASE_IDX 0
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6 0x109c
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6_BASE_IDX 0
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7 0x109d
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7_BASE_IDX 0
+
+
+// addressBlock: vce0_mmsch_dec
+// base address: 0x23b00
+#define mmVCE_MMSCH_VF_VMID 0x10cb
+#define mmVCE_MMSCH_VF_VMID_BASE_IDX 0
+#define mmVCE_MMSCH_VF_CTX_ADDR_LO 0x10cc
+#define mmVCE_MMSCH_VF_CTX_ADDR_LO_BASE_IDX 0
+#define mmVCE_MMSCH_VF_CTX_ADDR_HI 0x10cd
+#define mmVCE_MMSCH_VF_CTX_ADDR_HI_BASE_IDX 0
+#define mmVCE_MMSCH_VF_CTX_SIZE 0x10ce
+#define mmVCE_MMSCH_VF_CTX_SIZE_BASE_IDX 0
+#define mmVCE_MMSCH_VF_GPCOM_ADDR_LO 0x10cf
+#define mmVCE_MMSCH_VF_GPCOM_ADDR_LO_BASE_IDX 0
+#define mmVCE_MMSCH_VF_GPCOM_ADDR_HI 0x10d0
+#define mmVCE_MMSCH_VF_GPCOM_ADDR_HI_BASE_IDX 0
+#define mmVCE_MMSCH_VF_GPCOM_SIZE 0x10d1
+#define mmVCE_MMSCH_VF_GPCOM_SIZE_BASE_IDX 0
+#define mmVCE_MMSCH_VF_MAILBOX_HOST 0x10d2
+#define mmVCE_MMSCH_VF_MAILBOX_HOST_BASE_IDX 0
+#define mmVCE_MMSCH_VF_MAILBOX_RESP 0x10d3
+#define mmVCE_MMSCH_VF_MAILBOX_RESP_BASE_IDX 0
+
+
+// addressBlock: vce0_vce_rb_pg_dec
+// base address: 0x23fa0
+#define mmVCE_HW_VERSION 0x11e8
+#define mmVCE_HW_VERSION_BASE_IDX 0
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h
new file mode 100644
index 000000000000..4cf6e4424198
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h
@@ -0,0 +1,488 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _vce_4_0_SH_MASK_HEADER
+#define _vce_4_0_SH_MASK_HEADER
+
+
+// addressBlock: vce0_vce_dec
+//VCE_STATUS
+#define VCE_STATUS__JOB_BUSY__SHIFT 0x0
+#define VCE_STATUS__VCPU_REPORT__SHIFT 0x1
+#define VCE_STATUS__UENC_BUSY__SHIFT 0x8
+#define VCE_STATUS__VCE_CONFIGURATION__SHIFT 0x16
+#define VCE_STATUS__VCE_INSTANCE_ID__SHIFT 0x18
+#define VCE_STATUS__JOB_BUSY_MASK 0x00000001L
+#define VCE_STATUS__VCPU_REPORT_MASK 0x000000FEL
+#define VCE_STATUS__UENC_BUSY_MASK 0x00000100L
+#define VCE_STATUS__VCE_CONFIGURATION_MASK 0x00C00000L
+#define VCE_STATUS__VCE_INSTANCE_ID_MASK 0x03000000L
+//VCE_VCPU_CNTL
+#define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x0
+#define VCE_VCPU_CNTL__ED_ENABLE__SHIFT 0x1
+#define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x12
+#define VCE_VCPU_CNTL__ONE_CACHE_SURFACE_EN__SHIFT 0x15
+#define VCE_VCPU_CNTL__CLK_EN_MASK 0x00000001L
+#define VCE_VCPU_CNTL__ED_ENABLE_MASK 0x00000002L
+#define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00040000L
+#define VCE_VCPU_CNTL__ONE_CACHE_SURFACE_EN_MASK 0x00200000L
+//VCE_VCPU_CACHE_OFFSET0
+#define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT 0x0
+#define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK 0x0FFFFFFFL
+//VCE_VCPU_CACHE_SIZE0
+#define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT 0x0
+#define VCE_VCPU_CACHE_SIZE0__SIZE_MASK 0x00FFFFFFL
+//VCE_VCPU_CACHE_OFFSET1
+#define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT 0x0
+#define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK 0x0FFFFFFFL
+//VCE_VCPU_CACHE_SIZE1
+#define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT 0x0
+#define VCE_VCPU_CACHE_SIZE1__SIZE_MASK 0x00FFFFFFL
+//VCE_VCPU_CACHE_OFFSET2
+#define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT 0x0
+#define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK 0x0FFFFFFFL
+//VCE_VCPU_CACHE_SIZE2
+#define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT 0x0
+#define VCE_VCPU_CACHE_SIZE2__SIZE_MASK 0x00FFFFFFL
+//VCE_VCPU_CACHE_OFFSET3
+#define VCE_VCPU_CACHE_OFFSET3__OFFSET__SHIFT 0x0
+#define VCE_VCPU_CACHE_OFFSET3__OFFSET_MASK 0x0FFFFFFFL
+//VCE_VCPU_CACHE_SIZE3
+#define VCE_VCPU_CACHE_SIZE3__SIZE__SHIFT 0x0
+#define VCE_VCPU_CACHE_SIZE3__SIZE_MASK 0x00FFFFFFL
+//VCE_VCPU_CACHE_OFFSET4
+#define VCE_VCPU_CACHE_OFFSET4__OFFSET__SHIFT 0x0
+#define VCE_VCPU_CACHE_OFFSET4__OFFSET_MASK 0x0FFFFFFFL
+//VCE_VCPU_CACHE_SIZE4
+#define VCE_VCPU_CACHE_SIZE4__SIZE__SHIFT 0x0
+#define VCE_VCPU_CACHE_SIZE4__SIZE_MASK 0x00FFFFFFL
+//VCE_VCPU_CACHE_OFFSET5
+#define VCE_VCPU_CACHE_OFFSET5__OFFSET__SHIFT 0x0
+#define VCE_VCPU_CACHE_OFFSET5__OFFSET_MASK 0x0FFFFFFFL
+//VCE_VCPU_CACHE_SIZE5
+#define VCE_VCPU_CACHE_SIZE5__SIZE__SHIFT 0x0
+#define VCE_VCPU_CACHE_SIZE5__SIZE_MASK 0x00FFFFFFL
+//VCE_VCPU_CACHE_OFFSET6
+#define VCE_VCPU_CACHE_OFFSET6__OFFSET__SHIFT 0x0
+#define VCE_VCPU_CACHE_OFFSET6__OFFSET_MASK 0x0FFFFFFFL
+//VCE_VCPU_CACHE_SIZE6
+#define VCE_VCPU_CACHE_SIZE6__SIZE__SHIFT 0x0
+#define VCE_VCPU_CACHE_SIZE6__SIZE_MASK 0x00FFFFFFL
+//VCE_VCPU_CACHE_OFFSET7
+#define VCE_VCPU_CACHE_OFFSET7__OFFSET__SHIFT 0x0
+#define VCE_VCPU_CACHE_OFFSET7__OFFSET_MASK 0x0FFFFFFFL
+//VCE_VCPU_CACHE_SIZE7
+#define VCE_VCPU_CACHE_SIZE7__SIZE__SHIFT 0x0
+#define VCE_VCPU_CACHE_SIZE7__SIZE_MASK 0x00FFFFFFL
+//VCE_VCPU_CACHE_OFFSET8
+#define VCE_VCPU_CACHE_OFFSET8__OFFSET__SHIFT 0x0
+#define VCE_VCPU_CACHE_OFFSET8__OFFSET_MASK 0x0FFFFFFFL
+//VCE_VCPU_CACHE_SIZE8
+#define VCE_VCPU_CACHE_SIZE8__SIZE__SHIFT 0x0
+#define VCE_VCPU_CACHE_SIZE8__SIZE_MASK 0x00FFFFFFL
+//VCE_SOFT_RESET
+#define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x0
+#define VCE_SOFT_RESET__UENC_SOFT_RESET__SHIFT 0x1
+#define VCE_SOFT_RESET__FME_SOFT_RESET__SHIFT 0x2
+#define VCE_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0x3
+#define VCE_SOFT_RESET__DBF_SOFT_RESET__SHIFT 0x4
+#define VCE_SOFT_RESET__ENT_SOFT_RESET__SHIFT 0x5
+#define VCE_SOFT_RESET__TBE_SOFT_RESET__SHIFT 0x6
+#define VCE_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x7
+#define VCE_SOFT_RESET__CTL_SOFT_RESET__SHIFT 0x8
+#define VCE_SOFT_RESET__IME_SOFT_RESET__SHIFT 0x9
+#define VCE_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
+#define VCE_SOFT_RESET__SEM_SOFT_RESET__SHIFT 0xb
+#define VCE_SOFT_RESET__DCAP_SOFT_RESET__SHIFT 0xc
+#define VCE_SOFT_RESET__ACAP_SOFT_RESET__SHIFT 0xd
+#define VCE_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0xe
+#define VCE_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0xf
+#define VCE_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0x10
+#define VCE_SOFT_RESET__AVMUX_SOFT_RESET__SHIFT 0x13
+#define VCE_SOFT_RESET__VREG_SOFT_RESET__SHIFT 0x14
+#define VCE_SOFT_RESET__DCAP_FSM_SOFT_RESET__SHIFT 0x15
+#define VCE_SOFT_RESET__VEP_SOFT_RESET__SHIFT 0x16
+#define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x00000001L
+#define VCE_SOFT_RESET__UENC_SOFT_RESET_MASK 0x00000002L
+#define VCE_SOFT_RESET__FME_SOFT_RESET_MASK 0x00000004L
+#define VCE_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00000008L
+#define VCE_SOFT_RESET__DBF_SOFT_RESET_MASK 0x00000010L
+#define VCE_SOFT_RESET__ENT_SOFT_RESET_MASK 0x00000020L
+#define VCE_SOFT_RESET__TBE_SOFT_RESET_MASK 0x00000040L
+#define VCE_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00000080L
+#define VCE_SOFT_RESET__CTL_SOFT_RESET_MASK 0x00000100L
+#define VCE_SOFT_RESET__IME_SOFT_RESET_MASK 0x00000200L
+#define VCE_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L
+#define VCE_SOFT_RESET__SEM_SOFT_RESET_MASK 0x00000800L
+#define VCE_SOFT_RESET__DCAP_SOFT_RESET_MASK 0x00001000L
+#define VCE_SOFT_RESET__ACAP_SOFT_RESET_MASK 0x00002000L
+#define VCE_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00004000L
+#define VCE_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00008000L
+#define VCE_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00010000L
+#define VCE_SOFT_RESET__AVMUX_SOFT_RESET_MASK 0x00080000L
+#define VCE_SOFT_RESET__VREG_SOFT_RESET_MASK 0x00100000L
+#define VCE_SOFT_RESET__DCAP_FSM_SOFT_RESET_MASK 0x00200000L
+#define VCE_SOFT_RESET__VEP_SOFT_RESET_MASK 0x00400000L
+//VCE_RB_BASE_LO2
+#define VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6
+#define VCE_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L
+//VCE_RB_BASE_HI2
+#define VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0
+#define VCE_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL
+//VCE_RB_SIZE2
+#define VCE_RB_SIZE2__RB_SIZE__SHIFT 0x4
+#define VCE_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L
+//VCE_RB_RPTR2
+#define VCE_RB_RPTR2__RB_RPTR__SHIFT 0x4
+#define VCE_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L
+//VCE_RB_WPTR2
+#define VCE_RB_WPTR2__RB_WPTR__SHIFT 0x4
+#define VCE_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L
+//VCE_RB_BASE_LO
+#define VCE_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6
+#define VCE_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L
+//VCE_RB_BASE_HI
+#define VCE_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define VCE_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL
+//VCE_RB_SIZE
+#define VCE_RB_SIZE__RB_SIZE__SHIFT 0x4
+#define VCE_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L
+//VCE_RB_RPTR
+#define VCE_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define VCE_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
+//VCE_RB_WPTR
+#define VCE_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define VCE_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
+//VCE_RB_ARB_CTRL
+#define VCE_RB_ARB_CTRL__RB_ARB_CTRL__SHIFT 0x0
+#define VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE__SHIFT 0x10
+#define VCE_RB_ARB_CTRL__RB_ARB_CTRL_MASK 0x000001FFL
+#define VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE_MASK 0x00010000L
+//VCE_CLOCK_GATING_A
+#define VCE_CLOCK_GATING_A__CGC_CLK_ON_DELAY__SHIFT 0x0
+#define VCE_CLOCK_GATING_A__CGC_CLK_OFF_DELAY__SHIFT 0x4
+#define VCE_CLOCK_GATING_A__CGC_REG_AWAKE__SHIFT 0x11
+#define VCE_CLOCK_GATING_A__CGC_CLK_ON_DELAY_MASK 0x0000000FL
+#define VCE_CLOCK_GATING_A__CGC_CLK_OFF_DELAY_MASK 0x00000FF0L
+#define VCE_CLOCK_GATING_A__CGC_REG_AWAKE_MASK 0x00020000L
+//VCE_CLOCK_GATING_B
+#define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_ON__SHIFT 0x0
+#define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_ON__SHIFT 0x1
+#define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_ON__SHIFT 0x2
+#define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_ON__SHIFT 0x3
+#define VCE_CLOCK_GATING_B__CGC_VREG_CLK_FORCE_ON__SHIFT 0x4
+#define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_ON__SHIFT 0x5
+#define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_ON__SHIFT 0x6
+#define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_ON__SHIFT 0x7
+#define VCE_CLOCK_GATING_B__CGC_CTLREG_CLK_FORCE_ON__SHIFT 0x8
+#define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_ON__SHIFT 0x9
+#define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_OFF__SHIFT 0x10
+#define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_OFF__SHIFT 0x11
+#define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_OFF__SHIFT 0x12
+#define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_OFF__SHIFT 0x13
+#define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_OFF__SHIFT 0x15
+#define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_OFF__SHIFT 0x16
+#define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_OFF__SHIFT 0x17
+#define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_OFF__SHIFT 0x18
+#define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_ON_MASK 0x00000001L
+#define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_ON_MASK 0x00000002L
+#define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_ON_MASK 0x00000004L
+#define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_ON_MASK 0x00000008L
+#define VCE_CLOCK_GATING_B__CGC_VREG_CLK_FORCE_ON_MASK 0x00000010L
+#define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_ON_MASK 0x00000020L
+#define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_ON_MASK 0x00000040L
+#define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_ON_MASK 0x00000080L
+#define VCE_CLOCK_GATING_B__CGC_CTLREG_CLK_FORCE_ON_MASK 0x00000100L
+#define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_ON_MASK 0x00000200L
+#define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_OFF_MASK 0x00010000L
+#define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_OFF_MASK 0x00020000L
+#define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_OFF_MASK 0x00040000L
+#define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_OFF_MASK 0x00080000L
+#define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_OFF_MASK 0x00200000L
+#define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_OFF_MASK 0x00400000L
+#define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_OFF_MASK 0x00800000L
+#define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_OFF_MASK 0x01000000L
+//VCE_RB_BASE_LO3
+#define VCE_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6
+#define VCE_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L
+//VCE_RB_BASE_HI3
+#define VCE_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0
+#define VCE_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL
+//VCE_RB_SIZE3
+#define VCE_RB_SIZE3__RB_SIZE__SHIFT 0x4
+#define VCE_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L
+//VCE_RB_RPTR3
+#define VCE_RB_RPTR3__RB_RPTR__SHIFT 0x4
+#define VCE_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L
+//VCE_RB_WPTR3
+#define VCE_RB_WPTR3__RB_WPTR__SHIFT 0x4
+#define VCE_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L
+//VCE_SYS_INT_EN
+#define VCE_SYS_INT_EN__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_EN__SHIFT 0x0
+#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x3
+#define VCE_SYS_INT_EN__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_EN_MASK 0x00000001L
+#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK 0x00000008L
+//VCE_SYS_INT_ACK
+#define VCE_SYS_INT_ACK__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_ACK__SHIFT 0x0
+#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x3
+#define VCE_SYS_INT_ACK__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_ACK_MASK 0x00000001L
+#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK 0x00000008L
+//VCE_SYS_INT_STATUS
+#define VCE_SYS_INT_STATUS__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_INT__SHIFT 0x0
+#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x3
+#define VCE_SYS_INT_STATUS__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_INT_MASK 0x00000001L
+#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK 0x00000008L
+
+
+// addressBlock: vce0_ctl_dec
+//VCE_UENC_CLOCK_GATING
+#define VCE_UENC_CLOCK_GATING__CLOCK_ON_DELAY__SHIFT 0x0
+#define VCE_UENC_CLOCK_GATING__CLOCK_OFF_DELAY__SHIFT 0x4
+#define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_ON__SHIFT 0xc
+#define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_ON__SHIFT 0xd
+#define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_ON__SHIFT 0xe
+#define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_ON__SHIFT 0xf
+#define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_ON__SHIFT 0x10
+#define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_ON__SHIFT 0x11
+#define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_ON__SHIFT 0x12
+#define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_ON__SHIFT 0x13
+#define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_ON__SHIFT 0x14
+#define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_ON__SHIFT 0x15
+#define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_OFF__SHIFT 0x16
+#define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_OFF__SHIFT 0x17
+#define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_OFF__SHIFT 0x18
+#define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_OFF__SHIFT 0x19
+#define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_OFF__SHIFT 0x1a
+#define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_OFF__SHIFT 0x1b
+#define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_OFF__SHIFT 0x1c
+#define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_OFF__SHIFT 0x1d
+#define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_OFF__SHIFT 0x1e
+#define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_OFF__SHIFT 0x1f
+#define VCE_UENC_CLOCK_GATING__CLOCK_ON_DELAY_MASK 0x0000000FL
+#define VCE_UENC_CLOCK_GATING__CLOCK_OFF_DELAY_MASK 0x00000FF0L
+#define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_ON_MASK 0x00001000L
+#define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_ON_MASK 0x00002000L
+#define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_ON_MASK 0x00004000L
+#define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_ON_MASK 0x00008000L
+#define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_ON_MASK 0x00010000L
+#define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_ON_MASK 0x00020000L
+#define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_ON_MASK 0x00040000L
+#define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_ON_MASK 0x00080000L
+#define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_ON_MASK 0x00100000L
+#define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_ON_MASK 0x00200000L
+#define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_OFF_MASK 0x00400000L
+#define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_OFF_MASK 0x00800000L
+#define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_OFF_MASK 0x01000000L
+#define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_OFF_MASK 0x02000000L
+#define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_OFF_MASK 0x04000000L
+#define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_OFF_MASK 0x08000000L
+#define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_OFF_MASK 0x10000000L
+#define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_OFF_MASK 0x20000000L
+#define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_OFF_MASK 0x40000000L
+#define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_OFF_MASK 0x80000000L
+//VCE_UENC_REG_CLOCK_GATING
+#define VCE_UENC_REG_CLOCK_GATING__MIFREGCLK_FORCE_ON__SHIFT 0x0
+#define VCE_UENC_REG_CLOCK_GATING__IMEREGCLK_FORCE_ON__SHIFT 0x1
+#define VCE_UENC_REG_CLOCK_GATING__FMEREGCLK_FORCE_ON__SHIFT 0x2
+#define VCE_UENC_REG_CLOCK_GATING__TBEREGCLK_FORCE_ON__SHIFT 0x3
+#define VCE_UENC_REG_CLOCK_GATING__DBFREGCLK_FORCE_ON__SHIFT 0x4
+#define VCE_UENC_REG_CLOCK_GATING__ENTREGCLK_FORCE_ON__SHIFT 0x5
+#define VCE_UENC_REG_CLOCK_GATING__LCMREGCLK_FORCE_ON__SHIFT 0x6
+#define VCE_UENC_REG_CLOCK_GATING__RESERVED__SHIFT 0x7
+#define VCE_UENC_REG_CLOCK_GATING__AVMREGCLK_FORCE_ON__SHIFT 0x8
+#define VCE_UENC_REG_CLOCK_GATING__DCAPREGCLK_FORCE_ON__SHIFT 0x9
+#define VCE_UENC_REG_CLOCK_GATING__VEPREGCLK_FORCE_ON__SHIFT 0xa
+#define VCE_UENC_REG_CLOCK_GATING__MIFREGCLK_FORCE_ON_MASK 0x00000001L
+#define VCE_UENC_REG_CLOCK_GATING__IMEREGCLK_FORCE_ON_MASK 0x00000002L
+#define VCE_UENC_REG_CLOCK_GATING__FMEREGCLK_FORCE_ON_MASK 0x00000004L
+#define VCE_UENC_REG_CLOCK_GATING__TBEREGCLK_FORCE_ON_MASK 0x00000008L
+#define VCE_UENC_REG_CLOCK_GATING__DBFREGCLK_FORCE_ON_MASK 0x00000010L
+#define VCE_UENC_REG_CLOCK_GATING__ENTREGCLK_FORCE_ON_MASK 0x00000020L
+#define VCE_UENC_REG_CLOCK_GATING__LCMREGCLK_FORCE_ON_MASK 0x00000040L
+#define VCE_UENC_REG_CLOCK_GATING__RESERVED_MASK 0x00000080L
+#define VCE_UENC_REG_CLOCK_GATING__AVMREGCLK_FORCE_ON_MASK 0x00000100L
+#define VCE_UENC_REG_CLOCK_GATING__DCAPREGCLK_FORCE_ON_MASK 0x00000200L
+#define VCE_UENC_REG_CLOCK_GATING__VEPREGCLK_FORCE_ON_MASK 0x00000400L
+//VCE_UENC_CLOCK_GATING_2
+#define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_ON__SHIFT 0x1
+#define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_OFF__SHIFT 0x10
+#define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_ON_MASK 0x00000002L
+#define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_OFF_MASK 0x00010000L
+
+
+// addressBlock: vce0_vce_sclk_dec
+//VCE_LMI_VCPU_CACHE_40BIT_BAR
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT 0x0
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK 0xFFFFFFFFL
+//VCE_LMI_CTRL2
+#define VCE_LMI_CTRL2__STALL_ARB__SHIFT 0x1
+#define VCE_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2
+#define VCE_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3
+#define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
+#define VCE_LMI_CTRL2__STALL_ARB_MASK 0x00000002L
+#define VCE_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L
+#define VCE_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L
+#define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L
+//VCE_LMI_SWAP_CNTL3
+#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP__SHIFT 0x0
+#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_TRAN__SHIFT 0x14
+#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_URG__SHIFT 0x1a
+#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP_MASK 0x00000003L
+#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_TRAN_MASK 0x00100000L
+#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_URG_MASK 0x04000000L
+//VCE_LMI_CTRL
+#define VCE_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb
+#define VCE_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc
+#define VCE_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd
+#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15
+#define VCE_LMI_CTRL__MIF_DATA_COHERENCY_EN__SHIFT 0x16
+#define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_EN__SHIFT 0x17
+#define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_RESET__SHIFT 0x18
+#define VCE_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L
+#define VCE_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L
+#define VCE_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L
+#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L
+#define VCE_LMI_CTRL__MIF_DATA_COHERENCY_EN_MASK 0x00400000L
+#define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_EN_MASK 0x00800000L
+#define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_RESET_MASK 0x01000000L
+//VCE_LMI_SWAP_CNTL
+#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x0
+#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x2
+#define VCE_LMI_SWAP_CNTL__WR_MC_CID_TRAN__SHIFT 0x14
+#define VCE_LMI_SWAP_CNTL__WR_MC_CID_URG__SHIFT 0x1a
+#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000003L
+#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK 0x00003FFCL
+#define VCE_LMI_SWAP_CNTL__WR_MC_CID_TRAN_MASK 0x03F00000L
+#define VCE_LMI_SWAP_CNTL__WR_MC_CID_URG_MASK 0xFC000000L
+//VCE_LMI_SWAP_CNTL1
+#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x0
+#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x2
+#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_TRAN__SHIFT 0x14
+#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_URG__SHIFT 0x1a
+#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x00000003L
+#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x00003FFCL
+#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_TRAN_MASK 0x03F00000L
+#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_URG_MASK 0xFC000000L
+//VCE_LMI_SWAP_CNTL2
+#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP__SHIFT 0x0
+#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_TRAN__SHIFT 0x14
+#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_URG__SHIFT 0x1a
+#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP_MASK 0x000000FFL
+#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_TRAN_MASK 0x00F00000L
+#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_URG_MASK 0x3C000000L
+//VCE_LMI_CACHE_CTRL
+#define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x0
+#define VCE_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x1
+#define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x00000001L
+#define VCE_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x00000002L
+//VCE_LMI_VCPU_CACHE_64BIT_BAR0
+#define VCE_LMI_VCPU_CACHE_64BIT_BAR0__BAR__SHIFT 0x0
+#define VCE_LMI_VCPU_CACHE_64BIT_BAR0__BAR_MASK 0x000000FFL
+//VCE_LMI_VCPU_CACHE_64BIT_BAR1
+#define VCE_LMI_VCPU_CACHE_64BIT_BAR1__BAR__SHIFT 0x0
+#define VCE_LMI_VCPU_CACHE_64BIT_BAR1__BAR_MASK 0x000000FFL
+//VCE_LMI_VCPU_CACHE_64BIT_BAR2
+#define VCE_LMI_VCPU_CACHE_64BIT_BAR2__BAR__SHIFT 0x0
+#define VCE_LMI_VCPU_CACHE_64BIT_BAR2__BAR_MASK 0x000000FFL
+//VCE_LMI_VCPU_CACHE_64BIT_BAR3
+#define VCE_LMI_VCPU_CACHE_64BIT_BAR3__BAR__SHIFT 0x0
+#define VCE_LMI_VCPU_CACHE_64BIT_BAR3__BAR_MASK 0x000000FFL
+//VCE_LMI_VCPU_CACHE_64BIT_BAR4
+#define VCE_LMI_VCPU_CACHE_64BIT_BAR4__BAR__SHIFT 0x0
+#define VCE_LMI_VCPU_CACHE_64BIT_BAR4__BAR_MASK 0x000000FFL
+//VCE_LMI_VCPU_CACHE_64BIT_BAR5
+#define VCE_LMI_VCPU_CACHE_64BIT_BAR5__BAR__SHIFT 0x0
+#define VCE_LMI_VCPU_CACHE_64BIT_BAR5__BAR_MASK 0x000000FFL
+//VCE_LMI_VCPU_CACHE_64BIT_BAR6
+#define VCE_LMI_VCPU_CACHE_64BIT_BAR6__BAR__SHIFT 0x0
+#define VCE_LMI_VCPU_CACHE_64BIT_BAR6__BAR_MASK 0x000000FFL
+//VCE_LMI_VCPU_CACHE_64BIT_BAR7
+#define VCE_LMI_VCPU_CACHE_64BIT_BAR7__BAR__SHIFT 0x0
+#define VCE_LMI_VCPU_CACHE_64BIT_BAR7__BAR_MASK 0x000000FFL
+//VCE_LMI_VCPU_CACHE_40BIT_BAR0
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR0__BAR__SHIFT 0x0
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR0__BAR_MASK 0xFFFFFFFFL
+//VCE_LMI_VCPU_CACHE_40BIT_BAR1
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR1__BAR__SHIFT 0x0
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR1__BAR_MASK 0xFFFFFFFFL
+//VCE_LMI_VCPU_CACHE_40BIT_BAR2
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR2__BAR__SHIFT 0x0
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR2__BAR_MASK 0xFFFFFFFFL
+//VCE_LMI_VCPU_CACHE_40BIT_BAR3
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR3__BAR__SHIFT 0x0
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR3__BAR_MASK 0xFFFFFFFFL
+//VCE_LMI_VCPU_CACHE_40BIT_BAR4
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR4__BAR__SHIFT 0x0
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR4__BAR_MASK 0xFFFFFFFFL
+//VCE_LMI_VCPU_CACHE_40BIT_BAR5
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR5__BAR__SHIFT 0x0
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR5__BAR_MASK 0xFFFFFFFFL
+//VCE_LMI_VCPU_CACHE_40BIT_BAR6
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR6__BAR__SHIFT 0x0
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR6__BAR_MASK 0xFFFFFFFFL
+//VCE_LMI_VCPU_CACHE_40BIT_BAR7
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR7__BAR__SHIFT 0x0
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR7__BAR_MASK 0xFFFFFFFFL
+
+
+// addressBlock: vce0_mmsch_dec
+//VCE_MMSCH_VF_VMID
+#define VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT 0x0
+#define VCE_MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x4
+#define VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK 0x0000000FL
+#define VCE_MMSCH_VF_VMID__VF_GPCOM_VMID_MASK 0x000000F0L
+//VCE_MMSCH_VF_CTX_ADDR_LO
+#define VCE_MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT 0x6
+#define VCE_MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK 0xFFFFFFC0L
+//VCE_MMSCH_VF_CTX_ADDR_HI
+#define VCE_MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT 0x0
+#define VCE_MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK 0xFFFFFFFFL
+//VCE_MMSCH_VF_CTX_SIZE
+#define VCE_MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT 0x0
+#define VCE_MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK 0xFFFFFFFFL
+//VCE_MMSCH_VF_GPCOM_ADDR_LO
+#define VCE_MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT 0x6
+#define VCE_MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK 0xFFFFFFC0L
+//VCE_MMSCH_VF_GPCOM_ADDR_HI
+#define VCE_MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT 0x0
+#define VCE_MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK 0xFFFFFFFFL
+//VCE_MMSCH_VF_GPCOM_SIZE
+#define VCE_MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT 0x0
+#define VCE_MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK 0xFFFFFFFFL
+//VCE_MMSCH_VF_MAILBOX_HOST
+#define VCE_MMSCH_VF_MAILBOX_HOST__DATA__SHIFT 0x0
+#define VCE_MMSCH_VF_MAILBOX_HOST__DATA_MASK 0xFFFFFFFFL
+//VCE_MMSCH_VF_MAILBOX_RESP
+#define VCE_MMSCH_VF_MAILBOX_RESP__RESP__SHIFT 0x0
+#define VCE_MMSCH_VF_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL
+
+
+// addressBlock: vce0_vce_rb_pg_dec
+//VCE_HW_VERSION
+#define VCE_HW_VERSION__VCE_VERSION__SHIFT 0x0
+#define VCE_HW_VERSION__VCE_CONFIGURATION__SHIFT 0x8
+#define VCE_HW_VERSION__VCE_INSTANCE_ID__SHIFT 0xa
+#define VCE_HW_VERSION__VCE_VERSION_MASK 0x000000FFL
+#define VCE_HW_VERSION__VCE_CONFIGURATION_MASK 0x00000300L
+#define VCE_HW_VERSION__VCE_INSTANCE_ID_MASK 0x00000C00L
+
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h
new file mode 100644
index 000000000000..1767db69df7a
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h
@@ -0,0 +1,1343 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _soc15ip_new_HEADER
+#define _soc15ip_new_HEADER
+
+// HW ID
+#define MP1_HWID 1
+#define MP2_HWID 2
+#define THM_HWID 3
+#define SMUIO_HWID 4
+#define FUSE_HWID 5
+#define CLKA_HWID 6
+#define PWR_HWID 10
+#define GC_HWID 11
+#define UVD_HWID 12
+#define VCN_HWID UVD_HWID
+#define AUDIO_AZ_HWID 13
+#define ACP_HWID 14
+#define DCI_HWID 15
+#define DMU_HWID 271
+#define DCO_HWID 16
+#define DIO_HWID 272
+#define XDMA_HWID 17
+#define DCEAZ_HWID 18
+#define DAZ_HWID 274
+#define SDPMUX_HWID 19
+#define NTB_HWID 20
+#define IOHC_HWID 24
+#define L2IMU_HWID 28
+#define VCE_HWID 32
+#define MMHUB_HWID 34
+#define ATHUB_HWID 35
+#define DBGU_NBIO_HWID 36
+#define DFX_HWID 37
+#define DBGU0_HWID 38
+#define DBGU1_HWID 39
+#define OSSSYS_HWID 40
+#define HDP_HWID 41
+#define SDMA0_HWID 42
+#define SDMA1_HWID 43
+#define ISP_HWID 44
+#define DBGU_IO_HWID 45
+#define DF_HWID 46
+#define CLKB_HWID 47
+#define FCH_HWID 48
+#define DFX_DAP_HWID 49
+#define L1IMU_PCIE_HWID 50
+#define L1IMU_NBIF_HWID 51
+#define L1IMU_IOAGR_HWID 52
+#define L1IMU3_HWID 53
+#define L1IMU4_HWID 54
+#define L1IMU5_HWID 55
+#define L1IMU6_HWID 56
+#define L1IMU7_HWID 57
+#define L1IMU8_HWID 58
+#define L1IMU9_HWID 59
+#define L1IMU10_HWID 60
+#define L1IMU11_HWID 61
+#define L1IMU12_HWID 62
+#define L1IMU13_HWID 63
+#define L1IMU14_HWID 64
+#define L1IMU15_HWID 65
+#define WAFLC_HWID 66
+#define FCH_USB_PD_HWID 67
+#define PCIE_HWID 70
+#define PCS_HWID 80
+#define DDCL_HWID 89
+#define SST_HWID 90
+#define IOAGR_HWID 100
+#define NBIF_HWID 108
+#define IOAPIC_HWID 124
+#define SYSTEMHUB_HWID 128
+#define NTBCCP_HWID 144
+#define UMC_HWID 150
+#define SATA_HWID 168
+#define USB_HWID 170
+#define CCXSEC_HWID 176
+#define XGBE_HWID 216
+#define MP0_HWID 254
+
+#define MAX_INSTANCE 5
+#define MAX_SEGMENT 5
+
+
+struct IP_BASE_INSTANCE
+{
+ unsigned int segment[MAX_SEGMENT];
+};
+
+struct IP_BASE
+{
+ struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
+};
+
+
+static const struct IP_BASE NBIF_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP2_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE UVD_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment
+static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment
+static const struct IP_BASE DBGU_BASE = { { { { 0x00000180, 0x000001A0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; // not exist
+static const struct IP_BASE DBGU_NBIO_BASE = { { { { 0x000001C0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; // not exist
+static const struct IP_BASE DBGU_IO_BASE = { { { { 0x000001E0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; // not exist
+static const struct IP_BASE DFX_DAP_BASE = { { { { 0x000005A0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; // not exist
+static const struct IP_BASE DFX_BASE = { { { { 0x00000580, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers
+static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; // not exist
+static const struct IP_BASE SYSTEMHUB_BASE = { { { { 0x00000EA0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; // not exist
+static const struct IP_BASE L2IMU_BASE = { { { { 0x00007DC0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE IOHC_BASE = { { { { 0x00010000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE VCE_BASE = { { { { 0x00007E00, 0x00048800, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SDMA1_BASE = { { { { 0x00001460, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE XDMA_BASE = { { { { 0x00003400, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE PWR_BASE = { { { { 0x00016A00, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } },
+ { { 0x00016E00, 0, 0, 0, 0 } },
+ { { 0x00017000, 0, 0, 0, 0 } },
+ { { 0x00017200, 0, 0, 0, 0 } },
+ { { 0x00017E00, 0, 0, 0, 0 } } } };
+static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+
+
+#define NBIF_BASE__INST0_SEG0 0x00000000
+#define NBIF_BASE__INST0_SEG1 0x00000014
+#define NBIF_BASE__INST0_SEG2 0x00000D20
+#define NBIF_BASE__INST0_SEG3 0x00010400
+#define NBIF_BASE__INST0_SEG4 0
+
+#define NBIF_BASE__INST1_SEG0 0
+#define NBIF_BASE__INST1_SEG1 0
+#define NBIF_BASE__INST1_SEG2 0
+#define NBIF_BASE__INST1_SEG3 0
+#define NBIF_BASE__INST1_SEG4 0
+
+#define NBIF_BASE__INST2_SEG0 0
+#define NBIF_BASE__INST2_SEG1 0
+#define NBIF_BASE__INST2_SEG2 0
+#define NBIF_BASE__INST2_SEG3 0
+#define NBIF_BASE__INST2_SEG4 0
+
+#define NBIF_BASE__INST3_SEG0 0
+#define NBIF_BASE__INST3_SEG1 0
+#define NBIF_BASE__INST3_SEG2 0
+#define NBIF_BASE__INST3_SEG3 0
+#define NBIF_BASE__INST3_SEG4 0
+
+#define NBIF_BASE__INST4_SEG0 0
+#define NBIF_BASE__INST4_SEG1 0
+#define NBIF_BASE__INST4_SEG2 0
+#define NBIF_BASE__INST4_SEG3 0
+#define NBIF_BASE__INST4_SEG4 0
+
+#define NBIO_BASE__INST0_SEG0 0x00000000
+#define NBIO_BASE__INST0_SEG1 0x00000014
+#define NBIO_BASE__INST0_SEG2 0x00000D20
+#define NBIO_BASE__INST0_SEG3 0x00010400
+#define NBIO_BASE__INST0_SEG4 0
+
+#define NBIO_BASE__INST1_SEG0 0
+#define NBIO_BASE__INST1_SEG1 0
+#define NBIO_BASE__INST1_SEG2 0
+#define NBIO_BASE__INST1_SEG3 0
+#define NBIO_BASE__INST1_SEG4 0
+
+#define NBIO_BASE__INST2_SEG0 0
+#define NBIO_BASE__INST2_SEG1 0
+#define NBIO_BASE__INST2_SEG2 0
+#define NBIO_BASE__INST2_SEG3 0
+#define NBIO_BASE__INST2_SEG4 0
+
+#define NBIO_BASE__INST3_SEG0 0
+#define NBIO_BASE__INST3_SEG1 0
+#define NBIO_BASE__INST3_SEG2 0
+#define NBIO_BASE__INST3_SEG3 0
+#define NBIO_BASE__INST3_SEG4 0
+
+#define NBIO_BASE__INST4_SEG0 0
+#define NBIO_BASE__INST4_SEG1 0
+#define NBIO_BASE__INST4_SEG2 0
+#define NBIO_BASE__INST4_SEG3 0
+#define NBIO_BASE__INST4_SEG4 0
+
+#define DCE_BASE__INST0_SEG0 0x00000012
+#define DCE_BASE__INST0_SEG1 0x000000C0
+#define DCE_BASE__INST0_SEG2 0x000034C0
+#define DCE_BASE__INST0_SEG3 0
+#define DCE_BASE__INST0_SEG4 0
+
+#define DCE_BASE__INST1_SEG0 0
+#define DCE_BASE__INST1_SEG1 0
+#define DCE_BASE__INST1_SEG2 0
+#define DCE_BASE__INST1_SEG3 0
+#define DCE_BASE__INST1_SEG4 0
+
+#define DCE_BASE__INST2_SEG0 0
+#define DCE_BASE__INST2_SEG1 0
+#define DCE_BASE__INST2_SEG2 0
+#define DCE_BASE__INST2_SEG3 0
+#define DCE_BASE__INST2_SEG4 0
+
+#define DCE_BASE__INST3_SEG0 0
+#define DCE_BASE__INST3_SEG1 0
+#define DCE_BASE__INST3_SEG2 0
+#define DCE_BASE__INST3_SEG3 0
+#define DCE_BASE__INST3_SEG4 0
+
+#define DCE_BASE__INST4_SEG0 0
+#define DCE_BASE__INST4_SEG1 0
+#define DCE_BASE__INST4_SEG2 0
+#define DCE_BASE__INST4_SEG3 0
+#define DCE_BASE__INST4_SEG4 0
+
+#define DCN_BASE__INST0_SEG0 0x00000012
+#define DCN_BASE__INST0_SEG1 0x000000C0
+#define DCN_BASE__INST0_SEG2 0x000034C0
+#define DCN_BASE__INST0_SEG3 0
+#define DCN_BASE__INST0_SEG4 0
+
+#define DCN_BASE__INST1_SEG0 0
+#define DCN_BASE__INST1_SEG1 0
+#define DCN_BASE__INST1_SEG2 0
+#define DCN_BASE__INST1_SEG3 0
+#define DCN_BASE__INST1_SEG4 0
+
+#define DCN_BASE__INST2_SEG0 0
+#define DCN_BASE__INST2_SEG1 0
+#define DCN_BASE__INST2_SEG2 0
+#define DCN_BASE__INST2_SEG3 0
+#define DCN_BASE__INST2_SEG4 0
+
+#define DCN_BASE__INST3_SEG0 0
+#define DCN_BASE__INST3_SEG1 0
+#define DCN_BASE__INST3_SEG2 0
+#define DCN_BASE__INST3_SEG3 0
+#define DCN_BASE__INST3_SEG4 0
+
+#define DCN_BASE__INST4_SEG0 0
+#define DCN_BASE__INST4_SEG1 0
+#define DCN_BASE__INST4_SEG2 0
+#define DCN_BASE__INST4_SEG3 0
+#define DCN_BASE__INST4_SEG4 0
+
+#define MP0_BASE__INST0_SEG0 0x00016000
+#define MP0_BASE__INST0_SEG1 0
+#define MP0_BASE__INST0_SEG2 0
+#define MP0_BASE__INST0_SEG3 0
+#define MP0_BASE__INST0_SEG4 0
+
+#define MP0_BASE__INST1_SEG0 0
+#define MP0_BASE__INST1_SEG1 0
+#define MP0_BASE__INST1_SEG2 0
+#define MP0_BASE__INST1_SEG3 0
+#define MP0_BASE__INST1_SEG4 0
+
+#define MP0_BASE__INST2_SEG0 0
+#define MP0_BASE__INST2_SEG1 0
+#define MP0_BASE__INST2_SEG2 0
+#define MP0_BASE__INST2_SEG3 0
+#define MP0_BASE__INST2_SEG4 0
+
+#define MP0_BASE__INST3_SEG0 0
+#define MP0_BASE__INST3_SEG1 0
+#define MP0_BASE__INST3_SEG2 0
+#define MP0_BASE__INST3_SEG3 0
+#define MP0_BASE__INST3_SEG4 0
+
+#define MP0_BASE__INST4_SEG0 0
+#define MP0_BASE__INST4_SEG1 0
+#define MP0_BASE__INST4_SEG2 0
+#define MP0_BASE__INST4_SEG3 0
+#define MP0_BASE__INST4_SEG4 0
+
+#define MP1_BASE__INST0_SEG0 0x00016200
+#define MP1_BASE__INST0_SEG1 0
+#define MP1_BASE__INST0_SEG2 0
+#define MP1_BASE__INST0_SEG3 0
+#define MP1_BASE__INST0_SEG4 0
+
+#define MP1_BASE__INST1_SEG0 0
+#define MP1_BASE__INST1_SEG1 0
+#define MP1_BASE__INST1_SEG2 0
+#define MP1_BASE__INST1_SEG3 0
+#define MP1_BASE__INST1_SEG4 0
+
+#define MP1_BASE__INST2_SEG0 0
+#define MP1_BASE__INST2_SEG1 0
+#define MP1_BASE__INST2_SEG2 0
+#define MP1_BASE__INST2_SEG3 0
+#define MP1_BASE__INST2_SEG4 0
+
+#define MP1_BASE__INST3_SEG0 0
+#define MP1_BASE__INST3_SEG1 0
+#define MP1_BASE__INST3_SEG2 0
+#define MP1_BASE__INST3_SEG3 0
+#define MP1_BASE__INST3_SEG4 0
+
+#define MP1_BASE__INST4_SEG0 0
+#define MP1_BASE__INST4_SEG1 0
+#define MP1_BASE__INST4_SEG2 0
+#define MP1_BASE__INST4_SEG3 0
+#define MP1_BASE__INST4_SEG4 0
+
+#define MP2_BASE__INST0_SEG0 0x00016400
+#define MP2_BASE__INST0_SEG1 0
+#define MP2_BASE__INST0_SEG2 0
+#define MP2_BASE__INST0_SEG3 0
+#define MP2_BASE__INST0_SEG4 0
+
+#define MP2_BASE__INST1_SEG0 0
+#define MP2_BASE__INST1_SEG1 0
+#define MP2_BASE__INST1_SEG2 0
+#define MP2_BASE__INST1_SEG3 0
+#define MP2_BASE__INST1_SEG4 0
+
+#define MP2_BASE__INST2_SEG0 0
+#define MP2_BASE__INST2_SEG1 0
+#define MP2_BASE__INST2_SEG2 0
+#define MP2_BASE__INST2_SEG3 0
+#define MP2_BASE__INST2_SEG4 0
+
+#define MP2_BASE__INST3_SEG0 0
+#define MP2_BASE__INST3_SEG1 0
+#define MP2_BASE__INST3_SEG2 0
+#define MP2_BASE__INST3_SEG3 0
+#define MP2_BASE__INST3_SEG4 0
+
+#define MP2_BASE__INST4_SEG0 0
+#define MP2_BASE__INST4_SEG1 0
+#define MP2_BASE__INST4_SEG2 0
+#define MP2_BASE__INST4_SEG3 0
+#define MP2_BASE__INST4_SEG4 0
+
+#define DF_BASE__INST0_SEG0 0x00007000
+#define DF_BASE__INST0_SEG1 0
+#define DF_BASE__INST0_SEG2 0
+#define DF_BASE__INST0_SEG3 0
+#define DF_BASE__INST0_SEG4 0
+
+#define DF_BASE__INST1_SEG0 0
+#define DF_BASE__INST1_SEG1 0
+#define DF_BASE__INST1_SEG2 0
+#define DF_BASE__INST1_SEG3 0
+#define DF_BASE__INST1_SEG4 0
+
+#define DF_BASE__INST2_SEG0 0
+#define DF_BASE__INST2_SEG1 0
+#define DF_BASE__INST2_SEG2 0
+#define DF_BASE__INST2_SEG3 0
+#define DF_BASE__INST2_SEG4 0
+
+#define DF_BASE__INST3_SEG0 0
+#define DF_BASE__INST3_SEG1 0
+#define DF_BASE__INST3_SEG2 0
+#define DF_BASE__INST3_SEG3 0
+#define DF_BASE__INST3_SEG4 0
+
+#define DF_BASE__INST4_SEG0 0
+#define DF_BASE__INST4_SEG1 0
+#define DF_BASE__INST4_SEG2 0
+#define DF_BASE__INST4_SEG3 0
+#define DF_BASE__INST4_SEG4 0
+
+#define UVD_BASE__INST0_SEG0 0x00007800
+#define UVD_BASE__INST0_SEG1 0x00007E00
+#define UVD_BASE__INST0_SEG2 0
+#define UVD_BASE__INST0_SEG3 0
+#define UVD_BASE__INST0_SEG4 0
+
+#define UVD_BASE__INST1_SEG0 0
+#define UVD_BASE__INST1_SEG1 0
+#define UVD_BASE__INST1_SEG2 0
+#define UVD_BASE__INST1_SEG3 0
+#define UVD_BASE__INST1_SEG4 0
+
+#define UVD_BASE__INST2_SEG0 0
+#define UVD_BASE__INST2_SEG1 0
+#define UVD_BASE__INST2_SEG2 0
+#define UVD_BASE__INST2_SEG3 0
+#define UVD_BASE__INST2_SEG4 0
+
+#define UVD_BASE__INST3_SEG0 0
+#define UVD_BASE__INST3_SEG1 0
+#define UVD_BASE__INST3_SEG2 0
+#define UVD_BASE__INST3_SEG3 0
+#define UVD_BASE__INST3_SEG4 0
+
+#define UVD_BASE__INST4_SEG0 0
+#define UVD_BASE__INST4_SEG1 0
+#define UVD_BASE__INST4_SEG2 0
+#define UVD_BASE__INST4_SEG3 0
+#define UVD_BASE__INST4_SEG4 0
+
+#define VCN_BASE__INST0_SEG0 0x00007800
+#define VCN_BASE__INST0_SEG1 0x00007E00
+#define VCN_BASE__INST0_SEG2 0
+#define VCN_BASE__INST0_SEG3 0
+#define VCN_BASE__INST0_SEG4 0
+
+#define VCN_BASE__INST1_SEG0 0
+#define VCN_BASE__INST1_SEG1 0
+#define VCN_BASE__INST1_SEG2 0
+#define VCN_BASE__INST1_SEG3 0
+#define VCN_BASE__INST1_SEG4 0
+
+#define VCN_BASE__INST2_SEG0 0
+#define VCN_BASE__INST2_SEG1 0
+#define VCN_BASE__INST2_SEG2 0
+#define VCN_BASE__INST2_SEG3 0
+#define VCN_BASE__INST2_SEG4 0
+
+#define VCN_BASE__INST3_SEG0 0
+#define VCN_BASE__INST3_SEG1 0
+#define VCN_BASE__INST3_SEG2 0
+#define VCN_BASE__INST3_SEG3 0
+#define VCN_BASE__INST3_SEG4 0
+
+#define VCN_BASE__INST4_SEG0 0
+#define VCN_BASE__INST4_SEG1 0
+#define VCN_BASE__INST4_SEG2 0
+#define VCN_BASE__INST4_SEG3 0
+#define VCN_BASE__INST4_SEG4 0
+
+#define DBGU_BASE__INST0_SEG0 0x00000180
+#define DBGU_BASE__INST0_SEG1 0x000001A0
+#define DBGU_BASE__INST0_SEG2 0
+#define DBGU_BASE__INST0_SEG3 0
+#define DBGU_BASE__INST0_SEG4 0
+
+#define DBGU_BASE__INST1_SEG0 0
+#define DBGU_BASE__INST1_SEG1 0
+#define DBGU_BASE__INST1_SEG2 0
+#define DBGU_BASE__INST1_SEG3 0
+#define DBGU_BASE__INST1_SEG4 0
+
+#define DBGU_BASE__INST2_SEG0 0
+#define DBGU_BASE__INST2_SEG1 0
+#define DBGU_BASE__INST2_SEG2 0
+#define DBGU_BASE__INST2_SEG3 0
+#define DBGU_BASE__INST2_SEG4 0
+
+#define DBGU_BASE__INST3_SEG0 0
+#define DBGU_BASE__INST3_SEG1 0
+#define DBGU_BASE__INST3_SEG2 0
+#define DBGU_BASE__INST3_SEG3 0
+#define DBGU_BASE__INST3_SEG4 0
+
+#define DBGU_BASE__INST4_SEG0 0
+#define DBGU_BASE__INST4_SEG1 0
+#define DBGU_BASE__INST4_SEG2 0
+#define DBGU_BASE__INST4_SEG3 0
+#define DBGU_BASE__INST4_SEG4 0
+
+#define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0
+#define DBGU_NBIO_BASE__INST0_SEG1 0
+#define DBGU_NBIO_BASE__INST0_SEG2 0
+#define DBGU_NBIO_BASE__INST0_SEG3 0
+#define DBGU_NBIO_BASE__INST0_SEG4 0
+
+#define DBGU_NBIO_BASE__INST1_SEG0 0
+#define DBGU_NBIO_BASE__INST1_SEG1 0
+#define DBGU_NBIO_BASE__INST1_SEG2 0
+#define DBGU_NBIO_BASE__INST1_SEG3 0
+#define DBGU_NBIO_BASE__INST1_SEG4 0
+
+#define DBGU_NBIO_BASE__INST2_SEG0 0
+#define DBGU_NBIO_BASE__INST2_SEG1 0
+#define DBGU_NBIO_BASE__INST2_SEG2 0
+#define DBGU_NBIO_BASE__INST2_SEG3 0
+#define DBGU_NBIO_BASE__INST2_SEG4 0
+
+#define DBGU_NBIO_BASE__INST3_SEG0 0
+#define DBGU_NBIO_BASE__INST3_SEG1 0
+#define DBGU_NBIO_BASE__INST3_SEG2 0
+#define DBGU_NBIO_BASE__INST3_SEG3 0
+#define DBGU_NBIO_BASE__INST3_SEG4 0
+
+#define DBGU_NBIO_BASE__INST4_SEG0 0
+#define DBGU_NBIO_BASE__INST4_SEG1 0
+#define DBGU_NBIO_BASE__INST4_SEG2 0
+#define DBGU_NBIO_BASE__INST4_SEG3 0
+#define DBGU_NBIO_BASE__INST4_SEG4 0
+
+#define DBGU_IO_BASE__INST0_SEG0 0x000001E0
+#define DBGU_IO_BASE__INST0_SEG1 0
+#define DBGU_IO_BASE__INST0_SEG2 0
+#define DBGU_IO_BASE__INST0_SEG3 0
+#define DBGU_IO_BASE__INST0_SEG4 0
+
+#define DBGU_IO_BASE__INST1_SEG0 0
+#define DBGU_IO_BASE__INST1_SEG1 0
+#define DBGU_IO_BASE__INST1_SEG2 0
+#define DBGU_IO_BASE__INST1_SEG3 0
+#define DBGU_IO_BASE__INST1_SEG4 0
+
+#define DBGU_IO_BASE__INST2_SEG0 0
+#define DBGU_IO_BASE__INST2_SEG1 0
+#define DBGU_IO_BASE__INST2_SEG2 0
+#define DBGU_IO_BASE__INST2_SEG3 0
+#define DBGU_IO_BASE__INST2_SEG4 0
+
+#define DBGU_IO_BASE__INST3_SEG0 0
+#define DBGU_IO_BASE__INST3_SEG1 0
+#define DBGU_IO_BASE__INST3_SEG2 0
+#define DBGU_IO_BASE__INST3_SEG3 0
+#define DBGU_IO_BASE__INST3_SEG4 0
+
+#define DBGU_IO_BASE__INST4_SEG0 0
+#define DBGU_IO_BASE__INST4_SEG1 0
+#define DBGU_IO_BASE__INST4_SEG2 0
+#define DBGU_IO_BASE__INST4_SEG3 0
+#define DBGU_IO_BASE__INST4_SEG4 0
+
+#define DFX_DAP_BASE__INST0_SEG0 0x000005A0
+#define DFX_DAP_BASE__INST0_SEG1 0
+#define DFX_DAP_BASE__INST0_SEG2 0
+#define DFX_DAP_BASE__INST0_SEG3 0
+#define DFX_DAP_BASE__INST0_SEG4 0
+
+#define DFX_DAP_BASE__INST1_SEG0 0
+#define DFX_DAP_BASE__INST1_SEG1 0
+#define DFX_DAP_BASE__INST1_SEG2 0
+#define DFX_DAP_BASE__INST1_SEG3 0
+#define DFX_DAP_BASE__INST1_SEG4 0
+
+#define DFX_DAP_BASE__INST2_SEG0 0
+#define DFX_DAP_BASE__INST2_SEG1 0
+#define DFX_DAP_BASE__INST2_SEG2 0
+#define DFX_DAP_BASE__INST2_SEG3 0
+#define DFX_DAP_BASE__INST2_SEG4 0
+
+#define DFX_DAP_BASE__INST3_SEG0 0
+#define DFX_DAP_BASE__INST3_SEG1 0
+#define DFX_DAP_BASE__INST3_SEG2 0
+#define DFX_DAP_BASE__INST3_SEG3 0
+#define DFX_DAP_BASE__INST3_SEG4 0
+
+#define DFX_DAP_BASE__INST4_SEG0 0
+#define DFX_DAP_BASE__INST4_SEG1 0
+#define DFX_DAP_BASE__INST4_SEG2 0
+#define DFX_DAP_BASE__INST4_SEG3 0
+#define DFX_DAP_BASE__INST4_SEG4 0
+
+#define DFX_BASE__INST0_SEG0 0x00000580
+#define DFX_BASE__INST0_SEG1 0
+#define DFX_BASE__INST0_SEG2 0
+#define DFX_BASE__INST0_SEG3 0
+#define DFX_BASE__INST0_SEG4 0
+
+#define DFX_BASE__INST1_SEG0 0
+#define DFX_BASE__INST1_SEG1 0
+#define DFX_BASE__INST1_SEG2 0
+#define DFX_BASE__INST1_SEG3 0
+#define DFX_BASE__INST1_SEG4 0
+
+#define DFX_BASE__INST2_SEG0 0
+#define DFX_BASE__INST2_SEG1 0
+#define DFX_BASE__INST2_SEG2 0
+#define DFX_BASE__INST2_SEG3 0
+#define DFX_BASE__INST2_SEG4 0
+
+#define DFX_BASE__INST3_SEG0 0
+#define DFX_BASE__INST3_SEG1 0
+#define DFX_BASE__INST3_SEG2 0
+#define DFX_BASE__INST3_SEG3 0
+#define DFX_BASE__INST3_SEG4 0
+
+#define DFX_BASE__INST4_SEG0 0
+#define DFX_BASE__INST4_SEG1 0
+#define DFX_BASE__INST4_SEG2 0
+#define DFX_BASE__INST4_SEG3 0
+#define DFX_BASE__INST4_SEG4 0
+
+#define ISP_BASE__INST0_SEG0 0x00018000
+#define ISP_BASE__INST0_SEG1 0
+#define ISP_BASE__INST0_SEG2 0
+#define ISP_BASE__INST0_SEG3 0
+#define ISP_BASE__INST0_SEG4 0
+
+#define ISP_BASE__INST1_SEG0 0
+#define ISP_BASE__INST1_SEG1 0
+#define ISP_BASE__INST1_SEG2 0
+#define ISP_BASE__INST1_SEG3 0
+#define ISP_BASE__INST1_SEG4 0
+
+#define ISP_BASE__INST2_SEG0 0
+#define ISP_BASE__INST2_SEG1 0
+#define ISP_BASE__INST2_SEG2 0
+#define ISP_BASE__INST2_SEG3 0
+#define ISP_BASE__INST2_SEG4 0
+
+#define ISP_BASE__INST3_SEG0 0
+#define ISP_BASE__INST3_SEG1 0
+#define ISP_BASE__INST3_SEG2 0
+#define ISP_BASE__INST3_SEG3 0
+#define ISP_BASE__INST3_SEG4 0
+
+#define ISP_BASE__INST4_SEG0 0
+#define ISP_BASE__INST4_SEG1 0
+#define ISP_BASE__INST4_SEG2 0
+#define ISP_BASE__INST4_SEG3 0
+#define ISP_BASE__INST4_SEG4 0
+
+#define SYSTEMHUB_BASE__INST0_SEG0 0x00000EA0
+#define SYSTEMHUB_BASE__INST0_SEG1 0
+#define SYSTEMHUB_BASE__INST0_SEG2 0
+#define SYSTEMHUB_BASE__INST0_SEG3 0
+#define SYSTEMHUB_BASE__INST0_SEG4 0
+
+#define SYSTEMHUB_BASE__INST1_SEG0 0
+#define SYSTEMHUB_BASE__INST1_SEG1 0
+#define SYSTEMHUB_BASE__INST1_SEG2 0
+#define SYSTEMHUB_BASE__INST1_SEG3 0
+#define SYSTEMHUB_BASE__INST1_SEG4 0
+
+#define SYSTEMHUB_BASE__INST2_SEG0 0
+#define SYSTEMHUB_BASE__INST2_SEG1 0
+#define SYSTEMHUB_BASE__INST2_SEG2 0
+#define SYSTEMHUB_BASE__INST2_SEG3 0
+#define SYSTEMHUB_BASE__INST2_SEG4 0
+
+#define SYSTEMHUB_BASE__INST3_SEG0 0
+#define SYSTEMHUB_BASE__INST3_SEG1 0
+#define SYSTEMHUB_BASE__INST3_SEG2 0
+#define SYSTEMHUB_BASE__INST3_SEG3 0
+#define SYSTEMHUB_BASE__INST3_SEG4 0
+
+#define SYSTEMHUB_BASE__INST4_SEG0 0
+#define SYSTEMHUB_BASE__INST4_SEG1 0
+#define SYSTEMHUB_BASE__INST4_SEG2 0
+#define SYSTEMHUB_BASE__INST4_SEG3 0
+#define SYSTEMHUB_BASE__INST4_SEG4 0
+
+#define L2IMU_BASE__INST0_SEG0 0x00007DC0
+#define L2IMU_BASE__INST0_SEG1 0
+#define L2IMU_BASE__INST0_SEG2 0
+#define L2IMU_BASE__INST0_SEG3 0
+#define L2IMU_BASE__INST0_SEG4 0
+
+#define L2IMU_BASE__INST1_SEG0 0
+#define L2IMU_BASE__INST1_SEG1 0
+#define L2IMU_BASE__INST1_SEG2 0
+#define L2IMU_BASE__INST1_SEG3 0
+#define L2IMU_BASE__INST1_SEG4 0
+
+#define L2IMU_BASE__INST2_SEG0 0
+#define L2IMU_BASE__INST2_SEG1 0
+#define L2IMU_BASE__INST2_SEG2 0
+#define L2IMU_BASE__INST2_SEG3 0
+#define L2IMU_BASE__INST2_SEG4 0
+
+#define L2IMU_BASE__INST3_SEG0 0
+#define L2IMU_BASE__INST3_SEG1 0
+#define L2IMU_BASE__INST3_SEG2 0
+#define L2IMU_BASE__INST3_SEG3 0
+#define L2IMU_BASE__INST3_SEG4 0
+
+#define L2IMU_BASE__INST4_SEG0 0
+#define L2IMU_BASE__INST4_SEG1 0
+#define L2IMU_BASE__INST4_SEG2 0
+#define L2IMU_BASE__INST4_SEG3 0
+#define L2IMU_BASE__INST4_SEG4 0
+
+#define IOHC_BASE__INST0_SEG0 0x00010000
+#define IOHC_BASE__INST0_SEG1 0
+#define IOHC_BASE__INST0_SEG2 0
+#define IOHC_BASE__INST0_SEG3 0
+#define IOHC_BASE__INST0_SEG4 0
+
+#define IOHC_BASE__INST1_SEG0 0
+#define IOHC_BASE__INST1_SEG1 0
+#define IOHC_BASE__INST1_SEG2 0
+#define IOHC_BASE__INST1_SEG3 0
+#define IOHC_BASE__INST1_SEG4 0
+
+#define IOHC_BASE__INST2_SEG0 0
+#define IOHC_BASE__INST2_SEG1 0
+#define IOHC_BASE__INST2_SEG2 0
+#define IOHC_BASE__INST2_SEG3 0
+#define IOHC_BASE__INST2_SEG4 0
+
+#define IOHC_BASE__INST3_SEG0 0
+#define IOHC_BASE__INST3_SEG1 0
+#define IOHC_BASE__INST3_SEG2 0
+#define IOHC_BASE__INST3_SEG3 0
+#define IOHC_BASE__INST3_SEG4 0
+
+#define IOHC_BASE__INST4_SEG0 0
+#define IOHC_BASE__INST4_SEG1 0
+#define IOHC_BASE__INST4_SEG2 0
+#define IOHC_BASE__INST4_SEG3 0
+#define IOHC_BASE__INST4_SEG4 0
+
+#define ATHUB_BASE__INST0_SEG0 0x00000C20
+#define ATHUB_BASE__INST0_SEG1 0
+#define ATHUB_BASE__INST0_SEG2 0
+#define ATHUB_BASE__INST0_SEG3 0
+#define ATHUB_BASE__INST0_SEG4 0
+
+#define ATHUB_BASE__INST1_SEG0 0
+#define ATHUB_BASE__INST1_SEG1 0
+#define ATHUB_BASE__INST1_SEG2 0
+#define ATHUB_BASE__INST1_SEG3 0
+#define ATHUB_BASE__INST1_SEG4 0
+
+#define ATHUB_BASE__INST2_SEG0 0
+#define ATHUB_BASE__INST2_SEG1 0
+#define ATHUB_BASE__INST2_SEG2 0
+#define ATHUB_BASE__INST2_SEG3 0
+#define ATHUB_BASE__INST2_SEG4 0
+
+#define ATHUB_BASE__INST3_SEG0 0
+#define ATHUB_BASE__INST3_SEG1 0
+#define ATHUB_BASE__INST3_SEG2 0
+#define ATHUB_BASE__INST3_SEG3 0
+#define ATHUB_BASE__INST3_SEG4 0
+
+#define ATHUB_BASE__INST4_SEG0 0
+#define ATHUB_BASE__INST4_SEG1 0
+#define ATHUB_BASE__INST4_SEG2 0
+#define ATHUB_BASE__INST4_SEG3 0
+#define ATHUB_BASE__INST4_SEG4 0
+
+#define VCE_BASE__INST0_SEG0 0x00007E00
+#define VCE_BASE__INST0_SEG1 0x00048800
+#define VCE_BASE__INST0_SEG2 0
+#define VCE_BASE__INST0_SEG3 0
+#define VCE_BASE__INST0_SEG4 0
+
+#define VCE_BASE__INST1_SEG0 0
+#define VCE_BASE__INST1_SEG1 0
+#define VCE_BASE__INST1_SEG2 0
+#define VCE_BASE__INST1_SEG3 0
+#define VCE_BASE__INST1_SEG4 0
+
+#define VCE_BASE__INST2_SEG0 0
+#define VCE_BASE__INST2_SEG1 0
+#define VCE_BASE__INST2_SEG2 0
+#define VCE_BASE__INST2_SEG3 0
+#define VCE_BASE__INST2_SEG4 0
+
+#define VCE_BASE__INST3_SEG0 0
+#define VCE_BASE__INST3_SEG1 0
+#define VCE_BASE__INST3_SEG2 0
+#define VCE_BASE__INST3_SEG3 0
+#define VCE_BASE__INST3_SEG4 0
+
+#define VCE_BASE__INST4_SEG0 0
+#define VCE_BASE__INST4_SEG1 0
+#define VCE_BASE__INST4_SEG2 0
+#define VCE_BASE__INST4_SEG3 0
+#define VCE_BASE__INST4_SEG4 0
+
+#define GC_BASE__INST0_SEG0 0x00002000
+#define GC_BASE__INST0_SEG1 0x0000A000
+#define GC_BASE__INST0_SEG2 0
+#define GC_BASE__INST0_SEG3 0
+#define GC_BASE__INST0_SEG4 0
+
+#define GC_BASE__INST1_SEG0 0
+#define GC_BASE__INST1_SEG1 0
+#define GC_BASE__INST1_SEG2 0
+#define GC_BASE__INST1_SEG3 0
+#define GC_BASE__INST1_SEG4 0
+
+#define GC_BASE__INST2_SEG0 0
+#define GC_BASE__INST2_SEG1 0
+#define GC_BASE__INST2_SEG2 0
+#define GC_BASE__INST2_SEG3 0
+#define GC_BASE__INST2_SEG4 0
+
+#define GC_BASE__INST3_SEG0 0
+#define GC_BASE__INST3_SEG1 0
+#define GC_BASE__INST3_SEG2 0
+#define GC_BASE__INST3_SEG3 0
+#define GC_BASE__INST3_SEG4 0
+
+#define GC_BASE__INST4_SEG0 0
+#define GC_BASE__INST4_SEG1 0
+#define GC_BASE__INST4_SEG2 0
+#define GC_BASE__INST4_SEG3 0
+#define GC_BASE__INST4_SEG4 0
+
+#define MMHUB_BASE__INST0_SEG0 0x0001A000
+#define MMHUB_BASE__INST0_SEG1 0
+#define MMHUB_BASE__INST0_SEG2 0
+#define MMHUB_BASE__INST0_SEG3 0
+#define MMHUB_BASE__INST0_SEG4 0
+
+#define MMHUB_BASE__INST1_SEG0 0
+#define MMHUB_BASE__INST1_SEG1 0
+#define MMHUB_BASE__INST1_SEG2 0
+#define MMHUB_BASE__INST1_SEG3 0
+#define MMHUB_BASE__INST1_SEG4 0
+
+#define MMHUB_BASE__INST2_SEG0 0
+#define MMHUB_BASE__INST2_SEG1 0
+#define MMHUB_BASE__INST2_SEG2 0
+#define MMHUB_BASE__INST2_SEG3 0
+#define MMHUB_BASE__INST2_SEG4 0
+
+#define MMHUB_BASE__INST3_SEG0 0
+#define MMHUB_BASE__INST3_SEG1 0
+#define MMHUB_BASE__INST3_SEG2 0
+#define MMHUB_BASE__INST3_SEG3 0
+#define MMHUB_BASE__INST3_SEG4 0
+
+#define MMHUB_BASE__INST4_SEG0 0
+#define MMHUB_BASE__INST4_SEG1 0
+#define MMHUB_BASE__INST4_SEG2 0
+#define MMHUB_BASE__INST4_SEG3 0
+#define MMHUB_BASE__INST4_SEG4 0
+
+#define RSMU_BASE__INST0_SEG0 0x00012000
+#define RSMU_BASE__INST0_SEG1 0
+#define RSMU_BASE__INST0_SEG2 0
+#define RSMU_BASE__INST0_SEG3 0
+#define RSMU_BASE__INST0_SEG4 0
+
+#define RSMU_BASE__INST1_SEG0 0
+#define RSMU_BASE__INST1_SEG1 0
+#define RSMU_BASE__INST1_SEG2 0
+#define RSMU_BASE__INST1_SEG3 0
+#define RSMU_BASE__INST1_SEG4 0
+
+#define RSMU_BASE__INST2_SEG0 0
+#define RSMU_BASE__INST2_SEG1 0
+#define RSMU_BASE__INST2_SEG2 0
+#define RSMU_BASE__INST2_SEG3 0
+#define RSMU_BASE__INST2_SEG4 0
+
+#define RSMU_BASE__INST3_SEG0 0
+#define RSMU_BASE__INST3_SEG1 0
+#define RSMU_BASE__INST3_SEG2 0
+#define RSMU_BASE__INST3_SEG3 0
+#define RSMU_BASE__INST3_SEG4 0
+
+#define RSMU_BASE__INST4_SEG0 0
+#define RSMU_BASE__INST4_SEG1 0
+#define RSMU_BASE__INST4_SEG2 0
+#define RSMU_BASE__INST4_SEG3 0
+#define RSMU_BASE__INST4_SEG4 0
+
+#define HDP_BASE__INST0_SEG0 0x00000F20
+#define HDP_BASE__INST0_SEG1 0
+#define HDP_BASE__INST0_SEG2 0
+#define HDP_BASE__INST0_SEG3 0
+#define HDP_BASE__INST0_SEG4 0
+
+#define HDP_BASE__INST1_SEG0 0
+#define HDP_BASE__INST1_SEG1 0
+#define HDP_BASE__INST1_SEG2 0
+#define HDP_BASE__INST1_SEG3 0
+#define HDP_BASE__INST1_SEG4 0
+
+#define HDP_BASE__INST2_SEG0 0
+#define HDP_BASE__INST2_SEG1 0
+#define HDP_BASE__INST2_SEG2 0
+#define HDP_BASE__INST2_SEG3 0
+#define HDP_BASE__INST2_SEG4 0
+
+#define HDP_BASE__INST3_SEG0 0
+#define HDP_BASE__INST3_SEG1 0
+#define HDP_BASE__INST3_SEG2 0
+#define HDP_BASE__INST3_SEG3 0
+#define HDP_BASE__INST3_SEG4 0
+
+#define HDP_BASE__INST4_SEG0 0
+#define HDP_BASE__INST4_SEG1 0
+#define HDP_BASE__INST4_SEG2 0
+#define HDP_BASE__INST4_SEG3 0
+#define HDP_BASE__INST4_SEG4 0
+
+#define OSSSYS_BASE__INST0_SEG0 0x000010A0
+#define OSSSYS_BASE__INST0_SEG1 0
+#define OSSSYS_BASE__INST0_SEG2 0
+#define OSSSYS_BASE__INST0_SEG3 0
+#define OSSSYS_BASE__INST0_SEG4 0
+
+#define OSSSYS_BASE__INST1_SEG0 0
+#define OSSSYS_BASE__INST1_SEG1 0
+#define OSSSYS_BASE__INST1_SEG2 0
+#define OSSSYS_BASE__INST1_SEG3 0
+#define OSSSYS_BASE__INST1_SEG4 0
+
+#define OSSSYS_BASE__INST2_SEG0 0
+#define OSSSYS_BASE__INST2_SEG1 0
+#define OSSSYS_BASE__INST2_SEG2 0
+#define OSSSYS_BASE__INST2_SEG3 0
+#define OSSSYS_BASE__INST2_SEG4 0
+
+#define OSSSYS_BASE__INST3_SEG0 0
+#define OSSSYS_BASE__INST3_SEG1 0
+#define OSSSYS_BASE__INST3_SEG2 0
+#define OSSSYS_BASE__INST3_SEG3 0
+#define OSSSYS_BASE__INST3_SEG4 0
+
+#define OSSSYS_BASE__INST4_SEG0 0
+#define OSSSYS_BASE__INST4_SEG1 0
+#define OSSSYS_BASE__INST4_SEG2 0
+#define OSSSYS_BASE__INST4_SEG3 0
+#define OSSSYS_BASE__INST4_SEG4 0
+
+#define SDMA0_BASE__INST0_SEG0 0x00001260
+#define SDMA0_BASE__INST0_SEG1 0
+#define SDMA0_BASE__INST0_SEG2 0
+#define SDMA0_BASE__INST0_SEG3 0
+#define SDMA0_BASE__INST0_SEG4 0
+
+#define SDMA0_BASE__INST1_SEG0 0
+#define SDMA0_BASE__INST1_SEG1 0
+#define SDMA0_BASE__INST1_SEG2 0
+#define SDMA0_BASE__INST1_SEG3 0
+#define SDMA0_BASE__INST1_SEG4 0
+
+#define SDMA0_BASE__INST2_SEG0 0
+#define SDMA0_BASE__INST2_SEG1 0
+#define SDMA0_BASE__INST2_SEG2 0
+#define SDMA0_BASE__INST2_SEG3 0
+#define SDMA0_BASE__INST2_SEG4 0
+
+#define SDMA0_BASE__INST3_SEG0 0
+#define SDMA0_BASE__INST3_SEG1 0
+#define SDMA0_BASE__INST3_SEG2 0
+#define SDMA0_BASE__INST3_SEG3 0
+#define SDMA0_BASE__INST3_SEG4 0
+
+#define SDMA0_BASE__INST4_SEG0 0
+#define SDMA0_BASE__INST4_SEG1 0
+#define SDMA0_BASE__INST4_SEG2 0
+#define SDMA0_BASE__INST4_SEG3 0
+#define SDMA0_BASE__INST4_SEG4 0
+
+#define SDMA1_BASE__INST0_SEG0 0x00001460
+#define SDMA1_BASE__INST0_SEG1 0
+#define SDMA1_BASE__INST0_SEG2 0
+#define SDMA1_BASE__INST0_SEG3 0
+#define SDMA1_BASE__INST0_SEG4 0
+
+#define SDMA1_BASE__INST1_SEG0 0
+#define SDMA1_BASE__INST1_SEG1 0
+#define SDMA1_BASE__INST1_SEG2 0
+#define SDMA1_BASE__INST1_SEG3 0
+#define SDMA1_BASE__INST1_SEG4 0
+
+#define SDMA1_BASE__INST2_SEG0 0
+#define SDMA1_BASE__INST2_SEG1 0
+#define SDMA1_BASE__INST2_SEG2 0
+#define SDMA1_BASE__INST2_SEG3 0
+#define SDMA1_BASE__INST2_SEG4 0
+
+#define SDMA1_BASE__INST3_SEG0 0
+#define SDMA1_BASE__INST3_SEG1 0
+#define SDMA1_BASE__INST3_SEG2 0
+#define SDMA1_BASE__INST3_SEG3 0
+#define SDMA1_BASE__INST3_SEG4 0
+
+#define SDMA1_BASE__INST4_SEG0 0
+#define SDMA1_BASE__INST4_SEG1 0
+#define SDMA1_BASE__INST4_SEG2 0
+#define SDMA1_BASE__INST4_SEG3 0
+#define SDMA1_BASE__INST4_SEG4 0
+
+#define XDMA_BASE__INST0_SEG0 0x00003400
+#define XDMA_BASE__INST0_SEG1 0
+#define XDMA_BASE__INST0_SEG2 0
+#define XDMA_BASE__INST0_SEG3 0
+#define XDMA_BASE__INST0_SEG4 0
+
+#define XDMA_BASE__INST1_SEG0 0
+#define XDMA_BASE__INST1_SEG1 0
+#define XDMA_BASE__INST1_SEG2 0
+#define XDMA_BASE__INST1_SEG3 0
+#define XDMA_BASE__INST1_SEG4 0
+
+#define XDMA_BASE__INST2_SEG0 0
+#define XDMA_BASE__INST2_SEG1 0
+#define XDMA_BASE__INST2_SEG2 0
+#define XDMA_BASE__INST2_SEG3 0
+#define XDMA_BASE__INST2_SEG4 0
+
+#define XDMA_BASE__INST3_SEG0 0
+#define XDMA_BASE__INST3_SEG1 0
+#define XDMA_BASE__INST3_SEG2 0
+#define XDMA_BASE__INST3_SEG3 0
+#define XDMA_BASE__INST3_SEG4 0
+
+#define XDMA_BASE__INST4_SEG0 0
+#define XDMA_BASE__INST4_SEG1 0
+#define XDMA_BASE__INST4_SEG2 0
+#define XDMA_BASE__INST4_SEG3 0
+#define XDMA_BASE__INST4_SEG4 0
+
+#define UMC_BASE__INST0_SEG0 0x00014000
+#define UMC_BASE__INST0_SEG1 0
+#define UMC_BASE__INST0_SEG2 0
+#define UMC_BASE__INST0_SEG3 0
+#define UMC_BASE__INST0_SEG4 0
+
+#define UMC_BASE__INST1_SEG0 0
+#define UMC_BASE__INST1_SEG1 0
+#define UMC_BASE__INST1_SEG2 0
+#define UMC_BASE__INST1_SEG3 0
+#define UMC_BASE__INST1_SEG4 0
+
+#define UMC_BASE__INST2_SEG0 0
+#define UMC_BASE__INST2_SEG1 0
+#define UMC_BASE__INST2_SEG2 0
+#define UMC_BASE__INST2_SEG3 0
+#define UMC_BASE__INST2_SEG4 0
+
+#define UMC_BASE__INST3_SEG0 0
+#define UMC_BASE__INST3_SEG1 0
+#define UMC_BASE__INST3_SEG2 0
+#define UMC_BASE__INST3_SEG3 0
+#define UMC_BASE__INST3_SEG4 0
+
+#define UMC_BASE__INST4_SEG0 0
+#define UMC_BASE__INST4_SEG1 0
+#define UMC_BASE__INST4_SEG2 0
+#define UMC_BASE__INST4_SEG3 0
+#define UMC_BASE__INST4_SEG4 0
+
+#define THM_BASE__INST0_SEG0 0x00016600
+#define THM_BASE__INST0_SEG1 0
+#define THM_BASE__INST0_SEG2 0
+#define THM_BASE__INST0_SEG3 0
+#define THM_BASE__INST0_SEG4 0
+
+#define THM_BASE__INST1_SEG0 0
+#define THM_BASE__INST1_SEG1 0
+#define THM_BASE__INST1_SEG2 0
+#define THM_BASE__INST1_SEG3 0
+#define THM_BASE__INST1_SEG4 0
+
+#define THM_BASE__INST2_SEG0 0
+#define THM_BASE__INST2_SEG1 0
+#define THM_BASE__INST2_SEG2 0
+#define THM_BASE__INST2_SEG3 0
+#define THM_BASE__INST2_SEG4 0
+
+#define THM_BASE__INST3_SEG0 0
+#define THM_BASE__INST3_SEG1 0
+#define THM_BASE__INST3_SEG2 0
+#define THM_BASE__INST3_SEG3 0
+#define THM_BASE__INST3_SEG4 0
+
+#define THM_BASE__INST4_SEG0 0
+#define THM_BASE__INST4_SEG1 0
+#define THM_BASE__INST4_SEG2 0
+#define THM_BASE__INST4_SEG3 0
+#define THM_BASE__INST4_SEG4 0
+
+#define SMUIO_BASE__INST0_SEG0 0x00016800
+#define SMUIO_BASE__INST0_SEG1 0
+#define SMUIO_BASE__INST0_SEG2 0
+#define SMUIO_BASE__INST0_SEG3 0
+#define SMUIO_BASE__INST0_SEG4 0
+
+#define SMUIO_BASE__INST1_SEG0 0
+#define SMUIO_BASE__INST1_SEG1 0
+#define SMUIO_BASE__INST1_SEG2 0
+#define SMUIO_BASE__INST1_SEG3 0
+#define SMUIO_BASE__INST1_SEG4 0
+
+#define SMUIO_BASE__INST2_SEG0 0
+#define SMUIO_BASE__INST2_SEG1 0
+#define SMUIO_BASE__INST2_SEG2 0
+#define SMUIO_BASE__INST2_SEG3 0
+#define SMUIO_BASE__INST2_SEG4 0
+
+#define SMUIO_BASE__INST3_SEG0 0
+#define SMUIO_BASE__INST3_SEG1 0
+#define SMUIO_BASE__INST3_SEG2 0
+#define SMUIO_BASE__INST3_SEG3 0
+#define SMUIO_BASE__INST3_SEG4 0
+
+#define SMUIO_BASE__INST4_SEG0 0
+#define SMUIO_BASE__INST4_SEG1 0
+#define SMUIO_BASE__INST4_SEG2 0
+#define SMUIO_BASE__INST4_SEG3 0
+#define SMUIO_BASE__INST4_SEG4 0
+
+#define PWR_BASE__INST0_SEG0 0x00016A00
+#define PWR_BASE__INST0_SEG1 0
+#define PWR_BASE__INST0_SEG2 0
+#define PWR_BASE__INST0_SEG3 0
+#define PWR_BASE__INST0_SEG4 0
+
+#define PWR_BASE__INST1_SEG0 0
+#define PWR_BASE__INST1_SEG1 0
+#define PWR_BASE__INST1_SEG2 0
+#define PWR_BASE__INST1_SEG3 0
+#define PWR_BASE__INST1_SEG4 0
+
+#define PWR_BASE__INST2_SEG0 0
+#define PWR_BASE__INST2_SEG1 0
+#define PWR_BASE__INST2_SEG2 0
+#define PWR_BASE__INST2_SEG3 0
+#define PWR_BASE__INST2_SEG4 0
+
+#define PWR_BASE__INST3_SEG0 0
+#define PWR_BASE__INST3_SEG1 0
+#define PWR_BASE__INST3_SEG2 0
+#define PWR_BASE__INST3_SEG3 0
+#define PWR_BASE__INST3_SEG4 0
+
+#define PWR_BASE__INST4_SEG0 0
+#define PWR_BASE__INST4_SEG1 0
+#define PWR_BASE__INST4_SEG2 0
+#define PWR_BASE__INST4_SEG3 0
+#define PWR_BASE__INST4_SEG4 0
+
+#define CLK_BASE__INST0_SEG0 0x00016C00
+#define CLK_BASE__INST0_SEG1 0
+#define CLK_BASE__INST0_SEG2 0
+#define CLK_BASE__INST0_SEG3 0
+#define CLK_BASE__INST0_SEG4 0
+
+#define CLK_BASE__INST1_SEG0 0x00016E00
+#define CLK_BASE__INST1_SEG1 0
+#define CLK_BASE__INST1_SEG2 0
+#define CLK_BASE__INST1_SEG3 0
+#define CLK_BASE__INST1_SEG4 0
+
+#define CLK_BASE__INST2_SEG0 0x00017000
+#define CLK_BASE__INST2_SEG1 0
+#define CLK_BASE__INST2_SEG2 0
+#define CLK_BASE__INST2_SEG3 0
+#define CLK_BASE__INST2_SEG4 0
+
+#define CLK_BASE__INST3_SEG0 0x00017200
+#define CLK_BASE__INST3_SEG1 0
+#define CLK_BASE__INST3_SEG2 0
+#define CLK_BASE__INST3_SEG3 0
+#define CLK_BASE__INST3_SEG4 0
+
+#define CLK_BASE__INST4_SEG0 0x00017E00
+#define CLK_BASE__INST4_SEG1 0
+#define CLK_BASE__INST4_SEG2 0
+#define CLK_BASE__INST4_SEG3 0
+#define CLK_BASE__INST4_SEG4 0
+
+#define FUSE_BASE__INST0_SEG0 0x00017400
+#define FUSE_BASE__INST0_SEG1 0
+#define FUSE_BASE__INST0_SEG2 0
+#define FUSE_BASE__INST0_SEG3 0
+#define FUSE_BASE__INST0_SEG4 0
+
+#define FUSE_BASE__INST1_SEG0 0
+#define FUSE_BASE__INST1_SEG1 0
+#define FUSE_BASE__INST1_SEG2 0
+#define FUSE_BASE__INST1_SEG3 0
+#define FUSE_BASE__INST1_SEG4 0
+
+#define FUSE_BASE__INST2_SEG0 0
+#define FUSE_BASE__INST2_SEG1 0
+#define FUSE_BASE__INST2_SEG2 0
+#define FUSE_BASE__INST2_SEG3 0
+#define FUSE_BASE__INST2_SEG4 0
+
+#define FUSE_BASE__INST3_SEG0 0
+#define FUSE_BASE__INST3_SEG1 0
+#define FUSE_BASE__INST3_SEG2 0
+#define FUSE_BASE__INST3_SEG3 0
+#define FUSE_BASE__INST3_SEG4 0
+
+#define FUSE_BASE__INST4_SEG0 0
+#define FUSE_BASE__INST4_SEG1 0
+#define FUSE_BASE__INST4_SEG2 0
+#define FUSE_BASE__INST4_SEG3 0
+#define FUSE_BASE__INST4_SEG4 0
+
+
+#endif
+
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/vega10_enum.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/vega10_enum.h
new file mode 100644
index 000000000000..c14ba65a2415
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/vega10_enum.h
@@ -0,0 +1,22531 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#if !defined (_vega10_ENUM_HEADER)
+#define _vega10_ENUM_HEADER
+
+#ifndef _DRIVER_BUILD
+#ifndef GL_ZERO
+#define GL__ZERO BLEND_ZERO
+#define GL__ONE BLEND_ONE
+#define GL__SRC_COLOR BLEND_SRC_COLOR
+#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR
+#define GL__DST_COLOR BLEND_DST_COLOR
+#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR
+#define GL__SRC_ALPHA BLEND_SRC_ALPHA
+#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA
+#define GL__DST_ALPHA BLEND_DST_ALPHA
+#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA
+#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE
+#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR
+#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR
+#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA
+#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA
+#endif
+#endif
+
+/*******************************************************
+ * GDS DATA_TYPE Enums
+ *******************************************************/
+
+#ifndef ENUMS_GDS_PERFCOUNT_SELECT_H
+#define ENUMS_GDS_PERFCOUNT_SELECT_H
+typedef enum GDS_PERFCOUNT_SELECT {
+ GDS_PERF_SEL_DS_ADDR_CONFL = 0,
+ GDS_PERF_SEL_DS_BANK_CONFL = 1,
+ GDS_PERF_SEL_WBUF_FLUSH = 2,
+ GDS_PERF_SEL_WR_COMP = 3,
+ GDS_PERF_SEL_WBUF_WR = 4,
+ GDS_PERF_SEL_RBUF_HIT = 5,
+ GDS_PERF_SEL_RBUF_MISS = 6,
+ GDS_PERF_SEL_SE0_SH0_NORET = 7,
+ GDS_PERF_SEL_SE0_SH0_RET = 8,
+ GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9,
+ GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10,
+ GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11,
+ GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12,
+ GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13,
+ GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14,
+ GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15,
+ GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16,
+ GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17,
+ GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18,
+ GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19,
+ GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20,
+ GDS_PERF_SEL_SE0_SH1_NORET = 21,
+ GDS_PERF_SEL_SE0_SH1_RET = 22,
+ GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23,
+ GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24,
+ GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25,
+ GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26,
+ GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27,
+ GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28,
+ GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29,
+ GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30,
+ GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31,
+ GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32,
+ GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33,
+ GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34,
+ GDS_PERF_SEL_SE1_SH0_NORET = 35,
+ GDS_PERF_SEL_SE1_SH0_RET = 36,
+ GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37,
+ GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38,
+ GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39,
+ GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40,
+ GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41,
+ GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42,
+ GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43,
+ GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44,
+ GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45,
+ GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46,
+ GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47,
+ GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48,
+ GDS_PERF_SEL_SE1_SH1_NORET = 49,
+ GDS_PERF_SEL_SE1_SH1_RET = 50,
+ GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51,
+ GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52,
+ GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53,
+ GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54,
+ GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55,
+ GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56,
+ GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57,
+ GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58,
+ GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59,
+ GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60,
+ GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61,
+ GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62,
+ GDS_PERF_SEL_SE2_SH0_NORET = 63,
+ GDS_PERF_SEL_SE2_SH0_RET = 64,
+ GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65,
+ GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66,
+ GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67,
+ GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68,
+ GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69,
+ GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70,
+ GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71,
+ GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72,
+ GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73,
+ GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74,
+ GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75,
+ GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76,
+ GDS_PERF_SEL_SE2_SH1_NORET = 77,
+ GDS_PERF_SEL_SE2_SH1_RET = 78,
+ GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79,
+ GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80,
+ GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81,
+ GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82,
+ GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83,
+ GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84,
+ GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85,
+ GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86,
+ GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87,
+ GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88,
+ GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89,
+ GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90,
+ GDS_PERF_SEL_SE3_SH0_NORET = 91,
+ GDS_PERF_SEL_SE3_SH0_RET = 92,
+ GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93,
+ GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94,
+ GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95,
+ GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96,
+ GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97,
+ GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98,
+ GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99,
+ GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100,
+ GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101,
+ GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102,
+ GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103,
+ GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104,
+ GDS_PERF_SEL_SE3_SH1_NORET = 105,
+ GDS_PERF_SEL_SE3_SH1_RET = 106,
+ GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107,
+ GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108,
+ GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109,
+ GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110,
+ GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111,
+ GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112,
+ GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113,
+ GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114,
+ GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115,
+ GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116,
+ GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117,
+ GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118,
+ GDS_PERF_SEL_GWS_RELEASED = 119,
+ GDS_PERF_SEL_GWS_BYPASS = 120,
+} GDS_PERFCOUNT_SELECT;
+#endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/
+
+/*******************************************************
+ * Chip Enums
+ *******************************************************/
+
+/*
+ * MEM_PWR_FORCE_CTRL enum
+ */
+
+typedef enum MEM_PWR_FORCE_CTRL {
+NO_FORCE_REQUEST = 0x00000000,
+FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
+FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
+FORCE_SHUT_DOWN_REQUEST = 0x00000003,
+} MEM_PWR_FORCE_CTRL;
+
+/*
+ * MEM_PWR_FORCE_CTRL2 enum
+ */
+
+typedef enum MEM_PWR_FORCE_CTRL2 {
+NO_FORCE_REQ = 0x00000000,
+FORCE_LIGHT_SLEEP_REQ = 0x00000001,
+} MEM_PWR_FORCE_CTRL2;
+
+/*
+ * MEM_PWR_DIS_CTRL enum
+ */
+
+typedef enum MEM_PWR_DIS_CTRL {
+ENABLE_MEM_PWR_CTRL = 0x00000000,
+DISABLE_MEM_PWR_CTRL = 0x00000001,
+} MEM_PWR_DIS_CTRL;
+
+/*
+ * MEM_PWR_SEL_CTRL enum
+ */
+
+typedef enum MEM_PWR_SEL_CTRL {
+DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
+DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001,
+DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002,
+} MEM_PWR_SEL_CTRL;
+
+/*
+ * MEM_PWR_SEL_CTRL2 enum
+ */
+
+typedef enum MEM_PWR_SEL_CTRL2 {
+DYNAMIC_DEEP_SLEEP_EN = 0x00000000,
+DYNAMIC_LIGHT_SLEEP_EN = 0x00000001,
+} MEM_PWR_SEL_CTRL2;
+
+/*
+ * RowSize enum
+ */
+
+typedef enum RowSize {
+ADDR_CONFIG_1KB_ROW = 0x00000000,
+ADDR_CONFIG_2KB_ROW = 0x00000001,
+ADDR_CONFIG_4KB_ROW = 0x00000002,
+} RowSize;
+
+/*
+ * SurfaceEndian enum
+ */
+
+typedef enum SurfaceEndian {
+ENDIAN_NONE = 0x00000000,
+ENDIAN_8IN16 = 0x00000001,
+ENDIAN_8IN32 = 0x00000002,
+ENDIAN_8IN64 = 0x00000003,
+} SurfaceEndian;
+
+/*
+ * ArrayMode enum
+ */
+
+typedef enum ArrayMode {
+ARRAY_LINEAR_GENERAL = 0x00000000,
+ARRAY_LINEAR_ALIGNED = 0x00000001,
+ARRAY_1D_TILED_THIN1 = 0x00000002,
+ARRAY_1D_TILED_THICK = 0x00000003,
+ARRAY_2D_TILED_THIN1 = 0x00000004,
+ARRAY_PRT_TILED_THIN1 = 0x00000005,
+ARRAY_PRT_2D_TILED_THIN1 = 0x00000006,
+ARRAY_2D_TILED_THICK = 0x00000007,
+ARRAY_2D_TILED_XTHICK = 0x00000008,
+ARRAY_PRT_TILED_THICK = 0x00000009,
+ARRAY_PRT_2D_TILED_THICK = 0x0000000a,
+ARRAY_PRT_3D_TILED_THIN1 = 0x0000000b,
+ARRAY_3D_TILED_THIN1 = 0x0000000c,
+ARRAY_3D_TILED_THICK = 0x0000000d,
+ARRAY_3D_TILED_XTHICK = 0x0000000e,
+ARRAY_PRT_3D_TILED_THICK = 0x0000000f,
+} ArrayMode;
+
+/*
+ * NumPipes enum
+ */
+
+typedef enum NumPipes {
+ADDR_CONFIG_1_PIPE = 0x00000000,
+ADDR_CONFIG_2_PIPE = 0x00000001,
+ADDR_CONFIG_4_PIPE = 0x00000002,
+ADDR_CONFIG_8_PIPE = 0x00000003,
+ADDR_CONFIG_16_PIPE = 0x00000004,
+ADDR_CONFIG_32_PIPE = 0x00000005,
+} NumPipes;
+
+/*
+ * NumBanksConfig enum
+ */
+
+typedef enum NumBanksConfig {
+ADDR_CONFIG_1_BANK = 0x00000000,
+ADDR_CONFIG_2_BANK = 0x00000001,
+ADDR_CONFIG_4_BANK = 0x00000002,
+ADDR_CONFIG_8_BANK = 0x00000003,
+ADDR_CONFIG_16_BANK = 0x00000004,
+} NumBanksConfig;
+
+/*
+ * PipeInterleaveSize enum
+ */
+
+typedef enum PipeInterleaveSize {
+ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000,
+ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001,
+ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 0x00000002,
+ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 0x00000003,
+} PipeInterleaveSize;
+
+/*
+ * BankInterleaveSize enum
+ */
+
+typedef enum BankInterleaveSize {
+ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000,
+ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001,
+ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002,
+ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003,
+} BankInterleaveSize;
+
+/*
+ * NumShaderEngines enum
+ */
+
+typedef enum NumShaderEngines {
+ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000,
+ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001,
+ADDR_CONFIG_4_SHADER_ENGINE = 0x00000002,
+ADDR_CONFIG_8_SHADER_ENGINE = 0x00000003,
+} NumShaderEngines;
+
+/*
+ * NumRbPerShaderEngine enum
+ */
+
+typedef enum NumRbPerShaderEngine {
+ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0x00000000,
+ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 0x00000001,
+ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 0x00000002,
+} NumRbPerShaderEngine;
+
+/*
+ * NumGPUs enum
+ */
+
+typedef enum NumGPUs {
+ADDR_CONFIG_1_GPU = 0x00000000,
+ADDR_CONFIG_2_GPU = 0x00000001,
+ADDR_CONFIG_4_GPU = 0x00000002,
+ADDR_CONFIG_8_GPU = 0x00000003,
+} NumGPUs;
+
+/*
+ * NumMaxCompressedFragments enum
+ */
+
+typedef enum NumMaxCompressedFragments {
+ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0x00000000,
+ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 0x00000001,
+ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 0x00000002,
+ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 0x00000003,
+} NumMaxCompressedFragments;
+
+/*
+ * ShaderEngineTileSize enum
+ */
+
+typedef enum ShaderEngineTileSize {
+ADDR_CONFIG_SE_TILE_16 = 0x00000000,
+ADDR_CONFIG_SE_TILE_32 = 0x00000001,
+} ShaderEngineTileSize;
+
+/*
+ * MultiGPUTileSize enum
+ */
+
+typedef enum MultiGPUTileSize {
+ADDR_CONFIG_GPU_TILE_16 = 0x00000000,
+ADDR_CONFIG_GPU_TILE_32 = 0x00000001,
+ADDR_CONFIG_GPU_TILE_64 = 0x00000002,
+ADDR_CONFIG_GPU_TILE_128 = 0x00000003,
+} MultiGPUTileSize;
+
+/*
+ * NumLowerPipes enum
+ */
+
+typedef enum NumLowerPipes {
+ADDR_CONFIG_1_LOWER_PIPES = 0x00000000,
+ADDR_CONFIG_2_LOWER_PIPES = 0x00000001,
+} NumLowerPipes;
+
+/*
+ * ColorTransform enum
+ */
+
+typedef enum ColorTransform {
+DCC_CT_AUTO = 0x00000000,
+DCC_CT_NONE = 0x00000001,
+ABGR_TO_A_BG_G_RB = 0x00000002,
+BGRA_TO_BG_G_RB_A = 0x00000003,
+} ColorTransform;
+
+/*
+ * CompareRef enum
+ */
+
+typedef enum CompareRef {
+REF_NEVER = 0x00000000,
+REF_LESS = 0x00000001,
+REF_EQUAL = 0x00000002,
+REF_LEQUAL = 0x00000003,
+REF_GREATER = 0x00000004,
+REF_NOTEQUAL = 0x00000005,
+REF_GEQUAL = 0x00000006,
+REF_ALWAYS = 0x00000007,
+} CompareRef;
+
+/*
+ * ReadSize enum
+ */
+
+typedef enum ReadSize {
+READ_256_BITS = 0x00000000,
+READ_512_BITS = 0x00000001,
+} ReadSize;
+
+/*
+ * DepthFormat enum
+ */
+
+typedef enum DepthFormat {
+DEPTH_INVALID = 0x00000000,
+DEPTH_16 = 0x00000001,
+DEPTH_X8_24 = 0x00000002,
+DEPTH_8_24 = 0x00000003,
+DEPTH_X8_24_FLOAT = 0x00000004,
+DEPTH_8_24_FLOAT = 0x00000005,
+DEPTH_32_FLOAT = 0x00000006,
+DEPTH_X24_8_32_FLOAT = 0x00000007,
+} DepthFormat;
+
+/*
+ * ZFormat enum
+ */
+
+typedef enum ZFormat {
+Z_INVALID = 0x00000000,
+Z_16 = 0x00000001,
+Z_24 = 0x00000002,
+Z_32_FLOAT = 0x00000003,
+} ZFormat;
+
+/*
+ * StencilFormat enum
+ */
+
+typedef enum StencilFormat {
+STENCIL_INVALID = 0x00000000,
+STENCIL_8 = 0x00000001,
+} StencilFormat;
+
+/*
+ * CmaskMode enum
+ */
+
+typedef enum CmaskMode {
+CMASK_CLEAR_NONE = 0x00000000,
+CMASK_CLEAR_ONE = 0x00000001,
+CMASK_CLEAR_ALL = 0x00000002,
+CMASK_ANY_EXPANDED = 0x00000003,
+CMASK_ALPHA0_FRAG1 = 0x00000004,
+CMASK_ALPHA0_FRAG2 = 0x00000005,
+CMASK_ALPHA0_FRAG4 = 0x00000006,
+CMASK_ALPHA0_FRAGS = 0x00000007,
+CMASK_ALPHA1_FRAG1 = 0x00000008,
+CMASK_ALPHA1_FRAG2 = 0x00000009,
+CMASK_ALPHA1_FRAG4 = 0x0000000a,
+CMASK_ALPHA1_FRAGS = 0x0000000b,
+CMASK_ALPHAX_FRAG1 = 0x0000000c,
+CMASK_ALPHAX_FRAG2 = 0x0000000d,
+CMASK_ALPHAX_FRAG4 = 0x0000000e,
+CMASK_ALPHAX_FRAGS = 0x0000000f,
+} CmaskMode;
+
+/*
+ * QuadExportFormat enum
+ */
+
+typedef enum QuadExportFormat {
+EXPORT_UNUSED = 0x00000000,
+EXPORT_32_R = 0x00000001,
+EXPORT_32_GR = 0x00000002,
+EXPORT_32_AR = 0x00000003,
+EXPORT_FP16_ABGR = 0x00000004,
+EXPORT_UNSIGNED16_ABGR = 0x00000005,
+EXPORT_SIGNED16_ABGR = 0x00000006,
+EXPORT_32_ABGR = 0x00000007,
+EXPORT_32BPP_8PIX = 0x00000008,
+EXPORT_16_16_UNSIGNED_8PIX = 0x00000009,
+EXPORT_16_16_SIGNED_8PIX = 0x0000000a,
+EXPORT_16_16_FLOAT_8PIX = 0x0000000b,
+} QuadExportFormat;
+
+/*
+ * QuadExportFormatOld enum
+ */
+
+typedef enum QuadExportFormatOld {
+EXPORT_4P_32BPC_ABGR = 0x00000000,
+EXPORT_4P_16BPC_ABGR = 0x00000001,
+EXPORT_4P_32BPC_GR = 0x00000002,
+EXPORT_4P_32BPC_AR = 0x00000003,
+EXPORT_2P_32BPC_ABGR = 0x00000004,
+EXPORT_8P_32BPC_R = 0x00000005,
+} QuadExportFormatOld;
+
+/*
+ * ColorFormat enum
+ */
+
+typedef enum ColorFormat {
+COLOR_INVALID = 0x00000000,
+COLOR_8 = 0x00000001,
+COLOR_16 = 0x00000002,
+COLOR_8_8 = 0x00000003,
+COLOR_32 = 0x00000004,
+COLOR_16_16 = 0x00000005,
+COLOR_10_11_11 = 0x00000006,
+COLOR_11_11_10 = 0x00000007,
+COLOR_10_10_10_2 = 0x00000008,
+COLOR_2_10_10_10 = 0x00000009,
+COLOR_8_8_8_8 = 0x0000000a,
+COLOR_32_32 = 0x0000000b,
+COLOR_16_16_16_16 = 0x0000000c,
+COLOR_RESERVED_13 = 0x0000000d,
+COLOR_32_32_32_32 = 0x0000000e,
+COLOR_RESERVED_15 = 0x0000000f,
+COLOR_5_6_5 = 0x00000010,
+COLOR_1_5_5_5 = 0x00000011,
+COLOR_5_5_5_1 = 0x00000012,
+COLOR_4_4_4_4 = 0x00000013,
+COLOR_8_24 = 0x00000014,
+COLOR_24_8 = 0x00000015,
+COLOR_X24_8_32_FLOAT = 0x00000016,
+COLOR_RESERVED_23 = 0x00000017,
+COLOR_RESERVED_24 = 0x00000018,
+COLOR_RESERVED_25 = 0x00000019,
+COLOR_RESERVED_26 = 0x0000001a,
+COLOR_RESERVED_27 = 0x0000001b,
+COLOR_RESERVED_28 = 0x0000001c,
+COLOR_RESERVED_29 = 0x0000001d,
+COLOR_RESERVED_30 = 0x0000001e,
+COLOR_2_10_10_10_6E4 = 0x0000001f,
+} ColorFormat;
+
+/*
+ * SurfaceFormat enum
+ */
+
+typedef enum SurfaceFormat {
+FMT_INVALID = 0x00000000,
+FMT_8 = 0x00000001,
+FMT_16 = 0x00000002,
+FMT_8_8 = 0x00000003,
+FMT_32 = 0x00000004,
+FMT_16_16 = 0x00000005,
+FMT_10_11_11 = 0x00000006,
+FMT_11_11_10 = 0x00000007,
+FMT_10_10_10_2 = 0x00000008,
+FMT_2_10_10_10 = 0x00000009,
+FMT_8_8_8_8 = 0x0000000a,
+FMT_32_32 = 0x0000000b,
+FMT_16_16_16_16 = 0x0000000c,
+FMT_32_32_32 = 0x0000000d,
+FMT_32_32_32_32 = 0x0000000e,
+FMT_RESERVED_4 = 0x0000000f,
+FMT_5_6_5 = 0x00000010,
+FMT_1_5_5_5 = 0x00000011,
+FMT_5_5_5_1 = 0x00000012,
+FMT_4_4_4_4 = 0x00000013,
+FMT_8_24 = 0x00000014,
+FMT_24_8 = 0x00000015,
+FMT_X24_8_32_FLOAT = 0x00000016,
+FMT_RESERVED_33 = 0x00000017,
+FMT_11_11_10_FLOAT = 0x00000018,
+FMT_16_FLOAT = 0x00000019,
+FMT_32_FLOAT = 0x0000001a,
+FMT_16_16_FLOAT = 0x0000001b,
+FMT_8_24_FLOAT = 0x0000001c,
+FMT_24_8_FLOAT = 0x0000001d,
+FMT_32_32_FLOAT = 0x0000001e,
+FMT_10_11_11_FLOAT = 0x0000001f,
+FMT_16_16_16_16_FLOAT = 0x00000020,
+FMT_3_3_2 = 0x00000021,
+FMT_6_5_5 = 0x00000022,
+FMT_32_32_32_32_FLOAT = 0x00000023,
+FMT_RESERVED_36 = 0x00000024,
+FMT_1 = 0x00000025,
+FMT_1_REVERSED = 0x00000026,
+FMT_GB_GR = 0x00000027,
+FMT_BG_RG = 0x00000028,
+FMT_32_AS_8 = 0x00000029,
+FMT_32_AS_8_8 = 0x0000002a,
+FMT_5_9_9_9_SHAREDEXP = 0x0000002b,
+FMT_8_8_8 = 0x0000002c,
+FMT_16_16_16 = 0x0000002d,
+FMT_16_16_16_FLOAT = 0x0000002e,
+FMT_4_4 = 0x0000002f,
+FMT_32_32_32_FLOAT = 0x00000030,
+FMT_BC1 = 0x00000031,
+FMT_BC2 = 0x00000032,
+FMT_BC3 = 0x00000033,
+FMT_BC4 = 0x00000034,
+FMT_BC5 = 0x00000035,
+FMT_BC6 = 0x00000036,
+FMT_BC7 = 0x00000037,
+FMT_32_AS_32_32_32_32 = 0x00000038,
+FMT_APC3 = 0x00000039,
+FMT_APC4 = 0x0000003a,
+FMT_APC5 = 0x0000003b,
+FMT_APC6 = 0x0000003c,
+FMT_APC7 = 0x0000003d,
+FMT_CTX1 = 0x0000003e,
+FMT_RESERVED_63 = 0x0000003f,
+} SurfaceFormat;
+
+/*
+ * BUF_DATA_FORMAT enum
+ */
+
+typedef enum BUF_DATA_FORMAT {
+BUF_DATA_FORMAT_INVALID = 0x00000000,
+BUF_DATA_FORMAT_8 = 0x00000001,
+BUF_DATA_FORMAT_16 = 0x00000002,
+BUF_DATA_FORMAT_8_8 = 0x00000003,
+BUF_DATA_FORMAT_32 = 0x00000004,
+BUF_DATA_FORMAT_16_16 = 0x00000005,
+BUF_DATA_FORMAT_10_11_11 = 0x00000006,
+BUF_DATA_FORMAT_11_11_10 = 0x00000007,
+BUF_DATA_FORMAT_10_10_10_2 = 0x00000008,
+BUF_DATA_FORMAT_2_10_10_10 = 0x00000009,
+BUF_DATA_FORMAT_8_8_8_8 = 0x0000000a,
+BUF_DATA_FORMAT_32_32 = 0x0000000b,
+BUF_DATA_FORMAT_16_16_16_16 = 0x0000000c,
+BUF_DATA_FORMAT_32_32_32 = 0x0000000d,
+BUF_DATA_FORMAT_32_32_32_32 = 0x0000000e,
+BUF_DATA_FORMAT_RESERVED_15 = 0x0000000f,
+} BUF_DATA_FORMAT;
+
+/*
+ * IMG_DATA_FORMAT enum
+ */
+
+typedef enum IMG_DATA_FORMAT {
+IMG_DATA_FORMAT_INVALID = 0x00000000,
+IMG_DATA_FORMAT_8 = 0x00000001,
+IMG_DATA_FORMAT_16 = 0x00000002,
+IMG_DATA_FORMAT_8_8 = 0x00000003,
+IMG_DATA_FORMAT_32 = 0x00000004,
+IMG_DATA_FORMAT_16_16 = 0x00000005,
+IMG_DATA_FORMAT_10_11_11 = 0x00000006,
+IMG_DATA_FORMAT_11_11_10 = 0x00000007,
+IMG_DATA_FORMAT_10_10_10_2 = 0x00000008,
+IMG_DATA_FORMAT_2_10_10_10 = 0x00000009,
+IMG_DATA_FORMAT_8_8_8_8 = 0x0000000a,
+IMG_DATA_FORMAT_32_32 = 0x0000000b,
+IMG_DATA_FORMAT_16_16_16_16 = 0x0000000c,
+IMG_DATA_FORMAT_32_32_32 = 0x0000000d,
+IMG_DATA_FORMAT_32_32_32_32 = 0x0000000e,
+IMG_DATA_FORMAT_RESERVED_15 = 0x0000000f,
+IMG_DATA_FORMAT_5_6_5 = 0x00000010,
+IMG_DATA_FORMAT_1_5_5_5 = 0x00000011,
+IMG_DATA_FORMAT_5_5_5_1 = 0x00000012,
+IMG_DATA_FORMAT_4_4_4_4 = 0x00000013,
+IMG_DATA_FORMAT_8_24 = 0x00000014,
+IMG_DATA_FORMAT_24_8 = 0x00000015,
+IMG_DATA_FORMAT_X24_8_32 = 0x00000016,
+IMG_DATA_FORMAT_8_AS_8_8_8_8 = 0x00000017,
+IMG_DATA_FORMAT_ETC2_RGB = 0x00000018,
+IMG_DATA_FORMAT_ETC2_RGBA = 0x00000019,
+IMG_DATA_FORMAT_ETC2_R = 0x0000001a,
+IMG_DATA_FORMAT_ETC2_RG = 0x0000001b,
+IMG_DATA_FORMAT_ETC2_RGBA1 = 0x0000001c,
+IMG_DATA_FORMAT_RESERVED_29 = 0x0000001d,
+IMG_DATA_FORMAT_RESERVED_30 = 0x0000001e,
+IMG_DATA_FORMAT_6E4 = 0x0000001f,
+IMG_DATA_FORMAT_GB_GR = 0x00000020,
+IMG_DATA_FORMAT_BG_RG = 0x00000021,
+IMG_DATA_FORMAT_5_9_9_9 = 0x00000022,
+IMG_DATA_FORMAT_BC1 = 0x00000023,
+IMG_DATA_FORMAT_BC2 = 0x00000024,
+IMG_DATA_FORMAT_BC3 = 0x00000025,
+IMG_DATA_FORMAT_BC4 = 0x00000026,
+IMG_DATA_FORMAT_BC5 = 0x00000027,
+IMG_DATA_FORMAT_BC6 = 0x00000028,
+IMG_DATA_FORMAT_BC7 = 0x00000029,
+IMG_DATA_FORMAT_16_AS_32_32 = 0x0000002a,
+IMG_DATA_FORMAT_16_AS_16_16_16_16 = 0x0000002b,
+IMG_DATA_FORMAT_16_AS_32_32_32_32 = 0x0000002c,
+IMG_DATA_FORMAT_FMASK = 0x0000002d,
+IMG_DATA_FORMAT_ASTC_2D_LDR = 0x0000002e,
+IMG_DATA_FORMAT_ASTC_2D_HDR = 0x0000002f,
+IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB = 0x00000030,
+IMG_DATA_FORMAT_ASTC_3D_LDR = 0x00000031,
+IMG_DATA_FORMAT_ASTC_3D_HDR = 0x00000032,
+IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB = 0x00000033,
+IMG_DATA_FORMAT_N_IN_16 = 0x00000034,
+IMG_DATA_FORMAT_N_IN_16_16 = 0x00000035,
+IMG_DATA_FORMAT_N_IN_16_16_16_16 = 0x00000036,
+IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16 = 0x00000037,
+IMG_DATA_FORMAT_RESERVED_56 = 0x00000038,
+IMG_DATA_FORMAT_4_4 = 0x00000039,
+IMG_DATA_FORMAT_6_5_5 = 0x0000003a,
+IMG_DATA_FORMAT_RESERVED_59 = 0x0000003b,
+IMG_DATA_FORMAT_RESERVED_60 = 0x0000003c,
+IMG_DATA_FORMAT_8_AS_32 = 0x0000003d,
+IMG_DATA_FORMAT_8_AS_32_32 = 0x0000003e,
+IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x0000003f,
+} IMG_DATA_FORMAT;
+
+/*
+ * BUF_NUM_FORMAT enum
+ */
+
+typedef enum BUF_NUM_FORMAT {
+BUF_NUM_FORMAT_UNORM = 0x00000000,
+BUF_NUM_FORMAT_SNORM = 0x00000001,
+BUF_NUM_FORMAT_USCALED = 0x00000002,
+BUF_NUM_FORMAT_SSCALED = 0x00000003,
+BUF_NUM_FORMAT_UINT = 0x00000004,
+BUF_NUM_FORMAT_SINT = 0x00000005,
+BUF_NUM_FORMAT_UNORM_UINT = 0x00000006,
+BUF_NUM_FORMAT_FLOAT = 0x00000007,
+} BUF_NUM_FORMAT;
+
+/*
+ * IMG_NUM_FORMAT enum
+ */
+
+typedef enum IMG_NUM_FORMAT {
+IMG_NUM_FORMAT_UNORM = 0x00000000,
+IMG_NUM_FORMAT_SNORM = 0x00000001,
+IMG_NUM_FORMAT_USCALED = 0x00000002,
+IMG_NUM_FORMAT_SSCALED = 0x00000003,
+IMG_NUM_FORMAT_UINT = 0x00000004,
+IMG_NUM_FORMAT_SINT = 0x00000005,
+IMG_NUM_FORMAT_UNORM_UINT = 0x00000006,
+IMG_NUM_FORMAT_FLOAT = 0x00000007,
+IMG_NUM_FORMAT_RESERVED_8 = 0x00000008,
+IMG_NUM_FORMAT_SRGB = 0x00000009,
+IMG_NUM_FORMAT_RESERVED_10 = 0x0000000a,
+IMG_NUM_FORMAT_RESERVED_11 = 0x0000000b,
+IMG_NUM_FORMAT_RESERVED_12 = 0x0000000c,
+IMG_NUM_FORMAT_RESERVED_13 = 0x0000000d,
+IMG_NUM_FORMAT_RESERVED_14 = 0x0000000e,
+IMG_NUM_FORMAT_RESERVED_15 = 0x0000000f,
+} IMG_NUM_FORMAT;
+
+/*
+ * IMG_NUM_FORMAT_FMASK enum
+ */
+
+typedef enum IMG_NUM_FORMAT_FMASK {
+IMG_NUM_FORMAT_FMASK_8_2_1 = 0x00000000,
+IMG_NUM_FORMAT_FMASK_8_4_1 = 0x00000001,
+IMG_NUM_FORMAT_FMASK_8_8_1 = 0x00000002,
+IMG_NUM_FORMAT_FMASK_8_2_2 = 0x00000003,
+IMG_NUM_FORMAT_FMASK_8_4_2 = 0x00000004,
+IMG_NUM_FORMAT_FMASK_8_4_4 = 0x00000005,
+IMG_NUM_FORMAT_FMASK_16_16_1 = 0x00000006,
+IMG_NUM_FORMAT_FMASK_16_8_2 = 0x00000007,
+IMG_NUM_FORMAT_FMASK_32_16_2 = 0x00000008,
+IMG_NUM_FORMAT_FMASK_32_8_4 = 0x00000009,
+IMG_NUM_FORMAT_FMASK_32_8_8 = 0x0000000a,
+IMG_NUM_FORMAT_FMASK_64_16_4 = 0x0000000b,
+IMG_NUM_FORMAT_FMASK_64_16_8 = 0x0000000c,
+IMG_NUM_FORMAT_FMASK_RESERVED_13 = 0x0000000d,
+IMG_NUM_FORMAT_FMASK_RESERVED_14 = 0x0000000e,
+IMG_NUM_FORMAT_FMASK_RESERVED_15 = 0x0000000f,
+} IMG_NUM_FORMAT_FMASK;
+
+/*
+ * IMG_NUM_FORMAT_N_IN_16 enum
+ */
+
+typedef enum IMG_NUM_FORMAT_N_IN_16 {
+IMG_NUM_FORMAT_N_IN_16_RESERVED_0 = 0x00000000,
+IMG_NUM_FORMAT_N_IN_16_UNORM_10 = 0x00000001,
+IMG_NUM_FORMAT_N_IN_16_UNORM_9 = 0x00000002,
+IMG_NUM_FORMAT_N_IN_16_RESERVED_3 = 0x00000003,
+IMG_NUM_FORMAT_N_IN_16_UINT_10 = 0x00000004,
+IMG_NUM_FORMAT_N_IN_16_UINT_9 = 0x00000005,
+IMG_NUM_FORMAT_N_IN_16_RESERVED_6 = 0x00000006,
+IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10 = 0x00000007,
+IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9 = 0x00000008,
+IMG_NUM_FORMAT_N_IN_16_RESERVED_9 = 0x00000009,
+IMG_NUM_FORMAT_N_IN_16_RESERVED_10 = 0x0000000a,
+IMG_NUM_FORMAT_N_IN_16_RESERVED_11 = 0x0000000b,
+IMG_NUM_FORMAT_N_IN_16_RESERVED_12 = 0x0000000c,
+IMG_NUM_FORMAT_N_IN_16_RESERVED_13 = 0x0000000d,
+IMG_NUM_FORMAT_N_IN_16_RESERVED_14 = 0x0000000e,
+IMG_NUM_FORMAT_N_IN_16_RESERVED_15 = 0x0000000f,
+} IMG_NUM_FORMAT_N_IN_16;
+
+/*
+ * IMG_NUM_FORMAT_ASTC_2D enum
+ */
+
+typedef enum IMG_NUM_FORMAT_ASTC_2D {
+IMG_NUM_FORMAT_ASTC_2D_4x4 = 0x00000000,
+IMG_NUM_FORMAT_ASTC_2D_5x4 = 0x00000001,
+IMG_NUM_FORMAT_ASTC_2D_5x5 = 0x00000002,
+IMG_NUM_FORMAT_ASTC_2D_6x5 = 0x00000003,
+IMG_NUM_FORMAT_ASTC_2D_6x6 = 0x00000004,
+IMG_NUM_FORMAT_ASTC_2D_8x5 = 0x00000005,
+IMG_NUM_FORMAT_ASTC_2D_8x6 = 0x00000006,
+IMG_NUM_FORMAT_ASTC_2D_8x8 = 0x00000007,
+IMG_NUM_FORMAT_ASTC_2D_10x5 = 0x00000008,
+IMG_NUM_FORMAT_ASTC_2D_10x6 = 0x00000009,
+IMG_NUM_FORMAT_ASTC_2D_10x8 = 0x0000000a,
+IMG_NUM_FORMAT_ASTC_2D_10x10 = 0x0000000b,
+IMG_NUM_FORMAT_ASTC_2D_12x10 = 0x0000000c,
+IMG_NUM_FORMAT_ASTC_2D_12x12 = 0x0000000d,
+IMG_NUM_FORMAT_ASTC_2D_RESERVED_14 = 0x0000000e,
+IMG_NUM_FORMAT_ASTC_2D_RESERVED_15 = 0x0000000f,
+} IMG_NUM_FORMAT_ASTC_2D;
+
+/*
+ * IMG_NUM_FORMAT_ASTC_3D enum
+ */
+
+typedef enum IMG_NUM_FORMAT_ASTC_3D {
+IMG_NUM_FORMAT_ASTC_3D_3x3x3 = 0x00000000,
+IMG_NUM_FORMAT_ASTC_3D_4x3x3 = 0x00000001,
+IMG_NUM_FORMAT_ASTC_3D_4x4x3 = 0x00000002,
+IMG_NUM_FORMAT_ASTC_3D_4x4x4 = 0x00000003,
+IMG_NUM_FORMAT_ASTC_3D_5x4x4 = 0x00000004,
+IMG_NUM_FORMAT_ASTC_3D_5x5x4 = 0x00000005,
+IMG_NUM_FORMAT_ASTC_3D_5x5x5 = 0x00000006,
+IMG_NUM_FORMAT_ASTC_3D_6x5x5 = 0x00000007,
+IMG_NUM_FORMAT_ASTC_3D_6x6x5 = 0x00000008,
+IMG_NUM_FORMAT_ASTC_3D_6x6x6 = 0x00000009,
+IMG_NUM_FORMAT_ASTC_3D_RESERVED_10 = 0x0000000a,
+IMG_NUM_FORMAT_ASTC_3D_RESERVED_11 = 0x0000000b,
+IMG_NUM_FORMAT_ASTC_3D_RESERVED_12 = 0x0000000c,
+IMG_NUM_FORMAT_ASTC_3D_RESERVED_13 = 0x0000000d,
+IMG_NUM_FORMAT_ASTC_3D_RESERVED_14 = 0x0000000e,
+IMG_NUM_FORMAT_ASTC_3D_RESERVED_15 = 0x0000000f,
+} IMG_NUM_FORMAT_ASTC_3D;
+
+/*
+ * TileType enum
+ */
+
+typedef enum TileType {
+ARRAY_COLOR_TILE = 0x00000000,
+ARRAY_DEPTH_TILE = 0x00000001,
+} TileType;
+
+/*
+ * NonDispTilingOrder enum
+ */
+
+typedef enum NonDispTilingOrder {
+ADDR_SURF_MICRO_TILING_DISPLAY = 0x00000000,
+ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x00000001,
+} NonDispTilingOrder;
+
+/*
+ * MicroTileMode enum
+ */
+
+typedef enum MicroTileMode {
+ADDR_SURF_DISPLAY_MICRO_TILING = 0x00000000,
+ADDR_SURF_THIN_MICRO_TILING = 0x00000001,
+ADDR_SURF_DEPTH_MICRO_TILING = 0x00000002,
+ADDR_SURF_ROTATED_MICRO_TILING = 0x00000003,
+ADDR_SURF_THICK_MICRO_TILING = 0x00000004,
+} MicroTileMode;
+
+/*
+ * TileSplit enum
+ */
+
+typedef enum TileSplit {
+ADDR_SURF_TILE_SPLIT_64B = 0x00000000,
+ADDR_SURF_TILE_SPLIT_128B = 0x00000001,
+ADDR_SURF_TILE_SPLIT_256B = 0x00000002,
+ADDR_SURF_TILE_SPLIT_512B = 0x00000003,
+ADDR_SURF_TILE_SPLIT_1KB = 0x00000004,
+ADDR_SURF_TILE_SPLIT_2KB = 0x00000005,
+ADDR_SURF_TILE_SPLIT_4KB = 0x00000006,
+} TileSplit;
+
+/*
+ * SampleSplit enum
+ */
+
+typedef enum SampleSplit {
+ADDR_SURF_SAMPLE_SPLIT_1 = 0x00000000,
+ADDR_SURF_SAMPLE_SPLIT_2 = 0x00000001,
+ADDR_SURF_SAMPLE_SPLIT_4 = 0x00000002,
+ADDR_SURF_SAMPLE_SPLIT_8 = 0x00000003,
+} SampleSplit;
+
+/*
+ * PipeConfig enum
+ */
+
+typedef enum PipeConfig {
+ADDR_SURF_P2 = 0x00000000,
+ADDR_SURF_P2_RESERVED0 = 0x00000001,
+ADDR_SURF_P2_RESERVED1 = 0x00000002,
+ADDR_SURF_P2_RESERVED2 = 0x00000003,
+ADDR_SURF_P4_8x16 = 0x00000004,
+ADDR_SURF_P4_16x16 = 0x00000005,
+ADDR_SURF_P4_16x32 = 0x00000006,
+ADDR_SURF_P4_32x32 = 0x00000007,
+ADDR_SURF_P8_16x16_8x16 = 0x00000008,
+ADDR_SURF_P8_16x32_8x16 = 0x00000009,
+ADDR_SURF_P8_32x32_8x16 = 0x0000000a,
+ADDR_SURF_P8_16x32_16x16 = 0x0000000b,
+ADDR_SURF_P8_32x32_16x16 = 0x0000000c,
+ADDR_SURF_P8_32x32_16x32 = 0x0000000d,
+ADDR_SURF_P8_32x64_32x32 = 0x0000000e,
+ADDR_SURF_P8_RESERVED0 = 0x0000000f,
+ADDR_SURF_P16_32x32_8x16 = 0x00000010,
+ADDR_SURF_P16_32x32_16x16 = 0x00000011,
+} PipeConfig;
+
+/*
+ * SeEnable enum
+ */
+
+typedef enum SeEnable {
+ADDR_CONFIG_DISABLE_SE = 0x00000000,
+ADDR_CONFIG_ENABLE_SE = 0x00000001,
+} SeEnable;
+
+/*
+ * NumBanks enum
+ */
+
+typedef enum NumBanks {
+ADDR_SURF_2_BANK = 0x00000000,
+ADDR_SURF_4_BANK = 0x00000001,
+ADDR_SURF_8_BANK = 0x00000002,
+ADDR_SURF_16_BANK = 0x00000003,
+} NumBanks;
+
+/*
+ * BankWidth enum
+ */
+
+typedef enum BankWidth {
+ADDR_SURF_BANK_WIDTH_1 = 0x00000000,
+ADDR_SURF_BANK_WIDTH_2 = 0x00000001,
+ADDR_SURF_BANK_WIDTH_4 = 0x00000002,
+ADDR_SURF_BANK_WIDTH_8 = 0x00000003,
+} BankWidth;
+
+/*
+ * BankHeight enum
+ */
+
+typedef enum BankHeight {
+ADDR_SURF_BANK_HEIGHT_1 = 0x00000000,
+ADDR_SURF_BANK_HEIGHT_2 = 0x00000001,
+ADDR_SURF_BANK_HEIGHT_4 = 0x00000002,
+ADDR_SURF_BANK_HEIGHT_8 = 0x00000003,
+} BankHeight;
+
+/*
+ * BankWidthHeight enum
+ */
+
+typedef enum BankWidthHeight {
+ADDR_SURF_BANK_WH_1 = 0x00000000,
+ADDR_SURF_BANK_WH_2 = 0x00000001,
+ADDR_SURF_BANK_WH_4 = 0x00000002,
+ADDR_SURF_BANK_WH_8 = 0x00000003,
+} BankWidthHeight;
+
+/*
+ * MacroTileAspect enum
+ */
+
+typedef enum MacroTileAspect {
+ADDR_SURF_MACRO_ASPECT_1 = 0x00000000,
+ADDR_SURF_MACRO_ASPECT_2 = 0x00000001,
+ADDR_SURF_MACRO_ASPECT_4 = 0x00000002,
+ADDR_SURF_MACRO_ASPECT_8 = 0x00000003,
+} MacroTileAspect;
+
+/*
+ * GATCL1RequestType enum
+ */
+
+typedef enum GATCL1RequestType {
+GATCL1_TYPE_NORMAL = 0x00000000,
+GATCL1_TYPE_SHOOTDOWN = 0x00000001,
+GATCL1_TYPE_BYPASS = 0x00000002,
+} GATCL1RequestType;
+
+/*
+ * UTCL1RequestType enum
+ */
+
+typedef enum UTCL1RequestType {
+UTCL1_TYPE_NORMAL = 0x00000000,
+UTCL1_TYPE_SHOOTDOWN = 0x00000001,
+UTCL1_TYPE_BYPASS = 0x00000002,
+} UTCL1RequestType;
+
+/*
+ * UTCL1FaultType enum
+ */
+
+typedef enum UTCL1FaultType {
+UTCL1_XNACK_SUCCESS = 0x00000000,
+UTCL1_XNACK_RETRY = 0x00000001,
+UTCL1_XNACK_PRT = 0x00000002,
+UTCL1_XNACK_NO_RETRY = 0x00000003,
+} UTCL1FaultType;
+
+/*
+ * TCC_CACHE_POLICIES enum
+ */
+
+typedef enum TCC_CACHE_POLICIES {
+TCC_CACHE_POLICY_LRU = 0x00000000,
+TCC_CACHE_POLICY_STREAM = 0x00000001,
+} TCC_CACHE_POLICIES;
+
+/*
+ * MTYPE enum
+ */
+
+typedef enum MTYPE {
+MTYPE_NC = 0x00000000,
+MTYPE_WC = 0x00000001,
+MTYPE_CC = 0x00000002,
+MTYPE_UC = 0x00000003,
+} MTYPE;
+
+/*
+ * RMI_CID enum
+ */
+
+typedef enum RMI_CID {
+RMI_CID_CC = 0x00000000,
+RMI_CID_FC = 0x00000001,
+RMI_CID_CM = 0x00000002,
+RMI_CID_DC = 0x00000003,
+RMI_CID_Z = 0x00000004,
+RMI_CID_S = 0x00000005,
+RMI_CID_TILE = 0x00000006,
+RMI_CID_ZPCPSD = 0x00000007,
+} RMI_CID;
+
+/*
+ * PERFMON_COUNTER_MODE enum
+ */
+
+typedef enum PERFMON_COUNTER_MODE {
+PERFMON_COUNTER_MODE_ACCUM = 0x00000000,
+PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x00000001,
+PERFMON_COUNTER_MODE_MAX = 0x00000002,
+PERFMON_COUNTER_MODE_DIRTY = 0x00000003,
+PERFMON_COUNTER_MODE_SAMPLE = 0x00000004,
+PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005,
+PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006,
+PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x00000007,
+PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x00000008,
+PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x00000009,
+PERFMON_COUNTER_MODE_RESERVED = 0x0000000f,
+} PERFMON_COUNTER_MODE;
+
+/*
+ * PERFMON_SPM_MODE enum
+ */
+
+typedef enum PERFMON_SPM_MODE {
+PERFMON_SPM_MODE_OFF = 0x00000000,
+PERFMON_SPM_MODE_16BIT_CLAMP = 0x00000001,
+PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x00000002,
+PERFMON_SPM_MODE_32BIT_CLAMP = 0x00000003,
+PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x00000004,
+PERFMON_SPM_MODE_RESERVED_5 = 0x00000005,
+PERFMON_SPM_MODE_RESERVED_6 = 0x00000006,
+PERFMON_SPM_MODE_RESERVED_7 = 0x00000007,
+PERFMON_SPM_MODE_TEST_MODE_0 = 0x00000008,
+PERFMON_SPM_MODE_TEST_MODE_1 = 0x00000009,
+PERFMON_SPM_MODE_TEST_MODE_2 = 0x0000000a,
+} PERFMON_SPM_MODE;
+
+/*
+ * SurfaceTiling enum
+ */
+
+typedef enum SurfaceTiling {
+ARRAY_LINEAR = 0x00000000,
+ARRAY_TILED = 0x00000001,
+} SurfaceTiling;
+
+/*
+ * SurfaceArray enum
+ */
+
+typedef enum SurfaceArray {
+ARRAY_1D = 0x00000000,
+ARRAY_2D = 0x00000001,
+ARRAY_3D = 0x00000002,
+ARRAY_3D_SLICE = 0x00000003,
+} SurfaceArray;
+
+/*
+ * ColorArray enum
+ */
+
+typedef enum ColorArray {
+ARRAY_2D_ALT_COLOR = 0x00000000,
+ARRAY_2D_COLOR = 0x00000001,
+ARRAY_3D_SLICE_COLOR = 0x00000003,
+} ColorArray;
+
+/*
+ * DepthArray enum
+ */
+
+typedef enum DepthArray {
+ARRAY_2D_ALT_DEPTH = 0x00000000,
+ARRAY_2D_DEPTH = 0x00000001,
+} DepthArray;
+
+/*
+ * ENUM_NUM_SIMD_PER_CU enum
+ */
+
+typedef enum ENUM_NUM_SIMD_PER_CU {
+NUM_SIMD_PER_CU = 0x00000004,
+} ENUM_NUM_SIMD_PER_CU;
+
+/*
+ * DSM_ENABLE_ERROR_INJECT enum
+ */
+
+typedef enum DSM_ENABLE_ERROR_INJECT {
+DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000,
+DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001,
+DSM_ENABLE_ERROR_INJECT_DOUBLE = 0x00000002,
+DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED = 0x00000003,
+} DSM_ENABLE_ERROR_INJECT;
+
+/*
+ * DSM_SELECT_INJECT_DELAY enum
+ */
+
+typedef enum DSM_SELECT_INJECT_DELAY {
+DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000,
+DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001,
+} DSM_SELECT_INJECT_DELAY;
+
+/*
+ * SWIZZLE_TYPE_ENUM enum
+ */
+
+typedef enum SWIZZLE_TYPE_ENUM {
+SW_Z = 0x00000000,
+SW_S = 0x00000001,
+SW_D = 0x00000002,
+SW_R = 0x00000003,
+SW_L = 0x00000004,
+} SWIZZLE_TYPE_ENUM;
+
+/*
+ * TC_MICRO_TILE_MODE enum
+ */
+
+typedef enum TC_MICRO_TILE_MODE {
+MICRO_TILE_MODE_LINEAR = 0x00000000,
+MICRO_TILE_MODE_ROTATED = 0x00000001,
+MICRO_TILE_MODE_STD_2D = 0x00000002,
+MICRO_TILE_MODE_STD_3D = 0x00000003,
+MICRO_TILE_MODE_DISPLAY_2D = 0x00000004,
+MICRO_TILE_MODE_DISPLAY_3D = 0x00000005,
+MICRO_TILE_MODE_Z_2D = 0x00000006,
+MICRO_TILE_MODE_Z_3D = 0x00000007,
+} TC_MICRO_TILE_MODE;
+
+/*
+ * SWIZZLE_MODE_ENUM enum
+ */
+
+typedef enum SWIZZLE_MODE_ENUM {
+SW_LINEAR = 0x00000000,
+SW_256B_S = 0x00000001,
+SW_256B_D = 0x00000002,
+SW_256B_R = 0x00000003,
+SW_4KB_Z = 0x00000004,
+SW_4KB_S = 0x00000005,
+SW_4KB_D = 0x00000006,
+SW_4KB_R = 0x00000007,
+SW_64KB_Z = 0x00000008,
+SW_64KB_S = 0x00000009,
+SW_64KB_D = 0x0000000a,
+SW_64KB_R = 0x0000000b,
+SW_VAR_Z = 0x0000000c,
+SW_VAR_S = 0x0000000d,
+SW_VAR_D = 0x0000000e,
+SW_VAR_R = 0x0000000f,
+SW_RESERVED_16 = 0x00000010,
+SW_RESERVED_17 = 0x00000011,
+SW_RESERVED_18 = 0x00000012,
+SW_RESERVED_19 = 0x00000013,
+SW_4KB_Z_X = 0x00000014,
+SW_4KB_S_X = 0x00000015,
+SW_4KB_D_X = 0x00000016,
+SW_4KB_R_X = 0x00000017,
+SW_64KB_Z_X = 0x00000018,
+SW_64KB_S_X = 0x00000019,
+SW_64KB_D_X = 0x0000001a,
+SW_64KB_R_X = 0x0000001b,
+SW_VAR_Z_X = 0x0000001c,
+SW_VAR_S_X = 0x0000001d,
+SW_VAR_D_X = 0x0000001e,
+SW_VAR_R_X = 0x0000001f,
+SW_RESERVED_12 = 0x00000020,
+SW_RESERVED_13 = 0x00000021,
+SW_RESERVED_14 = 0x00000022,
+SW_RESERVED_15 = 0x00000023,
+} SWIZZLE_MODE_ENUM;
+
+/*
+ * PipeTiling enum
+ */
+
+typedef enum PipeTiling {
+CONFIG_1_PIPE = 0x00000000,
+CONFIG_2_PIPE = 0x00000001,
+CONFIG_4_PIPE = 0x00000002,
+CONFIG_8_PIPE = 0x00000003,
+} PipeTiling;
+
+/*
+ * BankTiling enum
+ */
+
+typedef enum BankTiling {
+CONFIG_4_BANK = 0x00000000,
+CONFIG_8_BANK = 0x00000001,
+} BankTiling;
+
+/*
+ * GroupInterleave enum
+ */
+
+typedef enum GroupInterleave {
+CONFIG_256B_GROUP = 0x00000000,
+CONFIG_512B_GROUP = 0x00000001,
+} GroupInterleave;
+
+/*
+ * RowTiling enum
+ */
+
+typedef enum RowTiling {
+CONFIG_1KB_ROW = 0x00000000,
+CONFIG_2KB_ROW = 0x00000001,
+CONFIG_4KB_ROW = 0x00000002,
+CONFIG_8KB_ROW = 0x00000003,
+CONFIG_1KB_ROW_OPT = 0x00000004,
+CONFIG_2KB_ROW_OPT = 0x00000005,
+CONFIG_4KB_ROW_OPT = 0x00000006,
+CONFIG_8KB_ROW_OPT = 0x00000007,
+} RowTiling;
+
+/*
+ * BankSwapBytes enum
+ */
+
+typedef enum BankSwapBytes {
+CONFIG_128B_SWAPS = 0x00000000,
+CONFIG_256B_SWAPS = 0x00000001,
+CONFIG_512B_SWAPS = 0x00000002,
+CONFIG_1KB_SWAPS = 0x00000003,
+} BankSwapBytes;
+
+/*
+ * SampleSplitBytes enum
+ */
+
+typedef enum SampleSplitBytes {
+CONFIG_1KB_SPLIT = 0x00000000,
+CONFIG_2KB_SPLIT = 0x00000001,
+CONFIG_4KB_SPLIT = 0x00000002,
+CONFIG_8KB_SPLIT = 0x00000003,
+} SampleSplitBytes;
+
+/*******************************************************
+ * AZSTREAM Enums
+ *******************************************************/
+
+/*
+ * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum
+ */
+
+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
+OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0x00000000,
+OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 0x00000001,
+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;
+
+/*
+ * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum
+ */
+
+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
+OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0x00000000,
+OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 0x00000001,
+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;
+
+/*
+ * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum
+ */
+
+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
+OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0x00000000,
+OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 0x00000001,
+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;
+
+/*
+ * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum
+ */
+
+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
+OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0x00000000,
+OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 0x00000001,
+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;
+
+/*
+ * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum
+ */
+
+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
+OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0x00000000,
+OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 0x00000001,
+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;
+
+/*
+ * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum
+ */
+
+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
+OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0x00000000,
+OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 0x00000001,
+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;
+
+/*
+ * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum
+ */
+
+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
+OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0x00000000,
+OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 0x00000001,
+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;
+
+/*
+ * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum
+ */
+
+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
+OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0x00000000,
+OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 0x00000001,
+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;
+
+/*
+ * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum
+ */
+
+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
+OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0x00000000,
+OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 0x00000001,
+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;
+
+/*
+ * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum
+ */
+
+typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
+} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;
+
+/*
+ * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum
+ */
+
+typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
+} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;
+
+/*
+ * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum
+ */
+
+typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
+} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;
+
+/*
+ * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum
+ */
+
+typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
+} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;
+
+/*
+ * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum
+ */
+
+typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 0x00000008,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 0x00000009,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 0x0000000a,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 0x0000000b,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 0x0000000c,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 0x0000000d,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 0x0000000e,
+OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 0x0000000f,
+} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;
+
+/*******************************************************
+ * BLNDV Enums
+ *******************************************************/
+
+/*
+ * BLNDV_CONTROL_BLND_MODE enum
+ */
+
+typedef enum BLNDV_CONTROL_BLND_MODE {
+BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x00000000,
+BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x00000001,
+BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x00000002,
+BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x00000003,
+} BLNDV_CONTROL_BLND_MODE;
+
+/*
+ * BLNDV_CONTROL_BLND_STEREO_TYPE enum
+ */
+
+typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE {
+BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0x00000000,
+BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 0x00000001,
+BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 0x00000002,
+BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x00000003,
+} BLNDV_CONTROL_BLND_STEREO_TYPE;
+
+/*
+ * BLNDV_CONTROL_BLND_STEREO_POLARITY enum
+ */
+
+typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY {
+BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW = 0x00000000,
+BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x00000001,
+} BLNDV_CONTROL_BLND_STEREO_POLARITY;
+
+/*
+ * BLNDV_CONTROL_BLND_FEEDTHROUGH_EN enum
+ */
+
+typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN {
+BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x00000000,
+BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x00000001,
+} BLNDV_CONTROL_BLND_FEEDTHROUGH_EN;
+
+/*
+ * BLNDV_CONTROL_BLND_ALPHA_MODE enum
+ */
+
+typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE {
+BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x00000000,
+BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
+BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x00000002,
+BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x00000003,
+} BLNDV_CONTROL_BLND_ALPHA_MODE;
+
+/*
+ * BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY enum
+ */
+
+typedef enum BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
+BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE = 0x00000000,
+BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE = 0x00000001,
+} BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
+
+/*
+ * BLNDV_CONTROL_BLND_MULTIPLIED_MODE enum
+ */
+
+typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE {
+BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x00000000,
+BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x00000001,
+} BLNDV_CONTROL_BLND_MULTIPLIED_MODE;
+
+/*
+ * BLNDV_SM_CONTROL2_SM_MODE enum
+ */
+
+typedef enum BLNDV_SM_CONTROL2_SM_MODE {
+BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x00000000,
+BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
+BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
+BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
+} BLNDV_SM_CONTROL2_SM_MODE;
+
+/*
+ * BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE enum
+ */
+
+typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE {
+BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x00000000,
+BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x00000001,
+} BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE;
+
+/*
+ * BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE enum
+ */
+
+typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE {
+BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x00000000,
+BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x00000001,
+} BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE;
+
+/*
+ * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL enum
+ */
+
+typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
+BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
+BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
+BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
+BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
+} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
+
+/*
+ * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL enum
+ */
+
+typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
+BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
+BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
+BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
+BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
+} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
+
+/*
+ * BLNDV_CONTROL2_PTI_ENABLE enum
+ */
+
+typedef enum BLNDV_CONTROL2_PTI_ENABLE {
+BLNDV_CONTROL2_PTI_ENABLE_FALSE = 0x00000000,
+BLNDV_CONTROL2_PTI_ENABLE_TRUE = 0x00000001,
+} BLNDV_CONTROL2_PTI_ENABLE;
+
+/*
+ * BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN enum
+ */
+
+typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
+BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x00000000,
+BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x00000001,
+} BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
+
+/*
+ * BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN enum
+ */
+
+typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
+BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x00000000,
+BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x00000001,
+} BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
+
+/*
+ * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK enum
+ */
+
+typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
+BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
+BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 0x00000001,
+} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
+
+/*
+ * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK enum
+ */
+
+typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
+BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0x00000000,
+BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 0x00000001,
+} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
+
+/*
+ * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK enum
+ */
+
+typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
+BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0x00000000,
+BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 0x00000001,
+} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
+
+/*
+ * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK enum
+ */
+
+typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
+BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0x00000000,
+BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 0x00000001,
+} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
+
+/*
+ * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK enum
+ */
+
+typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
+BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0x00000000,
+BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 0x00000001,
+} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
+
+/*
+ * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK enum
+ */
+
+typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
+BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0x00000000,
+BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 0x00000001,
+} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
+
+/*
+ * BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK enum
+ */
+
+typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
+BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x00000000,
+BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x00000001,
+} BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
+
+/*
+ * BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK enum
+ */
+
+typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
+BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x00000000,
+BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x00000001,
+} BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
+
+/*
+ * BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE enum
+ */
+
+typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
+BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x00000000,
+BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x00000001,
+} BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
+
+/*
+ * BLNDV_DEBUG_BLND_CNV_MUX_SELECT enum
+ */
+
+typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT {
+BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x00000000,
+BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x00000001,
+} BLNDV_DEBUG_BLND_CNV_MUX_SELECT;
+
+/*
+ * BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN enum
+ */
+
+typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
+BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
+BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
+} BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
+
+/*******************************************************
+ * LBV Enums
+ *******************************************************/
+
+/*
+ * LBV_PIXEL_DEPTH enum
+ */
+
+typedef enum LBV_PIXEL_DEPTH {
+PIXEL_DEPTH_30BPP = 0x00000000,
+PIXEL_DEPTH_24BPP = 0x00000001,
+PIXEL_DEPTH_18BPP = 0x00000002,
+PIXEL_DEPTH_38BPP = 0x00000003,
+} LBV_PIXEL_DEPTH;
+
+/*
+ * LBV_PIXEL_EXPAN_MODE enum
+ */
+
+typedef enum LBV_PIXEL_EXPAN_MODE {
+PIXEL_EXPAN_MODE_ZERO_EXP = 0x00000000,
+PIXEL_EXPAN_MODE_DYN_EXP = 0x00000001,
+} LBV_PIXEL_EXPAN_MODE;
+
+/*
+ * LBV_INTERLEAVE_EN enum
+ */
+
+typedef enum LBV_INTERLEAVE_EN {
+INTERLEAVE_DIS = 0x00000000,
+INTERLEAVE_EN = 0x00000001,
+} LBV_INTERLEAVE_EN;
+
+/*
+ * LBV_PIXEL_REDUCE_MODE enum
+ */
+
+typedef enum LBV_PIXEL_REDUCE_MODE {
+PIXEL_REDUCE_MODE_TRUNCATION = 0x00000000,
+PIXEL_REDUCE_MODE_ROUNDING = 0x00000001,
+} LBV_PIXEL_REDUCE_MODE;
+
+/*
+ * LBV_DYNAMIC_PIXEL_DEPTH enum
+ */
+
+typedef enum LBV_DYNAMIC_PIXEL_DEPTH {
+DYNAMIC_PIXEL_DEPTH_36BPP = 0x00000000,
+DYNAMIC_PIXEL_DEPTH_30BPP = 0x00000001,
+} LBV_DYNAMIC_PIXEL_DEPTH;
+
+/*
+ * LBV_DITHER_EN enum
+ */
+
+typedef enum LBV_DITHER_EN {
+DITHER_DIS = 0x00000000,
+DITHER_EN = 0x00000001,
+} LBV_DITHER_EN;
+
+/*
+ * LBV_DOWNSCALE_PREFETCH_EN enum
+ */
+
+typedef enum LBV_DOWNSCALE_PREFETCH_EN {
+DOWNSCALE_PREFETCH_DIS = 0x00000000,
+DOWNSCALE_PREFETCH_EN = 0x00000001,
+} LBV_DOWNSCALE_PREFETCH_EN;
+
+/*
+ * LBV_MEMORY_CONFIG enum
+ */
+
+typedef enum LBV_MEMORY_CONFIG {
+MEMORY_CONFIG_0 = 0x00000000,
+MEMORY_CONFIG_1 = 0x00000001,
+MEMORY_CONFIG_2 = 0x00000002,
+MEMORY_CONFIG_3 = 0x00000003,
+} LBV_MEMORY_CONFIG;
+
+/*
+ * LBV_SYNC_RESET_SEL2 enum
+ */
+
+typedef enum LBV_SYNC_RESET_SEL2 {
+SYNC_RESET_SEL2_VBLANK = 0x00000000,
+SYNC_RESET_SEL2_VSYNC = 0x00000001,
+} LBV_SYNC_RESET_SEL2;
+
+/*
+ * LBV_SYNC_DURATION enum
+ */
+
+typedef enum LBV_SYNC_DURATION {
+SYNC_DURATION_16 = 0x00000000,
+SYNC_DURATION_32 = 0x00000001,
+SYNC_DURATION_64 = 0x00000002,
+SYNC_DURATION_128 = 0x00000003,
+} LBV_SYNC_DURATION;
+
+/*******************************************************
+ * CRTC Enums
+ *******************************************************/
+
+/*
+ * CRTC_CONTROL_CRTC_START_POINT_CNTL enum
+ */
+
+typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {
+CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x00000000,
+CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x00000001,
+} CRTC_CONTROL_CRTC_START_POINT_CNTL;
+
+/*
+ * CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL enum
+ */
+
+typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {
+CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x00000000,
+CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x00000001,
+} CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL;
+
+/*
+ * CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL enum
+ */
+
+typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {
+CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0x00000000,
+CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT = 0x00000001,
+CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x00000002,
+CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST = 0x00000003,
+} CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL;
+
+/*
+ * CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY enum
+ */
+
+typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {
+CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0x00000000,
+CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x00000001,
+} CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY;
+
+/*
+ * CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE enum
+ */
+
+typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE {
+CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE = 0x00000000,
+CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x00000001,
+} CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE;
+
+/*
+ * CRTC_CONTROL_CRTC_SOF_PULL_EN enum
+ */
+
+typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN {
+CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE = 0x00000000,
+CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE = 0x00000001,
+} CRTC_CONTROL_CRTC_SOF_PULL_EN;
+
+/*
+ * CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL enum
+ */
+
+typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL {
+CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE = 0x00000000,
+CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE = 0x00000001,
+} CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL;
+
+/*
+ * CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL enum
+ */
+
+typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL {
+CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE = 0x00000000,
+CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE = 0x00000001,
+} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL;
+
+/*
+ * CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL enum
+ */
+
+typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL {
+CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE = 0x00000000,
+CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE = 0x00000001,
+} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL;
+
+/*
+ * CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN enum
+ */
+
+typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN {
+CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE = 0x00000000,
+CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE = 0x00000001,
+} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN;
+
+/*
+ * CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC enum
+ */
+
+typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC {
+CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000,
+CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 0x00000001,
+} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC;
+
+/*
+ * CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT enum
+ */
+
+typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT {
+CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000,
+CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE = 0x00000001,
+} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT;
+
+/*
+ * CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK enum
+ */
+
+typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
+CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0x00000000,
+CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE = 0x00000001,
+} CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;
+
+/*
+ * CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR enum
+ */
+
+typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR {
+CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000,
+CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE = 0x00000001,
+} CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR;
+
+/*
+ * CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL enum
+ */
+
+typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL {
+CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE = 0x00000000,
+CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE = 0x00000001,
+} CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL;
+
+/*
+ * CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN enum
+ */
+
+typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN {
+CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE = 0x00000000,
+CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE = 0x00000001,
+} CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN;
+
+/*
+ * CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT enum
+ */
+
+typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT {
+CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER = 0x00000001,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER = 0x00000002,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF = 0x00000005,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE = 0x00000006,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA = 0x00000007,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA = 0x00000008,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB = 0x00000009,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB = 0x0000000a,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1 = 0x0000000b,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2 = 0x0000000c,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD = 0x0000000d,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC = 0x0000000e,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0 = 0x00000010,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1 = 0x00000011,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2 = 0x00000012,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON = 0x00000013,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA = 0x00000014,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB = 0x00000015,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW = 0x00000016,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW = 0x00000017,
+} CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT;
+
+/*
+ * CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT enum
+ */
+
+typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT {
+CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE = 0x00000001,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA = 0x00000002,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB = 0x00000003,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA = 0x00000004,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB = 0x00000005,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 0x00000006,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC = 0x00000007,
+} CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT;
+
+/*
+ * CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN enum
+ */
+
+typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN {
+CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE = 0x00000000,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x00000001,
+} CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN;
+
+/*
+ * CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR enum
+ */
+
+typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR {
+CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE = 0x00000000,
+CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE = 0x00000001,
+} CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR;
+
+/*
+ * CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT enum
+ */
+
+typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT {
+CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER = 0x00000001,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER = 0x00000002,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF = 0x00000005,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE = 0x00000006,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA = 0x00000007,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA = 0x00000008,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB = 0x00000009,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB = 0x0000000a,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1 = 0x0000000b,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2 = 0x0000000c,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD = 0x0000000d,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC = 0x0000000e,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0 = 0x00000010,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1 = 0x00000011,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2 = 0x00000012,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON = 0x00000013,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA = 0x00000014,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB = 0x00000015,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW = 0x00000016,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW = 0x00000017,
+} CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT;
+
+/*
+ * CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT enum
+ */
+
+typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT {
+CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE = 0x00000001,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA = 0x00000002,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB = 0x00000003,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA = 0x00000004,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB = 0x00000005,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 0x00000006,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC = 0x00000007,
+} CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT;
+
+/*
+ * CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN enum
+ */
+
+typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN {
+CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE = 0x00000000,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x00000001,
+} CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN;
+
+/*
+ * CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR enum
+ */
+
+typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR {
+CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE = 0x00000000,
+CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE = 0x00000001,
+} CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR;
+
+/*
+ * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE enum
+ */
+
+typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE {
+CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE = 0x00000000,
+CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT = 0x00000001,
+CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 0x00000002,
+CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED = 0x00000003,
+} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE;
+
+/*
+ * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK enum
+ */
+
+typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK {
+CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE = 0x00000000,
+CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE = 0x00000001,
+} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK;
+
+/*
+ * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL enum
+ */
+
+typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL {
+CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0x00000000,
+CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 0x00000001,
+} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL;
+
+/*
+ * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR enum
+ */
+
+typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR {
+CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000,
+CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE = 0x00000001,
+} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR;
+
+/*
+ * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT enum
+ */
+
+typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT {
+CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0x00000000,
+CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 0x00000001,
+CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 0x00000002,
+CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 0x00000003,
+CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 0x00000004,
+CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 0x00000005,
+CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 0x00000006,
+CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 0x00000007,
+CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 0x00000008,
+CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK = 0x00000009,
+CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL = 0x0000000a,
+CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 0x0000000b,
+CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 0x0000000c,
+CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 0x0000000d,
+CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 0x0000000e,
+CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 0x0000000f,
+} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT;
+
+/*
+ * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY enum
+ */
+
+typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY {
+CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE = 0x00000000,
+CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE = 0x00000001,
+} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY;
+
+/*
+ * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY enum
+ */
+
+typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY {
+CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE = 0x00000000,
+CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE = 0x00000001,
+} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY;
+
+/*
+ * CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE enum
+ */
+
+typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE {
+CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO = 0x00000000,
+CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT = 0x00000001,
+CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT = 0x00000002,
+CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED = 0x00000003,
+} CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE;
+
+/*
+ * CRTC_CONTROL_CRTC_MASTER_EN enum
+ */
+
+typedef enum CRTC_CONTROL_CRTC_MASTER_EN {
+CRTC_CONTROL_CRTC_MASTER_EN_FALSE = 0x00000000,
+CRTC_CONTROL_CRTC_MASTER_EN_TRUE = 0x00000001,
+} CRTC_CONTROL_CRTC_MASTER_EN;
+
+/*
+ * CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN enum
+ */
+
+typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN {
+CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE = 0x00000000,
+CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE = 0x00000001,
+} CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN;
+
+/*
+ * CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE enum
+ */
+
+typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE {
+CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE = 0x00000000,
+CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE = 0x00000001,
+} CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE;
+
+/*
+ * CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE enum
+ */
+
+typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE {
+CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE = 0x00000000,
+CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE = 0x00000001,
+} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE;
+
+/*
+ * CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD enum
+ */
+
+typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD {
+CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT = 0x00000000,
+CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD = 0x00000001,
+CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN = 0x00000002,
+CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 0x00000003,
+} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD;
+
+/*
+ * CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY enum
+ */
+
+typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY {
+CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE = 0x00000000,
+CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE = 0x00000001,
+} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY;
+
+/*
+ * CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT enum
+ */
+
+typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT {
+CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE = 0x00000000,
+CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE = 0x00000001,
+} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT;
+
+/*
+ * CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN enum
+ */
+
+typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN {
+CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE = 0x00000000,
+CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE = 0x00000001,
+} CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN;
+
+/*
+ * CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE enum
+ */
+
+typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE {
+CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000,
+CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 0x00000001,
+} CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE;
+
+/*
+ * CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR enum
+ */
+
+typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR {
+CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000,
+CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 0x00000001,
+} CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR;
+
+/*
+ * CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE enum
+ */
+
+typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE {
+CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE = 0x00000000,
+CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 0x00000001,
+CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 0x00000002,
+CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED = 0x00000003,
+} CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE;
+
+/*
+ * CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY enum
+ */
+
+typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY {
+CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0x00000000,
+CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 0x00000001,
+} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY;
+
+/*
+ * CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY enum
+ */
+
+typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY {
+CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE = 0x00000000,
+CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE = 0x00000001,
+} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY;
+
+/*
+ * CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY enum
+ */
+
+typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY {
+CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE = 0x00000000,
+CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE = 0x00000001,
+} CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY;
+
+/*
+ * CRTC_STEREO_CONTROL_CRTC_STEREO_EN enum
+ */
+
+typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN {
+CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE = 0x00000000,
+CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE = 0x00000001,
+} CRTC_STEREO_CONTROL_CRTC_STEREO_EN;
+
+/*
+ * CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR enum
+ */
+
+typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR {
+CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0x00000000,
+CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE = 0x00000001,
+} CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR;
+
+/*
+ * CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL enum
+ */
+
+typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL {
+CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0x00000000,
+CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 0x00000001,
+CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 0x00000002,
+CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 0x00000003,
+} CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL;
+
+/*
+ * CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY enum
+ */
+
+typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY {
+CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE = 0x00000000,
+CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE = 0x00000001,
+} CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY;
+
+/*
+ * CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY enum
+ */
+
+typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY {
+CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE = 0x00000000,
+CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE = 0x00000001,
+} CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY;
+
+/*
+ * CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN enum
+ */
+
+typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN {
+CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE = 0x00000000,
+CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE = 0x00000001,
+} CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN;
+
+/*
+ * CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN enum
+ */
+
+typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN {
+CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE = 0x00000000,
+CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE = 0x00000001,
+} CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN;
+
+/*
+ * CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK enum
+ */
+
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK {
+CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE = 0x00000000,
+CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE = 0x00000001,
+} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK;
+
+/*
+ * CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE enum
+ */
+
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE {
+CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE = 0x00000000,
+CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE = 0x00000001,
+} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE;
+
+/*
+ * CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK enum
+ */
+
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK {
+CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE = 0x00000000,
+CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE = 0x00000001,
+} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK;
+
+/*
+ * CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE enum
+ */
+
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE {
+CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE = 0x00000000,
+CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE = 0x00000001,
+} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE;
+
+/*
+ * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK enum
+ */
+
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK {
+CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE = 0x00000000,
+CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE = 0x00000001,
+} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK;
+
+/*
+ * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE enum
+ */
+
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE {
+CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0x00000000,
+CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE = 0x00000001,
+} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE;
+
+/*
+ * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK enum
+ */
+
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK {
+CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0x00000000,
+CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 0x00000001,
+} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK;
+
+/*
+ * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum
+ */
+
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
+CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0x00000000,
+CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 0x00000001,
+} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
+
+/*
+ * CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK enum
+ */
+
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK {
+CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE = 0x00000000,
+CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE = 0x00000001,
+} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK;
+
+/*
+ * CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE enum
+ */
+
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE {
+CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0x00000000,
+CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE = 0x00000001,
+} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE;
+
+/*
+ * CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK enum
+ */
+
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK {
+CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE = 0x00000000,
+CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE = 0x00000001,
+} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK;
+
+/*
+ * CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE enum
+ */
+
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE {
+CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0x00000000,
+CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE = 0x00000001,
+} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE;
+
+/*
+ * CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK enum
+ */
+
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK {
+CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE = 0x00000000,
+CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE = 0x00000001,
+} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK;
+
+/*
+ * CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE enum
+ */
+
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE {
+CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE = 0x00000000,
+CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE = 0x00000001,
+} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE;
+
+/*
+ * CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK enum
+ */
+
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK {
+CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE = 0x00000000,
+CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE = 0x00000001,
+} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK;
+
+/*
+ * CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE enum
+ */
+
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE {
+CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0x00000000,
+CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE = 0x00000001,
+} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE;
+
+/*
+ * CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK enum
+ */
+
+typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK {
+CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE = 0x00000000,
+CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE = 0x00000001,
+} CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK;
+
+/*
+ * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY enum
+ */
+
+typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY {
+CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE = 0x00000000,
+CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE = 0x00000001,
+} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY;
+
+/*
+ * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN enum
+ */
+
+typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN {
+CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE = 0x00000000,
+CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE = 0x00000001,
+} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN;
+
+/*
+ * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE enum
+ */
+
+typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE {
+CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0 = 0x00000000,
+CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1 = 0x00000001,
+} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE;
+
+/*
+ * CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE enum
+ */
+
+typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE {
+CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE = 0x00000000,
+CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE = 0x00000001,
+} CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE;
+
+/*
+ * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN enum
+ */
+
+typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN {
+CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE = 0x00000000,
+CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE = 0x00000001,
+} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN;
+
+/*
+ * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE enum
+ */
+
+typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE {
+CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB = 0x00000000,
+CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601 = 0x00000001,
+CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709 = 0x00000002,
+CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS = 0x00000003,
+CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS = 0x00000004,
+CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB = 0x00000005,
+CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB = 0x00000006,
+CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS = 0x00000007,
+} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE;
+
+/*
+ * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE enum
+ */
+
+typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE {
+CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE = 0x00000000,
+CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE = 0x00000001,
+} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE;
+
+/*
+ * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT enum
+ */
+
+typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT {
+CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC = 0x00000000,
+CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC = 0x00000001,
+CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC = 0x00000002,
+CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED = 0x00000003,
+} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT;
+
+/*
+ * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum
+ */
+
+typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
+MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x00000000,
+MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x00000001,
+} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
+
+/*
+ * MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK enum
+ */
+
+typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK {
+MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE = 0x00000000,
+MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE = 0x00000001,
+} MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK;
+
+/*
+ * MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK enum
+ */
+
+typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
+MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0x00000000,
+MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 0x00000001,
+} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK;
+
+/*
+ * MASTER_UPDATE_MODE_MASTER_UPDATE_MODE enum
+ */
+
+typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE {
+MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN = 0x00000000,
+MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA = 0x00000001,
+MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA = 0x00000002,
+MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE = 0x00000003,
+} MASTER_UPDATE_MODE_MASTER_UPDATE_MODE;
+
+/*
+ * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum
+ */
+
+typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
+MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0x00000000,
+MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN = 0x00000001,
+MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD = 0x00000002,
+MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 0x00000003,
+} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
+
+/*
+ * CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE enum
+ */
+
+typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE {
+CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE = 0x00000000,
+CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG = 0x00000001,
+CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL = 0x00000002,
+} CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE;
+
+/*
+ * CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR enum
+ */
+
+typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR {
+CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0x00000000,
+CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE = 0x00000001,
+} CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR;
+
+/*
+ * CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR enum
+ */
+
+typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
+CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0x00000000,
+CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE = 0x00000001,
+} CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR;
+
+/*
+ * CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR enum
+ */
+
+typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR {
+CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE = 0x00000000,
+CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE = 0x00000001,
+} CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR;
+
+/*
+ * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum
+ */
+
+typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
+CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0x00000000,
+CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 0x00000001,
+} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
+
+/*
+ * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE enum
+ */
+
+typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE {
+CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000,
+CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 0x00000001,
+} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE;
+
+/*
+ * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR enum
+ */
+
+typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR {
+CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000,
+CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE = 0x00000001,
+} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR;
+
+/*
+ * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE enum
+ */
+
+typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE {
+CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0x00000000,
+CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 0x00000001,
+} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE;
+
+/*
+ * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR enum
+ */
+
+typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR {
+CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000,
+CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE = 0x00000001,
+} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR;
+
+/*
+ * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE enum
+ */
+
+typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE {
+CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000,
+CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 0x00000001,
+} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE;
+
+/*
+ * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE enum
+ */
+
+typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE {
+CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0x00000000,
+CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 0x00000001,
+} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE;
+
+/*
+ * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR enum
+ */
+
+typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR {
+CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000,
+CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE = 0x00000001,
+} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR;
+
+/*
+ * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE enum
+ */
+
+typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE {
+CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000,
+CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 0x00000001,
+} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE;
+
+/*
+ * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE enum
+ */
+
+typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE {
+CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0x00000000,
+CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 0x00000001,
+} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE;
+
+/*
+ * CRTC_CRC_CNTL_CRTC_CRC_EN enum
+ */
+
+typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN {
+CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE = 0x00000000,
+CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE = 0x00000001,
+} CRTC_CRC_CNTL_CRTC_CRC_EN;
+
+/*
+ * CRTC_CRC_CNTL_CRTC_CRC_CONT_EN enum
+ */
+
+typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN {
+CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE = 0x00000000,
+CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE = 0x00000001,
+} CRTC_CRC_CNTL_CRTC_CRC_CONT_EN;
+
+/*
+ * CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE enum
+ */
+
+typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE {
+CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT = 0x00000000,
+CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT = 0x00000001,
+CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES = 0x00000002,
+CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS = 0x00000003,
+} CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE;
+
+/*
+ * CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE enum
+ */
+
+typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE {
+CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP = 0x00000000,
+CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM = 0x00000001,
+CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002,
+CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 0x00000003,
+} CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE;
+
+/*
+ * CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS enum
+ */
+
+typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS {
+CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000,
+CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 0x00000001,
+} CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS;
+
+/*
+ * CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT enum
+ */
+
+typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT {
+CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB = 0x00000000,
+CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B = 0x00000001,
+CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB = 0x00000002,
+CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B = 0x00000003,
+CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB = 0x00000004,
+CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B = 0x00000005,
+CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB = 0x00000006,
+CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B = 0x00000007,
+} CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT;
+
+/*
+ * CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT enum
+ */
+
+typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT {
+CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB = 0x00000000,
+CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B = 0x00000001,
+CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB = 0x00000002,
+CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B = 0x00000003,
+CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB = 0x00000004,
+CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B = 0x00000005,
+CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB = 0x00000006,
+CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B = 0x00000007,
+} CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT;
+
+/*
+ * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE enum
+ */
+
+typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE {
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE = 0x00000000,
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT = 0x00000001,
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS = 0x00000002,
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED = 0x00000003,
+} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE;
+
+/*
+ * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE enum
+ */
+
+typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE {
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE = 0x00000000,
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE = 0x00000001,
+} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE;
+
+/*
+ * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE enum
+ */
+
+typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE {
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE = 0x00000000,
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE = 0x00000001,
+} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE;
+
+/*
+ * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW enum
+ */
+
+typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW {
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel = 0x00000000,
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel = 0x00000001,
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel = 0x00000002,
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel = 0x00000003,
+} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW;
+
+/*
+ * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE enum
+ */
+
+typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE {
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE = 0x00000000,
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE = 0x00000001,
+} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE;
+
+/*
+ * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE enum
+ */
+
+typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE {
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0x00000000,
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE = 0x00000001,
+} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE;
+
+/*
+ * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY enum
+ */
+
+typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY {
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE = 0x00000000,
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE = 0x00000001,
+} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY;
+
+/*
+ * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY enum
+ */
+
+typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY {
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE = 0x00000000,
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE = 0x00000001,
+} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY;
+
+/*
+ * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE enum
+ */
+
+typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE {
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE = 0x00000000,
+CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE = 0x00000001,
+} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE;
+
+/*
+ * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE enum
+ */
+
+typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE {
+CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE = 0x00000000,
+CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE = 0x00000001,
+} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE;
+
+/*
+ * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR enum
+ */
+
+typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR {
+CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0x00000000,
+CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE = 0x00000001,
+} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR;
+
+/*
+ * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE enum
+ */
+
+typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE {
+CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE = 0x00000000,
+CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE = 0x00000001,
+} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE;
+
+/*
+ * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT enum
+ */
+
+typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT {
+CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME = 0x00000000,
+CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME = 0x00000001,
+CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME = 0x00000002,
+CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME = 0x00000003,
+CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME = 0x00000004,
+CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME = 0x00000005,
+CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME = 0x00000006,
+CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME = 0x00000007,
+} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT;
+
+/*
+ * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE enum
+ */
+
+typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE {
+CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE = 0x00000000,
+CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE = 0x00000001,
+} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE;
+
+/*
+ * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR enum
+ */
+
+typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR {
+CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE = 0x00000000,
+CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE = 0x00000001,
+} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR;
+
+/*
+ * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE enum
+ */
+
+typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE {
+CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE = 0x00000000,
+CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE = 0x00000001,
+} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE;
+
+/*
+ * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE enum
+ */
+
+typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE {
+CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE = 0x00000000,
+CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE = 0x00000001,
+} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE;
+
+/*
+ * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR enum
+ */
+
+typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR {
+CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0x00000000,
+CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE = 0x00000001,
+} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR;
+
+/*
+ * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE enum
+ */
+
+typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE {
+CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE = 0x00000000,
+CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE = 0x00000001,
+} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE;
+
+/*
+ * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE enum
+ */
+
+typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE {
+CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE = 0x00000000,
+CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE = 0x00000001,
+} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE;
+
+/*
+ * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR enum
+ */
+
+typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR {
+CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE = 0x00000000,
+CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE = 0x00000001,
+} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR;
+
+/*
+ * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE enum
+ */
+
+typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE {
+CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE = 0x00000000,
+CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE = 0x00000001,
+} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE;
+
+/*
+ * CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE enum
+ */
+
+typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE {
+CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE = 0x00000000,
+CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE = 0x00000001,
+} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE;
+
+/*
+ * CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE enum
+ */
+
+typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE {
+CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0x00000000,
+CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON = 0x00000001,
+} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE;
+
+/*
+ * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN enum
+ */
+
+typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN {
+CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE = 0x00000000,
+CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE = 0x00000001,
+} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN;
+
+/*
+ * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB enum
+ */
+
+typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB {
+CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE = 0x00000000,
+CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE = 0x00000001,
+} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB;
+
+/*
+ * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE enum
+ */
+
+typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE {
+CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0x00000000,
+CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 0x00000001,
+CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 0x00000002,
+CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 0x00000003,
+} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE;
+
+/*
+ * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR enum
+ */
+
+typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR {
+CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0x00000000,
+CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 0x00000001,
+} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR;
+
+/*
+ * CRTC_V_SYNC_A_POL enum
+ */
+
+typedef enum CRTC_V_SYNC_A_POL {
+CRTC_V_SYNC_A_POL_HIGH = 0x00000000,
+CRTC_V_SYNC_A_POL_LOW = 0x00000001,
+} CRTC_V_SYNC_A_POL;
+
+/*
+ * CRTC_H_SYNC_A_POL enum
+ */
+
+typedef enum CRTC_H_SYNC_A_POL {
+CRTC_H_SYNC_A_POL_HIGH = 0x00000000,
+CRTC_H_SYNC_A_POL_LOW = 0x00000001,
+} CRTC_H_SYNC_A_POL;
+
+/*
+ * CRTC_HORZ_REPETITION_COUNT enum
+ */
+
+typedef enum CRTC_HORZ_REPETITION_COUNT {
+CRTC_HORZ_REPETITION_COUNT_0 = 0x00000000,
+CRTC_HORZ_REPETITION_COUNT_1 = 0x00000001,
+CRTC_HORZ_REPETITION_COUNT_2 = 0x00000002,
+CRTC_HORZ_REPETITION_COUNT_3 = 0x00000003,
+CRTC_HORZ_REPETITION_COUNT_4 = 0x00000004,
+CRTC_HORZ_REPETITION_COUNT_5 = 0x00000005,
+CRTC_HORZ_REPETITION_COUNT_6 = 0x00000006,
+CRTC_HORZ_REPETITION_COUNT_7 = 0x00000007,
+CRTC_HORZ_REPETITION_COUNT_8 = 0x00000008,
+CRTC_HORZ_REPETITION_COUNT_9 = 0x00000009,
+CRTC_HORZ_REPETITION_COUNT_10 = 0x0000000a,
+CRTC_HORZ_REPETITION_COUNT_11 = 0x0000000b,
+CRTC_HORZ_REPETITION_COUNT_12 = 0x0000000c,
+CRTC_HORZ_REPETITION_COUNT_13 = 0x0000000d,
+CRTC_HORZ_REPETITION_COUNT_14 = 0x0000000e,
+CRTC_HORZ_REPETITION_COUNT_15 = 0x0000000f,
+} CRTC_HORZ_REPETITION_COUNT;
+
+/*
+ * CRTC_DRR_MODE_DBUF_UPDATE_MODE enum
+ */
+
+typedef enum CRTC_DRR_MODE_DBUF_UPDATE_MODE {
+CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE = 0x00000000,
+CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL = 0x00000001,
+CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF = 0x00000002,
+CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF = 0x00000003,
+} CRTC_DRR_MODE_DBUF_UPDATE_MODE;
+
+/*******************************************************
+ * FMT Enums
+ *******************************************************/
+
+/*
+ * FMT_CONTROL_PIXEL_ENCODING enum
+ */
+
+typedef enum FMT_CONTROL_PIXEL_ENCODING {
+FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x00000000,
+FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x00000001,
+FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 0x00000002,
+FMT_CONTROL_PIXEL_ENCODING_RESERVED = 0x00000003,
+} FMT_CONTROL_PIXEL_ENCODING;
+
+/*
+ * FMT_CONTROL_SUBSAMPLING_MODE enum
+ */
+
+typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
+FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x00000000,
+FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x00000001,
+FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 0x00000002,
+FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 0x00000003,
+} FMT_CONTROL_SUBSAMPLING_MODE;
+
+/*
+ * FMT_CONTROL_SUBSAMPLING_ORDER enum
+ */
+
+typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
+FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x00000000,
+FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x00000001,
+} FMT_CONTROL_SUBSAMPLING_ORDER;
+
+/*
+ * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum
+ */
+
+typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
+FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0x00000000,
+FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 0x00000001,
+} FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS;
+
+/*
+ * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum
+ */
+
+typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
+FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x00000000,
+FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x00000001,
+} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
+
+/*
+ * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum
+ */
+
+typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
+FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x00000000,
+FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x00000001,
+FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x00000002,
+} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
+
+/*
+ * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum
+ */
+
+typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
+FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x00000000,
+FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001,
+FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x00000002,
+} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
+
+/*
+ * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum
+ */
+
+typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
+FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0x00000000,
+FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 0x00000001,
+FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 0x00000002,
+} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
+
+/*
+ * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum
+ */
+
+typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
+FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x00000000,
+FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x00000001,
+} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
+
+/*
+ * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum
+ */
+
+typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
+FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x00000000,
+FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x00000001,
+FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x00000002,
+FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x00000003,
+} FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
+
+/*
+ * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum
+ */
+
+typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
+FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x00000000,
+FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x00000001,
+FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x00000002,
+FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x00000003,
+} FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
+
+/*
+ * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum
+ */
+
+typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
+FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x00000000,
+FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x00000001,
+FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x00000002,
+FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x00000003,
+} FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
+
+/*
+ * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT enum
+ */
+
+typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT {
+FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN = 0x00000000,
+FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN = 0x00000001,
+} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT;
+
+/*
+ * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum
+ */
+
+typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
+FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0x00000000,
+FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 0x00000001,
+} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
+
+/*
+ * FMT_CLAMP_CNTL_COLOR_FORMAT enum
+ */
+
+typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
+FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x00000000,
+FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x00000001,
+FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x00000002,
+FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 0x00000003,
+FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x00000004,
+FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x00000005,
+FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x00000006,
+FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x00000007,
+} FMT_CLAMP_CNTL_COLOR_FORMAT;
+
+/*
+ * FMT_CRC_CNTL_CONT_EN enum
+ */
+
+typedef enum FMT_CRC_CNTL_CONT_EN {
+FMT_CRC_CNTL_CONT_EN_ONE_SHOT = 0x00000000,
+FMT_CRC_CNTL_CONT_EN_CONT = 0x00000001,
+} FMT_CRC_CNTL_CONT_EN;
+
+/*
+ * FMT_CRC_CNTL_INCLUDE_OVERSCAN enum
+ */
+
+typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN {
+FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE = 0x00000000,
+FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE = 0x00000001,
+} FMT_CRC_CNTL_INCLUDE_OVERSCAN;
+
+/*
+ * FMT_CRC_CNTL_ONLY_BLANKB enum
+ */
+
+typedef enum FMT_CRC_CNTL_ONLY_BLANKB {
+FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD = 0x00000000,
+FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK = 0x00000001,
+} FMT_CRC_CNTL_ONLY_BLANKB;
+
+/*
+ * FMT_CRC_CNTL_PSR_MODE_ENABLE enum
+ */
+
+typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE {
+FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL = 0x00000000,
+FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC = 0x00000001,
+} FMT_CRC_CNTL_PSR_MODE_ENABLE;
+
+/*
+ * FMT_CRC_CNTL_INTERLACE_MODE enum
+ */
+
+typedef enum FMT_CRC_CNTL_INTERLACE_MODE {
+FMT_CRC_CNTL_INTERLACE_MODE_TOP = 0x00000000,
+FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM = 0x00000001,
+FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002,
+FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH = 0x00000003,
+} FMT_CRC_CNTL_INTERLACE_MODE;
+
+/*
+ * FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE enum
+ */
+
+typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE {
+FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL = 0x00000000,
+FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN = 0x00000001,
+} FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE;
+
+/*
+ * FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT enum
+ */
+
+typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT {
+FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN = 0x00000000,
+FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD = 0x00000001,
+} FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT;
+
+/*
+ * FMT_DEBUG_CNTL_COLOR_SELECT enum
+ */
+
+typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
+FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0x00000000,
+FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 0x00000001,
+FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 0x00000002,
+FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 0x00000003,
+} FMT_DEBUG_CNTL_COLOR_SELECT;
+
+/*
+ * FMT_SPATIAL_DITHER_MODE enum
+ */
+
+typedef enum FMT_SPATIAL_DITHER_MODE {
+FMT_SPATIAL_DITHER_MODE_0 = 0x00000000,
+FMT_SPATIAL_DITHER_MODE_1 = 0x00000001,
+FMT_SPATIAL_DITHER_MODE_2 = 0x00000002,
+FMT_SPATIAL_DITHER_MODE_3 = 0x00000003,
+} FMT_SPATIAL_DITHER_MODE;
+
+/*
+ * FMT_STEREOSYNC_OVR_POL enum
+ */
+
+typedef enum FMT_STEREOSYNC_OVR_POL {
+FMT_STEREOSYNC_OVR_POL_INVERTED = 0x00000000,
+FMT_STEREOSYNC_OVR_POL_NOT_INVERTED = 0x00000001,
+} FMT_STEREOSYNC_OVR_POL;
+
+/*
+ * FMT_DYNAMIC_EXP_MODE enum
+ */
+
+typedef enum FMT_DYNAMIC_EXP_MODE {
+FMT_DYNAMIC_EXP_MODE_10to12 = 0x00000000,
+FMT_DYNAMIC_EXP_MODE_8to12 = 0x00000001,
+} FMT_DYNAMIC_EXP_MODE;
+
+/*******************************************************
+ * HPD Enums
+ *******************************************************/
+
+/*
+ * HPD_INT_CONTROL_ACK enum
+ */
+
+typedef enum HPD_INT_CONTROL_ACK {
+HPD_INT_CONTROL_ACK_0 = 0x00000000,
+HPD_INT_CONTROL_ACK_1 = 0x00000001,
+} HPD_INT_CONTROL_ACK;
+
+/*
+ * HPD_INT_CONTROL_POLARITY enum
+ */
+
+typedef enum HPD_INT_CONTROL_POLARITY {
+HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x00000000,
+HPD_INT_CONTROL_GEN_INT_ON_CON = 0x00000001,
+} HPD_INT_CONTROL_POLARITY;
+
+/*
+ * HPD_INT_CONTROL_RX_INT_ACK enum
+ */
+
+typedef enum HPD_INT_CONTROL_RX_INT_ACK {
+HPD_INT_CONTROL_RX_INT_ACK_0 = 0x00000000,
+HPD_INT_CONTROL_RX_INT_ACK_1 = 0x00000001,
+} HPD_INT_CONTROL_RX_INT_ACK;
+
+/*******************************************************
+ * LB Enums
+ *******************************************************/
+
+/*
+ * LB_DATA_FORMAT_PIXEL_DEPTH enum
+ */
+
+typedef enum LB_DATA_FORMAT_PIXEL_DEPTH {
+LB_DATA_FORMAT_PIXEL_DEPTH_30BPP = 0x00000000,
+LB_DATA_FORMAT_PIXEL_DEPTH_24BPP = 0x00000001,
+LB_DATA_FORMAT_PIXEL_DEPTH_18BPP = 0x00000002,
+LB_DATA_FORMAT_PIXEL_DEPTH_36BPP = 0x00000003,
+} LB_DATA_FORMAT_PIXEL_DEPTH;
+
+/*
+ * LB_DATA_FORMAT_PIXEL_EXPAN_MODE enum
+ */
+
+typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE {
+LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION = 0x00000000,
+LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION = 0x00000001,
+} LB_DATA_FORMAT_PIXEL_EXPAN_MODE;
+
+/*
+ * LB_DATA_FORMAT_PIXEL_REDUCE_MODE enum
+ */
+
+typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE {
+LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION = 0x00000000,
+LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING = 0x00000001,
+} LB_DATA_FORMAT_PIXEL_REDUCE_MODE;
+
+/*
+ * LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH enum
+ */
+
+typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH {
+LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP = 0x00000000,
+LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP = 0x00000001,
+} LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH;
+
+/*
+ * LB_DATA_FORMAT_INTERLEAVE_EN enum
+ */
+
+typedef enum LB_DATA_FORMAT_INTERLEAVE_EN {
+LB_DATA_FORMAT_INTERLEAVE_DISABLE = 0x00000000,
+LB_DATA_FORMAT_INTERLEAVE_ENABLE = 0x00000001,
+} LB_DATA_FORMAT_INTERLEAVE_EN;
+
+/*
+ * LB_DATA_FORMAT_REQUEST_MODE enum
+ */
+
+typedef enum LB_DATA_FORMAT_REQUEST_MODE {
+LB_DATA_FORMAT_REQUEST_MODE_NORMAL = 0x00000000,
+LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE = 0x00000001,
+} LB_DATA_FORMAT_REQUEST_MODE;
+
+/*
+ * LB_DATA_FORMAT_ALPHA_EN enum
+ */
+
+typedef enum LB_DATA_FORMAT_ALPHA_EN {
+LB_DATA_FORMAT_ALPHA_DISABLE = 0x00000000,
+LB_DATA_FORMAT_ALPHA_ENABLE = 0x00000001,
+} LB_DATA_FORMAT_ALPHA_EN;
+
+/*
+ * LB_VLINE_START_END_VLINE_INV enum
+ */
+
+typedef enum LB_VLINE_START_END_VLINE_INV {
+LB_VLINE_START_END_VLINE_NORMAL = 0x00000000,
+LB_VLINE_START_END_VLINE_INVERSE = 0x00000001,
+} LB_VLINE_START_END_VLINE_INV;
+
+/*
+ * LB_VLINE2_START_END_VLINE2_INV enum
+ */
+
+typedef enum LB_VLINE2_START_END_VLINE2_INV {
+LB_VLINE2_START_END_VLINE2_NORMAL = 0x00000000,
+LB_VLINE2_START_END_VLINE2_INVERSE = 0x00000001,
+} LB_VLINE2_START_END_VLINE2_INV;
+
+/*
+ * LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK enum
+ */
+
+typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK {
+LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE = 0x00000000,
+LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE = 0x00000001,
+} LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK;
+
+/*
+ * LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK enum
+ */
+
+typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK {
+LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE = 0x00000000,
+LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE = 0x00000001,
+} LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK;
+
+/*
+ * LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK enum
+ */
+
+typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK {
+LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE = 0x00000000,
+LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE = 0x00000001,
+} LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK;
+
+/*
+ * LB_VLINE_STATUS_VLINE_ACK enum
+ */
+
+typedef enum LB_VLINE_STATUS_VLINE_ACK {
+LB_VLINE_STATUS_VLINE_NORMAL = 0x00000000,
+LB_VLINE_STATUS_VLINE_CLEAR = 0x00000001,
+} LB_VLINE_STATUS_VLINE_ACK;
+
+/*
+ * LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE enum
+ */
+
+typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE {
+LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000,
+LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED = 0x00000001,
+} LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE;
+
+/*
+ * LB_VLINE2_STATUS_VLINE2_ACK enum
+ */
+
+typedef enum LB_VLINE2_STATUS_VLINE2_ACK {
+LB_VLINE2_STATUS_VLINE2_NORMAL = 0x00000000,
+LB_VLINE2_STATUS_VLINE2_CLEAR = 0x00000001,
+} LB_VLINE2_STATUS_VLINE2_ACK;
+
+/*
+ * LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE enum
+ */
+
+typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE {
+LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000,
+LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED = 0x00000001,
+} LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE;
+
+/*
+ * LB_VBLANK_STATUS_VBLANK_ACK enum
+ */
+
+typedef enum LB_VBLANK_STATUS_VBLANK_ACK {
+LB_VBLANK_STATUS_VBLANK_NORMAL = 0x00000000,
+LB_VBLANK_STATUS_VBLANK_CLEAR = 0x00000001,
+} LB_VBLANK_STATUS_VBLANK_ACK;
+
+/*
+ * LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE enum
+ */
+
+typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE {
+LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000,
+LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED = 0x00000001,
+} LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE;
+
+/*
+ * LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL enum
+ */
+
+typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL {
+LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE = 0x00000000,
+LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK = 0x00000001,
+LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET = 0x00000002,
+LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET = 0x00000003,
+} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL;
+
+/*
+ * LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 enum
+ */
+
+typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 {
+LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK = 0x00000000,
+LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC = 0x00000001,
+} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2;
+
+/*
+ * LB_SYNC_RESET_SEL_LB_SYNC_DURATION enum
+ */
+
+typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION {
+LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS = 0x00000000,
+LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS = 0x00000001,
+LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 0x00000002,
+LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS = 0x00000003,
+} LB_SYNC_RESET_SEL_LB_SYNC_DURATION;
+
+/*
+ * LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN enum
+ */
+
+typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN {
+LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE = 0x00000000,
+LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE = 0x00000001,
+} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN;
+
+/*
+ * LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN enum
+ */
+
+typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN {
+LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE = 0x00000000,
+LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE = 0x00000001,
+} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN;
+
+/*
+ * LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK enum
+ */
+
+typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK {
+LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL = 0x00000000,
+LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET = 0x00000001,
+} LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK;
+
+/*
+ * LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK enum
+ */
+
+typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK {
+LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL = 0x00000000,
+LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET = 0x00000001,
+} LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK;
+
+/*
+ * LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE enum
+ */
+
+typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE {
+LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 0x00000002,
+LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP = 0x00000003,
+} LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE;
+
+/*
+ * LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET enum
+ */
+
+typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET {
+LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL = 0x00000000,
+LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE = 0x00000001,
+} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET;
+
+/*
+ * LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK enum
+ */
+
+typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK {
+LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0 = 0x00000000,
+LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1 = 0x00000001,
+} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK;
+
+/*
+ * LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE enum
+ */
+
+typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE {
+LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT = 0x00000000,
+LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG = 0x00000001,
+LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE = 0x00000002,
+} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE;
+
+/*
+ * LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE enum
+ */
+
+typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE {
+LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE = 0x00000000,
+LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN = 0x00000001,
+} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE;
+
+/*
+ * LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE enum
+ */
+
+typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE {
+ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER = 0x00000001,
+ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE = 0x00000002,
+} LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE;
+
+/*
+ * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL enum
+ */
+
+typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL {
+LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0 = 0x00000000,
+LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1 = 0x00000001,
+} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL;
+
+/*
+ * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE enum
+ */
+
+typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE {
+LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE = 0x00000000,
+LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE = 0x00000001,
+} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE;
+
+/*
+ * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO enum
+ */
+
+typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO {
+LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO = 0x00000000,
+LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO = 0x00000001,
+} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO;
+
+/*
+ * LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN enum
+ */
+
+typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN {
+LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0 = 0x00000000,
+LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1 = 0x00000001,
+} LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN;
+
+/*******************************************************
+ * DIG Enums
+ *******************************************************/
+
+/*
+ * HDMI_KEEPOUT_MODE enum
+ */
+
+typedef enum HDMI_KEEPOUT_MODE {
+HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0x00000000,
+HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 0x00000001,
+} HDMI_KEEPOUT_MODE;
+
+/*
+ * HDMI_DATA_SCRAMBLE_EN enum
+ */
+
+typedef enum HDMI_DATA_SCRAMBLE_EN {
+HDMI_DATA_SCRAMBLE_DISABLE = 0x00000000,
+HDMI_DATA_SCRAMBLE_ENABLE = 0x00000001,
+} HDMI_DATA_SCRAMBLE_EN;
+
+/*
+ * HDMI_CLOCK_CHANNEL_RATE enum
+ */
+
+typedef enum HDMI_CLOCK_CHANNEL_RATE {
+HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x00000000,
+HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x00000001,
+} HDMI_CLOCK_CHANNEL_RATE;
+
+/*
+ * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum
+ */
+
+typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
+HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0x00000000,
+HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 0x00000001,
+} HDMI_NO_EXTRA_NULL_PACKET_FILLED;
+
+/*
+ * HDMI_PACKET_GEN_VERSION enum
+ */
+
+typedef enum HDMI_PACKET_GEN_VERSION {
+HDMI_PACKET_GEN_VERSION_OLD = 0x00000000,
+HDMI_PACKET_GEN_VERSION_NEW = 0x00000001,
+} HDMI_PACKET_GEN_VERSION;
+
+/*
+ * HDMI_ERROR_ACK enum
+ */
+
+typedef enum HDMI_ERROR_ACK {
+HDMI_ERROR_ACK_INT = 0x00000000,
+HDMI_ERROR_NOT_ACK = 0x00000001,
+} HDMI_ERROR_ACK;
+
+/*
+ * HDMI_ERROR_MASK enum
+ */
+
+typedef enum HDMI_ERROR_MASK {
+HDMI_ERROR_MASK_INT = 0x00000000,
+HDMI_ERROR_NOT_MASK = 0x00000001,
+} HDMI_ERROR_MASK;
+
+/*
+ * HDMI_DEEP_COLOR_DEPTH enum
+ */
+
+typedef enum HDMI_DEEP_COLOR_DEPTH {
+HDMI_DEEP_COLOR_DEPTH_24BPP = 0x00000000,
+HDMI_DEEP_COLOR_DEPTH_30BPP = 0x00000001,
+HDMI_DEEP_COLOR_DEPTH_36BPP = 0x00000002,
+HDMI_DEEP_COLOR_DEPTH_RESERVED = 0x00000003,
+} HDMI_DEEP_COLOR_DEPTH;
+
+/*
+ * HDMI_AUDIO_DELAY_EN enum
+ */
+
+typedef enum HDMI_AUDIO_DELAY_EN {
+HDMI_AUDIO_DELAY_DISABLE = 0x00000000,
+HDMI_AUDIO_DELAY_58CLK = 0x00000001,
+HDMI_AUDIO_DELAY_56CLK = 0x00000002,
+HDMI_AUDIO_DELAY_RESERVED = 0x00000003,
+} HDMI_AUDIO_DELAY_EN;
+
+/*
+ * HDMI_AUDIO_SEND_MAX_PACKETS enum
+ */
+
+typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
+HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0x00000000,
+HDMI_SEND_MAX_AUDIO_PACKETS = 0x00000001,
+} HDMI_AUDIO_SEND_MAX_PACKETS;
+
+/*
+ * HDMI_ACR_SEND enum
+ */
+
+typedef enum HDMI_ACR_SEND {
+HDMI_ACR_NOT_SEND = 0x00000000,
+HDMI_ACR_PKT_SEND = 0x00000001,
+} HDMI_ACR_SEND;
+
+/*
+ * HDMI_ACR_CONT enum
+ */
+
+typedef enum HDMI_ACR_CONT {
+HDMI_ACR_CONT_DISABLE = 0x00000000,
+HDMI_ACR_CONT_ENABLE = 0x00000001,
+} HDMI_ACR_CONT;
+
+/*
+ * HDMI_ACR_SELECT enum
+ */
+
+typedef enum HDMI_ACR_SELECT {
+HDMI_ACR_SELECT_HW = 0x00000000,
+HDMI_ACR_SELECT_32K = 0x00000001,
+HDMI_ACR_SELECT_44K = 0x00000002,
+HDMI_ACR_SELECT_48K = 0x00000003,
+} HDMI_ACR_SELECT;
+
+/*
+ * HDMI_ACR_SOURCE enum
+ */
+
+typedef enum HDMI_ACR_SOURCE {
+HDMI_ACR_SOURCE_HW = 0x00000000,
+HDMI_ACR_SOURCE_SW = 0x00000001,
+} HDMI_ACR_SOURCE;
+
+/*
+ * HDMI_ACR_N_MULTIPLE enum
+ */
+
+typedef enum HDMI_ACR_N_MULTIPLE {
+HDMI_ACR_0_MULTIPLE_RESERVED = 0x00000000,
+HDMI_ACR_1_MULTIPLE = 0x00000001,
+HDMI_ACR_2_MULTIPLE = 0x00000002,
+HDMI_ACR_3_MULTIPLE_RESERVED = 0x00000003,
+HDMI_ACR_4_MULTIPLE = 0x00000004,
+HDMI_ACR_5_MULTIPLE_RESERVED = 0x00000005,
+HDMI_ACR_6_MULTIPLE_RESERVED = 0x00000006,
+HDMI_ACR_7_MULTIPLE_RESERVED = 0x00000007,
+} HDMI_ACR_N_MULTIPLE;
+
+/*
+ * HDMI_ACR_AUDIO_PRIORITY enum
+ */
+
+typedef enum HDMI_ACR_AUDIO_PRIORITY {
+HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x00000000,
+HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x00000001,
+} HDMI_ACR_AUDIO_PRIORITY;
+
+/*
+ * HDMI_NULL_SEND enum
+ */
+
+typedef enum HDMI_NULL_SEND {
+HDMI_NULL_NOT_SEND = 0x00000000,
+HDMI_NULL_PKT_SEND = 0x00000001,
+} HDMI_NULL_SEND;
+
+/*
+ * HDMI_GC_SEND enum
+ */
+
+typedef enum HDMI_GC_SEND {
+HDMI_GC_NOT_SEND = 0x00000000,
+HDMI_GC_PKT_SEND = 0x00000001,
+} HDMI_GC_SEND;
+
+/*
+ * HDMI_GC_CONT enum
+ */
+
+typedef enum HDMI_GC_CONT {
+HDMI_GC_CONT_DISABLE = 0x00000000,
+HDMI_GC_CONT_ENABLE = 0x00000001,
+} HDMI_GC_CONT;
+
+/*
+ * HDMI_ISRC_SEND enum
+ */
+
+typedef enum HDMI_ISRC_SEND {
+HDMI_ISRC_NOT_SEND = 0x00000000,
+HDMI_ISRC_PKT_SEND = 0x00000001,
+} HDMI_ISRC_SEND;
+
+/*
+ * HDMI_ISRC_CONT enum
+ */
+
+typedef enum HDMI_ISRC_CONT {
+HDMI_ISRC_CONT_DISABLE = 0x00000000,
+HDMI_ISRC_CONT_ENABLE = 0x00000001,
+} HDMI_ISRC_CONT;
+
+/*
+ * HDMI_AVI_INFO_SEND enum
+ */
+
+typedef enum HDMI_AVI_INFO_SEND {
+HDMI_AVI_INFO_NOT_SEND = 0x00000000,
+HDMI_AVI_INFO_PKT_SEND = 0x00000001,
+} HDMI_AVI_INFO_SEND;
+
+/*
+ * HDMI_AVI_INFO_CONT enum
+ */
+
+typedef enum HDMI_AVI_INFO_CONT {
+HDMI_AVI_INFO_CONT_DISABLE = 0x00000000,
+HDMI_AVI_INFO_CONT_ENABLE = 0x00000001,
+} HDMI_AVI_INFO_CONT;
+
+/*
+ * HDMI_AUDIO_INFO_SEND enum
+ */
+
+typedef enum HDMI_AUDIO_INFO_SEND {
+HDMI_AUDIO_INFO_NOT_SEND = 0x00000000,
+HDMI_AUDIO_INFO_PKT_SEND = 0x00000001,
+} HDMI_AUDIO_INFO_SEND;
+
+/*
+ * HDMI_AUDIO_INFO_CONT enum
+ */
+
+typedef enum HDMI_AUDIO_INFO_CONT {
+HDMI_AUDIO_INFO_CONT_DISABLE = 0x00000000,
+HDMI_AUDIO_INFO_CONT_ENABLE = 0x00000001,
+} HDMI_AUDIO_INFO_CONT;
+
+/*
+ * HDMI_MPEG_INFO_SEND enum
+ */
+
+typedef enum HDMI_MPEG_INFO_SEND {
+HDMI_MPEG_INFO_NOT_SEND = 0x00000000,
+HDMI_MPEG_INFO_PKT_SEND = 0x00000001,
+} HDMI_MPEG_INFO_SEND;
+
+/*
+ * HDMI_MPEG_INFO_CONT enum
+ */
+
+typedef enum HDMI_MPEG_INFO_CONT {
+HDMI_MPEG_INFO_CONT_DISABLE = 0x00000000,
+HDMI_MPEG_INFO_CONT_ENABLE = 0x00000001,
+} HDMI_MPEG_INFO_CONT;
+
+/*
+ * HDMI_GENERIC0_SEND enum
+ */
+
+typedef enum HDMI_GENERIC0_SEND {
+HDMI_GENERIC0_NOT_SEND = 0x00000000,
+HDMI_GENERIC0_PKT_SEND = 0x00000001,
+} HDMI_GENERIC0_SEND;
+
+/*
+ * HDMI_GENERIC0_CONT enum
+ */
+
+typedef enum HDMI_GENERIC0_CONT {
+HDMI_GENERIC0_CONT_DISABLE = 0x00000000,
+HDMI_GENERIC0_CONT_ENABLE = 0x00000001,
+} HDMI_GENERIC0_CONT;
+
+/*
+ * HDMI_GENERIC1_SEND enum
+ */
+
+typedef enum HDMI_GENERIC1_SEND {
+HDMI_GENERIC1_NOT_SEND = 0x00000000,
+HDMI_GENERIC1_PKT_SEND = 0x00000001,
+} HDMI_GENERIC1_SEND;
+
+/*
+ * HDMI_GENERIC1_CONT enum
+ */
+
+typedef enum HDMI_GENERIC1_CONT {
+HDMI_GENERIC1_CONT_DISABLE = 0x00000000,
+HDMI_GENERIC1_CONT_ENABLE = 0x00000001,
+} HDMI_GENERIC1_CONT;
+
+/*
+ * HDMI_GC_AVMUTE_CONT enum
+ */
+
+typedef enum HDMI_GC_AVMUTE_CONT {
+HDMI_GC_AVMUTE_CONT_DISABLE = 0x00000000,
+HDMI_GC_AVMUTE_CONT_ENABLE = 0x00000001,
+} HDMI_GC_AVMUTE_CONT;
+
+/*
+ * HDMI_PACKING_PHASE_OVERRIDE enum
+ */
+
+typedef enum HDMI_PACKING_PHASE_OVERRIDE {
+HDMI_PACKING_PHASE_SET_BY_HW = 0x00000000,
+HDMI_PACKING_PHASE_SET_BY_SW = 0x00000001,
+} HDMI_PACKING_PHASE_OVERRIDE;
+
+/*
+ * HDMI_GENERIC2_SEND enum
+ */
+
+typedef enum HDMI_GENERIC2_SEND {
+HDMI_GENERIC2_NOT_SEND = 0x00000000,
+HDMI_GENERIC2_PKT_SEND = 0x00000001,
+} HDMI_GENERIC2_SEND;
+
+/*
+ * HDMI_GENERIC2_CONT enum
+ */
+
+typedef enum HDMI_GENERIC2_CONT {
+HDMI_GENERIC2_CONT_DISABLE = 0x00000000,
+HDMI_GENERIC2_CONT_ENABLE = 0x00000001,
+} HDMI_GENERIC2_CONT;
+
+/*
+ * HDMI_GENERIC3_SEND enum
+ */
+
+typedef enum HDMI_GENERIC3_SEND {
+HDMI_GENERIC3_NOT_SEND = 0x00000000,
+HDMI_GENERIC3_PKT_SEND = 0x00000001,
+} HDMI_GENERIC3_SEND;
+
+/*
+ * HDMI_GENERIC3_CONT enum
+ */
+
+typedef enum HDMI_GENERIC3_CONT {
+HDMI_GENERIC3_CONT_DISABLE = 0x00000000,
+HDMI_GENERIC3_CONT_ENABLE = 0x00000001,
+} HDMI_GENERIC3_CONT;
+
+/*
+ * TMDS_PIXEL_ENCODING enum
+ */
+
+typedef enum TMDS_PIXEL_ENCODING {
+TMDS_PIXEL_ENCODING_444_OR_420 = 0x00000000,
+TMDS_PIXEL_ENCODING_422 = 0x00000001,
+} TMDS_PIXEL_ENCODING;
+
+/*
+ * TMDS_COLOR_FORMAT enum
+ */
+
+typedef enum TMDS_COLOR_FORMAT {
+TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0x00000000,
+TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 0x00000001,
+TMDS_COLOR_FORMAT_DUAL30BPP = 0x00000002,
+TMDS_COLOR_FORMAT_RESERVED = 0x00000003,
+} TMDS_COLOR_FORMAT;
+
+/*
+ * TMDS_STEREOSYNC_CTL_SEL_REG enum
+ */
+
+typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
+TMDS_STEREOSYNC_CTL0 = 0x00000000,
+TMDS_STEREOSYNC_CTL1 = 0x00000001,
+TMDS_STEREOSYNC_CTL2 = 0x00000002,
+TMDS_STEREOSYNC_CTL3 = 0x00000003,
+} TMDS_STEREOSYNC_CTL_SEL_REG;
+
+/*
+ * TMDS_CTL0_DATA_SEL enum
+ */
+
+typedef enum TMDS_CTL0_DATA_SEL {
+TMDS_CTL0_DATA_SEL0_RESERVED = 0x00000000,
+TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
+TMDS_CTL0_DATA_SEL2_VSYNC = 0x00000002,
+TMDS_CTL0_DATA_SEL3_RESERVED = 0x00000003,
+TMDS_CTL0_DATA_SEL4_HSYNC = 0x00000004,
+TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 0x00000005,
+TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 0x00000006,
+TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 0x00000007,
+} TMDS_CTL0_DATA_SEL;
+
+/*
+ * TMDS_CTL0_DATA_INVERT enum
+ */
+
+typedef enum TMDS_CTL0_DATA_INVERT {
+TMDS_CTL0_DATA_NORMAL = 0x00000000,
+TMDS_CTL0_DATA_INVERT_EN = 0x00000001,
+} TMDS_CTL0_DATA_INVERT;
+
+/*
+ * TMDS_CTL0_DATA_MODULATION enum
+ */
+
+typedef enum TMDS_CTL0_DATA_MODULATION {
+TMDS_CTL0_DATA_MODULATION_DISABLE = 0x00000000,
+TMDS_CTL0_DATA_MODULATION_BIT0 = 0x00000001,
+TMDS_CTL0_DATA_MODULATION_BIT1 = 0x00000002,
+TMDS_CTL0_DATA_MODULATION_BIT2 = 0x00000003,
+} TMDS_CTL0_DATA_MODULATION;
+
+/*
+ * TMDS_CTL0_PATTERN_OUT_EN enum
+ */
+
+typedef enum TMDS_CTL0_PATTERN_OUT_EN {
+TMDS_CTL0_PATTERN_OUT_DISABLE = 0x00000000,
+TMDS_CTL0_PATTERN_OUT_ENABLE = 0x00000001,
+} TMDS_CTL0_PATTERN_OUT_EN;
+
+/*
+ * TMDS_CTL1_DATA_SEL enum
+ */
+
+typedef enum TMDS_CTL1_DATA_SEL {
+TMDS_CTL1_DATA_SEL0_RESERVED = 0x00000000,
+TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
+TMDS_CTL1_DATA_SEL2_VSYNC = 0x00000002,
+TMDS_CTL1_DATA_SEL3_RESERVED = 0x00000003,
+TMDS_CTL1_DATA_SEL4_HSYNC = 0x00000004,
+TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 0x00000005,
+TMDS_CTL1_DATA_SEL8_BLANK_TIME = 0x00000006,
+TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 0x00000007,
+} TMDS_CTL1_DATA_SEL;
+
+/*
+ * TMDS_CTL1_DATA_INVERT enum
+ */
+
+typedef enum TMDS_CTL1_DATA_INVERT {
+TMDS_CTL1_DATA_NORMAL = 0x00000000,
+TMDS_CTL1_DATA_INVERT_EN = 0x00000001,
+} TMDS_CTL1_DATA_INVERT;
+
+/*
+ * TMDS_CTL1_DATA_MODULATION enum
+ */
+
+typedef enum TMDS_CTL1_DATA_MODULATION {
+TMDS_CTL1_DATA_MODULATION_DISABLE = 0x00000000,
+TMDS_CTL1_DATA_MODULATION_BIT0 = 0x00000001,
+TMDS_CTL1_DATA_MODULATION_BIT1 = 0x00000002,
+TMDS_CTL1_DATA_MODULATION_BIT2 = 0x00000003,
+} TMDS_CTL1_DATA_MODULATION;
+
+/*
+ * TMDS_CTL1_PATTERN_OUT_EN enum
+ */
+
+typedef enum TMDS_CTL1_PATTERN_OUT_EN {
+TMDS_CTL1_PATTERN_OUT_DISABLE = 0x00000000,
+TMDS_CTL1_PATTERN_OUT_ENABLE = 0x00000001,
+} TMDS_CTL1_PATTERN_OUT_EN;
+
+/*
+ * TMDS_CTL2_DATA_SEL enum
+ */
+
+typedef enum TMDS_CTL2_DATA_SEL {
+TMDS_CTL2_DATA_SEL0_RESERVED = 0x00000000,
+TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
+TMDS_CTL2_DATA_SEL2_VSYNC = 0x00000002,
+TMDS_CTL2_DATA_SEL3_RESERVED = 0x00000003,
+TMDS_CTL2_DATA_SEL4_HSYNC = 0x00000004,
+TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 0x00000005,
+TMDS_CTL2_DATA_SEL8_BLANK_TIME = 0x00000006,
+TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 0x00000007,
+} TMDS_CTL2_DATA_SEL;
+
+/*
+ * TMDS_CTL2_DATA_INVERT enum
+ */
+
+typedef enum TMDS_CTL2_DATA_INVERT {
+TMDS_CTL2_DATA_NORMAL = 0x00000000,
+TMDS_CTL2_DATA_INVERT_EN = 0x00000001,
+} TMDS_CTL2_DATA_INVERT;
+
+/*
+ * TMDS_CTL2_DATA_MODULATION enum
+ */
+
+typedef enum TMDS_CTL2_DATA_MODULATION {
+TMDS_CTL2_DATA_MODULATION_DISABLE = 0x00000000,
+TMDS_CTL2_DATA_MODULATION_BIT0 = 0x00000001,
+TMDS_CTL2_DATA_MODULATION_BIT1 = 0x00000002,
+TMDS_CTL2_DATA_MODULATION_BIT2 = 0x00000003,
+} TMDS_CTL2_DATA_MODULATION;
+
+/*
+ * TMDS_CTL2_PATTERN_OUT_EN enum
+ */
+
+typedef enum TMDS_CTL2_PATTERN_OUT_EN {
+TMDS_CTL2_PATTERN_OUT_DISABLE = 0x00000000,
+TMDS_CTL2_PATTERN_OUT_ENABLE = 0x00000001,
+} TMDS_CTL2_PATTERN_OUT_EN;
+
+/*
+ * TMDS_CTL3_DATA_INVERT enum
+ */
+
+typedef enum TMDS_CTL3_DATA_INVERT {
+TMDS_CTL3_DATA_NORMAL = 0x00000000,
+TMDS_CTL3_DATA_INVERT_EN = 0x00000001,
+} TMDS_CTL3_DATA_INVERT;
+
+/*
+ * TMDS_CTL3_DATA_MODULATION enum
+ */
+
+typedef enum TMDS_CTL3_DATA_MODULATION {
+TMDS_CTL3_DATA_MODULATION_DISABLE = 0x00000000,
+TMDS_CTL3_DATA_MODULATION_BIT0 = 0x00000001,
+TMDS_CTL3_DATA_MODULATION_BIT1 = 0x00000002,
+TMDS_CTL3_DATA_MODULATION_BIT2 = 0x00000003,
+} TMDS_CTL3_DATA_MODULATION;
+
+/*
+ * TMDS_CTL3_PATTERN_OUT_EN enum
+ */
+
+typedef enum TMDS_CTL3_PATTERN_OUT_EN {
+TMDS_CTL3_PATTERN_OUT_DISABLE = 0x00000000,
+TMDS_CTL3_PATTERN_OUT_ENABLE = 0x00000001,
+} TMDS_CTL3_PATTERN_OUT_EN;
+
+/*
+ * TMDS_CTL3_DATA_SEL enum
+ */
+
+typedef enum TMDS_CTL3_DATA_SEL {
+TMDS_CTL3_DATA_SEL0_RESERVED = 0x00000000,
+TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
+TMDS_CTL3_DATA_SEL2_VSYNC = 0x00000002,
+TMDS_CTL3_DATA_SEL3_RESERVED = 0x00000003,
+TMDS_CTL3_DATA_SEL4_HSYNC = 0x00000004,
+TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 0x00000005,
+TMDS_CTL3_DATA_SEL8_BLANK_TIME = 0x00000006,
+TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 0x00000007,
+} TMDS_CTL3_DATA_SEL;
+
+/*
+ * DIG_FE_CNTL_SOURCE_SELECT enum
+ */
+
+typedef enum DIG_FE_CNTL_SOURCE_SELECT {
+DIG_FE_SOURCE_FROM_FMT0 = 0x00000000,
+DIG_FE_SOURCE_FROM_FMT1 = 0x00000001,
+DIG_FE_SOURCE_FROM_FMT2 = 0x00000002,
+DIG_FE_SOURCE_FROM_FMT3 = 0x00000003,
+DIG_FE_SOURCE_FROM_FMT4 = 0x00000004,
+DIG_FE_SOURCE_FROM_FMT5 = 0x00000005,
+} DIG_FE_CNTL_SOURCE_SELECT;
+
+/*
+ * DIG_FE_CNTL_STEREOSYNC_SELECT enum
+ */
+
+typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
+DIG_FE_STEREOSYNC_FROM_FMT0 = 0x00000000,
+DIG_FE_STEREOSYNC_FROM_FMT1 = 0x00000001,
+DIG_FE_STEREOSYNC_FROM_FMT2 = 0x00000002,
+DIG_FE_STEREOSYNC_FROM_FMT3 = 0x00000003,
+DIG_FE_STEREOSYNC_FROM_FMT4 = 0x00000004,
+DIG_FE_STEREOSYNC_FROM_FMT5 = 0x00000005,
+} DIG_FE_CNTL_STEREOSYNC_SELECT;
+
+/*
+ * DIG_FIFO_READ_CLOCK_SRC enum
+ */
+
+typedef enum DIG_FIFO_READ_CLOCK_SRC {
+DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0x00000000,
+DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x00000001,
+} DIG_FIFO_READ_CLOCK_SRC;
+
+/*
+ * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum
+ */
+
+typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
+DIG_OUTPUT_CRC_ON_LINK0 = 0x00000000,
+DIG_OUTPUT_CRC_ON_LINK1 = 0x00000001,
+} DIG_OUTPUT_CRC_CNTL_LINK_SEL;
+
+/*
+ * DIG_OUTPUT_CRC_DATA_SEL enum
+ */
+
+typedef enum DIG_OUTPUT_CRC_DATA_SEL {
+DIG_OUTPUT_CRC_FOR_FULLFRAME = 0x00000000,
+DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 0x00000001,
+DIG_OUTPUT_CRC_FOR_VBI = 0x00000002,
+DIG_OUTPUT_CRC_FOR_AUDIO = 0x00000003,
+} DIG_OUTPUT_CRC_DATA_SEL;
+
+/*
+ * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum
+ */
+
+typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
+DIG_IN_NORMAL_OPERATION = 0x00000000,
+DIG_IN_DEBUG_MODE = 0x00000001,
+} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
+
+/*
+ * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum
+ */
+
+typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
+DIG_10BIT_TEST_PATTERN = 0x00000000,
+DIG_ALTERNATING_TEST_PATTERN = 0x00000001,
+} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
+
+/*
+ * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum
+ */
+
+typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
+DIG_TEST_PATTERN_NORMAL = 0x00000000,
+DIG_TEST_PATTERN_RANDOM = 0x00000001,
+} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
+
+/*
+ * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum
+ */
+
+typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
+DIG_RANDOM_PATTERN_ENABLED = 0x00000000,
+DIG_RANDOM_PATTERN_RESETED = 0x00000001,
+} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
+
+/*
+ * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum
+ */
+
+typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
+DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0x00000000,
+DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x00000001,
+} DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
+
+/*
+ * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum
+ */
+
+typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
+DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x00000000,
+DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 0x00000001,
+} DIG_RANDOM_PATTERN_SEED_RAN_PAT;
+
+/*
+ * DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL enum
+ */
+
+typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
+DIG_FIFO_USE_OVERWRITE_LEVEL = 0x00000000,
+DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 0x00000001,
+} DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL;
+
+/*
+ * DIG_FIFO_ERROR_ACK enum
+ */
+
+typedef enum DIG_FIFO_ERROR_ACK {
+DIG_FIFO_ERROR_ACK_INT = 0x00000000,
+DIG_FIFO_ERROR_NOT_ACK = 0x00000001,
+} DIG_FIFO_ERROR_ACK;
+
+/*
+ * DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE enum
+ */
+
+typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
+DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0x00000000,
+DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 0x00000001,
+} DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE;
+
+/*
+ * DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX enum
+ */
+
+typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
+DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0x00000000,
+DIG_FIFO_FORCE_RECOMP_MINMAX = 0x00000001,
+} DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX;
+
+/*
+ * AFMT_INTERRUPT_STATUS_CHG_MASK enum
+ */
+
+typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
+AFMT_INTERRUPT_DISABLE = 0x00000000,
+AFMT_INTERRUPT_ENABLE = 0x00000001,
+} AFMT_INTERRUPT_STATUS_CHG_MASK;
+
+/*
+ * HDMI_GC_AVMUTE enum
+ */
+
+typedef enum HDMI_GC_AVMUTE {
+HDMI_GC_AVMUTE_SET = 0x00000000,
+HDMI_GC_AVMUTE_UNSET = 0x00000001,
+} HDMI_GC_AVMUTE;
+
+/*
+ * HDMI_DEFAULT_PAHSE enum
+ */
+
+typedef enum HDMI_DEFAULT_PAHSE {
+HDMI_DEFAULT_PHASE_IS_0 = 0x00000000,
+HDMI_DEFAULT_PHASE_IS_1 = 0x00000001,
+} HDMI_DEFAULT_PAHSE;
+
+/*
+ * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum
+ */
+
+typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
+AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0x00000000,
+AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 0x00000001,
+} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
+
+/*
+ * AUDIO_LAYOUT_SELECT enum
+ */
+
+typedef enum AUDIO_LAYOUT_SELECT {
+AUDIO_LAYOUT_0 = 0x00000000,
+AUDIO_LAYOUT_1 = 0x00000001,
+} AUDIO_LAYOUT_SELECT;
+
+/*
+ * AFMT_AUDIO_CRC_CONTROL_CONT enum
+ */
+
+typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
+AFMT_AUDIO_CRC_ONESHOT = 0x00000000,
+AFMT_AUDIO_CRC_AUTO_RESTART = 0x00000001,
+} AFMT_AUDIO_CRC_CONTROL_CONT;
+
+/*
+ * AFMT_AUDIO_CRC_CONTROL_SOURCE enum
+ */
+
+typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
+AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0x00000000,
+AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 0x00000001,
+} AFMT_AUDIO_CRC_CONTROL_SOURCE;
+
+/*
+ * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum
+ */
+
+typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
+AFMT_AUDIO_CRC_CH0_SIG = 0x00000000,
+AFMT_AUDIO_CRC_CH1_SIG = 0x00000001,
+AFMT_AUDIO_CRC_CH2_SIG = 0x00000002,
+AFMT_AUDIO_CRC_CH3_SIG = 0x00000003,
+AFMT_AUDIO_CRC_CH4_SIG = 0x00000004,
+AFMT_AUDIO_CRC_CH5_SIG = 0x00000005,
+AFMT_AUDIO_CRC_CH6_SIG = 0x00000006,
+AFMT_AUDIO_CRC_CH7_SIG = 0x00000007,
+AFMT_AUDIO_CRC_RESERVED_8 = 0x00000008,
+AFMT_AUDIO_CRC_RESERVED_9 = 0x00000009,
+AFMT_AUDIO_CRC_RESERVED_10 = 0x0000000a,
+AFMT_AUDIO_CRC_RESERVED_11 = 0x0000000b,
+AFMT_AUDIO_CRC_RESERVED_12 = 0x0000000c,
+AFMT_AUDIO_CRC_RESERVED_13 = 0x0000000d,
+AFMT_AUDIO_CRC_RESERVED_14 = 0x0000000e,
+AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 0x0000000f,
+} AFMT_AUDIO_CRC_CONTROL_CH_SEL;
+
+/*
+ * AFMT_RAMP_CONTROL0_SIGN enum
+ */
+
+typedef enum AFMT_RAMP_CONTROL0_SIGN {
+AFMT_RAMP_SIGNED = 0x00000000,
+AFMT_RAMP_UNSIGNED = 0x00000001,
+} AFMT_RAMP_CONTROL0_SIGN;
+
+/*
+ * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum
+ */
+
+typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
+AFMT_AUDIO_PACKET_SENT_DISABLED = 0x00000000,
+AFMT_AUDIO_PACKET_SENT_ENABLED = 0x00000001,
+} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;
+
+/*
+ * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum
+ */
+
+typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
+AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0x00000000,
+AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 0x00000001,
+} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;
+
+/*
+ * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum
+ */
+
+typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
+AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0x00000000,
+AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 0x00000001,
+} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;
+
+/*
+ * AFMT_AUDIO_SRC_CONTROL_SELECT enum
+ */
+
+typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
+AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0x00000000,
+AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 0x00000001,
+AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 0x00000002,
+AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 0x00000003,
+AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 0x00000004,
+AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 0x00000005,
+AFMT_AUDIO_SRC_RESERVED = 0x00000006,
+} AFMT_AUDIO_SRC_CONTROL_SELECT;
+
+/*
+ * DIG_BE_CNTL_MODE enum
+ */
+
+typedef enum DIG_BE_CNTL_MODE {
+DIG_BE_DP_SST_MODE = 0x00000000,
+DIG_BE_RESERVED1 = 0x00000001,
+DIG_BE_TMDS_DVI_MODE = 0x00000002,
+DIG_BE_TMDS_HDMI_MODE = 0x00000003,
+DIG_BE_SDVO_RESERVED = 0x00000004,
+DIG_BE_DP_MST_MODE = 0x00000005,
+DIG_BE_RESERVED2 = 0x00000006,
+DIG_BE_RESERVED3 = 0x00000007,
+} DIG_BE_CNTL_MODE;
+
+/*
+ * DIG_BE_CNTL_HPD_SELECT enum
+ */
+
+typedef enum DIG_BE_CNTL_HPD_SELECT {
+DIG_BE_CNTL_HPD1 = 0x00000000,
+DIG_BE_CNTL_HPD2 = 0x00000001,
+DIG_BE_CNTL_HPD3 = 0x00000002,
+DIG_BE_CNTL_HPD4 = 0x00000003,
+DIG_BE_CNTL_HPD5 = 0x00000004,
+DIG_BE_CNTL_HPD6 = 0x00000005,
+} DIG_BE_CNTL_HPD_SELECT;
+
+/*
+ * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum
+ */
+
+typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
+LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0x00000000,
+LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 0x00000001,
+} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;
+
+/*
+ * TMDS_SYNC_PHASE enum
+ */
+
+typedef enum TMDS_SYNC_PHASE {
+TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0x00000000,
+TMDS_SYNC_PHASE_ON_FRAME_START = 0x00000001,
+} TMDS_SYNC_PHASE;
+
+/*
+ * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum
+ */
+
+typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
+TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0x00000000,
+TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 0x00000001,
+} TMDS_DATA_SYNCHRONIZATION_DSINTSEL;
+
+/*
+ * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum
+ */
+
+typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
+TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0x00000000,
+TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 0x00000001,
+} TMDS_TRANSMITTER_ENABLE_HPD_MASK;
+
+/*
+ * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum
+ */
+
+typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
+TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0x00000000,
+TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 0x00000001,
+} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;
+
+/*
+ * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum
+ */
+
+typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
+TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0x00000000,
+TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 0x00000001,
+} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;
+
+/*
+ * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum
+ */
+
+typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
+TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0x00000000,
+TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 0x00000001,
+TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x00000002,
+TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 0x00000003,
+} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;
+
+/*
+ * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum
+ */
+
+typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
+TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0x00000000,
+TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 0x00000001,
+} TMDS_TRANSMITTER_CONTROL_IDSCKSELA;
+
+/*
+ * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum
+ */
+
+typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
+TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0x00000000,
+TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 0x00000001,
+} TMDS_TRANSMITTER_CONTROL_IDSCKSELB;
+
+/*
+ * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum
+ */
+
+typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
+TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0x00000000,
+TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 0x00000001,
+} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;
+
+/*
+ * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum
+ */
+
+typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
+TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0x00000000,
+TMDS_TRANSMITTER_PLL_RST_ON_HPD = 0x00000001,
+} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;
+
+/*
+ * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum
+ */
+
+typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
+TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0x00000000,
+TMDS_TRANSMITTER_TMCLK_FROM_PADS = 0x00000001,
+} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;
+
+/*
+ * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum
+ */
+
+typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
+TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0x00000000,
+TMDS_TRANSMITTER_TDCLK_FROM_PADS = 0x00000001,
+} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;
+
+/*
+ * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum
+ */
+
+typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
+TMDS_TRANSMITTER_PLLSEL_BY_HW = 0x00000000,
+TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 0x00000001,
+} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;
+
+/*
+ * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum
+ */
+
+typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
+TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0x00000000,
+TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 0x00000001,
+} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;
+
+/*
+ * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum
+ */
+
+typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
+TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0x00000000,
+TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 0x00000001,
+} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;
+
+/*
+ * TMDS_REG_TEST_OUTPUTA_CNTLA enum
+ */
+
+typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
+TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0x00000000,
+TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 0x00000001,
+TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 0x00000002,
+TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 0x00000003,
+} TMDS_REG_TEST_OUTPUTA_CNTLA;
+
+/*
+ * TMDS_REG_TEST_OUTPUTB_CNTLB enum
+ */
+
+typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
+TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0x00000000,
+TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 0x00000001,
+TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 0x00000002,
+TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 0x00000003,
+} TMDS_REG_TEST_OUTPUTB_CNTLB;
+
+/*******************************************************
+ * DCP Enums
+ *******************************************************/
+
+/*
+ * DCP_GRPH_ENABLE enum
+ */
+
+typedef enum DCP_GRPH_ENABLE {
+DCP_GRPH_ENABLE_FALSE = 0x00000000,
+DCP_GRPH_ENABLE_TRUE = 0x00000001,
+} DCP_GRPH_ENABLE;
+
+/*
+ * DCP_GRPH_KEYER_ALPHA_SEL enum
+ */
+
+typedef enum DCP_GRPH_KEYER_ALPHA_SEL {
+DCP_GRPH_KEYER_ALPHA_SEL_FALSE = 0x00000000,
+DCP_GRPH_KEYER_ALPHA_SEL_TRUE = 0x00000001,
+} DCP_GRPH_KEYER_ALPHA_SEL;
+
+/*
+ * DCP_GRPH_DEPTH enum
+ */
+
+typedef enum DCP_GRPH_DEPTH {
+DCP_GRPH_DEPTH_8BPP = 0x00000000,
+DCP_GRPH_DEPTH_16BPP = 0x00000001,
+DCP_GRPH_DEPTH_32BPP = 0x00000002,
+DCP_GRPH_DEPTH_64BPP = 0x00000003,
+} DCP_GRPH_DEPTH;
+
+/*
+ * DCP_GRPH_NUM_BANKS enum
+ */
+
+typedef enum DCP_GRPH_NUM_BANKS {
+DCP_GRPH_NUM_BANKS_1BANK = 0x00000000,
+DCP_GRPH_NUM_BANKS_2BANK = 0x00000001,
+DCP_GRPH_NUM_BANKS_4BANK = 0x00000002,
+DCP_GRPH_NUM_BANKS_8BANK = 0x00000003,
+DCP_GRPH_NUM_BANKS_16BANK = 0x00000004,
+} DCP_GRPH_NUM_BANKS;
+
+/*
+ * DCP_GRPH_NUM_PIPES enum
+ */
+
+typedef enum DCP_GRPH_NUM_PIPES {
+DCP_GRPH_NUM_PIPES_1PIPE = 0x00000000,
+DCP_GRPH_NUM_PIPES_2PIPE = 0x00000001,
+DCP_GRPH_NUM_PIPES_4PIPE = 0x00000002,
+DCP_GRPH_NUM_PIPES_8PIPE = 0x00000003,
+} DCP_GRPH_NUM_PIPES;
+
+/*
+ * DCP_GRPH_FORMAT enum
+ */
+
+typedef enum DCP_GRPH_FORMAT {
+DCP_GRPH_FORMAT_8BPP = 0x00000000,
+DCP_GRPH_FORMAT_16BPP = 0x00000001,
+DCP_GRPH_FORMAT_32BPP = 0x00000002,
+DCP_GRPH_FORMAT_64BPP = 0x00000003,
+} DCP_GRPH_FORMAT;
+
+/*
+ * DCP_GRPH_ADDRESS_TRANSLATION_ENABLE enum
+ */
+
+typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE {
+DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE = 0x00000000,
+DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE = 0x00000001,
+} DCP_GRPH_ADDRESS_TRANSLATION_ENABLE;
+
+/*
+ * DCP_GRPH_SW_MODE enum
+ */
+
+typedef enum DCP_GRPH_SW_MODE {
+DCP_GRPH_SW_MODE_0 = 0x00000000,
+DCP_GRPH_SW_MODE_2 = 0x00000002,
+DCP_GRPH_SW_MODE_3 = 0x00000003,
+DCP_GRPH_SW_MODE_22 = 0x00000016,
+DCP_GRPH_SW_MODE_23 = 0x00000017,
+DCP_GRPH_SW_MODE_26 = 0x0000001a,
+DCP_GRPH_SW_MODE_27 = 0x0000001b,
+DCP_GRPH_SW_MODE_30 = 0x0000001e,
+DCP_GRPH_SW_MODE_31 = 0x0000001f,
+} DCP_GRPH_SW_MODE;
+
+/*
+ * DCP_GRPH_COLOR_EXPANSION_MODE enum
+ */
+
+typedef enum DCP_GRPH_COLOR_EXPANSION_MODE {
+DCP_GRPH_COLOR_EXPANSION_MODE_DEXP = 0x00000000,
+DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP = 0x00000001,
+} DCP_GRPH_COLOR_EXPANSION_MODE;
+
+/*
+ * DCP_GRPH_LUT_10BIT_BYPASS_EN enum
+ */
+
+typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN {
+DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE = 0x00000000,
+DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE = 0x00000001,
+} DCP_GRPH_LUT_10BIT_BYPASS_EN;
+
+/*
+ * DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN enum
+ */
+
+typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN {
+DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE = 0x00000000,
+DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE = 0x00000001,
+} DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN;
+
+/*
+ * DCP_GRPH_ENDIAN_SWAP enum
+ */
+
+typedef enum DCP_GRPH_ENDIAN_SWAP {
+DCP_GRPH_ENDIAN_SWAP_NONE = 0x00000000,
+DCP_GRPH_ENDIAN_SWAP_8IN16 = 0x00000001,
+DCP_GRPH_ENDIAN_SWAP_8IN32 = 0x00000002,
+DCP_GRPH_ENDIAN_SWAP_8IN64 = 0x00000003,
+} DCP_GRPH_ENDIAN_SWAP;
+
+/*
+ * DCP_GRPH_RED_CROSSBAR enum
+ */
+
+typedef enum DCP_GRPH_RED_CROSSBAR {
+DCP_GRPH_RED_CROSSBAR_FROM_R = 0x00000000,
+DCP_GRPH_RED_CROSSBAR_FROM_G = 0x00000001,
+DCP_GRPH_RED_CROSSBAR_FROM_B = 0x00000002,
+DCP_GRPH_RED_CROSSBAR_FROM_A = 0x00000003,
+} DCP_GRPH_RED_CROSSBAR;
+
+/*
+ * DCP_GRPH_GREEN_CROSSBAR enum
+ */
+
+typedef enum DCP_GRPH_GREEN_CROSSBAR {
+DCP_GRPH_GREEN_CROSSBAR_FROM_G = 0x00000000,
+DCP_GRPH_GREEN_CROSSBAR_FROM_B = 0x00000001,
+DCP_GRPH_GREEN_CROSSBAR_FROM_A = 0x00000002,
+DCP_GRPH_GREEN_CROSSBAR_FROM_R = 0x00000003,
+} DCP_GRPH_GREEN_CROSSBAR;
+
+/*
+ * DCP_GRPH_BLUE_CROSSBAR enum
+ */
+
+typedef enum DCP_GRPH_BLUE_CROSSBAR {
+DCP_GRPH_BLUE_CROSSBAR_FROM_B = 0x00000000,
+DCP_GRPH_BLUE_CROSSBAR_FROM_A = 0x00000001,
+DCP_GRPH_BLUE_CROSSBAR_FROM_R = 0x00000002,
+DCP_GRPH_BLUE_CROSSBAR_FROM_G = 0x00000003,
+} DCP_GRPH_BLUE_CROSSBAR;
+
+/*
+ * DCP_GRPH_ALPHA_CROSSBAR enum
+ */
+
+typedef enum DCP_GRPH_ALPHA_CROSSBAR {
+DCP_GRPH_ALPHA_CROSSBAR_FROM_A = 0x00000000,
+DCP_GRPH_ALPHA_CROSSBAR_FROM_R = 0x00000001,
+DCP_GRPH_ALPHA_CROSSBAR_FROM_G = 0x00000002,
+DCP_GRPH_ALPHA_CROSSBAR_FROM_B = 0x00000003,
+} DCP_GRPH_ALPHA_CROSSBAR;
+
+/*
+ * DCP_GRPH_PRIMARY_DFQ_ENABLE enum
+ */
+
+typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE {
+DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE = 0x00000000,
+DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE = 0x00000001,
+} DCP_GRPH_PRIMARY_DFQ_ENABLE;
+
+/*
+ * DCP_GRPH_SECONDARY_DFQ_ENABLE enum
+ */
+
+typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE {
+DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE = 0x00000000,
+DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE = 0x00000001,
+} DCP_GRPH_SECONDARY_DFQ_ENABLE;
+
+/*
+ * DCP_GRPH_INPUT_GAMMA_MODE enum
+ */
+
+typedef enum DCP_GRPH_INPUT_GAMMA_MODE {
+DCP_GRPH_INPUT_GAMMA_MODE_LUT = 0x00000000,
+DCP_GRPH_INPUT_GAMMA_MODE_BYPASS = 0x00000001,
+} DCP_GRPH_INPUT_GAMMA_MODE;
+
+/*
+ * DCP_GRPH_MODE_UPDATE_PENDING enum
+ */
+
+typedef enum DCP_GRPH_MODE_UPDATE_PENDING {
+DCP_GRPH_MODE_UPDATE_PENDING_FALSE = 0x00000000,
+DCP_GRPH_MODE_UPDATE_PENDING_TRUE = 0x00000001,
+} DCP_GRPH_MODE_UPDATE_PENDING;
+
+/*
+ * DCP_GRPH_MODE_UPDATE_TAKEN enum
+ */
+
+typedef enum DCP_GRPH_MODE_UPDATE_TAKEN {
+DCP_GRPH_MODE_UPDATE_TAKEN_FALSE = 0x00000000,
+DCP_GRPH_MODE_UPDATE_TAKEN_TRUE = 0x00000001,
+} DCP_GRPH_MODE_UPDATE_TAKEN;
+
+/*
+ * DCP_GRPH_SURFACE_UPDATE_PENDING enum
+ */
+
+typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING {
+DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE = 0x00000000,
+DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE = 0x00000001,
+} DCP_GRPH_SURFACE_UPDATE_PENDING;
+
+/*
+ * DCP_GRPH_SURFACE_UPDATE_TAKEN enum
+ */
+
+typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN {
+DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE = 0x00000000,
+DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE = 0x00000001,
+} DCP_GRPH_SURFACE_UPDATE_TAKEN;
+
+/*
+ * DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE enum
+ */
+
+typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE {
+DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE = 0x00000000,
+DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE = 0x00000001,
+} DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE;
+
+/*
+ * DCP_GRPH_UPDATE_LOCK enum
+ */
+
+typedef enum DCP_GRPH_UPDATE_LOCK {
+DCP_GRPH_UPDATE_LOCK_FALSE = 0x00000000,
+DCP_GRPH_UPDATE_LOCK_TRUE = 0x00000001,
+} DCP_GRPH_UPDATE_LOCK;
+
+/*
+ * DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK enum
+ */
+
+typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
+DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE = 0x00000000,
+DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE = 0x00000001,
+} DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
+
+/*
+ * DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE enum
+ */
+
+typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
+DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x00000000,
+DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x00000001,
+} DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
+
+/*
+ * DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE enum
+ */
+
+typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
+DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x00000000,
+DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x00000001,
+} DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
+
+/*
+ * DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN enum
+ */
+
+typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN {
+DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE = 0x00000000,
+DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE = 0x00000001,
+} DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
+
+/*
+ * DCP_GRPH_XDMA_SUPER_AA_EN enum
+ */
+
+typedef enum DCP_GRPH_XDMA_SUPER_AA_EN {
+DCP_GRPH_XDMA_SUPER_AA_EN_FALSE = 0x00000000,
+DCP_GRPH_XDMA_SUPER_AA_EN_TRUE = 0x00000001,
+} DCP_GRPH_XDMA_SUPER_AA_EN;
+
+/*
+ * DCP_GRPH_DFQ_RESET enum
+ */
+
+typedef enum DCP_GRPH_DFQ_RESET {
+DCP_GRPH_DFQ_RESET_FALSE = 0x00000000,
+DCP_GRPH_DFQ_RESET_TRUE = 0x00000001,
+} DCP_GRPH_DFQ_RESET;
+
+/*
+ * DCP_GRPH_DFQ_SIZE enum
+ */
+
+typedef enum DCP_GRPH_DFQ_SIZE {
+DCP_GRPH_DFQ_SIZE_DEEP1 = 0x00000000,
+DCP_GRPH_DFQ_SIZE_DEEP2 = 0x00000001,
+DCP_GRPH_DFQ_SIZE_DEEP3 = 0x00000002,
+DCP_GRPH_DFQ_SIZE_DEEP4 = 0x00000003,
+DCP_GRPH_DFQ_SIZE_DEEP5 = 0x00000004,
+DCP_GRPH_DFQ_SIZE_DEEP6 = 0x00000005,
+DCP_GRPH_DFQ_SIZE_DEEP7 = 0x00000006,
+DCP_GRPH_DFQ_SIZE_DEEP8 = 0x00000007,
+} DCP_GRPH_DFQ_SIZE;
+
+/*
+ * DCP_GRPH_DFQ_MIN_FREE_ENTRIES enum
+ */
+
+typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES {
+DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1 = 0x00000000,
+DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2 = 0x00000001,
+DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3 = 0x00000002,
+DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4 = 0x00000003,
+DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5 = 0x00000004,
+DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6 = 0x00000005,
+DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7 = 0x00000006,
+DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8 = 0x00000007,
+} DCP_GRPH_DFQ_MIN_FREE_ENTRIES;
+
+/*
+ * DCP_GRPH_DFQ_RESET_ACK enum
+ */
+
+typedef enum DCP_GRPH_DFQ_RESET_ACK {
+DCP_GRPH_DFQ_RESET_ACK_FALSE = 0x00000000,
+DCP_GRPH_DFQ_RESET_ACK_TRUE = 0x00000001,
+} DCP_GRPH_DFQ_RESET_ACK;
+
+/*
+ * DCP_GRPH_PFLIP_INT_CLEAR enum
+ */
+
+typedef enum DCP_GRPH_PFLIP_INT_CLEAR {
+DCP_GRPH_PFLIP_INT_CLEAR_FALSE = 0x00000000,
+DCP_GRPH_PFLIP_INT_CLEAR_TRUE = 0x00000001,
+} DCP_GRPH_PFLIP_INT_CLEAR;
+
+/*
+ * DCP_GRPH_PFLIP_INT_MASK enum
+ */
+
+typedef enum DCP_GRPH_PFLIP_INT_MASK {
+DCP_GRPH_PFLIP_INT_MASK_FALSE = 0x00000000,
+DCP_GRPH_PFLIP_INT_MASK_TRUE = 0x00000001,
+} DCP_GRPH_PFLIP_INT_MASK;
+
+/*
+ * DCP_GRPH_PFLIP_INT_TYPE enum
+ */
+
+typedef enum DCP_GRPH_PFLIP_INT_TYPE {
+DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL = 0x00000000,
+DCP_GRPH_PFLIP_INT_TYPE_PULSE = 0x00000001,
+} DCP_GRPH_PFLIP_INT_TYPE;
+
+/*
+ * DCP_GRPH_PRESCALE_SELECT enum
+ */
+
+typedef enum DCP_GRPH_PRESCALE_SELECT {
+DCP_GRPH_PRESCALE_SELECT_FIXED = 0x00000000,
+DCP_GRPH_PRESCALE_SELECT_FLOATING = 0x00000001,
+} DCP_GRPH_PRESCALE_SELECT;
+
+/*
+ * DCP_GRPH_PRESCALE_R_SIGN enum
+ */
+
+typedef enum DCP_GRPH_PRESCALE_R_SIGN {
+DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED = 0x00000000,
+DCP_GRPH_PRESCALE_R_SIGN_SIGNED = 0x00000001,
+} DCP_GRPH_PRESCALE_R_SIGN;
+
+/*
+ * DCP_GRPH_PRESCALE_G_SIGN enum
+ */
+
+typedef enum DCP_GRPH_PRESCALE_G_SIGN {
+DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED = 0x00000000,
+DCP_GRPH_PRESCALE_G_SIGN_SIGNED = 0x00000001,
+} DCP_GRPH_PRESCALE_G_SIGN;
+
+/*
+ * DCP_GRPH_PRESCALE_B_SIGN enum
+ */
+
+typedef enum DCP_GRPH_PRESCALE_B_SIGN {
+DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED = 0x00000000,
+DCP_GRPH_PRESCALE_B_SIGN_SIGNED = 0x00000001,
+} DCP_GRPH_PRESCALE_B_SIGN;
+
+/*
+ * DCP_GRPH_PRESCALE_BYPASS enum
+ */
+
+typedef enum DCP_GRPH_PRESCALE_BYPASS {
+DCP_GRPH_PRESCALE_BYPASS_FALSE = 0x00000000,
+DCP_GRPH_PRESCALE_BYPASS_TRUE = 0x00000001,
+} DCP_GRPH_PRESCALE_BYPASS;
+
+/*
+ * DCP_INPUT_CSC_GRPH_MODE enum
+ */
+
+typedef enum DCP_INPUT_CSC_GRPH_MODE {
+DCP_INPUT_CSC_GRPH_MODE_BYPASS = 0x00000000,
+DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF = 0x00000001,
+DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF = 0x00000002,
+DCP_INPUT_CSC_GRPH_MODE_RESERVED = 0x00000003,
+} DCP_INPUT_CSC_GRPH_MODE;
+
+/*
+ * DCP_OUTPUT_CSC_GRPH_MODE enum
+ */
+
+typedef enum DCP_OUTPUT_CSC_GRPH_MODE {
+DCP_OUTPUT_CSC_GRPH_MODE_BYPASS = 0x00000000,
+DCP_OUTPUT_CSC_GRPH_MODE_RGB = 0x00000001,
+DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601 = 0x00000002,
+DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709 = 0x00000003,
+DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF = 0x00000004,
+DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF = 0x00000005,
+DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0 = 0x00000006,
+DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1 = 0x00000007,
+} DCP_OUTPUT_CSC_GRPH_MODE;
+
+/*
+ * DCP_DENORM_MODE enum
+ */
+
+typedef enum DCP_DENORM_MODE {
+DCP_DENORM_MODE_UNITY = 0x00000000,
+DCP_DENORM_MODE_6BIT = 0x00000001,
+DCP_DENORM_MODE_8BIT = 0x00000002,
+DCP_DENORM_MODE_10BIT = 0x00000003,
+DCP_DENORM_MODE_11BIT = 0x00000004,
+DCP_DENORM_MODE_12BIT = 0x00000005,
+DCP_DENORM_MODE_RESERVED0 = 0x00000006,
+DCP_DENORM_MODE_RESERVED1 = 0x00000007,
+} DCP_DENORM_MODE;
+
+/*
+ * DCP_DENORM_14BIT_OUT enum
+ */
+
+typedef enum DCP_DENORM_14BIT_OUT {
+DCP_DENORM_14BIT_OUT_FALSE = 0x00000000,
+DCP_DENORM_14BIT_OUT_TRUE = 0x00000001,
+} DCP_DENORM_14BIT_OUT;
+
+/*
+ * DCP_OUT_ROUND_TRUNC_MODE enum
+ */
+
+typedef enum DCP_OUT_ROUND_TRUNC_MODE {
+DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12 = 0x00000000,
+DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11 = 0x00000001,
+DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10 = 0x00000002,
+DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9 = 0x00000003,
+DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8 = 0x00000004,
+DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED = 0x00000005,
+DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14 = 0x00000006,
+DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13 = 0x00000007,
+DCP_OUT_ROUND_TRUNC_MODE_ROUND_12 = 0x00000008,
+DCP_OUT_ROUND_TRUNC_MODE_ROUND_11 = 0x00000009,
+DCP_OUT_ROUND_TRUNC_MODE_ROUND_10 = 0x0000000a,
+DCP_OUT_ROUND_TRUNC_MODE_ROUND_9 = 0x0000000b,
+DCP_OUT_ROUND_TRUNC_MODE_ROUND_8 = 0x0000000c,
+DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED = 0x0000000d,
+DCP_OUT_ROUND_TRUNC_MODE_ROUND_14 = 0x0000000e,
+DCP_OUT_ROUND_TRUNC_MODE_ROUND_13 = 0x0000000f,
+} DCP_OUT_ROUND_TRUNC_MODE;
+
+/*
+ * DCP_KEY_MODE enum
+ */
+
+typedef enum DCP_KEY_MODE {
+DCP_KEY_MODE_ALPHA0 = 0x00000000,
+DCP_KEY_MODE_ALPHA1 = 0x00000001,
+DCP_KEY_MODE_IN_RANGE_ALPHA1 = 0x00000002,
+DCP_KEY_MODE_IN_RANGE_ALPHA0 = 0x00000003,
+} DCP_KEY_MODE;
+
+/*
+ * DCP_GRPH_DEGAMMA_MODE enum
+ */
+
+typedef enum DCP_GRPH_DEGAMMA_MODE {
+DCP_GRPH_DEGAMMA_MODE_BYPASS = 0x00000000,
+DCP_GRPH_DEGAMMA_MODE_ROMA = 0x00000001,
+DCP_GRPH_DEGAMMA_MODE_ROMB = 0x00000002,
+DCP_GRPH_DEGAMMA_MODE_RESERVED = 0x00000003,
+} DCP_GRPH_DEGAMMA_MODE;
+
+/*
+ * DCP_CURSOR_DEGAMMA_MODE enum
+ */
+
+typedef enum DCP_CURSOR_DEGAMMA_MODE {
+DCP_CURSOR_DEGAMMA_MODE_BYPASS = 0x00000000,
+DCP_CURSOR_DEGAMMA_MODE_ROMA = 0x00000001,
+DCP_CURSOR_DEGAMMA_MODE_ROMB = 0x00000002,
+DCP_CURSOR_DEGAMMA_MODE_RESERVED = 0x00000003,
+} DCP_CURSOR_DEGAMMA_MODE;
+
+/*
+ * DCP_GRPH_GAMUT_REMAP_MODE enum
+ */
+
+typedef enum DCP_GRPH_GAMUT_REMAP_MODE {
+DCP_GRPH_GAMUT_REMAP_MODE_BYPASS = 0x00000000,
+DCP_GRPH_GAMUT_REMAP_MODE_ROMA = 0x00000001,
+DCP_GRPH_GAMUT_REMAP_MODE_ROMB = 0x00000002,
+DCP_GRPH_GAMUT_REMAP_MODE_RESERVED = 0x00000003,
+} DCP_GRPH_GAMUT_REMAP_MODE;
+
+/*
+ * DCP_SPATIAL_DITHER_EN enum
+ */
+
+typedef enum DCP_SPATIAL_DITHER_EN {
+DCP_SPATIAL_DITHER_EN_FALSE = 0x00000000,
+DCP_SPATIAL_DITHER_EN_TRUE = 0x00000001,
+} DCP_SPATIAL_DITHER_EN;
+
+/*
+ * DCP_SPATIAL_DITHER_MODE enum
+ */
+
+typedef enum DCP_SPATIAL_DITHER_MODE {
+DCP_SPATIAL_DITHER_MODE_BYPASS = 0x00000000,
+DCP_SPATIAL_DITHER_MODE_ROMA = 0x00000001,
+DCP_SPATIAL_DITHER_MODE_ROMB = 0x00000002,
+DCP_SPATIAL_DITHER_MODE_RESERVED = 0x00000003,
+} DCP_SPATIAL_DITHER_MODE;
+
+/*
+ * DCP_SPATIAL_DITHER_DEPTH enum
+ */
+
+typedef enum DCP_SPATIAL_DITHER_DEPTH {
+DCP_SPATIAL_DITHER_DEPTH_30BPP = 0x00000000,
+DCP_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001,
+DCP_SPATIAL_DITHER_DEPTH_36BPP = 0x00000002,
+DCP_SPATIAL_DITHER_DEPTH_UNDEFINED = 0x00000003,
+} DCP_SPATIAL_DITHER_DEPTH;
+
+/*
+ * DCP_FRAME_RANDOM_ENABLE enum
+ */
+
+typedef enum DCP_FRAME_RANDOM_ENABLE {
+DCP_FRAME_RANDOM_ENABLE_FALSE = 0x00000000,
+DCP_FRAME_RANDOM_ENABLE_TRUE = 0x00000001,
+} DCP_FRAME_RANDOM_ENABLE;
+
+/*
+ * DCP_RGB_RANDOM_ENABLE enum
+ */
+
+typedef enum DCP_RGB_RANDOM_ENABLE {
+DCP_RGB_RANDOM_ENABLE_FALSE = 0x00000000,
+DCP_RGB_RANDOM_ENABLE_TRUE = 0x00000001,
+} DCP_RGB_RANDOM_ENABLE;
+
+/*
+ * DCP_HIGHPASS_RANDOM_ENABLE enum
+ */
+
+typedef enum DCP_HIGHPASS_RANDOM_ENABLE {
+DCP_HIGHPASS_RANDOM_ENABLE_FALSE = 0x00000000,
+DCP_HIGHPASS_RANDOM_ENABLE_TRUE = 0x00000001,
+} DCP_HIGHPASS_RANDOM_ENABLE;
+
+/*
+ * DCP_CURSOR_EN enum
+ */
+
+typedef enum DCP_CURSOR_EN {
+DCP_CURSOR_EN_FALSE = 0x00000000,
+DCP_CURSOR_EN_TRUE = 0x00000001,
+} DCP_CURSOR_EN;
+
+/*
+ * DCP_CUR_INV_TRANS_CLAMP enum
+ */
+
+typedef enum DCP_CUR_INV_TRANS_CLAMP {
+DCP_CUR_INV_TRANS_CLAMP_FALSE = 0x00000000,
+DCP_CUR_INV_TRANS_CLAMP_TRUE = 0x00000001,
+} DCP_CUR_INV_TRANS_CLAMP;
+
+/*
+ * DCP_CURSOR_MODE enum
+ */
+
+typedef enum DCP_CURSOR_MODE {
+DCP_CURSOR_MODE_MONO_2BPP = 0x00000000,
+DCP_CURSOR_MODE_24BPP_1BIT = 0x00000001,
+DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI = 0x00000002,
+DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI = 0x00000003,
+} DCP_CURSOR_MODE;
+
+/*
+ * DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM enum
+ */
+
+typedef enum DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM {
+DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE = 0x00000000,
+DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO = 0x00000001,
+} DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM;
+
+/*
+ * DCP_CURSOR_2X_MAGNIFY enum
+ */
+
+typedef enum DCP_CURSOR_2X_MAGNIFY {
+DCP_CURSOR_2X_MAGNIFY_FALSE = 0x00000000,
+DCP_CURSOR_2X_MAGNIFY_TRUE = 0x00000001,
+} DCP_CURSOR_2X_MAGNIFY;
+
+/*
+ * DCP_CURSOR_FORCE_MC_ON enum
+ */
+
+typedef enum DCP_CURSOR_FORCE_MC_ON {
+DCP_CURSOR_FORCE_MC_ON_FALSE = 0x00000000,
+DCP_CURSOR_FORCE_MC_ON_TRUE = 0x00000001,
+} DCP_CURSOR_FORCE_MC_ON;
+
+/*
+ * DCP_CURSOR_URGENT_CONTROL enum
+ */
+
+typedef enum DCP_CURSOR_URGENT_CONTROL {
+DCP_CURSOR_URGENT_CONTROL_MODE_0 = 0x00000000,
+DCP_CURSOR_URGENT_CONTROL_MODE_1 = 0x00000001,
+DCP_CURSOR_URGENT_CONTROL_MODE_2 = 0x00000002,
+DCP_CURSOR_URGENT_CONTROL_MODE_3 = 0x00000003,
+DCP_CURSOR_URGENT_CONTROL_MODE_4 = 0x00000004,
+} DCP_CURSOR_URGENT_CONTROL;
+
+/*
+ * DCP_CURSOR_UPDATE_PENDING enum
+ */
+
+typedef enum DCP_CURSOR_UPDATE_PENDING {
+DCP_CURSOR_UPDATE_PENDING_FALSE = 0x00000000,
+DCP_CURSOR_UPDATE_PENDING_TRUE = 0x00000001,
+} DCP_CURSOR_UPDATE_PENDING;
+
+/*
+ * DCP_CURSOR_UPDATE_TAKEN enum
+ */
+
+typedef enum DCP_CURSOR_UPDATE_TAKEN {
+DCP_CURSOR_UPDATE_TAKEN_FALSE = 0x00000000,
+DCP_CURSOR_UPDATE_TAKEN_TRUE = 0x00000001,
+} DCP_CURSOR_UPDATE_TAKEN;
+
+/*
+ * DCP_CURSOR_UPDATE_LOCK enum
+ */
+
+typedef enum DCP_CURSOR_UPDATE_LOCK {
+DCP_CURSOR_UPDATE_LOCK_FALSE = 0x00000000,
+DCP_CURSOR_UPDATE_LOCK_TRUE = 0x00000001,
+} DCP_CURSOR_UPDATE_LOCK;
+
+/*
+ * DCP_CURSOR_DISABLE_MULTIPLE_UPDATE enum
+ */
+
+typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE {
+DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE = 0x00000000,
+DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE = 0x00000001,
+} DCP_CURSOR_DISABLE_MULTIPLE_UPDATE;
+
+/*
+ * DCP_CURSOR_UPDATE_STEREO_MODE enum
+ */
+
+typedef enum DCP_CURSOR_UPDATE_STEREO_MODE {
+DCP_CURSOR_UPDATE_STEREO_MODE_BOTH = 0x00000000,
+DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY = 0x00000001,
+DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED = 0x00000002,
+DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY = 0x00000003,
+} DCP_CURSOR_UPDATE_STEREO_MODE;
+
+/*
+ * DCP_CUR2_INV_TRANS_CLAMP enum
+ */
+
+typedef enum DCP_CUR2_INV_TRANS_CLAMP {
+DCP_CUR2_INV_TRANS_CLAMP_FALSE = 0x00000000,
+DCP_CUR2_INV_TRANS_CLAMP_TRUE = 0x00000001,
+} DCP_CUR2_INV_TRANS_CLAMP;
+
+/*
+ * DCP_CUR_REQUEST_FILTER_DIS enum
+ */
+
+typedef enum DCP_CUR_REQUEST_FILTER_DIS {
+DCP_CUR_REQUEST_FILTER_DIS_FALSE = 0x00000000,
+DCP_CUR_REQUEST_FILTER_DIS_TRUE = 0x00000001,
+} DCP_CUR_REQUEST_FILTER_DIS;
+
+/*
+ * DCP_CURSOR_STEREO_EN enum
+ */
+
+typedef enum DCP_CURSOR_STEREO_EN {
+DCP_CURSOR_STEREO_EN_FALSE = 0x00000000,
+DCP_CURSOR_STEREO_EN_TRUE = 0x00000001,
+} DCP_CURSOR_STEREO_EN;
+
+/*
+ * DCP_CURSOR_STEREO_OFFSET_YNX enum
+ */
+
+typedef enum DCP_CURSOR_STEREO_OFFSET_YNX {
+DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION = 0x00000000,
+DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION = 0x00000001,
+} DCP_CURSOR_STEREO_OFFSET_YNX;
+
+/*
+ * DCP_DC_LUT_RW_MODE enum
+ */
+
+typedef enum DCP_DC_LUT_RW_MODE {
+DCP_DC_LUT_RW_MODE_256_ENTRY = 0x00000000,
+DCP_DC_LUT_RW_MODE_PWL = 0x00000001,
+} DCP_DC_LUT_RW_MODE;
+
+/*
+ * DCP_DC_LUT_VGA_ACCESS_ENABLE enum
+ */
+
+typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE {
+DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE = 0x00000000,
+DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE = 0x00000001,
+} DCP_DC_LUT_VGA_ACCESS_ENABLE;
+
+/*
+ * DCP_DC_LUT_AUTOFILL enum
+ */
+
+typedef enum DCP_DC_LUT_AUTOFILL {
+DCP_DC_LUT_AUTOFILL_FALSE = 0x00000000,
+DCP_DC_LUT_AUTOFILL_TRUE = 0x00000001,
+} DCP_DC_LUT_AUTOFILL;
+
+/*
+ * DCP_DC_LUT_AUTOFILL_DONE enum
+ */
+
+typedef enum DCP_DC_LUT_AUTOFILL_DONE {
+DCP_DC_LUT_AUTOFILL_DONE_FALSE = 0x00000000,
+DCP_DC_LUT_AUTOFILL_DONE_TRUE = 0x00000001,
+} DCP_DC_LUT_AUTOFILL_DONE;
+
+/*
+ * DCP_DC_LUT_INC_B enum
+ */
+
+typedef enum DCP_DC_LUT_INC_B {
+DCP_DC_LUT_INC_B_NA = 0x00000000,
+DCP_DC_LUT_INC_B_2 = 0x00000001,
+DCP_DC_LUT_INC_B_4 = 0x00000002,
+DCP_DC_LUT_INC_B_8 = 0x00000003,
+DCP_DC_LUT_INC_B_16 = 0x00000004,
+DCP_DC_LUT_INC_B_32 = 0x00000005,
+DCP_DC_LUT_INC_B_64 = 0x00000006,
+DCP_DC_LUT_INC_B_128 = 0x00000007,
+DCP_DC_LUT_INC_B_256 = 0x00000008,
+DCP_DC_LUT_INC_B_512 = 0x00000009,
+} DCP_DC_LUT_INC_B;
+
+/*
+ * DCP_DC_LUT_DATA_B_SIGNED_EN enum
+ */
+
+typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN {
+DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE = 0x00000000,
+DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE = 0x00000001,
+} DCP_DC_LUT_DATA_B_SIGNED_EN;
+
+/*
+ * DCP_DC_LUT_DATA_B_FLOAT_POINT_EN enum
+ */
+
+typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN {
+DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE = 0x00000000,
+DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE = 0x00000001,
+} DCP_DC_LUT_DATA_B_FLOAT_POINT_EN;
+
+/*
+ * DCP_DC_LUT_DATA_B_FORMAT enum
+ */
+
+typedef enum DCP_DC_LUT_DATA_B_FORMAT {
+DCP_DC_LUT_DATA_B_FORMAT_U0P10 = 0x00000000,
+DCP_DC_LUT_DATA_B_FORMAT_S1P10 = 0x00000001,
+DCP_DC_LUT_DATA_B_FORMAT_U1P11 = 0x00000002,
+DCP_DC_LUT_DATA_B_FORMAT_U0P12 = 0x00000003,
+} DCP_DC_LUT_DATA_B_FORMAT;
+
+/*
+ * DCP_DC_LUT_INC_G enum
+ */
+
+typedef enum DCP_DC_LUT_INC_G {
+DCP_DC_LUT_INC_G_NA = 0x00000000,
+DCP_DC_LUT_INC_G_2 = 0x00000001,
+DCP_DC_LUT_INC_G_4 = 0x00000002,
+DCP_DC_LUT_INC_G_8 = 0x00000003,
+DCP_DC_LUT_INC_G_16 = 0x00000004,
+DCP_DC_LUT_INC_G_32 = 0x00000005,
+DCP_DC_LUT_INC_G_64 = 0x00000006,
+DCP_DC_LUT_INC_G_128 = 0x00000007,
+DCP_DC_LUT_INC_G_256 = 0x00000008,
+DCP_DC_LUT_INC_G_512 = 0x00000009,
+} DCP_DC_LUT_INC_G;
+
+/*
+ * DCP_DC_LUT_DATA_G_SIGNED_EN enum
+ */
+
+typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN {
+DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE = 0x00000000,
+DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE = 0x00000001,
+} DCP_DC_LUT_DATA_G_SIGNED_EN;
+
+/*
+ * DCP_DC_LUT_DATA_G_FLOAT_POINT_EN enum
+ */
+
+typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN {
+DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE = 0x00000000,
+DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE = 0x00000001,
+} DCP_DC_LUT_DATA_G_FLOAT_POINT_EN;
+
+/*
+ * DCP_DC_LUT_DATA_G_FORMAT enum
+ */
+
+typedef enum DCP_DC_LUT_DATA_G_FORMAT {
+DCP_DC_LUT_DATA_G_FORMAT_U0P10 = 0x00000000,
+DCP_DC_LUT_DATA_G_FORMAT_S1P10 = 0x00000001,
+DCP_DC_LUT_DATA_G_FORMAT_U1P11 = 0x00000002,
+DCP_DC_LUT_DATA_G_FORMAT_U0P12 = 0x00000003,
+} DCP_DC_LUT_DATA_G_FORMAT;
+
+/*
+ * DCP_DC_LUT_INC_R enum
+ */
+
+typedef enum DCP_DC_LUT_INC_R {
+DCP_DC_LUT_INC_R_NA = 0x00000000,
+DCP_DC_LUT_INC_R_2 = 0x00000001,
+DCP_DC_LUT_INC_R_4 = 0x00000002,
+DCP_DC_LUT_INC_R_8 = 0x00000003,
+DCP_DC_LUT_INC_R_16 = 0x00000004,
+DCP_DC_LUT_INC_R_32 = 0x00000005,
+DCP_DC_LUT_INC_R_64 = 0x00000006,
+DCP_DC_LUT_INC_R_128 = 0x00000007,
+DCP_DC_LUT_INC_R_256 = 0x00000008,
+DCP_DC_LUT_INC_R_512 = 0x00000009,
+} DCP_DC_LUT_INC_R;
+
+/*
+ * DCP_DC_LUT_DATA_R_SIGNED_EN enum
+ */
+
+typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN {
+DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE = 0x00000000,
+DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE = 0x00000001,
+} DCP_DC_LUT_DATA_R_SIGNED_EN;
+
+/*
+ * DCP_DC_LUT_DATA_R_FLOAT_POINT_EN enum
+ */
+
+typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN {
+DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE = 0x00000000,
+DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE = 0x00000001,
+} DCP_DC_LUT_DATA_R_FLOAT_POINT_EN;
+
+/*
+ * DCP_DC_LUT_DATA_R_FORMAT enum
+ */
+
+typedef enum DCP_DC_LUT_DATA_R_FORMAT {
+DCP_DC_LUT_DATA_R_FORMAT_U0P10 = 0x00000000,
+DCP_DC_LUT_DATA_R_FORMAT_S1P10 = 0x00000001,
+DCP_DC_LUT_DATA_R_FORMAT_U1P11 = 0x00000002,
+DCP_DC_LUT_DATA_R_FORMAT_U0P12 = 0x00000003,
+} DCP_DC_LUT_DATA_R_FORMAT;
+
+/*
+ * DCP_CRC_ENABLE enum
+ */
+
+typedef enum DCP_CRC_ENABLE {
+DCP_CRC_ENABLE_FALSE = 0x00000000,
+DCP_CRC_ENABLE_TRUE = 0x00000001,
+} DCP_CRC_ENABLE;
+
+/*
+ * DCP_CRC_SOURCE_SEL enum
+ */
+
+typedef enum DCP_CRC_SOURCE_SEL {
+DCP_CRC_SOURCE_SEL_OUTPUT_PIX = 0x00000000,
+DCP_CRC_SOURCE_SEL_INPUT_L32 = 0x00000001,
+DCP_CRC_SOURCE_SEL_INPUT_H32 = 0x00000002,
+DCP_CRC_SOURCE_SEL_OUTPUT_CNTL = 0x00000004,
+} DCP_CRC_SOURCE_SEL;
+
+/*
+ * DCP_CRC_LINE_SEL enum
+ */
+
+typedef enum DCP_CRC_LINE_SEL {
+DCP_CRC_LINE_SEL_RESERVED = 0x00000000,
+DCP_CRC_LINE_SEL_EVEN = 0x00000001,
+DCP_CRC_LINE_SEL_ODD = 0x00000002,
+DCP_CRC_LINE_SEL_BOTH = 0x00000003,
+} DCP_CRC_LINE_SEL;
+
+/*
+ * DCP_GRPH_FLIP_RATE enum
+ */
+
+typedef enum DCP_GRPH_FLIP_RATE {
+DCP_GRPH_FLIP_RATE_1FRAME = 0x00000000,
+DCP_GRPH_FLIP_RATE_2FRAME = 0x00000001,
+DCP_GRPH_FLIP_RATE_3FRAME = 0x00000002,
+DCP_GRPH_FLIP_RATE_4FRAME = 0x00000003,
+DCP_GRPH_FLIP_RATE_5FRAME = 0x00000004,
+DCP_GRPH_FLIP_RATE_6FRAME = 0x00000005,
+DCP_GRPH_FLIP_RATE_7FRAME = 0x00000006,
+DCP_GRPH_FLIP_RATE_8FRAME = 0x00000007,
+} DCP_GRPH_FLIP_RATE;
+
+/*
+ * DCP_GRPH_FLIP_RATE_ENABLE enum
+ */
+
+typedef enum DCP_GRPH_FLIP_RATE_ENABLE {
+DCP_GRPH_FLIP_RATE_ENABLE_FALSE = 0x00000000,
+DCP_GRPH_FLIP_RATE_ENABLE_TRUE = 0x00000001,
+} DCP_GRPH_FLIP_RATE_ENABLE;
+
+/*
+ * DCP_GSL0_EN enum
+ */
+
+typedef enum DCP_GSL0_EN {
+DCP_GSL0_EN_FALSE = 0x00000000,
+DCP_GSL0_EN_TRUE = 0x00000001,
+} DCP_GSL0_EN;
+
+/*
+ * DCP_GSL1_EN enum
+ */
+
+typedef enum DCP_GSL1_EN {
+DCP_GSL1_EN_FALSE = 0x00000000,
+DCP_GSL1_EN_TRUE = 0x00000001,
+} DCP_GSL1_EN;
+
+/*
+ * DCP_GSL2_EN enum
+ */
+
+typedef enum DCP_GSL2_EN {
+DCP_GSL2_EN_FALSE = 0x00000000,
+DCP_GSL2_EN_TRUE = 0x00000001,
+} DCP_GSL2_EN;
+
+/*
+ * DCP_GSL_MASTER_EN enum
+ */
+
+typedef enum DCP_GSL_MASTER_EN {
+DCP_GSL_MASTER_EN_FALSE = 0x00000000,
+DCP_GSL_MASTER_EN_TRUE = 0x00000001,
+} DCP_GSL_MASTER_EN;
+
+/*
+ * DCP_GSL_XDMA_GROUP enum
+ */
+
+typedef enum DCP_GSL_XDMA_GROUP {
+DCP_GSL_XDMA_GROUP_VSYNC = 0x00000000,
+DCP_GSL_XDMA_GROUP_HSYNC0 = 0x00000001,
+DCP_GSL_XDMA_GROUP_HSYNC1 = 0x00000002,
+DCP_GSL_XDMA_GROUP_HSYNC2 = 0x00000003,
+} DCP_GSL_XDMA_GROUP;
+
+/*
+ * DCP_GSL_XDMA_GROUP_UNDERFLOW_EN enum
+ */
+
+typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN {
+DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE = 0x00000000,
+DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE = 0x00000001,
+} DCP_GSL_XDMA_GROUP_UNDERFLOW_EN;
+
+/*
+ * DCP_GSL_SYNC_SOURCE enum
+ */
+
+typedef enum DCP_GSL_SYNC_SOURCE {
+DCP_GSL_SYNC_SOURCE_FLIP = 0x00000000,
+DCP_GSL_SYNC_SOURCE_PHASE0 = 0x00000001,
+DCP_GSL_SYNC_SOURCE_RESET = 0x00000002,
+DCP_GSL_SYNC_SOURCE_PHASE1 = 0x00000003,
+} DCP_GSL_SYNC_SOURCE;
+
+/*
+ * DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC enum
+ */
+
+typedef enum DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC {
+DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_DIS = 0x00000000,
+DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_EN = 0x00000001,
+} DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC;
+
+/*
+ * DCP_GSL_DELAY_SURFACE_UPDATE_PENDING enum
+ */
+
+typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING {
+DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE = 0x00000000,
+DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE = 0x00000001,
+} DCP_GSL_DELAY_SURFACE_UPDATE_PENDING;
+
+/*
+ * DCP_TEST_DEBUG_WRITE_EN enum
+ */
+
+typedef enum DCP_TEST_DEBUG_WRITE_EN {
+DCP_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
+DCP_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
+} DCP_TEST_DEBUG_WRITE_EN;
+
+/*
+ * DCP_GRPH_STEREOSYNC_FLIP_EN enum
+ */
+
+typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN {
+DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE = 0x00000000,
+DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE = 0x00000001,
+} DCP_GRPH_STEREOSYNC_FLIP_EN;
+
+/*
+ * DCP_GRPH_STEREOSYNC_FLIP_MODE enum
+ */
+
+typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE {
+DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP = 0x00000000,
+DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0 = 0x00000001,
+DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET = 0x00000002,
+DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1 = 0x00000003,
+} DCP_GRPH_STEREOSYNC_FLIP_MODE;
+
+/*
+ * DCP_GRPH_STEREOSYNC_SELECT_DISABLE enum
+ */
+
+typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE {
+DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE = 0x00000000,
+DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE = 0x00000001,
+} DCP_GRPH_STEREOSYNC_SELECT_DISABLE;
+
+/*
+ * DCP_GRPH_ROTATION_ANGLE enum
+ */
+
+typedef enum DCP_GRPH_ROTATION_ANGLE {
+DCP_GRPH_ROTATION_ANGLE_0 = 0x00000000,
+DCP_GRPH_ROTATION_ANGLE_90 = 0x00000001,
+DCP_GRPH_ROTATION_ANGLE_180 = 0x00000002,
+DCP_GRPH_ROTATION_ANGLE_270 = 0x00000003,
+} DCP_GRPH_ROTATION_ANGLE;
+
+/*
+ * DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN enum
+ */
+
+typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN {
+DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE = 0x00000000,
+DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE = 0x00000001,
+} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN;
+
+/*
+ * DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE enum
+ */
+
+typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE {
+DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM = 0x00000000,
+DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE = 0x00000001,
+} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE;
+
+/*
+ * DCP_GRPH_REGAMMA_MODE enum
+ */
+
+typedef enum DCP_GRPH_REGAMMA_MODE {
+DCP_GRPH_REGAMMA_MODE_BYPASS = 0x00000000,
+DCP_GRPH_REGAMMA_MODE_SRGB = 0x00000001,
+DCP_GRPH_REGAMMA_MODE_XVYCC = 0x00000002,
+DCP_GRPH_REGAMMA_MODE_PROGA = 0x00000003,
+DCP_GRPH_REGAMMA_MODE_PROGB = 0x00000004,
+} DCP_GRPH_REGAMMA_MODE;
+
+/*
+ * DCP_ALPHA_ROUND_TRUNC_MODE enum
+ */
+
+typedef enum DCP_ALPHA_ROUND_TRUNC_MODE {
+DCP_ALPHA_ROUND_TRUNC_MODE_ROUND = 0x00000000,
+DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC = 0x00000001,
+} DCP_ALPHA_ROUND_TRUNC_MODE;
+
+/*
+ * DCP_CURSOR_ALPHA_BLND_ENA enum
+ */
+
+typedef enum DCP_CURSOR_ALPHA_BLND_ENA {
+DCP_CURSOR_ALPHA_BLND_ENA_FALSE = 0x00000000,
+DCP_CURSOR_ALPHA_BLND_ENA_TRUE = 0x00000001,
+} DCP_CURSOR_ALPHA_BLND_ENA;
+
+/*
+ * DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK enum
+ */
+
+typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK {
+DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE = 0x00000000,
+DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE = 0x00000001,
+} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK;
+
+/*
+ * DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK enum
+ */
+
+typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK {
+DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE = 0x00000000,
+DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE = 0x00000001,
+} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK;
+
+/*
+ * DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK enum
+ */
+
+typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK {
+DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE = 0x00000000,
+DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE = 0x00000001,
+} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK;
+
+/*
+ * DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK enum
+ */
+
+typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK {
+DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
+DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE = 0x00000001,
+} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK;
+
+/*
+ * DCP_GRPH_SURFACE_COUNTER_EN enum
+ */
+
+typedef enum DCP_GRPH_SURFACE_COUNTER_EN {
+DCP_GRPH_SURFACE_COUNTER_EN_DISABLE = 0x00000000,
+DCP_GRPH_SURFACE_COUNTER_EN_ENABLE = 0x00000001,
+} DCP_GRPH_SURFACE_COUNTER_EN;
+
+/*
+ * DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT enum
+ */
+
+typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT {
+DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0 = 0x00000000,
+DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1 = 0x00000001,
+DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2 = 0x00000002,
+DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3 = 0x00000003,
+DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4 = 0x00000004,
+DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5 = 0x00000005,
+DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6 = 0x00000006,
+DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7 = 0x00000007,
+DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8 = 0x00000008,
+DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9 = 0x00000009,
+DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10 = 0x0000000a,
+DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11 = 0x0000000b,
+} DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT;
+
+/*
+ * DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED enum
+ */
+
+typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED {
+DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO = 0x00000000,
+DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES = 0x00000001,
+} DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED;
+
+/*
+ * DCP_GRPH_XDMA_FLIP_TYPE_CLEAR enum
+ */
+
+typedef enum DCP_GRPH_XDMA_FLIP_TYPE_CLEAR {
+DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_DISABLE = 0x00000000,
+DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_ENABLE = 0x00000001,
+} DCP_GRPH_XDMA_FLIP_TYPE_CLEAR;
+
+/*
+ * DCP_GRPH_XDMA_DRR_MODE_ENABLE enum
+ */
+
+typedef enum DCP_GRPH_XDMA_DRR_MODE_ENABLE {
+DCP_GRPH_XDMA_DRR_MODE_ENABLE_DISABLE = 0x00000000,
+DCP_GRPH_XDMA_DRR_MODE_ENABLE_ENABLE = 0x00000001,
+} DCP_GRPH_XDMA_DRR_MODE_ENABLE;
+
+/*
+ * DCP_GRPH_XDMA_MULTIFLIP_ENABLE enum
+ */
+
+typedef enum DCP_GRPH_XDMA_MULTIFLIP_ENABLE {
+DCP_GRPH_XDMA_MULTIFLIP_ENABLE_DISABLE = 0x00000000,
+DCP_GRPH_XDMA_MULTIFLIP_ENABLE_ENABLE = 0x00000001,
+} DCP_GRPH_XDMA_MULTIFLIP_ENABLE;
+
+/*
+ * DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK enum
+ */
+
+typedef enum DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK {
+DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_FALSE = 0x00000000,
+DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_TRUE = 0x00000001,
+} DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK;
+
+/*
+ * DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK enum
+ */
+
+typedef enum DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK {
+DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_FALSE = 0x00000000,
+DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_TRUE = 0x00000001,
+} DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK;
+
+/*******************************************************
+ * DC_PERFMON Enums
+ *******************************************************/
+
+/*
+ * PERFCOUNTER_CVALUE_SEL enum
+ */
+
+typedef enum PERFCOUNTER_CVALUE_SEL {
+PERFCOUNTER_CVALUE_SEL_47_0 = 0x00000000,
+PERFCOUNTER_CVALUE_SEL_15_0 = 0x00000001,
+PERFCOUNTER_CVALUE_SEL_31_16 = 0x00000002,
+PERFCOUNTER_CVALUE_SEL_47_32 = 0x00000003,
+PERFCOUNTER_CVALUE_SEL_11_0 = 0x00000004,
+PERFCOUNTER_CVALUE_SEL_23_12 = 0x00000005,
+PERFCOUNTER_CVALUE_SEL_35_24 = 0x00000006,
+PERFCOUNTER_CVALUE_SEL_47_36 = 0x00000007,
+} PERFCOUNTER_CVALUE_SEL;
+
+/*
+ * PERFCOUNTER_INC_MODE enum
+ */
+
+typedef enum PERFCOUNTER_INC_MODE {
+PERFCOUNTER_INC_MODE_MULTI_BIT = 0x00000000,
+PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x00000001,
+PERFCOUNTER_INC_MODE_LSB = 0x00000002,
+PERFCOUNTER_INC_MODE_POS_EDGE = 0x00000003,
+PERFCOUNTER_INC_MODE_NEG_EDGE = 0x00000004,
+} PERFCOUNTER_INC_MODE;
+
+/*
+ * PERFCOUNTER_HW_CNTL_SEL enum
+ */
+
+typedef enum PERFCOUNTER_HW_CNTL_SEL {
+PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x00000000,
+PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x00000001,
+} PERFCOUNTER_HW_CNTL_SEL;
+
+/*
+ * PERFCOUNTER_RUNEN_MODE enum
+ */
+
+typedef enum PERFCOUNTER_RUNEN_MODE {
+PERFCOUNTER_RUNEN_MODE_LEVEL = 0x00000000,
+PERFCOUNTER_RUNEN_MODE_EDGE = 0x00000001,
+} PERFCOUNTER_RUNEN_MODE;
+
+/*
+ * PERFCOUNTER_CNTOFF_START_DIS enum
+ */
+
+typedef enum PERFCOUNTER_CNTOFF_START_DIS {
+PERFCOUNTER_CNTOFF_START_ENABLE = 0x00000000,
+PERFCOUNTER_CNTOFF_START_DISABLE = 0x00000001,
+} PERFCOUNTER_CNTOFF_START_DIS;
+
+/*
+ * PERFCOUNTER_RESTART_EN enum
+ */
+
+typedef enum PERFCOUNTER_RESTART_EN {
+PERFCOUNTER_RESTART_DISABLE = 0x00000000,
+PERFCOUNTER_RESTART_ENABLE = 0x00000001,
+} PERFCOUNTER_RESTART_EN;
+
+/*
+ * PERFCOUNTER_INT_EN enum
+ */
+
+typedef enum PERFCOUNTER_INT_EN {
+PERFCOUNTER_INT_DISABLE = 0x00000000,
+PERFCOUNTER_INT_ENABLE = 0x00000001,
+} PERFCOUNTER_INT_EN;
+
+/*
+ * PERFCOUNTER_OFF_MASK enum
+ */
+
+typedef enum PERFCOUNTER_OFF_MASK {
+PERFCOUNTER_OFF_MASK_DISABLE = 0x00000000,
+PERFCOUNTER_OFF_MASK_ENABLE = 0x00000001,
+} PERFCOUNTER_OFF_MASK;
+
+/*
+ * PERFCOUNTER_ACTIVE enum
+ */
+
+typedef enum PERFCOUNTER_ACTIVE {
+PERFCOUNTER_IS_IDLE = 0x00000000,
+PERFCOUNTER_IS_ACTIVE = 0x00000001,
+} PERFCOUNTER_ACTIVE;
+
+/*
+ * PERFCOUNTER_INT_TYPE enum
+ */
+
+typedef enum PERFCOUNTER_INT_TYPE {
+PERFCOUNTER_INT_TYPE_LEVEL = 0x00000000,
+PERFCOUNTER_INT_TYPE_PULSE = 0x00000001,
+} PERFCOUNTER_INT_TYPE;
+
+/*
+ * PERFCOUNTER_COUNTED_VALUE_TYPE enum
+ */
+
+typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
+PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x00000000,
+PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x00000001,
+PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 0x00000002,
+} PERFCOUNTER_COUNTED_VALUE_TYPE;
+
+/*
+ * PERFCOUNTER_CNTL_SEL enum
+ */
+
+typedef enum PERFCOUNTER_CNTL_SEL {
+PERFCOUNTER_CNTL_SEL_0 = 0x00000000,
+PERFCOUNTER_CNTL_SEL_1 = 0x00000001,
+PERFCOUNTER_CNTL_SEL_2 = 0x00000002,
+PERFCOUNTER_CNTL_SEL_3 = 0x00000003,
+PERFCOUNTER_CNTL_SEL_4 = 0x00000004,
+PERFCOUNTER_CNTL_SEL_5 = 0x00000005,
+PERFCOUNTER_CNTL_SEL_6 = 0x00000006,
+PERFCOUNTER_CNTL_SEL_7 = 0x00000007,
+} PERFCOUNTER_CNTL_SEL;
+
+/*
+ * PERFCOUNTER_CNT0_STATE enum
+ */
+
+typedef enum PERFCOUNTER_CNT0_STATE {
+PERFCOUNTER_CNT0_STATE_RESET = 0x00000000,
+PERFCOUNTER_CNT0_STATE_START = 0x00000001,
+PERFCOUNTER_CNT0_STATE_FREEZE = 0x00000002,
+PERFCOUNTER_CNT0_STATE_HW = 0x00000003,
+} PERFCOUNTER_CNT0_STATE;
+
+/*
+ * PERFCOUNTER_STATE_SEL0 enum
+ */
+
+typedef enum PERFCOUNTER_STATE_SEL0 {
+PERFCOUNTER_STATE_SEL0_GLOBAL = 0x00000000,
+PERFCOUNTER_STATE_SEL0_LOCAL = 0x00000001,
+} PERFCOUNTER_STATE_SEL0;
+
+/*
+ * PERFCOUNTER_CNT1_STATE enum
+ */
+
+typedef enum PERFCOUNTER_CNT1_STATE {
+PERFCOUNTER_CNT1_STATE_RESET = 0x00000000,
+PERFCOUNTER_CNT1_STATE_START = 0x00000001,
+PERFCOUNTER_CNT1_STATE_FREEZE = 0x00000002,
+PERFCOUNTER_CNT1_STATE_HW = 0x00000003,
+} PERFCOUNTER_CNT1_STATE;
+
+/*
+ * PERFCOUNTER_STATE_SEL1 enum
+ */
+
+typedef enum PERFCOUNTER_STATE_SEL1 {
+PERFCOUNTER_STATE_SEL1_GLOBAL = 0x00000000,
+PERFCOUNTER_STATE_SEL1_LOCAL = 0x00000001,
+} PERFCOUNTER_STATE_SEL1;
+
+/*
+ * PERFCOUNTER_CNT2_STATE enum
+ */
+
+typedef enum PERFCOUNTER_CNT2_STATE {
+PERFCOUNTER_CNT2_STATE_RESET = 0x00000000,
+PERFCOUNTER_CNT2_STATE_START = 0x00000001,
+PERFCOUNTER_CNT2_STATE_FREEZE = 0x00000002,
+PERFCOUNTER_CNT2_STATE_HW = 0x00000003,
+} PERFCOUNTER_CNT2_STATE;
+
+/*
+ * PERFCOUNTER_STATE_SEL2 enum
+ */
+
+typedef enum PERFCOUNTER_STATE_SEL2 {
+PERFCOUNTER_STATE_SEL2_GLOBAL = 0x00000000,
+PERFCOUNTER_STATE_SEL2_LOCAL = 0x00000001,
+} PERFCOUNTER_STATE_SEL2;
+
+/*
+ * PERFCOUNTER_CNT3_STATE enum
+ */
+
+typedef enum PERFCOUNTER_CNT3_STATE {
+PERFCOUNTER_CNT3_STATE_RESET = 0x00000000,
+PERFCOUNTER_CNT3_STATE_START = 0x00000001,
+PERFCOUNTER_CNT3_STATE_FREEZE = 0x00000002,
+PERFCOUNTER_CNT3_STATE_HW = 0x00000003,
+} PERFCOUNTER_CNT3_STATE;
+
+/*
+ * PERFCOUNTER_STATE_SEL3 enum
+ */
+
+typedef enum PERFCOUNTER_STATE_SEL3 {
+PERFCOUNTER_STATE_SEL3_GLOBAL = 0x00000000,
+PERFCOUNTER_STATE_SEL3_LOCAL = 0x00000001,
+} PERFCOUNTER_STATE_SEL3;
+
+/*
+ * PERFCOUNTER_CNT4_STATE enum
+ */
+
+typedef enum PERFCOUNTER_CNT4_STATE {
+PERFCOUNTER_CNT4_STATE_RESET = 0x00000000,
+PERFCOUNTER_CNT4_STATE_START = 0x00000001,
+PERFCOUNTER_CNT4_STATE_FREEZE = 0x00000002,
+PERFCOUNTER_CNT4_STATE_HW = 0x00000003,
+} PERFCOUNTER_CNT4_STATE;
+
+/*
+ * PERFCOUNTER_STATE_SEL4 enum
+ */
+
+typedef enum PERFCOUNTER_STATE_SEL4 {
+PERFCOUNTER_STATE_SEL4_GLOBAL = 0x00000000,
+PERFCOUNTER_STATE_SEL4_LOCAL = 0x00000001,
+} PERFCOUNTER_STATE_SEL4;
+
+/*
+ * PERFCOUNTER_CNT5_STATE enum
+ */
+
+typedef enum PERFCOUNTER_CNT5_STATE {
+PERFCOUNTER_CNT5_STATE_RESET = 0x00000000,
+PERFCOUNTER_CNT5_STATE_START = 0x00000001,
+PERFCOUNTER_CNT5_STATE_FREEZE = 0x00000002,
+PERFCOUNTER_CNT5_STATE_HW = 0x00000003,
+} PERFCOUNTER_CNT5_STATE;
+
+/*
+ * PERFCOUNTER_STATE_SEL5 enum
+ */
+
+typedef enum PERFCOUNTER_STATE_SEL5 {
+PERFCOUNTER_STATE_SEL5_GLOBAL = 0x00000000,
+PERFCOUNTER_STATE_SEL5_LOCAL = 0x00000001,
+} PERFCOUNTER_STATE_SEL5;
+
+/*
+ * PERFCOUNTER_CNT6_STATE enum
+ */
+
+typedef enum PERFCOUNTER_CNT6_STATE {
+PERFCOUNTER_CNT6_STATE_RESET = 0x00000000,
+PERFCOUNTER_CNT6_STATE_START = 0x00000001,
+PERFCOUNTER_CNT6_STATE_FREEZE = 0x00000002,
+PERFCOUNTER_CNT6_STATE_HW = 0x00000003,
+} PERFCOUNTER_CNT6_STATE;
+
+/*
+ * PERFCOUNTER_STATE_SEL6 enum
+ */
+
+typedef enum PERFCOUNTER_STATE_SEL6 {
+PERFCOUNTER_STATE_SEL6_GLOBAL = 0x00000000,
+PERFCOUNTER_STATE_SEL6_LOCAL = 0x00000001,
+} PERFCOUNTER_STATE_SEL6;
+
+/*
+ * PERFCOUNTER_CNT7_STATE enum
+ */
+
+typedef enum PERFCOUNTER_CNT7_STATE {
+PERFCOUNTER_CNT7_STATE_RESET = 0x00000000,
+PERFCOUNTER_CNT7_STATE_START = 0x00000001,
+PERFCOUNTER_CNT7_STATE_FREEZE = 0x00000002,
+PERFCOUNTER_CNT7_STATE_HW = 0x00000003,
+} PERFCOUNTER_CNT7_STATE;
+
+/*
+ * PERFCOUNTER_STATE_SEL7 enum
+ */
+
+typedef enum PERFCOUNTER_STATE_SEL7 {
+PERFCOUNTER_STATE_SEL7_GLOBAL = 0x00000000,
+PERFCOUNTER_STATE_SEL7_LOCAL = 0x00000001,
+} PERFCOUNTER_STATE_SEL7;
+
+/*
+ * PERFMON_STATE enum
+ */
+
+typedef enum PERFMON_STATE {
+PERFMON_STATE_RESET = 0x00000000,
+PERFMON_STATE_START = 0x00000001,
+PERFMON_STATE_FREEZE = 0x00000002,
+PERFMON_STATE_HW = 0x00000003,
+} PERFMON_STATE;
+
+/*
+ * PERFMON_CNTOFF_AND_OR enum
+ */
+
+typedef enum PERFMON_CNTOFF_AND_OR {
+PERFMON_CNTOFF_OR = 0x00000000,
+PERFMON_CNTOFF_AND = 0x00000001,
+} PERFMON_CNTOFF_AND_OR;
+
+/*
+ * PERFMON_CNTOFF_INT_EN enum
+ */
+
+typedef enum PERFMON_CNTOFF_INT_EN {
+PERFMON_CNTOFF_INT_DISABLE = 0x00000000,
+PERFMON_CNTOFF_INT_ENABLE = 0x00000001,
+} PERFMON_CNTOFF_INT_EN;
+
+/*
+ * PERFMON_CNTOFF_INT_TYPE enum
+ */
+
+typedef enum PERFMON_CNTOFF_INT_TYPE {
+PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x00000000,
+PERFMON_CNTOFF_INT_TYPE_PULSE = 0x00000001,
+} PERFMON_CNTOFF_INT_TYPE;
+
+/*******************************************************
+ * SCL Enums
+ *******************************************************/
+
+/*
+ * SCL_C_RAM_TAP_PAIR_IDX enum
+ */
+
+typedef enum SCL_C_RAM_TAP_PAIR_IDX {
+SCL_C_RAM_TAP_PAIR_ID0 = 0x00000000,
+SCL_C_RAM_TAP_PAIR_ID1 = 0x00000001,
+SCL_C_RAM_TAP_PAIR_ID2 = 0x00000002,
+SCL_C_RAM_TAP_PAIR_ID3 = 0x00000003,
+SCL_C_RAM_TAP_PAIR_ID4 = 0x00000004,
+} SCL_C_RAM_TAP_PAIR_IDX;
+
+/*
+ * SCL_C_RAM_PHASE enum
+ */
+
+typedef enum SCL_C_RAM_PHASE {
+SCL_C_RAM_PHASE_0 = 0x00000000,
+SCL_C_RAM_PHASE_1 = 0x00000001,
+SCL_C_RAM_PHASE_2 = 0x00000002,
+SCL_C_RAM_PHASE_3 = 0x00000003,
+SCL_C_RAM_PHASE_4 = 0x00000004,
+SCL_C_RAM_PHASE_5 = 0x00000005,
+SCL_C_RAM_PHASE_6 = 0x00000006,
+SCL_C_RAM_PHASE_7 = 0x00000007,
+SCL_C_RAM_PHASE_8 = 0x00000008,
+} SCL_C_RAM_PHASE;
+
+/*
+ * SCL_C_RAM_FILTER_TYPE enum
+ */
+
+typedef enum SCL_C_RAM_FILTER_TYPE {
+SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT = 0x00000000,
+SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT = 0x00000001,
+SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT = 0x00000002,
+SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT = 0x00000003,
+} SCL_C_RAM_FILTER_TYPE;
+
+/*
+ * SCL_MODE_SEL enum
+ */
+
+typedef enum SCL_MODE_SEL {
+SCL_MODE_RGB_BYPASS = 0x00000000,
+SCL_MODE_RGB_SCALING = 0x00000001,
+SCL_MODE_YCBCR_SCALING = 0x00000002,
+SCL_MODE_YCBCR_BYPASS = 0x00000003,
+} SCL_MODE_SEL;
+
+/*
+ * SCL_PSCL_EN enum
+ */
+
+typedef enum SCL_PSCL_EN {
+SCL_PSCL_DISABLE = 0x00000000,
+SCL_PSCL_ENANBLE = 0x00000001,
+} SCL_PSCL_EN;
+
+/*
+ * SCL_V_NUM_OF_TAPS enum
+ */
+
+typedef enum SCL_V_NUM_OF_TAPS {
+SCL_V_NUM_OF_TAPS_1 = 0x00000000,
+SCL_V_NUM_OF_TAPS_2 = 0x00000001,
+SCL_V_NUM_OF_TAPS_3 = 0x00000002,
+SCL_V_NUM_OF_TAPS_4 = 0x00000003,
+SCL_V_NUM_OF_TAPS_5 = 0x00000004,
+SCL_V_NUM_OF_TAPS_6 = 0x00000005,
+} SCL_V_NUM_OF_TAPS;
+
+/*
+ * SCL_H_NUM_OF_TAPS enum
+ */
+
+typedef enum SCL_H_NUM_OF_TAPS {
+SCL_H_NUM_OF_TAPS_1 = 0x00000000,
+SCL_H_NUM_OF_TAPS_2 = 0x00000001,
+SCL_H_NUM_OF_TAPS_4 = 0x00000003,
+SCL_H_NUM_OF_TAPS_6 = 0x00000005,
+SCL_H_NUM_OF_TAPS_8 = 0x00000007,
+SCL_H_NUM_OF_TAPS_10 = 0x00000009,
+} SCL_H_NUM_OF_TAPS;
+
+/*
+ * SCL_BOUNDARY_MODE enum
+ */
+
+typedef enum SCL_BOUNDARY_MODE {
+SCL_BOUNDARY_MODE_BLACK = 0x00000000,
+SCL_BOUNDARY_MODE_EDGE = 0x00000001,
+} SCL_BOUNDARY_MODE;
+
+/*
+ * SCL_EARLY_EOL_MOD enum
+ */
+
+typedef enum SCL_EARLY_EOL_MOD {
+SCL_EARLY_EOL_MODE_CRTC = 0x00000000,
+SCL_EARLY_EOL_MODE_INTERNAL = 0x00000001,
+} SCL_EARLY_EOL_MOD;
+
+/*
+ * SCL_BYPASS_MODE enum
+ */
+
+typedef enum SCL_BYPASS_MODE {
+SCL_BYPASS_MODE_MC_MR = 0x00000000,
+SCL_BYPASS_MODE_AC_NR = 0x00000001,
+SCL_BYPASS_MODE_AC_AR = 0x00000002,
+SCL_BYPASS_MODE_RESERVED = 0x00000003,
+} SCL_BYPASS_MODE;
+
+/*
+ * SCL_V_MANUAL_REPLICATE_FACTOR enum
+ */
+
+typedef enum SCL_V_MANUAL_REPLICATE_FACTOR {
+SCL_V_MANUAL_REPLICATE_FACTOR_1 = 0x00000000,
+SCL_V_MANUAL_REPLICATE_FACTOR_2 = 0x00000001,
+SCL_V_MANUAL_REPLICATE_FACTOR_3 = 0x00000002,
+SCL_V_MANUAL_REPLICATE_FACTOR_4 = 0x00000003,
+SCL_V_MANUAL_REPLICATE_FACTOR_5 = 0x00000004,
+SCL_V_MANUAL_REPLICATE_FACTOR_6 = 0x00000005,
+SCL_V_MANUAL_REPLICATE_FACTOR_7 = 0x00000006,
+SCL_V_MANUAL_REPLICATE_FACTOR_8 = 0x00000007,
+SCL_V_MANUAL_REPLICATE_FACTOR_9 = 0x00000008,
+SCL_V_MANUAL_REPLICATE_FACTOR_10 = 0x00000009,
+SCL_V_MANUAL_REPLICATE_FACTOR_11 = 0x0000000a,
+SCL_V_MANUAL_REPLICATE_FACTOR_12 = 0x0000000b,
+SCL_V_MANUAL_REPLICATE_FACTOR_13 = 0x0000000c,
+SCL_V_MANUAL_REPLICATE_FACTOR_14 = 0x0000000d,
+SCL_V_MANUAL_REPLICATE_FACTOR_15 = 0x0000000e,
+SCL_V_MANUAL_REPLICATE_FACTOR_16 = 0x0000000f,
+} SCL_V_MANUAL_REPLICATE_FACTOR;
+
+/*
+ * SCL_H_MANUAL_REPLICATE_FACTOR enum
+ */
+
+typedef enum SCL_H_MANUAL_REPLICATE_FACTOR {
+SCL_H_MANUAL_REPLICATE_FACTOR_1 = 0x00000000,
+SCL_H_MANUAL_REPLICATE_FACTOR_2 = 0x00000001,
+SCL_H_MANUAL_REPLICATE_FACTOR_3 = 0x00000002,
+SCL_H_MANUAL_REPLICATE_FACTOR_4 = 0x00000003,
+SCL_H_MANUAL_REPLICATE_FACTOR_5 = 0x00000004,
+SCL_H_MANUAL_REPLICATE_FACTOR_6 = 0x00000005,
+SCL_H_MANUAL_REPLICATE_FACTOR_7 = 0x00000006,
+SCL_H_MANUAL_REPLICATE_FACTOR_8 = 0x00000007,
+SCL_H_MANUAL_REPLICATE_FACTOR_9 = 0x00000008,
+SCL_H_MANUAL_REPLICATE_FACTOR_10 = 0x00000009,
+SCL_H_MANUAL_REPLICATE_FACTOR_11 = 0x0000000a,
+SCL_H_MANUAL_REPLICATE_FACTOR_12 = 0x0000000b,
+SCL_H_MANUAL_REPLICATE_FACTOR_13 = 0x0000000c,
+SCL_H_MANUAL_REPLICATE_FACTOR_14 = 0x0000000d,
+SCL_H_MANUAL_REPLICATE_FACTOR_15 = 0x0000000e,
+SCL_H_MANUAL_REPLICATE_FACTOR_16 = 0x0000000f,
+} SCL_H_MANUAL_REPLICATE_FACTOR;
+
+/*
+ * SCL_V_CALC_AUTO_RATIO_EN enum
+ */
+
+typedef enum SCL_V_CALC_AUTO_RATIO_EN {
+SCL_V_CALC_AUTO_RATIO_DISABLE = 0x00000000,
+SCL_V_CALC_AUTO_RATIO_ENABLE = 0x00000001,
+} SCL_V_CALC_AUTO_RATIO_EN;
+
+/*
+ * SCL_H_CALC_AUTO_RATIO_EN enum
+ */
+
+typedef enum SCL_H_CALC_AUTO_RATIO_EN {
+SCL_H_CALC_AUTO_RATIO_DISABLE = 0x00000000,
+SCL_H_CALC_AUTO_RATIO_ENABLE = 0x00000001,
+} SCL_H_CALC_AUTO_RATIO_EN;
+
+/*
+ * SCL_H_FILTER_PICK_NEAREST enum
+ */
+
+typedef enum SCL_H_FILTER_PICK_NEAREST {
+SCL_H_FILTER_PICK_NEAREST_DISABLE = 0x00000000,
+SCL_H_FILTER_PICK_NEAREST_ENABLE = 0x00000001,
+} SCL_H_FILTER_PICK_NEAREST;
+
+/*
+ * SCL_H_2TAP_HARDCODE_COEF_EN enum
+ */
+
+typedef enum SCL_H_2TAP_HARDCODE_COEF_EN {
+SCL_H_2TAP_HARDCODE_COEF_DISABLE = 0x00000000,
+SCL_H_2TAP_HARDCODE_COEF_ENABLE = 0x00000001,
+} SCL_H_2TAP_HARDCODE_COEF_EN;
+
+/*
+ * SCL_V_FILTER_PICK_NEAREST enum
+ */
+
+typedef enum SCL_V_FILTER_PICK_NEAREST {
+SCL_V_FILTER_PICK_NEAREST_DISABLE = 0x00000000,
+SCL_V_FILTER_PICK_NEAREST_ENABLE = 0x00000001,
+} SCL_V_FILTER_PICK_NEAREST;
+
+/*
+ * SCL_V_2TAP_HARDCODE_COEF_EN enum
+ */
+
+typedef enum SCL_V_2TAP_HARDCODE_COEF_EN {
+SCL_V_2TAP_HARDCODE_COEF_DISABLE = 0x00000000,
+SCL_V_2TAP_HARDCODE_COEF_ENABLE = 0x00000001,
+} SCL_V_2TAP_HARDCODE_COEF_EN;
+
+/*
+ * SCL_UPDATE_TAKEN enum
+ */
+
+typedef enum SCL_UPDATE_TAKEN {
+SCL_UPDATE_TAKEN_NO = 0x00000000,
+SCL_UPDATE_TAKEN_YES = 0x00000001,
+} SCL_UPDATE_TAKEN;
+
+/*
+ * SCL_UPDATE_LOCK enum
+ */
+
+typedef enum SCL_UPDATE_LOCK {
+SCL_UPDATE_UNLOCKED = 0x00000000,
+SCL_UPDATE_LOCKED = 0x00000001,
+} SCL_UPDATE_LOCK;
+
+/*
+ * SCL_COEF_UPDATE_COMPLETE enum
+ */
+
+typedef enum SCL_COEF_UPDATE_COMPLETE {
+SCL_COEF_UPDATE_NOT_COMPLETED = 0x00000000,
+SCL_COEF_UPDATE_COMPLETED = 0x00000001,
+} SCL_COEF_UPDATE_COMPLETE;
+
+/*
+ * SCL_HF_SHARP_SCALE_FACTOR enum
+ */
+
+typedef enum SCL_HF_SHARP_SCALE_FACTOR {
+SCL_HF_SHARP_SCALE_FACTOR_0 = 0x00000000,
+SCL_HF_SHARP_SCALE_FACTOR_1 = 0x00000001,
+SCL_HF_SHARP_SCALE_FACTOR_2 = 0x00000002,
+SCL_HF_SHARP_SCALE_FACTOR_3 = 0x00000003,
+SCL_HF_SHARP_SCALE_FACTOR_4 = 0x00000004,
+SCL_HF_SHARP_SCALE_FACTOR_5 = 0x00000005,
+SCL_HF_SHARP_SCALE_FACTOR_6 = 0x00000006,
+SCL_HF_SHARP_SCALE_FACTOR_7 = 0x00000007,
+} SCL_HF_SHARP_SCALE_FACTOR;
+
+/*
+ * SCL_HF_SHARP_EN enum
+ */
+
+typedef enum SCL_HF_SHARP_EN {
+SCL_HF_SHARP_DISABLE = 0x00000000,
+SCL_HF_SHARP_ENABLE = 0x00000001,
+} SCL_HF_SHARP_EN;
+
+/*
+ * SCL_VF_SHARP_SCALE_FACTOR enum
+ */
+
+typedef enum SCL_VF_SHARP_SCALE_FACTOR {
+SCL_VF_SHARP_SCALE_FACTOR_0 = 0x00000000,
+SCL_VF_SHARP_SCALE_FACTOR_1 = 0x00000001,
+SCL_VF_SHARP_SCALE_FACTOR_2 = 0x00000002,
+SCL_VF_SHARP_SCALE_FACTOR_3 = 0x00000003,
+SCL_VF_SHARP_SCALE_FACTOR_4 = 0x00000004,
+SCL_VF_SHARP_SCALE_FACTOR_5 = 0x00000005,
+SCL_VF_SHARP_SCALE_FACTOR_6 = 0x00000006,
+SCL_VF_SHARP_SCALE_FACTOR_7 = 0x00000007,
+} SCL_VF_SHARP_SCALE_FACTOR;
+
+/*
+ * SCL_VF_SHARP_EN enum
+ */
+
+typedef enum SCL_VF_SHARP_EN {
+SCL_VF_SHARP_DISABLE = 0x00000000,
+SCL_VF_SHARP_ENABLE = 0x00000001,
+} SCL_VF_SHARP_EN;
+
+/*
+ * SCL_ALU_DISABLE enum
+ */
+
+typedef enum SCL_ALU_DISABLE {
+SCL_ALU_ENABLED = 0x00000000,
+SCL_ALU_DISABLED = 0x00000001,
+} SCL_ALU_DISABLE;
+
+/*
+ * SCL_HOST_CONFLICT_MASK enum
+ */
+
+typedef enum SCL_HOST_CONFLICT_MASK {
+SCL_HOST_CONFLICT_DISABLE_INTERRUPT = 0x00000000,
+SCL_HOST_CONFLICT_ENABLE_INTERRUPT = 0x00000001,
+} SCL_HOST_CONFLICT_MASK;
+
+/*
+ * SCL_SCL_MODE_CHANGE_MASK enum
+ */
+
+typedef enum SCL_SCL_MODE_CHANGE_MASK {
+SCL_MODE_CHANGE_DISABLE_INTERRUPT = 0x00000000,
+SCL_MODE_CHANGE_ENABLE_INTERRUPT = 0x00000001,
+} SCL_SCL_MODE_CHANGE_MASK;
+
+/*******************************************************
+ * SCLV Enums
+ *******************************************************/
+
+/*
+ * SCLV_MODE_SEL enum
+ */
+
+typedef enum SCLV_MODE_SEL {
+SCLV_MODE_RGB_BYPASS = 0x00000000,
+SCLV_MODE_RGB_SCALING = 0x00000001,
+SCLV_MODE_YCBCR_SCALING = 0x00000002,
+SCLV_MODE_YCBCR_BYPASS = 0x00000003,
+} SCLV_MODE_SEL;
+
+/*
+ * SCLV_INTERLACE_SOURCE enum
+ */
+
+typedef enum SCLV_INTERLACE_SOURCE {
+INTERLACE_SOURCE_PROGRESSIVE = 0x00000000,
+INTERLACE_SOURCE_INTERLEAVE = 0x00000001,
+INTERLACE_SOURCE_STACK = 0x00000002,
+} SCLV_INTERLACE_SOURCE;
+
+/*
+ * SCLV_UPDATE_LOCK enum
+ */
+
+typedef enum SCLV_UPDATE_LOCK {
+UPDATE_UNLOCKED = 0x00000000,
+UPDATE_LOCKED = 0x00000001,
+} SCLV_UPDATE_LOCK;
+
+/*
+ * SCLV_COEF_UPDATE_COMPLETE enum
+ */
+
+typedef enum SCLV_COEF_UPDATE_COMPLETE {
+COEF_UPDATE_NOT_COMPLETE = 0x00000000,
+COEF_UPDATE_COMPLETE = 0x00000001,
+} SCLV_COEF_UPDATE_COMPLETE;
+
+/*******************************************************
+ * DPRX_SD Enums
+ *******************************************************/
+
+/*
+ * DPRX_SD_PIXEL_ENCODING enum
+ */
+
+typedef enum DPRX_SD_PIXEL_ENCODING {
+PIXEL_FORMAT_RGB_444 = 0x00000000,
+PIXEL_FORMAT_YCBCR_444 = 0x00000001,
+PIXEL_FORMAT_YCBCR_422 = 0x00000002,
+PIXEL_FORMAT_Y_ONLY = 0x00000003,
+} DPRX_SD_PIXEL_ENCODING;
+
+/*
+ * DPRX_SD_COMPONENT_DEPTH enum
+ */
+
+typedef enum DPRX_SD_COMPONENT_DEPTH {
+COMPONENT_DEPTH_6BPC = 0x00000000,
+COMPONENT_DEPTH_8BPC = 0x00000001,
+COMPONENT_DEPTH_10BPC = 0x00000002,
+COMPONENT_DEPTH_12BPC = 0x00000003,
+COMPONENT_DEPTH_16BPC = 0x00000004,
+} DPRX_SD_COMPONENT_DEPTH;
+
+/*******************************************************
+ * AZF0STREAM Enums
+ *******************************************************/
+
+/*
+ * AZ_LATENCY_COUNTER_CONTROL enum
+ */
+
+typedef enum AZ_LATENCY_COUNTER_CONTROL {
+AZ_LATENCY_COUNTER_NO_RESET = 0x00000000,
+AZ_LATENCY_COUNTER_RESET_DONE = 0x00000001,
+} AZ_LATENCY_COUNTER_CONTROL;
+
+/*******************************************************
+ * BLND Enums
+ *******************************************************/
+
+/*
+ * BLND_CONTROL_BLND_MODE enum
+ */
+
+typedef enum BLND_CONTROL_BLND_MODE {
+BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x00000000,
+BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x00000001,
+BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x00000002,
+BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x00000003,
+} BLND_CONTROL_BLND_MODE;
+
+/*
+ * BLND_CONTROL_BLND_STEREO_TYPE enum
+ */
+
+typedef enum BLND_CONTROL_BLND_STEREO_TYPE {
+BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0x00000000,
+BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 0x00000001,
+BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 0x00000002,
+BLND_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x00000003,
+} BLND_CONTROL_BLND_STEREO_TYPE;
+
+/*
+ * BLND_CONTROL_BLND_STEREO_POLARITY enum
+ */
+
+typedef enum BLND_CONTROL_BLND_STEREO_POLARITY {
+BLND_CONTROL_BLND_STEREO_POLARITY_LOW = 0x00000000,
+BLND_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x00000001,
+} BLND_CONTROL_BLND_STEREO_POLARITY;
+
+/*
+ * BLND_CONTROL_BLND_FEEDTHROUGH_EN enum
+ */
+
+typedef enum BLND_CONTROL_BLND_FEEDTHROUGH_EN {
+BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x00000000,
+BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x00000001,
+} BLND_CONTROL_BLND_FEEDTHROUGH_EN;
+
+/*
+ * BLND_CONTROL_BLND_ALPHA_MODE enum
+ */
+
+typedef enum BLND_CONTROL_BLND_ALPHA_MODE {
+BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x00000000,
+BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
+BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x00000002,
+BLND_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x00000003,
+} BLND_CONTROL_BLND_ALPHA_MODE;
+
+/*
+ * BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY enum
+ */
+
+typedef enum BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
+BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE = 0x00000000,
+BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE = 0x00000001,
+} BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
+
+/*
+ * BLND_CONTROL_BLND_MULTIPLIED_MODE enum
+ */
+
+typedef enum BLND_CONTROL_BLND_MULTIPLIED_MODE {
+BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x00000000,
+BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x00000001,
+} BLND_CONTROL_BLND_MULTIPLIED_MODE;
+
+/*
+ * BLND_SM_CONTROL2_SM_MODE enum
+ */
+
+typedef enum BLND_SM_CONTROL2_SM_MODE {
+BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x00000000,
+BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
+BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
+BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
+} BLND_SM_CONTROL2_SM_MODE;
+
+/*
+ * BLND_SM_CONTROL2_SM_FRAME_ALTERNATE enum
+ */
+
+typedef enum BLND_SM_CONTROL2_SM_FRAME_ALTERNATE {
+BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x00000000,
+BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x00000001,
+} BLND_SM_CONTROL2_SM_FRAME_ALTERNATE;
+
+/*
+ * BLND_SM_CONTROL2_SM_FIELD_ALTERNATE enum
+ */
+
+typedef enum BLND_SM_CONTROL2_SM_FIELD_ALTERNATE {
+BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x00000000,
+BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x00000001,
+} BLND_SM_CONTROL2_SM_FIELD_ALTERNATE;
+
+/*
+ * BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL enum
+ */
+
+typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
+BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
+BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
+BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
+BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
+} BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
+
+/*
+ * BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL enum
+ */
+
+typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
+BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
+BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
+BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
+BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
+} BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
+
+/*
+ * BLND_CONTROL2_PTI_ENABLE enum
+ */
+
+typedef enum BLND_CONTROL2_PTI_ENABLE {
+BLND_CONTROL2_PTI_ENABLE_FALSE = 0x00000000,
+BLND_CONTROL2_PTI_ENABLE_TRUE = 0x00000001,
+} BLND_CONTROL2_PTI_ENABLE;
+
+/*
+ * BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN enum
+ */
+
+typedef enum BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
+BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x00000000,
+BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x00000001,
+} BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
+
+/*
+ * BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN enum
+ */
+
+typedef enum BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
+BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x00000000,
+BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x00000001,
+} BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
+
+/*
+ * BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK enum
+ */
+
+typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
+BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
+BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 0x00000001,
+} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
+
+/*
+ * BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK enum
+ */
+
+typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
+BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0x00000000,
+BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 0x00000001,
+} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
+
+/*
+ * BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK enum
+ */
+
+typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
+BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0x00000000,
+BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 0x00000001,
+} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
+
+/*
+ * BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK enum
+ */
+
+typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
+BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0x00000000,
+BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 0x00000001,
+} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
+
+/*
+ * BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK enum
+ */
+
+typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
+BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0x00000000,
+BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 0x00000001,
+} BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
+
+/*
+ * BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK enum
+ */
+
+typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
+BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0x00000000,
+BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 0x00000001,
+} BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
+
+/*
+ * BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK enum
+ */
+
+typedef enum BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
+BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x00000000,
+BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x00000001,
+} BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
+
+/*
+ * BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK enum
+ */
+
+typedef enum BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
+BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x00000000,
+BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x00000001,
+} BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
+
+/*
+ * BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE enum
+ */
+
+typedef enum BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
+BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x00000000,
+BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x00000001,
+} BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
+
+/*
+ * BLND_DEBUG_BLND_CNV_MUX_SELECT enum
+ */
+
+typedef enum BLND_DEBUG_BLND_CNV_MUX_SELECT {
+BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x00000000,
+BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x00000001,
+} BLND_DEBUG_BLND_CNV_MUX_SELECT;
+
+/*
+ * BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN enum
+ */
+
+typedef enum BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
+BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
+BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
+} BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
+
+/*******************************************************
+ * AZF0ENDPOINT Enums
+ *******************************************************/
+
+/*
+ * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008,
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
+
+/*
+ * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
+ */
+
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
+
+/*
+ * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
+ */
+
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
+
+/*
+ * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
+ */
+
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
+
+/*
+ * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
+ */
+
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
+
+/*
+ * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
+ */
+
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
+
+/*
+ * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
+ */
+
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000,
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
+
+/*
+ * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
+
+/*
+ * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000,
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 0x00000001,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
+
+/*
+ * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
+
+/*
+ * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
+ */
+
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
+
+/*
+ * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
+ */
+
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
+
+/*
+ * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
+ */
+
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000,
+AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
+
+/*
+ * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008,
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
+
+/*
+ * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
+ */
+
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
+
+/*
+ * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
+ */
+
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
+
+/*
+ * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
+ */
+
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
+
+/*
+ * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
+ */
+
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
+
+/*
+ * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
+ */
+
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
+
+/*
+ * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
+ */
+
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000,
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
+
+/*
+ * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
+
+/*
+ * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
+
+/*
+ * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
+ */
+
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
+
+/*
+ * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
+ */
+
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0x00000000,
+AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
+
+/*
+ * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
+AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0x00000000,
+AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 0x00000001,
+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
+
+/*
+ * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
+ */
+
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
+AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0x00000000,
+AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001,
+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
+
+/*
+ * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
+AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000,
+AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001,
+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
+
+/*
+ * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
+AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000,
+AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001,
+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
+
+/*
+ * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
+AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000,
+AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001,
+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
+
+/*
+ * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
+ */
+
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
+AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0x00000000,
+AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 0x00000001,
+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
+
+/*
+ * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
+ */
+
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
+AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000,
+AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001,
+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
+
+/*
+ * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
+AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000,
+AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001,
+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
+
+/*
+ * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
+AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000,
+AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001,
+} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
+
+/*
+ * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
+AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0x00000000,
+AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 0x00000001,
+} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
+
+/*******************************************************
+ * AZF0INPUTENDPOINT Enums
+ *******************************************************/
+
+/*
+ * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008,
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0x00000000,
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0x00000000,
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0x00000000,
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000,
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000,
+AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
+
+/*
+ * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
+ */
+
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
+AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0x00000000,
+AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 0x00000001,
+} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
+
+/*******************************************************
+ * UNP Enums
+ *******************************************************/
+
+/*
+ * UNP_GRPH_EN enum
+ */
+
+typedef enum UNP_GRPH_EN {
+UNP_GRPH_DISABLED = 0x00000000,
+UNP_GRPH_ENABLED = 0x00000001,
+} UNP_GRPH_EN;
+
+/*
+ * UNP_GRPH_DEPTH enum
+ */
+
+typedef enum UNP_GRPH_DEPTH {
+UNP_GRPH_8BPP = 0x00000000,
+UNP_GRPH_16BPP = 0x00000001,
+UNP_GRPH_32BPP = 0x00000002,
+} UNP_GRPH_DEPTH;
+
+/*
+ * UNP_GRPH_NUM_BANKS enum
+ */
+
+typedef enum UNP_GRPH_NUM_BANKS {
+UNP_GRPH_ADDR_SURF_2_BANK = 0x00000000,
+UNP_GRPH_ADDR_SURF_4_BANK = 0x00000001,
+UNP_GRPH_ADDR_SURF_8_BANK = 0x00000002,
+UNP_GRPH_ADDR_SURF_16_BANK = 0x00000003,
+} UNP_GRPH_NUM_BANKS;
+
+/*
+ * UNP_GRPH_BANK_WIDTH enum
+ */
+
+typedef enum UNP_GRPH_BANK_WIDTH {
+UNP_GRPH_ADDR_SURF_BANK_WIDTH_1 = 0x00000000,
+UNP_GRPH_ADDR_SURF_BANK_WIDTH_2 = 0x00000001,
+UNP_GRPH_ADDR_SURF_BANK_WIDTH_4 = 0x00000002,
+UNP_GRPH_ADDR_SURF_BANK_WIDTH_8 = 0x00000003,
+} UNP_GRPH_BANK_WIDTH;
+
+/*
+ * UNP_GRPH_BANK_HEIGHT enum
+ */
+
+typedef enum UNP_GRPH_BANK_HEIGHT {
+UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1 = 0x00000000,
+UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2 = 0x00000001,
+UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4 = 0x00000002,
+UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8 = 0x00000003,
+} UNP_GRPH_BANK_HEIGHT;
+
+/*
+ * UNP_GRPH_TILE_SPLIT enum
+ */
+
+typedef enum UNP_GRPH_TILE_SPLIT {
+UNP_ADDR_SURF_TILE_SPLIT_64B = 0x00000000,
+UNP_ADDR_SURF_TILE_SPLIT_128B = 0x00000001,
+UNP_ADDR_SURF_TILE_SPLIT_256B = 0x00000002,
+UNP_ADDR_SURF_TILE_SPLIT_512B = 0x00000003,
+UNP_ADDR_SURF_TILE_SPLIT_1KB = 0x00000004,
+UNP_ADDR_SURF_TILE_SPLIT_2KB = 0x00000005,
+UNP_ADDR_SURF_TILE_SPLIT_4KB = 0x00000006,
+} UNP_GRPH_TILE_SPLIT;
+
+/*
+ * UNP_GRPH_ADDRESS_TRANSLATION_ENABLE enum
+ */
+
+typedef enum UNP_GRPH_ADDRESS_TRANSLATION_ENABLE {
+UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0 = 0x00000000,
+UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1 = 0x00000001,
+} UNP_GRPH_ADDRESS_TRANSLATION_ENABLE;
+
+/*
+ * UNP_GRPH_MACRO_TILE_ASPECT enum
+ */
+
+typedef enum UNP_GRPH_MACRO_TILE_ASPECT {
+UNP_ADDR_SURF_MACRO_ASPECT_1 = 0x00000000,
+UNP_ADDR_SURF_MACRO_ASPECT_2 = 0x00000001,
+UNP_ADDR_SURF_MACRO_ASPECT_4 = 0x00000002,
+UNP_ADDR_SURF_MACRO_ASPECT_8 = 0x00000003,
+} UNP_GRPH_MACRO_TILE_ASPECT;
+
+/*
+ * UNP_GRPH_COLOR_EXPANSION_MODE enum
+ */
+
+typedef enum UNP_GRPH_COLOR_EXPANSION_MODE {
+UNP_GRPH_DYNAMIC_EXPANSION = 0x00000000,
+UNP_GRPH_ZERO_EXPANSION = 0x00000001,
+} UNP_GRPH_COLOR_EXPANSION_MODE;
+
+/*
+ * UNP_VIDEO_FORMAT enum
+ */
+
+typedef enum UNP_VIDEO_FORMAT {
+UNP_VIDEO_FORMAT0 = 0x00000000,
+UNP_VIDEO_FORMAT1 = 0x00000001,
+UNP_VIDEO_FORMAT_YUV420_YCbCr = 0x00000002,
+UNP_VIDEO_FORMAT_YUV420_YCrCb = 0x00000003,
+UNP_VIDEO_FORMAT_YUV422_YCb = 0x00000004,
+UNP_VIDEO_FORMAT_YUV422_YCr = 0x00000005,
+UNP_VIDEO_FORMAT_YUV422_CbY = 0x00000006,
+UNP_VIDEO_FORMAT_YUV422_CrY = 0x00000007,
+} UNP_VIDEO_FORMAT;
+
+/*
+ * UNP_GRPH_ENDIAN_SWAP enum
+ */
+
+typedef enum UNP_GRPH_ENDIAN_SWAP {
+UNP_GRPH_ENDIAN_SWAP_NONE = 0x00000000,
+UNP_GRPH_ENDIAN_SWAP_8IN16 = 0x00000001,
+UNP_GRPH_ENDIAN_SWAP_8IN32 = 0x00000002,
+UNP_GRPH_ENDIAN_SWAP_8IN43 = 0x00000003,
+} UNP_GRPH_ENDIAN_SWAP;
+
+/*
+ * UNP_GRPH_RED_CROSSBAR enum
+ */
+
+typedef enum UNP_GRPH_RED_CROSSBAR {
+UNP_GRPH_RED_CROSSBAR_R_Cr = 0x00000000,
+UNP_GRPH_RED_CROSSBAR_G_Y = 0x00000001,
+UNP_GRPH_RED_CROSSBAR_B_Cb = 0x00000002,
+UNP_GRPH_RED_CROSSBAR_A = 0x00000003,
+} UNP_GRPH_RED_CROSSBAR;
+
+/*
+ * UNP_GRPH_GREEN_CROSSBAR enum
+ */
+
+typedef enum UNP_GRPH_GREEN_CROSSBAR {
+UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y = 0x00000000,
+UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C = 0x00000001,
+UNP_UNP_GRPH_GREEN_CROSSBAR_A = 0x00000002,
+UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr = 0x00000003,
+} UNP_GRPH_GREEN_CROSSBAR;
+
+/*
+ * UNP_GRPH_BLUE_CROSSBAR enum
+ */
+
+typedef enum UNP_GRPH_BLUE_CROSSBAR {
+UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C = 0x00000000,
+UNP_GRPH_BLUE_CROSSBAR_A = 0x00000001,
+UNP_GRPH_BLUE_CROSSBAR_R_Cr = 0x00000002,
+UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y = 0x00000003,
+} UNP_GRPH_BLUE_CROSSBAR;
+
+/*
+ * UNP_GRPH_MODE_UPDATE_LOCKG enum
+ */
+
+typedef enum UNP_GRPH_MODE_UPDATE_LOCKG {
+UNP_GRPH_UPDATE_LOCK_0 = 0x00000000,
+UNP_GRPH_UPDATE_LOCK_1 = 0x00000001,
+} UNP_GRPH_MODE_UPDATE_LOCKG;
+
+/*
+ * UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK enum
+ */
+
+typedef enum UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
+UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0 = 0x00000000,
+UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1 = 0x00000001,
+} UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
+
+/*
+ * UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE enum
+ */
+
+typedef enum UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
+UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0 = 0x00000000,
+UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1 = 0x00000001,
+} UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
+
+/*
+ * UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE enum
+ */
+
+typedef enum UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
+UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0 = 0x00000000,
+UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1 = 0x00000001,
+} UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
+
+/*
+ * UNP_GRPH_STEREOSYNC_FLIP_EN enum
+ */
+
+typedef enum UNP_GRPH_STEREOSYNC_FLIP_EN {
+UNP_GRPH_STEREOSYNC_FLIP_DISABLE = 0x00000000,
+UNP_GRPH_STEREOSYNC_FLIP_ENABLE = 0x00000001,
+} UNP_GRPH_STEREOSYNC_FLIP_EN;
+
+/*
+ * UNP_GRPH_STEREOSYNC_FLIP_MODE enum
+ */
+
+typedef enum UNP_GRPH_STEREOSYNC_FLIP_MODE {
+UNP_GRPH_STEREOSYNC_FLIP_MODE_0 = 0x00000000,
+UNP_GRPH_STEREOSYNC_FLIP_MODE_1 = 0x00000001,
+UNP_GRPH_STEREOSYNC_FLIP_MODE_2 = 0x00000002,
+UNP_GRPH_STEREOSYNC_FLIP_MODE_3 = 0x00000003,
+} UNP_GRPH_STEREOSYNC_FLIP_MODE;
+
+/*
+ * UNP_GRPH_STACK_INTERLACE_FLIP_EN enum
+ */
+
+typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_EN {
+UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE = 0x00000000,
+UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE = 0x00000001,
+} UNP_GRPH_STACK_INTERLACE_FLIP_EN;
+
+/*
+ * UNP_GRPH_STACK_INTERLACE_FLIP_MODE enum
+ */
+
+typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_MODE {
+UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0 = 0x00000000,
+UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1 = 0x00000001,
+UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2 = 0x00000002,
+UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3 = 0x00000003,
+} UNP_GRPH_STACK_INTERLACE_FLIP_MODE;
+
+/*
+ * UNP_GRPH_STEREOSYNC_SELECT_DISABLE enum
+ */
+
+typedef enum UNP_GRPH_STEREOSYNC_SELECT_DISABLE {
+UNP_GRPH_STEREOSYNC_SELECT_EN = 0x00000000,
+UNP_GRPH_STEREOSYNC_SELECT_DIS = 0x00000001,
+} UNP_GRPH_STEREOSYNC_SELECT_DISABLE;
+
+/*
+ * UNP_CRC_SOURCE_SEL enum
+ */
+
+typedef enum UNP_CRC_SOURCE_SEL {
+UNP_CRC_SOURCE_SEL_NP_TO_LBV = 0x00000000,
+UNP_CRC_SOURCE_SEL_LOWER32 = 0x00000001,
+UNP_CRC_SOURCE_SEL_RESERVED = 0x00000002,
+UNP_CRC_SOURCE_SEL_LOWER16 = 0x00000003,
+UNP_CRC_SOURCE_SEL_UNP_TO_LBV = 0x00000004,
+} UNP_CRC_SOURCE_SEL;
+
+/*
+ * UNP_CRC_LINE_SEL enum
+ */
+
+typedef enum UNP_CRC_LINE_SEL {
+UNP_CRC_LINE_SEL_RESERVED = 0x00000000,
+UNP_CRC_LINE_SEL_EVEN_ONLY = 0x00000001,
+UNP_CRC_LINE_SEL_ODD_ONLY = 0x00000002,
+UNP_CRC_LINE_SEL_ODD_EVEN = 0x00000003,
+} UNP_CRC_LINE_SEL;
+
+/*
+ * UNP_ROTATION_ANGLE enum
+ */
+
+typedef enum UNP_ROTATION_ANGLE {
+UNP_ROTATION_ANGLE_0 = 0x00000000,
+UNP_ROTATION_ANGLE_90 = 0x00000001,
+UNP_ROTATION_ANGLE_180 = 0x00000002,
+UNP_ROTATION_ANGLE_270 = 0x00000003,
+UNP_ROTATION_ANGLE_0m = 0x00000004,
+UNP_ROTATION_ANGLE_90m = 0x00000005,
+UNP_ROTATION_ANGLE_180m = 0x00000006,
+UNP_ROTATION_ANGLE_270m = 0x00000007,
+} UNP_ROTATION_ANGLE;
+
+/*
+ * UNP_PIXEL_DROP enum
+ */
+
+typedef enum UNP_PIXEL_DROP {
+UNP_PIXEL_NO_DROP = 0x00000000,
+UNP_PIXEL_DROPPING = 0x00000001,
+} UNP_PIXEL_DROP;
+
+/*
+ * UNP_BUFFER_MODE enum
+ */
+
+typedef enum UNP_BUFFER_MODE {
+UNP_BUFFER_MODE_LUMA = 0x00000000,
+UNP_BUFFER_MODE_LUMA_CHROMA = 0x00000001,
+} UNP_BUFFER_MODE;
+
+/*******************************************************
+ * DP Enums
+ *******************************************************/
+
+/*
+ * DP_LINK_TRAINING_COMPLETE enum
+ */
+
+typedef enum DP_LINK_TRAINING_COMPLETE {
+DP_LINK_TRAINING_NOT_COMPLETE = 0x00000000,
+DP_LINK_TRAINING_ALREADY_COMPLETE = 0x00000001,
+} DP_LINK_TRAINING_COMPLETE;
+
+/*
+ * DP_EMBEDDED_PANEL_MODE enum
+ */
+
+typedef enum DP_EMBEDDED_PANEL_MODE {
+DP_EXTERNAL_PANEL = 0x00000000,
+DP_EMBEDDED_PANEL = 0x00000001,
+} DP_EMBEDDED_PANEL_MODE;
+
+/*
+ * DP_PIXEL_ENCODING enum
+ */
+
+typedef enum DP_PIXEL_ENCODING {
+DP_PIXEL_ENCODING_RGB444 = 0x00000000,
+DP_PIXEL_ENCODING_YCBCR422 = 0x00000001,
+DP_PIXEL_ENCODING_YCBCR444 = 0x00000002,
+DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x00000003,
+DP_PIXEL_ENCODING_Y_ONLY = 0x00000004,
+DP_PIXEL_ENCODING_YCBCR420 = 0x00000005,
+DP_PIXEL_ENCODING_RESERVED = 0x00000006,
+} DP_PIXEL_ENCODING;
+
+/*
+ * DP_DYN_RANGE enum
+ */
+
+typedef enum DP_DYN_RANGE {
+DP_DYN_VESA_RANGE = 0x00000000,
+DP_DYN_CEA_RANGE = 0x00000001,
+} DP_DYN_RANGE;
+
+/*
+ * DP_YCBCR_RANGE enum
+ */
+
+typedef enum DP_YCBCR_RANGE {
+DP_YCBCR_RANGE_BT601_5 = 0x00000000,
+DP_YCBCR_RANGE_BT709_5 = 0x00000001,
+} DP_YCBCR_RANGE;
+
+/*
+ * DP_COMPONENT_DEPTH enum
+ */
+
+typedef enum DP_COMPONENT_DEPTH {
+DP_COMPONENT_DEPTH_6BPC = 0x00000000,
+DP_COMPONENT_DEPTH_8BPC = 0x00000001,
+DP_COMPONENT_DEPTH_10BPC = 0x00000002,
+DP_COMPONENT_DEPTH_12BPC = 0x00000003,
+DP_COMPONENT_DEPTH_16BPC_RESERVED = 0x00000004,
+DP_COMPONENT_DEPTH_RESERVED = 0x00000005,
+} DP_COMPONENT_DEPTH;
+
+/*
+ * DP_MSA_MISC0_OVERRIDE_ENABLE enum
+ */
+
+typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE {
+MSA_MISC0_OVERRIDE_DISABLE = 0x00000000,
+MSA_MISC0_OVERRIDE_ENABLE = 0x00000001,
+} DP_MSA_MISC0_OVERRIDE_ENABLE;
+
+/*
+ * DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE enum
+ */
+
+typedef enum DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE {
+MSA_MISC1_BIT7_OVERRIDE_DISABLE = 0x00000000,
+MSA_MISC1_BIT7_OVERRIDE_ENABLE = 0x00000001,
+} DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE;
+
+/*
+ * DP_UDI_LANES enum
+ */
+
+typedef enum DP_UDI_LANES {
+DP_UDI_1_LANE = 0x00000000,
+DP_UDI_2_LANES = 0x00000001,
+DP_UDI_LANES_RESERVED = 0x00000002,
+DP_UDI_4_LANES = 0x00000003,
+} DP_UDI_LANES;
+
+/*
+ * DP_VID_STREAM_DIS_DEFER enum
+ */
+
+typedef enum DP_VID_STREAM_DIS_DEFER {
+DP_VID_STREAM_DIS_NO_DEFER = 0x00000000,
+DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 0x00000001,
+DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x00000002,
+} DP_VID_STREAM_DIS_DEFER;
+
+/*
+ * DP_STEER_OVERFLOW_ACK enum
+ */
+
+typedef enum DP_STEER_OVERFLOW_ACK {
+DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0x00000000,
+DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001,
+} DP_STEER_OVERFLOW_ACK;
+
+/*
+ * DP_STEER_OVERFLOW_MASK enum
+ */
+
+typedef enum DP_STEER_OVERFLOW_MASK {
+DP_STEER_OVERFLOW_MASKED = 0x00000000,
+DP_STEER_OVERFLOW_UNMASK = 0x00000001,
+} DP_STEER_OVERFLOW_MASK;
+
+/*
+ * DP_TU_OVERFLOW_ACK enum
+ */
+
+typedef enum DP_TU_OVERFLOW_ACK {
+DP_TU_OVERFLOW_ACK_NO_EFFECT = 0x00000000,
+DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001,
+} DP_TU_OVERFLOW_ACK;
+
+/*
+ * DPHY_ALT_SCRAMBLER_RESET_EN enum
+ */
+
+typedef enum DPHY_ALT_SCRAMBLER_RESET_EN {
+DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE = 0x00000000,
+DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION = 0x00000001,
+} DPHY_ALT_SCRAMBLER_RESET_EN;
+
+/*
+ * DPHY_ALT_SCRAMBLER_RESET_SEL enum
+ */
+
+typedef enum DPHY_ALT_SCRAMBLER_RESET_SEL {
+DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE = 0x00000000,
+DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE = 0x00000001,
+} DPHY_ALT_SCRAMBLER_RESET_SEL;
+
+/*
+ * DP_VID_TIMING_MODE enum
+ */
+
+typedef enum DP_VID_TIMING_MODE {
+DP_VID_TIMING_MODE_ASYNC = 0x00000000,
+DP_VID_TIMING_MODE_SYNC = 0x00000001,
+} DP_VID_TIMING_MODE;
+
+/*
+ * DP_VID_M_N_DOUBLE_BUFFER_MODE enum
+ */
+
+typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
+DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x00000000,
+DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 0x00000001,
+} DP_VID_M_N_DOUBLE_BUFFER_MODE;
+
+/*
+ * DP_VID_M_N_GEN_EN enum
+ */
+
+typedef enum DP_VID_M_N_GEN_EN {
+DP_VID_M_N_PROGRAMMED_VIA_REG = 0x00000000,
+DP_VID_M_N_CALC_AUTO = 0x00000001,
+} DP_VID_M_N_GEN_EN;
+
+/*
+ * DP_VID_M_DOUBLE_VALUE_EN enum
+ */
+
+typedef enum DP_VID_M_DOUBLE_VALUE_EN {
+DP_VID_M_INPUT_PIXEL_RATE = 0x00000000,
+DP_VID_M_DOUBLE_INPUT_PIXEL_RATE = 0x00000001,
+} DP_VID_M_DOUBLE_VALUE_EN;
+
+/*
+ * DP_VID_ENHANCED_FRAME_MODE enum
+ */
+
+typedef enum DP_VID_ENHANCED_FRAME_MODE {
+VID_NORMAL_FRAME_MODE = 0x00000000,
+VID_ENHANCED_MODE = 0x00000001,
+} DP_VID_ENHANCED_FRAME_MODE;
+
+/*
+ * DP_VID_MSA_TOP_FIELD_MODE enum
+ */
+
+typedef enum DP_VID_MSA_TOP_FIELD_MODE {
+DP_TOP_FIELD_ONLY = 0x00000000,
+DP_TOP_PLUS_BOTTOM_FIELD = 0x00000001,
+} DP_VID_MSA_TOP_FIELD_MODE;
+
+/*
+ * DP_VID_VBID_FIELD_POL enum
+ */
+
+typedef enum DP_VID_VBID_FIELD_POL {
+DP_VID_VBID_FIELD_POL_NORMAL = 0x00000000,
+DP_VID_VBID_FIELD_POL_INV = 0x00000001,
+} DP_VID_VBID_FIELD_POL;
+
+/*
+ * DP_VID_STREAM_DISABLE_ACK enum
+ */
+
+typedef enum DP_VID_STREAM_DISABLE_ACK {
+ID_STREAM_DISABLE_NO_ACK = 0x00000000,
+ID_STREAM_DISABLE_ACKED = 0x00000001,
+} DP_VID_STREAM_DISABLE_ACK;
+
+/*
+ * DP_VID_STREAM_DISABLE_MASK enum
+ */
+
+typedef enum DP_VID_STREAM_DISABLE_MASK {
+VID_STREAM_DISABLE_MASKED = 0x00000000,
+VID_STREAM_DISABLE_UNMASK = 0x00000001,
+} DP_VID_STREAM_DISABLE_MASK;
+
+/*
+ * DPHY_ATEST_SEL_LANE0 enum
+ */
+
+typedef enum DPHY_ATEST_SEL_LANE0 {
+DPHY_ATEST_LANE0_PRBS_PATTERN = 0x00000000,
+DPHY_ATEST_LANE0_REG_PATTERN = 0x00000001,
+} DPHY_ATEST_SEL_LANE0;
+
+/*
+ * DPHY_ATEST_SEL_LANE1 enum
+ */
+
+typedef enum DPHY_ATEST_SEL_LANE1 {
+DPHY_ATEST_LANE1_PRBS_PATTERN = 0x00000000,
+DPHY_ATEST_LANE1_REG_PATTERN = 0x00000001,
+} DPHY_ATEST_SEL_LANE1;
+
+/*
+ * DPHY_ATEST_SEL_LANE2 enum
+ */
+
+typedef enum DPHY_ATEST_SEL_LANE2 {
+DPHY_ATEST_LANE2_PRBS_PATTERN = 0x00000000,
+DPHY_ATEST_LANE2_REG_PATTERN = 0x00000001,
+} DPHY_ATEST_SEL_LANE2;
+
+/*
+ * DPHY_ATEST_SEL_LANE3 enum
+ */
+
+typedef enum DPHY_ATEST_SEL_LANE3 {
+DPHY_ATEST_LANE3_PRBS_PATTERN = 0x00000000,
+DPHY_ATEST_LANE3_REG_PATTERN = 0x00000001,
+} DPHY_ATEST_SEL_LANE3;
+
+/*
+ * DPHY_SCRAMBLER_SEL enum
+ */
+
+typedef enum DPHY_SCRAMBLER_SEL {
+DPHY_SCRAMBLER_SEL_LANE_DATA = 0x00000000,
+DPHY_SCRAMBLER_SEL_DBG_DATA = 0x00000001,
+} DPHY_SCRAMBLER_SEL;
+
+/*
+ * DPHY_BYPASS enum
+ */
+
+typedef enum DPHY_BYPASS {
+DPHY_8B10B_OUTPUT = 0x00000000,
+DPHY_DBG_OUTPUT = 0x00000001,
+} DPHY_BYPASS;
+
+/*
+ * DPHY_SKEW_BYPASS enum
+ */
+
+typedef enum DPHY_SKEW_BYPASS {
+DPHY_WITH_SKEW = 0x00000000,
+DPHY_NO_SKEW = 0x00000001,
+} DPHY_SKEW_BYPASS;
+
+/*
+ * DPHY_TRAINING_PATTERN_SEL enum
+ */
+
+typedef enum DPHY_TRAINING_PATTERN_SEL {
+DPHY_TRAINING_PATTERN_1 = 0x00000000,
+DPHY_TRAINING_PATTERN_2 = 0x00000001,
+DPHY_TRAINING_PATTERN_3 = 0x00000002,
+DPHY_TRAINING_PATTERN_4 = 0x00000003,
+} DPHY_TRAINING_PATTERN_SEL;
+
+/*
+ * DPHY_8B10B_RESET enum
+ */
+
+typedef enum DPHY_8B10B_RESET {
+DPHY_8B10B_NOT_RESET = 0x00000000,
+DPHY_8B10B_RESETET = 0x00000001,
+} DPHY_8B10B_RESET;
+
+/*
+ * DP_DPHY_8B10B_EXT_DISP enum
+ */
+
+typedef enum DP_DPHY_8B10B_EXT_DISP {
+DP_DPHY_8B10B_EXT_DISP_ZERO = 0x00000000,
+DP_DPHY_8B10B_EXT_DISP_ONE = 0x00000001,
+} DP_DPHY_8B10B_EXT_DISP;
+
+/*
+ * DPHY_8B10B_CUR_DISP enum
+ */
+
+typedef enum DPHY_8B10B_CUR_DISP {
+DPHY_8B10B_CUR_DISP_ZERO = 0x00000000,
+DPHY_8B10B_CUR_DISP_ONE = 0x00000001,
+} DPHY_8B10B_CUR_DISP;
+
+/*
+ * DPHY_PRBS_EN enum
+ */
+
+typedef enum DPHY_PRBS_EN {
+DPHY_PRBS_DISABLE = 0x00000000,
+DPHY_PRBS_ENABLE = 0x00000001,
+} DPHY_PRBS_EN;
+
+/*
+ * DPHY_PRBS_SEL enum
+ */
+
+typedef enum DPHY_PRBS_SEL {
+DPHY_PRBS7_SELECTED = 0x00000000,
+DPHY_PRBS23_SELECTED = 0x00000001,
+DPHY_PRBS11_SELECTED = 0x00000002,
+} DPHY_PRBS_SEL;
+
+/*
+ * DPHY_SCRAMBLER_DIS enum
+ */
+
+typedef enum DPHY_SCRAMBLER_DIS {
+DPHY_SCR_ENABLED = 0x00000000,
+DPHY_SCR_DISABLED = 0x00000001,
+} DPHY_SCRAMBLER_DIS;
+
+/*
+ * DPHY_SCRAMBLER_ADVANCE enum
+ */
+
+typedef enum DPHY_SCRAMBLER_ADVANCE {
+DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY = 0x00000000,
+DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL = 0x00000001,
+} DPHY_SCRAMBLER_ADVANCE;
+
+/*
+ * DPHY_SCRAMBLER_KCODE enum
+ */
+
+typedef enum DPHY_SCRAMBLER_KCODE {
+DPHY_SCRAMBLER_KCODE_DISABLED = 0x00000000,
+DPHY_SCRAMBLER_KCODE_ENABLED = 0x00000001,
+} DPHY_SCRAMBLER_KCODE;
+
+/*
+ * DPHY_LOAD_BS_COUNT_START enum
+ */
+
+typedef enum DPHY_LOAD_BS_COUNT_START {
+DPHY_LOAD_BS_COUNT_STARTED = 0x00000000,
+DPHY_LOAD_BS_COUNT_NOT_STARTED = 0x00000001,
+} DPHY_LOAD_BS_COUNT_START;
+
+/*
+ * DPHY_CRC_EN enum
+ */
+
+typedef enum DPHY_CRC_EN {
+DPHY_CRC_DISABLED = 0x00000000,
+DPHY_CRC_ENABLED = 0x00000001,
+} DPHY_CRC_EN;
+
+/*
+ * DPHY_CRC_CONT_EN enum
+ */
+
+typedef enum DPHY_CRC_CONT_EN {
+DPHY_CRC_ONE_SHOT = 0x00000000,
+DPHY_CRC_CONTINUOUS = 0x00000001,
+} DPHY_CRC_CONT_EN;
+
+/*
+ * DPHY_CRC_FIELD enum
+ */
+
+typedef enum DPHY_CRC_FIELD {
+DPHY_CRC_START_FROM_TOP_FIELD = 0x00000000,
+DPHY_CRC_START_FROM_BOTTOM_FIELD = 0x00000001,
+} DPHY_CRC_FIELD;
+
+/*
+ * DPHY_CRC_SEL enum
+ */
+
+typedef enum DPHY_CRC_SEL {
+DPHY_CRC_LANE0_SELECTED = 0x00000000,
+DPHY_CRC_LANE1_SELECTED = 0x00000001,
+DPHY_CRC_LANE2_SELECTED = 0x00000002,
+DPHY_CRC_LANE3_SELECTED = 0x00000003,
+} DPHY_CRC_SEL;
+
+/*
+ * DPHY_RX_FAST_TRAINING_CAPABLE enum
+ */
+
+typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
+DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0x00000000,
+DPHY_FAST_TRAINING_CAPABLE = 0x00000001,
+} DPHY_RX_FAST_TRAINING_CAPABLE;
+
+/*
+ * DP_SEC_COLLISION_ACK enum
+ */
+
+typedef enum DP_SEC_COLLISION_ACK {
+DP_SEC_COLLISION_ACK_NO_EFFECT = 0x00000000,
+DP_SEC_COLLISION_ACK_CLR_FLAG = 0x00000001,
+} DP_SEC_COLLISION_ACK;
+
+/*
+ * DP_SEC_AUDIO_MUTE enum
+ */
+
+typedef enum DP_SEC_AUDIO_MUTE {
+DP_SEC_AUDIO_MUTE_HW_CTRL = 0x00000000,
+DP_SEC_AUDIO_MUTE_SW_CTRL = 0x00000001,
+} DP_SEC_AUDIO_MUTE;
+
+/*
+ * DP_SEC_TIMESTAMP_MODE enum
+ */
+
+typedef enum DP_SEC_TIMESTAMP_MODE {
+DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0x00000000,
+DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 0x00000001,
+} DP_SEC_TIMESTAMP_MODE;
+
+/*
+ * DP_SEC_ASP_PRIORITY enum
+ */
+
+typedef enum DP_SEC_ASP_PRIORITY {
+DP_SEC_ASP_LOW_PRIORITY = 0x00000000,
+DP_SEC_ASP_HIGH_PRIORITY = 0x00000001,
+} DP_SEC_ASP_PRIORITY;
+
+/*
+ * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum
+ */
+
+typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
+DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0x00000000,
+DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x00000001,
+} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE;
+
+/*
+ * DP_MSE_SAT_UPDATE_ACT enum
+ */
+
+typedef enum DP_MSE_SAT_UPDATE_ACT {
+DP_MSE_SAT_UPDATE_NO_ACTION = 0x00000000,
+DP_MSE_SAT_UPDATE_WITH_TRIGGER = 0x00000001,
+DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 0x00000002,
+} DP_MSE_SAT_UPDATE_ACT;
+
+/*
+ * DP_MSE_LINK_LINE enum
+ */
+
+typedef enum DP_MSE_LINK_LINE {
+DP_MSE_LINK_LINE_32_MTP_LONG = 0x00000000,
+DP_MSE_LINK_LINE_64_MTP_LONG = 0x00000001,
+DP_MSE_LINK_LINE_128_MTP_LONG = 0x00000002,
+DP_MSE_LINK_LINE_256_MTP_LONG = 0x00000003,
+} DP_MSE_LINK_LINE;
+
+/*
+ * DP_MSE_BLANK_CODE enum
+ */
+
+typedef enum DP_MSE_BLANK_CODE {
+DP_MSE_BLANK_CODE_SF_FILLED = 0x00000000,
+DP_MSE_BLANK_CODE_ZERO_FILLED = 0x00000001,
+} DP_MSE_BLANK_CODE;
+
+/*
+ * DP_MSE_TIMESTAMP_MODE enum
+ */
+
+typedef enum DP_MSE_TIMESTAMP_MODE {
+DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0x00000000,
+DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 0x00000001,
+} DP_MSE_TIMESTAMP_MODE;
+
+/*
+ * DP_MSE_ZERO_ENCODER enum
+ */
+
+typedef enum DP_MSE_ZERO_ENCODER {
+DP_MSE_NOT_ZERO_FE_ENCODER = 0x00000000,
+DP_MSE_ZERO_FE_ENCODER = 0x00000001,
+} DP_MSE_ZERO_ENCODER;
+
+/*
+ * DP_MSE_OUTPUT_DPDBG_DATA enum
+ */
+
+typedef enum DP_MSE_OUTPUT_DPDBG_DATA {
+DP_MSE_OUTPUT_DPDBG_DATA_DIS = 0x00000000,
+DP_MSE_OUTPUT_DPDBG_DATA_EN = 0x00000001,
+} DP_MSE_OUTPUT_DPDBG_DATA;
+
+/*
+ * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum
+ */
+
+typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
+DP_DPHY_HBR2_PASS_THROUGH = 0x00000000,
+DP_DPHY_HBR2_PATTERN_1 = 0x00000001,
+DP_DPHY_HBR2_PATTERN_2_NEG = 0x00000002,
+DP_DPHY_HBR2_PATTERN_3 = 0x00000003,
+DP_DPHY_HBR2_PATTERN_2_POS = 0x00000006,
+} DP_DPHY_HBR2_PATTERN_CONTROL_MODE;
+
+/*
+ * DPHY_CRC_MST_PHASE_ERROR_ACK enum
+ */
+
+typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
+DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0x00000000,
+DPHY_CRC_MST_PHASE_ERROR_ACKED = 0x00000001,
+} DPHY_CRC_MST_PHASE_ERROR_ACK;
+
+/*
+ * DPHY_SW_FAST_TRAINING_START enum
+ */
+
+typedef enum DPHY_SW_FAST_TRAINING_START {
+DPHY_SW_FAST_TRAINING_NOT_STARTED = 0x00000000,
+DPHY_SW_FAST_TRAINING_STARTED = 0x00000001,
+} DPHY_SW_FAST_TRAINING_START;
+
+/*
+ * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum
+ */
+
+typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
+DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0x00000000,
+DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x00000001,
+} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN;
+
+/*
+ * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum
+ */
+
+typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
+DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0x00000000,
+DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 0x00000001,
+} DP_DPHY_FAST_TRAINING_COMPLETE_MASK;
+
+/*
+ * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum
+ */
+
+typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
+DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0x00000000,
+DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 0x00000001,
+} DP_DPHY_FAST_TRAINING_COMPLETE_ACK;
+
+/*
+ * DP_MSA_V_TIMING_OVERRIDE_EN enum
+ */
+
+typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
+MSA_V_TIMING_OVERRIDE_DISABLED = 0x00000000,
+MSA_V_TIMING_OVERRIDE_ENABLED = 0x00000001,
+} DP_MSA_V_TIMING_OVERRIDE_EN;
+
+/*
+ * DP_SEC_GSP0_PRIORITY enum
+ */
+
+typedef enum DP_SEC_GSP0_PRIORITY {
+SEC_GSP0_PRIORITY_LOW = 0x00000000,
+SEC_GSP0_PRIORITY_HIGH = 0x00000001,
+} DP_SEC_GSP0_PRIORITY;
+
+/*
+ * DP_SEC_GSP0_SEND enum
+ */
+
+typedef enum DP_SEC_GSP0_SEND {
+NOT_SENT = 0x00000000,
+FORCE_SENT = 0x00000001,
+} DP_SEC_GSP0_SEND;
+
+/*******************************************************
+ * COL_MAN Enums
+ *******************************************************/
+
+/*
+ * COL_MAN_UPDATE_LOCK enum
+ */
+
+typedef enum COL_MAN_UPDATE_LOCK {
+COL_MAN_UPDATE_UNLOCKED = 0x00000000,
+COL_MAN_UPDATE_LOCKED = 0x00000001,
+} COL_MAN_UPDATE_LOCK;
+
+/*
+ * COL_MAN_DISABLE_MULTIPLE_UPDATE enum
+ */
+
+typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE {
+COL_MAN_MULTIPLE_UPDATE = 0x00000000,
+COL_MAN_MULTIPLE_UPDAT_EDISABLE = 0x00000001,
+} COL_MAN_DISABLE_MULTIPLE_UPDATE;
+
+/*
+ * COL_MAN_INPUTCSC_MODE enum
+ */
+
+typedef enum COL_MAN_INPUTCSC_MODE {
+INPUTCSC_MODE_BYPASS = 0x00000000,
+INPUTCSC_MODE_A = 0x00000001,
+INPUTCSC_MODE_B = 0x00000002,
+INPUTCSC_MODE_UNITY = 0x00000003,
+} COL_MAN_INPUTCSC_MODE;
+
+/*
+ * COL_MAN_INPUTCSC_TYPE enum
+ */
+
+typedef enum COL_MAN_INPUTCSC_TYPE {
+INPUTCSC_TYPE_12_0 = 0x00000000,
+INPUTCSC_TYPE_10_2 = 0x00000001,
+INPUTCSC_TYPE_8_4 = 0x00000002,
+} COL_MAN_INPUTCSC_TYPE;
+
+/*
+ * COL_MAN_INPUTCSC_CONVERT enum
+ */
+
+typedef enum COL_MAN_INPUTCSC_CONVERT {
+INPUTCSC_ROUND = 0x00000000,
+INPUTCSC_TRUNCATE = 0x00000001,
+} COL_MAN_INPUTCSC_CONVERT;
+
+/*
+ * COL_MAN_PRESCALE_MODE enum
+ */
+
+typedef enum COL_MAN_PRESCALE_MODE {
+PRESCALE_MODE_BYPASS = 0x00000000,
+PRESCALE_MODE_PROGRAM = 0x00000001,
+PRESCALE_MODE_UNITY = 0x00000002,
+} COL_MAN_PRESCALE_MODE;
+
+/*
+ * COL_MAN_INPUT_GAMMA_MODE enum
+ */
+
+typedef enum COL_MAN_INPUT_GAMMA_MODE {
+INGAMMA_MODE_BYPASS = 0x00000000,
+INGAMMA_MODE_FIX = 0x00000001,
+INGAMMA_MODE_FLOAT = 0x00000002,
+} COL_MAN_INPUT_GAMMA_MODE;
+
+/*
+ * COL_MAN_OUTPUT_CSC_MODE enum
+ */
+
+typedef enum COL_MAN_OUTPUT_CSC_MODE {
+COL_MAN_OUTPUT_CSC_BYPASS = 0x00000000,
+COL_MAN_OUTPUT_CSC_RGB = 0x00000001,
+COL_MAN_OUTPUT_CSC_YCrCb601 = 0x00000002,
+COL_MAN_OUTPUT_CSC_YCrCb709 = 0x00000003,
+COL_MAN_OUTPUT_CSC_A = 0x00000004,
+COL_MAN_OUTPUT_CSC_B = 0x00000005,
+COL_MAN_OUTPUT_CSC_UNITY = 0x00000006,
+} COL_MAN_OUTPUT_CSC_MODE;
+
+/*
+ * COL_MAN_DENORM_CLAMP_CONTROL enum
+ */
+
+typedef enum COL_MAN_DENORM_CLAMP_CONTROL {
+DENORM_CLAMP_MODE_UNITY = 0x00000000,
+DENORM_CLAMP_MODE_8 = 0x00000001,
+DENORM_CLAMP_MODE_10 = 0x00000002,
+DENORM_CLAMP_MODE_12 = 0x00000003,
+} COL_MAN_DENORM_CLAMP_CONTROL;
+
+/*
+ * COL_MAN_REGAMMA_MODE_CONTROL enum
+ */
+
+typedef enum COL_MAN_REGAMMA_MODE_CONTROL {
+COL_MAN_REGAMMA_MODE_BYPASS = 0x00000000,
+COL_MAN_REGAMMA_MODE_ROM_A = 0x00000001,
+COL_MAN_REGAMMA_MODE_ROM_B = 0x00000002,
+COL_MAN_REGAMMA_MODE_A = 0x00000003,
+COL_MAN_REGAMMA_MODE_B = 0x00000004,
+} COL_MAN_REGAMMA_MODE_CONTROL;
+
+/*
+ * COL_MAN_GLOBAL_PASSTHROUGH_ENABLE enum
+ */
+
+typedef enum COL_MAN_GLOBAL_PASSTHROUGH_ENABLE {
+CM_GLOBAL_PASSTHROUGH_DISBALE = 0x00000000,
+CM_GLOBAL_PASSTHROUGH_ENABLE = 0x00000001,
+} COL_MAN_GLOBAL_PASSTHROUGH_ENABLE;
+
+/*
+ * COL_MAN_DEGAMMA_MODE enum
+ */
+
+typedef enum COL_MAN_DEGAMMA_MODE {
+DEGAMMA_MODE_BYPASS = 0x00000000,
+DEGAMMA_MODE_A = 0x00000001,
+DEGAMMA_MODE_B = 0x00000002,
+} COL_MAN_DEGAMMA_MODE;
+
+/*
+ * COL_MAN_GAMUT_REMAP_MODE enum
+ */
+
+typedef enum COL_MAN_GAMUT_REMAP_MODE {
+GAMUT_REMAP_MODE_BYPASS = 0x00000000,
+GAMUT_REMAP_MODE_1 = 0x00000001,
+GAMUT_REMAP_MODE_2 = 0x00000002,
+GAMUT_REMAP_MODE_3 = 0x00000003,
+} COL_MAN_GAMUT_REMAP_MODE;
+
+/*******************************************************
+ * MCIF_WB Enums
+ *******************************************************/
+
+/*******************************************************
+ * DP_AUX Enums
+ *******************************************************/
+
+/*
+ * DP_AUX_CONTROL_HPD_SEL enum
+ */
+
+typedef enum DP_AUX_CONTROL_HPD_SEL {
+DP_AUX_CONTROL_HPD1_SELECTED = 0x00000000,
+DP_AUX_CONTROL_HPD2_SELECTED = 0x00000001,
+DP_AUX_CONTROL_HPD3_SELECTED = 0x00000002,
+DP_AUX_CONTROL_HPD4_SELECTED = 0x00000003,
+DP_AUX_CONTROL_HPD5_SELECTED = 0x00000004,
+DP_AUX_CONTROL_HPD6_SELECTED = 0x00000005,
+} DP_AUX_CONTROL_HPD_SEL;
+
+/*
+ * DP_AUX_CONTROL_TEST_MODE enum
+ */
+
+typedef enum DP_AUX_CONTROL_TEST_MODE {
+DP_AUX_CONTROL_TEST_MODE_DISABLE = 0x00000000,
+DP_AUX_CONTROL_TEST_MODE_ENABLE = 0x00000001,
+} DP_AUX_CONTROL_TEST_MODE;
+
+/*
+ * DP_AUX_SW_CONTROL_SW_GO enum
+ */
+
+typedef enum DP_AUX_SW_CONTROL_SW_GO {
+DP_AUX_SW_CONTROL_SW__NOT_GO = 0x00000000,
+DP_AUX_SW_CONTROL_SW__GO = 0x00000001,
+} DP_AUX_SW_CONTROL_SW_GO;
+
+/*
+ * DP_AUX_SW_CONTROL_LS_READ_TRIG enum
+ */
+
+typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
+DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0x00000000,
+DP_AUX_SW_CONTROL_LS_READ__TRIG = 0x00000001,
+} DP_AUX_SW_CONTROL_LS_READ_TRIG;
+
+/*
+ * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum
+ */
+
+typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
+DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0x00000000,
+DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 0x00000001,
+DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x00000002,
+DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 0x00000003,
+} DP_AUX_ARB_CONTROL_ARB_PRIORITY;
+
+/*
+ * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum
+ */
+
+typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
+DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0x00000000,
+DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 0x00000001,
+} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ;
+
+/*
+ * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum
+ */
+
+typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
+DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x00000000,
+DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 0x00000001,
+} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG;
+
+/*
+ * DP_AUX_INT_ACK enum
+ */
+
+typedef enum DP_AUX_INT_ACK {
+DP_AUX_INT__NOT_ACK = 0x00000000,
+DP_AUX_INT__ACK = 0x00000001,
+} DP_AUX_INT_ACK;
+
+/*
+ * DP_AUX_LS_UPDATE_ACK enum
+ */
+
+typedef enum DP_AUX_LS_UPDATE_ACK {
+DP_AUX_INT_LS_UPDATE_NOT_ACK = 0x00000000,
+DP_AUX_INT_LS_UPDATE_ACK = 0x00000001,
+} DP_AUX_LS_UPDATE_ACK;
+
+/*
+ * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum
+ */
+
+typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
+DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0x00000000,
+DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 0x00000001,
+} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL;
+
+/*
+ * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum
+ */
+
+typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
+DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x00000000,
+DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x00000001,
+DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x00000002,
+DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x00000003,
+} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE;
+
+/*
+ * DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN enum
+ */
+
+typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN {
+DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US = 0x00000000,
+DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US = 0x00000001,
+DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US = 0x00000002,
+DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US = 0x00000003,
+DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US = 0x00000004,
+DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US = 0x00000005,
+DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US = 0x00000006,
+DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US = 0x00000007,
+} DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN;
+
+/*
+ * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum
+ */
+
+typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
+DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x00000000,
+DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 0x00000001,
+DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 0x00000002,
+DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 0x00000003,
+DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 0x00000004,
+DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 0x00000005,
+} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY;
+
+/*
+ * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum
+ */
+
+typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
+DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x00000000,
+DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x00000001,
+DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x00000002,
+DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 0x00000003,
+DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 0x00000004,
+DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 0x00000005,
+DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 0x00000006,
+DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 0x00000007,
+} DP_AUX_DPHY_RX_CONTROL_START_WINDOW;
+
+/*
+ * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum
+ */
+
+typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
+DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0x00000000,
+DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 0x00000001,
+DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 0x00000002,
+DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 0x00000003,
+DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 0x00000004,
+DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 0x00000005,
+DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 0x00000006,
+DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 0x00000007,
+} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW;
+
+/*
+ * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum
+ */
+
+typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
+DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0x00000000,
+DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 0x00000001,
+DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 0x00000002,
+DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 0x00000003,
+} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN;
+
+/*
+ * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum
+ */
+
+typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
+DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000000,
+DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000001,
+} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT;
+
+/*
+ * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum
+ */
+
+typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
+DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0x00000000,
+DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 0x00000001,
+} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START;
+
+/*
+ * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum
+ */
+
+typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
+DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0x00000000,
+DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 0x00000001,
+} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP;
+
+/*
+ * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum
+ */
+
+typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
+DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0x00000000,
+DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 0x00000001,
+DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 0x00000002,
+DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 0x00000003,
+} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN;
+
+/*
+ * DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN enum
+ */
+
+typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN {
+DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US = 0x00000000,
+DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US = 0x00000001,
+DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US = 0x00000002,
+DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US = 0x00000003,
+DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US = 0x00000004,
+DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US = 0x00000005,
+DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US = 0x00000006,
+DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US = 0x00000007,
+} DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN;
+
+/*
+ * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum
+ */
+
+typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
+DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0x00000000,
+DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 0x00000001,
+DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x00000002,
+DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 0x00000003,
+DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 0x00000004,
+DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 0x00000005,
+DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 0x00000006,
+DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 0x00000007,
+} DP_AUX_DPHY_RX_DETECTION_THRESHOLD;
+
+/*
+ * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum
+ */
+
+typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
+DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0x00000000,
+DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 0x00000001,
+} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ;
+
+/*
+ * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum
+ */
+
+typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
+DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0x00000000,
+DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 0x00000001,
+DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 0x00000002,
+DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 0x00000003,
+} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW;
+
+/*
+ * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum
+ */
+
+typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
+DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0x00000000,
+DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 0x00000001,
+DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 0x00000002,
+DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 0x00000003,
+} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT;
+
+/*
+ * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum
+ */
+
+typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
+DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0x00000000,
+DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 0x00000001,
+DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 0x00000002,
+DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 0x00000003,
+} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN;
+
+/*
+ * DP_AUX_ERR_OCCURRED_ACK enum
+ */
+
+typedef enum DP_AUX_ERR_OCCURRED_ACK {
+DP_AUX_ERR_OCCURRED__NOT_ACK = 0x00000000,
+DP_AUX_ERR_OCCURRED__ACK = 0x00000001,
+} DP_AUX_ERR_OCCURRED_ACK;
+
+/*
+ * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum
+ */
+
+typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
+DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0x00000000,
+DP_AUX_POTENTIAL_ERR_REACHED__ACK = 0x00000001,
+} DP_AUX_POTENTIAL_ERR_REACHED_ACK;
+
+/*
+ * DP_AUX_DEFINITE_ERR_REACHED_ACK enum
+ */
+
+typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
+ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x00000000,
+ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 0x00000001,
+} DP_AUX_DEFINITE_ERR_REACHED_ACK;
+
+/*
+ * DP_AUX_RESET enum
+ */
+
+typedef enum DP_AUX_RESET {
+DP_AUX_RESET_DEASSERTED = 0x00000000,
+DP_AUX_RESET_ASSERTED = 0x00000001,
+} DP_AUX_RESET;
+
+/*
+ * DP_AUX_RESET_DONE enum
+ */
+
+typedef enum DP_AUX_RESET_DONE {
+DP_AUX_RESET_SEQUENCE_NOT_DONE = 0x00000000,
+DP_AUX_RESET_SEQUENCE_DONE = 0x00000001,
+} DP_AUX_RESET_DONE;
+
+/*******************************************************
+ * DSI Enums
+ *******************************************************/
+
+/*
+ * DSI_COMMAND_MODE_SRC_FORMAT enum
+ */
+
+typedef enum DSI_COMMAND_MODE_SRC_FORMAT {
+DSI_COMMAND_SRC_FORMAT_RGB8BIT = 0x00000002,
+DSI_COMMAND_SRC_FORMAT_RGB332 = 0x00000003,
+DSI_COMMAND_SRC_FORMAT_RGB444 = 0x00000004,
+DSI_COMMAND_SRC_FORMAT_RGB555 = 0x00000005,
+DSI_COMMAND_SRC_FORMAT_RGB565 = 0x00000006,
+DSI_COMMAND_SRC_FORMAT_RGB888 = 0x00000008,
+} DSI_COMMAND_MODE_SRC_FORMAT;
+
+/*
+ * DSI_COMMAND_MODE_DST_FORMAT enum
+ */
+
+typedef enum DSI_COMMAND_MODE_DST_FORMAT {
+DSI_COMMAND_DST_FORMAT_RGB111 = 0x00000000,
+DSI_COMMAND_DST_FORMAT_RGB332 = 0x00000003,
+DSI_COMMAND_DST_FORMAT_RGB444 = 0x00000004,
+DSI_COMMAND_DST_FORMAT_RGB565 = 0x00000006,
+DSI_COMMAND_DST_FORMAT_RGB666 = 0x00000007,
+DSI_COMMAND_DST_FORMAT_RGB888 = 0x00000008,
+} DSI_COMMAND_MODE_DST_FORMAT;
+
+/*
+ * DSI_FLAG_CLR enum
+ */
+
+typedef enum DSI_FLAG_CLR {
+DSI_FLAG_NO_CLEAR = 0x00000000,
+DSI_FLAG_CLEAR = 0x00000001,
+} DSI_FLAG_CLR;
+
+/*
+ * DSI_BIT_SWAP enum
+ */
+
+typedef enum DSI_BIT_SWAP {
+DSI_BIT_SWAP_DISABLE = 0x00000000,
+DSI_BIT_SWAP_ENABLE = 0x00000001,
+} DSI_BIT_SWAP;
+
+/*
+ * DSI_CLK_GATING enum
+ */
+
+typedef enum DSI_CLK_GATING {
+DSI_CLK_GATING_ENABLE = 0x00000000,
+DSI_CLK_GATING_DISABLE = 0x00000001,
+} DSI_CLK_GATING;
+
+/*
+ * DSI_LANE_ULPS_REQUEST enum
+ */
+
+typedef enum DSI_LANE_ULPS_REQUEST {
+DSI_LANE_ULPS_REQUEST_DEASSERT = 0x00000000,
+DSI_LANE_ULPS_REQUEST_ASSERT = 0x00000001,
+} DSI_LANE_ULPS_REQUEST;
+
+/*
+ * DSI_LANE_ULPS_EXIT enum
+ */
+
+typedef enum DSI_LANE_ULPS_EXIT {
+DSI_LANE_ULPS_EXIT_DEASSERT = 0x00000000,
+DSI_LANE_ULPS_EXIT_ASSERT = 0x00000001,
+} DSI_LANE_ULPS_EXIT;
+
+/*
+ * DSI_LANE_FORCE_TX_STOP enum
+ */
+
+typedef enum DSI_LANE_FORCE_TX_STOP {
+DSI_LANE_FORCE_TX_STOP_DEASSERT = 0x00000000,
+DSI_LANE_FORCE_TX_STOP_ASSERT = 0x00000001,
+} DSI_LANE_FORCE_TX_STOP;
+
+/*
+ * DSI_CLOCK_LANE_HS_FORCE_REQUEST enum
+ */
+
+typedef enum DSI_CLOCK_LANE_HS_FORCE_REQUEST {
+DSI_CLOCK_LANE_HS_FORCE_REQUEST_DEASSERT = 0x00000000,
+DSI_CLOCK_LANE_HS_FORCE_REQUEST_ASSERT = 0x00000001,
+} DSI_CLOCK_LANE_HS_FORCE_REQUEST;
+
+/*
+ * DSI_CONTROLLER_EN enum
+ */
+
+typedef enum DSI_CONTROLLER_EN {
+DSI_CONTROLLER_DISABLE = 0x00000000,
+DSI_CONTROLLER_ENABLE = 0x00000001,
+} DSI_CONTROLLER_EN;
+
+/*
+ * DSI_VIDEO_MODE_EN enum
+ */
+
+typedef enum DSI_VIDEO_MODE_EN {
+DSI_VIDEO_MODE_DISABLE = 0x00000000,
+DSI_VIDEO_MODE_ENABLE = 0x00000001,
+} DSI_VIDEO_MODE_EN;
+
+/*
+ * DSI_CMD_MODE_EN enum
+ */
+
+typedef enum DSI_CMD_MODE_EN {
+DSI_CMD_MODE_DISABLE = 0x00000000,
+DSI_CMD_MODE_ENABLE = 0x00000001,
+} DSI_CMD_MODE_EN;
+
+/*
+ * DSI_DATA_LANE0_EN enum
+ */
+
+typedef enum DSI_DATA_LANE0_EN {
+DSI_DATA_LANE0_DISABLE = 0x00000000,
+DSI_DATA_LANE0_ENABLE = 0x00000001,
+} DSI_DATA_LANE0_EN;
+
+/*
+ * DSI_DATA_LANE1_EN enum
+ */
+
+typedef enum DSI_DATA_LANE1_EN {
+DSI_DATA_LANE1_DISABLE = 0x00000000,
+DSI_DATA_LANE1_ENABLE = 0x00000001,
+} DSI_DATA_LANE1_EN;
+
+/*
+ * DSI_DATA_LANE2_EN enum
+ */
+
+typedef enum DSI_DATA_LANE2_EN {
+DSI_DATA_LANE2_DISABLE = 0x00000000,
+DSI_DATA_LANE2_ENABLE = 0x00000001,
+} DSI_DATA_LANE2_EN;
+
+/*
+ * DSI_DATA_LANE3_EN enum
+ */
+
+typedef enum DSI_DATA_LANE3_EN {
+DSI_DATA_LANE3_DISABLE = 0x00000000,
+DSI_DATA_LANE3_ENABLE = 0x00000001,
+} DSI_DATA_LANE3_EN;
+
+/*
+ * DSI_CLOCK_LANE_EN enum
+ */
+
+typedef enum DSI_CLOCK_LANE_EN {
+DSI_CLOCK_LANE_DISABLE = 0x00000000,
+DSI_CLOCK_LANE_ENABLE = 0x00000001,
+} DSI_CLOCK_LANE_EN;
+
+/*
+ * DSI_PHY_DATA_LANE0_EN enum
+ */
+
+typedef enum DSI_PHY_DATA_LANE0_EN {
+DSI_PHY_DATA_LANE0_DISABLE = 0x00000000,
+DSI_PHY_DATA_LANE0_ENABLE = 0x00000001,
+} DSI_PHY_DATA_LANE0_EN;
+
+/*
+ * DSI_PHY_DATA_LANE1_EN enum
+ */
+
+typedef enum DSI_PHY_DATA_LANE1_EN {
+DSI_PHY_DATA_LANE1_DISABLE = 0x00000000,
+DSI_PHY_DATA_LANE1_ENABLE = 0x00000001,
+} DSI_PHY_DATA_LANE1_EN;
+
+/*
+ * DSI_PHY_DATA_LANE2_EN enum
+ */
+
+typedef enum DSI_PHY_DATA_LANE2_EN {
+DSI_PHY_DATA_LANE2_DISABLE = 0x00000000,
+DSI_PHY_DATA_LANE2_ENABLE = 0x00000001,
+} DSI_PHY_DATA_LANE2_EN;
+
+/*
+ * DSI_PHY_DATA_LANE3_EN enum
+ */
+
+typedef enum DSI_PHY_DATA_LANE3_EN {
+DSI_PHY_DATA_LANE3_DISABLE = 0x00000000,
+DSI_PHY_DATA_LANE3_ENABLE = 0x00000001,
+} DSI_PHY_DATA_LANE3_EN;
+
+/*
+ * DSI_RESET_DISPCLK enum
+ */
+
+typedef enum DSI_RESET_DISPCLK {
+DSI_NO_RESET_ON_DISPCLK_DOMAIN_LOGIC = 0x00000000,
+DSI_RESET_ON_DISPCLK_DOMAIN_LOGIC = 0x00000001,
+} DSI_RESET_DISPCLK;
+
+/*
+ * DSI_RESET_DSICLK enum
+ */
+
+typedef enum DSI_RESET_DSICLK {
+DSI_NO_RESET_ON_DSICLK_DOMAIN_LOGIC = 0x00000000,
+DSI_RESET_ON_DSICLK_DOMAIN_LOGIC = 0x00000001,
+} DSI_RESET_DSICLK;
+
+/*
+ * DSI_RESET_BYTECLK enum
+ */
+
+typedef enum DSI_RESET_BYTECLK {
+DSI_NO_RESET_ON_BYTECLK_DOMAIN_LOGIC = 0x00000000,
+DSI_RESET_ON_BYTECLK_DOMAIN_LOGIC = 0x00000001,
+} DSI_RESET_BYTECLK;
+
+/*
+ * DSI_RESET_ESCCLK enum
+ */
+
+typedef enum DSI_RESET_ESCCLK {
+DSI_NO_RESET_ON_ESCCLK_DOMAIN_LOGIC = 0x00000000,
+DSI_RESET_ON_ESCCLK_DOMAIN_LOGIC = 0x00000001,
+} DSI_RESET_ESCCLK;
+
+/*
+ * DSI_CRTC_SEL enum
+ */
+
+typedef enum DSI_CRTC_SEL {
+DSI_GET_PIXEL_STREAM_FROM_FMT0 = 0x00000000,
+DSI_GET_PIXEL_STREAM_FROM_FMT1 = 0x00000001,
+DSI_GET_PIXEL_STREAM_FROM_FMT2 = 0x00000002,
+DSI_GET_PIXEL_STREAM_FROM_FMT3 = 0x00000003,
+DSI_GET_PIXEL_STREAM_FROM_FMT4 = 0x00000004,
+DSI_GET_PIXEL_STREAM_FROM_FMT5 = 0x00000005,
+} DSI_CRTC_SEL;
+
+/*
+ * DSI_PACKET_BYTE_MSB_LSB_FLIP enum
+ */
+
+typedef enum DSI_PACKET_BYTE_MSB_LSB_FLIP {
+DSI_PACKET_BYTE_MSB_LSB_FLIP_NO_SWAP = 0x00000000,
+DSI_PACKET_BYTE_MSB_LSB_FLIP_SWAP = 0x00000001,
+} DSI_PACKET_BYTE_MSB_LSB_FLIP;
+
+/*
+ * DSI_VIDEO_MODE_DST_FORMAT enum
+ */
+
+typedef enum DSI_VIDEO_MODE_DST_FORMAT {
+DSI_VIDEO_DST_FORMAT_RGB565 = 0x00000000,
+DSI_VIDEO_DST_FORMAT_RGB666_PACKED = 0x00000001,
+DSI_VIDEO_DST_FORMAT_RGB666_LOOSELY_PACKED = 0x00000002,
+DSI_VIDEO_DST_FORMAT_RGB888 = 0x00000003,
+} DSI_VIDEO_MODE_DST_FORMAT;
+
+/*
+ * DSI_VIDEO_TRAFFIC_MODE enum
+ */
+
+typedef enum DSI_VIDEO_TRAFFIC_MODE {
+DSI_TRAFFIC_MODE_SYNC_PULSES = 0x00000000,
+DSI_TRAFFIC_MODE_SYNC_EVENTS = 0x00000001,
+DSI_TRAFFIC_MODE_BURST = 0x00000002,
+DSI_TRAFFIC_MODE_RESERVED = 0x00000003,
+} DSI_VIDEO_TRAFFIC_MODE;
+
+/*
+ * DSI_VIDEO_BLLP_PWR_MODE enum
+ */
+
+typedef enum DSI_VIDEO_BLLP_PWR_MODE {
+DSI_VIDEO_BLLP_PWR_MODE_HS = 0x00000000,
+DSI_VIDEO_BLLP_PWR_MODE_LP = 0x00000001,
+} DSI_VIDEO_BLLP_PWR_MODE;
+
+/*
+ * DSI_VIDEO_EOF_BLLP_PWR_MODE enum
+ */
+
+typedef enum DSI_VIDEO_EOF_BLLP_PWR_MODE {
+DSI_VIDEO_EOF_BLLP_PWR_MODE_HS = 0x00000000,
+DSI_VIDEO_EOF_BLLP_PWR_MODE_LP = 0x00000001,
+} DSI_VIDEO_EOF_BLLP_PWR_MODE;
+
+/*
+ * DSI_VIDEO_PWR_MODE enum
+ */
+
+typedef enum DSI_VIDEO_PWR_MODE {
+DSI_VIDEO_PWR_MODE_HS = 0x00000000,
+DSI_VIDEO_PWR_MODE_LP = 0x00000001,
+} DSI_VIDEO_PWR_MODE;
+
+/*
+ * DSI_VIDEO_PULSE_MODE_OPT enum
+ */
+
+typedef enum DSI_VIDEO_PULSE_MODE_OPT {
+PULSE_MODE_OPT_NO_HSA = 0x00000000,
+PULSE_MODE_OPT_SEND = 0x00000001,
+} DSI_VIDEO_PULSE_MODE_OPT;
+
+/*
+ * DSI_RGB_SWAP enum
+ */
+
+typedef enum DSI_RGB_SWAP {
+DSI_SWAP_RGB = 0x00000000,
+DSI_SWAP_RBG = 0x00000001,
+DSI_SWAP_BGR = 0x00000002,
+DSI_SWAP_BRG = 0x00000003,
+DSI_SWAP_GRB = 0x00000004,
+DSI_SWAP_GBR = 0x00000005,
+} DSI_RGB_SWAP;
+
+/*
+ * DSI_CMD_PACKET_TYPE enum
+ */
+
+typedef enum DSI_CMD_PACKET_TYPE {
+DSI_CMD_PACKET_TYPE_SHORT = 0x00000000,
+DSI_CMD_PACKET_TYPE_LONG = 0x00000001,
+} DSI_CMD_PACKET_TYPE;
+
+/*
+ * DSI_CMD_PWR_MODE enum
+ */
+
+typedef enum DSI_CMD_PWR_MODE {
+DSI_CMD_PWR_MODE_HS = 0x00000000,
+DSI_CMD_PWR_MODE_LP = 0x00000001,
+} DSI_CMD_PWR_MODE;
+
+/*
+ * DSI_CMD_EMBEDDED_MODE enum
+ */
+
+typedef enum DSI_CMD_EMBEDDED_MODE {
+CMD_EMBEDDED_MODE_DISABLE = 0x00000000,
+CMD_EMBEDDED_MODE_ENABLE = 0x00000001,
+} DSI_CMD_EMBEDDED_MODE;
+
+/*
+ * DSI_CMD_ORDER enum
+ */
+
+typedef enum DSI_CMD_ORDER {
+DSI_CMD_ORDER_COMMAND_FIRST = 0x00000000,
+DSI_CMD_ORDER_DATA_FIRST = 0x00000001,
+} DSI_CMD_ORDER;
+
+/*
+ * DSI_DATA_BUFFER_ID enum
+ */
+
+typedef enum DSI_DATA_BUFFER_ID {
+DSI_DATA_BUFFER_OFFSET0 = 0x00000000,
+DSI_DATA_BUFFER_OFFSET1 = 0x00000001,
+} DSI_DATA_BUFFER_ID;
+
+/*
+ * DSI_DWORD_BYTE_SWAP enum
+ */
+
+typedef enum DSI_DWORD_BYTE_SWAP {
+DWORD_BYTE_SWAP_NO_SWAP = 0x00000000,
+DWORD_BYTE_SWAP_BYTE_SWAP = 0x00000001,
+DWORD_BYTE_SWAP_WORD_SWAP = 0x00000002,
+DWORD_BYTE_SWAP_BOTH_SWAP = 0x00000003,
+} DSI_DWORD_BYTE_SWAP;
+
+/*
+ * DSI_INSERT_DCS_COMMAND enum
+ */
+
+typedef enum DSI_INSERT_DCS_COMMAND {
+DSI_INSERT_DCS_COMMAND_DISABLE = 0x00000000,
+DSI_INSERT_DCS_COMMAND_ENABLE = 0x00000001,
+} DSI_INSERT_DCS_COMMAND;
+
+/*
+ * DSI_DMAFIFO_WRITE_WATERMARK enum
+ */
+
+typedef enum DSI_DMAFIFO_WRITE_WATERMARK {
+DSI_DMAFIFO_WRITE_WATERMARK_HALF = 0x00000000,
+DSI_DMAFIFO_WRITE_WATERMARK_FOURTH = 0x00000001,
+DSI_DMAFIFO_WRITE_WATERMARK_EIGHTH = 0x00000002,
+DSI_DMAFIFO_WRITE_WATERMARK_SIXTEENTH = 0x00000003,
+} DSI_DMAFIFO_WRITE_WATERMARK;
+
+/*
+ * DSI_DMAFIFO_READ_WATERMARK enum
+ */
+
+typedef enum DSI_DMAFIFO_READ_WATERMARK {
+DSI_DMAFIFO_READ_WATERMARK_HALF = 0x00000000,
+DSI_DMAFIFO_READ_WATERMARK_FOURTH = 0x00000001,
+DSI_DMAFIFO_READ_WATERMARK_EIGHTH = 0x00000002,
+DSI_DMAFIFO_READ_WATERMARK_SIXTEENTH = 0x00000003,
+} DSI_DMAFIFO_READ_WATERMARK;
+
+/*
+ * DSI_USE_DENG_LENGTH enum
+ */
+
+typedef enum DSI_USE_DENG_LENGTH {
+DSI_USE_DENG_LENGTH_DISABLE = 0x00000000,
+DSI_USE_DENG_LENGTH_ENABLE = 0x00000001,
+} DSI_USE_DENG_LENGTH;
+
+/*
+ * DSI_COMMAND_TRIGGER_MODE enum
+ */
+
+typedef enum DSI_COMMAND_TRIGGER_MODE {
+DSI_COMMAND_TRIGGER_MODE_AUTO = 0x00000000,
+DSI_COMMAND_TRIGGER_MODE_MANUAL = 0x00000001,
+} DSI_COMMAND_TRIGGER_MODE;
+
+/*
+ * DSI_COMMAND_TRIGGER_SEL enum
+ */
+
+typedef enum DSI_COMMAND_TRIGGER_SEL {
+DSI_COMMAND_TRIGGER_SEL_NONE = 0x00000000,
+DSI_COMMAND_TRIGGER_SEL_CRTC = 0x00000001,
+DSI_COMMAND_TRIGGER_SEL_TE = 0x00000002,
+DSI_COMMAND_TRIGGER_SEL_HW = 0x00000003,
+} DSI_COMMAND_TRIGGER_SEL;
+
+/*
+ * DSI_HW_SOURCE_SEL enum
+ */
+
+typedef enum DSI_HW_SOURCE_SEL {
+HW_SOURCE_SEL_NONE = 0x00000000,
+HW_SOURCE_SEL_DSC_VUP = 0x00000001,
+HW_SOURCE_SEL_DSC_VLP = 0x00000002,
+HW_SOURCE_SEL_DSC_JPEG = 0x00000003,
+} DSI_HW_SOURCE_SEL;
+
+/*
+ * DSI_COMMAND_TRIGGER_ORDER enum
+ */
+
+typedef enum DSI_COMMAND_TRIGGER_ORDER {
+DSI_COMMAND_TRIGGER_ORDER_DMA = 0x00000000,
+DSI_COMMAND_TRIGGER_ORDER_DENG = 0x00000001,
+} DSI_COMMAND_TRIGGER_ORDER;
+
+/*
+ * DSI_TE_SRC_SEL enum
+ */
+
+typedef enum DSI_TE_SRC_SEL {
+DSI_TE_SEL_LINK = 0x00000000,
+DSI_TE_SEL_PIN = 0x00000001,
+} DSI_TE_SRC_SEL;
+
+/*
+ * DSI_EXT_TE_MUX enum
+ */
+
+typedef enum DSI_EXT_TE_MUX {
+DSI_XT_TE_MUX_LCDD17 = 0x00000000,
+DSI_XT_TE_MUX_DCLK = 0x00000001,
+DSI_XT_TE_MUX_SS = 0x00000002,
+DSI_XT_TE_MUX_GCLK = 0x00000003,
+DSI_XT_TE_MUX_GOE = 0x00000004,
+DSI_XT_TE_MUX_DINV = 0x00000005,
+DSI_XT_TE_MUX_FRAME = 0x00000006,
+DSI_XT_TE_MUX_GPIO4 = 0x00000007,
+DSI_XT_TE_MUX_GPIO5 = 0x00000008,
+} DSI_EXT_TE_MUX;
+
+/*
+ * DSI_EXT_TE_MODE enum
+ */
+
+typedef enum DSI_EXT_TE_MODE {
+DSI_EXT_TE_MODE_VSYNC_EDGE = 0x00000000,
+DSI_EXT_TE_MODE_VSYNC_WIDTH = 0x00000001,
+DSI_EXT_TE_MODE_HVSYNC_EDGE = 0x00000002,
+DSI_EXT_TE_MODE_HVSYNC_WIDTH = 0x00000003,
+} DSI_EXT_TE_MODE;
+
+/*
+ * DSI_EXT_RESET_POL enum
+ */
+
+typedef enum DSI_EXT_RESET_POL {
+DSI_EXT_RESET_POL_HIGH = 0x00000000,
+DSI_EXT_RESET_POL_LOW = 0x00000001,
+} DSI_EXT_RESET_POL;
+
+/*
+ * DSI_EXT_TE_POL enum
+ */
+
+typedef enum DSI_EXT_TE_POL {
+DSI_EXT_TE_POL_RISING = 0x00000000,
+DSI_EXT_TE_POL_FALLING = 0x00000001,
+} DSI_EXT_TE_POL;
+
+/*
+ * DSI_RESET_PANEL enum
+ */
+
+typedef enum DSI_RESET_PANEL {
+DSI_RESET_PANEL_DEASSERT = 0x00000000,
+DSI_RESET_PANEL_ASSERT = 0x00000001,
+} DSI_RESET_PANEL;
+
+/*
+ * DSI_CRC_ENABLE enum
+ */
+
+typedef enum DSI_CRC_ENABLE {
+DSI_CRC_CAL_DISABLE = 0x00000000,
+DSI_CRC_CAL_ENABLE = 0x00000001,
+} DSI_CRC_ENABLE;
+
+/*
+ * DSI_TX_EOT_APPEND enum
+ */
+
+typedef enum DSI_TX_EOT_APPEND {
+DSI_TX_EOT_APPEND_DISABLE = 0x00000000,
+DSI_TX_EOT_APPEND_ENABLE = 0x00000001,
+} DSI_TX_EOT_APPEND;
+
+/*
+ * DSI_RX_EOT_IGNORE enum
+ */
+
+typedef enum DSI_RX_EOT_IGNORE {
+DSI_RX_EOT_IGNORE_DISABLE = 0x00000000,
+DSI_RX_EOT_IGNORE_ENABLE = 0x00000001,
+} DSI_RX_EOT_IGNORE;
+
+/*
+ * DSI_MIPI_BIST_RESET enum
+ */
+
+typedef enum DSI_MIPI_BIST_RESET {
+DSI_MIPI_BIST_RESET_DEASSERT = 0x00000000,
+DSI_MIPI_BIST_RESET_ASSERT = 0x00000001,
+} DSI_MIPI_BIST_RESET;
+
+/*
+ * DSI_MIPI_BIST_VIDEO_FRMT enum
+ */
+
+typedef enum DSI_MIPI_BIST_VIDEO_FRMT {
+DSI_MIPI_BIST_VIDEO_FRMT_YUV422 = 0x00000000,
+DSI_MIPI_BIST_VIDEO_FRMT_RAW8 = 0x00000001,
+} DSI_MIPI_BIST_VIDEO_FRMT;
+
+/*
+ * DSI_MIPI_BIST_START enum
+ */
+
+typedef enum DSI_MIPI_BIST_START {
+DSI_MIPI_BIST_START_DEASSERT = 0x00000000,
+DSI_MIPI_BIST_START_ASSERT = 0x00000001,
+} DSI_MIPI_BIST_START;
+
+/*
+ * DSI_DBG_CLK_SEL enum
+ */
+
+typedef enum DSI_DBG_CLK_SEL {
+DSI_TEST_CLK_SEL_DISPCLK_P = 0x00000000,
+DSI_TEST_CLK_SEL_DISPCLK_G = 0x00000001,
+DSI_TEST_CLK_SEL_DISPCLK_R = 0x00000002,
+DSI_TEST_CLK_SEL_ESCCLK_G = 0x00000003,
+DSI_TEST_CLK_SEL_BYTECLK_G = 0x00000004,
+DSI_TEST_CLK_SEL_DSICLK_P = 0x00000005,
+DSI_TEST_CLK_SEL_DSICLK_R = 0x00000006,
+DSI_TEST_CLK_SEL_DSICLK_G = 0x00000007,
+DSI_TEST_CLK_SEL_DSICLK_TRN = 0x00000008,
+} DSI_DBG_CLK_SEL;
+
+/*
+ * DSI_DENG_FIFO_USE_OVERWRITE_LEVEL enum
+ */
+
+typedef enum DSI_DENG_FIFO_USE_OVERWRITE_LEVEL {
+DSI_DENG_FIFO_LEVEL_OVERWRITE = 0x00000000,
+DSI_DENG_FIFO_LEVEL_CAL_AVERAGE = 0x00000001,
+} DSI_DENG_FIFO_USE_OVERWRITE_LEVEL;
+
+/*
+ * DSI_DENG_FIFO_FORCE_RECAL_AVERAGE enum
+ */
+
+typedef enum DSI_DENG_FIFO_FORCE_RECAL_AVERAGE {
+DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_DEASSERT = 0x00000000,
+DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_ASSERT = 0x00000001,
+} DSI_DENG_FIFO_FORCE_RECAL_AVERAGE;
+
+/*
+ * DSI_DENG_FIFO_FORCE_RECOMP_MINMAX enum
+ */
+
+typedef enum DSI_DENG_FIFO_FORCE_RECOMP_MINMAX {
+DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_DEASSERT = 0x00000000,
+DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_ASSERT = 0x00000001,
+} DSI_DENG_FIFO_FORCE_RECOMP_MINMAX;
+
+/*
+ * DSI_DENG_FIFO_START enum
+ */
+
+typedef enum DSI_DENG_FIFO_START {
+DSI_DENG_FIFO_START_DEASSERT = 0x00000000,
+DSI_DENG_FIFO_START_ASSERT = 0x00000001,
+} DSI_DENG_FIFO_START;
+
+/*
+ * DSI_USE_CMDFIFO enum
+ */
+
+typedef enum DSI_USE_CMDFIFO {
+DSI_CMD_USE_DMAFIFO = 0x00000000,
+DSI_CMD_USE_CMDFIFO = 0x00000001,
+} DSI_USE_CMDFIFO;
+
+/*
+ * DSI_CRTC_FREEZE_TRIG enum
+ */
+
+typedef enum DSI_CRTC_FREEZE_TRIG {
+DSI_CRTC_FREEZE_TRIG_DEASSERT = 0x00000000,
+DSI_CRTC_FREEZE_TRIG_ASSERT = 0x00000001,
+} DSI_CRTC_FREEZE_TRIG;
+
+/*
+ * DSI_PERF_LATENCY_SEL enum
+ */
+
+typedef enum DSI_PERF_LATENCY_SEL {
+DSI_PERF_LATENCY_SEL_DATA_LANE0 = 0x00000000,
+DSI_PERF_LATENCY_SEL_DATA_LANE1 = 0x00000001,
+DSI_PERF_LATENCY_SEL_DATA_LANE2 = 0x00000002,
+DSI_PERF_LATENCY_SEL_DATA_LANE3 = 0x00000003,
+} DSI_PERF_LATENCY_SEL;
+
+/*
+ * DSI_DEBUG_DSICLK_SEL enum
+ */
+
+typedef enum DSI_DEBUG_DSICLK_SEL {
+DSI_DEBUG_DSICLK_SEL_VIDEO_ENGINE = 0x00000000,
+DSI_DEBUG_DSICLK_SEL_CMD_ENGINE = 0x00000001,
+DSI_DEBUG_DSICLK_SEL_RESYNC_FIFO = 0x00000002,
+DSI_DEBUG_DSICLK_SEL_CMDFIFO = 0x00000003,
+DSI_DEBUG_DSICLK_SEL_CMDBUFFER = 0x00000004,
+DSI_DEBUG_DSICLK_SEL_AFIFO = 0x00000005,
+DSI_DEBUG_DSICLK_SEL_LANECTRL = 0x00000006,
+} DSI_DEBUG_DSICLK_SEL;
+
+/*
+ * DSI_DEBUG_BYTECLK_SEL enum
+ */
+
+typedef enum DSI_DEBUG_BYTECLK_SEL {
+DSI_DEBUG_BYTECLK_SEL_AFIFO = 0x00000000,
+DSI_DEBUG_BYTECLK_SEL_LANEFIFO0 = 0x00000001,
+DSI_DEBUG_BYTECLK_SEL_LANEFIFO1 = 0x00000002,
+DSI_DEBUG_BYTECLK_SEL_LANEFIFO2 = 0x00000003,
+DSI_DEBUG_BYTECLK_SEL_LANEFIFO3 = 0x00000004,
+DSI_DEBUG_BYTECLK_SEL_LANEBUF0 = 0x00000005,
+DSI_DEBUG_BYTECLK_SEL_LANEBUF1 = 0x00000006,
+DSI_DEBUG_BYTECLK_SEL_LANEBUF2 = 0x00000007,
+DSI_DEBUG_BYTECLK_SEL_LANEBUF3 = 0x00000008,
+DSI_DEBUG_BYTECLK_SEL_PINGPONG0 = 0x00000009,
+DSI_DEBUG_BYTECLK_SEL_PINGPONG1 = 0x0000000a,
+DSI_DEBUG_BYTECLK_SEL_PINGPING2 = 0x0000000b,
+DSI_DEBUG_BYTECLK_SEL_PINGPING3 = 0x0000000c,
+DSI_DEBUG_BYTECLK_SEL_EOT = 0x0000000d,
+DSI_DEBUG_BYTECLK_SEL_LANECTRL = 0x0000000e,
+} DSI_DEBUG_BYTECLK_SEL;
+
+/*******************************************************
+ * DCIO_CHIP Enums
+ *******************************************************/
+
+/*
+ * DCIOCHIP_HPD_SEL enum
+ */
+
+typedef enum DCIOCHIP_HPD_SEL {
+DCIOCHIP_HPD_SEL_ASYNC = 0x00000000,
+DCIOCHIP_HPD_SEL_CLOCKED = 0x00000001,
+} DCIOCHIP_HPD_SEL;
+
+/*
+ * DCIOCHIP_PAD_MODE enum
+ */
+
+typedef enum DCIOCHIP_PAD_MODE {
+DCIOCHIP_PAD_MODE_DDC = 0x00000000,
+DCIOCHIP_PAD_MODE_DP = 0x00000001,
+} DCIOCHIP_PAD_MODE;
+
+/*
+ * DCIOCHIP_AUXSLAVE_PAD_MODE enum
+ */
+
+typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
+DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0x00000000,
+DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 0x00000001,
+} DCIOCHIP_AUXSLAVE_PAD_MODE;
+
+/*
+ * DCIOCHIP_INVERT enum
+ */
+
+typedef enum DCIOCHIP_INVERT {
+DCIOCHIP_POL_NON_INVERT = 0x00000000,
+DCIOCHIP_POL_INVERT = 0x00000001,
+} DCIOCHIP_INVERT;
+
+/*
+ * DCIOCHIP_PD_EN enum
+ */
+
+typedef enum DCIOCHIP_PD_EN {
+DCIOCHIP_PD_EN_NOTALLOW = 0x00000000,
+DCIOCHIP_PD_EN_ALLOW = 0x00000001,
+} DCIOCHIP_PD_EN;
+
+/*
+ * DCIOCHIP_GPIO_MASK_EN enum
+ */
+
+typedef enum DCIOCHIP_GPIO_MASK_EN {
+DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x00000000,
+DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x00000001,
+} DCIOCHIP_GPIO_MASK_EN;
+
+/*
+ * DCIOCHIP_MASK enum
+ */
+
+typedef enum DCIOCHIP_MASK {
+DCIOCHIP_MASK_DISABLE = 0x00000000,
+DCIOCHIP_MASK_ENABLE = 0x00000001,
+} DCIOCHIP_MASK;
+
+/*
+ * DCIOCHIP_GPIO_I2C_MASK enum
+ */
+
+typedef enum DCIOCHIP_GPIO_I2C_MASK {
+DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0x00000000,
+DCIOCHIP_GPIO_I2C_MASK_ENABLE = 0x00000001,
+} DCIOCHIP_GPIO_I2C_MASK;
+
+/*
+ * DCIOCHIP_GPIO_I2C_DRIVE enum
+ */
+
+typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
+DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0x00000000,
+DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 0x00000001,
+} DCIOCHIP_GPIO_I2C_DRIVE;
+
+/*
+ * DCIOCHIP_GPIO_I2C_EN enum
+ */
+
+typedef enum DCIOCHIP_GPIO_I2C_EN {
+DCIOCHIP_GPIO_I2C_DISABLE = 0x00000000,
+DCIOCHIP_GPIO_I2C_ENABLE = 0x00000001,
+} DCIOCHIP_GPIO_I2C_EN;
+
+/*
+ * DCIOCHIP_MASK_4BIT enum
+ */
+
+typedef enum DCIOCHIP_MASK_4BIT {
+DCIOCHIP_MASK_4BIT_DISABLE = 0x00000000,
+DCIOCHIP_MASK_4BIT_ENABLE = 0x0000000f,
+} DCIOCHIP_MASK_4BIT;
+
+/*
+ * DCIOCHIP_ENABLE_4BIT enum
+ */
+
+typedef enum DCIOCHIP_ENABLE_4BIT {
+DCIOCHIP_4BIT_DISABLE = 0x00000000,
+DCIOCHIP_4BIT_ENABLE = 0x0000000f,
+} DCIOCHIP_ENABLE_4BIT;
+
+/*
+ * DCIOCHIP_MASK_5BIT enum
+ */
+
+typedef enum DCIOCHIP_MASK_5BIT {
+DCIOCHIP_MASIK_5BIT_DISABLE = 0x00000000,
+DCIOCHIP_MASIK_5BIT_ENABLE = 0x0000001f,
+} DCIOCHIP_MASK_5BIT;
+
+/*
+ * DCIOCHIP_ENABLE_5BIT enum
+ */
+
+typedef enum DCIOCHIP_ENABLE_5BIT {
+DCIOCHIP_5BIT_DISABLE = 0x00000000,
+DCIOCHIP_5BIT_ENABLE = 0x0000001f,
+} DCIOCHIP_ENABLE_5BIT;
+
+/*
+ * DCIOCHIP_MASK_2BIT enum
+ */
+
+typedef enum DCIOCHIP_MASK_2BIT {
+DCIOCHIP_MASK_2BIT_DISABLE = 0x00000000,
+DCIOCHIP_MASK_2BIT_ENABLE = 0x00000003,
+} DCIOCHIP_MASK_2BIT;
+
+/*
+ * DCIOCHIP_ENABLE_2BIT enum
+ */
+
+typedef enum DCIOCHIP_ENABLE_2BIT {
+DCIOCHIP_2BIT_DISABLE = 0x00000000,
+DCIOCHIP_2BIT_ENABLE = 0x00000003,
+} DCIOCHIP_ENABLE_2BIT;
+
+/*
+ * DCIOCHIP_REF_27_SRC_SEL enum
+ */
+
+typedef enum DCIOCHIP_REF_27_SRC_SEL {
+DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x00000000,
+DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x00000001,
+DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x00000002,
+DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x00000003,
+} DCIOCHIP_REF_27_SRC_SEL;
+
+/*
+ * DCIOCHIP_DVO_VREFPON enum
+ */
+
+typedef enum DCIOCHIP_DVO_VREFPON {
+DCIOCHIP_DVO_VREFPON_DISABLE = 0x00000000,
+DCIOCHIP_DVO_VREFPON_ENABLE = 0x00000001,
+} DCIOCHIP_DVO_VREFPON;
+
+/*
+ * DCIOCHIP_DVO_VREFSEL enum
+ */
+
+typedef enum DCIOCHIP_DVO_VREFSEL {
+DCIOCHIP_DVO_VREFSEL_ONCHIP = 0x00000000,
+DCIOCHIP_DVO_VREFSEL_EXTERNAL = 0x00000001,
+} DCIOCHIP_DVO_VREFSEL;
+
+/*
+ * DCIOCHIP_SPDIF1_IMODE enum
+ */
+
+typedef enum DCIOCHIP_SPDIF1_IMODE {
+DCIOCHIP_SPDIF1_IMODE_OE_A = 0x00000000,
+DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO = 0x00000001,
+} DCIOCHIP_SPDIF1_IMODE;
+
+/*
+ * DCIOCHIP_AUX_FALLSLEWSEL enum
+ */
+
+typedef enum DCIOCHIP_AUX_FALLSLEWSEL {
+DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0x00000000,
+DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 0x00000001,
+DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 0x00000002,
+DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 0x00000003,
+} DCIOCHIP_AUX_FALLSLEWSEL;
+
+/*
+ * DCIOCHIP_AUX_SPIKESEL enum
+ */
+
+typedef enum DCIOCHIP_AUX_SPIKESEL {
+DCIOCHIP_AUX_SPIKESEL_50NS = 0x00000000,
+DCIOCHIP_AUX_SPIKESEL_10NS = 0x00000001,
+} DCIOCHIP_AUX_SPIKESEL;
+
+/*
+ * DCIOCHIP_AUX_CSEL0P9 enum
+ */
+
+typedef enum DCIOCHIP_AUX_CSEL0P9 {
+DCIOCHIP_AUX_CSEL_DEC1P0 = 0x00000000,
+DCIOCHIP_AUX_CSEL_DEC0P9 = 0x00000001,
+} DCIOCHIP_AUX_CSEL0P9;
+
+/*
+ * DCIOCHIP_AUX_CSEL1P1 enum
+ */
+
+typedef enum DCIOCHIP_AUX_CSEL1P1 {
+DCIOCHIP_AUX_CSEL_INC1P0 = 0x00000000,
+DCIOCHIP_AUX_CSEL_INC1P1 = 0x00000001,
+} DCIOCHIP_AUX_CSEL1P1;
+
+/*
+ * DCIOCHIP_AUX_RSEL0P9 enum
+ */
+
+typedef enum DCIOCHIP_AUX_RSEL0P9 {
+DCIOCHIP_AUX_RSEL_DEC1P0 = 0x00000000,
+DCIOCHIP_AUX_RSEL_DEC0P9 = 0x00000001,
+} DCIOCHIP_AUX_RSEL0P9;
+
+/*
+ * DCIOCHIP_AUX_RSEL1P1 enum
+ */
+
+typedef enum DCIOCHIP_AUX_RSEL1P1 {
+DCIOCHIP_AUX_RSEL_INC1P0 = 0x00000000,
+DCIOCHIP_AUX_RSEL_INC1P1 = 0x00000001,
+} DCIOCHIP_AUX_RSEL1P1;
+
+/*******************************************************
+ * AZCONTROLLER Enums
+ *******************************************************/
+
+/*
+ * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum
+ */
+
+typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
+GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0x00000000,
+GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 0x00000001,
+} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL;
+
+/*
+ * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum
+ */
+
+typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
+GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0x00000000,
+GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 0x00000001,
+} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED;
+
+/*
+ * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum
+ */
+
+typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
+GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0x00000000,
+GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 0x00000001,
+} GENERIC_AZ_CONTROLLER_REGISTER_STATUS;
+
+/*
+ * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum
+ */
+
+typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
+GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0x00000000,
+GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 0x00000001,
+} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED;
+
+/*
+ * AZ_GLOBAL_CAPABILITIES enum
+ */
+
+typedef enum AZ_GLOBAL_CAPABILITIES {
+AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0x00000000,
+AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 0x00000001,
+} AZ_GLOBAL_CAPABILITIES;
+
+/*
+ * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum
+ */
+
+typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
+ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0x00000000,
+ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 0x00000001,
+} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE;
+
+/*
+ * GLOBAL_CONTROL_FLUSH_CONTROL enum
+ */
+
+typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
+FLUSH_CONTROL_FLUSH_NOT_STARTED = 0x00000000,
+FLUSH_CONTROL_FLUSH_STARTED = 0x00000001,
+} GLOBAL_CONTROL_FLUSH_CONTROL;
+
+/*
+ * GLOBAL_CONTROL_CONTROLLER_RESET enum
+ */
+
+typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
+CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0x00000000,
+CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 0x00000001,
+} GLOBAL_CONTROL_CONTROLLER_RESET;
+
+/*
+ * AZ_STATE_CHANGE_STATUS enum
+ */
+
+typedef enum AZ_STATE_CHANGE_STATUS {
+AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0x00000000,
+AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 0x00000001,
+} AZ_STATE_CHANGE_STATUS;
+
+/*
+ * GLOBAL_STATUS_FLUSH_STATUS enum
+ */
+
+typedef enum GLOBAL_STATUS_FLUSH_STATUS {
+GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0x00000000,
+GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 0x00000001,
+} GLOBAL_STATUS_FLUSH_STATUS;
+
+/*
+ * STREAM_0_SYNCHRONIZATION enum
+ */
+
+typedef enum STREAM_0_SYNCHRONIZATION {
+STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
+STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
+} STREAM_0_SYNCHRONIZATION;
+
+/*
+ * STREAM_1_SYNCHRONIZATION enum
+ */
+
+typedef enum STREAM_1_SYNCHRONIZATION {
+STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
+STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
+} STREAM_1_SYNCHRONIZATION;
+
+/*
+ * STREAM_2_SYNCHRONIZATION enum
+ */
+
+typedef enum STREAM_2_SYNCHRONIZATION {
+STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
+STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
+} STREAM_2_SYNCHRONIZATION;
+
+/*
+ * STREAM_3_SYNCHRONIZATION enum
+ */
+
+typedef enum STREAM_3_SYNCHRONIZATION {
+STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
+STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
+} STREAM_3_SYNCHRONIZATION;
+
+/*
+ * STREAM_4_SYNCHRONIZATION enum
+ */
+
+typedef enum STREAM_4_SYNCHRONIZATION {
+STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
+STREAM_4_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
+} STREAM_4_SYNCHRONIZATION;
+
+/*
+ * STREAM_5_SYNCHRONIZATION enum
+ */
+
+typedef enum STREAM_5_SYNCHRONIZATION {
+STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
+STREAM_5_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
+} STREAM_5_SYNCHRONIZATION;
+
+/*
+ * STREAM_6_SYNCHRONIZATION enum
+ */
+
+typedef enum STREAM_6_SYNCHRONIZATION {
+STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
+STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
+} STREAM_6_SYNCHRONIZATION;
+
+/*
+ * STREAM_7_SYNCHRONIZATION enum
+ */
+
+typedef enum STREAM_7_SYNCHRONIZATION {
+STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
+STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
+} STREAM_7_SYNCHRONIZATION;
+
+/*
+ * STREAM_8_SYNCHRONIZATION enum
+ */
+
+typedef enum STREAM_8_SYNCHRONIZATION {
+STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
+STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
+} STREAM_8_SYNCHRONIZATION;
+
+/*
+ * STREAM_9_SYNCHRONIZATION enum
+ */
+
+typedef enum STREAM_9_SYNCHRONIZATION {
+STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
+STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
+} STREAM_9_SYNCHRONIZATION;
+
+/*
+ * STREAM_10_SYNCHRONIZATION enum
+ */
+
+typedef enum STREAM_10_SYNCHRONIZATION {
+STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
+STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
+} STREAM_10_SYNCHRONIZATION;
+
+/*
+ * STREAM_11_SYNCHRONIZATION enum
+ */
+
+typedef enum STREAM_11_SYNCHRONIZATION {
+STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
+STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
+} STREAM_11_SYNCHRONIZATION;
+
+/*
+ * STREAM_12_SYNCHRONIZATION enum
+ */
+
+typedef enum STREAM_12_SYNCHRONIZATION {
+STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
+STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
+} STREAM_12_SYNCHRONIZATION;
+
+/*
+ * STREAM_13_SYNCHRONIZATION enum
+ */
+
+typedef enum STREAM_13_SYNCHRONIZATION {
+STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
+STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
+} STREAM_13_SYNCHRONIZATION;
+
+/*
+ * STREAM_14_SYNCHRONIZATION enum
+ */
+
+typedef enum STREAM_14_SYNCHRONIZATION {
+STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
+STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
+} STREAM_14_SYNCHRONIZATION;
+
+/*
+ * STREAM_15_SYNCHRONIZATION enum
+ */
+
+typedef enum STREAM_15_SYNCHRONIZATION {
+STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
+STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
+} STREAM_15_SYNCHRONIZATION;
+
+/*
+ * CORB_READ_POINTER_RESET enum
+ */
+
+typedef enum CORB_READ_POINTER_RESET {
+CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0x00000000,
+CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 0x00000001,
+} CORB_READ_POINTER_RESET;
+
+/*
+ * AZ_CORB_SIZE enum
+ */
+
+typedef enum AZ_CORB_SIZE {
+AZ_CORB_SIZE_2ENTRIES_RESERVED = 0x00000000,
+AZ_CORB_SIZE_16ENTRIES_RESERVED = 0x00000001,
+AZ_CORB_SIZE_256ENTRIES = 0x00000002,
+AZ_CORB_SIZE_RESERVED = 0x00000003,
+} AZ_CORB_SIZE;
+
+/*
+ * AZ_RIRB_WRITE_POINTER_RESET enum
+ */
+
+typedef enum AZ_RIRB_WRITE_POINTER_RESET {
+AZ_RIRB_WRITE_POINTER_NOT_RESET = 0x00000000,
+AZ_RIRB_WRITE_POINTER_DO_RESET = 0x00000001,
+} AZ_RIRB_WRITE_POINTER_RESET;
+
+/*
+ * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum
+ */
+
+typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
+RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000,
+RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001,
+} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL;
+
+/*
+ * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum
+ */
+
+typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
+RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000,
+RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001,
+} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL;
+
+/*
+ * AZ_RIRB_SIZE enum
+ */
+
+typedef enum AZ_RIRB_SIZE {
+AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0x00000000,
+AZ_RIRB_SIZE_16ENTRIES_RESERVED = 0x00000001,
+AZ_RIRB_SIZE_256ENTRIES = 0x00000002,
+AZ_RIRB_SIZE_UNDEFINED = 0x00000003,
+} AZ_RIRB_SIZE;
+
+/*
+ * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum
+ */
+
+typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
+IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0x00000000,
+IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 0x00000001,
+} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID;
+
+/*
+ * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum
+ */
+
+typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
+IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0x00000000,
+IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 0x00000001,
+} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY;
+
+/*
+ * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum
+ */
+
+typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
+DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0x00000000,
+DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 0x00000001,
+} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE;
+
+/*******************************************************
+ * AZENDPOINT Enums
+ *******************************************************/
+
+/*
+ * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
+
+/*
+ * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
+
+/*
+ * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
+
+/*
+ * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
+ */
+
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
+
+/*
+ * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
+
+/*
+ * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
+ */
+
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
+
+/*
+ * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum
+ */
+
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
+AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0x00000000,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 0x00000001,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L;
+
+/*
+ * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum
+ */
+
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
+AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0x00000000,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 0x00000001,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO;
+
+/*
+ * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum
+ */
+
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
+AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0x00000000,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 0x00000001,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO;
+
+/*
+ * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum
+ */
+
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
+AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0x00000000,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 0x00000001,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY;
+
+/*
+ * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
+AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0x00000000,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 0x00000001,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE;
+
+/*
+ * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum
+ */
+
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
+AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0x00000000,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 0x00000001,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG;
+
+/*
+ * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum
+ */
+
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
+AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0x00000000,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 0x00000001,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V;
+
+/*
+ * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
+ */
+
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
+AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
+
+/*
+ * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
+AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0x00000000,
+AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 0x00000001,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE;
+
+/*
+ * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
+AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0x00000000,
+AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 0x00000001,
+} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE;
+
+/*
+ * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
+AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000,
+AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001,
+} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
+
+/*
+ * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum
+ */
+
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
+AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0x00000000,
+AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 0x00000001,
+} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT;
+
+/*
+ * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
+AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0x00000000,
+AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 0x00000001,
+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE;
+
+/*
+ * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
+AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0x00000000,
+AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 0x00000001,
+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE;
+
+/*
+ * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
+AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0x00000000,
+AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 0x00000001,
+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE;
+
+/*
+ * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
+AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0x00000000,
+AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 0x00000001,
+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE;
+
+/*
+ * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
+AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000,
+AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001,
+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
+
+/*
+ * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
+AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000,
+AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001,
+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
+
+/*
+ * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
+AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000,
+AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001,
+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
+
+/*
+ * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
+AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000,
+AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001,
+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
+
+/*
+ * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
+AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000,
+AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001,
+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
+
+/*******************************************************
+ * AZF0CONTROLLER Enums
+ *******************************************************/
+
+/*
+ * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum
+ */
+
+typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET {
+AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0x00000000,
+AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 0x00000001,
+} AZALIA_SOFT_RESET_REFCLK_SOFT_RESET;
+
+/*******************************************************
+ * AZF0ROOT Enums
+ *******************************************************/
+
+/*
+ * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum
+ */
+
+typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
+CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0x00000000,
+CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 0x00000001,
+CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 0x00000002,
+CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 0x00000003,
+CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 0x00000004,
+CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 0x00000005,
+CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 0x00000006,
+CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 0x00000007,
+} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY;
+
+/*
+ * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum
+ */
+
+typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
+CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0x00000000,
+CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 0x00000001,
+CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 0x00000002,
+CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 0x00000003,
+CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 0x00000004,
+CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 0x00000005,
+CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 0x00000006,
+CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 0x00000007,
+} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY;
+
+/*******************************************************
+ * AZINPUTENDPOINT Enums
+ *******************************************************/
+
+/*
+ * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001,
+} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
+
+/*
+ * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
+} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
+
+/*
+ * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
+} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
+
+/*
+ * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
+ */
+
+typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
+} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
+
+/*
+ * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
+} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
+
+/*
+ * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
+ */
+
+typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008,
+} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
+
+/*
+ * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
+ */
+
+typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000,
+AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001,
+} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
+
+/*
+ * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
+AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0x00000000,
+AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 0x00000001,
+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE;
+
+/*
+ * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
+AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000,
+AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001,
+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
+
+/*
+ * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
+AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0x00000000,
+AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 0x00000001,
+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE;
+
+/*
+ * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
+AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000,
+AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001,
+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
+
+/*
+ * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
+AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0x00000000,
+AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 0x00000001,
+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE;
+
+/*
+ * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
+AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000,
+AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001,
+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
+
+/*
+ * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
+AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0x00000000,
+AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 0x00000001,
+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE;
+
+/*
+ * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
+AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000,
+AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001,
+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
+
+/*
+ * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
+AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0x00000000,
+AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 0x00000001,
+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE;
+
+/*
+ * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
+ */
+
+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
+AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000,
+AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001,
+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
+
+/*******************************************************
+ * AZROOT Enums
+ *******************************************************/
+
+/*
+ * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum
+ */
+
+typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
+AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0x00000000,
+AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 0x00000001,
+} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET;
+
+/*******************************************************
+ * DCCG Enums
+ *******************************************************/
+
+/*
+ * ENABLE enum
+ */
+
+typedef enum ENABLE {
+DISABLE_THE_FEATURE = 0x00000000,
+ENABLE_THE_FEATURE = 0x00000001,
+} ENABLE;
+
+/*
+ * ENABLE_CLOCK enum
+ */
+
+typedef enum ENABLE_CLOCK {
+DISABLE_THE_CLOCK = 0x00000000,
+ENABLE_THE_CLOCK = 0x00000001,
+} ENABLE_CLOCK;
+
+/*
+ * FORCE_VBI enum
+ */
+
+typedef enum FORCE_VBI {
+FORCE_VBI_LOW = 0x00000000,
+FORCE_VBI_HIGH = 0x00000001,
+} FORCE_VBI;
+
+/*
+ * OVERRIDE_CGTT_SCLK enum
+ */
+
+typedef enum OVERRIDE_CGTT_SCLK {
+OVERRIDE_CGTT_SCLK_NOOP = 0x00000000,
+SET_OVERRIDE_CGTT_SCLK = 0x00000001,
+} OVERRIDE_CGTT_SCLK;
+
+/*
+ * CLEAR_SMU_INTR enum
+ */
+
+typedef enum CLEAR_SMU_INTR {
+SMU_INTR_STATUS_NOOP = 0x00000000,
+SMU_INTR_STATUS_CLEAR = 0x00000001,
+} CLEAR_SMU_INTR;
+
+/*
+ * STATIC_SCREEN_SMU_INTR enum
+ */
+
+typedef enum STATIC_SCREEN_SMU_INTR {
+STATIC_SCREEN_SMU_INTR_NOOP = 0x00000000,
+SET_STATIC_SCREEN_SMU_INTR = 0x00000001,
+} STATIC_SCREEN_SMU_INTR;
+
+/*
+ * JITTER_REMOVE_DISABLE enum
+ */
+
+typedef enum JITTER_REMOVE_DISABLE {
+ENABLE_JITTER_REMOVAL = 0x00000000,
+DISABLE_JITTER_REMOVAL = 0x00000001,
+} JITTER_REMOVE_DISABLE;
+
+/*
+ * DS_REF_SRC enum
+ */
+
+typedef enum DS_REF_SRC {
+DS_REF_IS_XTALIN = 0x00000000,
+DS_REF_IS_EXT_GENLOCK = 0x00000001,
+DS_REF_IS_PCIE = 0x00000002,
+} DS_REF_SRC;
+
+/*
+ * DISABLE_CLOCK_GATING enum
+ */
+
+typedef enum DISABLE_CLOCK_GATING {
+CLOCK_GATING_ENABLED = 0x00000000,
+CLOCK_GATING_DISABLED = 0x00000001,
+} DISABLE_CLOCK_GATING;
+
+/*
+ * DISABLE_CLOCK_GATING_IN_DCO enum
+ */
+
+typedef enum DISABLE_CLOCK_GATING_IN_DCO {
+CLOCK_GATING_ENABLED_IN_DCO = 0x00000000,
+CLOCK_GATING_DISABLED_IN_DCO = 0x00000001,
+} DISABLE_CLOCK_GATING_IN_DCO;
+
+/*
+ * DCCG_DEEP_COLOR_CNTL enum
+ */
+
+typedef enum DCCG_DEEP_COLOR_CNTL {
+DCCG_DEEP_COLOR_DTO_DISABLE = 0x00000000,
+DCCG_DEEP_COLOR_DTO_5_4_RATIO = 0x00000001,
+DCCG_DEEP_COLOR_DTO_3_2_RATIO = 0x00000002,
+DCCG_DEEP_COLOR_DTO_2_1_RATIO = 0x00000003,
+} DCCG_DEEP_COLOR_CNTL;
+
+/*
+ * REFCLK_CLOCK_EN enum
+ */
+
+typedef enum REFCLK_CLOCK_EN {
+REFCLK_CLOCK_EN_XTALIN_CLK = 0x00000000,
+REFCLK_CLOCK_EN_ALLOW_SRC_SEL = 0x00000001,
+} REFCLK_CLOCK_EN;
+
+/*
+ * REFCLK_SRC_SEL enum
+ */
+
+typedef enum REFCLK_SRC_SEL {
+REFCLK_SRC_SEL_PCIE_REFCLK = 0x00000000,
+REFCLK_SRC_SEL_CPL_REFCLK = 0x00000001,
+} REFCLK_SRC_SEL;
+
+/*
+ * DPREFCLK_SRC_SEL enum
+ */
+
+typedef enum DPREFCLK_SRC_SEL {
+DPREFCLK_SRC_SEL_CK = 0x00000000,
+DPREFCLK_SRC_SEL_P0PLL = 0x00000001,
+DPREFCLK_SRC_SEL_P1PLL = 0x00000002,
+DPREFCLK_SRC_SEL_P2PLL = 0x00000003,
+DPREFCLK_SRC_SEL_P3PLL = 0x00000004,
+} DPREFCLK_SRC_SEL;
+
+/*
+ * XTAL_REF_SEL enum
+ */
+
+typedef enum XTAL_REF_SEL {
+XTAL_REF_SEL_1X = 0x00000000,
+XTAL_REF_SEL_2X = 0x00000001,
+} XTAL_REF_SEL;
+
+/*
+ * XTAL_REF_CLOCK_SOURCE_SEL enum
+ */
+
+typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
+XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0x00000000,
+XTAL_REF_CLOCK_SOURCE_SEL_PPLL = 0x00000001,
+} XTAL_REF_CLOCK_SOURCE_SEL;
+
+/*
+ * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
+ */
+
+typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
+MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000,
+MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 0x00000001,
+} MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL;
+
+/*
+ * ALLOW_SR_ON_TRANS_REQ enum
+ */
+
+typedef enum ALLOW_SR_ON_TRANS_REQ {
+ALLOW_SR_ON_TRANS_REQ_ENABLE = 0x00000000,
+ALLOW_SR_ON_TRANS_REQ_DISABLE = 0x00000001,
+} ALLOW_SR_ON_TRANS_REQ;
+
+/*
+ * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
+ */
+
+typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
+MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000,
+MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 0x00000001,
+} MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL;
+
+/*
+ * PIPE_PIXEL_RATE_SOURCE enum
+ */
+
+typedef enum PIPE_PIXEL_RATE_SOURCE {
+PIPE_PIXEL_RATE_SOURCE_P0PLL = 0x00000000,
+PIPE_PIXEL_RATE_SOURCE_P1PLL = 0x00000001,
+PIPE_PIXEL_RATE_SOURCE_P2PLL = 0x00000002,
+} PIPE_PIXEL_RATE_SOURCE;
+
+/*
+ * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum
+ */
+
+typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
+PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0x00000000,
+PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 0x00000001,
+PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 0x00000002,
+PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 0x00000003,
+PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE = 0x00000004,
+PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF = 0x00000005,
+PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG = 0x00000006,
+} PIPE_PHYPLL_PIXEL_RATE_SOURCE;
+
+/*
+ * PIPE_PIXEL_RATE_PLL_SOURCE enum
+ */
+
+typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
+PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0x00000000,
+PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 0x00000001,
+} PIPE_PIXEL_RATE_PLL_SOURCE;
+
+/*
+ * DP_DTO_DS_DISABLE enum
+ */
+
+typedef enum DP_DTO_DS_DISABLE {
+DP_DTO_DESPREAD_DISABLE = 0x00000000,
+DP_DTO_DESPREAD_ENABLE = 0x00000001,
+} DP_DTO_DS_DISABLE;
+
+/*
+ * CRTC_ADD_PIXEL enum
+ */
+
+typedef enum CRTC_ADD_PIXEL {
+CRTC_ADD_PIXEL_NOOP = 0x00000000,
+CRTC_ADD_PIXEL_FORCE = 0x00000001,
+} CRTC_ADD_PIXEL;
+
+/*
+ * CRTC_DROP_PIXEL enum
+ */
+
+typedef enum CRTC_DROP_PIXEL {
+CRTC_DROP_PIXEL_NOOP = 0x00000000,
+CRTC_DROP_PIXEL_FORCE = 0x00000001,
+} CRTC_DROP_PIXEL;
+
+/*
+ * SYMCLK_FE_FORCE_EN enum
+ */
+
+typedef enum SYMCLK_FE_FORCE_EN {
+SYMCLK_FE_FORCE_EN_DISABLE = 0x00000000,
+SYMCLK_FE_FORCE_EN_ENABLE = 0x00000001,
+} SYMCLK_FE_FORCE_EN;
+
+/*
+ * SYMCLK_FE_FORCE_SRC enum
+ */
+
+typedef enum SYMCLK_FE_FORCE_SRC {
+SYMCLK_FE_FORCE_SRC_UNIPHYA = 0x00000000,
+SYMCLK_FE_FORCE_SRC_UNIPHYB = 0x00000001,
+SYMCLK_FE_FORCE_SRC_UNIPHYC = 0x00000002,
+SYMCLK_FE_FORCE_SRC_UNIPHYD = 0x00000003,
+SYMCLK_FE_FORCE_SRC_UNIPHYE = 0x00000004,
+SYMCLK_FE_FORCE_SRC_UNIPHYF = 0x00000005,
+SYMCLK_FE_FORCE_SRC_UNIPHYG = 0x00000006,
+} SYMCLK_FE_FORCE_SRC;
+
+/*
+ * DPDBG_CLK_FORCE_EN enum
+ */
+
+typedef enum DPDBG_CLK_FORCE_EN {
+DPDBG_CLK_FORCE_EN_DISABLE = 0x00000000,
+DPDBG_CLK_FORCE_EN_ENABLE = 0x00000001,
+} DPDBG_CLK_FORCE_EN;
+
+/*
+ * DVOACLK_COARSE_SKEW_CNTL enum
+ */
+
+typedef enum DVOACLK_COARSE_SKEW_CNTL {
+DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000,
+DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 0x00000001,
+DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002,
+DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003,
+DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 0x00000004,
+DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 0x00000005,
+DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 0x00000006,
+DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 0x00000007,
+DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 0x00000008,
+DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 0x00000009,
+DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 0x0000000a,
+DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 0x0000000b,
+DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 0x0000000c,
+DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 0x0000000d,
+DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 0x0000000e,
+DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 0x0000000f,
+DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 0x00000010,
+DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 0x00000011,
+DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 0x00000012,
+DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 0x00000013,
+DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 0x00000014,
+DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 0x00000015,
+DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 0x00000016,
+DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 0x00000017,
+DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 0x00000018,
+DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 0x00000019,
+DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 0x0000001a,
+DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 0x0000001b,
+DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 0x0000001c,
+DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 0x0000001d,
+DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 0x0000001e,
+} DVOACLK_COARSE_SKEW_CNTL;
+
+/*
+ * DVOACLK_FINE_SKEW_CNTL enum
+ */
+
+typedef enum DVOACLK_FINE_SKEW_CNTL {
+DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000,
+DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 0x00000001,
+DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002,
+DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003,
+DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 0x00000004,
+DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 0x00000005,
+DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 0x00000006,
+DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 0x00000007,
+} DVOACLK_FINE_SKEW_CNTL;
+
+/*
+ * DVOACLKD_IN_PHASE enum
+ */
+
+typedef enum DVOACLKD_IN_PHASE {
+DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
+DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 0x00000001,
+} DVOACLKD_IN_PHASE;
+
+/*
+ * DVOACLKC_IN_PHASE enum
+ */
+
+typedef enum DVOACLKC_IN_PHASE {
+DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
+DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 0x00000001,
+} DVOACLKC_IN_PHASE;
+
+/*
+ * DVOACLKC_MVP_IN_PHASE enum
+ */
+
+typedef enum DVOACLKC_MVP_IN_PHASE {
+DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
+DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 0x00000001,
+} DVOACLKC_MVP_IN_PHASE;
+
+/*
+ * DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum
+ */
+
+typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE {
+DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0x00000000,
+DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 0x00000001,
+} DVOACLKC_MVP_SKEW_PHASE_OVERRIDE;
+
+/*
+ * MVP_CLK_SRC_SEL enum
+ */
+
+typedef enum MVP_CLK_SRC_SEL {
+MVP_CLK_SRC_SEL_RSRV = 0x00000000,
+MVP_CLK_SRC_SEL_IO_1 = 0x00000001,
+MVP_CLK_SRC_SEL_IO_2 = 0x00000002,
+MVP_CLK_SRC_SEL_REFCLK = 0x00000003,
+} MVP_CLK_SRC_SEL;
+
+/*
+ * DCCG_AUDIO_DTO0_SOURCE_SEL enum
+ */
+
+typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
+DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0 = 0x00000000,
+DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1 = 0x00000001,
+DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2 = 0x00000002,
+DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3 = 0x00000003,
+DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4 = 0x00000004,
+DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5 = 0x00000005,
+DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 0x00000006,
+} DCCG_AUDIO_DTO0_SOURCE_SEL;
+
+/*
+ * DCCG_AUDIO_DTO_SEL enum
+ */
+
+typedef enum DCCG_AUDIO_DTO_SEL {
+DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0x00000000,
+DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 0x00000001,
+DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 0x00000002,
+} DCCG_AUDIO_DTO_SEL;
+
+/*
+ * DCCG_AUDIO_DTO2_SOURCE_SEL enum
+ */
+
+typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
+DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0x00000000,
+DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1 = 0x00000001,
+} DCCG_AUDIO_DTO2_SOURCE_SEL;
+
+/*
+ * DCCG_AUDIO_DTO_USE_512FBR_DTO enum
+ */
+
+typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
+DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0x00000000,
+DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 0x00000001,
+} DCCG_AUDIO_DTO_USE_512FBR_DTO;
+
+/*
+ * DCCG_DBG_EN enum
+ */
+
+typedef enum DCCG_DBG_EN {
+DCCG_DBG_EN_DISABLE = 0x00000000,
+DCCG_DBG_EN_ENABLE = 0x00000001,
+} DCCG_DBG_EN;
+
+/*
+ * DCCG_DBG_BLOCK_SEL enum
+ */
+
+typedef enum DCCG_DBG_BLOCK_SEL {
+DCCG_DBG_BLOCK_SEL_DCCG = 0x00000000,
+DCCG_DBG_BLOCK_SEL_PMON = 0x00000001,
+DCCG_DBG_BLOCK_SEL_PMON2 = 0x00000002,
+} DCCG_DBG_BLOCK_SEL;
+
+/*
+ * DISPCLK_FREQ_RAMP_DONE enum
+ */
+
+typedef enum DISPCLK_FREQ_RAMP_DONE {
+DISPCLK_FREQ_RAMP_IN_PROGRESS = 0x00000000,
+DISPCLK_FREQ_RAMP_COMPLETED = 0x00000001,
+} DISPCLK_FREQ_RAMP_DONE;
+
+/*
+ * DCCG_FIFO_ERRDET_RESET enum
+ */
+
+typedef enum DCCG_FIFO_ERRDET_RESET {
+DCCG_FIFO_ERRDET_RESET_NOOP = 0x00000000,
+DCCG_FIFO_ERRDET_RESET_FORCE = 0x00000001,
+} DCCG_FIFO_ERRDET_RESET;
+
+/*
+ * DCCG_FIFO_ERRDET_STATE enum
+ */
+
+typedef enum DCCG_FIFO_ERRDET_STATE {
+DCCG_FIFO_ERRDET_STATE_DETECTION = 0x00000000,
+DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0x00000001,
+} DCCG_FIFO_ERRDET_STATE;
+
+/*
+ * DCCG_FIFO_ERRDET_OVR_EN enum
+ */
+
+typedef enum DCCG_FIFO_ERRDET_OVR_EN {
+DCCG_FIFO_ERRDET_OVR_DISABLE = 0x00000000,
+DCCG_FIFO_ERRDET_OVR_ENABLE = 0x00000001,
+} DCCG_FIFO_ERRDET_OVR_EN;
+
+/*
+ * DISPCLK_CHG_FWD_CORR_DISABLE enum
+ */
+
+typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
+DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0x00000000,
+DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 0x00000001,
+} DISPCLK_CHG_FWD_CORR_DISABLE;
+
+/*
+ * DC_MEM_GLOBAL_PWR_REQ_DIS enum
+ */
+
+typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
+DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0x00000000,
+DC_MEM_GLOBAL_PWR_REQ_DISABLE = 0x00000001,
+} DC_MEM_GLOBAL_PWR_REQ_DIS;
+
+/*
+ * DCCG_PERF_RUN enum
+ */
+
+typedef enum DCCG_PERF_RUN {
+DCCG_PERF_RUN_NOOP = 0x00000000,
+DCCG_PERF_RUN_START = 0x00000001,
+} DCCG_PERF_RUN;
+
+/*
+ * DCCG_PERF_MODE_VSYNC enum
+ */
+
+typedef enum DCCG_PERF_MODE_VSYNC {
+DCCG_PERF_MODE_VSYNC_NOOP = 0x00000000,
+DCCG_PERF_MODE_VSYNC_START = 0x00000001,
+} DCCG_PERF_MODE_VSYNC;
+
+/*
+ * DCCG_PERF_MODE_HSYNC enum
+ */
+
+typedef enum DCCG_PERF_MODE_HSYNC {
+DCCG_PERF_MODE_HSYNC_NOOP = 0x00000000,
+DCCG_PERF_MODE_HSYNC_START = 0x00000001,
+} DCCG_PERF_MODE_HSYNC;
+
+/*
+ * DCCG_PERF_CRTC_SELECT enum
+ */
+
+typedef enum DCCG_PERF_CRTC_SELECT {
+DCCG_PERF_SEL_CRTC0 = 0x00000000,
+DCCG_PERF_SEL_CRTC1 = 0x00000001,
+DCCG_PERF_SEL_CRTC2 = 0x00000002,
+DCCG_PERF_SEL_CRTC3 = 0x00000003,
+DCCG_PERF_SEL_CRTC4 = 0x00000004,
+DCCG_PERF_SEL_CRTC5 = 0x00000005,
+} DCCG_PERF_CRTC_SELECT;
+
+/*
+ * CLOCK_BRANCH_SOFT_RESET enum
+ */
+
+typedef enum CLOCK_BRANCH_SOFT_RESET {
+CLOCK_BRANCH_SOFT_RESET_NOOP = 0x00000000,
+CLOCK_BRANCH_SOFT_RESET_FORCE = 0x00000001,
+} CLOCK_BRANCH_SOFT_RESET;
+
+/*
+ * PLL_CFG_IF_SOFT_RESET enum
+ */
+
+typedef enum PLL_CFG_IF_SOFT_RESET {
+PLL_CFG_IF_SOFT_RESET_NOOP = 0x00000000,
+PLL_CFG_IF_SOFT_RESET_FORCE = 0x00000001,
+} PLL_CFG_IF_SOFT_RESET;
+
+/*
+ * DVO_ENABLE_RST enum
+ */
+
+typedef enum DVO_ENABLE_RST {
+DVO_ENABLE_RST_DISABLE = 0x00000000,
+DVO_ENABLE_RST_ENABLE = 0x00000001,
+} DVO_ENABLE_RST;
+
+/*******************************************************
+ * DCI Enums
+ *******************************************************/
+
+/*
+ * LptNumPipes enum
+ */
+
+typedef enum LptNumPipes {
+LPT_NUM_PIPES_1CH = 0x00000000,
+LPT_NUM_PIPES_2CH = 0x00000001,
+LPT_NUM_PIPES_4CH = 0x00000002,
+LPT_NUM_PIPES_8CH = 0x00000003,
+} LptNumPipes;
+
+/*
+ * LptNumBanks enum
+ */
+
+typedef enum LptNumBanks {
+LPT_NUM_BANKS_2BANK = 0x00000000,
+LPT_NUM_BANKS_4BANK = 0x00000001,
+LPT_NUM_BANKS_8BANK = 0x00000002,
+LPT_NUM_BANKS_16BANK = 0x00000003,
+LPT_NUM_BANKS_32BANK = 0x00000004,
+} LptNumBanks;
+
+/*
+ * OVERRIDE_CGTT_DCEFCLK enum
+ */
+
+typedef enum OVERRIDE_CGTT_DCEFCLK {
+OVERRIDE_CGTT_DCEFCLK_NOOP = 0x00000000,
+SET_OVERRIDE_CGTT_DCEFCLK = 0x00000001,
+} OVERRIDE_CGTT_DCEFCLK;
+
+/*******************************************************
+ * DCIO Enums
+ *******************************************************/
+
+/*
+ * DCIO_DC_GENERICA_SEL enum
+ */
+
+typedef enum DCIO_DC_GENERICA_SEL {
+DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0x00000000,
+DCIO_GENERICA_SEL_STEREOSYNC = 0x00000001,
+DCIO_GENERICA_SEL_DACA_PIXCLK = 0x00000002,
+DCIO_GENERICA_SEL_DACB_PIXCLK = 0x00000003,
+DCIO_GENERICA_SEL_DVOA_CTL3 = 0x00000004,
+DCIO_GENERICA_SEL_P1_PLLCLK = 0x00000005,
+DCIO_GENERICA_SEL_P2_PLLCLK = 0x00000006,
+DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 0x00000007,
+DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 0x00000008,
+DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 0x00000009,
+DCIO_GENERICA_SEL_GENERICA_DCCG = 0x0000000a,
+DCIO_GENERICA_SEL_SYNCEN = 0x0000000b,
+DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK = 0x0000000c,
+DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK = 0x0000000d,
+DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK = 0x0000000e,
+DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2 = 0x0000000f,
+DCIO_GENERICA_SEL_GENERICA_DPRX = 0x00000010,
+DCIO_GENERICA_SEL_GENERICB_DPRX = 0x00000011,
+} DCIO_DC_GENERICA_SEL;
+
+/*
+ * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum
+ */
+
+typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
+DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x00000000,
+DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x00000001,
+DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x00000002,
+DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x00000003,
+DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x00000004,
+DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x00000005,
+DCIO_UNIPHYG_TEST_REFDIV_CLK = 0x00000006,
+DCIO_UNIPHYLPA_TEST_REFDIV_CLK = 0x00000007,
+DCIO_UNIPHYLPB_TEST_REFDIV_CLK = 0x00000008,
+} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
+
+/*
+ * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum
+ */
+
+typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
+DCIO_UNIPHYA_FBDIV_CLK = 0x00000000,
+DCIO_UNIPHYB_FBDIV_CLK = 0x00000001,
+DCIO_UNIPHYC_FBDIV_CLK = 0x00000002,
+DCIO_UNIPHYD_FBDIV_CLK = 0x00000003,
+DCIO_UNIPHYE_FBDIV_CLK = 0x00000004,
+DCIO_UNIPHYF_FBDIV_CLK = 0x00000005,
+DCIO_UNIPHYG_FBDIV_CLK = 0x00000006,
+DCIO_UNIPHYLPA_FBDIV_CLK = 0x00000007,
+DCIO_UNIPHYLPB_FBDIV_CLK = 0x00000008,
+} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
+
+/*
+ * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum
+ */
+
+typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
+DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x00000000,
+DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x00000001,
+DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x00000002,
+DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x00000003,
+DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x00000004,
+DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x00000005,
+DCIO_UNIPHYG_FBDIV_SSC_CLK = 0x00000006,
+DCIO_UNIPHYLPA_FBDIV_SSC_CLK = 0x00000007,
+DCIO_UNIPHYLPB_FBDIV_SSC_CLK = 0x00000008,
+} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
+
+/*
+ * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum
+ */
+
+typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
+DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x00000000,
+DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x00000001,
+DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x00000002,
+DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x00000003,
+DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x00000004,
+DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x00000005,
+DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 0x00000006,
+DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2 = 0x00000007,
+DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2 = 0x00000008,
+} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
+
+/*
+ * DCIO_DC_GENERICB_SEL enum
+ */
+
+typedef enum DCIO_DC_GENERICB_SEL {
+DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0x00000000,
+DCIO_GENERICB_SEL_STEREOSYNC = 0x00000001,
+DCIO_GENERICB_SEL_DACA_PIXCLK = 0x00000002,
+DCIO_GENERICB_SEL_DACB_PIXCLK = 0x00000003,
+DCIO_GENERICB_SEL_DVOA_CTL3 = 0x00000004,
+DCIO_GENERICB_SEL_P1_PLLCLK = 0x00000005,
+DCIO_GENERICB_SEL_P2_PLLCLK = 0x00000006,
+DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 0x00000007,
+DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 0x00000008,
+DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 0x00000009,
+DCIO_GENERICB_SEL_GENERICB_DCCG = 0x0000000a,
+DCIO_GENERICB_SEL_SYNCEN = 0x0000000b,
+DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK = 0x0000000c,
+DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK = 0x0000000d,
+DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK = 0x0000000e,
+DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2 = 0x0000000f,
+} DCIO_DC_GENERICB_SEL;
+
+/*
+ * DCIO_DC_PAD_EXTERN_SIG_SEL enum
+ */
+
+typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
+DCIO_DC_PAD_EXTERN_SIG_SEL_MVP = 0x00000000,
+DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 0x00000001,
+DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 0x00000002,
+DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 0x00000003,
+DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA = 0x00000004,
+DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB = 0x00000005,
+DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC = 0x00000006,
+DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1 = 0x00000007,
+DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2 = 0x00000008,
+DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK = 0x00000009,
+DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 0x0000000a,
+DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK = 0x0000000b,
+DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA = 0x0000000c,
+DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1 = 0x0000000d,
+DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0 = 0x0000000e,
+DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL = 0x0000000f,
+} DCIO_DC_PAD_EXTERN_SIG_SEL;
+
+/*
+ * DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS enum
+ */
+
+typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {
+DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA = 0x00000000,
+DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 0x00000001,
+DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 0x00000002,
+DCIO_MVP_PIXEL_SRC_STATUS_LB = 0x00000003,
+} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS;
+
+/*
+ * DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL enum
+ */
+
+typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
+DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x00000000,
+DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x00000001,
+DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x00000002,
+DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x00000003,
+} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
+
+/*
+ * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum
+ */
+
+typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
+DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x00000000,
+DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x00000001,
+DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x00000002,
+DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x00000003,
+} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
+
+/*
+ * DCIO_DC_GPIO_VIP_DEBUG enum
+ */
+
+typedef enum DCIO_DC_GPIO_VIP_DEBUG {
+DCIO_DC_GPIO_VIP_DEBUG_NORMAL = 0x00000000,
+DCIO_DC_GPIO_VIP_DEBUG_CG_BIG = 0x00000001,
+} DCIO_DC_GPIO_VIP_DEBUG;
+
+/*
+ * DCIO_DC_GPIO_MACRO_DEBUG enum
+ */
+
+typedef enum DCIO_DC_GPIO_MACRO_DEBUG {
+DCIO_DC_GPIO_MACRO_DEBUG_NORMAL = 0x00000000,
+DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF = 0x00000001,
+DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 0x00000002,
+DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 0x00000003,
+} DCIO_DC_GPIO_MACRO_DEBUG;
+
+/*
+ * DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL enum
+ */
+
+typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {
+DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0x00000000,
+DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 0x00000001,
+} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL;
+
+/*
+ * DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN enum
+ */
+
+typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {
+DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS = 0x00000000,
+DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE = 0x00000001,
+} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN;
+
+/*
+ * DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE enum
+ */
+
+typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
+DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x00000000,
+DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x00000001,
+} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
+
+/*
+ * DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION enum
+ */
+
+typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
+DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x00000000,
+DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x00000001,
+DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS = 0x00000002,
+DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS = 0x00000003,
+DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS = 0x00000004,
+DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS = 0x00000005,
+DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS = 0x00000006,
+DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS = 0x00000007,
+} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;
+
+/*
+ * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum
+ */
+
+typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
+DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x00000000,
+DCIO_UNIPHY_CHANNEL_INVERTED = 0x00000001,
+} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
+
+/*
+ * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum
+ */
+
+typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
+DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x00000000,
+DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x00000001,
+DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x00000002,
+DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 0x00000003,
+} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
+
+/*
+ * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum
+ */
+
+typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
+DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x00000000,
+DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x00000001,
+DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x00000002,
+DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x00000003,
+} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
+
+/*
+ * DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN enum
+ */
+
+typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
+DCIO_VIP_MUX_EN_DVO = 0x00000000,
+DCIO_VIP_MUX_EN_VIP = 0x00000001,
+} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;
+
+/*
+ * DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN enum
+ */
+
+typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
+DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0x00000000,
+DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 0x00000001,
+} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;
+
+/*
+ * DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN enum
+ */
+
+typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
+DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0x00000000,
+DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 0x00000001,
+} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;
+
+/*
+ * DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN enum
+ */
+
+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
+DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE = 0x00000000,
+DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE = 0x00000001,
+} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;
+
+/*
+ * DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE enum
+ */
+
+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
+DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0x00000000,
+DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 0x00000001,
+} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;
+
+/*
+ * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL enum
+ */
+
+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
+DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0x00000000,
+DCIO_LVTMA_SYNCEN_POL_INVERT = 0x00000001,
+} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;
+
+/*
+ * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON enum
+ */
+
+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
+DCIO_LVTMA_DIGON_OFF = 0x00000000,
+DCIO_LVTMA_DIGON_ON = 0x00000001,
+} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;
+
+/*
+ * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL enum
+ */
+
+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
+DCIO_LVTMA_DIGON_POL_NON_INVERT = 0x00000000,
+DCIO_LVTMA_DIGON_POL_INVERT = 0x00000001,
+} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;
+
+/*
+ * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON enum
+ */
+
+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
+DCIO_LVTMA_BLON_OFF = 0x00000000,
+DCIO_LVTMA_BLON_ON = 0x00000001,
+} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;
+
+/*
+ * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL enum
+ */
+
+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
+DCIO_LVTMA_BLON_POL_NON_INVERT = 0x00000000,
+DCIO_LVTMA_BLON_POL_INVERT = 0x00000001,
+} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;
+
+/*
+ * DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN enum
+ */
+
+typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
+DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0x00000000,
+DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 0x00000001,
+} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;
+
+/*
+ * DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum
+ */
+
+typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
+DCIO_BL_PWM_FRACTIONAL_DISABLE = 0x00000000,
+DCIO_BL_PWM_FRACTIONAL_ENABLE = 0x00000001,
+} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
+
+/*
+ * DCIO_BL_PWM_CNTL_BL_PWM_EN enum
+ */
+
+typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
+DCIO_BL_PWM_DISABLE = 0x00000000,
+DCIO_BL_PWM_ENABLE = 0x00000001,
+} DCIO_BL_PWM_CNTL_BL_PWM_EN;
+
+/*
+ * DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT enum
+ */
+
+typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
+DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x00000000,
+DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x00000001,
+DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x00000002,
+DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x00000003,
+} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
+
+/*
+ * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum
+ */
+
+typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
+DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x00000000,
+DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x00000001,
+} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
+
+/*
+ * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN enum
+ */
+
+typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
+DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0x00000000,
+DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 0x00000001,
+} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;
+
+/*
+ * DCIO_BL_PWM_GRP1_REG_LOCK enum
+ */
+
+typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
+DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x00000000,
+DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x00000001,
+} DCIO_BL_PWM_GRP1_REG_LOCK;
+
+/*
+ * DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum
+ */
+
+typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
+DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x00000000,
+DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x00000001,
+} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
+
+/*
+ * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum
+ */
+
+typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
+DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0x00000000,
+DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 0x00000001,
+DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 0x00000002,
+DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 0x00000003,
+DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 0x00000004,
+DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 0x00000005,
+} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
+
+/*
+ * DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum
+ */
+
+typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
+DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x00000000,
+DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 0x00000001,
+} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
+
+/*
+ * DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum
+ */
+
+typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
+DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x00000000,
+DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x00000001,
+} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
+
+/*
+ * DCIO_GSL_SEL enum
+ */
+
+typedef enum DCIO_GSL_SEL {
+DCIO_GSL_SEL_GROUP_0 = 0x00000000,
+DCIO_GSL_SEL_GROUP_1 = 0x00000001,
+DCIO_GSL_SEL_GROUP_2 = 0x00000002,
+} DCIO_GSL_SEL;
+
+/*
+ * DCIO_GENLK_CLK_GSL_MASK enum
+ */
+
+typedef enum DCIO_GENLK_CLK_GSL_MASK {
+DCIO_GENLK_CLK_GSL_MASK_NO = 0x00000000,
+DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x00000001,
+DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x00000002,
+} DCIO_GENLK_CLK_GSL_MASK;
+
+/*
+ * DCIO_GENLK_VSYNC_GSL_MASK enum
+ */
+
+typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
+DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x00000000,
+DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x00000001,
+DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x00000002,
+} DCIO_GENLK_VSYNC_GSL_MASK;
+
+/*
+ * DCIO_SWAPLOCK_A_GSL_MASK enum
+ */
+
+typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
+DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x00000000,
+DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x00000001,
+DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x00000002,
+} DCIO_SWAPLOCK_A_GSL_MASK;
+
+/*
+ * DCIO_SWAPLOCK_B_GSL_MASK enum
+ */
+
+typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
+DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x00000000,
+DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x00000001,
+DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x00000002,
+} DCIO_SWAPLOCK_B_GSL_MASK;
+
+/*
+ * DCIO_GSL_VSYNC_SEL enum
+ */
+
+typedef enum DCIO_GSL_VSYNC_SEL {
+DCIO_GSL_VSYNC_SEL_PIPE0 = 0x00000000,
+DCIO_GSL_VSYNC_SEL_PIPE1 = 0x00000001,
+DCIO_GSL_VSYNC_SEL_PIPE2 = 0x00000002,
+DCIO_GSL_VSYNC_SEL_PIPE3 = 0x00000003,
+DCIO_GSL_VSYNC_SEL_PIPE4 = 0x00000004,
+DCIO_GSL_VSYNC_SEL_PIPE5 = 0x00000005,
+} DCIO_GSL_VSYNC_SEL;
+
+/*
+ * DCIO_GSL0_TIMING_SYNC_SEL enum
+ */
+
+typedef enum DCIO_GSL0_TIMING_SYNC_SEL {
+DCIO_GSL0_TIMING_SYNC_SEL_PIPE = 0x00000000,
+DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x00000001,
+DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 0x00000002,
+DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A = 0x00000003,
+DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B = 0x00000004,
+} DCIO_GSL0_TIMING_SYNC_SEL;
+
+/*
+ * DCIO_GSL0_GLOBAL_UNLOCK_SEL enum
+ */
+
+typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {
+DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION = 0x00000000,
+DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x00000001,
+DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x00000002,
+DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x00000003,
+DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x00000004,
+} DCIO_GSL0_GLOBAL_UNLOCK_SEL;
+
+/*
+ * DCIO_GSL1_TIMING_SYNC_SEL enum
+ */
+
+typedef enum DCIO_GSL1_TIMING_SYNC_SEL {
+DCIO_GSL1_TIMING_SYNC_SEL_PIPE = 0x00000000,
+DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x00000001,
+DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 0x00000002,
+DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A = 0x00000003,
+DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B = 0x00000004,
+} DCIO_GSL1_TIMING_SYNC_SEL;
+
+/*
+ * DCIO_GSL1_GLOBAL_UNLOCK_SEL enum
+ */
+
+typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {
+DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION = 0x00000000,
+DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x00000001,
+DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x00000002,
+DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x00000003,
+DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x00000004,
+} DCIO_GSL1_GLOBAL_UNLOCK_SEL;
+
+/*
+ * DCIO_GSL2_TIMING_SYNC_SEL enum
+ */
+
+typedef enum DCIO_GSL2_TIMING_SYNC_SEL {
+DCIO_GSL2_TIMING_SYNC_SEL_PIPE = 0x00000000,
+DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x00000001,
+DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 0x00000002,
+DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A = 0x00000003,
+DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B = 0x00000004,
+} DCIO_GSL2_TIMING_SYNC_SEL;
+
+/*
+ * DCIO_GSL2_GLOBAL_UNLOCK_SEL enum
+ */
+
+typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {
+DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION = 0x00000000,
+DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x00000001,
+DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x00000002,
+DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x00000003,
+DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x00000004,
+} DCIO_GSL2_GLOBAL_UNLOCK_SEL;
+
+/*
+ * DCIO_DC_GPU_TIMER_START_POSITION enum
+ */
+
+typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
+DCIO_GPU_TIMER_START_0_END_27 = 0x00000000,
+DCIO_GPU_TIMER_START_1_END_28 = 0x00000001,
+DCIO_GPU_TIMER_START_2_END_29 = 0x00000002,
+DCIO_GPU_TIMER_START_3_END_30 = 0x00000003,
+DCIO_GPU_TIMER_START_4_END_31 = 0x00000004,
+DCIO_GPU_TIMER_START_6_END_33 = 0x00000005,
+DCIO_GPU_TIMER_START_8_END_35 = 0x00000006,
+DCIO_GPU_TIMER_START_10_END_37 = 0x00000007,
+} DCIO_DC_GPU_TIMER_START_POSITION;
+
+/*
+ * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum
+ */
+
+typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
+DCIO_TEST_CLK_SEL_DISPCLK = 0x00000000,
+DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x00000001,
+DCIO_TEST_CLK_SEL_SCLK = 0x00000002,
+} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
+
+/*
+ * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum
+ */
+
+typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
+DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x00000000,
+DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x00000001,
+} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
+
+/*
+ * DCIO_DCO_DCFE_EXT_VSYNC_MUX enum
+ */
+
+typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {
+DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x00000000,
+DCIO_EXT_VSYNC_MUX_CRTC0 = 0x00000001,
+DCIO_EXT_VSYNC_MUX_CRTC1 = 0x00000002,
+DCIO_EXT_VSYNC_MUX_CRTC2 = 0x00000003,
+DCIO_EXT_VSYNC_MUX_CRTC3 = 0x00000004,
+DCIO_EXT_VSYNC_MUX_CRTC4 = 0x00000005,
+DCIO_EXT_VSYNC_MUX_CRTC5 = 0x00000006,
+DCIO_EXT_VSYNC_MUX_GENERICB = 0x00000007,
+} DCIO_DCO_DCFE_EXT_VSYNC_MUX;
+
+/*
+ * DCIO_DCO_EXT_VSYNC_MASK enum
+ */
+
+typedef enum DCIO_DCO_EXT_VSYNC_MASK {
+DCIO_EXT_VSYNC_MASK_NONE = 0x00000000,
+DCIO_EXT_VSYNC_MASK_PIPE0 = 0x00000001,
+DCIO_EXT_VSYNC_MASK_PIPE1 = 0x00000002,
+DCIO_EXT_VSYNC_MASK_PIPE2 = 0x00000003,
+DCIO_EXT_VSYNC_MASK_PIPE3 = 0x00000004,
+DCIO_EXT_VSYNC_MASK_PIPE4 = 0x00000005,
+DCIO_EXT_VSYNC_MASK_PIPE5 = 0x00000006,
+DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x00000007,
+} DCIO_DCO_EXT_VSYNC_MASK;
+
+/*
+ * DCIO_DSYNC_SOFT_RESET enum
+ */
+
+typedef enum DCIO_DSYNC_SOFT_RESET {
+DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x00000000,
+DCIO_DSYNC_SOFT_RESET_ASSERT = 0x00000001,
+} DCIO_DSYNC_SOFT_RESET;
+
+/*
+ * DCIO_DACA_SOFT_RESET enum
+ */
+
+typedef enum DCIO_DACA_SOFT_RESET {
+DCIO_DACA_SOFT_RESET_DEASSERT = 0x00000000,
+DCIO_DACA_SOFT_RESET_ASSERT = 0x00000001,
+} DCIO_DACA_SOFT_RESET;
+
+/*
+ * DCIO_DCRXPHY_SOFT_RESET enum
+ */
+
+typedef enum DCIO_DCRXPHY_SOFT_RESET {
+DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x00000000,
+DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x00000001,
+} DCIO_DCRXPHY_SOFT_RESET;
+
+/*
+ * DCIO_DPHY_LANE_SEL enum
+ */
+
+typedef enum DCIO_DPHY_LANE_SEL {
+DCIO_DPHY_LANE_SEL_LANE0 = 0x00000000,
+DCIO_DPHY_LANE_SEL_LANE1 = 0x00000001,
+DCIO_DPHY_LANE_SEL_LANE2 = 0x00000002,
+DCIO_DPHY_LANE_SEL_LANE3 = 0x00000003,
+} DCIO_DPHY_LANE_SEL;
+
+/*
+ * DCIO_DPCS_INTERRUPT_TYPE enum
+ */
+
+typedef enum DCIO_DPCS_INTERRUPT_TYPE {
+DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000,
+DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 0x00000001,
+} DCIO_DPCS_INTERRUPT_TYPE;
+
+/*
+ * DCIO_DPCS_INTERRUPT_MASK enum
+ */
+
+typedef enum DCIO_DPCS_INTERRUPT_MASK {
+DCIO_DPCS_INTERRUPT_DISABLE = 0x00000000,
+DCIO_DPCS_INTERRUPT_ENABLE = 0x00000001,
+} DCIO_DPCS_INTERRUPT_MASK;
+
+/*
+ * DCIO_DC_GPU_TIMER_READ_SELECT enum
+ */
+
+typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
+DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x00000000,
+DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x00000001,
+DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 0x00000002,
+DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 0x00000003,
+DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x00000004,
+DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 0x00000005,
+DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE = 0x00000006,
+DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE = 0x00000007,
+DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE = 0x00000008,
+DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE = 0x00000009,
+DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE = 0x0000000a,
+DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE = 0x0000000b,
+DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0x0000000c,
+DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0x0000000d,
+DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 0x0000000e,
+DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 0x0000000f,
+DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 0x00000010,
+DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 0x00000011,
+DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP = 0x00000012,
+DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP = 0x00000013,
+DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP = 0x00000014,
+DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP = 0x00000015,
+DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP = 0x00000016,
+DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP = 0x00000017,
+DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x00000018,
+DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x00000019,
+DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 0x0000001a,
+DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 0x0000001b,
+DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 0x0000001c,
+DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 0x0000001d,
+DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM = 0x0000001e,
+DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM = 0x0000001f,
+DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM = 0x00000020,
+DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM = 0x00000021,
+DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM = 0x00000022,
+DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM = 0x00000023,
+} DCIO_DC_GPU_TIMER_READ_SELECT;
+
+/*
+ * DCIO_IMPCAL_STEP_DELAY enum
+ */
+
+typedef enum DCIO_IMPCAL_STEP_DELAY {
+DCIO_IMPCAL_STEP_DELAY_1us = 0x00000000,
+DCIO_IMPCAL_STEP_DELAY_2us = 0x00000001,
+DCIO_IMPCAL_STEP_DELAY_3us = 0x00000002,
+DCIO_IMPCAL_STEP_DELAY_4us = 0x00000003,
+DCIO_IMPCAL_STEP_DELAY_5us = 0x00000004,
+DCIO_IMPCAL_STEP_DELAY_6us = 0x00000005,
+DCIO_IMPCAL_STEP_DELAY_7us = 0x00000006,
+DCIO_IMPCAL_STEP_DELAY_8us = 0x00000007,
+DCIO_IMPCAL_STEP_DELAY_9us = 0x00000008,
+DCIO_IMPCAL_STEP_DELAY_10us = 0x00000009,
+DCIO_IMPCAL_STEP_DELAY_11us = 0x0000000a,
+DCIO_IMPCAL_STEP_DELAY_12us = 0x0000000b,
+DCIO_IMPCAL_STEP_DELAY_13us = 0x0000000c,
+DCIO_IMPCAL_STEP_DELAY_14us = 0x0000000d,
+DCIO_IMPCAL_STEP_DELAY_15us = 0x0000000e,
+DCIO_IMPCAL_STEP_DELAY_16us = 0x0000000f,
+} DCIO_IMPCAL_STEP_DELAY;
+
+/*
+ * DCIO_UNIPHY_IMPCAL_SEL enum
+ */
+
+typedef enum DCIO_UNIPHY_IMPCAL_SEL {
+DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x00000000,
+DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x00000001,
+} DCIO_UNIPHY_IMPCAL_SEL;
+
+/*
+ * DCIO_DBG_ASYNC_BLOCK_SEL enum
+ */
+
+typedef enum DCIO_DBG_ASYNC_BLOCK_SEL {
+DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0x00000000,
+DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 0x00000001,
+DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 0x00000002,
+DCIO_DBG_ASYNC_BLOCK_SEL_DCO = 0x00000003,
+} DCIO_DBG_ASYNC_BLOCK_SEL;
+
+/*
+ * DCIO_DBG_ASYNC_4BIT_SEL enum
+ */
+
+typedef enum DCIO_DBG_ASYNC_4BIT_SEL {
+DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0x00000000,
+DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 0x00000001,
+DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 0x00000002,
+DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 0x00000003,
+DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 0x00000004,
+DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 0x00000005,
+DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 0x00000006,
+DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 0x00000007,
+} DCIO_DBG_ASYNC_4BIT_SEL;
+
+/*******************************************************
+ * AOUT Enums
+ *******************************************************/
+
+/*
+ * AOUT_EN enum
+ */
+
+typedef enum AOUT_EN {
+AOUT_DISABLE = 0x00000000,
+AOUT_ENABLE = 0x00000001,
+} AOUT_EN;
+
+/*
+ * AOUT_FIFO_START_ADDR enum
+ */
+
+typedef enum AOUT_FIFO_START_ADDR {
+AOUT_FIFO_START_ADDR_2 = 0x00000000,
+AOUT_FIFO_START_ADDR_3 = 0x00000001,
+} AOUT_FIFO_START_ADDR;
+
+/*
+ * AOUT_CRC_TEST_EN enum
+ */
+
+typedef enum AOUT_CRC_TEST_EN {
+AOUT_CRC_DISABLE = 0x00000000,
+AOUT_CRC_ENABLE = 0x00000001,
+} AOUT_CRC_TEST_EN;
+
+/*
+ * AOUT_CRC_SOFT_RESET enum
+ */
+
+typedef enum AOUT_CRC_SOFT_RESET {
+AOUT_CRC_NO_RESET = 0x00000000,
+AOUT_CRC_RESET = 0x00000001,
+} AOUT_CRC_SOFT_RESET;
+
+/*
+ * AOUT_CRC_CONT_EN enum
+ */
+
+typedef enum AOUT_CRC_CONT_EN {
+AOUT_CRC_ONE_SHOT = 0x00000000,
+AOUT_CRC_CONT = 0x00000001,
+} AOUT_CRC_CONT_EN;
+
+/*
+ * I2S_WORD_SIZE enum
+ */
+
+typedef enum I2S_WORD_SIZE {
+I2S_WORD_SIZE_32 = 0x00000000,
+I2S_WORD_SIZE_16 = 0x00000001,
+} I2S_WORD_SIZE;
+
+/*
+ * I2S_SAMPLE_ALIGNMENT enum
+ */
+
+typedef enum I2S_SAMPLE_ALIGNMENT {
+I2S_SAMPLE_LEFT_ALIGNED = 0x00000000,
+I2S_SAMPLE_RIGHT_ALIGNED = 0x00000001,
+} I2S_SAMPLE_ALIGNMENT;
+
+/*
+ * I2S_SAMPLE_BIT_ORDER enum
+ */
+
+typedef enum I2S_SAMPLE_BIT_ORDER {
+I2S_SAMPLE_BIT_ORDER_MSB = 0x00000000,
+I2S_SAMPLE_BIT_ORDER_LSB = 0x00000001,
+} I2S_SAMPLE_BIT_ORDER;
+
+/*
+ * I2S_LRCLK_POLARITY enum
+ */
+
+typedef enum I2S_LRCLK_POLARITY {
+I2S_LRCLK_LOW_LEFT = 0x00000000,
+I2S_LRCLK_HIGH_LEFT = 0x00000001,
+} I2S_LRCLK_POLARITY;
+
+/*
+ * I2S_WORD_ALIGNMENT enum
+ */
+
+typedef enum I2S_WORD_ALIGNMENT {
+I2S_WORD_ALTERNATE_ALIGNMENT = 0x00000000,
+I2S_WORD_I2S_ALIGNMENT = 0x00000001,
+} I2S_WORD_ALIGNMENT;
+
+/*
+ * SPDIF_INVERT_EN enum
+ */
+
+typedef enum SPDIF_INVERT_EN {
+SPDIF_INVERT_DISABLE = 0x00000000,
+SPDIF_INVERT_ENABLE = 0x00000001,
+} SPDIF_INVERT_EN;
+
+/*******************************************************
+ * DCO Enums
+ *******************************************************/
+
+/*
+ * DPDBG_EN enum
+ */
+
+typedef enum DPDBG_EN {
+DPDBG_DISABLE = 0x00000000,
+DPDBG_ENABLE = 0x00000001,
+} DPDBG_EN;
+
+/*
+ * DPDBG_INPUT_EN enum
+ */
+
+typedef enum DPDBG_INPUT_EN {
+DPDBG_INPUT_DISABLE = 0x00000000,
+DPDBG_INPUT_ENABLE = 0x00000001,
+} DPDBG_INPUT_EN;
+
+/*
+ * DPDBG_ERROR_DETECTION_MODE enum
+ */
+
+typedef enum DPDBG_ERROR_DETECTION_MODE {
+DPDBG_ERROR_DETECTION_MODE_CSC = 0x00000000,
+DPDBG_ERROR_DETECTION_MODE_RS_ENCODING = 0x00000001,
+} DPDBG_ERROR_DETECTION_MODE;
+
+/*
+ * DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK enum
+ */
+
+typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK {
+DPDBG_FIFO_OVERFLOW_INT_DISABLE = 0x00000000,
+DPDBG_FIFO_OVERFLOW_INT_ENABLE = 0x00000001,
+} DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK;
+
+/*
+ * DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE enum
+ */
+
+typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE {
+DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED = 0x00000000,
+DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED = 0x00000001,
+} DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE;
+
+/*
+ * DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK enum
+ */
+
+typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK {
+DPDBG_FIFO_OVERFLOW_INT_NO_ACK = 0x00000000,
+DPDBG_FIFO_OVERFLOW_INT_CLEAR = 0x00000001,
+} DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK;
+
+/*
+ * PM_ASSERT_RESET enum
+ */
+
+typedef enum PM_ASSERT_RESET {
+PM_ASSERT_RESET_0 = 0x00000000,
+PM_ASSERT_RESET_1 = 0x00000001,
+} PM_ASSERT_RESET;
+
+/*
+ * DAC_MUX_SELECT enum
+ */
+
+typedef enum DAC_MUX_SELECT {
+DAC_MUX_SELECT_DACA = 0x00000000,
+DAC_MUX_SELECT_DACB = 0x00000001,
+} DAC_MUX_SELECT;
+
+/*
+ * TMDS_DVO_MUX_SELECT enum
+ */
+
+typedef enum TMDS_DVO_MUX_SELECT {
+TMDS_DVO_MUX_SELECT_B = 0x00000000,
+TMDS_DVO_MUX_SELECT_G = 0x00000001,
+TMDS_DVO_MUX_SELECT_R = 0x00000002,
+TMDS_DVO_MUX_SELECT_RESERVED = 0x00000003,
+} TMDS_DVO_MUX_SELECT;
+
+/*
+ * DACA_SOFT_RESET enum
+ */
+
+typedef enum DACA_SOFT_RESET {
+DACA_SOFT_RESET_0 = 0x00000000,
+DACA_SOFT_RESET_1 = 0x00000001,
+} DACA_SOFT_RESET;
+
+/*
+ * I2S0_SPDIF0_SOFT_RESET enum
+ */
+
+typedef enum I2S0_SPDIF0_SOFT_RESET {
+I2S0_SPDIF0_SOFT_RESET_0 = 0x00000000,
+I2S0_SPDIF0_SOFT_RESET_1 = 0x00000001,
+} I2S0_SPDIF0_SOFT_RESET;
+
+/*
+ * I2S1_SOFT_RESET enum
+ */
+
+typedef enum I2S1_SOFT_RESET {
+I2S1_SOFT_RESET_0 = 0x00000000,
+I2S1_SOFT_RESET_1 = 0x00000001,
+} I2S1_SOFT_RESET;
+
+/*
+ * SPDIF1_SOFT_RESET enum
+ */
+
+typedef enum SPDIF1_SOFT_RESET {
+SPDIF1_SOFT_RESET_0 = 0x00000000,
+SPDIF1_SOFT_RESET_1 = 0x00000001,
+} SPDIF1_SOFT_RESET;
+
+/*
+ * DB_CLK_SOFT_RESET enum
+ */
+
+typedef enum DB_CLK_SOFT_RESET {
+DB_CLK_SOFT_RESET_0 = 0x00000000,
+DB_CLK_SOFT_RESET_1 = 0x00000001,
+} DB_CLK_SOFT_RESET;
+
+/*
+ * FMT0_SOFT_RESET enum
+ */
+
+typedef enum FMT0_SOFT_RESET {
+FMT0_SOFT_RESET_0 = 0x00000000,
+FMT0_SOFT_RESET_1 = 0x00000001,
+} FMT0_SOFT_RESET;
+
+/*
+ * FMT1_SOFT_RESET enum
+ */
+
+typedef enum FMT1_SOFT_RESET {
+FMT1_SOFT_RESET_0 = 0x00000000,
+FMT1_SOFT_RESET_1 = 0x00000001,
+} FMT1_SOFT_RESET;
+
+/*
+ * FMT2_SOFT_RESET enum
+ */
+
+typedef enum FMT2_SOFT_RESET {
+FMT2_SOFT_RESET_0 = 0x00000000,
+FMT2_SOFT_RESET_1 = 0x00000001,
+} FMT2_SOFT_RESET;
+
+/*
+ * FMT3_SOFT_RESET enum
+ */
+
+typedef enum FMT3_SOFT_RESET {
+FMT3_SOFT_RESET_0 = 0x00000000,
+FMT3_SOFT_RESET_1 = 0x00000001,
+} FMT3_SOFT_RESET;
+
+/*
+ * FMT4_SOFT_RESET enum
+ */
+
+typedef enum FMT4_SOFT_RESET {
+FMT4_SOFT_RESET_0 = 0x00000000,
+FMT4_SOFT_RESET_1 = 0x00000001,
+} FMT4_SOFT_RESET;
+
+/*
+ * FMT5_SOFT_RESET enum
+ */
+
+typedef enum FMT5_SOFT_RESET {
+FMT5_SOFT_RESET_0 = 0x00000000,
+FMT5_SOFT_RESET_1 = 0x00000001,
+} FMT5_SOFT_RESET;
+
+/*
+ * MVP_SOFT_RESET enum
+ */
+
+typedef enum MVP_SOFT_RESET {
+MVP_SOFT_RESET_0 = 0x00000000,
+MVP_SOFT_RESET_1 = 0x00000001,
+} MVP_SOFT_RESET;
+
+/*
+ * ABM_SOFT_RESET enum
+ */
+
+typedef enum ABM_SOFT_RESET {
+ABM_SOFT_RESET_0 = 0x00000000,
+ABM_SOFT_RESET_1 = 0x00000001,
+} ABM_SOFT_RESET;
+
+/*
+ * DVO_SOFT_RESET enum
+ */
+
+typedef enum DVO_SOFT_RESET {
+DVO_SOFT_RESET_0 = 0x00000000,
+DVO_SOFT_RESET_1 = 0x00000001,
+} DVO_SOFT_RESET;
+
+/*
+ * DIGA_FE_SOFT_RESET enum
+ */
+
+typedef enum DIGA_FE_SOFT_RESET {
+DIGA_FE_SOFT_RESET_0 = 0x00000000,
+DIGA_FE_SOFT_RESET_1 = 0x00000001,
+} DIGA_FE_SOFT_RESET;
+
+/*
+ * DIGA_BE_SOFT_RESET enum
+ */
+
+typedef enum DIGA_BE_SOFT_RESET {
+DIGA_BE_SOFT_RESET_0 = 0x00000000,
+DIGA_BE_SOFT_RESET_1 = 0x00000001,
+} DIGA_BE_SOFT_RESET;
+
+/*
+ * DIGB_FE_SOFT_RESET enum
+ */
+
+typedef enum DIGB_FE_SOFT_RESET {
+DIGB_FE_SOFT_RESET_0 = 0x00000000,
+DIGB_FE_SOFT_RESET_1 = 0x00000001,
+} DIGB_FE_SOFT_RESET;
+
+/*
+ * DIGB_BE_SOFT_RESET enum
+ */
+
+typedef enum DIGB_BE_SOFT_RESET {
+DIGB_BE_SOFT_RESET_0 = 0x00000000,
+DIGB_BE_SOFT_RESET_1 = 0x00000001,
+} DIGB_BE_SOFT_RESET;
+
+/*
+ * DIGC_FE_SOFT_RESET enum
+ */
+
+typedef enum DIGC_FE_SOFT_RESET {
+DIGC_FE_SOFT_RESET_0 = 0x00000000,
+DIGC_FE_SOFT_RESET_1 = 0x00000001,
+} DIGC_FE_SOFT_RESET;
+
+/*
+ * DIGC_BE_SOFT_RESET enum
+ */
+
+typedef enum DIGC_BE_SOFT_RESET {
+DIGC_BE_SOFT_RESET_0 = 0x00000000,
+DIGC_BE_SOFT_RESET_1 = 0x00000001,
+} DIGC_BE_SOFT_RESET;
+
+/*
+ * DIGD_FE_SOFT_RESET enum
+ */
+
+typedef enum DIGD_FE_SOFT_RESET {
+DIGD_FE_SOFT_RESET_0 = 0x00000000,
+DIGD_FE_SOFT_RESET_1 = 0x00000001,
+} DIGD_FE_SOFT_RESET;
+
+/*
+ * DIGD_BE_SOFT_RESET enum
+ */
+
+typedef enum DIGD_BE_SOFT_RESET {
+DIGD_BE_SOFT_RESET_0 = 0x00000000,
+DIGD_BE_SOFT_RESET_1 = 0x00000001,
+} DIGD_BE_SOFT_RESET;
+
+/*
+ * DIGE_FE_SOFT_RESET enum
+ */
+
+typedef enum DIGE_FE_SOFT_RESET {
+DIGE_FE_SOFT_RESET_0 = 0x00000000,
+DIGE_FE_SOFT_RESET_1 = 0x00000001,
+} DIGE_FE_SOFT_RESET;
+
+/*
+ * DIGE_BE_SOFT_RESET enum
+ */
+
+typedef enum DIGE_BE_SOFT_RESET {
+DIGE_BE_SOFT_RESET_0 = 0x00000000,
+DIGE_BE_SOFT_RESET_1 = 0x00000001,
+} DIGE_BE_SOFT_RESET;
+
+/*
+ * DIGF_FE_SOFT_RESET enum
+ */
+
+typedef enum DIGF_FE_SOFT_RESET {
+DIGF_FE_SOFT_RESET_0 = 0x00000000,
+DIGF_FE_SOFT_RESET_1 = 0x00000001,
+} DIGF_FE_SOFT_RESET;
+
+/*
+ * DIGF_BE_SOFT_RESET enum
+ */
+
+typedef enum DIGF_BE_SOFT_RESET {
+DIGF_BE_SOFT_RESET_0 = 0x00000000,
+DIGF_BE_SOFT_RESET_1 = 0x00000001,
+} DIGF_BE_SOFT_RESET;
+
+/*
+ * DIGG_FE_SOFT_RESET enum
+ */
+
+typedef enum DIGG_FE_SOFT_RESET {
+DIGG_FE_SOFT_RESET_0 = 0x00000000,
+DIGG_FE_SOFT_RESET_1 = 0x00000001,
+} DIGG_FE_SOFT_RESET;
+
+/*
+ * DIGG_BE_SOFT_RESET enum
+ */
+
+typedef enum DIGG_BE_SOFT_RESET {
+DIGG_BE_SOFT_RESET_0 = 0x00000000,
+DIGG_BE_SOFT_RESET_1 = 0x00000001,
+} DIGG_BE_SOFT_RESET;
+
+/*
+ * DPDBG_SOFT_RESET enum
+ */
+
+typedef enum DPDBG_SOFT_RESET {
+DPDBG_SOFT_RESET_0 = 0x00000000,
+DPDBG_SOFT_RESET_1 = 0x00000001,
+} DPDBG_SOFT_RESET;
+
+/*
+ * DIGLPA_FE_SOFT_RESET enum
+ */
+
+typedef enum DIGLPA_FE_SOFT_RESET {
+DIGLPA_FE_SOFT_RESET_0 = 0x00000000,
+DIGLPA_FE_SOFT_RESET_1 = 0x00000001,
+} DIGLPA_FE_SOFT_RESET;
+
+/*
+ * DIGLPA_BE_SOFT_RESET enum
+ */
+
+typedef enum DIGLPA_BE_SOFT_RESET {
+DIGLPA_BE_SOFT_RESET_0 = 0x00000000,
+DIGLPA_BE_SOFT_RESET_1 = 0x00000001,
+} DIGLPA_BE_SOFT_RESET;
+
+/*
+ * DIGLPB_FE_SOFT_RESET enum
+ */
+
+typedef enum DIGLPB_FE_SOFT_RESET {
+DIGLPB_FE_SOFT_RESET_0 = 0x00000000,
+DIGLPB_FE_SOFT_RESET_1 = 0x00000001,
+} DIGLPB_FE_SOFT_RESET;
+
+/*
+ * DIGLPB_BE_SOFT_RESET enum
+ */
+
+typedef enum DIGLPB_BE_SOFT_RESET {
+DIGLPB_BE_SOFT_RESET_0 = 0x00000000,
+DIGLPB_BE_SOFT_RESET_1 = 0x00000001,
+} DIGLPB_BE_SOFT_RESET;
+
+/*
+ * GENERICA_STEREOSYNC_SEL enum
+ */
+
+typedef enum GENERICA_STEREOSYNC_SEL {
+GENERICA_STEREOSYNC_SEL_D1 = 0x00000000,
+GENERICA_STEREOSYNC_SEL_D2 = 0x00000001,
+GENERICA_STEREOSYNC_SEL_D3 = 0x00000002,
+GENERICA_STEREOSYNC_SEL_D4 = 0x00000003,
+GENERICA_STEREOSYNC_SEL_D5 = 0x00000004,
+GENERICA_STEREOSYNC_SEL_D6 = 0x00000005,
+GENERICA_STEREOSYNC_SEL_RESERVED = 0x00000006,
+} GENERICA_STEREOSYNC_SEL;
+
+/*
+ * GENERICB_STEREOSYNC_SEL enum
+ */
+
+typedef enum GENERICB_STEREOSYNC_SEL {
+GENERICB_STEREOSYNC_SEL_D1 = 0x00000000,
+GENERICB_STEREOSYNC_SEL_D2 = 0x00000001,
+GENERICB_STEREOSYNC_SEL_D3 = 0x00000002,
+GENERICB_STEREOSYNC_SEL_D4 = 0x00000003,
+GENERICB_STEREOSYNC_SEL_D5 = 0x00000004,
+GENERICB_STEREOSYNC_SEL_D6 = 0x00000005,
+GENERICB_STEREOSYNC_SEL_RESERVED = 0x00000006,
+} GENERICB_STEREOSYNC_SEL;
+
+/*
+ * DCO_DBG_BLOCK_SEL enum
+ */
+
+typedef enum DCO_DBG_BLOCK_SEL {
+DCO_DBG_BLOCK_SEL_DCO = 0x00000000,
+DCO_DBG_BLOCK_SEL_ABM = 0x00000001,
+DCO_DBG_BLOCK_SEL_DVO = 0x00000002,
+DCO_DBG_BLOCK_SEL_DAC = 0x00000003,
+DCO_DBG_BLOCK_SEL_MVP = 0x00000004,
+DCO_DBG_BLOCK_SEL_FMT0 = 0x00000005,
+DCO_DBG_BLOCK_SEL_FMT1 = 0x00000006,
+DCO_DBG_BLOCK_SEL_FMT2 = 0x00000007,
+DCO_DBG_BLOCK_SEL_FMT3 = 0x00000008,
+DCO_DBG_BLOCK_SEL_FMT4 = 0x00000009,
+DCO_DBG_BLOCK_SEL_FMT5 = 0x0000000a,
+DCO_DBG_BLOCK_SEL_DIGFE_A = 0x0000000b,
+DCO_DBG_BLOCK_SEL_DIGFE_B = 0x0000000c,
+DCO_DBG_BLOCK_SEL_DIGFE_C = 0x0000000d,
+DCO_DBG_BLOCK_SEL_DIGFE_D = 0x0000000e,
+DCO_DBG_BLOCK_SEL_DIGFE_E = 0x0000000f,
+DCO_DBG_BLOCK_SEL_DIGFE_F = 0x00000010,
+DCO_DBG_BLOCK_SEL_DIGFE_G = 0x00000011,
+DCO_DBG_BLOCK_SEL_DIGA = 0x00000012,
+DCO_DBG_BLOCK_SEL_DIGB = 0x00000013,
+DCO_DBG_BLOCK_SEL_DIGC = 0x00000014,
+DCO_DBG_BLOCK_SEL_DIGD = 0x00000015,
+DCO_DBG_BLOCK_SEL_DIGE = 0x00000016,
+DCO_DBG_BLOCK_SEL_DIGF = 0x00000017,
+DCO_DBG_BLOCK_SEL_DIGG = 0x00000018,
+DCO_DBG_BLOCK_SEL_DPFE_A = 0x00000019,
+DCO_DBG_BLOCK_SEL_DPFE_B = 0x0000001a,
+DCO_DBG_BLOCK_SEL_DPFE_C = 0x0000001b,
+DCO_DBG_BLOCK_SEL_DPFE_D = 0x0000001c,
+DCO_DBG_BLOCK_SEL_DPFE_E = 0x0000001d,
+DCO_DBG_BLOCK_SEL_DPFE_F = 0x0000001e,
+DCO_DBG_BLOCK_SEL_DPFE_G = 0x0000001f,
+DCO_DBG_BLOCK_SEL_DPA = 0x00000020,
+DCO_DBG_BLOCK_SEL_DPB = 0x00000021,
+DCO_DBG_BLOCK_SEL_DPC = 0x00000022,
+DCO_DBG_BLOCK_SEL_DPD = 0x00000023,
+DCO_DBG_BLOCK_SEL_DPE = 0x00000024,
+DCO_DBG_BLOCK_SEL_DPF = 0x00000025,
+DCO_DBG_BLOCK_SEL_DPG = 0x00000026,
+DCO_DBG_BLOCK_SEL_AUX0 = 0x00000027,
+DCO_DBG_BLOCK_SEL_AUX1 = 0x00000028,
+DCO_DBG_BLOCK_SEL_AUX2 = 0x00000029,
+DCO_DBG_BLOCK_SEL_AUX3 = 0x0000002a,
+DCO_DBG_BLOCK_SEL_AUX4 = 0x0000002b,
+DCO_DBG_BLOCK_SEL_AUX5 = 0x0000002c,
+DCO_DBG_BLOCK_SEL_PERFMON_DCO = 0x0000002d,
+DCO_DBG_BLOCK_SEL_AUDIO_OUT = 0x0000002e,
+DCO_DBG_BLOCK_SEL_DIGLPFEA = 0x0000002f,
+DCO_DBG_BLOCK_SEL_DIGLPFEB = 0x00000030,
+DCO_DBG_BLOCK_SEL_DIGLPA = 0x00000031,
+DCO_DBG_BLOCK_SEL_DIGLPB = 0x00000032,
+DCO_DBG_BLOCK_SEL_DPLPFEA = 0x00000033,
+DCO_DBG_BLOCK_SEL_DPLPFEB = 0x00000034,
+DCO_DBG_BLOCK_SEL_DPLPA = 0x00000035,
+DCO_DBG_BLOCK_SEL_DPLPB = 0x00000036,
+} DCO_DBG_BLOCK_SEL;
+
+/*
+ * DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE enum
+ */
+
+typedef enum DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE {
+DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0x00000000,
+DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 0x00000001,
+} DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE;
+
+/*
+ * FMT420_MEMORY_SOURCE_SEL enum
+ */
+
+typedef enum FMT420_MEMORY_SOURCE_SEL {
+FMT420_MEMORY_SOURCE_SEL_FMT0 = 0x00000000,
+FMT420_MEMORY_SOURCE_SEL_FMT1 = 0x00000001,
+FMT420_MEMORY_SOURCE_SEL_FMT2 = 0x00000002,
+FMT420_MEMORY_SOURCE_SEL_FMT3 = 0x00000003,
+FMT420_MEMORY_SOURCE_SEL_FMT4 = 0x00000004,
+FMT420_MEMORY_SOURCE_SEL_FMT5 = 0x00000005,
+FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED = 0x00000006,
+} FMT420_MEMORY_SOURCE_SEL;
+
+/*******************************************************
+ * DOUT_I2C Enums
+ *******************************************************/
+
+/*
+ * DOUT_I2C_CONTROL_GO enum
+ */
+
+typedef enum DOUT_I2C_CONTROL_GO {
+DOUT_I2C_CONTROL_STOP_TRANSFER = 0x00000000,
+DOUT_I2C_CONTROL_START_TRANSFER = 0x00000001,
+} DOUT_I2C_CONTROL_GO;
+
+/*
+ * DOUT_I2C_CONTROL_SOFT_RESET enum
+ */
+
+typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
+DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x00000000,
+DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 0x00000001,
+} DOUT_I2C_CONTROL_SOFT_RESET;
+
+/*
+ * DOUT_I2C_CONTROL_SEND_RESET enum
+ */
+
+typedef enum DOUT_I2C_CONTROL_SEND_RESET {
+DOUT_I2C_CONTROL__NOT_SEND_RESET = 0x00000000,
+DOUT_I2C_CONTROL__SEND_RESET = 0x00000001,
+} DOUT_I2C_CONTROL_SEND_RESET;
+
+/*
+ * DOUT_I2C_CONTROL_SW_STATUS_RESET enum
+ */
+
+typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
+DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0x00000000,
+DOUT_I2C_CONTROL_RESET_SW_STATUS = 0x00000001,
+} DOUT_I2C_CONTROL_SW_STATUS_RESET;
+
+/*
+ * DOUT_I2C_CONTROL_DDC_SELECT enum
+ */
+
+typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
+DOUT_I2C_CONTROL_SELECT_DDC1 = 0x00000000,
+DOUT_I2C_CONTROL_SELECT_DDC2 = 0x00000001,
+DOUT_I2C_CONTROL_SELECT_DDC3 = 0x00000002,
+DOUT_I2C_CONTROL_SELECT_DDC4 = 0x00000003,
+DOUT_I2C_CONTROL_SELECT_DDC5 = 0x00000004,
+DOUT_I2C_CONTROL_SELECT_DDC6 = 0x00000005,
+DOUT_I2C_CONTROL_SELECT_DDCVGA = 0x00000006,
+} DOUT_I2C_CONTROL_DDC_SELECT;
+
+/*
+ * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum
+ */
+
+typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
+DOUT_I2C_CONTROL_TRANS0 = 0x00000000,
+DOUT_I2C_CONTROL_TRANS0_TRANS1 = 0x00000001,
+DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 0x00000002,
+DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 0x00000003,
+} DOUT_I2C_CONTROL_TRANSACTION_COUNT;
+
+/*
+ * DOUT_I2C_CONTROL_DBG_REF_SEL enum
+ */
+
+typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL {
+DOUT_I2C_CONTROL_NORMAL_DEBUG = 0x00000000,
+DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 0x00000001,
+} DOUT_I2C_CONTROL_DBG_REF_SEL;
+
+/*
+ * DOUT_I2C_ARBITRATION_SW_PRIORITY enum
+ */
+
+typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
+DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0x00000000,
+DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 0x00000001,
+DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x00000002,
+DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x00000003,
+} DOUT_I2C_ARBITRATION_SW_PRIORITY;
+
+/*
+ * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum
+ */
+
+typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
+DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0x00000000,
+DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 0x00000001,
+} DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO;
+
+/*
+ * DOUT_I2C_ARBITRATION_ABORT_XFER enum
+ */
+
+typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
+DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x00000000,
+DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 0x00000001,
+} DOUT_I2C_ARBITRATION_ABORT_XFER;
+
+/*
+ * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum
+ */
+
+typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
+DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x00000000,
+DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 0x00000001,
+} DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ;
+
+/*
+ * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum
+ */
+
+typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
+DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x00000000,
+DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 0x00000001,
+} DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG;
+
+/*
+ * DOUT_I2C_ACK enum
+ */
+
+typedef enum DOUT_I2C_ACK {
+DOUT_I2C_NO_ACK = 0x00000000,
+DOUT_I2C_ACK_TO_CLEAN = 0x00000001,
+} DOUT_I2C_ACK;
+
+/*
+ * DOUT_I2C_DDC_SPEED_THRESHOLD enum
+ */
+
+typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
+DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0x00000000,
+DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 0x00000001,
+DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 0x00000002,
+DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 0x00000003,
+} DOUT_I2C_DDC_SPEED_THRESHOLD;
+
+/*
+ * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum
+ */
+
+typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
+DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000,
+DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 0x00000001,
+} DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN;
+
+/*
+ * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum
+ */
+
+typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
+DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0x00000000,
+DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 0x00000001,
+} DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL;
+
+/*
+ * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum
+ */
+
+typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
+DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0x00000000,
+DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 0x00000001,
+} DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE;
+
+/*
+ * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum
+ */
+
+typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
+DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000,
+DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 0x00000001,
+} DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN;
+
+/*
+ * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum
+ */
+
+typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
+DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0x00000000,
+DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 0x00000001,
+} DOUT_I2C_TRANSACTION_STOP_ON_NACK;
+
+/*
+ * DOUT_I2C_DATA_INDEX_WRITE enum
+ */
+
+typedef enum DOUT_I2C_DATA_INDEX_WRITE {
+DOUT_I2C_DATA__NOT_INDEX_WRITE = 0x00000000,
+DOUT_I2C_DATA__INDEX_WRITE = 0x00000001,
+} DOUT_I2C_DATA_INDEX_WRITE;
+
+/*
+ * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum
+ */
+
+typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
+DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000000,
+DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000001,
+} DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET;
+
+/*
+ * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum
+ */
+
+typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
+DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0x00000000,
+DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 0x00000001,
+} DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE;
+
+/*******************************************************
+ * FBC Enums
+ *******************************************************/
+
+/*
+ * FBC_IDLE_MASK_MASK_BITS enum
+ */
+
+typedef enum FBC_IDLE_MASK_MASK_BITS {
+FBC_IDLE_MASK_DISP_REG_UPDATE = 0x00000000,
+FBC_IDLE_MASK_RESERVED1 = 0x00000001,
+FBC_IDLE_MASK_FBC_GRPH_COMP_EN = 0x00000002,
+FBC_IDLE_MASK_FBC_MIN_COMPRESSION = 0x00000003,
+FBC_IDLE_MASK_FBC_ALPHA_COMP_EN = 0x00000004,
+FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN = 0x00000005,
+FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF = 0x00000006,
+FBC_IDLE_MASK_RESERVED7 = 0x00000007,
+FBC_IDLE_MASK_RESERVED8 = 0x00000008,
+FBC_IDLE_MASK_RESERVED9 = 0x00000009,
+FBC_IDLE_MASK_RESERVED10 = 0x0000000a,
+FBC_IDLE_MASK_RESERVED11 = 0x0000000b,
+FBC_IDLE_MASK_RESERVED12 = 0x0000000c,
+FBC_IDLE_MASK_RESERVED13 = 0x0000000d,
+FBC_IDLE_MASK_RESERVED14 = 0x0000000e,
+FBC_IDLE_MASK_RESERVED15 = 0x0000000f,
+FBC_IDLE_MASK_RESERVED16 = 0x00000010,
+FBC_IDLE_MASK_RESERVED17 = 0x00000011,
+FBC_IDLE_MASK_RESERVED18 = 0x00000012,
+FBC_IDLE_MASK_RESERVED19 = 0x00000013,
+FBC_IDLE_MASK_RESERVED20 = 0x00000014,
+FBC_IDLE_MASK_RESERVED21 = 0x00000015,
+FBC_IDLE_MASK_RESERVED22 = 0x00000016,
+FBC_IDLE_MASK_RESERVED23 = 0x00000017,
+FBC_IDLE_MASK_MC_HIT_REGION_0 = 0x00000018,
+FBC_IDLE_MASK_MC_HIT_REGION_1 = 0x00000019,
+FBC_IDLE_MASK_MC_HIT_REGION_2 = 0x0000001a,
+FBC_IDLE_MASK_MC_HIT_REGION_3 = 0x0000001b,
+FBC_IDLE_MASK_MC_WRITE = 0x0000001c,
+FBC_IDLE_MASK_RESERVED29 = 0x0000001d,
+FBC_IDLE_MASK_RESERVED30 = 0x0000001e,
+FBC_IDLE_MASK_RESERVED31 = 0x0000001f,
+} FBC_IDLE_MASK_MASK_BITS;
+
+/*******************************************************
+ * DPCSRX Enums
+ *******************************************************/
+
+/*
+ * DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL enum
+ */
+
+typedef enum DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL {
+DPCSRX_BPHY_PCS_RX0_CLK = 0x00000000,
+DPCSRX_BPHY_PCS_RX1_CLK = 0x00000001,
+DPCSRX_BPHY_PCS_RX2_CLK = 0x00000002,
+DPCSRX_BPHY_PCS_RX3_CLK = 0x00000003,
+} DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL;
+
+/*
+ * DPCSRX_DBG_CFGCLK_SEL enum
+ */
+
+typedef enum DPCSRX_DBG_CFGCLK_SEL {
+DPCSRX_DBG_CFGCLK_SEL_DC_DPCS_INF = 0x00000000,
+DPCSRX_DBG_CFGCLK_SEL_DPCS_BPHY_INF = 0x00000001,
+DPCSRX_DBG_CFGCLK_SEL_CBUS_SLAVE = 0x00000002,
+DPCSRX_DBG_CFGCLK_SEL_CBUS_MASTER = 0x00000003,
+} DPCSRX_DBG_CFGCLK_SEL;
+
+/*
+ * DPCSRX_RX_SYMCLK_SEL enum
+ */
+
+typedef enum DPCSRX_RX_SYMCLK_SEL {
+DPCSRX_DBG_RX_SYMCLK_SEL_OUT0 = 0x00000000,
+DPCSRX_DBG_RX_SYMCLK_SEL_OUT1 = 0x00000001,
+DPCSRX_DBG_RX_SYMCLK_SEL_INT = 0x00000002,
+} DPCSRX_RX_SYMCLK_SEL;
+
+/*******************************************************
+ * DPCSTX Enums
+ *******************************************************/
+
+/*
+ * DPCSTX_DBG_CFGCLK_SEL enum
+ */
+
+typedef enum DPCSTX_DBG_CFGCLK_SEL {
+DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF = 0x00000000,
+DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF = 0x00000001,
+DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE = 0x00000002,
+DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER = 0x00000003,
+} DPCSTX_DBG_CFGCLK_SEL;
+
+/*
+ * DPCSTX_TX_SYMCLK_SEL enum
+ */
+
+typedef enum DPCSTX_TX_SYMCLK_SEL {
+DPCSTX_DBG_TX_SYMCLK_SEL_IN0 = 0x00000000,
+DPCSTX_DBG_TX_SYMCLK_SEL_IN1 = 0x00000001,
+DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR = 0x00000002,
+} DPCSTX_TX_SYMCLK_SEL;
+
+/*
+ * DPCSTX_TX_SYMCLK_DIV2_SEL enum
+ */
+
+typedef enum DPCSTX_TX_SYMCLK_DIV2_SEL {
+DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0 = 0x00000000,
+DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1 = 0x00000001,
+DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2 = 0x00000002,
+DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3 = 0x00000003,
+DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD = 0x00000004,
+DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT = 0x00000005,
+} DPCSTX_TX_SYMCLK_DIV2_SEL;
+
+/*******************************************************
+ * CB Enums
+ *******************************************************/
+
+/*
+ * SurfaceNumber enum
+ */
+
+typedef enum SurfaceNumber {
+NUMBER_UNORM = 0x00000000,
+NUMBER_SNORM = 0x00000001,
+NUMBER_USCALED = 0x00000002,
+NUMBER_SSCALED = 0x00000003,
+NUMBER_UINT = 0x00000004,
+NUMBER_SINT = 0x00000005,
+NUMBER_SRGB = 0x00000006,
+NUMBER_FLOAT = 0x00000007,
+} SurfaceNumber;
+
+/*
+ * SurfaceSwap enum
+ */
+
+typedef enum SurfaceSwap {
+SWAP_STD = 0x00000000,
+SWAP_ALT = 0x00000001,
+SWAP_STD_REV = 0x00000002,
+SWAP_ALT_REV = 0x00000003,
+} SurfaceSwap;
+
+/*
+ * CBMode enum
+ */
+
+typedef enum CBMode {
+CB_DISABLE = 0x00000000,
+CB_NORMAL = 0x00000001,
+CB_ELIMINATE_FAST_CLEAR = 0x00000002,
+CB_RESOLVE = 0x00000003,
+CB_DECOMPRESS = 0x00000004,
+CB_FMASK_DECOMPRESS = 0x00000005,
+CB_DCC_DECOMPRESS = 0x00000006,
+} CBMode;
+
+/*
+ * RoundMode enum
+ */
+
+typedef enum RoundMode {
+ROUND_BY_HALF = 0x00000000,
+ROUND_TRUNCATE = 0x00000001,
+} RoundMode;
+
+/*
+ * SourceFormat enum
+ */
+
+typedef enum SourceFormat {
+EXPORT_4C_32BPC = 0x00000000,
+EXPORT_4C_16BPC = 0x00000001,
+EXPORT_2C_32BPC_GR = 0x00000002,
+EXPORT_2C_32BPC_AR = 0x00000003,
+} SourceFormat;
+
+/*
+ * BlendOp enum
+ */
+
+typedef enum BlendOp {
+BLEND_ZERO = 0x00000000,
+BLEND_ONE = 0x00000001,
+BLEND_SRC_COLOR = 0x00000002,
+BLEND_ONE_MINUS_SRC_COLOR = 0x00000003,
+BLEND_SRC_ALPHA = 0x00000004,
+BLEND_ONE_MINUS_SRC_ALPHA = 0x00000005,
+BLEND_DST_ALPHA = 0x00000006,
+BLEND_ONE_MINUS_DST_ALPHA = 0x00000007,
+BLEND_DST_COLOR = 0x00000008,
+BLEND_ONE_MINUS_DST_COLOR = 0x00000009,
+BLEND_SRC_ALPHA_SATURATE = 0x0000000a,
+BLEND_BOTH_SRC_ALPHA = 0x0000000b,
+BLEND_BOTH_INV_SRC_ALPHA = 0x0000000c,
+BLEND_CONSTANT_COLOR = 0x0000000d,
+BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0000000e,
+BLEND_SRC1_COLOR = 0x0000000f,
+BLEND_INV_SRC1_COLOR = 0x00000010,
+BLEND_SRC1_ALPHA = 0x00000011,
+BLEND_INV_SRC1_ALPHA = 0x00000012,
+BLEND_CONSTANT_ALPHA = 0x00000013,
+BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x00000014,
+} BlendOp;
+
+/*
+ * CombFunc enum
+ */
+
+typedef enum CombFunc {
+COMB_DST_PLUS_SRC = 0x00000000,
+COMB_SRC_MINUS_DST = 0x00000001,
+COMB_MIN_DST_SRC = 0x00000002,
+COMB_MAX_DST_SRC = 0x00000003,
+COMB_DST_MINUS_SRC = 0x00000004,
+} CombFunc;
+
+/*
+ * BlendOpt enum
+ */
+
+typedef enum BlendOpt {
+FORCE_OPT_AUTO = 0x00000000,
+FORCE_OPT_DISABLE = 0x00000001,
+FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x00000002,
+FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x00000003,
+FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x00000004,
+FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x00000005,
+FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x00000006,
+FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x00000007,
+} BlendOpt;
+
+/*
+ * CmaskCode enum
+ */
+
+typedef enum CmaskCode {
+CMASK_CLR00_F0 = 0x00000000,
+CMASK_CLR00_F1 = 0x00000001,
+CMASK_CLR00_F2 = 0x00000002,
+CMASK_CLR00_FX = 0x00000003,
+CMASK_CLR01_F0 = 0x00000004,
+CMASK_CLR01_F1 = 0x00000005,
+CMASK_CLR01_F2 = 0x00000006,
+CMASK_CLR01_FX = 0x00000007,
+CMASK_CLR10_F0 = 0x00000008,
+CMASK_CLR10_F1 = 0x00000009,
+CMASK_CLR10_F2 = 0x0000000a,
+CMASK_CLR10_FX = 0x0000000b,
+CMASK_CLR11_F0 = 0x0000000c,
+CMASK_CLR11_F1 = 0x0000000d,
+CMASK_CLR11_F2 = 0x0000000e,
+CMASK_CLR11_FX = 0x0000000f,
+} CmaskCode;
+
+/*
+ * CmaskAddr enum
+ */
+
+typedef enum CmaskAddr {
+CMASK_ADDR_TILED = 0x00000000,
+CMASK_ADDR_LINEAR = 0x00000001,
+CMASK_ADDR_COMPATIBLE = 0x00000002,
+} CmaskAddr;
+
+/*
+ * MemArbMode enum
+ */
+
+typedef enum MemArbMode {
+MEM_ARB_MODE_FIXED = 0x00000000,
+MEM_ARB_MODE_AGE = 0x00000001,
+MEM_ARB_MODE_WEIGHT = 0x00000002,
+MEM_ARB_MODE_BOTH = 0x00000003,
+} MemArbMode;
+
+/*
+ * CBPerfSel enum
+ */
+
+typedef enum CBPerfSel {
+CB_PERF_SEL_NONE = 0x00000000,
+CB_PERF_SEL_BUSY = 0x00000001,
+CB_PERF_SEL_CORE_SCLK_VLD = 0x00000002,
+CB_PERF_SEL_REG_SCLK0_VLD = 0x00000003,
+CB_PERF_SEL_REG_SCLK1_VLD = 0x00000004,
+CB_PERF_SEL_DRAWN_QUAD = 0x00000005,
+CB_PERF_SEL_DRAWN_PIXEL = 0x00000006,
+CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x00000007,
+CB_PERF_SEL_DRAWN_TILE = 0x00000008,
+CB_PERF_SEL_DB_CB_TILE_VALID_READY = 0x00000009,
+CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0x0000000a,
+CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 0x0000000b,
+CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 0x0000000c,
+CB_PERF_SEL_CM_FC_TILE_VALID_READY = 0x0000000d,
+CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 0x0000000e,
+CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 0x0000000f,
+CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 0x00000010,
+CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 0x00000011,
+CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x00000012,
+CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 0x00000013,
+CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 0x00000014,
+CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 0x00000015,
+CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 0x00000016,
+CB_PERF_SEL_LQUAD_NO_TILE = 0x00000017,
+CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 0x00000018,
+CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x00000019,
+CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x0000001a,
+CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x0000001b,
+CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x0000001c,
+CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x0000001d,
+CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR = 0x0000001e,
+CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x0000001f,
+CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x00000020,
+CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK = 0x00000021,
+CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x00000022,
+CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x00000023,
+CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 0x00000024,
+CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 0x00000025,
+CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 0x00000026,
+CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 0x00000027,
+CB_PERF_SEL_FOP_IN_VALID_READY = 0x00000028,
+CB_PERF_SEL_FOP_IN_VALID_READYB = 0x00000029,
+CB_PERF_SEL_FOP_IN_VALIDB_READY = 0x0000002a,
+CB_PERF_SEL_FOP_IN_VALIDB_READYB = 0x0000002b,
+CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 0x0000002c,
+CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 0x0000002d,
+CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 0x0000002e,
+CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x0000002f,
+CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 0x00000030,
+CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 0x00000031,
+CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 0x00000032,
+CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 0x00000033,
+CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 0x00000034,
+CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 0x00000035,
+CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 0x00000036,
+CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 0x00000037,
+CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x00000038,
+CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x00000039,
+CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x0000003a,
+CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x0000003b,
+CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x0000003c,
+CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x0000003d,
+CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x0000003e,
+CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x0000003f,
+CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 0x00000040,
+CB_PERF_SEL_CM_CACHE_HIT = 0x00000041,
+CB_PERF_SEL_CM_CACHE_TAG_MISS = 0x00000042,
+CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 0x00000043,
+CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 0x00000044,
+CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000045,
+CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000046,
+CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000047,
+CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 0x00000048,
+CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 0x00000049,
+CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 0x0000004a,
+CB_PERF_SEL_CM_CACHE_STALL = 0x0000004b,
+CB_PERF_SEL_CM_CACHE_FLUSH = 0x0000004c,
+CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 0x0000004d,
+CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 0x0000004e,
+CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000004f,
+CB_PERF_SEL_FC_CACHE_HIT = 0x00000050,
+CB_PERF_SEL_FC_CACHE_TAG_MISS = 0x00000051,
+CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 0x00000052,
+CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 0x00000053,
+CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000054,
+CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000055,
+CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000056,
+CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 0x00000057,
+CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 0x00000058,
+CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 0x00000059,
+CB_PERF_SEL_FC_CACHE_STALL = 0x0000005a,
+CB_PERF_SEL_FC_CACHE_FLUSH = 0x0000005b,
+CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 0x0000005c,
+CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 0x0000005d,
+CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000005e,
+CB_PERF_SEL_CC_CACHE_HIT = 0x0000005f,
+CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x00000060,
+CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x00000061,
+CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x00000062,
+CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000063,
+CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000064,
+CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000065,
+CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x00000066,
+CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x00000067,
+CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x00000068,
+CB_PERF_SEL_CC_CACHE_STALL = 0x00000069,
+CB_PERF_SEL_CC_CACHE_FLUSH = 0x0000006a,
+CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x0000006b,
+CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x0000006c,
+CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000006d,
+CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x0000006e,
+CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 0x0000006f,
+CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 0x00000070,
+CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 0x00000071,
+CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 0x00000072,
+CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 0x00000073,
+CB_PERF_SEL_CM_MC_WRITE_REQUEST = 0x00000074,
+CB_PERF_SEL_FC_MC_WRITE_REQUEST = 0x00000075,
+CB_PERF_SEL_CC_MC_WRITE_REQUEST = 0x00000076,
+CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000077,
+CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000078,
+CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000079,
+CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 0x0000007a,
+CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 0x0000007b,
+CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 0x0000007c,
+CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 0x0000007d,
+CB_PERF_SEL_CM_MC_READ_REQUEST = 0x0000007e,
+CB_PERF_SEL_FC_MC_READ_REQUEST = 0x0000007f,
+CB_PERF_SEL_CC_MC_READ_REQUEST = 0x00000080,
+CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 0x00000081,
+CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 0x00000082,
+CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x00000083,
+CB_PERF_SEL_CM_TQ_FULL = 0x00000084,
+CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 0x00000085,
+CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 0x00000086,
+CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 0x00000087,
+CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 0x00000088,
+CB_PERF_SEL_FOP_FMASK_RAW_STALL = 0x00000089,
+CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 0x0000008a,
+CB_PERF_SEL_CC_SF_FULL = 0x0000008b,
+CB_PERF_SEL_CC_RB_FULL = 0x0000008c,
+CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 0x0000008d,
+CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 0x0000008e,
+CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 0x0000008f,
+CB_PERF_SEL_EVENT = 0x00000090,
+CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x00000091,
+CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x00000092,
+CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x00000093,
+CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000094,
+CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x00000095,
+CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x00000096,
+CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x00000097,
+CB_PERF_SEL_CC_SURFACE_SYNC = 0x00000098,
+CB_PERF_SEL_CMASK_READ_DATA_0xC = 0x00000099,
+CB_PERF_SEL_CMASK_READ_DATA_0xD = 0x0000009a,
+CB_PERF_SEL_CMASK_READ_DATA_0xE = 0x0000009b,
+CB_PERF_SEL_CMASK_READ_DATA_0xF = 0x0000009c,
+CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 0x0000009d,
+CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 0x0000009e,
+CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 0x0000009f,
+CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 0x000000a0,
+CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 0x000000a1,
+CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0x000000a2,
+CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 0x000000a3,
+CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 0x000000a4,
+CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 0x000000a5,
+CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 0x000000a6,
+CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 0x000000a7,
+CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 0x000000a8,
+CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 0x000000a9,
+CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 0x000000aa,
+CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 0x000000ab,
+CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 0x000000ac,
+CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 0x000000ad,
+CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 0x000000ae,
+CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 0x000000af,
+CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 0x000000b0,
+CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 0x000000b1,
+CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 0x000000b2,
+CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 0x000000b3,
+CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 0x000000b4,
+CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 0x000000b5,
+CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 0x000000b6,
+CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 0x000000b7,
+CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 0x000000b8,
+CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 0x000000b9,
+CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 0x000000ba,
+CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 0x000000bb,
+CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 0x000000bc,
+CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 0x000000bd,
+CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 0x000000be,
+CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 0x000000bf,
+CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 0x000000c0,
+CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 0x000000c1,
+CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 0x000000c2,
+CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 0x000000c3,
+CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 0x000000c4,
+CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 0x000000c5,
+CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 0x000000c6,
+CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 0x000000c7,
+CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 0x000000c8,
+CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 0x000000c9,
+CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 0x000000ca,
+CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 0x000000cb,
+CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 0x000000cc,
+CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 0x000000cd,
+CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 0x000000ce,
+CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 0x000000cf,
+CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 0x000000d0,
+CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 0x000000d1,
+CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 0x000000d2,
+CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 0x000000d3,
+CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 0x000000d4,
+CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 0x000000d5,
+CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 0x000000d6,
+CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 0x000000d7,
+CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0x000000d8,
+CB_PERF_SEL_DRAWN_BUSY = 0x000000d9,
+CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 0x000000da,
+CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 0x000000db,
+CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 0x000000dc,
+CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 0x000000dd,
+CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED = 0x000000de,
+CB_PERF_SEL_FC_SEQUENCER_CLEAR = 0x000000df,
+CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 0x000000e0,
+CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 0x000000e1,
+CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE = 0x000000e2,
+CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL = 0x000000e3,
+CB_PERF_SEL_FC_DOC_IS_STALLED = 0x000000e4,
+CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED = 0x000000e5,
+CB_PERF_SEL_FC_DOC_MRTS_COMBINED = 0x000000e6,
+CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS = 0x000000e7,
+CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT = 0x000000e8,
+CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS = 0x000000e9,
+CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT = 0x000000ea,
+CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL = 0x000000eb,
+CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR = 0x000000ec,
+CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS = 0x000000ed,
+CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS = 0x000000ee,
+CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS = 0x000000ef,
+CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS = 0x000000f0,
+CB_PERF_SEL_FC_DCC_CACHE_HIT = 0x000000f1,
+CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS = 0x000000f2,
+CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS = 0x000000f3,
+CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL = 0x000000f4,
+CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x000000f5,
+CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x000000f6,
+CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x000000f7,
+CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL = 0x000000f8,
+CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL = 0x000000f9,
+CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL = 0x000000fa,
+CB_PERF_SEL_FC_DCC_CACHE_STALL = 0x000000fb,
+CB_PERF_SEL_FC_DCC_CACHE_FLUSH = 0x000000fc,
+CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED = 0x000000fd,
+CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED = 0x000000fe,
+CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 0x000000ff,
+CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT = 0x00000100,
+CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST = 0x00000101,
+CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT = 0x00000102,
+CB_PERF_SEL_FC_MC_DCC_READ_REQUEST = 0x00000103,
+CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT = 0x00000104,
+CB_PERF_SEL_CC_DCC_RDREQ_STALL = 0x00000105,
+CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN = 0x00000106,
+CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT = 0x00000107,
+CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN = 0x00000108,
+CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT = 0x00000109,
+CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR = 0x0000010a,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1 = 0x0000010b,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2 = 0x0000010c,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x0000010d,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1 = 0x0000010e,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1 = 0x0000010f,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2 = 0x00000110,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1 = 0x00000111,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000112,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000113,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1 = 0x00000114,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2 = 0x00000115,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2 = 0x00000116,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2 = 0x00000117,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000118,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1 = 0x00000119,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1 = 0x0000011a,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2 = 0x0000011b,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3 = 0x0000011c,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4 = 0x0000011d,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1 = 0x0000011e,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2 = 0x0000011f,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3 = 0x00000120,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4 = 0x00000121,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1 = 0x00000122,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2 = 0x00000123,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3 = 0x00000124,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4 = 0x00000125,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1 = 0x00000126,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2 = 0x00000127,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3 = 0x00000128,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1 = 0x00000129,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2 = 0x0000012a,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3 = 0x0000012b,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4 = 0x0000012c,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1 = 0x0000012d,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2 = 0x0000012e,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3 = 0x0000012f,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4 = 0x00000130,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1 = 0x00000131,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2 = 0x00000132,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3 = 0x00000133,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4 = 0x00000134,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1 = 0x00000135,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2 = 0x00000136,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3 = 0x00000137,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1 = 0x00000138,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1 = 0x00000139,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1 = 0x0000013a,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1 = 0x0000013b,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1 = 0x0000013c,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1 = 0x0000013d,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1 = 0x0000013e,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1 = 0x0000013f,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2 = 0x00000140,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2 = 0x00000141,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2 = 0x00000142,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2 = 0x00000143,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2 = 0x00000144,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2 = 0x00000145,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2 = 0x00000146,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1 = 0x00000147,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1 = 0x00000148,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1 = 0x00000149,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1 = 0x0000014a,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2 = 0x0000014b,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2 = 0x0000014c,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2 = 0x0000014d,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2 = 0x0000014e,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x0000014f,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000150,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000151,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000152,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000153,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000154,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000155,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1 = 0x00000156,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2 = 0x00000157,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3 = 0x00000158,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4 = 0x00000159,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5 = 0x0000015a,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6 = 0x0000015b,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0 = 0x0000015c,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1 = 0x0000015d,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1 = 0x0000015e,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2 = 0x0000015f,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3 = 0x00000160,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4 = 0x00000161,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5 = 0x00000162,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0 = 0x00000163,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1 = 0x00000164,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1 = 0x00000165,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1 = 0x00000166,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1 = 0x00000167,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1 = 0x00000168,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1 = 0x00000169,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1 = 0x0000016a,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1 = 0x0000016b,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1 = 0x0000016c,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2 = 0x0000016d,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2 = 0x0000016e,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2 = 0x0000016f,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2 = 0x00000170,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2 = 0x00000171,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2 = 0x00000172,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2 = 0x00000173,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1 = 0x00000174,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2 = 0x00000175,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3 = 0x00000176,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4 = 0x00000177,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5 = 0x00000178,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6 = 0x00000179,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7 = 0x0000017a,
+CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED = 0x0000017b,
+CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1 = 0x0000017c,
+CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1 = 0x0000017d,
+CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2 = 0x0000017e,
+CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3 = 0x0000017f,
+CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1 = 0x00000180,
+CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2 = 0x00000181,
+CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3 = 0x00000182,
+CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4 = 0x00000183,
+CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5 = 0x00000184,
+CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1 = 0x00000185,
+CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2 = 0x00000186,
+CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3 = 0x00000187,
+CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4 = 0x00000188,
+CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5 = 0x00000189,
+CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6 = 0x0000018a,
+CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7 = 0x0000018b,
+CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 0x0000018c,
+CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 0x0000018d,
+CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 0x0000018e,
+CB_PERF_SEL_RBP_SPLIT_MICROTILE = 0x0000018f,
+CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK = 0x00000190,
+CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK = 0x00000191,
+CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING = 0x00000192,
+CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS = 0x00000193,
+CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD = 0x00000194,
+} CBPerfSel;
+
+/*
+ * CBPerfOpFilterSel enum
+ */
+
+typedef enum CBPerfOpFilterSel {
+CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x00000000,
+CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x00000001,
+CB_PERF_OP_FILTER_SEL_RESOLVE = 0x00000002,
+CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x00000003,
+CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x00000004,
+CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x00000005,
+} CBPerfOpFilterSel;
+
+/*
+ * CBPerfClearFilterSel enum
+ */
+
+typedef enum CBPerfClearFilterSel {
+CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x00000000,
+CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x00000001,
+} CBPerfClearFilterSel;
+
+/*******************************************************
+ * TC Enums
+ *******************************************************/
+
+/*
+ * TC_OP_MASKS enum
+ */
+
+typedef enum TC_OP_MASKS {
+TC_OP_MASK_FLUSH_DENROM = 0x00000008,
+TC_OP_MASK_64 = 0x00000020,
+TC_OP_MASK_NO_RTN = 0x00000040,
+} TC_OP_MASKS;
+
+/*
+ * TC_OP enum
+ */
+
+typedef enum TC_OP {
+TC_OP_READ = 0x00000000,
+TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001,
+TC_OP_ATOMIC_FMIN_RTN_32 = 0x00000002,
+TC_OP_ATOMIC_FMAX_RTN_32 = 0x00000003,
+TC_OP_RESERVED_FOP_RTN_32_0 = 0x00000004,
+TC_OP_RESERVED_FOP_RTN_32_1 = 0x00000005,
+TC_OP_RESERVED_FOP_RTN_32_2 = 0x00000006,
+TC_OP_ATOMIC_SWAP_RTN_32 = 0x00000007,
+TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008,
+TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009,
+TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a,
+TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b,
+TC_OP_PROBE_FILTER = 0x0000000c,
+TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0x0000000d,
+TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e,
+TC_OP_ATOMIC_ADD_RTN_32 = 0x0000000f,
+TC_OP_ATOMIC_SUB_RTN_32 = 0x00000010,
+TC_OP_ATOMIC_SMIN_RTN_32 = 0x00000011,
+TC_OP_ATOMIC_UMIN_RTN_32 = 0x00000012,
+TC_OP_ATOMIC_SMAX_RTN_32 = 0x00000013,
+TC_OP_ATOMIC_UMAX_RTN_32 = 0x00000014,
+TC_OP_ATOMIC_AND_RTN_32 = 0x00000015,
+TC_OP_ATOMIC_OR_RTN_32 = 0x00000016,
+TC_OP_ATOMIC_XOR_RTN_32 = 0x00000017,
+TC_OP_ATOMIC_INC_RTN_32 = 0x00000018,
+TC_OP_ATOMIC_DEC_RTN_32 = 0x00000019,
+TC_OP_WBINVL1_VOL = 0x0000001a,
+TC_OP_WBINVL1_SD = 0x0000001b,
+TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x0000001c,
+TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x0000001d,
+TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x0000001e,
+TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x0000001f,
+TC_OP_WRITE = 0x00000020,
+TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021,
+TC_OP_ATOMIC_FMIN_RTN_64 = 0x00000022,
+TC_OP_ATOMIC_FMAX_RTN_64 = 0x00000023,
+TC_OP_RESERVED_FOP_RTN_64_0 = 0x00000024,
+TC_OP_RESERVED_FOP_RTN_64_1 = 0x00000025,
+TC_OP_RESERVED_FOP_RTN_64_2 = 0x00000026,
+TC_OP_ATOMIC_SWAP_RTN_64 = 0x00000027,
+TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028,
+TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029,
+TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a,
+TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b,
+TC_OP_WBINVL2_SD = 0x0000002c,
+TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x0000002d,
+TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x0000002e,
+TC_OP_ATOMIC_ADD_RTN_64 = 0x0000002f,
+TC_OP_ATOMIC_SUB_RTN_64 = 0x00000030,
+TC_OP_ATOMIC_SMIN_RTN_64 = 0x00000031,
+TC_OP_ATOMIC_UMIN_RTN_64 = 0x00000032,
+TC_OP_ATOMIC_SMAX_RTN_64 = 0x00000033,
+TC_OP_ATOMIC_UMAX_RTN_64 = 0x00000034,
+TC_OP_ATOMIC_AND_RTN_64 = 0x00000035,
+TC_OP_ATOMIC_OR_RTN_64 = 0x00000036,
+TC_OP_ATOMIC_XOR_RTN_64 = 0x00000037,
+TC_OP_ATOMIC_INC_RTN_64 = 0x00000038,
+TC_OP_ATOMIC_DEC_RTN_64 = 0x00000039,
+TC_OP_WBL2_NC = 0x0000003a,
+TC_OP_WBL2_WC = 0x0000003b,
+TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x0000003c,
+TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x0000003d,
+TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x0000003e,
+TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x0000003f,
+TC_OP_WBINVL1 = 0x00000040,
+TC_OP_ATOMIC_FCMPSWAP_32 = 0x00000041,
+TC_OP_ATOMIC_FMIN_32 = 0x00000042,
+TC_OP_ATOMIC_FMAX_32 = 0x00000043,
+TC_OP_RESERVED_FOP_32_0 = 0x00000044,
+TC_OP_RESERVED_FOP_32_1 = 0x00000045,
+TC_OP_RESERVED_FOP_32_2 = 0x00000046,
+TC_OP_ATOMIC_SWAP_32 = 0x00000047,
+TC_OP_ATOMIC_CMPSWAP_32 = 0x00000048,
+TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049,
+TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a,
+TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b,
+TC_OP_INV_METADATA = 0x0000004c,
+TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 0x0000004d,
+TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x0000004e,
+TC_OP_ATOMIC_ADD_32 = 0x0000004f,
+TC_OP_ATOMIC_SUB_32 = 0x00000050,
+TC_OP_ATOMIC_SMIN_32 = 0x00000051,
+TC_OP_ATOMIC_UMIN_32 = 0x00000052,
+TC_OP_ATOMIC_SMAX_32 = 0x00000053,
+TC_OP_ATOMIC_UMAX_32 = 0x00000054,
+TC_OP_ATOMIC_AND_32 = 0x00000055,
+TC_OP_ATOMIC_OR_32 = 0x00000056,
+TC_OP_ATOMIC_XOR_32 = 0x00000057,
+TC_OP_ATOMIC_INC_32 = 0x00000058,
+TC_OP_ATOMIC_DEC_32 = 0x00000059,
+TC_OP_INVL2_NC = 0x0000005a,
+TC_OP_NOP_RTN0 = 0x0000005b,
+TC_OP_RESERVED_NON_FLOAT_32_1 = 0x0000005c,
+TC_OP_RESERVED_NON_FLOAT_32_2 = 0x0000005d,
+TC_OP_RESERVED_NON_FLOAT_32_3 = 0x0000005e,
+TC_OP_RESERVED_NON_FLOAT_32_4 = 0x0000005f,
+TC_OP_WBINVL2 = 0x00000060,
+TC_OP_ATOMIC_FCMPSWAP_64 = 0x00000061,
+TC_OP_ATOMIC_FMIN_64 = 0x00000062,
+TC_OP_ATOMIC_FMAX_64 = 0x00000063,
+TC_OP_RESERVED_FOP_64_0 = 0x00000064,
+TC_OP_RESERVED_FOP_64_1 = 0x00000065,
+TC_OP_RESERVED_FOP_64_2 = 0x00000066,
+TC_OP_ATOMIC_SWAP_64 = 0x00000067,
+TC_OP_ATOMIC_CMPSWAP_64 = 0x00000068,
+TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069,
+TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a,
+TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b,
+TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x0000006c,
+TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x0000006d,
+TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x0000006e,
+TC_OP_ATOMIC_ADD_64 = 0x0000006f,
+TC_OP_ATOMIC_SUB_64 = 0x00000070,
+TC_OP_ATOMIC_SMIN_64 = 0x00000071,
+TC_OP_ATOMIC_UMIN_64 = 0x00000072,
+TC_OP_ATOMIC_SMAX_64 = 0x00000073,
+TC_OP_ATOMIC_UMAX_64 = 0x00000074,
+TC_OP_ATOMIC_AND_64 = 0x00000075,
+TC_OP_ATOMIC_OR_64 = 0x00000076,
+TC_OP_ATOMIC_XOR_64 = 0x00000077,
+TC_OP_ATOMIC_INC_64 = 0x00000078,
+TC_OP_ATOMIC_DEC_64 = 0x00000079,
+TC_OP_WBINVL2_NC = 0x0000007a,
+TC_OP_NOP_ACK = 0x0000007b,
+TC_OP_RESERVED_NON_FLOAT_64_1 = 0x0000007c,
+TC_OP_RESERVED_NON_FLOAT_64_2 = 0x0000007d,
+TC_OP_RESERVED_NON_FLOAT_64_3 = 0x0000007e,
+TC_OP_RESERVED_NON_FLOAT_64_4 = 0x0000007f,
+} TC_OP;
+
+/*
+ * TC_CHUB_REQ_CREDITS_ENUM enum
+ */
+
+typedef enum TC_CHUB_REQ_CREDITS_ENUM {
+TC_CHUB_REQ_CREDITS = 0x00000010,
+} TC_CHUB_REQ_CREDITS_ENUM;
+
+/*
+ * CHUB_TC_RET_CREDITS_ENUM enum
+ */
+
+typedef enum CHUB_TC_RET_CREDITS_ENUM {
+CHUB_TC_RET_CREDITS = 0x00000020,
+} CHUB_TC_RET_CREDITS_ENUM;
+
+/*
+ * TC_NACKS enum
+ */
+
+typedef enum TC_NACKS {
+TC_NACK_NO_FAULT = 0x00000000,
+TC_NACK_PAGE_FAULT = 0x00000001,
+TC_NACK_PROTECTION_FAULT = 0x00000002,
+TC_NACK_DATA_ERROR = 0x00000003,
+} TC_NACKS;
+
+/*
+ * TC_EA_CID enum
+ */
+
+typedef enum TC_EA_CID {
+TC_EA_CID_RT = 0x00000000,
+TC_EA_CID_FMASK = 0x00000001,
+TC_EA_CID_DCC = 0x00000002,
+TC_EA_CID_TCPMETA = 0x00000003,
+TC_EA_CID_Z = 0x00000004,
+TC_EA_CID_STENCIL = 0x00000005,
+TC_EA_CID_HTILE = 0x00000006,
+TC_EA_CID_MISC = 0x00000007,
+TC_EA_CID_TCP = 0x00000008,
+TC_EA_CID_SQC = 0x00000009,
+TC_EA_CID_CPF = 0x0000000a,
+TC_EA_CID_CPG = 0x0000000b,
+TC_EA_CID_IA = 0x0000000c,
+TC_EA_CID_WD = 0x0000000d,
+TC_EA_CID_PA = 0x0000000e,
+TC_EA_CID_UTCL2_TPI = 0x0000000f,
+} TC_EA_CID;
+
+/*******************************************************
+ * SPI Enums
+ *******************************************************/
+
+/*
+ * SPI_SAMPLE_CNTL enum
+ */
+
+typedef enum SPI_SAMPLE_CNTL {
+CENTROIDS_ONLY = 0x00000000,
+CENTERS_ONLY = 0x00000001,
+CENTROIDS_AND_CENTERS = 0x00000002,
+UNDEF = 0x00000003,
+} SPI_SAMPLE_CNTL;
+
+/*
+ * SPI_FOG_MODE enum
+ */
+
+typedef enum SPI_FOG_MODE {
+SPI_FOG_NONE = 0x00000000,
+SPI_FOG_EXP = 0x00000001,
+SPI_FOG_EXP2 = 0x00000002,
+SPI_FOG_LINEAR = 0x00000003,
+} SPI_FOG_MODE;
+
+/*
+ * SPI_PNT_SPRITE_OVERRIDE enum
+ */
+
+typedef enum SPI_PNT_SPRITE_OVERRIDE {
+SPI_PNT_SPRITE_SEL_0 = 0x00000000,
+SPI_PNT_SPRITE_SEL_1 = 0x00000001,
+SPI_PNT_SPRITE_SEL_S = 0x00000002,
+SPI_PNT_SPRITE_SEL_T = 0x00000003,
+SPI_PNT_SPRITE_SEL_NONE = 0x00000004,
+} SPI_PNT_SPRITE_OVERRIDE;
+
+/*
+ * SPI_PERFCNT_SEL enum
+ */
+
+typedef enum SPI_PERFCNT_SEL {
+SPI_PERF_VS_WINDOW_VALID = 0x00000000,
+SPI_PERF_VS_BUSY = 0x00000001,
+SPI_PERF_VS_FIRST_WAVE = 0x00000002,
+SPI_PERF_VS_LAST_WAVE = 0x00000003,
+SPI_PERF_VS_LSHS_DEALLOC = 0x00000004,
+SPI_PERF_VS_PC_STALL = 0x00000005,
+SPI_PERF_VS_POS0_STALL = 0x00000006,
+SPI_PERF_VS_POS1_STALL = 0x00000007,
+SPI_PERF_VS_CRAWLER_STALL = 0x00000008,
+SPI_PERF_VS_EVENT_WAVE = 0x00000009,
+SPI_PERF_VS_WAVE = 0x0000000a,
+SPI_PERF_VS_PERS_UPD_FULL0 = 0x0000000b,
+SPI_PERF_VS_PERS_UPD_FULL1 = 0x0000000c,
+SPI_PERF_VS_LATE_ALLOC_FULL = 0x0000000d,
+SPI_PERF_VS_FIRST_SUBGRP = 0x0000000e,
+SPI_PERF_VS_LAST_SUBGRP = 0x0000000f,
+SPI_PERF_GS_WINDOW_VALID = 0x00000010,
+SPI_PERF_GS_BUSY = 0x00000011,
+SPI_PERF_GS_CRAWLER_STALL = 0x00000012,
+SPI_PERF_GS_EVENT_WAVE = 0x00000013,
+SPI_PERF_GS_WAVE = 0x00000014,
+SPI_PERF_GS_PERS_UPD_FULL0 = 0x00000015,
+SPI_PERF_GS_PERS_UPD_FULL1 = 0x00000016,
+SPI_PERF_GS_FIRST_SUBGRP = 0x00000017,
+SPI_PERF_GS_LAST_SUBGRP = 0x00000018,
+SPI_PERF_ES_WINDOW_VALID = 0x00000019,
+SPI_PERF_ES_BUSY = 0x0000001a,
+SPI_PERF_ES_CRAWLER_STALL = 0x0000001b,
+SPI_PERF_ES_FIRST_WAVE = 0x0000001c,
+SPI_PERF_ES_LAST_WAVE = 0x0000001d,
+SPI_PERF_ES_LSHS_DEALLOC = 0x0000001e,
+SPI_PERF_ES_EVENT_WAVE = 0x0000001f,
+SPI_PERF_ES_WAVE = 0x00000020,
+SPI_PERF_ES_PERS_UPD_FULL0 = 0x00000021,
+SPI_PERF_ES_PERS_UPD_FULL1 = 0x00000022,
+SPI_PERF_ES_FIRST_SUBGRP = 0x00000023,
+SPI_PERF_ES_LAST_SUBGRP = 0x00000024,
+SPI_PERF_HS_WINDOW_VALID = 0x00000025,
+SPI_PERF_HS_BUSY = 0x00000026,
+SPI_PERF_HS_CRAWLER_STALL = 0x00000027,
+SPI_PERF_HS_FIRST_WAVE = 0x00000028,
+SPI_PERF_HS_LAST_WAVE = 0x00000029,
+SPI_PERF_HS_LSHS_DEALLOC = 0x0000002a,
+SPI_PERF_HS_EVENT_WAVE = 0x0000002b,
+SPI_PERF_HS_WAVE = 0x0000002c,
+SPI_PERF_HS_PERS_UPD_FULL0 = 0x0000002d,
+SPI_PERF_HS_PERS_UPD_FULL1 = 0x0000002e,
+SPI_PERF_LS_WINDOW_VALID = 0x0000002f,
+SPI_PERF_LS_BUSY = 0x00000030,
+SPI_PERF_LS_CRAWLER_STALL = 0x00000031,
+SPI_PERF_LS_FIRST_WAVE = 0x00000032,
+SPI_PERF_LS_LAST_WAVE = 0x00000033,
+SPI_PERF_OFFCHIP_LDS_STALL_LS = 0x00000034,
+SPI_PERF_LS_EVENT_WAVE = 0x00000035,
+SPI_PERF_LS_WAVE = 0x00000036,
+SPI_PERF_LS_PERS_UPD_FULL0 = 0x00000037,
+SPI_PERF_LS_PERS_UPD_FULL1 = 0x00000038,
+SPI_PERF_CSG_WINDOW_VALID = 0x00000039,
+SPI_PERF_CSG_BUSY = 0x0000003a,
+SPI_PERF_CSG_NUM_THREADGROUPS = 0x0000003b,
+SPI_PERF_CSG_CRAWLER_STALL = 0x0000003c,
+SPI_PERF_CSG_EVENT_WAVE = 0x0000003d,
+SPI_PERF_CSG_WAVE = 0x0000003e,
+SPI_PERF_CSN_WINDOW_VALID = 0x0000003f,
+SPI_PERF_CSN_BUSY = 0x00000040,
+SPI_PERF_CSN_NUM_THREADGROUPS = 0x00000041,
+SPI_PERF_CSN_CRAWLER_STALL = 0x00000042,
+SPI_PERF_CSN_EVENT_WAVE = 0x00000043,
+SPI_PERF_CSN_WAVE = 0x00000044,
+SPI_PERF_PS_CTL_WINDOW_VALID = 0x00000045,
+SPI_PERF_PS_CTL_BUSY = 0x00000046,
+SPI_PERF_PS_CTL_ACTIVE = 0x00000047,
+SPI_PERF_PS_CTL_DEALLOC_BIN0 = 0x00000048,
+SPI_PERF_PS_CTL_FPOS_BIN1_STALL = 0x00000049,
+SPI_PERF_PS_CTL_EVENT_WAVE = 0x0000004a,
+SPI_PERF_PS_CTL_WAVE = 0x0000004b,
+SPI_PERF_PS_CTL_OPT_WAVE = 0x0000004c,
+SPI_PERF_PS_CTL_PASS_BIN0 = 0x0000004d,
+SPI_PERF_PS_CTL_PASS_BIN1 = 0x0000004e,
+SPI_PERF_PS_CTL_FPOS_BIN2 = 0x0000004f,
+SPI_PERF_PS_CTL_PRIM_BIN0 = 0x00000050,
+SPI_PERF_PS_CTL_PRIM_BIN1 = 0x00000051,
+SPI_PERF_PS_CTL_CNF_BIN2 = 0x00000052,
+SPI_PERF_PS_CTL_CNF_BIN3 = 0x00000053,
+SPI_PERF_PS_CTL_CRAWLER_STALL = 0x00000054,
+SPI_PERF_PS_CTL_LDS_RES_FULL = 0x00000055,
+SPI_PERF_PS_PERS_UPD_FULL0 = 0x00000056,
+SPI_PERF_PS_PERS_UPD_FULL1 = 0x00000057,
+SPI_PERF_PIX_ALLOC_PEND_CNT = 0x00000058,
+SPI_PERF_PIX_ALLOC_SCB_STALL = 0x00000059,
+SPI_PERF_PIX_ALLOC_DB0_STALL = 0x0000005a,
+SPI_PERF_PIX_ALLOC_DB1_STALL = 0x0000005b,
+SPI_PERF_PIX_ALLOC_DB2_STALL = 0x0000005c,
+SPI_PERF_PIX_ALLOC_DB3_STALL = 0x0000005d,
+SPI_PERF_LDS0_PC_VALID = 0x0000005e,
+SPI_PERF_LDS1_PC_VALID = 0x0000005f,
+SPI_PERF_RA_PIPE_REQ_BIN2 = 0x00000060,
+SPI_PERF_RA_TASK_REQ_BIN3 = 0x00000061,
+SPI_PERF_RA_WR_CTL_FULL = 0x00000062,
+SPI_PERF_RA_REQ_NO_ALLOC = 0x00000063,
+SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x00000064,
+SPI_PERF_RA_REQ_NO_ALLOC_VS = 0x00000065,
+SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x00000066,
+SPI_PERF_RA_REQ_NO_ALLOC_ES = 0x00000067,
+SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x00000068,
+SPI_PERF_RA_REQ_NO_ALLOC_LS = 0x00000069,
+SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x0000006a,
+SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x0000006b,
+SPI_PERF_RA_RES_STALL_PS = 0x0000006c,
+SPI_PERF_RA_RES_STALL_VS = 0x0000006d,
+SPI_PERF_RA_RES_STALL_GS = 0x0000006e,
+SPI_PERF_RA_RES_STALL_ES = 0x0000006f,
+SPI_PERF_RA_RES_STALL_HS = 0x00000070,
+SPI_PERF_RA_RES_STALL_LS = 0x00000071,
+SPI_PERF_RA_RES_STALL_CSG = 0x00000072,
+SPI_PERF_RA_RES_STALL_CSN = 0x00000073,
+SPI_PERF_RA_TMP_STALL_PS = 0x00000074,
+SPI_PERF_RA_TMP_STALL_VS = 0x00000075,
+SPI_PERF_RA_TMP_STALL_GS = 0x00000076,
+SPI_PERF_RA_TMP_STALL_ES = 0x00000077,
+SPI_PERF_RA_TMP_STALL_HS = 0x00000078,
+SPI_PERF_RA_TMP_STALL_LS = 0x00000079,
+SPI_PERF_RA_TMP_STALL_CSG = 0x0000007a,
+SPI_PERF_RA_TMP_STALL_CSN = 0x0000007b,
+SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x0000007c,
+SPI_PERF_RA_WAVE_SIMD_FULL_VS = 0x0000007d,
+SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x0000007e,
+SPI_PERF_RA_WAVE_SIMD_FULL_ES = 0x0000007f,
+SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x00000080,
+SPI_PERF_RA_WAVE_SIMD_FULL_LS = 0x00000081,
+SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x00000082,
+SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x00000083,
+SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x00000084,
+SPI_PERF_RA_VGPR_SIMD_FULL_VS = 0x00000085,
+SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x00000086,
+SPI_PERF_RA_VGPR_SIMD_FULL_ES = 0x00000087,
+SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x00000088,
+SPI_PERF_RA_VGPR_SIMD_FULL_LS = 0x00000089,
+SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x0000008a,
+SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x0000008b,
+SPI_PERF_RA_SGPR_SIMD_FULL_PS = 0x0000008c,
+SPI_PERF_RA_SGPR_SIMD_FULL_VS = 0x0000008d,
+SPI_PERF_RA_SGPR_SIMD_FULL_GS = 0x0000008e,
+SPI_PERF_RA_SGPR_SIMD_FULL_ES = 0x0000008f,
+SPI_PERF_RA_SGPR_SIMD_FULL_HS = 0x00000090,
+SPI_PERF_RA_SGPR_SIMD_FULL_LS = 0x00000091,
+SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 0x00000092,
+SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 0x00000093,
+SPI_PERF_RA_LDS_CU_FULL_PS = 0x00000094,
+SPI_PERF_RA_LDS_CU_FULL_LS = 0x00000095,
+SPI_PERF_RA_LDS_CU_FULL_ES = 0x00000096,
+SPI_PERF_RA_LDS_CU_FULL_CSG = 0x00000097,
+SPI_PERF_RA_LDS_CU_FULL_CSN = 0x00000098,
+SPI_PERF_RA_BAR_CU_FULL_HS = 0x00000099,
+SPI_PERF_RA_BAR_CU_FULL_CSG = 0x0000009a,
+SPI_PERF_RA_BAR_CU_FULL_CSN = 0x0000009b,
+SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x0000009c,
+SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x0000009d,
+SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x0000009e,
+SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x0000009f,
+SPI_PERF_RA_WVLIM_STALL_PS = 0x000000a0,
+SPI_PERF_RA_WVLIM_STALL_VS = 0x000000a1,
+SPI_PERF_RA_WVLIM_STALL_GS = 0x000000a2,
+SPI_PERF_RA_WVLIM_STALL_ES = 0x000000a3,
+SPI_PERF_RA_WVLIM_STALL_HS = 0x000000a4,
+SPI_PERF_RA_WVLIM_STALL_LS = 0x000000a5,
+SPI_PERF_RA_WVLIM_STALL_CSG = 0x000000a6,
+SPI_PERF_RA_WVLIM_STALL_CSN = 0x000000a7,
+SPI_PERF_RA_PS_LOCK_NA = 0x000000a8,
+SPI_PERF_RA_VS_LOCK = 0x000000a9,
+SPI_PERF_RA_GS_LOCK = 0x000000aa,
+SPI_PERF_RA_ES_LOCK = 0x000000ab,
+SPI_PERF_RA_HS_LOCK = 0x000000ac,
+SPI_PERF_RA_LS_LOCK = 0x000000ad,
+SPI_PERF_RA_CSG_LOCK = 0x000000ae,
+SPI_PERF_RA_CSN_LOCK = 0x000000af,
+SPI_PERF_RA_RSV_UPD = 0x000000b0,
+SPI_PERF_EXP_ARB_COL_CNT = 0x000000b1,
+SPI_PERF_EXP_ARB_PAR_CNT = 0x000000b2,
+SPI_PERF_EXP_ARB_POS_CNT = 0x000000b3,
+SPI_PERF_EXP_ARB_GDS_CNT = 0x000000b4,
+SPI_PERF_CLKGATE_BUSY_STALL = 0x000000b5,
+SPI_PERF_CLKGATE_ACTIVE_STALL = 0x000000b6,
+SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 0x000000b7,
+SPI_PERF_CLKGATE_CGTT_DYN_ON = 0x000000b8,
+SPI_PERF_CLKGATE_CGTT_REG_ON = 0x000000b9,
+SPI_PERF_NUM_VS_POS_EXPORTS = 0x000000ba,
+SPI_PERF_NUM_VS_PARAM_EXPORTS = 0x000000bb,
+SPI_PERF_NUM_PS_COL_EXPORTS = 0x000000bc,
+SPI_PERF_ES_GRP_FIFO_FULL = 0x000000bd,
+SPI_PERF_GS_GRP_FIFO_FULL = 0x000000be,
+SPI_PERF_HS_GRP_FIFO_FULL = 0x000000bf,
+SPI_PERF_LS_GRP_FIFO_FULL = 0x000000c0,
+SPI_PERF_VS_ALLOC_CNT = 0x000000c1,
+SPI_PERF_VS_LATE_ALLOC_ACCUM = 0x000000c2,
+SPI_PERF_PC_ALLOC_CNT = 0x000000c3,
+SPI_PERF_PC_ALLOC_ACCUM = 0x000000c4,
+} SPI_PERFCNT_SEL;
+
+/*
+ * SPI_SHADER_FORMAT enum
+ */
+
+typedef enum SPI_SHADER_FORMAT {
+SPI_SHADER_NONE = 0x00000000,
+SPI_SHADER_1COMP = 0x00000001,
+SPI_SHADER_2COMP = 0x00000002,
+SPI_SHADER_4COMPRESS = 0x00000003,
+SPI_SHADER_4COMP = 0x00000004,
+} SPI_SHADER_FORMAT;
+
+/*
+ * SPI_SHADER_EX_FORMAT enum
+ */
+
+typedef enum SPI_SHADER_EX_FORMAT {
+SPI_SHADER_ZERO = 0x00000000,
+SPI_SHADER_32_R = 0x00000001,
+SPI_SHADER_32_GR = 0x00000002,
+SPI_SHADER_32_AR = 0x00000003,
+SPI_SHADER_FP16_ABGR = 0x00000004,
+SPI_SHADER_UNORM16_ABGR = 0x00000005,
+SPI_SHADER_SNORM16_ABGR = 0x00000006,
+SPI_SHADER_UINT16_ABGR = 0x00000007,
+SPI_SHADER_SINT16_ABGR = 0x00000008,
+SPI_SHADER_32_ABGR = 0x00000009,
+} SPI_SHADER_EX_FORMAT;
+
+/*
+ * CLKGATE_SM_MODE enum
+ */
+
+typedef enum CLKGATE_SM_MODE {
+ON_SEQ = 0x00000000,
+OFF_SEQ = 0x00000001,
+PROG_SEQ = 0x00000002,
+READ_SEQ = 0x00000003,
+SM_MODE_RESERVED = 0x00000004,
+} CLKGATE_SM_MODE;
+
+/*
+ * CLKGATE_BASE_MODE enum
+ */
+
+typedef enum CLKGATE_BASE_MODE {
+MULT_8 = 0x00000000,
+MULT_16 = 0x00000001,
+} CLKGATE_BASE_MODE;
+
+/*******************************************************
+ * SQ Enums
+ *******************************************************/
+
+/*
+ * SQ_TEX_CLAMP enum
+ */
+
+typedef enum SQ_TEX_CLAMP {
+SQ_TEX_WRAP = 0x00000000,
+SQ_TEX_MIRROR = 0x00000001,
+SQ_TEX_CLAMP_LAST_TEXEL = 0x00000002,
+SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x00000003,
+SQ_TEX_CLAMP_HALF_BORDER = 0x00000004,
+SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x00000005,
+SQ_TEX_CLAMP_BORDER = 0x00000006,
+SQ_TEX_MIRROR_ONCE_BORDER = 0x00000007,
+} SQ_TEX_CLAMP;
+
+/*
+ * SQ_TEX_XY_FILTER enum
+ */
+
+typedef enum SQ_TEX_XY_FILTER {
+SQ_TEX_XY_FILTER_POINT = 0x00000000,
+SQ_TEX_XY_FILTER_BILINEAR = 0x00000001,
+SQ_TEX_XY_FILTER_ANISO_POINT = 0x00000002,
+SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x00000003,
+} SQ_TEX_XY_FILTER;
+
+/*
+ * SQ_TEX_Z_FILTER enum
+ */
+
+typedef enum SQ_TEX_Z_FILTER {
+SQ_TEX_Z_FILTER_NONE = 0x00000000,
+SQ_TEX_Z_FILTER_POINT = 0x00000001,
+SQ_TEX_Z_FILTER_LINEAR = 0x00000002,
+} SQ_TEX_Z_FILTER;
+
+/*
+ * SQ_TEX_MIP_FILTER enum
+ */
+
+typedef enum SQ_TEX_MIP_FILTER {
+SQ_TEX_MIP_FILTER_NONE = 0x00000000,
+SQ_TEX_MIP_FILTER_POINT = 0x00000001,
+SQ_TEX_MIP_FILTER_LINEAR = 0x00000002,
+SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 0x00000003,
+} SQ_TEX_MIP_FILTER;
+
+/*
+ * SQ_TEX_ANISO_RATIO enum
+ */
+
+typedef enum SQ_TEX_ANISO_RATIO {
+SQ_TEX_ANISO_RATIO_1 = 0x00000000,
+SQ_TEX_ANISO_RATIO_2 = 0x00000001,
+SQ_TEX_ANISO_RATIO_4 = 0x00000002,
+SQ_TEX_ANISO_RATIO_8 = 0x00000003,
+SQ_TEX_ANISO_RATIO_16 = 0x00000004,
+} SQ_TEX_ANISO_RATIO;
+
+/*
+ * SQ_TEX_DEPTH_COMPARE enum
+ */
+
+typedef enum SQ_TEX_DEPTH_COMPARE {
+SQ_TEX_DEPTH_COMPARE_NEVER = 0x00000000,
+SQ_TEX_DEPTH_COMPARE_LESS = 0x00000001,
+SQ_TEX_DEPTH_COMPARE_EQUAL = 0x00000002,
+SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x00000003,
+SQ_TEX_DEPTH_COMPARE_GREATER = 0x00000004,
+SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x00000005,
+SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x00000006,
+SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x00000007,
+} SQ_TEX_DEPTH_COMPARE;
+
+/*
+ * SQ_TEX_BORDER_COLOR enum
+ */
+
+typedef enum SQ_TEX_BORDER_COLOR {
+SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00000000,
+SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x00000001,
+SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x00000002,
+SQ_TEX_BORDER_COLOR_REGISTER = 0x00000003,
+} SQ_TEX_BORDER_COLOR;
+
+/*
+ * SQ_RSRC_BUF_TYPE enum
+ */
+
+typedef enum SQ_RSRC_BUF_TYPE {
+SQ_RSRC_BUF = 0x00000000,
+SQ_RSRC_BUF_RSVD_1 = 0x00000001,
+SQ_RSRC_BUF_RSVD_2 = 0x00000002,
+SQ_RSRC_BUF_RSVD_3 = 0x00000003,
+} SQ_RSRC_BUF_TYPE;
+
+/*
+ * SQ_RSRC_IMG_TYPE enum
+ */
+
+typedef enum SQ_RSRC_IMG_TYPE {
+SQ_RSRC_IMG_RSVD_0 = 0x00000000,
+SQ_RSRC_IMG_RSVD_1 = 0x00000001,
+SQ_RSRC_IMG_RSVD_2 = 0x00000002,
+SQ_RSRC_IMG_RSVD_3 = 0x00000003,
+SQ_RSRC_IMG_RSVD_4 = 0x00000004,
+SQ_RSRC_IMG_RSVD_5 = 0x00000005,
+SQ_RSRC_IMG_RSVD_6 = 0x00000006,
+SQ_RSRC_IMG_RSVD_7 = 0x00000007,
+SQ_RSRC_IMG_1D = 0x00000008,
+SQ_RSRC_IMG_2D = 0x00000009,
+SQ_RSRC_IMG_3D = 0x0000000a,
+SQ_RSRC_IMG_CUBE = 0x0000000b,
+SQ_RSRC_IMG_1D_ARRAY = 0x0000000c,
+SQ_RSRC_IMG_2D_ARRAY = 0x0000000d,
+SQ_RSRC_IMG_2D_MSAA = 0x0000000e,
+SQ_RSRC_IMG_2D_MSAA_ARRAY = 0x0000000f,
+} SQ_RSRC_IMG_TYPE;
+
+/*
+ * SQ_RSRC_FLAT_TYPE enum
+ */
+
+typedef enum SQ_RSRC_FLAT_TYPE {
+SQ_RSRC_FLAT_RSVD_0 = 0x00000000,
+SQ_RSRC_FLAT = 0x00000001,
+SQ_RSRC_FLAT_RSVD_2 = 0x00000002,
+SQ_RSRC_FLAT_RSVD_3 = 0x00000003,
+} SQ_RSRC_FLAT_TYPE;
+
+/*
+ * SQ_IMG_FILTER_TYPE enum
+ */
+
+typedef enum SQ_IMG_FILTER_TYPE {
+SQ_IMG_FILTER_MODE_BLEND = 0x00000000,
+SQ_IMG_FILTER_MODE_MIN = 0x00000001,
+SQ_IMG_FILTER_MODE_MAX = 0x00000002,
+} SQ_IMG_FILTER_TYPE;
+
+/*
+ * SQ_SEL_XYZW01 enum
+ */
+
+typedef enum SQ_SEL_XYZW01 {
+SQ_SEL_0 = 0x00000000,
+SQ_SEL_1 = 0x00000001,
+SQ_SEL_RESERVED_0 = 0x00000002,
+SQ_SEL_RESERVED_1 = 0x00000003,
+SQ_SEL_X = 0x00000004,
+SQ_SEL_Y = 0x00000005,
+SQ_SEL_Z = 0x00000006,
+SQ_SEL_W = 0x00000007,
+} SQ_SEL_XYZW01;
+
+/*
+ * SQ_WAVE_TYPE enum
+ */
+
+typedef enum SQ_WAVE_TYPE {
+SQ_WAVE_TYPE_PS = 0x00000000,
+SQ_WAVE_TYPE_VS = 0x00000001,
+SQ_WAVE_TYPE_GS = 0x00000002,
+SQ_WAVE_TYPE_ES = 0x00000003,
+SQ_WAVE_TYPE_HS = 0x00000004,
+SQ_WAVE_TYPE_LS = 0x00000005,
+SQ_WAVE_TYPE_CS = 0x00000006,
+SQ_WAVE_TYPE_PS1 = 0x00000007,
+} SQ_WAVE_TYPE;
+
+/*
+ * SQ_THREAD_TRACE_TOKEN_TYPE enum
+ */
+
+typedef enum SQ_THREAD_TRACE_TOKEN_TYPE {
+SQ_THREAD_TRACE_TOKEN_MISC = 0x00000000,
+SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 0x00000001,
+SQ_THREAD_TRACE_TOKEN_REG = 0x00000002,
+SQ_THREAD_TRACE_TOKEN_WAVE_START = 0x00000003,
+SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC = 0x00000004,
+SQ_THREAD_TRACE_TOKEN_REG_CSPRIV = 0x00000005,
+SQ_THREAD_TRACE_TOKEN_WAVE_END = 0x00000006,
+SQ_THREAD_TRACE_TOKEN_EVENT = 0x00000007,
+SQ_THREAD_TRACE_TOKEN_EVENT_CS = 0x00000008,
+SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 0x00000009,
+SQ_THREAD_TRACE_TOKEN_INST = 0x0000000a,
+SQ_THREAD_TRACE_TOKEN_INST_PC = 0x0000000b,
+SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 0x0000000c,
+SQ_THREAD_TRACE_TOKEN_ISSUE = 0x0000000d,
+SQ_THREAD_TRACE_TOKEN_PERF = 0x0000000e,
+SQ_THREAD_TRACE_TOKEN_REG_CS = 0x0000000f,
+} SQ_THREAD_TRACE_TOKEN_TYPE;
+
+/*
+ * SQ_THREAD_TRACE_MISC_TOKEN_TYPE enum
+ */
+
+typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE {
+SQ_THREAD_TRACE_MISC_TOKEN_TIME = 0x00000000,
+SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET = 0x00000001,
+SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 0x00000002,
+SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC = 0x00000003,
+SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN = 0x00000004,
+SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END = 0x00000005,
+SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX = 0x00000006,
+SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN = 0x00000007,
+} SQ_THREAD_TRACE_MISC_TOKEN_TYPE;
+
+/*
+ * SQ_THREAD_TRACE_INST_TYPE enum
+ */
+
+typedef enum SQ_THREAD_TRACE_INST_TYPE {
+SQ_THREAD_TRACE_INST_TYPE_SMEM_RD = 0x00000000,
+SQ_THREAD_TRACE_INST_TYPE_SALU_32 = 0x00000001,
+SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 0x00000002,
+SQ_THREAD_TRACE_INST_TYPE_VMEM_WR = 0x00000003,
+SQ_THREAD_TRACE_INST_TYPE_FLAT_WR = 0x00000004,
+SQ_THREAD_TRACE_INST_TYPE_VALU_32 = 0x00000005,
+SQ_THREAD_TRACE_INST_TYPE_LDS = 0x00000006,
+SQ_THREAD_TRACE_INST_TYPE_PC = 0x00000007,
+SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 0x00000008,
+SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 0x00000009,
+SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 0x0000000a,
+SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 0x0000000b,
+SQ_THREAD_TRACE_INST_TYPE_JUMP = 0x0000000c,
+SQ_THREAD_TRACE_INST_TYPE_NEXT = 0x0000000d,
+SQ_THREAD_TRACE_INST_TYPE_FLAT_RD = 0x0000000e,
+SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 0x0000000f,
+SQ_THREAD_TRACE_INST_TYPE_SMEM_WR = 0x00000010,
+SQ_THREAD_TRACE_INST_TYPE_SALU_64 = 0x00000011,
+SQ_THREAD_TRACE_INST_TYPE_VALU_64 = 0x00000012,
+SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY = 0x00000013,
+SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY = 0x00000014,
+SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY = 0x00000015,
+SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY = 0x00000016,
+SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY = 0x00000017,
+SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY = 0x00000018,
+SQ_THREAD_TRACE_INST_TYPE_FATAL_HALT = 0x00000019,
+} SQ_THREAD_TRACE_INST_TYPE;
+
+/*
+ * SQ_THREAD_TRACE_REG_TYPE enum
+ */
+
+typedef enum SQ_THREAD_TRACE_REG_TYPE {
+SQ_THREAD_TRACE_REG_TYPE_EVENT = 0x00000000,
+SQ_THREAD_TRACE_REG_TYPE_DRAW = 0x00000001,
+SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 0x00000002,
+SQ_THREAD_TRACE_REG_TYPE_USERDATA = 0x00000003,
+SQ_THREAD_TRACE_REG_TYPE_MARKER = 0x00000004,
+SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 0x00000005,
+SQ_THREAD_TRACE_REG_TYPE_SHDEC = 0x00000006,
+SQ_THREAD_TRACE_REG_TYPE_OTHER = 0x00000007,
+} SQ_THREAD_TRACE_REG_TYPE;
+
+/*
+ * SQ_THREAD_TRACE_REG_OP enum
+ */
+
+typedef enum SQ_THREAD_TRACE_REG_OP {
+SQ_THREAD_TRACE_REG_OP_READ = 0x00000000,
+SQ_THREAD_TRACE_REG_OP_WRITE = 0x00000001,
+} SQ_THREAD_TRACE_REG_OP;
+
+/*
+ * SQ_THREAD_TRACE_MODE_SEL enum
+ */
+
+typedef enum SQ_THREAD_TRACE_MODE_SEL {
+SQ_THREAD_TRACE_MODE_OFF = 0x00000000,
+SQ_THREAD_TRACE_MODE_ON = 0x00000001,
+} SQ_THREAD_TRACE_MODE_SEL;
+
+/*
+ * SQ_THREAD_TRACE_CAPTURE_MODE enum
+ */
+
+typedef enum SQ_THREAD_TRACE_CAPTURE_MODE {
+SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0x00000000,
+SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 0x00000001,
+SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x00000002,
+} SQ_THREAD_TRACE_CAPTURE_MODE;
+
+/*
+ * SQ_THREAD_TRACE_VM_ID_MASK enum
+ */
+
+typedef enum SQ_THREAD_TRACE_VM_ID_MASK {
+SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0x00000000,
+SQ_THREAD_TRACE_VM_ID_MASK_ALL = 0x00000001,
+SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x00000002,
+} SQ_THREAD_TRACE_VM_ID_MASK;
+
+/*
+ * SQ_THREAD_TRACE_WAVE_MASK enum
+ */
+
+typedef enum SQ_THREAD_TRACE_WAVE_MASK {
+SQ_THREAD_TRACE_WAVE_MASK_NONE = 0x00000000,
+SQ_THREAD_TRACE_WAVE_MASK_ALL = 0x00000001,
+} SQ_THREAD_TRACE_WAVE_MASK;
+
+/*
+ * SQ_THREAD_TRACE_ISSUE enum
+ */
+
+typedef enum SQ_THREAD_TRACE_ISSUE {
+SQ_THREAD_TRACE_ISSUE_NULL = 0x00000000,
+SQ_THREAD_TRACE_ISSUE_STALL = 0x00000001,
+SQ_THREAD_TRACE_ISSUE_INST = 0x00000002,
+SQ_THREAD_TRACE_ISSUE_IMMED = 0x00000003,
+} SQ_THREAD_TRACE_ISSUE;
+
+/*
+ * SQ_THREAD_TRACE_ISSUE_MASK enum
+ */
+
+typedef enum SQ_THREAD_TRACE_ISSUE_MASK {
+SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0x00000000,
+SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 0x00000001,
+SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x00000002,
+SQ_THREAD_TRACE_ISSUE_MASK_IMMED = 0x00000003,
+} SQ_THREAD_TRACE_ISSUE_MASK;
+
+/*
+ * SQ_PERF_SEL enum
+ */
+
+typedef enum SQ_PERF_SEL {
+SQ_PERF_SEL_NONE = 0x00000000,
+SQ_PERF_SEL_ACCUM_PREV = 0x00000001,
+SQ_PERF_SEL_CYCLES = 0x00000002,
+SQ_PERF_SEL_BUSY_CYCLES = 0x00000003,
+SQ_PERF_SEL_WAVES = 0x00000004,
+SQ_PERF_SEL_LEVEL_WAVES = 0x00000005,
+SQ_PERF_SEL_WAVES_EQ_64 = 0x00000006,
+SQ_PERF_SEL_WAVES_LT_64 = 0x00000007,
+SQ_PERF_SEL_WAVES_LT_48 = 0x00000008,
+SQ_PERF_SEL_WAVES_LT_32 = 0x00000009,
+SQ_PERF_SEL_WAVES_LT_16 = 0x0000000a,
+SQ_PERF_SEL_WAVES_CU = 0x0000000b,
+SQ_PERF_SEL_LEVEL_WAVES_CU = 0x0000000c,
+SQ_PERF_SEL_BUSY_CU_CYCLES = 0x0000000d,
+SQ_PERF_SEL_ITEMS = 0x0000000e,
+SQ_PERF_SEL_QUADS = 0x0000000f,
+SQ_PERF_SEL_EVENTS = 0x00000010,
+SQ_PERF_SEL_SURF_SYNCS = 0x00000011,
+SQ_PERF_SEL_TTRACE_REQS = 0x00000012,
+SQ_PERF_SEL_TTRACE_INFLIGHT_REQS = 0x00000013,
+SQ_PERF_SEL_TTRACE_STALL = 0x00000014,
+SQ_PERF_SEL_MSG_CNTR = 0x00000015,
+SQ_PERF_SEL_MSG_PERF = 0x00000016,
+SQ_PERF_SEL_MSG_GSCNT = 0x00000017,
+SQ_PERF_SEL_MSG_INTERRUPT = 0x00000018,
+SQ_PERF_SEL_INSTS = 0x00000019,
+SQ_PERF_SEL_INSTS_VALU = 0x0000001a,
+SQ_PERF_SEL_INSTS_VMEM_WR = 0x0000001b,
+SQ_PERF_SEL_INSTS_VMEM_RD = 0x0000001c,
+SQ_PERF_SEL_INSTS_VMEM = 0x0000001d,
+SQ_PERF_SEL_INSTS_SALU = 0x0000001e,
+SQ_PERF_SEL_INSTS_SMEM = 0x0000001f,
+SQ_PERF_SEL_INSTS_FLAT = 0x00000020,
+SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY = 0x00000021,
+SQ_PERF_SEL_INSTS_LDS = 0x00000022,
+SQ_PERF_SEL_INSTS_GDS = 0x00000023,
+SQ_PERF_SEL_INSTS_EXP = 0x00000024,
+SQ_PERF_SEL_INSTS_EXP_GDS = 0x00000025,
+SQ_PERF_SEL_INSTS_BRANCH = 0x00000026,
+SQ_PERF_SEL_INSTS_SENDMSG = 0x00000027,
+SQ_PERF_SEL_INSTS_VSKIPPED = 0x00000028,
+SQ_PERF_SEL_INST_LEVEL_VMEM = 0x00000029,
+SQ_PERF_SEL_INST_LEVEL_SMEM = 0x0000002a,
+SQ_PERF_SEL_INST_LEVEL_LDS = 0x0000002b,
+SQ_PERF_SEL_INST_LEVEL_GDS = 0x0000002c,
+SQ_PERF_SEL_INST_LEVEL_EXP = 0x0000002d,
+SQ_PERF_SEL_WAVE_CYCLES = 0x0000002e,
+SQ_PERF_SEL_WAVE_READY = 0x0000002f,
+SQ_PERF_SEL_WAIT_CNT_VM = 0x00000030,
+SQ_PERF_SEL_WAIT_CNT_LGKM = 0x00000031,
+SQ_PERF_SEL_WAIT_CNT_EXP = 0x00000032,
+SQ_PERF_SEL_WAIT_CNT_ANY = 0x00000033,
+SQ_PERF_SEL_WAIT_BARRIER = 0x00000034,
+SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x00000035,
+SQ_PERF_SEL_WAIT_SLEEP = 0x00000036,
+SQ_PERF_SEL_WAIT_SLEEP_XNACK = 0x00000037,
+SQ_PERF_SEL_WAIT_OTHER = 0x00000038,
+SQ_PERF_SEL_WAIT_ANY = 0x00000039,
+SQ_PERF_SEL_WAIT_TTRACE = 0x0000003a,
+SQ_PERF_SEL_WAIT_IFETCH = 0x0000003b,
+SQ_PERF_SEL_WAIT_INST_ANY = 0x0000003c,
+SQ_PERF_SEL_WAIT_INST_VMEM = 0x0000003d,
+SQ_PERF_SEL_WAIT_INST_SCA = 0x0000003e,
+SQ_PERF_SEL_WAIT_INST_LDS = 0x0000003f,
+SQ_PERF_SEL_WAIT_INST_VALU = 0x00000040,
+SQ_PERF_SEL_WAIT_INST_EXP_GDS = 0x00000041,
+SQ_PERF_SEL_WAIT_INST_MISC = 0x00000042,
+SQ_PERF_SEL_WAIT_INST_FLAT = 0x00000043,
+SQ_PERF_SEL_ACTIVE_INST_ANY = 0x00000044,
+SQ_PERF_SEL_ACTIVE_INST_VMEM = 0x00000045,
+SQ_PERF_SEL_ACTIVE_INST_LDS = 0x00000046,
+SQ_PERF_SEL_ACTIVE_INST_VALU = 0x00000047,
+SQ_PERF_SEL_ACTIVE_INST_SCA = 0x00000048,
+SQ_PERF_SEL_ACTIVE_INST_EXP_GDS = 0x00000049,
+SQ_PERF_SEL_ACTIVE_INST_MISC = 0x0000004a,
+SQ_PERF_SEL_ACTIVE_INST_FLAT = 0x0000004b,
+SQ_PERF_SEL_INST_CYCLES_VMEM_WR = 0x0000004c,
+SQ_PERF_SEL_INST_CYCLES_VMEM_RD = 0x0000004d,
+SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR = 0x0000004e,
+SQ_PERF_SEL_INST_CYCLES_VMEM_DATA = 0x0000004f,
+SQ_PERF_SEL_INST_CYCLES_VMEM_CMD = 0x00000050,
+SQ_PERF_SEL_INST_CYCLES_EXP = 0x00000051,
+SQ_PERF_SEL_INST_CYCLES_GDS = 0x00000052,
+SQ_PERF_SEL_INST_CYCLES_SMEM = 0x00000053,
+SQ_PERF_SEL_INST_CYCLES_SALU = 0x00000054,
+SQ_PERF_SEL_THREAD_CYCLES_VALU = 0x00000055,
+SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX = 0x00000056,
+SQ_PERF_SEL_IFETCH = 0x00000057,
+SQ_PERF_SEL_IFETCH_LEVEL = 0x00000058,
+SQ_PERF_SEL_CBRANCH_FORK = 0x00000059,
+SQ_PERF_SEL_CBRANCH_FORK_SPLIT = 0x0000005a,
+SQ_PERF_SEL_VALU_LDS_DIRECT_RD = 0x0000005b,
+SQ_PERF_SEL_VALU_LDS_INTERP_OP = 0x0000005c,
+SQ_PERF_SEL_LDS_BANK_CONFLICT = 0x0000005d,
+SQ_PERF_SEL_LDS_ADDR_CONFLICT = 0x0000005e,
+SQ_PERF_SEL_LDS_UNALIGNED_STALL = 0x0000005f,
+SQ_PERF_SEL_LDS_MEM_VIOLATIONS = 0x00000060,
+SQ_PERF_SEL_LDS_ATOMIC_RETURN = 0x00000061,
+SQ_PERF_SEL_LDS_IDX_ACTIVE = 0x00000062,
+SQ_PERF_SEL_VALU_DEP_STALL = 0x00000063,
+SQ_PERF_SEL_VALU_STARVE = 0x00000064,
+SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x00000065,
+SQ_PERF_SEL_LDS_DATA_FIFO_FULL = 0x00000066,
+SQ_PERF_SEL_LDS_CMD_FIFO_FULL = 0x00000067,
+SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL = 0x00000068,
+SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL = 0x00000069,
+SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY = 0x0000006a,
+SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL = 0x0000006b,
+SQ_PERF_SEL_VALU_SRC_C_CONFLICT = 0x0000006c,
+SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT = 0x0000006d,
+SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT = 0x0000006e,
+SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT = 0x0000006f,
+SQ_PERF_SEL_LDS_SRC_CD_CONFLICT = 0x00000070,
+SQ_PERF_SEL_SRC_CD_BUSY = 0x00000071,
+SQ_PERF_SEL_PT_POWER_STALL = 0x00000072,
+SQ_PERF_SEL_USER0 = 0x00000073,
+SQ_PERF_SEL_USER1 = 0x00000074,
+SQ_PERF_SEL_USER2 = 0x00000075,
+SQ_PERF_SEL_USER3 = 0x00000076,
+SQ_PERF_SEL_USER4 = 0x00000077,
+SQ_PERF_SEL_USER5 = 0x00000078,
+SQ_PERF_SEL_USER6 = 0x00000079,
+SQ_PERF_SEL_USER7 = 0x0000007a,
+SQ_PERF_SEL_USER8 = 0x0000007b,
+SQ_PERF_SEL_USER9 = 0x0000007c,
+SQ_PERF_SEL_USER10 = 0x0000007d,
+SQ_PERF_SEL_USER11 = 0x0000007e,
+SQ_PERF_SEL_USER12 = 0x0000007f,
+SQ_PERF_SEL_USER13 = 0x00000080,
+SQ_PERF_SEL_USER14 = 0x00000081,
+SQ_PERF_SEL_USER15 = 0x00000082,
+SQ_PERF_SEL_USER_LEVEL0 = 0x00000083,
+SQ_PERF_SEL_USER_LEVEL1 = 0x00000084,
+SQ_PERF_SEL_USER_LEVEL2 = 0x00000085,
+SQ_PERF_SEL_USER_LEVEL3 = 0x00000086,
+SQ_PERF_SEL_USER_LEVEL4 = 0x00000087,
+SQ_PERF_SEL_USER_LEVEL5 = 0x00000088,
+SQ_PERF_SEL_USER_LEVEL6 = 0x00000089,
+SQ_PERF_SEL_USER_LEVEL7 = 0x0000008a,
+SQ_PERF_SEL_USER_LEVEL8 = 0x0000008b,
+SQ_PERF_SEL_USER_LEVEL9 = 0x0000008c,
+SQ_PERF_SEL_USER_LEVEL10 = 0x0000008d,
+SQ_PERF_SEL_USER_LEVEL11 = 0x0000008e,
+SQ_PERF_SEL_USER_LEVEL12 = 0x0000008f,
+SQ_PERF_SEL_USER_LEVEL13 = 0x00000090,
+SQ_PERF_SEL_USER_LEVEL14 = 0x00000091,
+SQ_PERF_SEL_USER_LEVEL15 = 0x00000092,
+SQ_PERF_SEL_POWER_VALU = 0x00000093,
+SQ_PERF_SEL_POWER_VALU0 = 0x00000094,
+SQ_PERF_SEL_POWER_VALU1 = 0x00000095,
+SQ_PERF_SEL_POWER_VALU2 = 0x00000096,
+SQ_PERF_SEL_POWER_GPR_RD = 0x00000097,
+SQ_PERF_SEL_POWER_GPR_WR = 0x00000098,
+SQ_PERF_SEL_POWER_LDS_BUSY = 0x00000099,
+SQ_PERF_SEL_POWER_ALU_BUSY = 0x0000009a,
+SQ_PERF_SEL_POWER_TEX_BUSY = 0x0000009b,
+SQ_PERF_SEL_ACCUM_PREV_HIRES = 0x0000009c,
+SQ_PERF_SEL_WAVES_RESTORED = 0x0000009d,
+SQ_PERF_SEL_WAVES_SAVED = 0x0000009e,
+SQ_PERF_SEL_INSTS_SMEM_NORM = 0x0000009f,
+SQ_PERF_SEL_ATC_INSTS_VMEM = 0x000000a0,
+SQ_PERF_SEL_ATC_INST_LEVEL_VMEM = 0x000000a1,
+SQ_PERF_SEL_ATC_XNACK_FIRST = 0x000000a2,
+SQ_PERF_SEL_ATC_XNACK_ALL = 0x000000a3,
+SQ_PERF_SEL_ATC_XNACK_FIFO_FULL = 0x000000a4,
+SQ_PERF_SEL_ATC_INSTS_SMEM = 0x000000a5,
+SQ_PERF_SEL_ATC_INST_LEVEL_SMEM = 0x000000a6,
+SQ_PERF_SEL_IFETCH_XNACK = 0x000000a7,
+SQ_PERF_SEL_TLB_SHOOTDOWN = 0x000000a8,
+SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES = 0x000000a9,
+SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY = 0x000000aa,
+SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY = 0x000000ab,
+SQ_PERF_SEL_INSTS_VMEM_REPLAY = 0x000000ac,
+SQ_PERF_SEL_INSTS_SMEM_REPLAY = 0x000000ad,
+SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY = 0x000000ae,
+SQ_PERF_SEL_INSTS_FLAT_REPLAY = 0x000000af,
+SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY = 0x000000b0,
+SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY = 0x000000b1,
+SQ_PERF_SEL_UTCL1_TRANSLATION_MISS = 0x000000b2,
+SQ_PERF_SEL_UTCL1_PERMISSION_MISS = 0x000000b3,
+SQ_PERF_SEL_UTCL1_REQUEST = 0x000000b4,
+SQ_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 0x000000b5,
+SQ_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 0x000000b6,
+SQ_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 0x000000b7,
+SQ_PERF_SEL_UTCL1_LFIFO_FULL = 0x000000b8,
+SQ_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 0x000000b9,
+SQ_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x000000ba,
+SQ_PERF_SEL_DUMMY_END = 0x000000bb,
+SQ_PERF_SEL_DUMMY_LAST = 0x000000ff,
+SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 0x00000100,
+SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0x00000101,
+SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 0x00000102,
+SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 0x00000103,
+SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0x00000104,
+SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 0x00000105,
+SQC_PERF_SEL_TC_REQ = 0x00000106,
+SQC_PERF_SEL_TC_INST_REQ = 0x00000107,
+SQC_PERF_SEL_TC_DATA_READ_REQ = 0x00000108,
+SQC_PERF_SEL_TC_DATA_WRITE_REQ = 0x00000109,
+SQC_PERF_SEL_TC_DATA_ATOMIC_REQ = 0x0000010a,
+SQC_PERF_SEL_TC_STALL = 0x0000010b,
+SQC_PERF_SEL_TC_STARVE = 0x0000010c,
+SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0x0000010d,
+SQC_PERF_SEL_ICACHE_REQ = 0x0000010e,
+SQC_PERF_SEL_ICACHE_HITS = 0x0000010f,
+SQC_PERF_SEL_ICACHE_MISSES = 0x00000110,
+SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0x00000111,
+SQC_PERF_SEL_ICACHE_INVAL_INST = 0x00000112,
+SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0x00000113,
+SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0x00000114,
+SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0x00000115,
+SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0x00000116,
+SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0x00000117,
+SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000118,
+SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 0x00000119,
+SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0x0000011a,
+SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0x0000011b,
+SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 0x0000011c,
+SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x0000011d,
+SQC_PERF_SEL_ICACHE_PREFETCH_1 = 0x0000011e,
+SQC_PERF_SEL_ICACHE_PREFETCH_2 = 0x0000011f,
+SQC_PERF_SEL_ICACHE_PREFETCH_FILTERED = 0x00000120,
+SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0x00000121,
+SQC_PERF_SEL_DCACHE_REQ = 0x00000122,
+SQC_PERF_SEL_DCACHE_HITS = 0x00000123,
+SQC_PERF_SEL_DCACHE_MISSES = 0x00000124,
+SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0x00000125,
+SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 0x00000126,
+SQC_PERF_SEL_DCACHE_MISS_EVICT_READ = 0x00000127,
+SQC_PERF_SEL_DCACHE_WC_LRU_WRITE = 0x00000128,
+SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE = 0x00000129,
+SQC_PERF_SEL_DCACHE_ATOMIC = 0x0000012a,
+SQC_PERF_SEL_DCACHE_VOLATILE = 0x0000012b,
+SQC_PERF_SEL_DCACHE_INVAL_INST = 0x0000012c,
+SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0x0000012d,
+SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST = 0x0000012e,
+SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC = 0x0000012f,
+SQC_PERF_SEL_DCACHE_WB_INST = 0x00000130,
+SQC_PERF_SEL_DCACHE_WB_ASYNC = 0x00000131,
+SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST = 0x00000132,
+SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC = 0x00000133,
+SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0x00000134,
+SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0x00000135,
+SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0x00000136,
+SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000137,
+SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0x00000138,
+SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT = 0x00000139,
+SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED = 0x0000013a,
+SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE = 0x0000013b,
+SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT = 0x0000013c,
+SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH = 0x0000013d,
+SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE = 0x0000013e,
+SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0x0000013f,
+SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0x00000140,
+SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 0x00000141,
+SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x00000142,
+SQC_PERF_SEL_DCACHE_REQ_READ_1 = 0x00000143,
+SQC_PERF_SEL_DCACHE_REQ_READ_2 = 0x00000144,
+SQC_PERF_SEL_DCACHE_REQ_READ_4 = 0x00000145,
+SQC_PERF_SEL_DCACHE_REQ_READ_8 = 0x00000146,
+SQC_PERF_SEL_DCACHE_REQ_READ_16 = 0x00000147,
+SQC_PERF_SEL_DCACHE_REQ_TIME = 0x00000148,
+SQC_PERF_SEL_DCACHE_REQ_WRITE_1 = 0x00000149,
+SQC_PERF_SEL_DCACHE_REQ_WRITE_2 = 0x0000014a,
+SQC_PERF_SEL_DCACHE_REQ_WRITE_4 = 0x0000014b,
+SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 0x0000014c,
+SQC_PERF_SEL_SQ_DCACHE_REQS = 0x0000014d,
+SQC_PERF_SEL_DCACHE_FLAT_REQ = 0x0000014e,
+SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 0x0000014f,
+SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0x00000150,
+SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0x00000151,
+SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0x00000152,
+SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0x00000153,
+SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0x00000154,
+SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS = 0x00000155,
+SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS = 0x00000156,
+SQC_PERF_SEL_ICACHE_GATCL1_REQUEST = 0x00000157,
+SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX = 0x00000158,
+SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT = 0x00000159,
+SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL = 0x0000015a,
+SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x0000015b,
+SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS = 0x0000015c,
+SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT = 0x0000015d,
+SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL = 0x0000015e,
+SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS = 0x0000015f,
+SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS = 0x00000160,
+SQC_PERF_SEL_DCACHE_GATCL1_REQUEST = 0x00000161,
+SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX = 0x00000162,
+SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT = 0x00000163,
+SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL = 0x00000164,
+SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x00000165,
+SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS = 0x00000166,
+SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT = 0x00000167,
+SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL = 0x00000168,
+SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS = 0x00000169,
+SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL = 0x0000016a,
+SQC_PERF_SEL_DUMMY_LAST = 0x0000016b,
+} SQ_PERF_SEL;
+
+/*
+ * SQ_CAC_POWER_SEL enum
+ */
+
+typedef enum SQ_CAC_POWER_SEL {
+SQ_CAC_POWER_VALU = 0x00000000,
+SQ_CAC_POWER_VALU0 = 0x00000001,
+SQ_CAC_POWER_VALU1 = 0x00000002,
+SQ_CAC_POWER_VALU2 = 0x00000003,
+SQ_CAC_POWER_GPR_RD = 0x00000004,
+SQ_CAC_POWER_GPR_WR = 0x00000005,
+SQ_CAC_POWER_LDS_BUSY = 0x00000006,
+SQ_CAC_POWER_ALU_BUSY = 0x00000007,
+SQ_CAC_POWER_TEX_BUSY = 0x00000008,
+} SQ_CAC_POWER_SEL;
+
+/*
+ * SQ_IND_CMD_CMD enum
+ */
+
+typedef enum SQ_IND_CMD_CMD {
+SQ_IND_CMD_CMD_NULL = 0x00000000,
+SQ_IND_CMD_CMD_SETHALT = 0x00000001,
+SQ_IND_CMD_CMD_SAVECTX = 0x00000002,
+SQ_IND_CMD_CMD_KILL = 0x00000003,
+SQ_IND_CMD_CMD_DEBUG = 0x00000004,
+SQ_IND_CMD_CMD_TRAP = 0x00000005,
+SQ_IND_CMD_CMD_SET_SPI_PRIO = 0x00000006,
+SQ_IND_CMD_CMD_SETFATALHALT = 0x00000007,
+} SQ_IND_CMD_CMD;
+
+/*
+ * SQ_IND_CMD_MODE enum
+ */
+
+typedef enum SQ_IND_CMD_MODE {
+SQ_IND_CMD_MODE_SINGLE = 0x00000000,
+SQ_IND_CMD_MODE_BROADCAST = 0x00000001,
+SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002,
+SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003,
+SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004,
+} SQ_IND_CMD_MODE;
+
+/*
+ * SQ_EDC_INFO_SOURCE enum
+ */
+
+typedef enum SQ_EDC_INFO_SOURCE {
+SQ_EDC_INFO_SOURCE_INVALID = 0x00000000,
+SQ_EDC_INFO_SOURCE_INST = 0x00000001,
+SQ_EDC_INFO_SOURCE_SGPR = 0x00000002,
+SQ_EDC_INFO_SOURCE_VGPR = 0x00000003,
+SQ_EDC_INFO_SOURCE_LDS = 0x00000004,
+SQ_EDC_INFO_SOURCE_GDS = 0x00000005,
+SQ_EDC_INFO_SOURCE_TA = 0x00000006,
+} SQ_EDC_INFO_SOURCE;
+
+/*
+ * SQ_ROUND_MODE enum
+ */
+
+typedef enum SQ_ROUND_MODE {
+SQ_ROUND_NEAREST_EVEN = 0x00000000,
+SQ_ROUND_PLUS_INFINITY = 0x00000001,
+SQ_ROUND_MINUS_INFINITY = 0x00000002,
+SQ_ROUND_TO_ZERO = 0x00000003,
+} SQ_ROUND_MODE;
+
+/*
+ * SQ_INTERRUPT_WORD_ENCODING enum
+ */
+
+typedef enum SQ_INTERRUPT_WORD_ENCODING {
+SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x00000000,
+SQ_INTERRUPT_WORD_ENCODING_INST = 0x00000001,
+SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x00000002,
+} SQ_INTERRUPT_WORD_ENCODING;
+
+/*
+ * ENUM_SQ_EXPORT_RAT_INST enum
+ */
+
+typedef enum ENUM_SQ_EXPORT_RAT_INST {
+SQ_EXPORT_RAT_INST_NOP = 0x00000000,
+SQ_EXPORT_RAT_INST_STORE_TYPED = 0x00000001,
+SQ_EXPORT_RAT_INST_STORE_RAW = 0x00000002,
+SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 0x00000003,
+SQ_EXPORT_RAT_INST_CMPXCHG_INT = 0x00000004,
+SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 0x00000005,
+SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 0x00000006,
+SQ_EXPORT_RAT_INST_ADD = 0x00000007,
+SQ_EXPORT_RAT_INST_SUB = 0x00000008,
+SQ_EXPORT_RAT_INST_RSUB = 0x00000009,
+SQ_EXPORT_RAT_INST_MIN_INT = 0x0000000a,
+SQ_EXPORT_RAT_INST_MIN_UINT = 0x0000000b,
+SQ_EXPORT_RAT_INST_MAX_INT = 0x0000000c,
+SQ_EXPORT_RAT_INST_MAX_UINT = 0x0000000d,
+SQ_EXPORT_RAT_INST_AND = 0x0000000e,
+SQ_EXPORT_RAT_INST_OR = 0x0000000f,
+SQ_EXPORT_RAT_INST_XOR = 0x00000010,
+SQ_EXPORT_RAT_INST_MSKOR = 0x00000011,
+SQ_EXPORT_RAT_INST_INC_UINT = 0x00000012,
+SQ_EXPORT_RAT_INST_DEC_UINT = 0x00000013,
+SQ_EXPORT_RAT_INST_STORE_DWORD = 0x00000014,
+SQ_EXPORT_RAT_INST_STORE_SHORT = 0x00000015,
+SQ_EXPORT_RAT_INST_STORE_BYTE = 0x00000016,
+SQ_EXPORT_RAT_INST_NOP_RTN = 0x00000020,
+SQ_EXPORT_RAT_INST_XCHG_RTN = 0x00000022,
+SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 0x00000023,
+SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 0x00000024,
+SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 0x00000025,
+SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 0x00000026,
+SQ_EXPORT_RAT_INST_ADD_RTN = 0x00000027,
+SQ_EXPORT_RAT_INST_SUB_RTN = 0x00000028,
+SQ_EXPORT_RAT_INST_RSUB_RTN = 0x00000029,
+SQ_EXPORT_RAT_INST_MIN_INT_RTN = 0x0000002a,
+SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 0x0000002b,
+SQ_EXPORT_RAT_INST_MAX_INT_RTN = 0x0000002c,
+SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 0x0000002d,
+SQ_EXPORT_RAT_INST_AND_RTN = 0x0000002e,
+SQ_EXPORT_RAT_INST_OR_RTN = 0x0000002f,
+SQ_EXPORT_RAT_INST_XOR_RTN = 0x00000030,
+SQ_EXPORT_RAT_INST_MSKOR_RTN = 0x00000031,
+SQ_EXPORT_RAT_INST_INC_UINT_RTN = 0x00000032,
+SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 0x00000033,
+} ENUM_SQ_EXPORT_RAT_INST;
+
+/*
+ * SQ_IBUF_ST enum
+ */
+
+typedef enum SQ_IBUF_ST {
+SQ_IBUF_IB_IDLE = 0x00000000,
+SQ_IBUF_IB_INI_WAIT_GNT = 0x00000001,
+SQ_IBUF_IB_INI_WAIT_DRET = 0x00000002,
+SQ_IBUF_IB_LE_4DW = 0x00000003,
+SQ_IBUF_IB_WAIT_DRET = 0x00000004,
+SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x00000005,
+SQ_IBUF_IB_DRET = 0x00000006,
+SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x00000007,
+} SQ_IBUF_ST;
+
+/*
+ * SQ_INST_STR_ST enum
+ */
+
+typedef enum SQ_INST_STR_ST {
+SQ_INST_STR_IB_WAVE_NORML = 0x00000000,
+SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x00000001,
+SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x00000002,
+SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x00000003,
+SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 0x00000004,
+SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 0x00000005,
+SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x00000006,
+SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x00000007,
+} SQ_INST_STR_ST;
+
+/*
+ * SQ_WAVE_IB_ECC_ST enum
+ */
+
+typedef enum SQ_WAVE_IB_ECC_ST {
+SQ_WAVE_IB_ECC_CLEAN = 0x00000000,
+SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x00000001,
+SQ_WAVE_IB_ECC_ERR_HALT = 0x00000002,
+SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x00000003,
+} SQ_WAVE_IB_ECC_ST;
+
+/*
+ * SH_MEM_ADDRESS_MODE enum
+ */
+
+typedef enum SH_MEM_ADDRESS_MODE {
+SH_MEM_ADDRESS_MODE_64 = 0x00000000,
+SH_MEM_ADDRESS_MODE_32 = 0x00000001,
+} SH_MEM_ADDRESS_MODE;
+
+/*
+ * SH_MEM_ALIGNMENT_MODE enum
+ */
+
+typedef enum SH_MEM_ALIGNMENT_MODE {
+SH_MEM_ALIGNMENT_MODE_DWORD = 0x00000000,
+SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x00000001,
+SH_MEM_ALIGNMENT_MODE_STRICT = 0x00000002,
+SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x00000003,
+} SH_MEM_ALIGNMENT_MODE;
+
+/*
+ * SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX enum
+ */
+
+typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX {
+SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC = 0x00000018,
+SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE = 0x00000019,
+} SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX;
+
+/*
+ * SQ_LB_CTR_SEL_VALUES enum
+ */
+
+typedef enum SQ_LB_CTR_SEL_VALUES {
+SQ_LB_CTR_SEL_ALU_CYCLES = 0x00000000,
+SQ_LB_CTR_SEL_ALU_STALLS = 0x00000001,
+SQ_LB_CTR_SEL_TEX_CYCLES = 0x00000002,
+SQ_LB_CTR_SEL_TEX_STALLS = 0x00000003,
+SQ_LB_CTR_SEL_SALU_CYCLES = 0x00000004,
+SQ_LB_CTR_SEL_SCALAR_STALLS = 0x00000005,
+SQ_LB_CTR_SEL_SMEM_CYCLES = 0x00000006,
+SQ_LB_CTR_SEL_ICACHE_STALLS = 0x00000007,
+SQ_LB_CTR_SEL_DCACHE_STALLS = 0x00000008,
+SQ_LB_CTR_SEL_RESERVED0 = 0x00000009,
+SQ_LB_CTR_SEL_RESERVED1 = 0x0000000a,
+SQ_LB_CTR_SEL_RESERVED2 = 0x0000000b,
+SQ_LB_CTR_SEL_RESERVED3 = 0x0000000c,
+SQ_LB_CTR_SEL_RESERVED4 = 0x0000000d,
+SQ_LB_CTR_SEL_RESERVED5 = 0x0000000e,
+SQ_LB_CTR_SEL_RESERVED6 = 0x0000000f,
+} SQ_LB_CTR_SEL_VALUES;
+
+/*
+ * SQ_WAVE_TYPE value
+ */
+
+#define SQ_WAVE_TYPE_PS0 0x00000000
+
+/*
+ * SQIND_PARTITIONS value
+ */
+
+#define SQIND_GLOBAL_REGS_OFFSET 0x00000000
+#define SQIND_GLOBAL_REGS_SIZE 0x00000008
+#define SQIND_LOCAL_REGS_OFFSET 0x00000008
+#define SQIND_LOCAL_REGS_SIZE 0x00000008
+#define SQIND_WAVE_HWREGS_OFFSET 0x00000010
+#define SQIND_WAVE_HWREGS_SIZE 0x000001f0
+#define SQIND_WAVE_SGPRS_OFFSET 0x00000200
+#define SQIND_WAVE_SGPRS_SIZE 0x00000200
+#define SQIND_WAVE_VGPRS_OFFSET 0x00000400
+#define SQIND_WAVE_VGPRS_SIZE 0x00000100
+
+/*
+ * SQ_GFXDEC value
+ */
+
+#define SQ_GFXDEC_BEGIN 0x0000a000
+#define SQ_GFXDEC_END 0x0000c000
+#define SQ_GFXDEC_STATE_ID_SHIFT 0x0000000a
+
+/*
+ * SQDEC value
+ */
+
+#define SQDEC_BEGIN 0x00002300
+#define SQDEC_END 0x000023ff
+
+/*
+ * SQPERFSDEC value
+ */
+
+#define SQPERFSDEC_BEGIN 0x0000d9c0
+#define SQPERFSDEC_END 0x0000da40
+
+/*
+ * SQPERFDDEC value
+ */
+
+#define SQPERFDDEC_BEGIN 0x0000d1c0
+#define SQPERFDDEC_END 0x0000d240
+
+/*
+ * SQGFXUDEC value
+ */
+
+#define SQGFXUDEC_BEGIN 0x0000c330
+#define SQGFXUDEC_END 0x0000c380
+
+/*
+ * SQPWRDEC value
+ */
+
+#define SQPWRDEC_BEGIN 0x0000f08c
+#define SQPWRDEC_END 0x0000f094
+
+/*
+ * SQ_DISPATCHER value
+ */
+
+#define SQ_DISPATCHER_GFX_MIN 0x00000010
+#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x00000008
+
+/*
+ * SQ_MAX value
+ */
+
+#define SQ_MAX_PGM_SGPRS 0x00000068
+#define SQ_MAX_PGM_VGPRS 0x00000100
+
+/*
+ * SQ_THREAD_TRACE_TIME_UNIT value
+ */
+
+#define SQ_THREAD_TRACE_TIME_UNIT 0x00000004
+
+/*
+ * SQ_EXCP_BITS value
+ */
+
+#define SQ_EX_MODE_EXCP_VALU_BASE 0x00000000
+#define SQ_EX_MODE_EXCP_VALU_SIZE 0x00000007
+#define SQ_EX_MODE_EXCP_INVALID 0x00000000
+#define SQ_EX_MODE_EXCP_INPUT_DENORM 0x00000001
+#define SQ_EX_MODE_EXCP_DIV0 0x00000002
+#define SQ_EX_MODE_EXCP_OVERFLOW 0x00000003
+#define SQ_EX_MODE_EXCP_UNDERFLOW 0x00000004
+#define SQ_EX_MODE_EXCP_INEXACT 0x00000005
+#define SQ_EX_MODE_EXCP_INT_DIV0 0x00000006
+#define SQ_EX_MODE_EXCP_ADDR_WATCH0 0x00000007
+#define SQ_EX_MODE_EXCP_MEM_VIOL 0x00000008
+
+/*
+ * SQ_EXCP_HI_BITS value
+ */
+
+#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 0x00000000
+#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 0x00000001
+#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 0x00000002
+
+/*
+ * HW_INSERTED_INST_ID value
+ */
+
+#define INST_ID_PRIV_START 0x80000000
+#define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0
+#define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1
+#define INST_ID_HW_TRAP 0xfffffff2
+#define INST_ID_KILL_SEQ 0xfffffff3
+#define INST_ID_SPI_WREXEC 0xfffffff4
+#define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe
+
+/*
+ * SIMM16_WAITCNT_PARTITIONS value
+ */
+
+#define SIMM16_WAITCNT_VM_CNT_START 0x00000000
+#define SIMM16_WAITCNT_VM_CNT_SIZE 0x00000004
+#define SIMM16_WAITCNT_EXP_CNT_START 0x00000004
+#define SIMM16_WAITCNT_EXP_CNT_SIZE 0x00000003
+#define SIMM16_WAITCNT_LGKM_CNT_START 0x00000008
+#define SIMM16_WAITCNT_LGKM_CNT_SIZE 0x00000004
+#define SIMM16_WAITCNT_VM_CNT_HI_START 0x0000000e
+#define SIMM16_WAITCNT_VM_CNT_HI_SIZE 0x00000002
+
+/*
+ * SQ_EDC_FUE_CNTL_BITS value
+ */
+
+#define SQ_EDC_FUE_CNTL_SQ 0x00000000
+#define SQ_EDC_FUE_CNTL_LDS 0x00000001
+#define SQ_EDC_FUE_CNTL_SIMD0 0x00000002
+#define SQ_EDC_FUE_CNTL_SIMD1 0x00000003
+#define SQ_EDC_FUE_CNTL_SIMD2 0x00000004
+#define SQ_EDC_FUE_CNTL_SIMD3 0x00000005
+#define SQ_EDC_FUE_CNTL_TA 0x00000006
+#define SQ_EDC_FUE_CNTL_TD 0x00000007
+#define SQ_EDC_FUE_CNTL_TCP 0x00000008
+
+/*******************************************************
+ * COMP Enums
+ *******************************************************/
+
+/*
+ * CSDATA_TYPE enum
+ */
+
+typedef enum CSDATA_TYPE {
+CSDATA_TYPE_TG = 0x00000000,
+CSDATA_TYPE_STATE = 0x00000001,
+CSDATA_TYPE_EVENT = 0x00000002,
+CSDATA_TYPE_PRIVATE = 0x00000003,
+} CSDATA_TYPE;
+
+/*
+ * CSDATA_TYPE_WIDTH value
+ */
+
+#define CSDATA_TYPE_WIDTH 0x00000002
+
+/*
+ * CSDATA_ADDR_WIDTH value
+ */
+
+#define CSDATA_ADDR_WIDTH 0x00000007
+
+/*
+ * CSDATA_DATA_WIDTH value
+ */
+
+#define CSDATA_DATA_WIDTH 0x00000020
+
+/*******************************************************
+ * VGT Enums
+ *******************************************************/
+
+/*
+ * VGT_OUT_PRIM_TYPE enum
+ */
+
+typedef enum VGT_OUT_PRIM_TYPE {
+VGT_OUT_POINT = 0x00000000,
+VGT_OUT_LINE = 0x00000001,
+VGT_OUT_TRI = 0x00000002,
+VGT_OUT_RECT_V0 = 0x00000003,
+VGT_OUT_RECT_V1 = 0x00000004,
+VGT_OUT_RECT_V2 = 0x00000005,
+VGT_OUT_RECT_V3 = 0x00000006,
+VGT_OUT_2D_RECT = 0x00000007,
+VGT_TE_QUAD = 0x00000008,
+VGT_TE_PRIM_INDEX_LINE = 0x00000009,
+VGT_TE_PRIM_INDEX_TRI = 0x0000000a,
+VGT_TE_PRIM_INDEX_QUAD = 0x0000000b,
+VGT_OUT_LINE_ADJ = 0x0000000c,
+VGT_OUT_TRI_ADJ = 0x0000000d,
+VGT_OUT_PATCH = 0x0000000e,
+} VGT_OUT_PRIM_TYPE;
+
+/*
+ * VGT_DI_PRIM_TYPE enum
+ */
+
+typedef enum VGT_DI_PRIM_TYPE {
+DI_PT_NONE = 0x00000000,
+DI_PT_POINTLIST = 0x00000001,
+DI_PT_LINELIST = 0x00000002,
+DI_PT_LINESTRIP = 0x00000003,
+DI_PT_TRILIST = 0x00000004,
+DI_PT_TRIFAN = 0x00000005,
+DI_PT_TRISTRIP = 0x00000006,
+DI_PT_2D_RECTANGLE = 0x00000007,
+DI_PT_UNUSED_1 = 0x00000008,
+DI_PT_PATCH = 0x00000009,
+DI_PT_LINELIST_ADJ = 0x0000000a,
+DI_PT_LINESTRIP_ADJ = 0x0000000b,
+DI_PT_TRILIST_ADJ = 0x0000000c,
+DI_PT_TRISTRIP_ADJ = 0x0000000d,
+DI_PT_UNUSED_3 = 0x0000000e,
+DI_PT_UNUSED_4 = 0x0000000f,
+DI_PT_TRI_WITH_WFLAGS = 0x00000010,
+DI_PT_RECTLIST = 0x00000011,
+DI_PT_LINELOOP = 0x00000012,
+DI_PT_QUADLIST = 0x00000013,
+DI_PT_QUADSTRIP = 0x00000014,
+DI_PT_POLYGON = 0x00000015,
+} VGT_DI_PRIM_TYPE;
+
+/*
+ * VGT_DI_SOURCE_SELECT enum
+ */
+
+typedef enum VGT_DI_SOURCE_SELECT {
+DI_SRC_SEL_DMA = 0x00000000,
+DI_SRC_SEL_IMMEDIATE = 0x00000001,
+DI_SRC_SEL_AUTO_INDEX = 0x00000002,
+DI_SRC_SEL_RESERVED = 0x00000003,
+} VGT_DI_SOURCE_SELECT;
+
+/*
+ * VGT_DI_MAJOR_MODE_SELECT enum
+ */
+
+typedef enum VGT_DI_MAJOR_MODE_SELECT {
+DI_MAJOR_MODE_0 = 0x00000000,
+DI_MAJOR_MODE_1 = 0x00000001,
+} VGT_DI_MAJOR_MODE_SELECT;
+
+/*
+ * VGT_DI_INDEX_SIZE enum
+ */
+
+typedef enum VGT_DI_INDEX_SIZE {
+DI_INDEX_SIZE_16_BIT = 0x00000000,
+DI_INDEX_SIZE_32_BIT = 0x00000001,
+DI_INDEX_SIZE_8_BIT = 0x00000002,
+} VGT_DI_INDEX_SIZE;
+
+/*
+ * VGT_EVENT_TYPE enum
+ */
+
+typedef enum VGT_EVENT_TYPE {
+Reserved_0x00 = 0x00000000,
+SAMPLE_STREAMOUTSTATS1 = 0x00000001,
+SAMPLE_STREAMOUTSTATS2 = 0x00000002,
+SAMPLE_STREAMOUTSTATS3 = 0x00000003,
+CACHE_FLUSH_TS = 0x00000004,
+CONTEXT_DONE = 0x00000005,
+CACHE_FLUSH = 0x00000006,
+CS_PARTIAL_FLUSH = 0x00000007,
+VGT_STREAMOUT_SYNC = 0x00000008,
+Reserved_0x09 = 0x00000009,
+VGT_STREAMOUT_RESET = 0x0000000a,
+END_OF_PIPE_INCR_DE = 0x0000000b,
+END_OF_PIPE_IB_END = 0x0000000c,
+RST_PIX_CNT = 0x0000000d,
+BREAK_BATCH = 0x0000000e,
+VS_PARTIAL_FLUSH = 0x0000000f,
+PS_PARTIAL_FLUSH = 0x00000010,
+FLUSH_HS_OUTPUT = 0x00000011,
+FLUSH_DFSM = 0x00000012,
+RESET_TO_LOWEST_VGT = 0x00000013,
+CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014,
+ZPASS_DONE = 0x00000015,
+CACHE_FLUSH_AND_INV_EVENT = 0x00000016,
+PERFCOUNTER_START = 0x00000017,
+PERFCOUNTER_STOP = 0x00000018,
+PIPELINESTAT_START = 0x00000019,
+PIPELINESTAT_STOP = 0x0000001a,
+PERFCOUNTER_SAMPLE = 0x0000001b,
+Available_0x1c = 0x0000001c,
+Available_0x1d = 0x0000001d,
+SAMPLE_PIPELINESTAT = 0x0000001e,
+SO_VGTSTREAMOUT_FLUSH = 0x0000001f,
+SAMPLE_STREAMOUTSTATS = 0x00000020,
+RESET_VTX_CNT = 0x00000021,
+BLOCK_CONTEXT_DONE = 0x00000022,
+CS_CONTEXT_DONE = 0x00000023,
+VGT_FLUSH = 0x00000024,
+TGID_ROLLOVER = 0x00000025,
+SQ_NON_EVENT = 0x00000026,
+SC_SEND_DB_VPZ = 0x00000027,
+BOTTOM_OF_PIPE_TS = 0x00000028,
+FLUSH_SX_TS = 0x00000029,
+DB_CACHE_FLUSH_AND_INV = 0x0000002a,
+FLUSH_AND_INV_DB_DATA_TS = 0x0000002b,
+FLUSH_AND_INV_DB_META = 0x0000002c,
+FLUSH_AND_INV_CB_DATA_TS = 0x0000002d,
+FLUSH_AND_INV_CB_META = 0x0000002e,
+CS_DONE = 0x0000002f,
+PS_DONE = 0x00000030,
+FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000031,
+SX_CB_RAT_ACK_REQUEST = 0x00000032,
+THREAD_TRACE_START = 0x00000033,
+THREAD_TRACE_STOP = 0x00000034,
+THREAD_TRACE_MARKER = 0x00000035,
+THREAD_TRACE_FLUSH = 0x00000036,
+THREAD_TRACE_FINISH = 0x00000037,
+PIXEL_PIPE_STAT_CONTROL = 0x00000038,
+PIXEL_PIPE_STAT_DUMP = 0x00000039,
+PIXEL_PIPE_STAT_RESET = 0x0000003a,
+CONTEXT_SUSPEND = 0x0000003b,
+OFFCHIP_HS_DEALLOC = 0x0000003c,
+ENABLE_NGG_PIPELINE = 0x0000003d,
+ENABLE_LEGACY_PIPELINE = 0x0000003e,
+Reserved_0x3f = 0x0000003f,
+} VGT_EVENT_TYPE;
+
+/*
+ * VGT_DMA_SWAP_MODE enum
+ */
+
+typedef enum VGT_DMA_SWAP_MODE {
+VGT_DMA_SWAP_NONE = 0x00000000,
+VGT_DMA_SWAP_16_BIT = 0x00000001,
+VGT_DMA_SWAP_32_BIT = 0x00000002,
+VGT_DMA_SWAP_WORD = 0x00000003,
+} VGT_DMA_SWAP_MODE;
+
+/*
+ * VGT_INDEX_TYPE_MODE enum
+ */
+
+typedef enum VGT_INDEX_TYPE_MODE {
+VGT_INDEX_16 = 0x00000000,
+VGT_INDEX_32 = 0x00000001,
+VGT_INDEX_8 = 0x00000002,
+} VGT_INDEX_TYPE_MODE;
+
+/*
+ * VGT_DMA_BUF_TYPE enum
+ */
+
+typedef enum VGT_DMA_BUF_TYPE {
+VGT_DMA_BUF_MEM = 0x00000000,
+VGT_DMA_BUF_RING = 0x00000001,
+VGT_DMA_BUF_SETUP = 0x00000002,
+VGT_DMA_PTR_UPDATE = 0x00000003,
+} VGT_DMA_BUF_TYPE;
+
+/*
+ * VGT_OUTPATH_SELECT enum
+ */
+
+typedef enum VGT_OUTPATH_SELECT {
+VGT_OUTPATH_VTX_REUSE = 0x00000000,
+VGT_OUTPATH_TESS_EN = 0x00000001,
+VGT_OUTPATH_PASSTHRU = 0x00000002,
+VGT_OUTPATH_GS_BLOCK = 0x00000003,
+VGT_OUTPATH_HS_BLOCK = 0x00000004,
+VGT_OUTPATH_PRIM_GEN = 0x00000005,
+} VGT_OUTPATH_SELECT;
+
+/*
+ * VGT_GRP_PRIM_TYPE enum
+ */
+
+typedef enum VGT_GRP_PRIM_TYPE {
+VGT_GRP_3D_POINT = 0x00000000,
+VGT_GRP_3D_LINE = 0x00000001,
+VGT_GRP_3D_TRI = 0x00000002,
+VGT_GRP_3D_RECT = 0x00000003,
+VGT_GRP_3D_QUAD = 0x00000004,
+VGT_GRP_2D_COPY_RECT_V0 = 0x00000005,
+VGT_GRP_2D_COPY_RECT_V1 = 0x00000006,
+VGT_GRP_2D_COPY_RECT_V2 = 0x00000007,
+VGT_GRP_2D_COPY_RECT_V3 = 0x00000008,
+VGT_GRP_2D_FILL_RECT = 0x00000009,
+VGT_GRP_2D_LINE = 0x0000000a,
+VGT_GRP_2D_TRI = 0x0000000b,
+VGT_GRP_PRIM_INDEX_LINE = 0x0000000c,
+VGT_GRP_PRIM_INDEX_TRI = 0x0000000d,
+VGT_GRP_PRIM_INDEX_QUAD = 0x0000000e,
+VGT_GRP_3D_LINE_ADJ = 0x0000000f,
+VGT_GRP_3D_TRI_ADJ = 0x00000010,
+VGT_GRP_3D_PATCH = 0x00000011,
+VGT_GRP_2D_RECT = 0x00000012,
+} VGT_GRP_PRIM_TYPE;
+
+/*
+ * VGT_GRP_PRIM_ORDER enum
+ */
+
+typedef enum VGT_GRP_PRIM_ORDER {
+VGT_GRP_LIST = 0x00000000,
+VGT_GRP_STRIP = 0x00000001,
+VGT_GRP_FAN = 0x00000002,
+VGT_GRP_LOOP = 0x00000003,
+VGT_GRP_POLYGON = 0x00000004,
+} VGT_GRP_PRIM_ORDER;
+
+/*
+ * VGT_GROUP_CONV_SEL enum
+ */
+
+typedef enum VGT_GROUP_CONV_SEL {
+VGT_GRP_INDEX_16 = 0x00000000,
+VGT_GRP_INDEX_32 = 0x00000001,
+VGT_GRP_UINT_16 = 0x00000002,
+VGT_GRP_UINT_32 = 0x00000003,
+VGT_GRP_SINT_16 = 0x00000004,
+VGT_GRP_SINT_32 = 0x00000005,
+VGT_GRP_FLOAT_32 = 0x00000006,
+VGT_GRP_AUTO_PRIM = 0x00000007,
+VGT_GRP_FIX_1_23_TO_FLOAT = 0x00000008,
+} VGT_GROUP_CONV_SEL;
+
+/*
+ * VGT_GS_MODE_TYPE enum
+ */
+
+typedef enum VGT_GS_MODE_TYPE {
+GS_OFF = 0x00000000,
+GS_SCENARIO_A = 0x00000001,
+GS_SCENARIO_B = 0x00000002,
+GS_SCENARIO_G = 0x00000003,
+GS_SCENARIO_C = 0x00000004,
+SPRITE_EN = 0x00000005,
+} VGT_GS_MODE_TYPE;
+
+/*
+ * VGT_GS_CUT_MODE enum
+ */
+
+typedef enum VGT_GS_CUT_MODE {
+GS_CUT_1024 = 0x00000000,
+GS_CUT_512 = 0x00000001,
+GS_CUT_256 = 0x00000002,
+GS_CUT_128 = 0x00000003,
+} VGT_GS_CUT_MODE;
+
+/*
+ * VGT_GS_OUTPRIM_TYPE enum
+ */
+
+typedef enum VGT_GS_OUTPRIM_TYPE {
+POINTLIST = 0x00000000,
+LINESTRIP = 0x00000001,
+TRISTRIP = 0x00000002,
+RECTLIST = 0x00000003,
+} VGT_GS_OUTPRIM_TYPE;
+
+/*
+ * VGT_CACHE_INVALID_MODE enum
+ */
+
+typedef enum VGT_CACHE_INVALID_MODE {
+VC_ONLY = 0x00000000,
+TC_ONLY = 0x00000001,
+VC_AND_TC = 0x00000002,
+} VGT_CACHE_INVALID_MODE;
+
+/*
+ * VGT_TESS_TYPE enum
+ */
+
+typedef enum VGT_TESS_TYPE {
+TESS_ISOLINE = 0x00000000,
+TESS_TRIANGLE = 0x00000001,
+TESS_QUAD = 0x00000002,
+} VGT_TESS_TYPE;
+
+/*
+ * VGT_TESS_PARTITION enum
+ */
+
+typedef enum VGT_TESS_PARTITION {
+PART_INTEGER = 0x00000000,
+PART_POW2 = 0x00000001,
+PART_FRAC_ODD = 0x00000002,
+PART_FRAC_EVEN = 0x00000003,
+} VGT_TESS_PARTITION;
+
+/*
+ * VGT_TESS_TOPOLOGY enum
+ */
+
+typedef enum VGT_TESS_TOPOLOGY {
+OUTPUT_POINT = 0x00000000,
+OUTPUT_LINE = 0x00000001,
+OUTPUT_TRIANGLE_CW = 0x00000002,
+OUTPUT_TRIANGLE_CCW = 0x00000003,
+} VGT_TESS_TOPOLOGY;
+
+/*
+ * VGT_RDREQ_POLICY enum
+ */
+
+typedef enum VGT_RDREQ_POLICY {
+VGT_POLICY_LRU = 0x00000000,
+VGT_POLICY_STREAM = 0x00000001,
+} VGT_RDREQ_POLICY;
+
+/*
+ * VGT_DIST_MODE enum
+ */
+
+typedef enum VGT_DIST_MODE {
+NO_DIST = 0x00000000,
+PATCHES = 0x00000001,
+DONUTS = 0x00000002,
+TRAPEZOIDS = 0x00000003,
+} VGT_DIST_MODE;
+
+/*
+ * VGT_STAGES_LS_EN enum
+ */
+
+typedef enum VGT_STAGES_LS_EN {
+LS_STAGE_OFF = 0x00000000,
+LS_STAGE_ON = 0x00000001,
+CS_STAGE_ON = 0x00000002,
+RESERVED_LS = 0x00000003,
+} VGT_STAGES_LS_EN;
+
+/*
+ * VGT_STAGES_HS_EN enum
+ */
+
+typedef enum VGT_STAGES_HS_EN {
+HS_STAGE_OFF = 0x00000000,
+HS_STAGE_ON = 0x00000001,
+} VGT_STAGES_HS_EN;
+
+/*
+ * VGT_STAGES_ES_EN enum
+ */
+
+typedef enum VGT_STAGES_ES_EN {
+ES_STAGE_OFF = 0x00000000,
+ES_STAGE_DS = 0x00000001,
+ES_STAGE_REAL = 0x00000002,
+RESERVED_ES = 0x00000003,
+} VGT_STAGES_ES_EN;
+
+/*
+ * VGT_STAGES_GS_EN enum
+ */
+
+typedef enum VGT_STAGES_GS_EN {
+GS_STAGE_OFF = 0x00000000,
+GS_STAGE_ON = 0x00000001,
+} VGT_STAGES_GS_EN;
+
+/*
+ * VGT_STAGES_VS_EN enum
+ */
+
+typedef enum VGT_STAGES_VS_EN {
+VS_STAGE_REAL = 0x00000000,
+VS_STAGE_DS = 0x00000001,
+VS_STAGE_COPY_SHADER = 0x00000002,
+RESERVED_VS = 0x00000003,
+} VGT_STAGES_VS_EN;
+
+/*
+ * VGT_PERFCOUNT_SELECT enum
+ */
+
+typedef enum VGT_PERFCOUNT_SELECT {
+vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0x00000000,
+vgt_perf_VGT_SPI_ESVERT_VALID = 0x00000001,
+vgt_perf_VGT_SPI_ESVERT_EOV = 0x00000002,
+vgt_perf_VGT_SPI_ESVERT_STALLED = 0x00000003,
+vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 0x00000004,
+vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 0x00000005,
+vgt_perf_VGT_SPI_ESVERT_STATIC = 0x00000006,
+vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT = 0x00000007,
+vgt_perf_VGT_SPI_ESTHREAD_SEND = 0x00000008,
+vgt_perf_VGT_SPI_GSPRIM_VALID = 0x00000009,
+vgt_perf_VGT_SPI_GSPRIM_EOV = 0x0000000a,
+vgt_perf_VGT_SPI_GSPRIM_CONT = 0x0000000b,
+vgt_perf_VGT_SPI_GSPRIM_STALLED = 0x0000000c,
+vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 0x0000000d,
+vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 0x0000000e,
+vgt_perf_VGT_SPI_GSPRIM_STATIC = 0x0000000f,
+vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 0x00000010,
+vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT = 0x00000011,
+vgt_perf_VGT_SPI_GSTHREAD_SEND = 0x00000012,
+vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 0x00000013,
+vgt_perf_VGT_SPI_VSVERT_SEND = 0x00000014,
+vgt_perf_VGT_SPI_VSVERT_EOV = 0x00000015,
+vgt_perf_VGT_SPI_VSVERT_STALLED = 0x00000016,
+vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 0x00000017,
+vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 0x00000018,
+vgt_perf_VGT_SPI_VSVERT_STATIC = 0x00000019,
+vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT = 0x0000001a,
+vgt_perf_VGT_SPI_VSTHREAD_SEND = 0x0000001b,
+vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 0x0000001c,
+vgt_perf_VGT_PA_CLIPV_SEND = 0x0000001d,
+vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 0x0000001e,
+vgt_perf_VGT_PA_CLIPV_STALLED = 0x0000001f,
+vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 0x00000020,
+vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 0x00000021,
+vgt_perf_VGT_PA_CLIPV_STATIC = 0x00000022,
+vgt_perf_VGT_PA_CLIPP_SEND = 0x00000023,
+vgt_perf_VGT_PA_CLIPP_EOP = 0x00000024,
+vgt_perf_VGT_PA_CLIPP_IS_EVENT = 0x00000025,
+vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 0x00000026,
+vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 0x00000027,
+vgt_perf_VGT_PA_CLIPP_STALLED = 0x00000028,
+vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 0x00000029,
+vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 0x0000002a,
+vgt_perf_VGT_PA_CLIPP_STATIC = 0x0000002b,
+vgt_perf_VGT_PA_CLIPS_SEND = 0x0000002c,
+vgt_perf_VGT_PA_CLIPS_STALLED = 0x0000002d,
+vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 0x0000002e,
+vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 0x0000002f,
+vgt_perf_VGT_PA_CLIPS_STATIC = 0x00000030,
+vgt_perf_vsvert_ds_send = 0x00000031,
+vgt_perf_vsvert_api_send = 0x00000032,
+vgt_perf_hs_tif_stall = 0x00000033,
+vgt_perf_hs_input_stall = 0x00000034,
+vgt_perf_hs_interface_stall = 0x00000035,
+vgt_perf_hs_tfm_stall = 0x00000036,
+vgt_perf_te11_starved = 0x00000037,
+vgt_perf_gs_event_stall = 0x00000038,
+vgt_perf_vgt_pa_clipp_send_not_event = 0x00000039,
+vgt_perf_vgt_pa_clipp_valid_prim = 0x0000003a,
+vgt_perf_reused_es_indices = 0x0000003b,
+vgt_perf_vs_cache_hits = 0x0000003c,
+vgt_perf_gs_cache_hits = 0x0000003d,
+vgt_perf_ds_cache_hits = 0x0000003e,
+vgt_perf_total_cache_hits = 0x0000003f,
+vgt_perf_vgt_busy = 0x00000040,
+vgt_perf_vgt_gs_busy = 0x00000041,
+vgt_perf_esvert_stalled_es_tbl = 0x00000042,
+vgt_perf_esvert_stalled_gs_tbl = 0x00000043,
+vgt_perf_esvert_stalled_gs_event = 0x00000044,
+vgt_perf_esvert_stalled_gsprim = 0x00000045,
+vgt_perf_gsprim_stalled_es_tbl = 0x00000046,
+vgt_perf_gsprim_stalled_gs_tbl = 0x00000047,
+vgt_perf_gsprim_stalled_gs_event = 0x00000048,
+vgt_perf_gsprim_stalled_esvert = 0x00000049,
+vgt_perf_esthread_stalled_es_rb_full = 0x0000004a,
+vgt_perf_esthread_stalled_spi_bp = 0x0000004b,
+vgt_perf_counters_avail_stalled = 0x0000004c,
+vgt_perf_gs_rb_space_avail_stalled = 0x0000004d,
+vgt_perf_gs_issue_rtr_stalled = 0x0000004e,
+vgt_perf_gsthread_stalled = 0x0000004f,
+vgt_perf_strmout_stalled = 0x00000050,
+vgt_perf_wait_for_es_done_stalled = 0x00000051,
+vgt_perf_cm_stalled_by_gog = 0x00000052,
+vgt_perf_cm_reading_stalled = 0x00000053,
+vgt_perf_cm_stalled_by_gsfetch_done = 0x00000054,
+vgt_perf_gog_vs_tbl_stalled = 0x00000055,
+vgt_perf_gog_out_indx_stalled = 0x00000056,
+vgt_perf_gog_out_prim_stalled = 0x00000057,
+vgt_perf_waveid_stalled = 0x00000058,
+vgt_perf_gog_busy = 0x00000059,
+vgt_perf_reused_vs_indices = 0x0000005a,
+vgt_perf_sclk_reg_vld_event = 0x0000005b,
+vgt_perf_vs_conflicting_indices = 0x0000005c,
+vgt_perf_sclk_core_vld_event = 0x0000005d,
+vgt_perf_hswave_stalled = 0x0000005e,
+vgt_perf_sclk_gs_vld_event = 0x0000005f,
+vgt_perf_VGT_SPI_LSVERT_VALID = 0x00000060,
+vgt_perf_VGT_SPI_LSVERT_EOV = 0x00000061,
+vgt_perf_VGT_SPI_LSVERT_STALLED = 0x00000062,
+vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY = 0x00000063,
+vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE = 0x00000064,
+vgt_perf_VGT_SPI_LSVERT_STATIC = 0x00000065,
+vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 0x00000066,
+vgt_perf_VGT_SPI_LSWAVE_IS_EVENT = 0x00000067,
+vgt_perf_VGT_SPI_LSWAVE_SEND = 0x00000068,
+vgt_perf_VGT_SPI_HSVERT_VALID = 0x00000069,
+vgt_perf_VGT_SPI_HSVERT_EOV = 0x0000006a,
+vgt_perf_VGT_SPI_HSVERT_STALLED = 0x0000006b,
+vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY = 0x0000006c,
+vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE = 0x0000006d,
+vgt_perf_VGT_SPI_HSVERT_STATIC = 0x0000006e,
+vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 0x0000006f,
+vgt_perf_VGT_SPI_HSWAVE_IS_EVENT = 0x00000070,
+vgt_perf_VGT_SPI_HSWAVE_SEND = 0x00000071,
+vgt_perf_ds_prims = 0x00000072,
+vgt_perf_ds_RESERVED = 0x00000073,
+vgt_perf_ls_thread_groups = 0x00000074,
+vgt_perf_hs_thread_groups = 0x00000075,
+vgt_perf_es_thread_groups = 0x00000076,
+vgt_perf_vs_thread_groups = 0x00000077,
+vgt_perf_ls_done_latency = 0x00000078,
+vgt_perf_hs_done_latency = 0x00000079,
+vgt_perf_es_done_latency = 0x0000007a,
+vgt_perf_gs_done_latency = 0x0000007b,
+vgt_perf_vgt_hs_busy = 0x0000007c,
+vgt_perf_vgt_te11_busy = 0x0000007d,
+vgt_perf_ls_flush = 0x0000007e,
+vgt_perf_hs_flush = 0x0000007f,
+vgt_perf_es_flush = 0x00000080,
+vgt_perf_vgt_pa_clipp_eopg = 0x00000081,
+vgt_perf_ls_done = 0x00000082,
+vgt_perf_hs_done = 0x00000083,
+vgt_perf_es_done = 0x00000084,
+vgt_perf_gs_done = 0x00000085,
+vgt_perf_vsfetch_done = 0x00000086,
+vgt_perf_gs_done_received = 0x00000087,
+vgt_perf_es_ring_high_water_mark = 0x00000088,
+vgt_perf_gs_ring_high_water_mark = 0x00000089,
+vgt_perf_vs_table_high_water_mark = 0x0000008a,
+vgt_perf_hs_tgs_active_high_water_mark = 0x0000008b,
+vgt_perf_pa_clipp_dealloc = 0x0000008c,
+vgt_perf_cut_mem_flush_stalled = 0x0000008d,
+vgt_perf_vsvert_work_received = 0x0000008e,
+vgt_perf_vgt_pa_clipp_starved_after_work = 0x0000008f,
+vgt_perf_te11_con_starved_after_work = 0x00000090,
+vgt_perf_hs_waiting_on_ls_done_stall = 0x00000091,
+vgt_spi_vsvert_valid = 0x00000092,
+} VGT_PERFCOUNT_SELECT;
+
+/*
+ * IA_PERFCOUNT_SELECT enum
+ */
+
+typedef enum IA_PERFCOUNT_SELECT {
+ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE = 0x00000000,
+ia_perf_dma_data_fifo_full = 0x00000001,
+ia_perf_RESERVED1 = 0x00000002,
+ia_perf_RESERVED2 = 0x00000003,
+ia_perf_RESERVED3 = 0x00000004,
+ia_perf_RESERVED4 = 0x00000005,
+ia_perf_RESERVED5 = 0x00000006,
+ia_perf_MC_LAT_BIN_0 = 0x00000007,
+ia_perf_MC_LAT_BIN_1 = 0x00000008,
+ia_perf_MC_LAT_BIN_2 = 0x00000009,
+ia_perf_MC_LAT_BIN_3 = 0x0000000a,
+ia_perf_MC_LAT_BIN_4 = 0x0000000b,
+ia_perf_MC_LAT_BIN_5 = 0x0000000c,
+ia_perf_MC_LAT_BIN_6 = 0x0000000d,
+ia_perf_MC_LAT_BIN_7 = 0x0000000e,
+ia_perf_ia_busy = 0x0000000f,
+ia_perf_ia_sclk_reg_vld_event = 0x00000010,
+ia_perf_RESERVED6 = 0x00000011,
+ia_perf_ia_sclk_core_vld_event = 0x00000012,
+ia_perf_RESERVED7 = 0x00000013,
+ia_perf_ia_dma_return = 0x00000014,
+ia_perf_ia_stalled = 0x00000015,
+ia_perf_shift_starved_pipe0_event = 0x00000016,
+ia_perf_shift_starved_pipe1_event = 0x00000017,
+} IA_PERFCOUNT_SELECT;
+
+/*
+ * WD_PERFCOUNT_SELECT enum
+ */
+
+typedef enum WD_PERFCOUNT_SELECT {
+wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0x00000000,
+wd_perf_RBIU_DR_FIFO_STARVED = 0x00000001,
+wd_perf_RBIU_DR_FIFO_STALLED = 0x00000002,
+wd_perf_RBIU_DI_FIFO_STARVED = 0x00000003,
+wd_perf_RBIU_DI_FIFO_STALLED = 0x00000004,
+wd_perf_wd_busy = 0x00000005,
+wd_perf_wd_sclk_reg_vld_event = 0x00000006,
+wd_perf_wd_sclk_input_vld_event = 0x00000007,
+wd_perf_wd_sclk_core_vld_event = 0x00000008,
+wd_perf_wd_stalled = 0x00000009,
+wd_perf_inside_tf_bin_0 = 0x0000000a,
+wd_perf_inside_tf_bin_1 = 0x0000000b,
+wd_perf_inside_tf_bin_2 = 0x0000000c,
+wd_perf_inside_tf_bin_3 = 0x0000000d,
+wd_perf_inside_tf_bin_4 = 0x0000000e,
+wd_perf_inside_tf_bin_5 = 0x0000000f,
+wd_perf_inside_tf_bin_6 = 0x00000010,
+wd_perf_inside_tf_bin_7 = 0x00000011,
+wd_perf_inside_tf_bin_8 = 0x00000012,
+wd_perf_tfreq_lat_bin_0 = 0x00000013,
+wd_perf_tfreq_lat_bin_1 = 0x00000014,
+wd_perf_tfreq_lat_bin_2 = 0x00000015,
+wd_perf_tfreq_lat_bin_3 = 0x00000016,
+wd_perf_tfreq_lat_bin_4 = 0x00000017,
+wd_perf_tfreq_lat_bin_5 = 0x00000018,
+wd_perf_tfreq_lat_bin_6 = 0x00000019,
+wd_perf_tfreq_lat_bin_7 = 0x0000001a,
+wd_starved_on_hs_done = 0x0000001b,
+wd_perf_se0_hs_done_latency = 0x0000001c,
+wd_perf_se1_hs_done_latency = 0x0000001d,
+wd_perf_se2_hs_done_latency = 0x0000001e,
+wd_perf_se3_hs_done_latency = 0x0000001f,
+wd_perf_hs_done_se0 = 0x00000020,
+wd_perf_hs_done_se1 = 0x00000021,
+wd_perf_hs_done_se2 = 0x00000022,
+wd_perf_hs_done_se3 = 0x00000023,
+wd_perf_null_patches = 0x00000024,
+} WD_PERFCOUNT_SELECT;
+
+/*
+ * WD_IA_DRAW_TYPE enum
+ */
+
+typedef enum WD_IA_DRAW_TYPE {
+WD_IA_DRAW_TYPE_DI_MM0 = 0x00000000,
+WD_IA_DRAW_TYPE_REG_XFER = 0x00000001,
+WD_IA_DRAW_TYPE_EVENT_INIT = 0x00000002,
+WD_IA_DRAW_TYPE_EVENT_ADDR = 0x00000003,
+WD_IA_DRAW_TYPE_MIN_INDX = 0x00000004,
+WD_IA_DRAW_TYPE_MAX_INDX = 0x00000005,
+WD_IA_DRAW_TYPE_INDX_OFF = 0x00000006,
+WD_IA_DRAW_TYPE_IMM_DATA = 0x00000007,
+} WD_IA_DRAW_TYPE;
+
+/*
+ * WD_IA_DRAW_REG_XFER enum
+ */
+
+typedef enum WD_IA_DRAW_REG_XFER {
+WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0x00000000,
+WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 0x00000001,
+} WD_IA_DRAW_REG_XFER;
+
+/*
+ * WD_IA_DRAW_SOURCE enum
+ */
+
+typedef enum WD_IA_DRAW_SOURCE {
+WD_IA_DRAW_SOURCE_DMA = 0x00000000,
+WD_IA_DRAW_SOURCE_IMMD = 0x00000001,
+WD_IA_DRAW_SOURCE_AUTO = 0x00000002,
+WD_IA_DRAW_SOURCE_OPAQ = 0x00000003,
+} WD_IA_DRAW_SOURCE;
+
+/*
+ * GS_THREADID_SIZE value
+ */
+
+#define GSTHREADID_SIZE 0x00000002
+
+/*******************************************************
+ * GB Enums
+ *******************************************************/
+
+/*
+ * GB_EDC_DED_MODE enum
+ */
+
+typedef enum GB_EDC_DED_MODE {
+GB_EDC_DED_MODE_LOG = 0x00000000,
+GB_EDC_DED_MODE_HALT = 0x00000001,
+GB_EDC_DED_MODE_INT_HALT = 0x00000002,
+} GB_EDC_DED_MODE;
+
+/*
+ * VALUE_GB_TILING_CONFIG_TABLE_SIZE value
+ */
+
+#define GB_TILING_CONFIG_TABLE_SIZE 0x00000020
+
+/*
+ * VALUE_GB_TILING_CONFIG_MACROTABLE_SIZE value
+ */
+
+#define GB_TILING_CONFIG_MACROTABLE_SIZE 0x00000010
+
+/*******************************************************
+ * TP Enums
+ *******************************************************/
+
+/*
+ * TA_TC_ADDR_MODES enum
+ */
+
+typedef enum TA_TC_ADDR_MODES {
+TA_TC_ADDR_MODE_DEFAULT = 0x00000000,
+TA_TC_ADDR_MODE_COMP0 = 0x00000001,
+TA_TC_ADDR_MODE_COMP1 = 0x00000002,
+TA_TC_ADDR_MODE_COMP2 = 0x00000003,
+TA_TC_ADDR_MODE_COMP3 = 0x00000004,
+TA_TC_ADDR_MODE_UNALIGNED = 0x00000005,
+TA_TC_ADDR_MODE_BORDER_COLOR = 0x00000006,
+} TA_TC_ADDR_MODES;
+
+/*
+ * TA_PERFCOUNT_SEL enum
+ */
+
+typedef enum TA_PERFCOUNT_SEL {
+TA_PERF_SEL_NULL = 0x00000000,
+TA_PERF_SEL_sh_fifo_busy = 0x00000001,
+TA_PERF_SEL_sh_fifo_cmd_busy = 0x00000002,
+TA_PERF_SEL_sh_fifo_addr_busy = 0x00000003,
+TA_PERF_SEL_sh_fifo_data_busy = 0x00000004,
+TA_PERF_SEL_sh_fifo_data_sfifo_busy = 0x00000005,
+TA_PERF_SEL_sh_fifo_data_tfifo_busy = 0x00000006,
+TA_PERF_SEL_gradient_busy = 0x00000007,
+TA_PERF_SEL_gradient_fifo_busy = 0x00000008,
+TA_PERF_SEL_lod_busy = 0x00000009,
+TA_PERF_SEL_lod_fifo_busy = 0x0000000a,
+TA_PERF_SEL_addresser_busy = 0x0000000b,
+TA_PERF_SEL_addresser_fifo_busy = 0x0000000c,
+TA_PERF_SEL_aligner_busy = 0x0000000d,
+TA_PERF_SEL_write_path_busy = 0x0000000e,
+TA_PERF_SEL_ta_busy = 0x0000000f,
+TA_PERF_SEL_sq_ta_cmd_cycles = 0x00000010,
+TA_PERF_SEL_sp_ta_addr_cycles = 0x00000011,
+TA_PERF_SEL_sp_ta_data_cycles = 0x00000012,
+TA_PERF_SEL_ta_fa_data_state_cycles = 0x00000013,
+TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 0x00000014,
+TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 0x00000015,
+TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles = 0x00000016,
+TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles = 0x00000017,
+TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles = 0x00000018,
+TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles = 0x00000019,
+TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles = 0x0000001a,
+TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles = 0x0000001b,
+TA_PERF_SEL_RESERVED_28 = 0x0000001c,
+TA_PERF_SEL_RESERVED_29 = 0x0000001d,
+TA_PERF_SEL_sh_fifo_addr_cycles = 0x0000001e,
+TA_PERF_SEL_sh_fifo_data_cycles = 0x0000001f,
+TA_PERF_SEL_total_wavefronts = 0x00000020,
+TA_PERF_SEL_gradient_cycles = 0x00000021,
+TA_PERF_SEL_walker_cycles = 0x00000022,
+TA_PERF_SEL_aligner_cycles = 0x00000023,
+TA_PERF_SEL_image_wavefronts = 0x00000024,
+TA_PERF_SEL_image_read_wavefronts = 0x00000025,
+TA_PERF_SEL_image_write_wavefronts = 0x00000026,
+TA_PERF_SEL_image_atomic_wavefronts = 0x00000027,
+TA_PERF_SEL_image_total_cycles = 0x00000028,
+TA_PERF_SEL_RESERVED_41 = 0x00000029,
+TA_PERF_SEL_RESERVED_42 = 0x0000002a,
+TA_PERF_SEL_RESERVED_43 = 0x0000002b,
+TA_PERF_SEL_buffer_wavefronts = 0x0000002c,
+TA_PERF_SEL_buffer_read_wavefronts = 0x0000002d,
+TA_PERF_SEL_buffer_write_wavefronts = 0x0000002e,
+TA_PERF_SEL_buffer_atomic_wavefronts = 0x0000002f,
+TA_PERF_SEL_buffer_coalescable_wavefronts = 0x00000030,
+TA_PERF_SEL_buffer_total_cycles = 0x00000031,
+TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles = 0x00000032,
+TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles = 0x00000033,
+TA_PERF_SEL_buffer_coalesced_read_cycles = 0x00000034,
+TA_PERF_SEL_buffer_coalesced_write_cycles = 0x00000035,
+TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x00000036,
+TA_PERF_SEL_addr_stalled_by_td_cycles = 0x00000037,
+TA_PERF_SEL_data_stalled_by_tc_cycles = 0x00000038,
+TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 0x00000039,
+TA_PERF_SEL_addresser_stalled_cycles = 0x0000003a,
+TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 0x0000003b,
+TA_PERF_SEL_aniso_stalled_cycles = 0x0000003c,
+TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x0000003d,
+TA_PERF_SEL_deriv_stalled_cycles = 0x0000003e,
+TA_PERF_SEL_aniso_gt1_cycle_quads = 0x0000003f,
+TA_PERF_SEL_color_1_cycle_pixels = 0x00000040,
+TA_PERF_SEL_color_2_cycle_pixels = 0x00000041,
+TA_PERF_SEL_color_3_cycle_pixels = 0x00000042,
+TA_PERF_SEL_color_4_cycle_pixels = 0x00000043,
+TA_PERF_SEL_mip_1_cycle_pixels = 0x00000044,
+TA_PERF_SEL_mip_2_cycle_pixels = 0x00000045,
+TA_PERF_SEL_vol_1_cycle_pixels = 0x00000046,
+TA_PERF_SEL_vol_2_cycle_pixels = 0x00000047,
+TA_PERF_SEL_bilin_point_1_cycle_pixels = 0x00000048,
+TA_PERF_SEL_mipmap_lod_0_samples = 0x00000049,
+TA_PERF_SEL_mipmap_lod_1_samples = 0x0000004a,
+TA_PERF_SEL_mipmap_lod_2_samples = 0x0000004b,
+TA_PERF_SEL_mipmap_lod_3_samples = 0x0000004c,
+TA_PERF_SEL_mipmap_lod_4_samples = 0x0000004d,
+TA_PERF_SEL_mipmap_lod_5_samples = 0x0000004e,
+TA_PERF_SEL_mipmap_lod_6_samples = 0x0000004f,
+TA_PERF_SEL_mipmap_lod_7_samples = 0x00000050,
+TA_PERF_SEL_mipmap_lod_8_samples = 0x00000051,
+TA_PERF_SEL_mipmap_lod_9_samples = 0x00000052,
+TA_PERF_SEL_mipmap_lod_10_samples = 0x00000053,
+TA_PERF_SEL_mipmap_lod_11_samples = 0x00000054,
+TA_PERF_SEL_mipmap_lod_12_samples = 0x00000055,
+TA_PERF_SEL_mipmap_lod_13_samples = 0x00000056,
+TA_PERF_SEL_mipmap_lod_14_samples = 0x00000057,
+TA_PERF_SEL_mipmap_invalid_samples = 0x00000058,
+TA_PERF_SEL_aniso_1_cycle_quads = 0x00000059,
+TA_PERF_SEL_aniso_2_cycle_quads = 0x0000005a,
+TA_PERF_SEL_aniso_4_cycle_quads = 0x0000005b,
+TA_PERF_SEL_aniso_6_cycle_quads = 0x0000005c,
+TA_PERF_SEL_aniso_8_cycle_quads = 0x0000005d,
+TA_PERF_SEL_aniso_10_cycle_quads = 0x0000005e,
+TA_PERF_SEL_aniso_12_cycle_quads = 0x0000005f,
+TA_PERF_SEL_aniso_14_cycle_quads = 0x00000060,
+TA_PERF_SEL_aniso_16_cycle_quads = 0x00000061,
+TA_PERF_SEL_write_path_input_cycles = 0x00000062,
+TA_PERF_SEL_write_path_output_cycles = 0x00000063,
+TA_PERF_SEL_flat_wavefronts = 0x00000064,
+TA_PERF_SEL_flat_read_wavefronts = 0x00000065,
+TA_PERF_SEL_flat_write_wavefronts = 0x00000066,
+TA_PERF_SEL_flat_atomic_wavefronts = 0x00000067,
+TA_PERF_SEL_flat_coalesceable_wavefronts = 0x00000068,
+TA_PERF_SEL_reg_sclk_vld = 0x00000069,
+TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x0000006a,
+TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x0000006b,
+TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 0x0000006c,
+TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x0000006d,
+TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x0000006e,
+TA_PERF_SEL_xnack_on_phase0 = 0x0000006f,
+TA_PERF_SEL_xnack_on_phase1 = 0x00000070,
+TA_PERF_SEL_xnack_on_phase2 = 0x00000071,
+TA_PERF_SEL_xnack_on_phase3 = 0x00000072,
+TA_PERF_SEL_first_xnack_on_phase0 = 0x00000073,
+TA_PERF_SEL_first_xnack_on_phase1 = 0x00000074,
+TA_PERF_SEL_first_xnack_on_phase2 = 0x00000075,
+TA_PERF_SEL_first_xnack_on_phase3 = 0x00000076,
+} TA_PERFCOUNT_SEL;
+
+/*
+ * TD_PERFCOUNT_SEL enum
+ */
+
+typedef enum TD_PERFCOUNT_SEL {
+TD_PERF_SEL_none = 0x00000000,
+TD_PERF_SEL_td_busy = 0x00000001,
+TD_PERF_SEL_input_busy = 0x00000002,
+TD_PERF_SEL_output_busy = 0x00000003,
+TD_PERF_SEL_lerp_busy = 0x00000004,
+TD_PERF_SEL_reg_sclk_vld = 0x00000005,
+TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x00000006,
+TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x00000007,
+TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x00000008,
+TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x00000009,
+TD_PERF_SEL_tc_td_fifo_full = 0x0000000a,
+TD_PERF_SEL_constant_state_full = 0x0000000b,
+TD_PERF_SEL_sample_state_full = 0x0000000c,
+TD_PERF_SEL_output_fifo_full = 0x0000000d,
+TD_PERF_SEL_RESERVED_14 = 0x0000000e,
+TD_PERF_SEL_tc_stall = 0x0000000f,
+TD_PERF_SEL_pc_stall = 0x00000010,
+TD_PERF_SEL_gds_stall = 0x00000011,
+TD_PERF_SEL_RESERVED_18 = 0x00000012,
+TD_PERF_SEL_RESERVED_19 = 0x00000013,
+TD_PERF_SEL_gather4_wavefront = 0x00000014,
+TD_PERF_SEL_gather4h_wavefront = 0x00000015,
+TD_PERF_SEL_gather4h_packed_wavefront = 0x00000016,
+TD_PERF_SEL_gather8h_packed_wavefront = 0x00000017,
+TD_PERF_SEL_sample_c_wavefront = 0x00000018,
+TD_PERF_SEL_load_wavefront = 0x00000019,
+TD_PERF_SEL_atomic_wavefront = 0x0000001a,
+TD_PERF_SEL_store_wavefront = 0x0000001b,
+TD_PERF_SEL_ldfptr_wavefront = 0x0000001c,
+TD_PERF_SEL_d16_en_wavefront = 0x0000001d,
+TD_PERF_SEL_bypass_filter_wavefront = 0x0000001e,
+TD_PERF_SEL_min_max_filter_wavefront = 0x0000001f,
+TD_PERF_SEL_coalescable_wavefront = 0x00000020,
+TD_PERF_SEL_coalesced_phase = 0x00000021,
+TD_PERF_SEL_four_phase_wavefront = 0x00000022,
+TD_PERF_SEL_eight_phase_wavefront = 0x00000023,
+TD_PERF_SEL_sixteen_phase_wavefront = 0x00000024,
+TD_PERF_SEL_four_phase_forward_wavefront = 0x00000025,
+TD_PERF_SEL_write_ack_wavefront = 0x00000026,
+TD_PERF_SEL_RESERVED_39 = 0x00000027,
+TD_PERF_SEL_user_defined_border = 0x00000028,
+TD_PERF_SEL_white_border = 0x00000029,
+TD_PERF_SEL_opaque_black_border = 0x0000002a,
+TD_PERF_SEL_RESERVED_43 = 0x0000002b,
+TD_PERF_SEL_RESERVED_44 = 0x0000002c,
+TD_PERF_SEL_nack = 0x0000002d,
+TD_PERF_SEL_td_sp_traffic = 0x0000002e,
+TD_PERF_SEL_consume_gds_traffic = 0x0000002f,
+TD_PERF_SEL_addresscmd_poison = 0x00000030,
+TD_PERF_SEL_data_poison = 0x00000031,
+TD_PERF_SEL_start_cycle_0 = 0x00000032,
+TD_PERF_SEL_start_cycle_1 = 0x00000033,
+TD_PERF_SEL_start_cycle_2 = 0x00000034,
+TD_PERF_SEL_start_cycle_3 = 0x00000035,
+TD_PERF_SEL_null_cycle_output = 0x00000036,
+TD_PERF_SEL_d16_data_packed = 0x00000037,
+TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt = 0x00000038,
+} TD_PERFCOUNT_SEL;
+
+/*
+ * TCP_PERFCOUNT_SELECT enum
+ */
+
+typedef enum TCP_PERFCOUNT_SELECT {
+TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0x00000000,
+TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 0x00000001,
+TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 0x00000002,
+TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 0x00000003,
+TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 0x00000004,
+TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 0x00000005,
+TCP_PERF_SEL_LOD_STALL_CYCLES = 0x00000006,
+TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 0x00000007,
+TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 0x00000008,
+TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 0x00000009,
+TCP_PERF_SEL_ALLOC_STALL_CYCLES = 0x0000000a,
+TCP_PERF_SEL_LFIFO_STALL_CYCLES = 0x0000000b,
+TCP_PERF_SEL_RFIFO_STALL_CYCLES = 0x0000000c,
+TCP_PERF_SEL_TCR_RDRET_STALL = 0x0000000d,
+TCP_PERF_SEL_WRITE_CONFLICT_STALL = 0x0000000e,
+TCP_PERF_SEL_HOLE_READ_STALL = 0x0000000f,
+TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 0x00000010,
+TCP_PERF_SEL_PENDING_STALL_CYCLES = 0x00000011,
+TCP_PERF_SEL_READFIFO_STALL_CYCLES = 0x00000012,
+TCP_PERF_SEL_TCP_LATENCY = 0x00000013,
+TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 0x00000014,
+TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 0x00000015,
+TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 0x00000016,
+TCP_PERF_SEL_TCC_READ_REQ = 0x00000017,
+TCP_PERF_SEL_TCC_WRITE_REQ = 0x00000018,
+TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 0x00000019,
+TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 0x0000001a,
+TCP_PERF_SEL_TOTAL_LOCAL_READ = 0x0000001b,
+TCP_PERF_SEL_TOTAL_GLOBAL_READ = 0x0000001c,
+TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 0x0000001d,
+TCP_PERF_SEL_TOTAL_GLOBAL_WRITE = 0x0000001e,
+TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 0x0000001f,
+TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 0x00000020,
+TCP_PERF_SEL_TOTAL_WBINVL1 = 0x00000021,
+TCP_PERF_SEL_IMG_READ_FMT_1 = 0x00000022,
+TCP_PERF_SEL_IMG_READ_FMT_8 = 0x00000023,
+TCP_PERF_SEL_IMG_READ_FMT_16 = 0x00000024,
+TCP_PERF_SEL_IMG_READ_FMT_32 = 0x00000025,
+TCP_PERF_SEL_IMG_READ_FMT_32_AS_8 = 0x00000026,
+TCP_PERF_SEL_IMG_READ_FMT_32_AS_16 = 0x00000027,
+TCP_PERF_SEL_IMG_READ_FMT_32_AS_128 = 0x00000028,
+TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE = 0x00000029,
+TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE = 0x0000002a,
+TCP_PERF_SEL_IMG_READ_FMT_96 = 0x0000002b,
+TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE = 0x0000002c,
+TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE = 0x0000002d,
+TCP_PERF_SEL_IMG_READ_FMT_BC1 = 0x0000002e,
+TCP_PERF_SEL_IMG_READ_FMT_BC2 = 0x0000002f,
+TCP_PERF_SEL_IMG_READ_FMT_BC3 = 0x00000030,
+TCP_PERF_SEL_IMG_READ_FMT_BC4 = 0x00000031,
+TCP_PERF_SEL_IMG_READ_FMT_BC5 = 0x00000032,
+TCP_PERF_SEL_IMG_READ_FMT_BC6 = 0x00000033,
+TCP_PERF_SEL_IMG_READ_FMT_BC7 = 0x00000034,
+TCP_PERF_SEL_IMG_READ_FMT_I8 = 0x00000035,
+TCP_PERF_SEL_IMG_READ_FMT_I16 = 0x00000036,
+TCP_PERF_SEL_IMG_READ_FMT_I32 = 0x00000037,
+TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8 = 0x00000038,
+TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16 = 0x00000039,
+TCP_PERF_SEL_IMG_READ_FMT_D8 = 0x0000003a,
+TCP_PERF_SEL_IMG_READ_FMT_D16 = 0x0000003b,
+TCP_PERF_SEL_IMG_READ_FMT_D32 = 0x0000003c,
+TCP_PERF_SEL_IMG_WRITE_FMT_8 = 0x0000003d,
+TCP_PERF_SEL_IMG_WRITE_FMT_16 = 0x0000003e,
+TCP_PERF_SEL_IMG_WRITE_FMT_32 = 0x0000003f,
+TCP_PERF_SEL_IMG_WRITE_FMT_64 = 0x00000040,
+TCP_PERF_SEL_IMG_WRITE_FMT_128 = 0x00000041,
+TCP_PERF_SEL_IMG_WRITE_FMT_D8 = 0x00000042,
+TCP_PERF_SEL_IMG_WRITE_FMT_D16 = 0x00000043,
+TCP_PERF_SEL_IMG_WRITE_FMT_D32 = 0x00000044,
+TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32 = 0x00000045,
+TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32 = 0x00000046,
+TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64 = 0x00000047,
+TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64 = 0x00000048,
+TCP_PERF_SEL_BUF_READ_FMT_8 = 0x00000049,
+TCP_PERF_SEL_BUF_READ_FMT_16 = 0x0000004a,
+TCP_PERF_SEL_BUF_READ_FMT_32 = 0x0000004b,
+TCP_PERF_SEL_BUF_WRITE_FMT_8 = 0x0000004c,
+TCP_PERF_SEL_BUF_WRITE_FMT_16 = 0x0000004d,
+TCP_PERF_SEL_BUF_WRITE_FMT_32 = 0x0000004e,
+TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32 = 0x0000004f,
+TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32 = 0x00000050,
+TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64 = 0x00000051,
+TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64 = 0x00000052,
+TCP_PERF_SEL_ARR_LINEAR_GENERAL = 0x00000053,
+TCP_PERF_SEL_ARR_LINEAR_ALIGNED = 0x00000054,
+TCP_PERF_SEL_ARR_1D_THIN1 = 0x00000055,
+TCP_PERF_SEL_ARR_1D_THICK = 0x00000056,
+TCP_PERF_SEL_ARR_2D_THIN1 = 0x00000057,
+TCP_PERF_SEL_ARR_2D_THICK = 0x00000058,
+TCP_PERF_SEL_ARR_2D_XTHICK = 0x00000059,
+TCP_PERF_SEL_ARR_3D_THIN1 = 0x0000005a,
+TCP_PERF_SEL_ARR_3D_THICK = 0x0000005b,
+TCP_PERF_SEL_ARR_3D_XTHICK = 0x0000005c,
+TCP_PERF_SEL_DIM_1D = 0x0000005d,
+TCP_PERF_SEL_DIM_2D = 0x0000005e,
+TCP_PERF_SEL_DIM_3D = 0x0000005f,
+TCP_PERF_SEL_DIM_1D_ARRAY = 0x00000060,
+TCP_PERF_SEL_DIM_2D_ARRAY = 0x00000061,
+TCP_PERF_SEL_DIM_2D_MSAA = 0x00000062,
+TCP_PERF_SEL_DIM_2D_ARRAY_MSAA = 0x00000063,
+TCP_PERF_SEL_DIM_CUBE_ARRAY = 0x00000064,
+TCP_PERF_SEL_CP_TCP_INVALIDATE = 0x00000065,
+TCP_PERF_SEL_TA_TCP_STATE_READ = 0x00000066,
+TCP_PERF_SEL_TAGRAM0_REQ = 0x00000067,
+TCP_PERF_SEL_TAGRAM1_REQ = 0x00000068,
+TCP_PERF_SEL_TAGRAM2_REQ = 0x00000069,
+TCP_PERF_SEL_TAGRAM3_REQ = 0x0000006a,
+TCP_PERF_SEL_GATE_EN1 = 0x0000006b,
+TCP_PERF_SEL_GATE_EN2 = 0x0000006c,
+TCP_PERF_SEL_CORE_REG_SCLK_VLD = 0x0000006d,
+TCP_PERF_SEL_TCC_REQ = 0x0000006e,
+TCP_PERF_SEL_TCC_NON_READ_REQ = 0x0000006f,
+TCP_PERF_SEL_TCC_BYPASS_READ_REQ = 0x00000070,
+TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ = 0x00000071,
+TCP_PERF_SEL_TCC_VOLATILE_READ_REQ = 0x00000072,
+TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ = 0x00000073,
+TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ = 0x00000074,
+TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ = 0x00000075,
+TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ = 0x00000076,
+TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ = 0x00000077,
+TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ = 0x00000078,
+TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ = 0x00000079,
+TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ = 0x0000007a,
+TCP_PERF_SEL_TCC_ATOMIC_REQ = 0x0000007b,
+TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ = 0x0000007c,
+TCP_PERF_SEL_TCC_DATA_BUS_BUSY = 0x0000007d,
+TCP_PERF_SEL_TOTAL_ACCESSES = 0x0000007e,
+TCP_PERF_SEL_TOTAL_READ = 0x0000007f,
+TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 0x00000080,
+TCP_PERF_SEL_TOTAL_HIT_EVICT_READ = 0x00000081,
+TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 0x00000082,
+TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 0x00000083,
+TCP_PERF_SEL_TOTAL_NON_READ = 0x00000084,
+TCP_PERF_SEL_TOTAL_WRITE = 0x00000085,
+TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 0x00000086,
+TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 0x00000087,
+TCP_PERF_SEL_TOTAL_WBINVL1_VOL = 0x00000088,
+TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 0x00000089,
+TCP_PERF_SEL_DISPLAY_MICROTILING = 0x0000008a,
+TCP_PERF_SEL_THIN_MICROTILING = 0x0000008b,
+TCP_PERF_SEL_DEPTH_MICROTILING = 0x0000008c,
+TCP_PERF_SEL_ARR_PRT_THIN1 = 0x0000008d,
+TCP_PERF_SEL_ARR_PRT_2D_THIN1 = 0x0000008e,
+TCP_PERF_SEL_ARR_PRT_3D_THIN1 = 0x0000008f,
+TCP_PERF_SEL_ARR_PRT_THICK = 0x00000090,
+TCP_PERF_SEL_ARR_PRT_2D_THICK = 0x00000091,
+TCP_PERF_SEL_ARR_PRT_3D_THICK = 0x00000092,
+TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL = 0x00000093,
+TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL = 0x00000094,
+TCP_PERF_SEL_UNALIGNED = 0x00000095,
+TCP_PERF_SEL_ROTATED_MICROTILING = 0x00000096,
+TCP_PERF_SEL_THICK_MICROTILING = 0x00000097,
+TCP_PERF_SEL_ATC = 0x00000098,
+TCP_PERF_SEL_POWER_STALL = 0x00000099,
+TCP_PERF_SEL_RESERVED_154 = 0x0000009a,
+TCP_PERF_SEL_TCC_LRU_REQ = 0x0000009b,
+TCP_PERF_SEL_TCC_STREAM_REQ = 0x0000009c,
+TCP_PERF_SEL_TCC_NC_READ_REQ = 0x0000009d,
+TCP_PERF_SEL_TCC_NC_WRITE_REQ = 0x0000009e,
+TCP_PERF_SEL_TCC_NC_ATOMIC_REQ = 0x0000009f,
+TCP_PERF_SEL_TCC_UC_READ_REQ = 0x000000a0,
+TCP_PERF_SEL_TCC_UC_WRITE_REQ = 0x000000a1,
+TCP_PERF_SEL_TCC_UC_ATOMIC_REQ = 0x000000a2,
+TCP_PERF_SEL_TCC_CC_READ_REQ = 0x000000a3,
+TCP_PERF_SEL_TCC_CC_WRITE_REQ = 0x000000a4,
+TCP_PERF_SEL_TCC_CC_ATOMIC_REQ = 0x000000a5,
+TCP_PERF_SEL_TCC_DCC_REQ = 0x000000a6,
+TCP_PERF_SEL_TCC_PHYSICAL_REQ = 0x000000a7,
+TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 0x000000a8,
+TCP_PERF_SEL_VOLATILE = 0x000000a9,
+TCP_PERF_SEL_TC_TA_XNACK_STALL = 0x000000aa,
+TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL = 0x000000ab,
+TCP_PERF_SEL_SHOOTDOWN = 0x000000ac,
+TCP_PERF_SEL_UTCL1_TRANSLATION_MISS = 0x000000ad,
+TCP_PERF_SEL_UTCL1_PERMISSION_MISS = 0x000000ae,
+TCP_PERF_SEL_UTCL1_REQUEST = 0x000000af,
+TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 0x000000b0,
+TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 0x000000b1,
+TCP_PERF_SEL_UTCL1_LFIFO_FULL = 0x000000b2,
+TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 0x000000b3,
+TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x000000b4,
+TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT = 0x000000b5,
+TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 0x000000b6,
+TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB = 0x000000b7,
+TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA = 0x000000b8,
+TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1 = 0x000000b9,
+TCP_PERF_SEL_IMG_READ_FMT_ETC2_R = 0x000000ba,
+TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG = 0x000000bb,
+TCP_PERF_SEL_IMG_READ_FMT_8_AS_32 = 0x000000bc,
+TCP_PERF_SEL_IMG_READ_FMT_8_AS_64 = 0x000000bd,
+TCP_PERF_SEL_IMG_READ_FMT_16_AS_64 = 0x000000be,
+TCP_PERF_SEL_IMG_READ_FMT_16_AS_128 = 0x000000bf,
+TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32 = 0x000000c0,
+TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64 = 0x000000c1,
+TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64 = 0x000000c2,
+TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128 = 0x000000c3,
+} TCP_PERFCOUNT_SELECT;
+
+/*
+ * TCP_CACHE_POLICIES enum
+ */
+
+typedef enum TCP_CACHE_POLICIES {
+TCP_CACHE_POLICY_MISS_LRU = 0x00000000,
+TCP_CACHE_POLICY_MISS_EVICT = 0x00000001,
+TCP_CACHE_POLICY_HIT_LRU = 0x00000002,
+TCP_CACHE_POLICY_HIT_EVICT = 0x00000003,
+} TCP_CACHE_POLICIES;
+
+/*
+ * TCP_CACHE_STORE_POLICIES enum
+ */
+
+typedef enum TCP_CACHE_STORE_POLICIES {
+TCP_CACHE_STORE_POLICY_WT_LRU = 0x00000000,
+TCP_CACHE_STORE_POLICY_WT_EVICT = 0x00000001,
+} TCP_CACHE_STORE_POLICIES;
+
+/*
+ * TCP_WATCH_MODES enum
+ */
+
+typedef enum TCP_WATCH_MODES {
+TCP_WATCH_MODE_READ = 0x00000000,
+TCP_WATCH_MODE_NONREAD = 0x00000001,
+TCP_WATCH_MODE_ATOMIC = 0x00000002,
+TCP_WATCH_MODE_ALL = 0x00000003,
+} TCP_WATCH_MODES;
+
+/*
+ * TCP_DSM_DATA_SEL enum
+ */
+
+typedef enum TCP_DSM_DATA_SEL {
+TCP_DSM_DISABLE = 0x00000000,
+TCP_DSM_SEL0 = 0x00000001,
+TCP_DSM_SEL1 = 0x00000002,
+TCP_DSM_SEL_BOTH = 0x00000003,
+} TCP_DSM_DATA_SEL;
+
+/*
+ * TCP_DSM_SINGLE_WRITE enum
+ */
+
+typedef enum TCP_DSM_SINGLE_WRITE {
+TCP_DSM_SINGLE_WRITE_DIS = 0x00000000,
+TCP_DSM_SINGLE_WRITE_EN = 0x00000001,
+} TCP_DSM_SINGLE_WRITE;
+
+/*
+ * TCP_DSM_INJECT_SEL enum
+ */
+
+typedef enum TCP_DSM_INJECT_SEL {
+TCP_DSM_INJECT_SEL0 = 0x00000000,
+TCP_DSM_INJECT_SEL1 = 0x00000001,
+TCP_DSM_INJECT_SEL2 = 0x00000002,
+TCP_DSM_INJECT_SEL3 = 0x00000003,
+} TCP_DSM_INJECT_SEL;
+
+/*******************************************************
+ * TCC Enums
+ *******************************************************/
+
+/*
+ * TCC_PERF_SEL enum
+ */
+
+typedef enum TCC_PERF_SEL {
+TCC_PERF_SEL_NONE = 0x00000000,
+TCC_PERF_SEL_CYCLE = 0x00000001,
+TCC_PERF_SEL_BUSY = 0x00000002,
+TCC_PERF_SEL_REQ = 0x00000003,
+TCC_PERF_SEL_STREAMING_REQ = 0x00000004,
+TCC_PERF_SEL_EXE_REQ = 0x00000005,
+TCC_PERF_SEL_COMPRESSED_REQ = 0x00000006,
+TCC_PERF_SEL_COMPRESSED_0_REQ = 0x00000007,
+TCC_PERF_SEL_METADATA_REQ = 0x00000008,
+TCC_PERF_SEL_NC_VIRTUAL_REQ = 0x00000009,
+TCC_PERF_SEL_UC_VIRTUAL_REQ = 0x0000000a,
+TCC_PERF_SEL_CC_PHYSICAL_REQ = 0x0000000b,
+TCC_PERF_SEL_PROBE = 0x0000000c,
+TCC_PERF_SEL_PROBE_ALL = 0x0000000d,
+TCC_PERF_SEL_READ = 0x0000000e,
+TCC_PERF_SEL_WRITE = 0x0000000f,
+TCC_PERF_SEL_ATOMIC = 0x00000010,
+TCC_PERF_SEL_HIT = 0x00000011,
+TCC_PERF_SEL_SECTOR_HIT = 0x00000012,
+TCC_PERF_SEL_MISS = 0x00000013,
+TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0x00000014,
+TCC_PERF_SEL_FULLY_WRITTEN_HIT = 0x00000015,
+TCC_PERF_SEL_WRITEBACK = 0x00000016,
+TCC_PERF_SEL_LATENCY_FIFO_FULL = 0x00000017,
+TCC_PERF_SEL_SRC_FIFO_FULL = 0x00000018,
+TCC_PERF_SEL_HOLE_FIFO_FULL = 0x00000019,
+TCC_PERF_SEL_EA_WRREQ = 0x0000001a,
+TCC_PERF_SEL_EA_WRREQ_64B = 0x0000001b,
+TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 0x0000001c,
+TCC_PERF_SEL_EA_WR_UNCACHED_32B = 0x0000001d,
+TCC_PERF_SEL_EA_WRREQ_STALL = 0x0000001e,
+TCC_PERF_SEL_EA_WRREQ_CREDIT_STALL = 0x0000001f,
+TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 0x00000020,
+TCC_PERF_SEL_EA_WRREQ_LEVEL = 0x00000021,
+TCC_PERF_SEL_EA_ATOMIC = 0x00000022,
+TCC_PERF_SEL_EA_ATOMIC_LEVEL = 0x00000023,
+TCC_PERF_SEL_EA_RDREQ = 0x00000024,
+TCC_PERF_SEL_EA_RDREQ_32B = 0x00000025,
+TCC_PERF_SEL_EA_RD_UNCACHED_32B = 0x00000026,
+TCC_PERF_SEL_EA_RD_MDC_32B = 0x00000027,
+TCC_PERF_SEL_EA_RD_COMPRESSED_32B = 0x00000028,
+TCC_PERF_SEL_EA_RDREQ_CREDIT_STALL = 0x00000029,
+TCC_PERF_SEL_EA_RDREQ_LEVEL = 0x0000002a,
+TCC_PERF_SEL_TAG_STALL = 0x0000002b,
+TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x0000002c,
+TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x0000002d,
+TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 0x0000002e,
+TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 0x0000002f,
+TCC_PERF_SEL_TAG_PROBE_STALL = 0x00000030,
+TCC_PERF_SEL_TAG_PROBE_FILTER_STALL = 0x00000031,
+TCC_PERF_SEL_READ_RETURN_TIMEOUT = 0x00000032,
+TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x00000033,
+TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x00000034,
+TCC_PERF_SEL_BUBBLE = 0x00000035,
+TCC_PERF_SEL_RETURN_ACK = 0x00000036,
+TCC_PERF_SEL_RETURN_DATA = 0x00000037,
+TCC_PERF_SEL_RETURN_HOLE = 0x00000038,
+TCC_PERF_SEL_RETURN_ACK_HOLE = 0x00000039,
+TCC_PERF_SEL_IB_REQ = 0x0000003a,
+TCC_PERF_SEL_IB_STALL = 0x0000003b,
+TCC_PERF_SEL_IB_TAG_STALL = 0x0000003c,
+TCC_PERF_SEL_IB_MDC_STALL = 0x0000003d,
+TCC_PERF_SEL_TCA_LEVEL = 0x0000003e,
+TCC_PERF_SEL_HOLE_LEVEL = 0x0000003f,
+TCC_PERF_SEL_NORMAL_WRITEBACK = 0x00000040,
+TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK = 0x00000041,
+TCC_PERF_SEL_TC_OP_WBL2_WC_WRITEBACK = 0x00000042,
+TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK = 0x00000043,
+TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK = 0x00000044,
+TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK = 0x00000045,
+TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK = 0x00000046,
+TCC_PERF_SEL_NORMAL_EVICT = 0x00000047,
+TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT = 0x00000048,
+TCC_PERF_SEL_TC_OP_WBL2_WC_EVICT = 0x00000049,
+TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT = 0x0000004a,
+TCC_PERF_SEL_TC_OP_WBINVL2_EVICT = 0x0000004b,
+TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT = 0x0000004c,
+TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT = 0x0000004d,
+TCC_PERF_SEL_ALL_TC_OP_INV_EVICT = 0x0000004e,
+TCC_PERF_SEL_PROBE_EVICT = 0x0000004f,
+TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE = 0x00000050,
+TCC_PERF_SEL_TC_OP_WBL2_WC_CYCLE = 0x00000051,
+TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE = 0x00000052,
+TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE = 0x00000053,
+TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE = 0x00000054,
+TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE = 0x00000055,
+TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE = 0x00000056,
+TCC_PERF_SEL_TC_OP_WBL2_NC_START = 0x00000057,
+TCC_PERF_SEL_TC_OP_WBL2_WC_START = 0x00000058,
+TCC_PERF_SEL_TC_OP_INVL2_NC_START = 0x00000059,
+TCC_PERF_SEL_TC_OP_WBINVL2_START = 0x0000005a,
+TCC_PERF_SEL_TC_OP_WBINVL2_NC_START = 0x0000005b,
+TCC_PERF_SEL_TC_OP_WBINVL2_SD_START = 0x0000005c,
+TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x0000005d,
+TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH = 0x0000005e,
+TCC_PERF_SEL_TC_OP_WBL2_WC_FINISH = 0x0000005f,
+TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH = 0x00000060,
+TCC_PERF_SEL_TC_OP_WBINVL2_FINISH = 0x00000061,
+TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH = 0x00000062,
+TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH = 0x00000063,
+TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH = 0x00000064,
+TCC_PERF_SEL_MDC_REQ = 0x00000065,
+TCC_PERF_SEL_MDC_LEVEL = 0x00000066,
+TCC_PERF_SEL_MDC_TAG_HIT = 0x00000067,
+TCC_PERF_SEL_MDC_SECTOR_HIT = 0x00000068,
+TCC_PERF_SEL_MDC_SECTOR_MISS = 0x00000069,
+TCC_PERF_SEL_MDC_TAG_STALL = 0x0000006a,
+TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 0x0000006b,
+TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 0x0000006c,
+TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 0x0000006d,
+TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 0x0000006e,
+TCC_PERF_SEL_PROBE_FILTER_DISABLED = 0x0000006f,
+TCC_PERF_SEL_CLIENT0_REQ = 0x00000080,
+TCC_PERF_SEL_CLIENT1_REQ = 0x00000081,
+TCC_PERF_SEL_CLIENT2_REQ = 0x00000082,
+TCC_PERF_SEL_CLIENT3_REQ = 0x00000083,
+TCC_PERF_SEL_CLIENT4_REQ = 0x00000084,
+TCC_PERF_SEL_CLIENT5_REQ = 0x00000085,
+TCC_PERF_SEL_CLIENT6_REQ = 0x00000086,
+TCC_PERF_SEL_CLIENT7_REQ = 0x00000087,
+TCC_PERF_SEL_CLIENT8_REQ = 0x00000088,
+TCC_PERF_SEL_CLIENT9_REQ = 0x00000089,
+TCC_PERF_SEL_CLIENT10_REQ = 0x0000008a,
+TCC_PERF_SEL_CLIENT11_REQ = 0x0000008b,
+TCC_PERF_SEL_CLIENT12_REQ = 0x0000008c,
+TCC_PERF_SEL_CLIENT13_REQ = 0x0000008d,
+TCC_PERF_SEL_CLIENT14_REQ = 0x0000008e,
+TCC_PERF_SEL_CLIENT15_REQ = 0x0000008f,
+TCC_PERF_SEL_CLIENT16_REQ = 0x00000090,
+TCC_PERF_SEL_CLIENT17_REQ = 0x00000091,
+TCC_PERF_SEL_CLIENT18_REQ = 0x00000092,
+TCC_PERF_SEL_CLIENT19_REQ = 0x00000093,
+TCC_PERF_SEL_CLIENT20_REQ = 0x00000094,
+TCC_PERF_SEL_CLIENT21_REQ = 0x00000095,
+TCC_PERF_SEL_CLIENT22_REQ = 0x00000096,
+TCC_PERF_SEL_CLIENT23_REQ = 0x00000097,
+TCC_PERF_SEL_CLIENT24_REQ = 0x00000098,
+TCC_PERF_SEL_CLIENT25_REQ = 0x00000099,
+TCC_PERF_SEL_CLIENT26_REQ = 0x0000009a,
+TCC_PERF_SEL_CLIENT27_REQ = 0x0000009b,
+TCC_PERF_SEL_CLIENT28_REQ = 0x0000009c,
+TCC_PERF_SEL_CLIENT29_REQ = 0x0000009d,
+TCC_PERF_SEL_CLIENT30_REQ = 0x0000009e,
+TCC_PERF_SEL_CLIENT31_REQ = 0x0000009f,
+TCC_PERF_SEL_CLIENT32_REQ = 0x000000a0,
+TCC_PERF_SEL_CLIENT33_REQ = 0x000000a1,
+TCC_PERF_SEL_CLIENT34_REQ = 0x000000a2,
+TCC_PERF_SEL_CLIENT35_REQ = 0x000000a3,
+TCC_PERF_SEL_CLIENT36_REQ = 0x000000a4,
+TCC_PERF_SEL_CLIENT37_REQ = 0x000000a5,
+TCC_PERF_SEL_CLIENT38_REQ = 0x000000a6,
+TCC_PERF_SEL_CLIENT39_REQ = 0x000000a7,
+TCC_PERF_SEL_CLIENT40_REQ = 0x000000a8,
+TCC_PERF_SEL_CLIENT41_REQ = 0x000000a9,
+TCC_PERF_SEL_CLIENT42_REQ = 0x000000aa,
+TCC_PERF_SEL_CLIENT43_REQ = 0x000000ab,
+TCC_PERF_SEL_CLIENT44_REQ = 0x000000ac,
+TCC_PERF_SEL_CLIENT45_REQ = 0x000000ad,
+TCC_PERF_SEL_CLIENT46_REQ = 0x000000ae,
+TCC_PERF_SEL_CLIENT47_REQ = 0x000000af,
+TCC_PERF_SEL_CLIENT48_REQ = 0x000000b0,
+TCC_PERF_SEL_CLIENT49_REQ = 0x000000b1,
+TCC_PERF_SEL_CLIENT50_REQ = 0x000000b2,
+TCC_PERF_SEL_CLIENT51_REQ = 0x000000b3,
+TCC_PERF_SEL_CLIENT52_REQ = 0x000000b4,
+TCC_PERF_SEL_CLIENT53_REQ = 0x000000b5,
+TCC_PERF_SEL_CLIENT54_REQ = 0x000000b6,
+TCC_PERF_SEL_CLIENT55_REQ = 0x000000b7,
+TCC_PERF_SEL_CLIENT56_REQ = 0x000000b8,
+TCC_PERF_SEL_CLIENT57_REQ = 0x000000b9,
+TCC_PERF_SEL_CLIENT58_REQ = 0x000000ba,
+TCC_PERF_SEL_CLIENT59_REQ = 0x000000bb,
+TCC_PERF_SEL_CLIENT60_REQ = 0x000000bc,
+TCC_PERF_SEL_CLIENT61_REQ = 0x000000bd,
+TCC_PERF_SEL_CLIENT62_REQ = 0x000000be,
+TCC_PERF_SEL_CLIENT63_REQ = 0x000000bf,
+TCC_PERF_SEL_CLIENT64_REQ = 0x000000c0,
+TCC_PERF_SEL_CLIENT65_REQ = 0x000000c1,
+TCC_PERF_SEL_CLIENT66_REQ = 0x000000c2,
+TCC_PERF_SEL_CLIENT67_REQ = 0x000000c3,
+TCC_PERF_SEL_CLIENT68_REQ = 0x000000c4,
+TCC_PERF_SEL_CLIENT69_REQ = 0x000000c5,
+TCC_PERF_SEL_CLIENT70_REQ = 0x000000c6,
+TCC_PERF_SEL_CLIENT71_REQ = 0x000000c7,
+TCC_PERF_SEL_CLIENT72_REQ = 0x000000c8,
+TCC_PERF_SEL_CLIENT73_REQ = 0x000000c9,
+TCC_PERF_SEL_CLIENT74_REQ = 0x000000ca,
+TCC_PERF_SEL_CLIENT75_REQ = 0x000000cb,
+TCC_PERF_SEL_CLIENT76_REQ = 0x000000cc,
+TCC_PERF_SEL_CLIENT77_REQ = 0x000000cd,
+TCC_PERF_SEL_CLIENT78_REQ = 0x000000ce,
+TCC_PERF_SEL_CLIENT79_REQ = 0x000000cf,
+TCC_PERF_SEL_CLIENT80_REQ = 0x000000d0,
+TCC_PERF_SEL_CLIENT81_REQ = 0x000000d1,
+TCC_PERF_SEL_CLIENT82_REQ = 0x000000d2,
+TCC_PERF_SEL_CLIENT83_REQ = 0x000000d3,
+TCC_PERF_SEL_CLIENT84_REQ = 0x000000d4,
+TCC_PERF_SEL_CLIENT85_REQ = 0x000000d5,
+TCC_PERF_SEL_CLIENT86_REQ = 0x000000d6,
+TCC_PERF_SEL_CLIENT87_REQ = 0x000000d7,
+TCC_PERF_SEL_CLIENT88_REQ = 0x000000d8,
+TCC_PERF_SEL_CLIENT89_REQ = 0x000000d9,
+TCC_PERF_SEL_CLIENT90_REQ = 0x000000da,
+TCC_PERF_SEL_CLIENT91_REQ = 0x000000db,
+TCC_PERF_SEL_CLIENT92_REQ = 0x000000dc,
+TCC_PERF_SEL_CLIENT93_REQ = 0x000000dd,
+TCC_PERF_SEL_CLIENT94_REQ = 0x000000de,
+TCC_PERF_SEL_CLIENT95_REQ = 0x000000df,
+TCC_PERF_SEL_CLIENT96_REQ = 0x000000e0,
+TCC_PERF_SEL_CLIENT97_REQ = 0x000000e1,
+TCC_PERF_SEL_CLIENT98_REQ = 0x000000e2,
+TCC_PERF_SEL_CLIENT99_REQ = 0x000000e3,
+TCC_PERF_SEL_CLIENT100_REQ = 0x000000e4,
+TCC_PERF_SEL_CLIENT101_REQ = 0x000000e5,
+TCC_PERF_SEL_CLIENT102_REQ = 0x000000e6,
+TCC_PERF_SEL_CLIENT103_REQ = 0x000000e7,
+TCC_PERF_SEL_CLIENT104_REQ = 0x000000e8,
+TCC_PERF_SEL_CLIENT105_REQ = 0x000000e9,
+TCC_PERF_SEL_CLIENT106_REQ = 0x000000ea,
+TCC_PERF_SEL_CLIENT107_REQ = 0x000000eb,
+TCC_PERF_SEL_CLIENT108_REQ = 0x000000ec,
+TCC_PERF_SEL_CLIENT109_REQ = 0x000000ed,
+TCC_PERF_SEL_CLIENT110_REQ = 0x000000ee,
+TCC_PERF_SEL_CLIENT111_REQ = 0x000000ef,
+TCC_PERF_SEL_CLIENT112_REQ = 0x000000f0,
+TCC_PERF_SEL_CLIENT113_REQ = 0x000000f1,
+TCC_PERF_SEL_CLIENT114_REQ = 0x000000f2,
+TCC_PERF_SEL_CLIENT115_REQ = 0x000000f3,
+TCC_PERF_SEL_CLIENT116_REQ = 0x000000f4,
+TCC_PERF_SEL_CLIENT117_REQ = 0x000000f5,
+TCC_PERF_SEL_CLIENT118_REQ = 0x000000f6,
+TCC_PERF_SEL_CLIENT119_REQ = 0x000000f7,
+TCC_PERF_SEL_CLIENT120_REQ = 0x000000f8,
+TCC_PERF_SEL_CLIENT121_REQ = 0x000000f9,
+TCC_PERF_SEL_CLIENT122_REQ = 0x000000fa,
+TCC_PERF_SEL_CLIENT123_REQ = 0x000000fb,
+TCC_PERF_SEL_CLIENT124_REQ = 0x000000fc,
+TCC_PERF_SEL_CLIENT125_REQ = 0x000000fd,
+TCC_PERF_SEL_CLIENT126_REQ = 0x000000fe,
+TCC_PERF_SEL_CLIENT127_REQ = 0x000000ff,
+} TCC_PERF_SEL;
+
+/*
+ * TCA_PERF_SEL enum
+ */
+
+typedef enum TCA_PERF_SEL {
+TCA_PERF_SEL_NONE = 0x00000000,
+TCA_PERF_SEL_CYCLE = 0x00000001,
+TCA_PERF_SEL_BUSY = 0x00000002,
+TCA_PERF_SEL_FORCED_HOLE_TCC0 = 0x00000003,
+TCA_PERF_SEL_FORCED_HOLE_TCC1 = 0x00000004,
+TCA_PERF_SEL_FORCED_HOLE_TCC2 = 0x00000005,
+TCA_PERF_SEL_FORCED_HOLE_TCC3 = 0x00000006,
+TCA_PERF_SEL_FORCED_HOLE_TCC4 = 0x00000007,
+TCA_PERF_SEL_FORCED_HOLE_TCC5 = 0x00000008,
+TCA_PERF_SEL_FORCED_HOLE_TCC6 = 0x00000009,
+TCA_PERF_SEL_FORCED_HOLE_TCC7 = 0x0000000a,
+TCA_PERF_SEL_REQ_TCC0 = 0x0000000b,
+TCA_PERF_SEL_REQ_TCC1 = 0x0000000c,
+TCA_PERF_SEL_REQ_TCC2 = 0x0000000d,
+TCA_PERF_SEL_REQ_TCC3 = 0x0000000e,
+TCA_PERF_SEL_REQ_TCC4 = 0x0000000f,
+TCA_PERF_SEL_REQ_TCC5 = 0x00000010,
+TCA_PERF_SEL_REQ_TCC6 = 0x00000011,
+TCA_PERF_SEL_REQ_TCC7 = 0x00000012,
+TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 0x00000013,
+TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 0x00000014,
+TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 0x00000015,
+TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 0x00000016,
+TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 0x00000017,
+TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 0x00000018,
+TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 0x00000019,
+TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 0x0000001a,
+TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 0x0000001b,
+TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 0x0000001c,
+TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 0x0000001d,
+TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 0x0000001e,
+TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 0x0000001f,
+TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 0x00000020,
+TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 0x00000021,
+TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 0x00000022,
+} TCA_PERF_SEL;
+
+/*******************************************************
+ * GRBM Enums
+ *******************************************************/
+
+/*
+ * GRBM_PERF_SEL enum
+ */
+
+typedef enum GRBM_PERF_SEL {
+GRBM_PERF_SEL_COUNT = 0x00000000,
+GRBM_PERF_SEL_USER_DEFINED = 0x00000001,
+GRBM_PERF_SEL_GUI_ACTIVE = 0x00000002,
+GRBM_PERF_SEL_CP_BUSY = 0x00000003,
+GRBM_PERF_SEL_CP_COHER_BUSY = 0x00000004,
+GRBM_PERF_SEL_CP_DMA_BUSY = 0x00000005,
+GRBM_PERF_SEL_CB_BUSY = 0x00000006,
+GRBM_PERF_SEL_DB_BUSY = 0x00000007,
+GRBM_PERF_SEL_PA_BUSY = 0x00000008,
+GRBM_PERF_SEL_SC_BUSY = 0x00000009,
+GRBM_PERF_SEL_RESERVED_6 = 0x0000000a,
+GRBM_PERF_SEL_SPI_BUSY = 0x0000000b,
+GRBM_PERF_SEL_SX_BUSY = 0x0000000c,
+GRBM_PERF_SEL_TA_BUSY = 0x0000000d,
+GRBM_PERF_SEL_CB_CLEAN = 0x0000000e,
+GRBM_PERF_SEL_DB_CLEAN = 0x0000000f,
+GRBM_PERF_SEL_RESERVED_5 = 0x00000010,
+GRBM_PERF_SEL_VGT_BUSY = 0x00000011,
+GRBM_PERF_SEL_RESERVED_4 = 0x00000012,
+GRBM_PERF_SEL_RESERVED_3 = 0x00000013,
+GRBM_PERF_SEL_RESERVED_2 = 0x00000014,
+GRBM_PERF_SEL_RESERVED_1 = 0x00000015,
+GRBM_PERF_SEL_RESERVED_0 = 0x00000016,
+GRBM_PERF_SEL_IA_BUSY = 0x00000017,
+GRBM_PERF_SEL_IA_NO_DMA_BUSY = 0x00000018,
+GRBM_PERF_SEL_GDS_BUSY = 0x00000019,
+GRBM_PERF_SEL_BCI_BUSY = 0x0000001a,
+GRBM_PERF_SEL_RLC_BUSY = 0x0000001b,
+GRBM_PERF_SEL_TC_BUSY = 0x0000001c,
+GRBM_PERF_SEL_CPG_BUSY = 0x0000001d,
+GRBM_PERF_SEL_CPC_BUSY = 0x0000001e,
+GRBM_PERF_SEL_CPF_BUSY = 0x0000001f,
+GRBM_PERF_SEL_WD_BUSY = 0x00000020,
+GRBM_PERF_SEL_WD_NO_DMA_BUSY = 0x00000021,
+GRBM_PERF_SEL_UTCL2_BUSY = 0x00000022,
+GRBM_PERF_SEL_EA_BUSY = 0x00000023,
+GRBM_PERF_SEL_RMI_BUSY = 0x00000024,
+GRBM_PERF_SEL_CPAXI_BUSY = 0x00000025,
+} GRBM_PERF_SEL;
+
+/*
+ * GRBM_SE0_PERF_SEL enum
+ */
+
+typedef enum GRBM_SE0_PERF_SEL {
+GRBM_SE0_PERF_SEL_COUNT = 0x00000000,
+GRBM_SE0_PERF_SEL_USER_DEFINED = 0x00000001,
+GRBM_SE0_PERF_SEL_CB_BUSY = 0x00000002,
+GRBM_SE0_PERF_SEL_DB_BUSY = 0x00000003,
+GRBM_SE0_PERF_SEL_SC_BUSY = 0x00000004,
+GRBM_SE0_PERF_SEL_RESERVED_1 = 0x00000005,
+GRBM_SE0_PERF_SEL_SPI_BUSY = 0x00000006,
+GRBM_SE0_PERF_SEL_SX_BUSY = 0x00000007,
+GRBM_SE0_PERF_SEL_TA_BUSY = 0x00000008,
+GRBM_SE0_PERF_SEL_CB_CLEAN = 0x00000009,
+GRBM_SE0_PERF_SEL_DB_CLEAN = 0x0000000a,
+GRBM_SE0_PERF_SEL_RESERVED_0 = 0x0000000b,
+GRBM_SE0_PERF_SEL_PA_BUSY = 0x0000000c,
+GRBM_SE0_PERF_SEL_VGT_BUSY = 0x0000000d,
+GRBM_SE0_PERF_SEL_BCI_BUSY = 0x0000000e,
+GRBM_SE0_PERF_SEL_RMI_BUSY = 0x0000000f,
+} GRBM_SE0_PERF_SEL;
+
+/*
+ * GRBM_SE1_PERF_SEL enum
+ */
+
+typedef enum GRBM_SE1_PERF_SEL {
+GRBM_SE1_PERF_SEL_COUNT = 0x00000000,
+GRBM_SE1_PERF_SEL_USER_DEFINED = 0x00000001,
+GRBM_SE1_PERF_SEL_CB_BUSY = 0x00000002,
+GRBM_SE1_PERF_SEL_DB_BUSY = 0x00000003,
+GRBM_SE1_PERF_SEL_SC_BUSY = 0x00000004,
+GRBM_SE1_PERF_SEL_RESERVED_1 = 0x00000005,
+GRBM_SE1_PERF_SEL_SPI_BUSY = 0x00000006,
+GRBM_SE1_PERF_SEL_SX_BUSY = 0x00000007,
+GRBM_SE1_PERF_SEL_TA_BUSY = 0x00000008,
+GRBM_SE1_PERF_SEL_CB_CLEAN = 0x00000009,
+GRBM_SE1_PERF_SEL_DB_CLEAN = 0x0000000a,
+GRBM_SE1_PERF_SEL_RESERVED_0 = 0x0000000b,
+GRBM_SE1_PERF_SEL_PA_BUSY = 0x0000000c,
+GRBM_SE1_PERF_SEL_VGT_BUSY = 0x0000000d,
+GRBM_SE1_PERF_SEL_BCI_BUSY = 0x0000000e,
+GRBM_SE1_PERF_SEL_RMI_BUSY = 0x0000000f,
+} GRBM_SE1_PERF_SEL;
+
+/*
+ * GRBM_SE2_PERF_SEL enum
+ */
+
+typedef enum GRBM_SE2_PERF_SEL {
+GRBM_SE2_PERF_SEL_COUNT = 0x00000000,
+GRBM_SE2_PERF_SEL_USER_DEFINED = 0x00000001,
+GRBM_SE2_PERF_SEL_CB_BUSY = 0x00000002,
+GRBM_SE2_PERF_SEL_DB_BUSY = 0x00000003,
+GRBM_SE2_PERF_SEL_SC_BUSY = 0x00000004,
+GRBM_SE2_PERF_SEL_RESERVED_1 = 0x00000005,
+GRBM_SE2_PERF_SEL_SPI_BUSY = 0x00000006,
+GRBM_SE2_PERF_SEL_SX_BUSY = 0x00000007,
+GRBM_SE2_PERF_SEL_TA_BUSY = 0x00000008,
+GRBM_SE2_PERF_SEL_CB_CLEAN = 0x00000009,
+GRBM_SE2_PERF_SEL_DB_CLEAN = 0x0000000a,
+GRBM_SE2_PERF_SEL_RESERVED_0 = 0x0000000b,
+GRBM_SE2_PERF_SEL_PA_BUSY = 0x0000000c,
+GRBM_SE2_PERF_SEL_VGT_BUSY = 0x0000000d,
+GRBM_SE2_PERF_SEL_BCI_BUSY = 0x0000000e,
+GRBM_SE2_PERF_SEL_RMI_BUSY = 0x0000000f,
+} GRBM_SE2_PERF_SEL;
+
+/*
+ * GRBM_SE3_PERF_SEL enum
+ */
+
+typedef enum GRBM_SE3_PERF_SEL {
+GRBM_SE3_PERF_SEL_COUNT = 0x00000000,
+GRBM_SE3_PERF_SEL_USER_DEFINED = 0x00000001,
+GRBM_SE3_PERF_SEL_CB_BUSY = 0x00000002,
+GRBM_SE3_PERF_SEL_DB_BUSY = 0x00000003,
+GRBM_SE3_PERF_SEL_SC_BUSY = 0x00000004,
+GRBM_SE3_PERF_SEL_RESERVED_1 = 0x00000005,
+GRBM_SE3_PERF_SEL_SPI_BUSY = 0x00000006,
+GRBM_SE3_PERF_SEL_SX_BUSY = 0x00000007,
+GRBM_SE3_PERF_SEL_TA_BUSY = 0x00000008,
+GRBM_SE3_PERF_SEL_CB_CLEAN = 0x00000009,
+GRBM_SE3_PERF_SEL_DB_CLEAN = 0x0000000a,
+GRBM_SE3_PERF_SEL_RESERVED_0 = 0x0000000b,
+GRBM_SE3_PERF_SEL_PA_BUSY = 0x0000000c,
+GRBM_SE3_PERF_SEL_VGT_BUSY = 0x0000000d,
+GRBM_SE3_PERF_SEL_BCI_BUSY = 0x0000000e,
+GRBM_SE3_PERF_SEL_RMI_BUSY = 0x0000000f,
+} GRBM_SE3_PERF_SEL;
+
+/*******************************************************
+ * CP Enums
+ *******************************************************/
+
+/*
+ * CP_RING_ID enum
+ */
+
+typedef enum CP_RING_ID {
+RINGID0 = 0x00000000,
+RINGID1 = 0x00000001,
+RINGID2 = 0x00000002,
+RINGID3 = 0x00000003,
+} CP_RING_ID;
+
+/*
+ * CP_PIPE_ID enum
+ */
+
+typedef enum CP_PIPE_ID {
+PIPE_ID0 = 0x00000000,
+PIPE_ID1 = 0x00000001,
+PIPE_ID2 = 0x00000002,
+PIPE_ID3 = 0x00000003,
+} CP_PIPE_ID;
+
+/*
+ * CP_ME_ID enum
+ */
+
+typedef enum CP_ME_ID {
+ME_ID0 = 0x00000000,
+ME_ID1 = 0x00000001,
+ME_ID2 = 0x00000002,
+ME_ID3 = 0x00000003,
+} CP_ME_ID;
+
+/*
+ * SPM_PERFMON_STATE enum
+ */
+
+typedef enum SPM_PERFMON_STATE {
+STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000,
+STRM_PERFMON_STATE_START_COUNTING = 0x00000001,
+STRM_PERFMON_STATE_STOP_COUNTING = 0x00000002,
+STRM_PERFMON_STATE_RESERVED_3 = 0x00000003,
+STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
+STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005,
+} SPM_PERFMON_STATE;
+
+/*
+ * CP_PERFMON_STATE enum
+ */
+
+typedef enum CP_PERFMON_STATE {
+CP_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000,
+CP_PERFMON_STATE_START_COUNTING = 0x00000001,
+CP_PERFMON_STATE_STOP_COUNTING = 0x00000002,
+CP_PERFMON_STATE_RESERVED_3 = 0x00000003,
+CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
+CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005,
+} CP_PERFMON_STATE;
+
+/*
+ * CP_PERFMON_ENABLE_MODE enum
+ */
+
+typedef enum CP_PERFMON_ENABLE_MODE {
+CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x00000000,
+CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x00000001,
+CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002,
+CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003,
+} CP_PERFMON_ENABLE_MODE;
+
+/*
+ * CPG_PERFCOUNT_SEL enum
+ */
+
+typedef enum CPG_PERFCOUNT_SEL {
+CPG_PERF_SEL_ALWAYS_COUNT = 0x00000000,
+CPG_PERF_SEL_RBIU_FIFO_FULL = 0x00000001,
+CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x00000002,
+CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 0x00000003,
+CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x00000004,
+CPG_PERF_SEL_ME_PARSER_BUSY = 0x00000005,
+CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x00000006,
+CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x00000007,
+CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x00000008,
+CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x00000009,
+CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0x0000000a,
+CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0x0000000b,
+CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0x0000000c,
+CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0x0000000d,
+CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0x0000000e,
+CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0x0000000f,
+CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x00000010,
+CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x00000011,
+CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x00000012,
+CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x00000013,
+CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x00000014,
+CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x00000015,
+CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x00000016,
+CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x00000017,
+CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x00000018,
+CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x00000019,
+CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x0000001a,
+CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x0000001b,
+CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x0000001c,
+CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x0000001d,
+CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x0000001e,
+CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x0000001f,
+CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x00000020,
+CPG_PERF_SEL_REGISTER_CLK_VALID = 0x00000021,
+CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 0x00000022,
+CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 0x00000023,
+CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x00000024,
+CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x00000025,
+CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x00000026,
+CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x00000027,
+CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 0x00000028,
+CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x00000029,
+CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x0000002a,
+CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x0000002b,
+CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x0000002c,
+CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x0000002d,
+CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x0000002e,
+CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x0000002f,
+CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000030,
+} CPG_PERFCOUNT_SEL;
+
+/*
+ * CPF_PERFCOUNT_SEL enum
+ */
+
+typedef enum CPF_PERFCOUNT_SEL {
+CPF_PERF_SEL_ALWAYS_COUNT = 0x00000000,
+CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x00000001,
+CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x00000002,
+CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x00000003,
+CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x00000004,
+CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x00000005,
+CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x00000006,
+CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x00000007,
+CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x00000008,
+CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 0x00000009,
+CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0x0000000a,
+CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x0000000b,
+CPF_PERF_SEL_GRBM_DWORDS_SENT = 0x0000000c,
+CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0x0000000d,
+CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0x0000000e,
+CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 0x0000000f,
+CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 0x00000010,
+CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000011,
+CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000012,
+CPF_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000013,
+CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000014,
+} CPF_PERFCOUNT_SEL;
+
+/*
+ * CPC_PERFCOUNT_SEL enum
+ */
+
+typedef enum CPC_PERFCOUNT_SEL {
+CPC_PERF_SEL_ALWAYS_COUNT = 0x00000000,
+CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000001,
+CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x00000002,
+CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 0x00000003,
+CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 0x00000004,
+CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x00000005,
+CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x00000006,
+CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x00000007,
+CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x00000008,
+CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 0x00000009,
+CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0x0000000a,
+CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0x0000000b,
+CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0x0000000c,
+CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0x0000000d,
+CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0x0000000e,
+CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0x0000000f,
+CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x00000010,
+CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 0x00000011,
+CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 0x00000012,
+CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x00000013,
+CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x00000014,
+CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x00000015,
+CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000016,
+CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000017,
+CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000018,
+} CPC_PERFCOUNT_SEL;
+
+/*
+ * CP_ALPHA_TAG_RAM_SEL enum
+ */
+
+typedef enum CP_ALPHA_TAG_RAM_SEL {
+CPG_TAG_RAM = 0x00000000,
+CPC_TAG_RAM = 0x00000001,
+CPF_TAG_RAM = 0x00000002,
+RSV_TAG_RAM = 0x00000003,
+} CP_ALPHA_TAG_RAM_SEL;
+
+/*
+ * SEM_RESPONSE value
+ */
+
+#define SEM_ECC_ERROR 0x00000000
+#define SEM_TRANS_ERROR 0x00000001
+#define SEM_FAILED 0x00000002
+#define SEM_PASSED 0x00000003
+
+/*
+ * IQ_RETRY_TYPE value
+ */
+
+#define IQ_QUEUE_SLEEP 0x00000000
+#define IQ_OFFLOAD_RETRY 0x00000001
+#define IQ_SCH_WAVE_MSG 0x00000002
+#define IQ_SEM_REARM 0x00000003
+#define IQ_DEQUEUE_RETRY 0x00000004
+
+/*
+ * IQ_INTR_TYPE value
+ */
+
+#define IQ_INTR_TYPE_PQ 0x00000000
+#define IQ_INTR_TYPE_IB 0x00000001
+#define IQ_INTR_TYPE_MQD 0x00000002
+
+/*
+ * VMID_SIZE value
+ */
+
+#define VMID_SZ 0x00000004
+
+/*
+ * CONFIG_SPACE value
+ */
+
+#define CONFIG_SPACE_START 0x00002000
+#define CONFIG_SPACE_END 0x00009fff
+
+/*
+ * CONFIG_SPACE1 value
+ */
+
+#define CONFIG_SPACE1_START 0x00002000
+#define CONFIG_SPACE1_END 0x00002bff
+
+/*
+ * CONFIG_SPACE2 value
+ */
+
+#define CONFIG_SPACE2_START 0x00003000
+#define CONFIG_SPACE2_END 0x00009fff
+
+/*
+ * UCONFIG_SPACE value
+ */
+
+#define UCONFIG_SPACE_START 0x0000c000
+#define UCONFIG_SPACE_END 0x0000ffff
+
+/*
+ * PERSISTENT_SPACE value
+ */
+
+#define PERSISTENT_SPACE_START 0x00002c00
+#define PERSISTENT_SPACE_END 0x00002fff
+
+/*
+ * CONTEXT_SPACE value
+ */
+
+#define CONTEXT_SPACE_START 0x0000a000
+#define CONTEXT_SPACE_END 0x0000bfff
+
+/*******************************************************
+ * SQ_UC Enums
+ *******************************************************/
+
+/*
+ * VALUE_SQ_ENC_SOP1 value
+ */
+
+#define SQ_ENC_SOP1_BITS 0xbe800000
+#define SQ_ENC_SOP1_MASK 0xff800000
+#define SQ_ENC_SOP1_FIELD 0x0000017d
+
+/*
+ * VALUE_SQ_ENC_SOPC value
+ */
+
+#define SQ_ENC_SOPC_BITS 0xbf000000
+#define SQ_ENC_SOPC_MASK 0xff800000
+#define SQ_ENC_SOPC_FIELD 0x0000017e
+
+/*
+ * VALUE_SQ_ENC_SOPP value
+ */
+
+#define SQ_ENC_SOPP_BITS 0xbf800000
+#define SQ_ENC_SOPP_MASK 0xff800000
+#define SQ_ENC_SOPP_FIELD 0x0000017f
+
+/*
+ * VALUE_SQ_ENC_SOPK value
+ */
+
+#define SQ_ENC_SOPK_BITS 0xb0000000
+#define SQ_ENC_SOPK_MASK 0xf0000000
+#define SQ_ENC_SOPK_FIELD 0x0000000b
+
+/*
+ * VALUE_SQ_ENC_SOP2 value
+ */
+
+#define SQ_ENC_SOP2_BITS 0x80000000
+#define SQ_ENC_SOP2_MASK 0xc0000000
+#define SQ_ENC_SOP2_FIELD 0x00000002
+
+/*
+ * VALUE_SQ_ENC_SMEM value
+ */
+
+#define SQ_ENC_SMEM_BITS 0xc0000000
+#define SQ_ENC_SMEM_MASK 0xfc000000
+#define SQ_ENC_SMEM_FIELD 0x00000030
+
+/*
+ * VALUE_SQ_ENC_VOP1 value
+ */
+
+#define SQ_ENC_VOP1_BITS 0x7e000000
+#define SQ_ENC_VOP1_MASK 0xfe000000
+#define SQ_ENC_VOP1_FIELD 0x0000003f
+
+/*
+ * VALUE_SQ_ENC_VOPC value
+ */
+
+#define SQ_ENC_VOPC_BITS 0x7c000000
+#define SQ_ENC_VOPC_MASK 0xfe000000
+#define SQ_ENC_VOPC_FIELD 0x0000003e
+
+/*
+ * VALUE_SQ_ENC_VOP2 value
+ */
+
+#define SQ_ENC_VOP2_BITS 0x00000000
+#define SQ_ENC_VOP2_MASK 0x80000000
+#define SQ_ENC_VOP2_FIELD 0x00000000
+
+/*
+ * VALUE_SQ_ENC_VINTRP value
+ */
+
+#define SQ_ENC_VINTRP_BITS 0xd4000000
+#define SQ_ENC_VINTRP_MASK 0xfc000000
+#define SQ_ENC_VINTRP_FIELD 0x00000035
+
+/*
+ * VALUE_SQ_ENC_VOP3P value
+ */
+
+#define SQ_ENC_VOP3P_BITS 0xd3800000
+#define SQ_ENC_VOP3P_MASK 0xff800000
+#define SQ_ENC_VOP3P_FIELD 0x000001a7
+
+/*
+ * VALUE_SQ_ENC_VOP3 value
+ */
+
+#define SQ_ENC_VOP3_BITS 0xd0000000
+#define SQ_ENC_VOP3_MASK 0xfc000000
+#define SQ_ENC_VOP3_FIELD 0x00000034
+
+/*
+ * VALUE_SQ_ENC_DS value
+ */
+
+#define SQ_ENC_DS_BITS 0xd8000000
+#define SQ_ENC_DS_MASK 0xfc000000
+#define SQ_ENC_DS_FIELD 0x00000036
+
+/*
+ * VALUE_SQ_ENC_MUBUF value
+ */
+
+#define SQ_ENC_MUBUF_BITS 0xe0000000
+#define SQ_ENC_MUBUF_MASK 0xfc000000
+#define SQ_ENC_MUBUF_FIELD 0x00000038
+
+/*
+ * VALUE_SQ_ENC_MTBUF value
+ */
+
+#define SQ_ENC_MTBUF_BITS 0xe8000000
+#define SQ_ENC_MTBUF_MASK 0xfc000000
+#define SQ_ENC_MTBUF_FIELD 0x0000003a
+
+/*
+ * VALUE_SQ_ENC_MIMG value
+ */
+
+#define SQ_ENC_MIMG_BITS 0xf0000000
+#define SQ_ENC_MIMG_MASK 0xfc000000
+#define SQ_ENC_MIMG_FIELD 0x0000003c
+
+/*
+ * VALUE_SQ_ENC_EXP value
+ */
+
+#define SQ_ENC_EXP_BITS 0xc4000000
+#define SQ_ENC_EXP_MASK 0xfc000000
+#define SQ_ENC_EXP_FIELD 0x00000031
+
+/*
+ * VALUE_SQ_ENC_FLAT value
+ */
+
+#define SQ_ENC_FLAT_BITS 0xdc000000
+#define SQ_ENC_FLAT_MASK 0xfc000000
+#define SQ_ENC_FLAT_FIELD 0x00000037
+
+/*
+ * VALUE_SQ_V_OP3_INTRP_COUNT value
+ */
+
+#define SQ_V_OP3_INTRP_COUNT 0x0000000c
+
+/*
+ * VALUE_SQ_SENDMSG_SYSTEM_SIZE value
+ */
+
+#define SQ_SENDMSG_SYSTEM_SIZE 0x00000003
+
+/*
+ * VALUE_SQ_HWREG_ID_SIZE value
+ */
+
+#define SQ_HWREG_ID_SIZE 0x00000006
+
+/*
+ * VALUE_SQ_V_OPC_COUNT value
+ */
+
+#define SQ_V_OPC_COUNT 0x00000100
+
+/*
+ * VALUE_SQ_NUM_VGPR value
+ */
+
+#define SQ_NUM_VGPR 0x00000100
+
+/*
+ * VALUE_SQ_WAITCNT_LGKM_SHIFT value
+ */
+
+#define SQ_WAITCNT_LGKM_SHIFT 0x00000008
+
+/*
+ * VALUE_SQ_HWREG_ID_SHIFT value
+ */
+
+#define SQ_HWREG_ID_SHIFT 0x00000000
+
+/*
+ * VALUE_SQ_EXP_NUM_POS value
+ */
+
+#define SQ_EXP_NUM_POS 0x00000004
+
+/*
+ * VALUE_SQ_XLATE_VOP3_TO_VOPC_OFFSET value
+ */
+
+#define SQ_XLATE_VOP3_TO_VOPC_OFFSET 0x00000000
+
+/*
+ * VALUE_SQ_V_OP3_2IN_OFFSET value
+ */
+
+#define SQ_V_OP3_2IN_OFFSET 0x00000280
+
+/*
+ * VALUE_SQ_XLATE_VOP3_TO_VOP2_OFFSET value
+ */
+
+#define SQ_XLATE_VOP3_TO_VOP2_OFFSET 0x00000100
+
+/*
+ * VALUE_SQ_EXP_NUM_MRT value
+ */
+
+#define SQ_EXP_NUM_MRT 0x00000008
+
+/*
+ * VALUE_SQ_NUM_TTMP value
+ */
+
+#define SQ_NUM_TTMP 0x00000010
+
+/*
+ * VALUE_SQ_SENDMSG_STREAMID_SHIFT value
+ */
+
+#define SQ_SENDMSG_STREAMID_SHIFT 0x00000008
+
+/*
+ * VALUE_SQ_V_OP1_COUNT value
+ */
+
+#define SQ_V_OP1_COUNT 0x00000080
+
+/*
+ * VALUE_SQ_WAITCNT_LGKM_SIZE value
+ */
+
+#define SQ_WAITCNT_LGKM_SIZE 0x00000004
+
+/*
+ * VALUE_SQ_XLATE_VOP3_TO_VOPC_COUNT value
+ */
+
+#define SQ_XLATE_VOP3_TO_VOPC_COUNT 0x00000100
+
+/*
+ * VALUE_SQ_SENDMSG_MSG_SHIFT value
+ */
+
+#define SQ_SENDMSG_MSG_SHIFT 0x00000000
+
+/*
+ * VALUE_SQ_V_OP3_3IN_OFFSET value
+ */
+
+#define SQ_V_OP3_3IN_OFFSET 0x000001c0
+
+/*
+ * VALUE_SQ_HWREG_OFFSET_SHIFT value
+ */
+
+#define SQ_HWREG_OFFSET_SHIFT 0x00000006
+
+/*
+ * VALUE_SQ_HWREG_SIZE_SHIFT value
+ */
+
+#define SQ_HWREG_SIZE_SHIFT 0x0000000b
+
+/*
+ * VALUE_SQ_HWREG_OFFSET_SIZE value
+ */
+
+#define SQ_HWREG_OFFSET_SIZE 0x00000005
+
+/*
+ * VALUE_SQ_V_OP3_3IN_COUNT value
+ */
+
+#define SQ_V_OP3_3IN_COUNT 0x000000b0
+
+/*
+ * VALUE_SQ_SENDMSG_MSG_SIZE value
+ */
+
+#define SQ_SENDMSG_MSG_SIZE 0x00000004
+
+/*
+ * VALUE_SQ_XLATE_VOP3_TO_VOP1_COUNT value
+ */
+
+#define SQ_XLATE_VOP3_TO_VOP1_COUNT 0x00000080
+
+/*
+ * VALUE_SQ_EXP_NUM_GDS value
+ */
+
+#define SQ_EXP_NUM_GDS 0x00000005
+
+/*
+ * VALUE_SQ_V_OP2_COUNT value
+ */
+
+#define SQ_V_OP2_COUNT 0x00000040
+
+/*
+ * VALUE_SQ_SENDMSG_GSOP_SIZE value
+ */
+
+#define SQ_SENDMSG_GSOP_SIZE 0x00000002
+
+/*
+ * VALUE_SQ_WAITCNT_VM_SHIFT value
+ */
+
+#define SQ_WAITCNT_VM_SHIFT 0x00000000
+
+/*
+ * VALUE_SQ_XLATE_VOP3_TO_VOP3P_COUNT value
+ */
+
+#define SQ_XLATE_VOP3_TO_VOP3P_COUNT 0x00000080
+
+/*
+ * VALUE_SQ_V_OP3_2IN_COUNT value
+ */
+
+#define SQ_V_OP3_2IN_COUNT 0x00000080
+
+/*
+ * VALUE_SQ_SENDMSG_SYSTEM_SHIFT value
+ */
+
+#define SQ_SENDMSG_SYSTEM_SHIFT 0x00000004
+
+/*
+ * VALUE_SQ_WAITCNT_VM_SIZE value
+ */
+
+#define SQ_WAITCNT_VM_SIZE 0x00000004
+
+/*
+ * VALUE_SQ_XLATE_VOP3_TO_VOP3P_OFFSET value
+ */
+
+#define SQ_XLATE_VOP3_TO_VOP3P_OFFSET 0x00000380
+
+/*
+ * VALUE_SQ_WAITCNT_EXP_SHIFT value
+ */
+
+#define SQ_WAITCNT_EXP_SHIFT 0x00000004
+
+/*
+ * VALUE_SQ_XLATE_VOP3_TO_VOP2_COUNT value
+ */
+
+#define SQ_XLATE_VOP3_TO_VOP2_COUNT 0x00000040
+
+/*
+ * VALUE_SQ_EXP_NUM_PARAM value
+ */
+
+#define SQ_EXP_NUM_PARAM 0x00000020
+
+/*
+ * VALUE_SQ_HWREG_SIZE_SIZE value
+ */
+
+#define SQ_HWREG_SIZE_SIZE 0x00000005
+
+/*
+ * VALUE_SQ_WAITCNT_EXP_SIZE value
+ */
+
+#define SQ_WAITCNT_EXP_SIZE 0x00000003
+
+/*
+ * VALUE_SQ_V_OP3_INTRP_OFFSET value
+ */
+
+#define SQ_V_OP3_INTRP_OFFSET 0x00000274
+
+/*
+ * VALUE_SQ_SENDMSG_GSOP_SHIFT value
+ */
+
+#define SQ_SENDMSG_GSOP_SHIFT 0x00000004
+
+/*
+ * VALUE_SQ_XLATE_VOP3_TO_VINTRP_OFFSET value
+ */
+
+#define SQ_XLATE_VOP3_TO_VINTRP_OFFSET 0x00000270
+
+/*
+ * VALUE_SQ_NUM_ATTR value
+ */
+
+#define SQ_NUM_ATTR 0x00000021
+
+/*
+ * VALUE_SQ_NUM_SGPR value
+ */
+
+#define SQ_NUM_SGPR 0x00000066
+
+/*
+ * VALUE_SQ_SRC_VGPR_BIT value
+ */
+
+#define SQ_SRC_VGPR_BIT 0x00000100
+
+/*
+ * VALUE_SQ_V_INTRP_COUNT value
+ */
+
+#define SQ_V_INTRP_COUNT 0x00000004
+
+/*
+ * VALUE_SQ_SENDMSG_STREAMID_SIZE value
+ */
+
+#define SQ_SENDMSG_STREAMID_SIZE 0x00000002
+
+/*
+ * VALUE_SQ_V_OP3P_COUNT value
+ */
+
+#define SQ_V_OP3P_COUNT 0x00000080
+
+/*
+ * VALUE_SQ_XLATE_VOP3_TO_VOP1_OFFSET value
+ */
+
+#define SQ_XLATE_VOP3_TO_VOP1_OFFSET 0x00000140
+
+/*
+ * VALUE_SQ_XLATE_VOP3_TO_VINTRP_COUNT value
+ */
+
+#define SQ_XLATE_VOP3_TO_VINTRP_COUNT 0x00000004
+
+/*
+ * VALUE_SQ_SSRC_SPECIAL_DPP value
+ */
+
+#define SQ_SRC_DPP 0x000000fa
+
+/*
+ * VALUE_SQ_OP_MTBUF value
+ */
+
+#define SQ_TBUFFER_LOAD_FORMAT_X 0x00000000
+#define SQ_TBUFFER_LOAD_FORMAT_XY 0x00000001
+#define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x00000002
+#define SQ_TBUFFER_LOAD_FORMAT_XYZW 0x00000003
+#define SQ_TBUFFER_STORE_FORMAT_X 0x00000004
+#define SQ_TBUFFER_STORE_FORMAT_XY 0x00000005
+#define SQ_TBUFFER_STORE_FORMAT_XYZ 0x00000006
+#define SQ_TBUFFER_STORE_FORMAT_XYZW 0x00000007
+#define SQ_TBUFFER_LOAD_FORMAT_D16_X 0x00000008
+#define SQ_TBUFFER_LOAD_FORMAT_D16_XY 0x00000009
+#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ 0x0000000a
+#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW 0x0000000b
+#define SQ_TBUFFER_STORE_FORMAT_D16_X 0x0000000c
+#define SQ_TBUFFER_STORE_FORMAT_D16_XY 0x0000000d
+#define SQ_TBUFFER_STORE_FORMAT_D16_XYZ 0x0000000e
+#define SQ_TBUFFER_STORE_FORMAT_D16_XYZW 0x0000000f
+
+/*
+ * VALUE_SQ_OP_FLAT_GLBL value
+ */
+
+#define SQ_GLOBAL_LOAD_UBYTE 0x00000010
+#define SQ_GLOBAL_LOAD_SBYTE 0x00000011
+#define SQ_GLOBAL_LOAD_USHORT 0x00000012
+#define SQ_GLOBAL_LOAD_SSHORT 0x00000013
+#define SQ_GLOBAL_LOAD_DWORD 0x00000014
+#define SQ_GLOBAL_LOAD_DWORDX2 0x00000015
+#define SQ_GLOBAL_LOAD_DWORDX3 0x00000016
+#define SQ_GLOBAL_LOAD_DWORDX4 0x00000017
+#define SQ_GLOBAL_STORE_BYTE 0x00000018
+#define SQ_GLOBAL_STORE_SHORT 0x0000001a
+#define SQ_GLOBAL_STORE_DWORD 0x0000001c
+#define SQ_GLOBAL_STORE_DWORDX2 0x0000001d
+#define SQ_GLOBAL_STORE_DWORDX3 0x0000001e
+#define SQ_GLOBAL_STORE_DWORDX4 0x0000001f
+#define SQ_GLOBAL_ATOMIC_SWAP 0x00000040
+#define SQ_GLOBAL_ATOMIC_CMPSWAP 0x00000041
+#define SQ_GLOBAL_ATOMIC_ADD 0x00000042
+#define SQ_GLOBAL_ATOMIC_SUB 0x00000043
+#define SQ_GLOBAL_ATOMIC_SMIN 0x00000044
+#define SQ_GLOBAL_ATOMIC_UMIN 0x00000045
+#define SQ_GLOBAL_ATOMIC_SMAX 0x00000046
+#define SQ_GLOBAL_ATOMIC_UMAX 0x00000047
+#define SQ_GLOBAL_ATOMIC_AND 0x00000048
+#define SQ_GLOBAL_ATOMIC_OR 0x00000049
+#define SQ_GLOBAL_ATOMIC_XOR 0x0000004a
+#define SQ_GLOBAL_ATOMIC_INC 0x0000004b
+#define SQ_GLOBAL_ATOMIC_DEC 0x0000004c
+#define SQ_GLOBAL_ATOMIC_SWAP_X2 0x00000060
+#define SQ_GLOBAL_ATOMIC_CMPSWAP_X2 0x00000061
+#define SQ_GLOBAL_ATOMIC_ADD_X2 0x00000062
+#define SQ_GLOBAL_ATOMIC_SUB_X2 0x00000063
+#define SQ_GLOBAL_ATOMIC_SMIN_X2 0x00000064
+#define SQ_GLOBAL_ATOMIC_UMIN_X2 0x00000065
+#define SQ_GLOBAL_ATOMIC_SMAX_X2 0x00000066
+#define SQ_GLOBAL_ATOMIC_UMAX_X2 0x00000067
+#define SQ_GLOBAL_ATOMIC_AND_X2 0x00000068
+#define SQ_GLOBAL_ATOMIC_OR_X2 0x00000069
+#define SQ_GLOBAL_ATOMIC_XOR_X2 0x0000006a
+#define SQ_GLOBAL_ATOMIC_INC_X2 0x0000006b
+#define SQ_GLOBAL_ATOMIC_DEC_X2 0x0000006c
+
+/*
+ * VALUE_SQ_VGPR value
+ */
+
+#define SQ_VGPR0 0x00000000
+
+/*
+ * VALUE_SQ_OP_FLAT_SCRATCH value
+ */
+
+#define SQ_SCRATCH_LOAD_UBYTE 0x00000010
+#define SQ_SCRATCH_LOAD_SBYTE 0x00000011
+#define SQ_SCRATCH_LOAD_USHORT 0x00000012
+#define SQ_SCRATCH_LOAD_SSHORT 0x00000013
+#define SQ_SCRATCH_LOAD_DWORD 0x00000014
+#define SQ_SCRATCH_LOAD_DWORDX2 0x00000015
+#define SQ_SCRATCH_LOAD_DWORDX3 0x00000016
+#define SQ_SCRATCH_LOAD_DWORDX4 0x00000017
+#define SQ_SCRATCH_STORE_BYTE 0x00000018
+#define SQ_SCRATCH_STORE_SHORT 0x0000001a
+#define SQ_SCRATCH_STORE_DWORD 0x0000001c
+#define SQ_SCRATCH_STORE_DWORDX2 0x0000001d
+#define SQ_SCRATCH_STORE_DWORDX3 0x0000001e
+#define SQ_SCRATCH_STORE_DWORDX4 0x0000001f
+
+/*
+ * VALUE_SQ_VCC value
+ */
+
+#define SQ_VCC_ALL 0x00000000
+
+/*
+ * VALUE_SQ_SSRC_0_63_INLINES value
+ */
+
+#define SQ_SRC_0 0x00000080
+#define SQ_SRC_1_INT 0x00000081
+#define SQ_SRC_2_INT 0x00000082
+#define SQ_SRC_3_INT 0x00000083
+#define SQ_SRC_4_INT 0x00000084
+#define SQ_SRC_5_INT 0x00000085
+#define SQ_SRC_6_INT 0x00000086
+#define SQ_SRC_7_INT 0x00000087
+#define SQ_SRC_8_INT 0x00000088
+#define SQ_SRC_9_INT 0x00000089
+#define SQ_SRC_10_INT 0x0000008a
+#define SQ_SRC_11_INT 0x0000008b
+#define SQ_SRC_12_INT 0x0000008c
+#define SQ_SRC_13_INT 0x0000008d
+#define SQ_SRC_14_INT 0x0000008e
+#define SQ_SRC_15_INT 0x0000008f
+#define SQ_SRC_16_INT 0x00000090
+#define SQ_SRC_17_INT 0x00000091
+#define SQ_SRC_18_INT 0x00000092
+#define SQ_SRC_19_INT 0x00000093
+#define SQ_SRC_20_INT 0x00000094
+#define SQ_SRC_21_INT 0x00000095
+#define SQ_SRC_22_INT 0x00000096
+#define SQ_SRC_23_INT 0x00000097
+#define SQ_SRC_24_INT 0x00000098
+#define SQ_SRC_25_INT 0x00000099
+#define SQ_SRC_26_INT 0x0000009a
+#define SQ_SRC_27_INT 0x0000009b
+#define SQ_SRC_28_INT 0x0000009c
+#define SQ_SRC_29_INT 0x0000009d
+#define SQ_SRC_30_INT 0x0000009e
+#define SQ_SRC_31_INT 0x0000009f
+#define SQ_SRC_32_INT 0x000000a0
+#define SQ_SRC_33_INT 0x000000a1
+#define SQ_SRC_34_INT 0x000000a2
+#define SQ_SRC_35_INT 0x000000a3
+#define SQ_SRC_36_INT 0x000000a4
+#define SQ_SRC_37_INT 0x000000a5
+#define SQ_SRC_38_INT 0x000000a6
+#define SQ_SRC_39_INT 0x000000a7
+#define SQ_SRC_40_INT 0x000000a8
+#define SQ_SRC_41_INT 0x000000a9
+#define SQ_SRC_42_INT 0x000000aa
+#define SQ_SRC_43_INT 0x000000ab
+#define SQ_SRC_44_INT 0x000000ac
+#define SQ_SRC_45_INT 0x000000ad
+#define SQ_SRC_46_INT 0x000000ae
+#define SQ_SRC_47_INT 0x000000af
+#define SQ_SRC_48_INT 0x000000b0
+#define SQ_SRC_49_INT 0x000000b1
+#define SQ_SRC_50_INT 0x000000b2
+#define SQ_SRC_51_INT 0x000000b3
+#define SQ_SRC_52_INT 0x000000b4
+#define SQ_SRC_53_INT 0x000000b5
+#define SQ_SRC_54_INT 0x000000b6
+#define SQ_SRC_55_INT 0x000000b7
+#define SQ_SRC_56_INT 0x000000b8
+#define SQ_SRC_57_INT 0x000000b9
+#define SQ_SRC_58_INT 0x000000ba
+#define SQ_SRC_59_INT 0x000000bb
+#define SQ_SRC_60_INT 0x000000bc
+#define SQ_SRC_61_INT 0x000000bd
+#define SQ_SRC_62_INT 0x000000be
+#define SQ_SRC_63_INT 0x000000bf
+
+/*
+ * VALUE_SQ_OP_MIMG value
+ */
+
+#define SQ_IMAGE_LOAD 0x00000000
+#define SQ_IMAGE_LOAD_MIP 0x00000001
+#define SQ_IMAGE_LOAD_PCK 0x00000002
+#define SQ_IMAGE_LOAD_PCK_SGN 0x00000003
+#define SQ_IMAGE_LOAD_MIP_PCK 0x00000004
+#define SQ_IMAGE_LOAD_MIP_PCK_SGN 0x00000005
+#define SQ_IMAGE_STORE 0x00000008
+#define SQ_IMAGE_STORE_MIP 0x00000009
+#define SQ_IMAGE_STORE_PCK 0x0000000a
+#define SQ_IMAGE_STORE_MIP_PCK 0x0000000b
+#define SQ_IMAGE_GET_RESINFO 0x0000000e
+#define SQ_IMAGE_ATOMIC_SWAP 0x00000010
+#define SQ_IMAGE_ATOMIC_CMPSWAP 0x00000011
+#define SQ_IMAGE_ATOMIC_ADD 0x00000012
+#define SQ_IMAGE_ATOMIC_SUB 0x00000013
+#define SQ_IMAGE_ATOMIC_SMIN 0x00000014
+#define SQ_IMAGE_ATOMIC_UMIN 0x00000015
+#define SQ_IMAGE_ATOMIC_SMAX 0x00000016
+#define SQ_IMAGE_ATOMIC_UMAX 0x00000017
+#define SQ_IMAGE_ATOMIC_AND 0x00000018
+#define SQ_IMAGE_ATOMIC_OR 0x00000019
+#define SQ_IMAGE_ATOMIC_XOR 0x0000001a
+#define SQ_IMAGE_ATOMIC_INC 0x0000001b
+#define SQ_IMAGE_ATOMIC_DEC 0x0000001c
+#define SQ_IMAGE_SAMPLE 0x00000020
+#define SQ_IMAGE_SAMPLE_CL 0x00000021
+#define SQ_IMAGE_SAMPLE_D 0x00000022
+#define SQ_IMAGE_SAMPLE_D_CL 0x00000023
+#define SQ_IMAGE_SAMPLE_L 0x00000024
+#define SQ_IMAGE_SAMPLE_B 0x00000025
+#define SQ_IMAGE_SAMPLE_B_CL 0x00000026
+#define SQ_IMAGE_SAMPLE_LZ 0x00000027
+#define SQ_IMAGE_SAMPLE_C 0x00000028
+#define SQ_IMAGE_SAMPLE_C_CL 0x00000029
+#define SQ_IMAGE_SAMPLE_C_D 0x0000002a
+#define SQ_IMAGE_SAMPLE_C_D_CL 0x0000002b
+#define SQ_IMAGE_SAMPLE_C_L 0x0000002c
+#define SQ_IMAGE_SAMPLE_C_B 0x0000002d
+#define SQ_IMAGE_SAMPLE_C_B_CL 0x0000002e
+#define SQ_IMAGE_SAMPLE_C_LZ 0x0000002f
+#define SQ_IMAGE_SAMPLE_O 0x00000030
+#define SQ_IMAGE_SAMPLE_CL_O 0x00000031
+#define SQ_IMAGE_SAMPLE_D_O 0x00000032
+#define SQ_IMAGE_SAMPLE_D_CL_O 0x00000033
+#define SQ_IMAGE_SAMPLE_L_O 0x00000034
+#define SQ_IMAGE_SAMPLE_B_O 0x00000035
+#define SQ_IMAGE_SAMPLE_B_CL_O 0x00000036
+#define SQ_IMAGE_SAMPLE_LZ_O 0x00000037
+#define SQ_IMAGE_SAMPLE_C_O 0x00000038
+#define SQ_IMAGE_SAMPLE_C_CL_O 0x00000039
+#define SQ_IMAGE_SAMPLE_C_D_O 0x0000003a
+#define SQ_IMAGE_SAMPLE_C_D_CL_O 0x0000003b
+#define SQ_IMAGE_SAMPLE_C_L_O 0x0000003c
+#define SQ_IMAGE_SAMPLE_C_B_O 0x0000003d
+#define SQ_IMAGE_SAMPLE_C_B_CL_O 0x0000003e
+#define SQ_IMAGE_SAMPLE_C_LZ_O 0x0000003f
+#define SQ_IMAGE_GATHER4 0x00000040
+#define SQ_IMAGE_GATHER4_CL 0x00000041
+#define SQ_IMAGE_GATHER4H 0x00000042
+#define SQ_IMAGE_GATHER4_L 0x00000044
+#define SQ_IMAGE_GATHER4_B 0x00000045
+#define SQ_IMAGE_GATHER4_B_CL 0x00000046
+#define SQ_IMAGE_GATHER4_LZ 0x00000047
+#define SQ_IMAGE_GATHER4_C 0x00000048
+#define SQ_IMAGE_GATHER4_C_CL 0x00000049
+#define SQ_IMAGE_GATHER4H_PCK 0x0000004a
+#define SQ_IMAGE_GATHER8H_PCK 0x0000004b
+#define SQ_IMAGE_GATHER4_C_L 0x0000004c
+#define SQ_IMAGE_GATHER4_C_B 0x0000004d
+#define SQ_IMAGE_GATHER4_C_B_CL 0x0000004e
+#define SQ_IMAGE_GATHER4_C_LZ 0x0000004f
+#define SQ_IMAGE_GATHER4_O 0x00000050
+#define SQ_IMAGE_GATHER4_CL_O 0x00000051
+#define SQ_IMAGE_GATHER4_L_O 0x00000054
+#define SQ_IMAGE_GATHER4_B_O 0x00000055
+#define SQ_IMAGE_GATHER4_B_CL_O 0x00000056
+#define SQ_IMAGE_GATHER4_LZ_O 0x00000057
+#define SQ_IMAGE_GATHER4_C_O 0x00000058
+#define SQ_IMAGE_GATHER4_C_CL_O 0x00000059
+#define SQ_IMAGE_GATHER4_C_L_O 0x0000005c
+#define SQ_IMAGE_GATHER4_C_B_O 0x0000005d
+#define SQ_IMAGE_GATHER4_C_B_CL_O 0x0000005e
+#define SQ_IMAGE_GATHER4_C_LZ_O 0x0000005f
+#define SQ_IMAGE_GET_LOD 0x00000060
+#define SQ_IMAGE_SAMPLE_CD 0x00000068
+#define SQ_IMAGE_SAMPLE_CD_CL 0x00000069
+#define SQ_IMAGE_SAMPLE_C_CD 0x0000006a
+#define SQ_IMAGE_SAMPLE_C_CD_CL 0x0000006b
+#define SQ_IMAGE_SAMPLE_CD_O 0x0000006c
+#define SQ_IMAGE_SAMPLE_CD_CL_O 0x0000006d
+#define SQ_IMAGE_SAMPLE_C_CD_O 0x0000006e
+#define SQ_IMAGE_SAMPLE_C_CD_CL_O 0x0000006f
+#define SQ_IMAGE_RSRC256 0x0000007e
+#define SQ_IMAGE_SAMPLER 0x0000007f
+
+/*
+ * VALUE_SQ_HW_REG value
+ */
+
+#define SQ_HW_REG_MODE 0x00000001
+#define SQ_HW_REG_STATUS 0x00000002
+#define SQ_HW_REG_TRAPSTS 0x00000003
+#define SQ_HW_REG_HW_ID 0x00000004
+#define SQ_HW_REG_GPR_ALLOC 0x00000005
+#define SQ_HW_REG_LDS_ALLOC 0x00000006
+#define SQ_HW_REG_IB_STS 0x00000007
+#define SQ_HW_REG_PC_LO 0x00000008
+#define SQ_HW_REG_PC_HI 0x00000009
+#define SQ_HW_REG_INST_DW0 0x0000000a
+#define SQ_HW_REG_INST_DW1 0x0000000b
+#define SQ_HW_REG_IB_DBG0 0x0000000c
+#define SQ_HW_REG_IB_DBG1 0x0000000d
+#define SQ_HW_REG_FLUSH_IB 0x0000000e
+#define SQ_HW_REG_SH_MEM_BASES 0x0000000f
+#define SQ_HW_REG_SQ_SHADER_TBA_LO 0x00000010
+#define SQ_HW_REG_SQ_SHADER_TBA_HI 0x00000011
+#define SQ_HW_REG_SQ_SHADER_TMA_LO 0x00000012
+#define SQ_HW_REG_SQ_SHADER_TMA_HI 0x00000013
+
+/*
+ * VALUE_SQ_OP_SOP1 value
+ */
+
+#define SQ_S_MOV_B32 0x00000000
+#define SQ_S_MOV_B64 0x00000001
+#define SQ_S_CMOV_B32 0x00000002
+#define SQ_S_CMOV_B64 0x00000003
+#define SQ_S_NOT_B32 0x00000004
+#define SQ_S_NOT_B64 0x00000005
+#define SQ_S_WQM_B32 0x00000006
+#define SQ_S_WQM_B64 0x00000007
+#define SQ_S_BREV_B32 0x00000008
+#define SQ_S_BREV_B64 0x00000009
+#define SQ_S_BCNT0_I32_B32 0x0000000a
+#define SQ_S_BCNT0_I32_B64 0x0000000b
+#define SQ_S_BCNT1_I32_B32 0x0000000c
+#define SQ_S_BCNT1_I32_B64 0x0000000d
+#define SQ_S_FF0_I32_B32 0x0000000e
+#define SQ_S_FF0_I32_B64 0x0000000f
+#define SQ_S_FF1_I32_B32 0x00000010
+#define SQ_S_FF1_I32_B64 0x00000011
+#define SQ_S_FLBIT_I32_B32 0x00000012
+#define SQ_S_FLBIT_I32_B64 0x00000013
+#define SQ_S_FLBIT_I32 0x00000014
+#define SQ_S_FLBIT_I32_I64 0x00000015
+#define SQ_S_SEXT_I32_I8 0x00000016
+#define SQ_S_SEXT_I32_I16 0x00000017
+#define SQ_S_BITSET0_B32 0x00000018
+#define SQ_S_BITSET0_B64 0x00000019
+#define SQ_S_BITSET1_B32 0x0000001a
+#define SQ_S_BITSET1_B64 0x0000001b
+#define SQ_S_GETPC_B64 0x0000001c
+#define SQ_S_SETPC_B64 0x0000001d
+#define SQ_S_SWAPPC_B64 0x0000001e
+#define SQ_S_RFE_B64 0x0000001f
+#define SQ_S_AND_SAVEEXEC_B64 0x00000020
+#define SQ_S_OR_SAVEEXEC_B64 0x00000021
+#define SQ_S_XOR_SAVEEXEC_B64 0x00000022
+#define SQ_S_ANDN2_SAVEEXEC_B64 0x00000023
+#define SQ_S_ORN2_SAVEEXEC_B64 0x00000024
+#define SQ_S_NAND_SAVEEXEC_B64 0x00000025
+#define SQ_S_NOR_SAVEEXEC_B64 0x00000026
+#define SQ_S_XNOR_SAVEEXEC_B64 0x00000027
+#define SQ_S_QUADMASK_B32 0x00000028
+#define SQ_S_QUADMASK_B64 0x00000029
+#define SQ_S_MOVRELS_B32 0x0000002a
+#define SQ_S_MOVRELS_B64 0x0000002b
+#define SQ_S_MOVRELD_B32 0x0000002c
+#define SQ_S_MOVRELD_B64 0x0000002d
+#define SQ_S_CBRANCH_JOIN 0x0000002e
+#define SQ_S_MOV_REGRD_B32 0x0000002f
+#define SQ_S_ABS_I32 0x00000030
+#define SQ_S_MOV_FED_B32 0x00000031
+#define SQ_S_SET_GPR_IDX_IDX 0x00000032
+#define SQ_S_ANDN1_SAVEEXEC_B64 0x00000033
+#define SQ_S_ORN1_SAVEEXEC_B64 0x00000034
+#define SQ_S_ANDN1_WREXEC_B64 0x00000035
+#define SQ_S_ANDN2_WREXEC_B64 0x00000036
+#define SQ_S_BITREPLICATE_B64_B32 0x00000037
+
+/*
+ * VALUE_SQ_CNT value
+ */
+
+#define SQ_CNT1 0x00000000
+#define SQ_CNT2 0x00000001
+#define SQ_CNT3 0x00000002
+#define SQ_CNT4 0x00000003
+
+/*
+ * VALUE_SQ_OP_VOP3 value
+ */
+
+#define SQ_V_MAD_LEGACY_F32 0x000001c0
+#define SQ_V_MAD_F32 0x000001c1
+#define SQ_V_MAD_I32_I24 0x000001c2
+#define SQ_V_MAD_U32_U24 0x000001c3
+#define SQ_V_CUBEID_F32 0x000001c4
+#define SQ_V_CUBESC_F32 0x000001c5
+#define SQ_V_CUBETC_F32 0x000001c6
+#define SQ_V_CUBEMA_F32 0x000001c7
+#define SQ_V_BFE_U32 0x000001c8
+#define SQ_V_BFE_I32 0x000001c9
+#define SQ_V_BFI_B32 0x000001ca
+#define SQ_V_FMA_F32 0x000001cb
+#define SQ_V_FMA_F64 0x000001cc
+#define SQ_V_LERP_U8 0x000001cd
+#define SQ_V_ALIGNBIT_B32 0x000001ce
+#define SQ_V_ALIGNBYTE_B32 0x000001cf
+#define SQ_V_MIN3_F32 0x000001d0
+#define SQ_V_MIN3_I32 0x000001d1
+#define SQ_V_MIN3_U32 0x000001d2
+#define SQ_V_MAX3_F32 0x000001d3
+#define SQ_V_MAX3_I32 0x000001d4
+#define SQ_V_MAX3_U32 0x000001d5
+#define SQ_V_MED3_F32 0x000001d6
+#define SQ_V_MED3_I32 0x000001d7
+#define SQ_V_MED3_U32 0x000001d8
+#define SQ_V_SAD_U8 0x000001d9
+#define SQ_V_SAD_HI_U8 0x000001da
+#define SQ_V_SAD_U16 0x000001db
+#define SQ_V_SAD_U32 0x000001dc
+#define SQ_V_CVT_PK_U8_F32 0x000001dd
+#define SQ_V_DIV_FIXUP_F32 0x000001de
+#define SQ_V_DIV_FIXUP_F64 0x000001df
+#define SQ_V_DIV_SCALE_F32 0x000001e0
+#define SQ_V_DIV_SCALE_F64 0x000001e1
+#define SQ_V_DIV_FMAS_F32 0x000001e2
+#define SQ_V_DIV_FMAS_F64 0x000001e3
+#define SQ_V_MSAD_U8 0x000001e4
+#define SQ_V_QSAD_PK_U16_U8 0x000001e5
+#define SQ_V_MQSAD_PK_U16_U8 0x000001e6
+#define SQ_V_MQSAD_U32_U8 0x000001e7
+#define SQ_V_MAD_U64_U32 0x000001e8
+#define SQ_V_MAD_I64_I32 0x000001e9
+#define SQ_V_MAD_LEGACY_F16 0x000001ea
+#define SQ_V_MAD_LEGACY_U16 0x000001eb
+#define SQ_V_MAD_LEGACY_I16 0x000001ec
+#define SQ_V_PERM_B32 0x000001ed
+#define SQ_V_FMA_LEGACY_F16 0x000001ee
+#define SQ_V_DIV_FIXUP_LEGACY_F16 0x000001ef
+#define SQ_V_CVT_PKACCUM_U8_F32 0x000001f0
+#define SQ_V_MAD_U32_U16 0x000001f1
+#define SQ_V_MAD_I32_I16 0x000001f2
+#define SQ_V_XAD_U32 0x000001f3
+#define SQ_V_MIN3_F16 0x000001f4
+#define SQ_V_MIN3_I16 0x000001f5
+#define SQ_V_MIN3_U16 0x000001f6
+#define SQ_V_MAX3_F16 0x000001f7
+#define SQ_V_MAX3_I16 0x000001f8
+#define SQ_V_MAX3_U16 0x000001f9
+#define SQ_V_MED3_F16 0x000001fa
+#define SQ_V_MED3_I16 0x000001fb
+#define SQ_V_MED3_U16 0x000001fc
+#define SQ_V_LSHL_ADD_U32 0x000001fd
+#define SQ_V_ADD_LSHL_U32 0x000001fe
+#define SQ_V_ADD3_U32 0x000001ff
+#define SQ_V_LSHL_OR_B32 0x00000200
+#define SQ_V_AND_OR_B32 0x00000201
+#define SQ_V_OR3_B32 0x00000202
+#define SQ_V_MAD_F16 0x00000203
+#define SQ_V_MAD_U16 0x00000204
+#define SQ_V_MAD_I16 0x00000205
+#define SQ_V_FMA_F16 0x00000206
+#define SQ_V_DIV_FIXUP_F16 0x00000207
+#define SQ_V_INTERP_P1LL_F16 0x00000274
+#define SQ_V_INTERP_P1LV_F16 0x00000275
+#define SQ_V_INTERP_P2_LEGACY_F16 0x00000276
+#define SQ_V_INTERP_P2_F16 0x00000277
+#define SQ_V_ADD_F64 0x00000280
+#define SQ_V_MUL_F64 0x00000281
+#define SQ_V_MIN_F64 0x00000282
+#define SQ_V_MAX_F64 0x00000283
+#define SQ_V_LDEXP_F64 0x00000284
+#define SQ_V_MUL_LO_U32 0x00000285
+#define SQ_V_MUL_HI_U32 0x00000286
+#define SQ_V_MUL_HI_I32 0x00000287
+#define SQ_V_LDEXP_F32 0x00000288
+#define SQ_V_READLANE_B32 0x00000289
+#define SQ_V_WRITELANE_B32 0x0000028a
+#define SQ_V_BCNT_U32_B32 0x0000028b
+#define SQ_V_MBCNT_LO_U32_B32 0x0000028c
+#define SQ_V_MBCNT_HI_U32_B32 0x0000028d
+#define SQ_V_MAC_LEGACY_F32 0x0000028e
+#define SQ_V_LSHLREV_B64 0x0000028f
+#define SQ_V_LSHRREV_B64 0x00000290
+#define SQ_V_ASHRREV_I64 0x00000291
+#define SQ_V_TRIG_PREOP_F64 0x00000292
+#define SQ_V_BFM_B32 0x00000293
+#define SQ_V_CVT_PKNORM_I16_F32 0x00000294
+#define SQ_V_CVT_PKNORM_U16_F32 0x00000295
+#define SQ_V_CVT_PKRTZ_F16_F32 0x00000296
+#define SQ_V_CVT_PK_U16_U32 0x00000297
+#define SQ_V_CVT_PK_I16_I32 0x00000298
+#define SQ_V_CVT_PKNORM_I16_F16 0x00000299
+#define SQ_V_CVT_PKNORM_U16_F16 0x0000029a
+#define SQ_V_READLANE_REGRD_B32 0x0000029b
+#define SQ_V_ADD_I32 0x0000029c
+#define SQ_V_SUB_I32 0x0000029d
+#define SQ_V_ADD_I16 0x0000029e
+#define SQ_V_SUB_I16 0x0000029f
+#define SQ_V_PACK_B32_F16 0x000002a0
+
+/*
+ * VALUE_SQ_SSRC_SPECIAL_LIT value
+ */
+
+#define SQ_SRC_LITERAL 0x000000ff
+
+/*
+ * VALUE_SQ_DPP_CTRL value
+ */
+
+#define SQ_DPP_QUAD_PERM 0x00000000
+#define SQ_DPP_ROW_SL1 0x00000101
+#define SQ_DPP_ROW_SL2 0x00000102
+#define SQ_DPP_ROW_SL3 0x00000103
+#define SQ_DPP_ROW_SL4 0x00000104
+#define SQ_DPP_ROW_SL5 0x00000105
+#define SQ_DPP_ROW_SL6 0x00000106
+#define SQ_DPP_ROW_SL7 0x00000107
+#define SQ_DPP_ROW_SL8 0x00000108
+#define SQ_DPP_ROW_SL9 0x00000109
+#define SQ_DPP_ROW_SL10 0x0000010a
+#define SQ_DPP_ROW_SL11 0x0000010b
+#define SQ_DPP_ROW_SL12 0x0000010c
+#define SQ_DPP_ROW_SL13 0x0000010d
+#define SQ_DPP_ROW_SL14 0x0000010e
+#define SQ_DPP_ROW_SL15 0x0000010f
+#define SQ_DPP_ROW_SR1 0x00000111
+#define SQ_DPP_ROW_SR2 0x00000112
+#define SQ_DPP_ROW_SR3 0x00000113
+#define SQ_DPP_ROW_SR4 0x00000114
+#define SQ_DPP_ROW_SR5 0x00000115
+#define SQ_DPP_ROW_SR6 0x00000116
+#define SQ_DPP_ROW_SR7 0x00000117
+#define SQ_DPP_ROW_SR8 0x00000118
+#define SQ_DPP_ROW_SR9 0x00000119
+#define SQ_DPP_ROW_SR10 0x0000011a
+#define SQ_DPP_ROW_SR11 0x0000011b
+#define SQ_DPP_ROW_SR12 0x0000011c
+#define SQ_DPP_ROW_SR13 0x0000011d
+#define SQ_DPP_ROW_SR14 0x0000011e
+#define SQ_DPP_ROW_SR15 0x0000011f
+#define SQ_DPP_ROW_RR1 0x00000121
+#define SQ_DPP_ROW_RR2 0x00000122
+#define SQ_DPP_ROW_RR3 0x00000123
+#define SQ_DPP_ROW_RR4 0x00000124
+#define SQ_DPP_ROW_RR5 0x00000125
+#define SQ_DPP_ROW_RR6 0x00000126
+#define SQ_DPP_ROW_RR7 0x00000127
+#define SQ_DPP_ROW_RR8 0x00000128
+#define SQ_DPP_ROW_RR9 0x00000129
+#define SQ_DPP_ROW_RR10 0x0000012a
+#define SQ_DPP_ROW_RR11 0x0000012b
+#define SQ_DPP_ROW_RR12 0x0000012c
+#define SQ_DPP_ROW_RR13 0x0000012d
+#define SQ_DPP_ROW_RR14 0x0000012e
+#define SQ_DPP_ROW_RR15 0x0000012f
+#define SQ_DPP_WF_SL1 0x00000130
+#define SQ_DPP_WF_RL1 0x00000134
+#define SQ_DPP_WF_SR1 0x00000138
+#define SQ_DPP_WF_RR1 0x0000013c
+#define SQ_DPP_ROW_MIRROR 0x00000140
+#define SQ_DPP_ROW_HALF_MIRROR 0x00000141
+#define SQ_DPP_ROW_BCAST15 0x00000142
+#define SQ_DPP_ROW_BCAST31 0x00000143
+
+/*
+ * VALUE_SQ_FLAT_SCRATCH_LOHI value
+ */
+
+#define SQ_FLAT_SCRATCH_LO 0x00000066
+#define SQ_FLAT_SCRATCH_HI 0x00000067
+
+/*
+ * VALUE_SQ_OP_VOP1 value
+ */
+
+#define SQ_V_NOP 0x00000000
+#define SQ_V_MOV_B32 0x00000001
+#define SQ_V_READFIRSTLANE_B32 0x00000002
+#define SQ_V_CVT_I32_F64 0x00000003
+#define SQ_V_CVT_F64_I32 0x00000004
+#define SQ_V_CVT_F32_I32 0x00000005
+#define SQ_V_CVT_F32_U32 0x00000006
+#define SQ_V_CVT_U32_F32 0x00000007
+#define SQ_V_CVT_I32_F32 0x00000008
+#define SQ_V_MOV_FED_B32 0x00000009
+#define SQ_V_CVT_F16_F32 0x0000000a
+#define SQ_V_CVT_F32_F16 0x0000000b
+#define SQ_V_CVT_RPI_I32_F32 0x0000000c
+#define SQ_V_CVT_FLR_I32_F32 0x0000000d
+#define SQ_V_CVT_OFF_F32_I4 0x0000000e
+#define SQ_V_CVT_F32_F64 0x0000000f
+#define SQ_V_CVT_F64_F32 0x00000010
+#define SQ_V_CVT_F32_UBYTE0 0x00000011
+#define SQ_V_CVT_F32_UBYTE1 0x00000012
+#define SQ_V_CVT_F32_UBYTE2 0x00000013
+#define SQ_V_CVT_F32_UBYTE3 0x00000014
+#define SQ_V_CVT_U32_F64 0x00000015
+#define SQ_V_CVT_F64_U32 0x00000016
+#define SQ_V_TRUNC_F64 0x00000017
+#define SQ_V_CEIL_F64 0x00000018
+#define SQ_V_RNDNE_F64 0x00000019
+#define SQ_V_FLOOR_F64 0x0000001a
+#define SQ_V_FRACT_F32 0x0000001b
+#define SQ_V_TRUNC_F32 0x0000001c
+#define SQ_V_CEIL_F32 0x0000001d
+#define SQ_V_RNDNE_F32 0x0000001e
+#define SQ_V_FLOOR_F32 0x0000001f
+#define SQ_V_EXP_F32 0x00000020
+#define SQ_V_LOG_F32 0x00000021
+#define SQ_V_RCP_F32 0x00000022
+#define SQ_V_RCP_IFLAG_F32 0x00000023
+#define SQ_V_RSQ_F32 0x00000024
+#define SQ_V_RCP_F64 0x00000025
+#define SQ_V_RSQ_F64 0x00000026
+#define SQ_V_SQRT_F32 0x00000027
+#define SQ_V_SQRT_F64 0x00000028
+#define SQ_V_SIN_F32 0x00000029
+#define SQ_V_COS_F32 0x0000002a
+#define SQ_V_NOT_B32 0x0000002b
+#define SQ_V_BFREV_B32 0x0000002c
+#define SQ_V_FFBH_U32 0x0000002d
+#define SQ_V_FFBL_B32 0x0000002e
+#define SQ_V_FFBH_I32 0x0000002f
+#define SQ_V_FREXP_EXP_I32_F64 0x00000030
+#define SQ_V_FREXP_MANT_F64 0x00000031
+#define SQ_V_FRACT_F64 0x00000032
+#define SQ_V_FREXP_EXP_I32_F32 0x00000033
+#define SQ_V_FREXP_MANT_F32 0x00000034
+#define SQ_V_CLREXCP 0x00000035
+#define SQ_V_MOV_PRSV_B32 0x00000036
+#define SQ_V_CVT_F16_U16 0x00000039
+#define SQ_V_CVT_F16_I16 0x0000003a
+#define SQ_V_CVT_U16_F16 0x0000003b
+#define SQ_V_CVT_I16_F16 0x0000003c
+#define SQ_V_RCP_F16 0x0000003d
+#define SQ_V_SQRT_F16 0x0000003e
+#define SQ_V_RSQ_F16 0x0000003f
+#define SQ_V_LOG_F16 0x00000040
+#define SQ_V_EXP_F16 0x00000041
+#define SQ_V_FREXP_MANT_F16 0x00000042
+#define SQ_V_FREXP_EXP_I16_F16 0x00000043
+#define SQ_V_FLOOR_F16 0x00000044
+#define SQ_V_CEIL_F16 0x00000045
+#define SQ_V_TRUNC_F16 0x00000046
+#define SQ_V_RNDNE_F16 0x00000047
+#define SQ_V_FRACT_F16 0x00000048
+#define SQ_V_SIN_F16 0x00000049
+#define SQ_V_COS_F16 0x0000004a
+#define SQ_V_EXP_LEGACY_F32 0x0000004b
+#define SQ_V_LOG_LEGACY_F32 0x0000004c
+#define SQ_V_CVT_NORM_I16_F16 0x0000004d
+#define SQ_V_CVT_NORM_U16_F16 0x0000004e
+#define SQ_V_SAT_PK_U8_I16 0x0000004f
+#define SQ_V_WRITELANE_IMM32 0x00000050
+#define SQ_V_SWAP_B32 0x00000051
+
+/*
+ * VALUE_SQ_OP_FLAT value
+ */
+
+#define SQ_FLAT_LOAD_UBYTE 0x00000010
+#define SQ_FLAT_LOAD_SBYTE 0x00000011
+#define SQ_FLAT_LOAD_USHORT 0x00000012
+#define SQ_FLAT_LOAD_SSHORT 0x00000013
+#define SQ_FLAT_LOAD_DWORD 0x00000014
+#define SQ_FLAT_LOAD_DWORDX2 0x00000015
+#define SQ_FLAT_LOAD_DWORDX3 0x00000016
+#define SQ_FLAT_LOAD_DWORDX4 0x00000017
+#define SQ_FLAT_STORE_BYTE 0x00000018
+#define SQ_FLAT_STORE_SHORT 0x0000001a
+#define SQ_FLAT_STORE_DWORD 0x0000001c
+#define SQ_FLAT_STORE_DWORDX2 0x0000001d
+#define SQ_FLAT_STORE_DWORDX3 0x0000001e
+#define SQ_FLAT_STORE_DWORDX4 0x0000001f
+#define SQ_FLAT_ATOMIC_SWAP 0x00000040
+#define SQ_FLAT_ATOMIC_CMPSWAP 0x00000041
+#define SQ_FLAT_ATOMIC_ADD 0x00000042
+#define SQ_FLAT_ATOMIC_SUB 0x00000043
+#define SQ_FLAT_ATOMIC_SMIN 0x00000044
+#define SQ_FLAT_ATOMIC_UMIN 0x00000045
+#define SQ_FLAT_ATOMIC_SMAX 0x00000046
+#define SQ_FLAT_ATOMIC_UMAX 0x00000047
+#define SQ_FLAT_ATOMIC_AND 0x00000048
+#define SQ_FLAT_ATOMIC_OR 0x00000049
+#define SQ_FLAT_ATOMIC_XOR 0x0000004a
+#define SQ_FLAT_ATOMIC_INC 0x0000004b
+#define SQ_FLAT_ATOMIC_DEC 0x0000004c
+#define SQ_FLAT_ATOMIC_SWAP_X2 0x00000060
+#define SQ_FLAT_ATOMIC_CMPSWAP_X2 0x00000061
+#define SQ_FLAT_ATOMIC_ADD_X2 0x00000062
+#define SQ_FLAT_ATOMIC_SUB_X2 0x00000063
+#define SQ_FLAT_ATOMIC_SMIN_X2 0x00000064
+#define SQ_FLAT_ATOMIC_UMIN_X2 0x00000065
+#define SQ_FLAT_ATOMIC_SMAX_X2 0x00000066
+#define SQ_FLAT_ATOMIC_UMAX_X2 0x00000067
+#define SQ_FLAT_ATOMIC_AND_X2 0x00000068
+#define SQ_FLAT_ATOMIC_OR_X2 0x00000069
+#define SQ_FLAT_ATOMIC_XOR_X2 0x0000006a
+#define SQ_FLAT_ATOMIC_INC_X2 0x0000006b
+#define SQ_FLAT_ATOMIC_DEC_X2 0x0000006c
+
+/*
+ * VALUE_SQ_OP_DS value
+ */
+
+#define SQ_DS_ADD_U32 0x00000000
+#define SQ_DS_SUB_U32 0x00000001
+#define SQ_DS_RSUB_U32 0x00000002
+#define SQ_DS_INC_U32 0x00000003
+#define SQ_DS_DEC_U32 0x00000004
+#define SQ_DS_MIN_I32 0x00000005
+#define SQ_DS_MAX_I32 0x00000006
+#define SQ_DS_MIN_U32 0x00000007
+#define SQ_DS_MAX_U32 0x00000008
+#define SQ_DS_AND_B32 0x00000009
+#define SQ_DS_OR_B32 0x0000000a
+#define SQ_DS_XOR_B32 0x0000000b
+#define SQ_DS_MSKOR_B32 0x0000000c
+#define SQ_DS_WRITE_B32 0x0000000d
+#define SQ_DS_WRITE2_B32 0x0000000e
+#define SQ_DS_WRITE2ST64_B32 0x0000000f
+#define SQ_DS_CMPST_B32 0x00000010
+#define SQ_DS_CMPST_F32 0x00000011
+#define SQ_DS_MIN_F32 0x00000012
+#define SQ_DS_MAX_F32 0x00000013
+#define SQ_DS_NOP 0x00000014
+#define SQ_DS_ADD_F32 0x00000015
+#define SQ_DS_WRITE_ADDTID_B32 0x0000001d
+#define SQ_DS_WRITE_B8 0x0000001e
+#define SQ_DS_WRITE_B16 0x0000001f
+#define SQ_DS_ADD_RTN_U32 0x00000020
+#define SQ_DS_SUB_RTN_U32 0x00000021
+#define SQ_DS_RSUB_RTN_U32 0x00000022
+#define SQ_DS_INC_RTN_U32 0x00000023
+#define SQ_DS_DEC_RTN_U32 0x00000024
+#define SQ_DS_MIN_RTN_I32 0x00000025
+#define SQ_DS_MAX_RTN_I32 0x00000026
+#define SQ_DS_MIN_RTN_U32 0x00000027
+#define SQ_DS_MAX_RTN_U32 0x00000028
+#define SQ_DS_AND_RTN_B32 0x00000029
+#define SQ_DS_OR_RTN_B32 0x0000002a
+#define SQ_DS_XOR_RTN_B32 0x0000002b
+#define SQ_DS_MSKOR_RTN_B32 0x0000002c
+#define SQ_DS_WRXCHG_RTN_B32 0x0000002d
+#define SQ_DS_WRXCHG2_RTN_B32 0x0000002e
+#define SQ_DS_WRXCHG2ST64_RTN_B32 0x0000002f
+#define SQ_DS_CMPST_RTN_B32 0x00000030
+#define SQ_DS_CMPST_RTN_F32 0x00000031
+#define SQ_DS_MIN_RTN_F32 0x00000032
+#define SQ_DS_MAX_RTN_F32 0x00000033
+#define SQ_DS_WRAP_RTN_B32 0x00000034
+#define SQ_DS_ADD_RTN_F32 0x00000035
+#define SQ_DS_READ_B32 0x00000036
+#define SQ_DS_READ2_B32 0x00000037
+#define SQ_DS_READ2ST64_B32 0x00000038
+#define SQ_DS_READ_I8 0x00000039
+#define SQ_DS_READ_U8 0x0000003a
+#define SQ_DS_READ_I16 0x0000003b
+#define SQ_DS_READ_U16 0x0000003c
+#define SQ_DS_SWIZZLE_B32 0x0000003d
+#define SQ_DS_PERMUTE_B32 0x0000003e
+#define SQ_DS_BPERMUTE_B32 0x0000003f
+#define SQ_DS_ADD_U64 0x00000040
+#define SQ_DS_SUB_U64 0x00000041
+#define SQ_DS_RSUB_U64 0x00000042
+#define SQ_DS_INC_U64 0x00000043
+#define SQ_DS_DEC_U64 0x00000044
+#define SQ_DS_MIN_I64 0x00000045
+#define SQ_DS_MAX_I64 0x00000046
+#define SQ_DS_MIN_U64 0x00000047
+#define SQ_DS_MAX_U64 0x00000048
+#define SQ_DS_AND_B64 0x00000049
+#define SQ_DS_OR_B64 0x0000004a
+#define SQ_DS_XOR_B64 0x0000004b
+#define SQ_DS_MSKOR_B64 0x0000004c
+#define SQ_DS_WRITE_B64 0x0000004d
+#define SQ_DS_WRITE2_B64 0x0000004e
+#define SQ_DS_WRITE2ST64_B64 0x0000004f
+#define SQ_DS_CMPST_B64 0x00000050
+#define SQ_DS_CMPST_F64 0x00000051
+#define SQ_DS_MIN_F64 0x00000052
+#define SQ_DS_MAX_F64 0x00000053
+#define SQ_DS_ADD_RTN_U64 0x00000060
+#define SQ_DS_SUB_RTN_U64 0x00000061
+#define SQ_DS_RSUB_RTN_U64 0x00000062
+#define SQ_DS_INC_RTN_U64 0x00000063
+#define SQ_DS_DEC_RTN_U64 0x00000064
+#define SQ_DS_MIN_RTN_I64 0x00000065
+#define SQ_DS_MAX_RTN_I64 0x00000066
+#define SQ_DS_MIN_RTN_U64 0x00000067
+#define SQ_DS_MAX_RTN_U64 0x00000068
+#define SQ_DS_AND_RTN_B64 0x00000069
+#define SQ_DS_OR_RTN_B64 0x0000006a
+#define SQ_DS_XOR_RTN_B64 0x0000006b
+#define SQ_DS_MSKOR_RTN_B64 0x0000006c
+#define SQ_DS_WRXCHG_RTN_B64 0x0000006d
+#define SQ_DS_WRXCHG2_RTN_B64 0x0000006e
+#define SQ_DS_WRXCHG2ST64_RTN_B64 0x0000006f
+#define SQ_DS_CMPST_RTN_B64 0x00000070
+#define SQ_DS_CMPST_RTN_F64 0x00000071
+#define SQ_DS_MIN_RTN_F64 0x00000072
+#define SQ_DS_MAX_RTN_F64 0x00000073
+#define SQ_DS_READ_B64 0x00000076
+#define SQ_DS_READ2_B64 0x00000077
+#define SQ_DS_READ2ST64_B64 0x00000078
+#define SQ_DS_CONDXCHG32_RTN_B64 0x0000007e
+#define SQ_DS_ADD_SRC2_U32 0x00000080
+#define SQ_DS_SUB_SRC2_U32 0x00000081
+#define SQ_DS_RSUB_SRC2_U32 0x00000082
+#define SQ_DS_INC_SRC2_U32 0x00000083
+#define SQ_DS_DEC_SRC2_U32 0x00000084
+#define SQ_DS_MIN_SRC2_I32 0x00000085
+#define SQ_DS_MAX_SRC2_I32 0x00000086
+#define SQ_DS_MIN_SRC2_U32 0x00000087
+#define SQ_DS_MAX_SRC2_U32 0x00000088
+#define SQ_DS_AND_SRC2_B32 0x00000089
+#define SQ_DS_OR_SRC2_B32 0x0000008a
+#define SQ_DS_XOR_SRC2_B32 0x0000008b
+#define SQ_DS_WRITE_SRC2_B32 0x0000008d
+#define SQ_DS_MIN_SRC2_F32 0x00000092
+#define SQ_DS_MAX_SRC2_F32 0x00000093
+#define SQ_DS_ADD_SRC2_F32 0x00000095
+#define SQ_DS_GWS_SEMA_RELEASE_ALL 0x00000098
+#define SQ_DS_GWS_INIT 0x00000099
+#define SQ_DS_GWS_SEMA_V 0x0000009a
+#define SQ_DS_GWS_SEMA_BR 0x0000009b
+#define SQ_DS_GWS_SEMA_P 0x0000009c
+#define SQ_DS_GWS_BARRIER 0x0000009d
+#define SQ_DS_READ_ADDTID_B32 0x000000b6
+#define SQ_DS_CONSUME 0x000000bd
+#define SQ_DS_APPEND 0x000000be
+#define SQ_DS_ORDERED_COUNT 0x000000bf
+#define SQ_DS_ADD_SRC2_U64 0x000000c0
+#define SQ_DS_SUB_SRC2_U64 0x000000c1
+#define SQ_DS_RSUB_SRC2_U64 0x000000c2
+#define SQ_DS_INC_SRC2_U64 0x000000c3
+#define SQ_DS_DEC_SRC2_U64 0x000000c4
+#define SQ_DS_MIN_SRC2_I64 0x000000c5
+#define SQ_DS_MAX_SRC2_I64 0x000000c6
+#define SQ_DS_MIN_SRC2_U64 0x000000c7
+#define SQ_DS_MAX_SRC2_U64 0x000000c8
+#define SQ_DS_AND_SRC2_B64 0x000000c9
+#define SQ_DS_OR_SRC2_B64 0x000000ca
+#define SQ_DS_XOR_SRC2_B64 0x000000cb
+#define SQ_DS_WRITE_SRC2_B64 0x000000cd
+#define SQ_DS_MIN_SRC2_F64 0x000000d2
+#define SQ_DS_MAX_SRC2_F64 0x000000d3
+#define SQ_DS_WRITE_B96 0x000000de
+#define SQ_DS_WRITE_B128 0x000000df
+#define SQ_DS_CONDXCHG32_RTN_B128 0x000000fd
+#define SQ_DS_READ_B96 0x000000fe
+#define SQ_DS_READ_B128 0x000000ff
+
+/*
+ * VALUE_SQ_OP_SMEM value
+ */
+
+#define SQ_S_LOAD_DWORD 0x00000000
+#define SQ_S_LOAD_DWORDX2 0x00000001
+#define SQ_S_LOAD_DWORDX4 0x00000002
+#define SQ_S_LOAD_DWORDX8 0x00000003
+#define SQ_S_LOAD_DWORDX16 0x00000004
+#define SQ_S_SCRATCH_LOAD_DWORD 0x00000005
+#define SQ_S_SCRATCH_LOAD_DWORDX2 0x00000006
+#define SQ_S_SCRATCH_LOAD_DWORDX4 0x00000007
+#define SQ_S_BUFFER_LOAD_DWORD 0x00000008
+#define SQ_S_BUFFER_LOAD_DWORDX2 0x00000009
+#define SQ_S_BUFFER_LOAD_DWORDX4 0x0000000a
+#define SQ_S_BUFFER_LOAD_DWORDX8 0x0000000b
+#define SQ_S_BUFFER_LOAD_DWORDX16 0x0000000c
+#define SQ_S_STORE_DWORD 0x00000010
+#define SQ_S_STORE_DWORDX2 0x00000011
+#define SQ_S_STORE_DWORDX4 0x00000012
+#define SQ_S_SCRATCH_STORE_DWORD 0x00000015
+#define SQ_S_SCRATCH_STORE_DWORDX2 0x00000016
+#define SQ_S_SCRATCH_STORE_DWORDX4 0x00000017
+#define SQ_S_BUFFER_STORE_DWORD 0x00000018
+#define SQ_S_BUFFER_STORE_DWORDX2 0x00000019
+#define SQ_S_BUFFER_STORE_DWORDX4 0x0000001a
+#define SQ_S_DCACHE_INV 0x00000020
+#define SQ_S_DCACHE_WB 0x00000021
+#define SQ_S_DCACHE_INV_VOL 0x00000022
+#define SQ_S_DCACHE_WB_VOL 0x00000023
+#define SQ_S_MEMTIME 0x00000024
+#define SQ_S_MEMREALTIME 0x00000025
+#define SQ_S_ATC_PROBE 0x00000026
+#define SQ_S_ATC_PROBE_BUFFER 0x00000027
+#define SQ_S_BUFFER_ATOMIC_SWAP 0x00000040
+#define SQ_S_BUFFER_ATOMIC_CMPSWAP 0x00000041
+#define SQ_S_BUFFER_ATOMIC_ADD 0x00000042
+#define SQ_S_BUFFER_ATOMIC_SUB 0x00000043
+#define SQ_S_BUFFER_ATOMIC_SMIN 0x00000044
+#define SQ_S_BUFFER_ATOMIC_UMIN 0x00000045
+#define SQ_S_BUFFER_ATOMIC_SMAX 0x00000046
+#define SQ_S_BUFFER_ATOMIC_UMAX 0x00000047
+#define SQ_S_BUFFER_ATOMIC_AND 0x00000048
+#define SQ_S_BUFFER_ATOMIC_OR 0x00000049
+#define SQ_S_BUFFER_ATOMIC_XOR 0x0000004a
+#define SQ_S_BUFFER_ATOMIC_INC 0x0000004b
+#define SQ_S_BUFFER_ATOMIC_DEC 0x0000004c
+#define SQ_S_BUFFER_ATOMIC_SWAP_X2 0x00000060
+#define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2 0x00000061
+#define SQ_S_BUFFER_ATOMIC_ADD_X2 0x00000062
+#define SQ_S_BUFFER_ATOMIC_SUB_X2 0x00000063
+#define SQ_S_BUFFER_ATOMIC_SMIN_X2 0x00000064
+#define SQ_S_BUFFER_ATOMIC_UMIN_X2 0x00000065
+#define SQ_S_BUFFER_ATOMIC_SMAX_X2 0x00000066
+#define SQ_S_BUFFER_ATOMIC_UMAX_X2 0x00000067
+#define SQ_S_BUFFER_ATOMIC_AND_X2 0x00000068
+#define SQ_S_BUFFER_ATOMIC_OR_X2 0x00000069
+#define SQ_S_BUFFER_ATOMIC_XOR_X2 0x0000006a
+#define SQ_S_BUFFER_ATOMIC_INC_X2 0x0000006b
+#define SQ_S_BUFFER_ATOMIC_DEC_X2 0x0000006c
+#define SQ_S_ATOMIC_SWAP 0x00000080
+#define SQ_S_ATOMIC_CMPSWAP 0x00000081
+#define SQ_S_ATOMIC_ADD 0x00000082
+#define SQ_S_ATOMIC_SUB 0x00000083
+#define SQ_S_ATOMIC_SMIN 0x00000084
+#define SQ_S_ATOMIC_UMIN 0x00000085
+#define SQ_S_ATOMIC_SMAX 0x00000086
+#define SQ_S_ATOMIC_UMAX 0x00000087
+#define SQ_S_ATOMIC_AND 0x00000088
+#define SQ_S_ATOMIC_OR 0x00000089
+#define SQ_S_ATOMIC_XOR 0x0000008a
+#define SQ_S_ATOMIC_INC 0x0000008b
+#define SQ_S_ATOMIC_DEC 0x0000008c
+#define SQ_S_ATOMIC_SWAP_X2 0x000000a0
+#define SQ_S_ATOMIC_CMPSWAP_X2 0x000000a1
+#define SQ_S_ATOMIC_ADD_X2 0x000000a2
+#define SQ_S_ATOMIC_SUB_X2 0x000000a3
+#define SQ_S_ATOMIC_SMIN_X2 0x000000a4
+#define SQ_S_ATOMIC_UMIN_X2 0x000000a5
+#define SQ_S_ATOMIC_SMAX_X2 0x000000a6
+#define SQ_S_ATOMIC_UMAX_X2 0x000000a7
+#define SQ_S_ATOMIC_AND_X2 0x000000a8
+#define SQ_S_ATOMIC_OR_X2 0x000000a9
+#define SQ_S_ATOMIC_XOR_X2 0x000000aa
+#define SQ_S_ATOMIC_INC_X2 0x000000ab
+#define SQ_S_ATOMIC_DEC_X2 0x000000ac
+
+/*
+ * VALUE_SQ_OP_VOP2 value
+ */
+
+#define SQ_V_CNDMASK_B32 0x00000000
+#define SQ_V_ADD_F32 0x00000001
+#define SQ_V_SUB_F32 0x00000002
+#define SQ_V_SUBREV_F32 0x00000003
+#define SQ_V_MUL_LEGACY_F32 0x00000004
+#define SQ_V_MUL_F32 0x00000005
+#define SQ_V_MUL_I32_I24 0x00000006
+#define SQ_V_MUL_HI_I32_I24 0x00000007
+#define SQ_V_MUL_U32_U24 0x00000008
+#define SQ_V_MUL_HI_U32_U24 0x00000009
+#define SQ_V_MIN_F32 0x0000000a
+#define SQ_V_MAX_F32 0x0000000b
+#define SQ_V_MIN_I32 0x0000000c
+#define SQ_V_MAX_I32 0x0000000d
+#define SQ_V_MIN_U32 0x0000000e
+#define SQ_V_MAX_U32 0x0000000f
+#define SQ_V_LSHRREV_B32 0x00000010
+#define SQ_V_ASHRREV_I32 0x00000011
+#define SQ_V_LSHLREV_B32 0x00000012
+#define SQ_V_AND_B32 0x00000013
+#define SQ_V_OR_B32 0x00000014
+#define SQ_V_XOR_B32 0x00000015
+#define SQ_V_MAC_F32 0x00000016
+#define SQ_V_MADMK_F32 0x00000017
+#define SQ_V_MADAK_F32 0x00000018
+#define SQ_V_ADD_CO_U32 0x00000019
+#define SQ_V_SUB_CO_U32 0x0000001a
+#define SQ_V_SUBREV_CO_U32 0x0000001b
+#define SQ_V_ADDC_CO_U32 0x0000001c
+#define SQ_V_SUBB_CO_U32 0x0000001d
+#define SQ_V_SUBBREV_CO_U32 0x0000001e
+#define SQ_V_ADD_F16 0x0000001f
+#define SQ_V_SUB_F16 0x00000020
+#define SQ_V_SUBREV_F16 0x00000021
+#define SQ_V_MUL_F16 0x00000022
+#define SQ_V_MAC_F16 0x00000023
+#define SQ_V_MADMK_F16 0x00000024
+#define SQ_V_MADAK_F16 0x00000025
+#define SQ_V_ADD_U16 0x00000026
+#define SQ_V_SUB_U16 0x00000027
+#define SQ_V_SUBREV_U16 0x00000028
+#define SQ_V_MUL_LO_U16 0x00000029
+#define SQ_V_LSHLREV_B16 0x0000002a
+#define SQ_V_LSHRREV_B16 0x0000002b
+#define SQ_V_ASHRREV_I16 0x0000002c
+#define SQ_V_MAX_F16 0x0000002d
+#define SQ_V_MIN_F16 0x0000002e
+#define SQ_V_MAX_U16 0x0000002f
+#define SQ_V_MAX_I16 0x00000030
+#define SQ_V_MIN_U16 0x00000031
+#define SQ_V_MIN_I16 0x00000032
+#define SQ_V_LDEXP_F16 0x00000033
+#define SQ_V_ADD_U32 0x00000034
+#define SQ_V_SUB_U32 0x00000035
+#define SQ_V_SUBREV_U32 0x00000036
+
+/*
+ * VALUE_SQ_SYSMSG_OP value
+ */
+
+#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x00000001
+#define SQ_SYSMSG_OP_REG_RD 0x00000002
+#define SQ_SYSMSG_OP_HOST_TRAP_ACK 0x00000003
+#define SQ_SYSMSG_OP_TTRACE_PC 0x00000004
+#define SQ_SYSMSG_OP_ILLEGAL_INST_INTERRUPT 0x00000005
+#define SQ_SYSMSG_OP_MEMVIOL_INTERRUPT 0x00000006
+
+/*
+ * VALUE_SQ_SSRC_SPECIAL_VCCZ value
+ */
+
+#define SQ_SRC_VCCZ 0x000000fb
+
+/*
+ * VALUE_SQ_CHAN value
+ */
+
+#define SQ_CHAN_X 0x00000000
+#define SQ_CHAN_Y 0x00000001
+#define SQ_CHAN_Z 0x00000002
+#define SQ_CHAN_W 0x00000003
+
+/*
+ * VALUE_SQ_OP_SOPK value
+ */
+
+#define SQ_S_MOVK_I32 0x00000000
+#define SQ_S_CMOVK_I32 0x00000001
+#define SQ_S_CMPK_EQ_I32 0x00000002
+#define SQ_S_CMPK_LG_I32 0x00000003
+#define SQ_S_CMPK_GT_I32 0x00000004
+#define SQ_S_CMPK_GE_I32 0x00000005
+#define SQ_S_CMPK_LT_I32 0x00000006
+#define SQ_S_CMPK_LE_I32 0x00000007
+#define SQ_S_CMPK_EQ_U32 0x00000008
+#define SQ_S_CMPK_LG_U32 0x00000009
+#define SQ_S_CMPK_GT_U32 0x0000000a
+#define SQ_S_CMPK_GE_U32 0x0000000b
+#define SQ_S_CMPK_LT_U32 0x0000000c
+#define SQ_S_CMPK_LE_U32 0x0000000d
+#define SQ_S_ADDK_I32 0x0000000e
+#define SQ_S_MULK_I32 0x0000000f
+#define SQ_S_CBRANCH_I_FORK 0x00000010
+#define SQ_S_GETREG_B32 0x00000011
+#define SQ_S_SETREG_B32 0x00000012
+#define SQ_S_GETREG_REGRD_B32 0x00000013
+#define SQ_S_SETREG_IMM32_B32 0x00000014
+#define SQ_S_CALL_B64 0x00000015
+
+/*
+ * VALUE_SQ_DPP_CTRL_L_1_15 value
+ */
+
+#define SQ_L1 0x00000001
+#define SQ_L2 0x00000002
+#define SQ_L3 0x00000003
+#define SQ_L4 0x00000004
+#define SQ_L5 0x00000005
+#define SQ_L6 0x00000006
+#define SQ_L7 0x00000007
+#define SQ_L8 0x00000008
+#define SQ_L9 0x00000009
+#define SQ_L10 0x0000000a
+#define SQ_L11 0x0000000b
+#define SQ_L12 0x0000000c
+#define SQ_L13 0x0000000d
+#define SQ_L14 0x0000000e
+#define SQ_L15 0x0000000f
+
+/*
+ * VALUE_SQ_SGPR value
+ */
+
+#define SQ_SGPR0 0x00000000
+
+/*
+ * VALUE_SQ_OP_VOP3P value
+ */
+
+#define SQ_V_PK_MAD_I16 0x00000000
+#define SQ_V_PK_MUL_LO_U16 0x00000001
+#define SQ_V_PK_ADD_I16 0x00000002
+#define SQ_V_PK_SUB_I16 0x00000003
+#define SQ_V_PK_LSHLREV_B16 0x00000004
+#define SQ_V_PK_LSHRREV_B16 0x00000005
+#define SQ_V_PK_ASHRREV_I16 0x00000006
+#define SQ_V_PK_MAX_I16 0x00000007
+#define SQ_V_PK_MIN_I16 0x00000008
+#define SQ_V_PK_MAD_U16 0x00000009
+#define SQ_V_PK_ADD_U16 0x0000000a
+#define SQ_V_PK_SUB_U16 0x0000000b
+#define SQ_V_PK_MAX_U16 0x0000000c
+#define SQ_V_PK_MIN_U16 0x0000000d
+#define SQ_V_PK_MAD_F16 0x0000000e
+#define SQ_V_PK_ADD_F16 0x0000000f
+#define SQ_V_PK_MUL_F16 0x00000010
+#define SQ_V_PK_MIN_F16 0x00000011
+#define SQ_V_PK_MAX_F16 0x00000012
+#define SQ_V_MAD_MIX_F32 0x00000020
+#define SQ_V_MAD_MIXLO_F16 0x00000021
+#define SQ_V_MAD_MIXHI_F16 0x00000022
+
+/*
+ * VALUE_SQ_OP_VINTRP value
+ */
+
+#define SQ_V_INTERP_P1_F32 0x00000000
+#define SQ_V_INTERP_P2_F32 0x00000001
+#define SQ_V_INTERP_MOV_F32 0x00000002
+
+/*
+ * VALUE_SQ_DPP_CTRL_R_1_15 value
+ */
+
+#define SQ_R1 0x00000001
+#define SQ_R2 0x00000002
+#define SQ_R3 0x00000003
+#define SQ_R4 0x00000004
+#define SQ_R5 0x00000005
+#define SQ_R6 0x00000006
+#define SQ_R7 0x00000007
+#define SQ_R8 0x00000008
+#define SQ_R9 0x00000009
+#define SQ_R10 0x0000000a
+#define SQ_R11 0x0000000b
+#define SQ_R12 0x0000000c
+#define SQ_R13 0x0000000d
+#define SQ_R14 0x0000000e
+#define SQ_R15 0x0000000f
+
+/*
+ * VALUE_SQ_OP_SOP2 value
+ */
+
+#define SQ_S_ADD_U32 0x00000000
+#define SQ_S_SUB_U32 0x00000001
+#define SQ_S_ADD_I32 0x00000002
+#define SQ_S_SUB_I32 0x00000003
+#define SQ_S_ADDC_U32 0x00000004
+#define SQ_S_SUBB_U32 0x00000005
+#define SQ_S_MIN_I32 0x00000006
+#define SQ_S_MIN_U32 0x00000007
+#define SQ_S_MAX_I32 0x00000008
+#define SQ_S_MAX_U32 0x00000009
+#define SQ_S_CSELECT_B32 0x0000000a
+#define SQ_S_CSELECT_B64 0x0000000b
+#define SQ_S_AND_B32 0x0000000c
+#define SQ_S_AND_B64 0x0000000d
+#define SQ_S_OR_B32 0x0000000e
+#define SQ_S_OR_B64 0x0000000f
+#define SQ_S_XOR_B32 0x00000010
+#define SQ_S_XOR_B64 0x00000011
+#define SQ_S_ANDN2_B32 0x00000012
+#define SQ_S_ANDN2_B64 0x00000013
+#define SQ_S_ORN2_B32 0x00000014
+#define SQ_S_ORN2_B64 0x00000015
+#define SQ_S_NAND_B32 0x00000016
+#define SQ_S_NAND_B64 0x00000017
+#define SQ_S_NOR_B32 0x00000018
+#define SQ_S_NOR_B64 0x00000019
+#define SQ_S_XNOR_B32 0x0000001a
+#define SQ_S_XNOR_B64 0x0000001b
+#define SQ_S_LSHL_B32 0x0000001c
+#define SQ_S_LSHL_B64 0x0000001d
+#define SQ_S_LSHR_B32 0x0000001e
+#define SQ_S_LSHR_B64 0x0000001f
+#define SQ_S_ASHR_I32 0x00000020
+#define SQ_S_ASHR_I64 0x00000021
+#define SQ_S_BFM_B32 0x00000022
+#define SQ_S_BFM_B64 0x00000023
+#define SQ_S_MUL_I32 0x00000024
+#define SQ_S_BFE_U32 0x00000025
+#define SQ_S_BFE_I32 0x00000026
+#define SQ_S_BFE_U64 0x00000027
+#define SQ_S_BFE_I64 0x00000028
+#define SQ_S_CBRANCH_G_FORK 0x00000029
+#define SQ_S_ABSDIFF_I32 0x0000002a
+#define SQ_S_RFE_RESTORE_B64 0x0000002b
+#define SQ_S_MUL_HI_U32 0x0000002c
+#define SQ_S_MUL_HI_I32 0x0000002d
+#define SQ_S_LSHL1_ADD_U32 0x0000002e
+#define SQ_S_LSHL2_ADD_U32 0x0000002f
+#define SQ_S_LSHL3_ADD_U32 0x00000030
+#define SQ_S_LSHL4_ADD_U32 0x00000031
+#define SQ_S_PACK_LL_B32_B16 0x00000032
+#define SQ_S_PACK_LH_B32_B16 0x00000033
+#define SQ_S_PACK_HH_B32_B16 0x00000034
+
+/*
+ * VALUE_SQ_SEG value
+ */
+
+#define SQ_FLAT 0x00000000
+#define SQ_SCRATCH 0x00000001
+#define SQ_GLOBAL 0x00000002
+
+/*
+ * VALUE_SQ_SDST_EXEC value
+ */
+
+#define SQ_EXEC_LO 0x0000007e
+#define SQ_EXEC_HI 0x0000007f
+
+/*
+ * VALUE_SQ_SSRC_SPECIAL_NOLIT value
+ */
+
+#define SQ_SRC_64_INT 0x000000c0
+#define SQ_SRC_M_1_INT 0x000000c1
+#define SQ_SRC_M_2_INT 0x000000c2
+#define SQ_SRC_M_3_INT 0x000000c3
+#define SQ_SRC_M_4_INT 0x000000c4
+#define SQ_SRC_M_5_INT 0x000000c5
+#define SQ_SRC_M_6_INT 0x000000c6
+#define SQ_SRC_M_7_INT 0x000000c7
+#define SQ_SRC_M_8_INT 0x000000c8
+#define SQ_SRC_M_9_INT 0x000000c9
+#define SQ_SRC_M_10_INT 0x000000ca
+#define SQ_SRC_M_11_INT 0x000000cb
+#define SQ_SRC_M_12_INT 0x000000cc
+#define SQ_SRC_M_13_INT 0x000000cd
+#define SQ_SRC_M_14_INT 0x000000ce
+#define SQ_SRC_M_15_INT 0x000000cf
+#define SQ_SRC_M_16_INT 0x000000d0
+#define SQ_SRC_0_5 0x000000f0
+#define SQ_SRC_M_0_5 0x000000f1
+#define SQ_SRC_1 0x000000f2
+#define SQ_SRC_M_1 0x000000f3
+#define SQ_SRC_2 0x000000f4
+#define SQ_SRC_M_2 0x000000f5
+#define SQ_SRC_4 0x000000f6
+#define SQ_SRC_M_4 0x000000f7
+#define SQ_SRC_INV_2PI 0x000000f8
+
+/*
+ * VALUE_SQ_VCC_LOHI value
+ */
+
+#define SQ_VCC_LO 0x0000006a
+#define SQ_VCC_HI 0x0000006b
+
+/*
+ * VALUE_SQ_TGT value
+ */
+
+#define SQ_EXP_MRT0 0x00000000
+#define SQ_EXP_MRTZ 0x00000008
+#define SQ_EXP_NULL 0x00000009
+#define SQ_EXP_POS0 0x0000000c
+#define SQ_EXP_PARAM0 0x00000020
+
+/*
+ * VALUE_SQ_OP_SOPP value
+ */
+
+#define SQ_S_NOP 0x00000000
+#define SQ_S_ENDPGM 0x00000001
+#define SQ_S_BRANCH 0x00000002
+#define SQ_S_WAKEUP 0x00000003
+#define SQ_S_CBRANCH_SCC0 0x00000004
+#define SQ_S_CBRANCH_SCC1 0x00000005
+#define SQ_S_CBRANCH_VCCZ 0x00000006
+#define SQ_S_CBRANCH_VCCNZ 0x00000007
+#define SQ_S_CBRANCH_EXECZ 0x00000008
+#define SQ_S_CBRANCH_EXECNZ 0x00000009
+#define SQ_S_BARRIER 0x0000000a
+#define SQ_S_SETKILL 0x0000000b
+#define SQ_S_WAITCNT 0x0000000c
+#define SQ_S_SETHALT 0x0000000d
+#define SQ_S_SLEEP 0x0000000e
+#define SQ_S_SETPRIO 0x0000000f
+#define SQ_S_SENDMSG 0x00000010
+#define SQ_S_SENDMSGHALT 0x00000011
+#define SQ_S_TRAP 0x00000012
+#define SQ_S_ICACHE_INV 0x00000013
+#define SQ_S_INCPERFLEVEL 0x00000014
+#define SQ_S_DECPERFLEVEL 0x00000015
+#define SQ_S_TTRACEDATA 0x00000016
+#define SQ_S_CBRANCH_CDBGSYS 0x00000017
+#define SQ_S_CBRANCH_CDBGUSER 0x00000018
+#define SQ_S_CBRANCH_CDBGSYS_OR_USER 0x00000019
+#define SQ_S_CBRANCH_CDBGSYS_AND_USER 0x0000001a
+#define SQ_S_ENDPGM_SAVED 0x0000001b
+#define SQ_S_SET_GPR_IDX_OFF 0x0000001c
+#define SQ_S_SET_GPR_IDX_MODE 0x0000001d
+#define SQ_S_ENDPGM_ORDERED_PS_DONE 0x0000001e
+
+/*
+ * VALUE_SQ_OP_EXP value
+ */
+
+#define SQ_EXP 0x00000000
+
+/*
+ * VALUE_SQ_SSRC_SPECIAL_POPS_EXITING_WAVE_ID value
+ */
+
+#define SQ_SRC_POPS_EXITING_WAVE_ID 0x000000ef
+
+/*
+ * VALUE_SQ_XNACK_MASK_LOHI value
+ */
+
+#define SQ_XNACK_MASK_LO 0x00000068
+#define SQ_XNACK_MASK_HI 0x00000069
+
+/*
+ * VALUE_SQ_OMOD value
+ */
+
+#define SQ_OMOD_OFF 0x00000000
+#define SQ_OMOD_M2 0x00000001
+#define SQ_OMOD_M4 0x00000002
+#define SQ_OMOD_D2 0x00000003
+
+/*
+ * VALUE_SQ_SSRC_SPECIAL_EXECZ value
+ */
+
+#define SQ_SRC_EXECZ 0x000000fc
+
+/*
+ * VALUE_SQ_COMPI value
+ */
+
+#define SQ_F 0x00000000
+#define SQ_LT 0x00000001
+#define SQ_EQ 0x00000002
+#define SQ_LE 0x00000003
+#define SQ_GT 0x00000004
+#define SQ_NE 0x00000005
+#define SQ_GE 0x00000006
+#define SQ_T 0x00000007
+
+/*
+ * VALUE_SQ_DPP_BOUND_CTRL value
+ */
+
+#define SQ_DPP_BOUND_OFF 0x00000000
+#define SQ_DPP_BOUND_ZERO 0x00000001
+
+/*
+ * VALUE_SQ_SDST_M0 value
+ */
+
+#define SQ_M0 0x0000007c
+
+/*
+ * VALUE_SQ_MSG value
+ */
+
+#define SQ_MSG_INTERRUPT 0x00000001
+#define SQ_MSG_GS 0x00000002
+#define SQ_MSG_GS_DONE 0x00000003
+#define SQ_MSG_SAVEWAVE 0x00000004
+#define SQ_MSG_STALL_WAVE_GEN 0x00000005
+#define SQ_MSG_HALT_WAVES 0x00000006
+#define SQ_MSG_ORDERED_PS_DONE 0x00000007
+#define SQ_MSG_EARLY_PRIM_DEALLOC 0x00000008
+#define SQ_MSG_GS_ALLOC_REQ 0x00000009
+#define SQ_MSG_SYSMSG 0x0000000f
+
+/*
+ * VALUE_SQ_PARAM value
+ */
+
+#define SQ_PARAM_P10 0x00000000
+#define SQ_PARAM_P20 0x00000001
+#define SQ_PARAM_P0 0x00000002
+
+/*
+ * VALUE_SQ_OPU_VOP3 value
+ */
+
+#define SQ_V_OPC_OFFSET 0x00000000
+#define SQ_V_OP2_OFFSET 0x00000100
+#define SQ_V_OP1_OFFSET 0x00000140
+#define SQ_V_INTRP_OFFSET 0x00000270
+#define SQ_V_OP3P_OFFSET 0x00000380
+
+/*
+ * VALUE_SQ_SSRC_SPECIAL_SDWA value
+ */
+
+#define SQ_SRC_SDWA 0x000000f9
+
+/*
+ * VALUE_SQ_SSRC_SPECIAL_APERTURE value
+ */
+
+#define SQ_SRC_SHARED_BASE 0x000000eb
+#define SQ_SRC_SHARED_LIMIT 0x000000ec
+#define SQ_SRC_PRIVATE_BASE 0x000000ed
+#define SQ_SRC_PRIVATE_LIMIT 0x000000ee
+
+/*
+ * VALUE_SQ_COMPF value
+ */
+
+#define SQ_F 0x00000000
+#define SQ_LT 0x00000001
+#define SQ_EQ 0x00000002
+#define SQ_LE 0x00000003
+#define SQ_GT 0x00000004
+#define SQ_LG 0x00000005
+#define SQ_GE 0x00000006
+#define SQ_O 0x00000007
+#define SQ_U 0x00000008
+#define SQ_NGE 0x00000009
+#define SQ_NLG 0x0000000a
+#define SQ_NGT 0x0000000b
+#define SQ_NLE 0x0000000c
+#define SQ_NEQ 0x0000000d
+#define SQ_NLT 0x0000000e
+#define SQ_TRU 0x0000000f
+
+/*
+ * VALUE_SQ_SDWA_UNUSED value
+ */
+
+#define SQ_SDWA_UNUSED_PAD 0x00000000
+#define SQ_SDWA_UNUSED_SEXT 0x00000001
+#define SQ_SDWA_UNUSED_PRESERVE 0x00000002
+
+/*
+ * VALUE_SQ_SSRC_SPECIAL_SCC value
+ */
+
+#define SQ_SRC_SCC 0x000000fd
+
+/*
+ * VALUE_SQ_OP_VOPC value
+ */
+
+#define SQ_V_CMP_CLASS_F32 0x00000010
+#define SQ_V_CMPX_CLASS_F32 0x00000011
+#define SQ_V_CMP_CLASS_F64 0x00000012
+#define SQ_V_CMPX_CLASS_F64 0x00000013
+#define SQ_V_CMP_CLASS_F16 0x00000014
+#define SQ_V_CMPX_CLASS_F16 0x00000015
+#define SQ_V_CMP_F_F16 0x00000020
+#define SQ_V_CMP_LT_F16 0x00000021
+#define SQ_V_CMP_EQ_F16 0x00000022
+#define SQ_V_CMP_LE_F16 0x00000023
+#define SQ_V_CMP_GT_F16 0x00000024
+#define SQ_V_CMP_LG_F16 0x00000025
+#define SQ_V_CMP_GE_F16 0x00000026
+#define SQ_V_CMP_O_F16 0x00000027
+#define SQ_V_CMP_U_F16 0x00000028
+#define SQ_V_CMP_NGE_F16 0x00000029
+#define SQ_V_CMP_NLG_F16 0x0000002a
+#define SQ_V_CMP_NGT_F16 0x0000002b
+#define SQ_V_CMP_NLE_F16 0x0000002c
+#define SQ_V_CMP_NEQ_F16 0x0000002d
+#define SQ_V_CMP_NLT_F16 0x0000002e
+#define SQ_V_CMP_TRU_F16 0x0000002f
+#define SQ_V_CMPX_F_F16 0x00000030
+#define SQ_V_CMPX_LT_F16 0x00000031
+#define SQ_V_CMPX_EQ_F16 0x00000032
+#define SQ_V_CMPX_LE_F16 0x00000033
+#define SQ_V_CMPX_GT_F16 0x00000034
+#define SQ_V_CMPX_LG_F16 0x00000035
+#define SQ_V_CMPX_GE_F16 0x00000036
+#define SQ_V_CMPX_O_F16 0x00000037
+#define SQ_V_CMPX_U_F16 0x00000038
+#define SQ_V_CMPX_NGE_F16 0x00000039
+#define SQ_V_CMPX_NLG_F16 0x0000003a
+#define SQ_V_CMPX_NGT_F16 0x0000003b
+#define SQ_V_CMPX_NLE_F16 0x0000003c
+#define SQ_V_CMPX_NEQ_F16 0x0000003d
+#define SQ_V_CMPX_NLT_F16 0x0000003e
+#define SQ_V_CMPX_TRU_F16 0x0000003f
+#define SQ_V_CMP_F_F32 0x00000040
+#define SQ_V_CMP_LT_F32 0x00000041
+#define SQ_V_CMP_EQ_F32 0x00000042
+#define SQ_V_CMP_LE_F32 0x00000043
+#define SQ_V_CMP_GT_F32 0x00000044
+#define SQ_V_CMP_LG_F32 0x00000045
+#define SQ_V_CMP_GE_F32 0x00000046
+#define SQ_V_CMP_O_F32 0x00000047
+#define SQ_V_CMP_U_F32 0x00000048
+#define SQ_V_CMP_NGE_F32 0x00000049
+#define SQ_V_CMP_NLG_F32 0x0000004a
+#define SQ_V_CMP_NGT_F32 0x0000004b
+#define SQ_V_CMP_NLE_F32 0x0000004c
+#define SQ_V_CMP_NEQ_F32 0x0000004d
+#define SQ_V_CMP_NLT_F32 0x0000004e
+#define SQ_V_CMP_TRU_F32 0x0000004f
+#define SQ_V_CMPX_F_F32 0x00000050
+#define SQ_V_CMPX_LT_F32 0x00000051
+#define SQ_V_CMPX_EQ_F32 0x00000052
+#define SQ_V_CMPX_LE_F32 0x00000053
+#define SQ_V_CMPX_GT_F32 0x00000054
+#define SQ_V_CMPX_LG_F32 0x00000055
+#define SQ_V_CMPX_GE_F32 0x00000056
+#define SQ_V_CMPX_O_F32 0x00000057
+#define SQ_V_CMPX_U_F32 0x00000058
+#define SQ_V_CMPX_NGE_F32 0x00000059
+#define SQ_V_CMPX_NLG_F32 0x0000005a
+#define SQ_V_CMPX_NGT_F32 0x0000005b
+#define SQ_V_CMPX_NLE_F32 0x0000005c
+#define SQ_V_CMPX_NEQ_F32 0x0000005d
+#define SQ_V_CMPX_NLT_F32 0x0000005e
+#define SQ_V_CMPX_TRU_F32 0x0000005f
+#define SQ_V_CMP_F_F64 0x00000060
+#define SQ_V_CMP_LT_F64 0x00000061
+#define SQ_V_CMP_EQ_F64 0x00000062
+#define SQ_V_CMP_LE_F64 0x00000063
+#define SQ_V_CMP_GT_F64 0x00000064
+#define SQ_V_CMP_LG_F64 0x00000065
+#define SQ_V_CMP_GE_F64 0x00000066
+#define SQ_V_CMP_O_F64 0x00000067
+#define SQ_V_CMP_U_F64 0x00000068
+#define SQ_V_CMP_NGE_F64 0x00000069
+#define SQ_V_CMP_NLG_F64 0x0000006a
+#define SQ_V_CMP_NGT_F64 0x0000006b
+#define SQ_V_CMP_NLE_F64 0x0000006c
+#define SQ_V_CMP_NEQ_F64 0x0000006d
+#define SQ_V_CMP_NLT_F64 0x0000006e
+#define SQ_V_CMP_TRU_F64 0x0000006f
+#define SQ_V_CMPX_F_F64 0x00000070
+#define SQ_V_CMPX_LT_F64 0x00000071
+#define SQ_V_CMPX_EQ_F64 0x00000072
+#define SQ_V_CMPX_LE_F64 0x00000073
+#define SQ_V_CMPX_GT_F64 0x00000074
+#define SQ_V_CMPX_LG_F64 0x00000075
+#define SQ_V_CMPX_GE_F64 0x00000076
+#define SQ_V_CMPX_O_F64 0x00000077
+#define SQ_V_CMPX_U_F64 0x00000078
+#define SQ_V_CMPX_NGE_F64 0x00000079
+#define SQ_V_CMPX_NLG_F64 0x0000007a
+#define SQ_V_CMPX_NGT_F64 0x0000007b
+#define SQ_V_CMPX_NLE_F64 0x0000007c
+#define SQ_V_CMPX_NEQ_F64 0x0000007d
+#define SQ_V_CMPX_NLT_F64 0x0000007e
+#define SQ_V_CMPX_TRU_F64 0x0000007f
+#define SQ_V_CMP_F_I16 0x000000a0
+#define SQ_V_CMP_LT_I16 0x000000a1
+#define SQ_V_CMP_EQ_I16 0x000000a2
+#define SQ_V_CMP_LE_I16 0x000000a3
+#define SQ_V_CMP_GT_I16 0x000000a4
+#define SQ_V_CMP_NE_I16 0x000000a5
+#define SQ_V_CMP_GE_I16 0x000000a6
+#define SQ_V_CMP_T_I16 0x000000a7
+#define SQ_V_CMP_F_U16 0x000000a8
+#define SQ_V_CMP_LT_U16 0x000000a9
+#define SQ_V_CMP_EQ_U16 0x000000aa
+#define SQ_V_CMP_LE_U16 0x000000ab
+#define SQ_V_CMP_GT_U16 0x000000ac
+#define SQ_V_CMP_NE_U16 0x000000ad
+#define SQ_V_CMP_GE_U16 0x000000ae
+#define SQ_V_CMP_T_U16 0x000000af
+#define SQ_V_CMPX_F_I16 0x000000b0
+#define SQ_V_CMPX_LT_I16 0x000000b1
+#define SQ_V_CMPX_EQ_I16 0x000000b2
+#define SQ_V_CMPX_LE_I16 0x000000b3
+#define SQ_V_CMPX_GT_I16 0x000000b4
+#define SQ_V_CMPX_NE_I16 0x000000b5
+#define SQ_V_CMPX_GE_I16 0x000000b6
+#define SQ_V_CMPX_T_I16 0x000000b7
+#define SQ_V_CMPX_F_U16 0x000000b8
+#define SQ_V_CMPX_LT_U16 0x000000b9
+#define SQ_V_CMPX_EQ_U16 0x000000ba
+#define SQ_V_CMPX_LE_U16 0x000000bb
+#define SQ_V_CMPX_GT_U16 0x000000bc
+#define SQ_V_CMPX_NE_U16 0x000000bd
+#define SQ_V_CMPX_GE_U16 0x000000be
+#define SQ_V_CMPX_T_U16 0x000000bf
+#define SQ_V_CMP_F_I32 0x000000c0
+#define SQ_V_CMP_LT_I32 0x000000c1
+#define SQ_V_CMP_EQ_I32 0x000000c2
+#define SQ_V_CMP_LE_I32 0x000000c3
+#define SQ_V_CMP_GT_I32 0x000000c4
+#define SQ_V_CMP_NE_I32 0x000000c5
+#define SQ_V_CMP_GE_I32 0x000000c6
+#define SQ_V_CMP_T_I32 0x000000c7
+#define SQ_V_CMP_F_U32 0x000000c8
+#define SQ_V_CMP_LT_U32 0x000000c9
+#define SQ_V_CMP_EQ_U32 0x000000ca
+#define SQ_V_CMP_LE_U32 0x000000cb
+#define SQ_V_CMP_GT_U32 0x000000cc
+#define SQ_V_CMP_NE_U32 0x000000cd
+#define SQ_V_CMP_GE_U32 0x000000ce
+#define SQ_V_CMP_T_U32 0x000000cf
+#define SQ_V_CMPX_F_I32 0x000000d0
+#define SQ_V_CMPX_LT_I32 0x000000d1
+#define SQ_V_CMPX_EQ_I32 0x000000d2
+#define SQ_V_CMPX_LE_I32 0x000000d3
+#define SQ_V_CMPX_GT_I32 0x000000d4
+#define SQ_V_CMPX_NE_I32 0x000000d5
+#define SQ_V_CMPX_GE_I32 0x000000d6
+#define SQ_V_CMPX_T_I32 0x000000d7
+#define SQ_V_CMPX_F_U32 0x000000d8
+#define SQ_V_CMPX_LT_U32 0x000000d9
+#define SQ_V_CMPX_EQ_U32 0x000000da
+#define SQ_V_CMPX_LE_U32 0x000000db
+#define SQ_V_CMPX_GT_U32 0x000000dc
+#define SQ_V_CMPX_NE_U32 0x000000dd
+#define SQ_V_CMPX_GE_U32 0x000000de
+#define SQ_V_CMPX_T_U32 0x000000df
+#define SQ_V_CMP_F_I64 0x000000e0
+#define SQ_V_CMP_LT_I64 0x000000e1
+#define SQ_V_CMP_EQ_I64 0x000000e2
+#define SQ_V_CMP_LE_I64 0x000000e3
+#define SQ_V_CMP_GT_I64 0x000000e4
+#define SQ_V_CMP_NE_I64 0x000000e5
+#define SQ_V_CMP_GE_I64 0x000000e6
+#define SQ_V_CMP_T_I64 0x000000e7
+#define SQ_V_CMP_F_U64 0x000000e8
+#define SQ_V_CMP_LT_U64 0x000000e9
+#define SQ_V_CMP_EQ_U64 0x000000ea
+#define SQ_V_CMP_LE_U64 0x000000eb
+#define SQ_V_CMP_GT_U64 0x000000ec
+#define SQ_V_CMP_NE_U64 0x000000ed
+#define SQ_V_CMP_GE_U64 0x000000ee
+#define SQ_V_CMP_T_U64 0x000000ef
+#define SQ_V_CMPX_F_I64 0x000000f0
+#define SQ_V_CMPX_LT_I64 0x000000f1
+#define SQ_V_CMPX_EQ_I64 0x000000f2
+#define SQ_V_CMPX_LE_I64 0x000000f3
+#define SQ_V_CMPX_GT_I64 0x000000f4
+#define SQ_V_CMPX_NE_I64 0x000000f5
+#define SQ_V_CMPX_GE_I64 0x000000f6
+#define SQ_V_CMPX_T_I64 0x000000f7
+#define SQ_V_CMPX_F_U64 0x000000f8
+#define SQ_V_CMPX_LT_U64 0x000000f9
+#define SQ_V_CMPX_EQ_U64 0x000000fa
+#define SQ_V_CMPX_LE_U64 0x000000fb
+#define SQ_V_CMPX_GT_U64 0x000000fc
+#define SQ_V_CMPX_NE_U64 0x000000fd
+#define SQ_V_CMPX_GE_U64 0x000000fe
+#define SQ_V_CMPX_T_U64 0x000000ff
+
+/*
+ * VALUE_SQ_GS_OP value
+ */
+
+#define SQ_GS_OP_NOP 0x00000000
+#define SQ_GS_OP_CUT 0x00000001
+#define SQ_GS_OP_EMIT 0x00000002
+#define SQ_GS_OP_EMIT_CUT 0x00000003
+
+/*
+ * VALUE_SQ_SSRC_SPECIAL_LDS value
+ */
+
+#define SQ_SRC_LDS_DIRECT 0x000000fe
+
+/*
+ * VALUE_SQ_ATTR value
+ */
+
+#define SQ_ATTR0 0x00000000
+
+/*
+ * VALUE_SQ_TGT_INTERNAL value
+ */
+
+#define SQ_EXP_GDS0 0x00000018
+
+/*
+ * VALUE_SQ_OP_SOPC value
+ */
+
+#define SQ_S_CMP_EQ_I32 0x00000000
+#define SQ_S_CMP_LG_I32 0x00000001
+#define SQ_S_CMP_GT_I32 0x00000002
+#define SQ_S_CMP_GE_I32 0x00000003
+#define SQ_S_CMP_LT_I32 0x00000004
+#define SQ_S_CMP_LE_I32 0x00000005
+#define SQ_S_CMP_EQ_U32 0x00000006
+#define SQ_S_CMP_LG_U32 0x00000007
+#define SQ_S_CMP_GT_U32 0x00000008
+#define SQ_S_CMP_GE_U32 0x00000009
+#define SQ_S_CMP_LT_U32 0x0000000a
+#define SQ_S_CMP_LE_U32 0x0000000b
+#define SQ_S_BITCMP0_B32 0x0000000c
+#define SQ_S_BITCMP1_B32 0x0000000d
+#define SQ_S_BITCMP0_B64 0x0000000e
+#define SQ_S_BITCMP1_B64 0x0000000f
+#define SQ_S_SETVSKIP 0x00000010
+#define SQ_S_SET_GPR_IDX_ON 0x00000011
+#define SQ_S_CMP_EQ_U64 0x00000012
+#define SQ_S_CMP_LG_U64 0x00000013
+
+/*
+ * VALUE_SQ_TRAP value
+ */
+
+#define SQ_TTMP0 0x0000006c
+#define SQ_TTMP1 0x0000006d
+#define SQ_TTMP2 0x0000006e
+#define SQ_TTMP3 0x0000006f
+#define SQ_TTMP4 0x00000070
+#define SQ_TTMP5 0x00000071
+#define SQ_TTMP6 0x00000072
+#define SQ_TTMP7 0x00000073
+#define SQ_TTMP8 0x00000074
+#define SQ_TTMP9 0x00000075
+#define SQ_TTMP10 0x00000076
+#define SQ_TTMP11 0x00000077
+#define SQ_TTMP12 0x00000078
+#define SQ_TTMP13 0x00000079
+#define SQ_TTMP14 0x0000007a
+#define SQ_TTMP15 0x0000007b
+
+/*
+ * VALUE_SQ_SRC_VGPR value
+ */
+
+#define SQ_SRC_VGPR0 0x00000100
+
+/*
+ * VALUE_SQ_OP_MUBUF value
+ */
+
+#define SQ_BUFFER_LOAD_FORMAT_X 0x00000000
+#define SQ_BUFFER_LOAD_FORMAT_XY 0x00000001
+#define SQ_BUFFER_LOAD_FORMAT_XYZ 0x00000002
+#define SQ_BUFFER_LOAD_FORMAT_XYZW 0x00000003
+#define SQ_BUFFER_STORE_FORMAT_X 0x00000004
+#define SQ_BUFFER_STORE_FORMAT_XY 0x00000005
+#define SQ_BUFFER_STORE_FORMAT_XYZ 0x00000006
+#define SQ_BUFFER_STORE_FORMAT_XYZW 0x00000007
+#define SQ_BUFFER_LOAD_FORMAT_D16_X 0x00000008
+#define SQ_BUFFER_LOAD_FORMAT_D16_XY 0x00000009
+#define SQ_BUFFER_LOAD_FORMAT_D16_XYZ 0x0000000a
+#define SQ_BUFFER_LOAD_FORMAT_D16_XYZW 0x0000000b
+#define SQ_BUFFER_STORE_FORMAT_D16_X 0x0000000c
+#define SQ_BUFFER_STORE_FORMAT_D16_XY 0x0000000d
+#define SQ_BUFFER_STORE_FORMAT_D16_XYZ 0x0000000e
+#define SQ_BUFFER_STORE_FORMAT_D16_XYZW 0x0000000f
+#define SQ_BUFFER_LOAD_UBYTE 0x00000010
+#define SQ_BUFFER_LOAD_SBYTE 0x00000011
+#define SQ_BUFFER_LOAD_USHORT 0x00000012
+#define SQ_BUFFER_LOAD_SSHORT 0x00000013
+#define SQ_BUFFER_LOAD_DWORD 0x00000014
+#define SQ_BUFFER_LOAD_DWORDX2 0x00000015
+#define SQ_BUFFER_LOAD_DWORDX3 0x00000016
+#define SQ_BUFFER_LOAD_DWORDX4 0x00000017
+#define SQ_BUFFER_STORE_BYTE 0x00000018
+#define SQ_BUFFER_STORE_SHORT 0x0000001a
+#define SQ_BUFFER_STORE_DWORD 0x0000001c
+#define SQ_BUFFER_STORE_DWORDX2 0x0000001d
+#define SQ_BUFFER_STORE_DWORDX3 0x0000001e
+#define SQ_BUFFER_STORE_DWORDX4 0x0000001f
+#define SQ_BUFFER_STORE_LDS_DWORD 0x0000003d
+#define SQ_BUFFER_WBINVL1 0x0000003e
+#define SQ_BUFFER_WBINVL1_VOL 0x0000003f
+#define SQ_BUFFER_ATOMIC_SWAP 0x00000040
+#define SQ_BUFFER_ATOMIC_CMPSWAP 0x00000041
+#define SQ_BUFFER_ATOMIC_ADD 0x00000042
+#define SQ_BUFFER_ATOMIC_SUB 0x00000043
+#define SQ_BUFFER_ATOMIC_SMIN 0x00000044
+#define SQ_BUFFER_ATOMIC_UMIN 0x00000045
+#define SQ_BUFFER_ATOMIC_SMAX 0x00000046
+#define SQ_BUFFER_ATOMIC_UMAX 0x00000047
+#define SQ_BUFFER_ATOMIC_AND 0x00000048
+#define SQ_BUFFER_ATOMIC_OR 0x00000049
+#define SQ_BUFFER_ATOMIC_XOR 0x0000004a
+#define SQ_BUFFER_ATOMIC_INC 0x0000004b
+#define SQ_BUFFER_ATOMIC_DEC 0x0000004c
+#define SQ_BUFFER_ATOMIC_SWAP_X2 0x00000060
+#define SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x00000061
+#define SQ_BUFFER_ATOMIC_ADD_X2 0x00000062
+#define SQ_BUFFER_ATOMIC_SUB_X2 0x00000063
+#define SQ_BUFFER_ATOMIC_SMIN_X2 0x00000064
+#define SQ_BUFFER_ATOMIC_UMIN_X2 0x00000065
+#define SQ_BUFFER_ATOMIC_SMAX_X2 0x00000066
+#define SQ_BUFFER_ATOMIC_UMAX_X2 0x00000067
+#define SQ_BUFFER_ATOMIC_AND_X2 0x00000068
+#define SQ_BUFFER_ATOMIC_OR_X2 0x00000069
+#define SQ_BUFFER_ATOMIC_XOR_X2 0x0000006a
+#define SQ_BUFFER_ATOMIC_INC_X2 0x0000006b
+#define SQ_BUFFER_ATOMIC_DEC_X2 0x0000006c
+
+/*
+ * VALUE_SQ_SDWA_SEL value
+ */
+
+#define SQ_SDWA_BYTE_0 0x00000000
+#define SQ_SDWA_BYTE_1 0x00000001
+#define SQ_SDWA_BYTE_2 0x00000002
+#define SQ_SDWA_BYTE_3 0x00000003
+#define SQ_SDWA_WORD_0 0x00000004
+#define SQ_SDWA_WORD_1 0x00000005
+#define SQ_SDWA_DWORD 0x00000006
+
+/*******************************************************
+ * SX Enums
+ *******************************************************/
+
+/*
+ * SX_BLEND_OPT enum
+ */
+
+typedef enum SX_BLEND_OPT {
+BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0x00000000,
+BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 0x00000001,
+BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 0x00000002,
+BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 0x00000003,
+BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 0x00000004,
+BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 0x00000005,
+BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 0x00000006,
+BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 0x00000007,
+} SX_BLEND_OPT;
+
+/*
+ * SX_OPT_COMB_FCN enum
+ */
+
+typedef enum SX_OPT_COMB_FCN {
+OPT_COMB_NONE = 0x00000000,
+OPT_COMB_ADD = 0x00000001,
+OPT_COMB_SUBTRACT = 0x00000002,
+OPT_COMB_MIN = 0x00000003,
+OPT_COMB_MAX = 0x00000004,
+OPT_COMB_REVSUBTRACT = 0x00000005,
+OPT_COMB_BLEND_DISABLED = 0x00000006,
+OPT_COMB_SAFE_ADD = 0x00000007,
+} SX_OPT_COMB_FCN;
+
+/*
+ * SX_DOWNCONVERT_FORMAT enum
+ */
+
+typedef enum SX_DOWNCONVERT_FORMAT {
+SX_RT_EXPORT_NO_CONVERSION = 0x00000000,
+SX_RT_EXPORT_32_R = 0x00000001,
+SX_RT_EXPORT_32_A = 0x00000002,
+SX_RT_EXPORT_10_11_11 = 0x00000003,
+SX_RT_EXPORT_2_10_10_10 = 0x00000004,
+SX_RT_EXPORT_8_8_8_8 = 0x00000005,
+SX_RT_EXPORT_5_6_5 = 0x00000006,
+SX_RT_EXPORT_1_5_5_5 = 0x00000007,
+SX_RT_EXPORT_4_4_4_4 = 0x00000008,
+SX_RT_EXPORT_16_16_GR = 0x00000009,
+SX_RT_EXPORT_16_16_AR = 0x0000000a,
+} SX_DOWNCONVERT_FORMAT;
+
+/*
+ * SX_PERFCOUNTER_VALS enum
+ */
+
+typedef enum SX_PERFCOUNTER_VALS {
+SX_PERF_SEL_PA_IDLE_CYCLES = 0x00000000,
+SX_PERF_SEL_PA_REQ = 0x00000001,
+SX_PERF_SEL_PA_POS = 0x00000002,
+SX_PERF_SEL_CLOCK = 0x00000003,
+SX_PERF_SEL_GATE_EN1 = 0x00000004,
+SX_PERF_SEL_GATE_EN2 = 0x00000005,
+SX_PERF_SEL_GATE_EN3 = 0x00000006,
+SX_PERF_SEL_GATE_EN4 = 0x00000007,
+SX_PERF_SEL_SH_POS_STARVE = 0x00000008,
+SX_PERF_SEL_SH_COLOR_STARVE = 0x00000009,
+SX_PERF_SEL_SH_POS_STALL = 0x0000000a,
+SX_PERF_SEL_SH_COLOR_STALL = 0x0000000b,
+SX_PERF_SEL_DB0_PIXELS = 0x0000000c,
+SX_PERF_SEL_DB0_HALF_QUADS = 0x0000000d,
+SX_PERF_SEL_DB0_PIXEL_STALL = 0x0000000e,
+SX_PERF_SEL_DB0_PIXEL_IDLE = 0x0000000f,
+SX_PERF_SEL_DB0_PRED_PIXELS = 0x00000010,
+SX_PERF_SEL_DB1_PIXELS = 0x00000011,
+SX_PERF_SEL_DB1_HALF_QUADS = 0x00000012,
+SX_PERF_SEL_DB1_PIXEL_STALL = 0x00000013,
+SX_PERF_SEL_DB1_PIXEL_IDLE = 0x00000014,
+SX_PERF_SEL_DB1_PRED_PIXELS = 0x00000015,
+SX_PERF_SEL_DB2_PIXELS = 0x00000016,
+SX_PERF_SEL_DB2_HALF_QUADS = 0x00000017,
+SX_PERF_SEL_DB2_PIXEL_STALL = 0x00000018,
+SX_PERF_SEL_DB2_PIXEL_IDLE = 0x00000019,
+SX_PERF_SEL_DB2_PRED_PIXELS = 0x0000001a,
+SX_PERF_SEL_DB3_PIXELS = 0x0000001b,
+SX_PERF_SEL_DB3_HALF_QUADS = 0x0000001c,
+SX_PERF_SEL_DB3_PIXEL_STALL = 0x0000001d,
+SX_PERF_SEL_DB3_PIXEL_IDLE = 0x0000001e,
+SX_PERF_SEL_DB3_PRED_PIXELS = 0x0000001f,
+SX_PERF_SEL_COL_BUSY = 0x00000020,
+SX_PERF_SEL_POS_BUSY = 0x00000021,
+SX_PERF_SEL_DB0_A2M_DISCARD_QUADS = 0x00000022,
+SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS = 0x00000023,
+SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST = 0x00000024,
+SX_PERF_SEL_DB0_MRT0_DISCARD_SRC = 0x00000025,
+SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS = 0x00000026,
+SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS = 0x00000027,
+SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS = 0x00000028,
+SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST = 0x00000029,
+SX_PERF_SEL_DB0_MRT1_DISCARD_SRC = 0x0000002a,
+SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS = 0x0000002b,
+SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS = 0x0000002c,
+SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS = 0x0000002d,
+SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST = 0x0000002e,
+SX_PERF_SEL_DB0_MRT2_DISCARD_SRC = 0x0000002f,
+SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS = 0x00000030,
+SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS = 0x00000031,
+SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS = 0x00000032,
+SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST = 0x00000033,
+SX_PERF_SEL_DB0_MRT3_DISCARD_SRC = 0x00000034,
+SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS = 0x00000035,
+SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS = 0x00000036,
+SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS = 0x00000037,
+SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST = 0x00000038,
+SX_PERF_SEL_DB0_MRT4_DISCARD_SRC = 0x00000039,
+SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS = 0x0000003a,
+SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS = 0x0000003b,
+SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS = 0x0000003c,
+SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST = 0x0000003d,
+SX_PERF_SEL_DB0_MRT5_DISCARD_SRC = 0x0000003e,
+SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS = 0x0000003f,
+SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS = 0x00000040,
+SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS = 0x00000041,
+SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST = 0x00000042,
+SX_PERF_SEL_DB0_MRT6_DISCARD_SRC = 0x00000043,
+SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS = 0x00000044,
+SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS = 0x00000045,
+SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS = 0x00000046,
+SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST = 0x00000047,
+SX_PERF_SEL_DB0_MRT7_DISCARD_SRC = 0x00000048,
+SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS = 0x00000049,
+SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS = 0x0000004a,
+SX_PERF_SEL_DB1_A2M_DISCARD_QUADS = 0x0000004b,
+SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS = 0x0000004c,
+SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST = 0x0000004d,
+SX_PERF_SEL_DB1_MRT0_DISCARD_SRC = 0x0000004e,
+SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS = 0x0000004f,
+SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS = 0x00000050,
+SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS = 0x00000051,
+SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST = 0x00000052,
+SX_PERF_SEL_DB1_MRT1_DISCARD_SRC = 0x00000053,
+SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS = 0x00000054,
+SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS = 0x00000055,
+SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS = 0x00000056,
+SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST = 0x00000057,
+SX_PERF_SEL_DB1_MRT2_DISCARD_SRC = 0x00000058,
+SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS = 0x00000059,
+SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS = 0x0000005a,
+SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS = 0x0000005b,
+SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST = 0x0000005c,
+SX_PERF_SEL_DB1_MRT3_DISCARD_SRC = 0x0000005d,
+SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS = 0x0000005e,
+SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS = 0x0000005f,
+SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS = 0x00000060,
+SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST = 0x00000061,
+SX_PERF_SEL_DB1_MRT4_DISCARD_SRC = 0x00000062,
+SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS = 0x00000063,
+SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS = 0x00000064,
+SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS = 0x00000065,
+SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST = 0x00000066,
+SX_PERF_SEL_DB1_MRT5_DISCARD_SRC = 0x00000067,
+SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS = 0x00000068,
+SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS = 0x00000069,
+SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS = 0x0000006a,
+SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST = 0x0000006b,
+SX_PERF_SEL_DB1_MRT6_DISCARD_SRC = 0x0000006c,
+SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS = 0x0000006d,
+SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS = 0x0000006e,
+SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS = 0x0000006f,
+SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST = 0x00000070,
+SX_PERF_SEL_DB1_MRT7_DISCARD_SRC = 0x00000071,
+SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS = 0x00000072,
+SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS = 0x00000073,
+SX_PERF_SEL_DB2_A2M_DISCARD_QUADS = 0x00000074,
+SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS = 0x00000075,
+SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST = 0x00000076,
+SX_PERF_SEL_DB2_MRT0_DISCARD_SRC = 0x00000077,
+SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS = 0x00000078,
+SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS = 0x00000079,
+SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS = 0x0000007a,
+SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST = 0x0000007b,
+SX_PERF_SEL_DB2_MRT1_DISCARD_SRC = 0x0000007c,
+SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS = 0x0000007d,
+SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS = 0x0000007e,
+SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS = 0x0000007f,
+SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST = 0x00000080,
+SX_PERF_SEL_DB2_MRT2_DISCARD_SRC = 0x00000081,
+SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS = 0x00000082,
+SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS = 0x00000083,
+SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS = 0x00000084,
+SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST = 0x00000085,
+SX_PERF_SEL_DB2_MRT3_DISCARD_SRC = 0x00000086,
+SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS = 0x00000087,
+SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS = 0x00000088,
+SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS = 0x00000089,
+SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST = 0x0000008a,
+SX_PERF_SEL_DB2_MRT4_DISCARD_SRC = 0x0000008b,
+SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS = 0x0000008c,
+SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS = 0x0000008d,
+SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS = 0x0000008e,
+SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST = 0x0000008f,
+SX_PERF_SEL_DB2_MRT5_DISCARD_SRC = 0x00000090,
+SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS = 0x00000091,
+SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS = 0x00000092,
+SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS = 0x00000093,
+SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST = 0x00000094,
+SX_PERF_SEL_DB2_MRT6_DISCARD_SRC = 0x00000095,
+SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS = 0x00000096,
+SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS = 0x00000097,
+SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS = 0x00000098,
+SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST = 0x00000099,
+SX_PERF_SEL_DB2_MRT7_DISCARD_SRC = 0x0000009a,
+SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS = 0x0000009b,
+SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS = 0x0000009c,
+SX_PERF_SEL_DB3_A2M_DISCARD_QUADS = 0x0000009d,
+SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS = 0x0000009e,
+SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST = 0x0000009f,
+SX_PERF_SEL_DB3_MRT0_DISCARD_SRC = 0x000000a0,
+SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS = 0x000000a1,
+SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS = 0x000000a2,
+SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS = 0x000000a3,
+SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST = 0x000000a4,
+SX_PERF_SEL_DB3_MRT1_DISCARD_SRC = 0x000000a5,
+SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS = 0x000000a6,
+SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS = 0x000000a7,
+SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS = 0x000000a8,
+SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST = 0x000000a9,
+SX_PERF_SEL_DB3_MRT2_DISCARD_SRC = 0x000000aa,
+SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS = 0x000000ab,
+SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS = 0x000000ac,
+SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS = 0x000000ad,
+SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST = 0x000000ae,
+SX_PERF_SEL_DB3_MRT3_DISCARD_SRC = 0x000000af,
+SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS = 0x000000b0,
+SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS = 0x000000b1,
+SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS = 0x000000b2,
+SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST = 0x000000b3,
+SX_PERF_SEL_DB3_MRT4_DISCARD_SRC = 0x000000b4,
+SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS = 0x000000b5,
+SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS = 0x000000b6,
+SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS = 0x000000b7,
+SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST = 0x000000b8,
+SX_PERF_SEL_DB3_MRT5_DISCARD_SRC = 0x000000b9,
+SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS = 0x000000ba,
+SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS = 0x000000bb,
+SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS = 0x000000bc,
+SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST = 0x000000bd,
+SX_PERF_SEL_DB3_MRT6_DISCARD_SRC = 0x000000be,
+SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS = 0x000000bf,
+SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS = 0x000000c0,
+SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS = 0x000000c1,
+SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST = 0x000000c2,
+SX_PERF_SEL_DB3_MRT7_DISCARD_SRC = 0x000000c3,
+SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS = 0x000000c4,
+SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS = 0x000000c5,
+} SX_PERFCOUNTER_VALS;
+
+/*******************************************************
+ * DB Enums
+ *******************************************************/
+
+/*
+ * ForceControl enum
+ */
+
+typedef enum ForceControl {
+FORCE_OFF = 0x00000000,
+FORCE_ENABLE = 0x00000001,
+FORCE_DISABLE = 0x00000002,
+FORCE_RESERVED = 0x00000003,
+} ForceControl;
+
+/*
+ * ZSamplePosition enum
+ */
+
+typedef enum ZSamplePosition {
+Z_SAMPLE_CENTER = 0x00000000,
+Z_SAMPLE_CENTROID = 0x00000001,
+} ZSamplePosition;
+
+/*
+ * ZOrder enum
+ */
+
+typedef enum ZOrder {
+LATE_Z = 0x00000000,
+EARLY_Z_THEN_LATE_Z = 0x00000001,
+RE_Z = 0x00000002,
+EARLY_Z_THEN_RE_Z = 0x00000003,
+} ZOrder;
+
+/*
+ * ZpassControl enum
+ */
+
+typedef enum ZpassControl {
+ZPASS_DISABLE = 0x00000000,
+ZPASS_SAMPLES = 0x00000001,
+ZPASS_PIXELS = 0x00000002,
+} ZpassControl;
+
+/*
+ * ZModeForce enum
+ */
+
+typedef enum ZModeForce {
+NO_FORCE = 0x00000000,
+FORCE_EARLY_Z = 0x00000001,
+FORCE_LATE_Z = 0x00000002,
+FORCE_RE_Z = 0x00000003,
+} ZModeForce;
+
+/*
+ * ZLimitSumm enum
+ */
+
+typedef enum ZLimitSumm {
+FORCE_SUMM_OFF = 0x00000000,
+FORCE_SUMM_MINZ = 0x00000001,
+FORCE_SUMM_MAXZ = 0x00000002,
+FORCE_SUMM_BOTH = 0x00000003,
+} ZLimitSumm;
+
+/*
+ * CompareFrag enum
+ */
+
+typedef enum CompareFrag {
+FRAG_NEVER = 0x00000000,
+FRAG_LESS = 0x00000001,
+FRAG_EQUAL = 0x00000002,
+FRAG_LEQUAL = 0x00000003,
+FRAG_GREATER = 0x00000004,
+FRAG_NOTEQUAL = 0x00000005,
+FRAG_GEQUAL = 0x00000006,
+FRAG_ALWAYS = 0x00000007,
+} CompareFrag;
+
+/*
+ * StencilOp enum
+ */
+
+typedef enum StencilOp {
+STENCIL_KEEP = 0x00000000,
+STENCIL_ZERO = 0x00000001,
+STENCIL_ONES = 0x00000002,
+STENCIL_REPLACE_TEST = 0x00000003,
+STENCIL_REPLACE_OP = 0x00000004,
+STENCIL_ADD_CLAMP = 0x00000005,
+STENCIL_SUB_CLAMP = 0x00000006,
+STENCIL_INVERT = 0x00000007,
+STENCIL_ADD_WRAP = 0x00000008,
+STENCIL_SUB_WRAP = 0x00000009,
+STENCIL_AND = 0x0000000a,
+STENCIL_OR = 0x0000000b,
+STENCIL_XOR = 0x0000000c,
+STENCIL_NAND = 0x0000000d,
+STENCIL_NOR = 0x0000000e,
+STENCIL_XNOR = 0x0000000f,
+} StencilOp;
+
+/*
+ * ConservativeZExport enum
+ */
+
+typedef enum ConservativeZExport {
+EXPORT_ANY_Z = 0x00000000,
+EXPORT_LESS_THAN_Z = 0x00000001,
+EXPORT_GREATER_THAN_Z = 0x00000002,
+EXPORT_RESERVED = 0x00000003,
+} ConservativeZExport;
+
+/*
+ * DbPSLControl enum
+ */
+
+typedef enum DbPSLControl {
+PSLC_AUTO = 0x00000000,
+PSLC_ON_HANG_ONLY = 0x00000001,
+PSLC_ASAP = 0x00000002,
+PSLC_COUNTDOWN = 0x00000003,
+} DbPSLControl;
+
+/*
+ * DbPRTFaultBehavior enum
+ */
+
+typedef enum DbPRTFaultBehavior {
+FAULT_ZERO = 0x00000000,
+FAULT_ONE = 0x00000001,
+FAULT_FAIL = 0x00000002,
+FAULT_PASS = 0x00000003,
+} DbPRTFaultBehavior;
+
+/*
+ * PerfCounter_Vals enum
+ */
+
+typedef enum PerfCounter_Vals {
+DB_PERF_SEL_SC_DB_tile_sends = 0x00000000,
+DB_PERF_SEL_SC_DB_tile_busy = 0x00000001,
+DB_PERF_SEL_SC_DB_tile_stalls = 0x00000002,
+DB_PERF_SEL_SC_DB_tile_events = 0x00000003,
+DB_PERF_SEL_SC_DB_tile_tiles = 0x00000004,
+DB_PERF_SEL_SC_DB_tile_covered = 0x00000005,
+DB_PERF_SEL_hiz_tc_read_starved = 0x00000006,
+DB_PERF_SEL_hiz_tc_write_stall = 0x00000007,
+DB_PERF_SEL_hiz_qtiles_culled = 0x00000008,
+DB_PERF_SEL_his_qtiles_culled = 0x00000009,
+DB_PERF_SEL_DB_SC_tile_sends = 0x0000000a,
+DB_PERF_SEL_DB_SC_tile_busy = 0x0000000b,
+DB_PERF_SEL_DB_SC_tile_stalls = 0x0000000c,
+DB_PERF_SEL_DB_SC_tile_df_stalls = 0x0000000d,
+DB_PERF_SEL_DB_SC_tile_tiles = 0x0000000e,
+DB_PERF_SEL_DB_SC_tile_culled = 0x0000000f,
+DB_PERF_SEL_DB_SC_tile_hier_kill = 0x00000010,
+DB_PERF_SEL_DB_SC_tile_fast_ops = 0x00000011,
+DB_PERF_SEL_DB_SC_tile_no_ops = 0x00000012,
+DB_PERF_SEL_DB_SC_tile_tile_rate = 0x00000013,
+DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x00000014,
+DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x00000015,
+DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x00000016,
+DB_PERF_SEL_SC_DB_quad_sends = 0x00000017,
+DB_PERF_SEL_SC_DB_quad_busy = 0x00000018,
+DB_PERF_SEL_SC_DB_quad_squads = 0x00000019,
+DB_PERF_SEL_SC_DB_quad_tiles = 0x0000001a,
+DB_PERF_SEL_SC_DB_quad_pixels = 0x0000001b,
+DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x0000001c,
+DB_PERF_SEL_DB_SC_quad_sends = 0x0000001d,
+DB_PERF_SEL_DB_SC_quad_busy = 0x0000001e,
+DB_PERF_SEL_DB_SC_quad_stalls = 0x0000001f,
+DB_PERF_SEL_DB_SC_quad_tiles = 0x00000020,
+DB_PERF_SEL_DB_SC_quad_lit_quad = 0x00000021,
+DB_PERF_SEL_DB_CB_tile_sends = 0x00000022,
+DB_PERF_SEL_DB_CB_tile_busy = 0x00000023,
+DB_PERF_SEL_DB_CB_tile_stalls = 0x00000024,
+DB_PERF_SEL_SX_DB_quad_sends = 0x00000025,
+DB_PERF_SEL_SX_DB_quad_busy = 0x00000026,
+DB_PERF_SEL_SX_DB_quad_stalls = 0x00000027,
+DB_PERF_SEL_SX_DB_quad_quads = 0x00000028,
+DB_PERF_SEL_SX_DB_quad_pixels = 0x00000029,
+DB_PERF_SEL_SX_DB_quad_exports = 0x0000002a,
+DB_PERF_SEL_SH_quads_outstanding_sum = 0x0000002b,
+DB_PERF_SEL_DB_CB_lquad_sends = 0x0000002c,
+DB_PERF_SEL_DB_CB_lquad_busy = 0x0000002d,
+DB_PERF_SEL_DB_CB_lquad_stalls = 0x0000002e,
+DB_PERF_SEL_DB_CB_lquad_quads = 0x0000002f,
+DB_PERF_SEL_tile_rd_sends = 0x00000030,
+DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x00000031,
+DB_PERF_SEL_quad_rd_sends = 0x00000032,
+DB_PERF_SEL_quad_rd_busy = 0x00000033,
+DB_PERF_SEL_quad_rd_mi_stall = 0x00000034,
+DB_PERF_SEL_quad_rd_rw_collision = 0x00000035,
+DB_PERF_SEL_quad_rd_tag_stall = 0x00000036,
+DB_PERF_SEL_quad_rd_32byte_reqs = 0x00000037,
+DB_PERF_SEL_quad_rd_panic = 0x00000038,
+DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x00000039,
+DB_PERF_SEL_quad_rdret_sends = 0x0000003a,
+DB_PERF_SEL_quad_rdret_busy = 0x0000003b,
+DB_PERF_SEL_tile_wr_sends = 0x0000003c,
+DB_PERF_SEL_tile_wr_acks = 0x0000003d,
+DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x0000003e,
+DB_PERF_SEL_quad_wr_sends = 0x0000003f,
+DB_PERF_SEL_quad_wr_busy = 0x00000040,
+DB_PERF_SEL_quad_wr_mi_stall = 0x00000041,
+DB_PERF_SEL_quad_wr_coherency_stall = 0x00000042,
+DB_PERF_SEL_quad_wr_acks = 0x00000043,
+DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x00000044,
+DB_PERF_SEL_Tile_Cache_misses = 0x00000045,
+DB_PERF_SEL_Tile_Cache_hits = 0x00000046,
+DB_PERF_SEL_Tile_Cache_flushes = 0x00000047,
+DB_PERF_SEL_Tile_Cache_surface_stall = 0x00000048,
+DB_PERF_SEL_Tile_Cache_starves = 0x00000049,
+DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x0000004a,
+DB_PERF_SEL_tcp_dispatcher_reads = 0x0000004b,
+DB_PERF_SEL_tcp_prefetcher_reads = 0x0000004c,
+DB_PERF_SEL_tcp_preloader_reads = 0x0000004d,
+DB_PERF_SEL_tcp_dispatcher_flushes = 0x0000004e,
+DB_PERF_SEL_tcp_prefetcher_flushes = 0x0000004f,
+DB_PERF_SEL_tcp_preloader_flushes = 0x00000050,
+DB_PERF_SEL_Depth_Tile_Cache_sends = 0x00000051,
+DB_PERF_SEL_Depth_Tile_Cache_busy = 0x00000052,
+DB_PERF_SEL_Depth_Tile_Cache_starves = 0x00000053,
+DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x00000054,
+DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x00000055,
+DB_PERF_SEL_Depth_Tile_Cache_misses = 0x00000056,
+DB_PERF_SEL_Depth_Tile_Cache_hits = 0x00000057,
+DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x00000058,
+DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x00000059,
+DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x0000005a,
+DB_PERF_SEL_Depth_Tile_Cache_event = 0x0000005b,
+DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x0000005c,
+DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x0000005d,
+DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x0000005e,
+DB_PERF_SEL_Stencil_Cache_misses = 0x0000005f,
+DB_PERF_SEL_Stencil_Cache_hits = 0x00000060,
+DB_PERF_SEL_Stencil_Cache_flushes = 0x00000061,
+DB_PERF_SEL_Stencil_Cache_starves = 0x00000062,
+DB_PERF_SEL_Stencil_Cache_frees = 0x00000063,
+DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x00000064,
+DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x00000065,
+DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x00000066,
+DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x00000067,
+DB_PERF_SEL_Z_Cache_pmask_misses = 0x00000068,
+DB_PERF_SEL_Z_Cache_pmask_hits = 0x00000069,
+DB_PERF_SEL_Z_Cache_pmask_flushes = 0x0000006a,
+DB_PERF_SEL_Z_Cache_pmask_starves = 0x0000006b,
+DB_PERF_SEL_Z_Cache_frees = 0x0000006c,
+DB_PERF_SEL_Plane_Cache_misses = 0x0000006d,
+DB_PERF_SEL_Plane_Cache_hits = 0x0000006e,
+DB_PERF_SEL_Plane_Cache_flushes = 0x0000006f,
+DB_PERF_SEL_Plane_Cache_starves = 0x00000070,
+DB_PERF_SEL_Plane_Cache_frees = 0x00000071,
+DB_PERF_SEL_flush_expanded_stencil = 0x00000072,
+DB_PERF_SEL_flush_compressed_stencil = 0x00000073,
+DB_PERF_SEL_flush_single_stencil = 0x00000074,
+DB_PERF_SEL_planes_flushed = 0x00000075,
+DB_PERF_SEL_flush_1plane = 0x00000076,
+DB_PERF_SEL_flush_2plane = 0x00000077,
+DB_PERF_SEL_flush_3plane = 0x00000078,
+DB_PERF_SEL_flush_4plane = 0x00000079,
+DB_PERF_SEL_flush_5plane = 0x0000007a,
+DB_PERF_SEL_flush_6plane = 0x0000007b,
+DB_PERF_SEL_flush_7plane = 0x0000007c,
+DB_PERF_SEL_flush_8plane = 0x0000007d,
+DB_PERF_SEL_flush_9plane = 0x0000007e,
+DB_PERF_SEL_flush_10plane = 0x0000007f,
+DB_PERF_SEL_flush_11plane = 0x00000080,
+DB_PERF_SEL_flush_12plane = 0x00000081,
+DB_PERF_SEL_flush_13plane = 0x00000082,
+DB_PERF_SEL_flush_14plane = 0x00000083,
+DB_PERF_SEL_flush_15plane = 0x00000084,
+DB_PERF_SEL_flush_16plane = 0x00000085,
+DB_PERF_SEL_flush_expanded_z = 0x00000086,
+DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x00000087,
+DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x00000088,
+DB_PERF_SEL_dk_tile_sends = 0x00000089,
+DB_PERF_SEL_dk_tile_busy = 0x0000008a,
+DB_PERF_SEL_dk_tile_quad_starves = 0x0000008b,
+DB_PERF_SEL_dk_tile_stalls = 0x0000008c,
+DB_PERF_SEL_dk_squad_sends = 0x0000008d,
+DB_PERF_SEL_dk_squad_busy = 0x0000008e,
+DB_PERF_SEL_dk_squad_stalls = 0x0000008f,
+DB_PERF_SEL_Op_Pipe_Busy = 0x00000090,
+DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x00000091,
+DB_PERF_SEL_qc_busy = 0x00000092,
+DB_PERF_SEL_qc_xfc = 0x00000093,
+DB_PERF_SEL_qc_conflicts = 0x00000094,
+DB_PERF_SEL_qc_full_stall = 0x00000095,
+DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x00000096,
+DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x00000097,
+DB_PERF_SEL_tsc_insert_summarize_stall = 0x00000098,
+DB_PERF_SEL_tl_busy = 0x00000099,
+DB_PERF_SEL_tl_dtc_read_starved = 0x0000009a,
+DB_PERF_SEL_tl_z_fetch_stall = 0x0000009b,
+DB_PERF_SEL_tl_stencil_stall = 0x0000009c,
+DB_PERF_SEL_tl_z_decompress_stall = 0x0000009d,
+DB_PERF_SEL_tl_stencil_locked_stall = 0x0000009e,
+DB_PERF_SEL_tl_events = 0x0000009f,
+DB_PERF_SEL_tl_summarize_squads = 0x000000a0,
+DB_PERF_SEL_tl_flush_expand_squads = 0x000000a1,
+DB_PERF_SEL_tl_expand_squads = 0x000000a2,
+DB_PERF_SEL_tl_preZ_squads = 0x000000a3,
+DB_PERF_SEL_tl_postZ_squads = 0x000000a4,
+DB_PERF_SEL_tl_preZ_noop_squads = 0x000000a5,
+DB_PERF_SEL_tl_postZ_noop_squads = 0x000000a6,
+DB_PERF_SEL_tl_tile_ops = 0x000000a7,
+DB_PERF_SEL_tl_in_xfc = 0x000000a8,
+DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0x000000a9,
+DB_PERF_SEL_tl_in_fast_z_stall = 0x000000aa,
+DB_PERF_SEL_tl_out_xfc = 0x000000ab,
+DB_PERF_SEL_tl_out_squads = 0x000000ac,
+DB_PERF_SEL_zf_plane_multicycle = 0x000000ad,
+DB_PERF_SEL_PostZ_Samples_passing_Z = 0x000000ae,
+DB_PERF_SEL_PostZ_Samples_failing_Z = 0x000000af,
+DB_PERF_SEL_PostZ_Samples_failing_S = 0x000000b0,
+DB_PERF_SEL_PreZ_Samples_passing_Z = 0x000000b1,
+DB_PERF_SEL_PreZ_Samples_failing_Z = 0x000000b2,
+DB_PERF_SEL_PreZ_Samples_failing_S = 0x000000b3,
+DB_PERF_SEL_ts_tc_update_stall = 0x000000b4,
+DB_PERF_SEL_sc_kick_start = 0x000000b5,
+DB_PERF_SEL_sc_kick_end = 0x000000b6,
+DB_PERF_SEL_clock_reg_active = 0x000000b7,
+DB_PERF_SEL_clock_main_active = 0x000000b8,
+DB_PERF_SEL_clock_mem_export_active = 0x000000b9,
+DB_PERF_SEL_esr_ps_out_busy = 0x000000ba,
+DB_PERF_SEL_esr_ps_lqf_busy = 0x000000bb,
+DB_PERF_SEL_esr_ps_lqf_stall = 0x000000bc,
+DB_PERF_SEL_etr_out_send = 0x000000bd,
+DB_PERF_SEL_etr_out_busy = 0x000000be,
+DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0x000000bf,
+DB_PERF_SEL_etr_out_cb_tile_stall = 0x000000c0,
+DB_PERF_SEL_etr_out_esr_stall = 0x000000c1,
+DB_PERF_SEL_esr_ps_sqq_busy = 0x000000c2,
+DB_PERF_SEL_esr_ps_sqq_stall = 0x000000c3,
+DB_PERF_SEL_esr_eot_fwd_busy = 0x000000c4,
+DB_PERF_SEL_esr_eot_fwd_holding_squad = 0x000000c5,
+DB_PERF_SEL_esr_eot_fwd_forward = 0x000000c6,
+DB_PERF_SEL_esr_sqq_zi_busy = 0x000000c7,
+DB_PERF_SEL_esr_sqq_zi_stall = 0x000000c8,
+DB_PERF_SEL_postzl_sq_pt_busy = 0x000000c9,
+DB_PERF_SEL_postzl_sq_pt_stall = 0x000000ca,
+DB_PERF_SEL_postzl_se_busy = 0x000000cb,
+DB_PERF_SEL_postzl_se_stall = 0x000000cc,
+DB_PERF_SEL_postzl_partial_launch = 0x000000cd,
+DB_PERF_SEL_postzl_full_launch = 0x000000ce,
+DB_PERF_SEL_postzl_partial_waiting = 0x000000cf,
+DB_PERF_SEL_postzl_tile_mem_stall = 0x000000d0,
+DB_PERF_SEL_postzl_tile_init_stall = 0x000000d1,
+DB_PEFF_SEL_prezl_tile_mem_stall = 0x000000d2,
+DB_PERF_SEL_prezl_tile_init_stall = 0x000000d3,
+DB_PERF_SEL_dtt_sm_clash_stall = 0x000000d4,
+DB_PERF_SEL_dtt_sm_slot_stall = 0x000000d5,
+DB_PERF_SEL_dtt_sm_miss_stall = 0x000000d6,
+DB_PERF_SEL_mi_rdreq_busy = 0x000000d7,
+DB_PERF_SEL_mi_rdreq_stall = 0x000000d8,
+DB_PERF_SEL_mi_wrreq_busy = 0x000000d9,
+DB_PERF_SEL_mi_wrreq_stall = 0x000000da,
+DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0x000000db,
+DB_PERF_SEL_dkg_tile_rate_tile = 0x000000dc,
+DB_PERF_SEL_prezl_src_in_sends = 0x000000dd,
+DB_PERF_SEL_prezl_src_in_stall = 0x000000de,
+DB_PERF_SEL_prezl_src_in_squads = 0x000000df,
+DB_PERF_SEL_prezl_src_in_squads_unrolled = 0x000000e0,
+DB_PERF_SEL_prezl_src_in_tile_rate = 0x000000e1,
+DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0x000000e2,
+DB_PERF_SEL_prezl_src_out_stall = 0x000000e3,
+DB_PERF_SEL_postzl_src_in_sends = 0x000000e4,
+DB_PERF_SEL_postzl_src_in_stall = 0x000000e5,
+DB_PERF_SEL_postzl_src_in_squads = 0x000000e6,
+DB_PERF_SEL_postzl_src_in_squads_unrolled = 0x000000e7,
+DB_PERF_SEL_postzl_src_in_tile_rate = 0x000000e8,
+DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0x000000e9,
+DB_PERF_SEL_postzl_src_out_stall = 0x000000ea,
+DB_PERF_SEL_esr_ps_src_in_sends = 0x000000eb,
+DB_PERF_SEL_esr_ps_src_in_stall = 0x000000ec,
+DB_PERF_SEL_esr_ps_src_in_squads = 0x000000ed,
+DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0x000000ee,
+DB_PERF_SEL_esr_ps_src_in_tile_rate = 0x000000ef,
+DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0x000000f0,
+DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 0x000000f1,
+DB_PERF_SEL_esr_ps_src_out_stall = 0x000000f2,
+DB_PERF_SEL_depth_bounds_qtiles_culled = 0x000000f3,
+DB_PERF_SEL_PreZ_Samples_failing_DB = 0x000000f4,
+DB_PERF_SEL_PostZ_Samples_failing_DB = 0x000000f5,
+DB_PERF_SEL_flush_compressed = 0x000000f6,
+DB_PERF_SEL_flush_plane_le4 = 0x000000f7,
+DB_PERF_SEL_tiles_z_fully_summarized = 0x000000f8,
+DB_PERF_SEL_tiles_stencil_fully_summarized = 0x000000f9,
+DB_PERF_SEL_tiles_z_clear_on_expclear = 0x000000fa,
+DB_PERF_SEL_tiles_s_clear_on_expclear = 0x000000fb,
+DB_PERF_SEL_tiles_decomp_on_expclear = 0x000000fc,
+DB_PERF_SEL_tiles_compressed_to_decompressed = 0x000000fd,
+DB_PERF_SEL_Op_Pipe_Prez_Busy = 0x000000fe,
+DB_PERF_SEL_Op_Pipe_Postz_Busy = 0x000000ff,
+DB_PERF_SEL_di_dt_stall = 0x00000100,
+DB_PERF_SEL_DB_SC_quad_double_quad = 0x00000101,
+DB_PERF_SEL_SX_DB_quad_export_quads = 0x00000102,
+DB_PERF_SEL_SX_DB_quad_double_format = 0x00000103,
+DB_PERF_SEL_SX_DB_quad_fast_format = 0x00000104,
+DB_PERF_SEL_SX_DB_quad_slow_format = 0x00000105,
+DB_PERF_SEL_DB_CB_lquad_export_quads = 0x00000106,
+DB_PERF_SEL_DB_CB_lquad_double_format = 0x00000107,
+DB_PERF_SEL_DB_CB_lquad_fast_format = 0x00000108,
+DB_PERF_SEL_DB_CB_lquad_slow_format = 0x00000109,
+DB_PERF_SEL_CB_DB_rdreq_sends = 0x0000010a,
+DB_PERF_SEL_CB_DB_rdreq_prt_sends = 0x0000010b,
+DB_PERF_SEL_CB_DB_wrreq_sends = 0x0000010c,
+DB_PERF_SEL_CB_DB_wrreq_prt_sends = 0x0000010d,
+DB_PERF_SEL_DB_CB_rdret_ack = 0x0000010e,
+DB_PERF_SEL_DB_CB_rdret_nack = 0x0000010f,
+DB_PERF_SEL_DB_CB_wrret_ack = 0x00000110,
+DB_PERF_SEL_DB_CB_wrret_nack = 0x00000111,
+DB_PERF_SEL_DFSM_squads_in = 0x00000112,
+DB_PERF_SEL_DFSM_full_cleared_squads_out = 0x00000113,
+DB_PERF_SEL_DFSM_quads_in = 0x00000114,
+DB_PERF_SEL_DFSM_fully_cleared_quads_out = 0x00000115,
+DB_PERF_SEL_DFSM_lit_pixels_in = 0x00000116,
+DB_PERF_SEL_DFSM_fully_cleared_pixels_out = 0x00000117,
+DB_PERF_SEL_DFSM_lit_samples_in = 0x00000118,
+DB_PERF_SEL_DFSM_lit_samples_out = 0x00000119,
+DB_PERF_SEL_DFSM_cycles_above_watermark = 0x0000011a,
+DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream = 0x0000011b,
+DB_PERF_SEL_DFSM_stalled_by_downstream = 0x0000011c,
+DB_PERF_SEL_DFSM_evicted_squads_above_watermark = 0x0000011d,
+DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow = 0x0000011e,
+DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO = 0x0000011f,
+DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark = 0x00000120,
+} PerfCounter_Vals;
+
+/*
+ * RingCounterControl enum
+ */
+
+typedef enum RingCounterControl {
+COUNTER_RING_SPLIT = 0x00000000,
+COUNTER_RING_0 = 0x00000001,
+COUNTER_RING_1 = 0x00000002,
+} RingCounterControl;
+
+/*
+ * DbMemArbWatermarks enum
+ */
+
+typedef enum DbMemArbWatermarks {
+TRANSFERRED_64_BYTES = 0x00000000,
+TRANSFERRED_128_BYTES = 0x00000001,
+TRANSFERRED_256_BYTES = 0x00000002,
+TRANSFERRED_512_BYTES = 0x00000003,
+TRANSFERRED_1024_BYTES = 0x00000004,
+TRANSFERRED_2048_BYTES = 0x00000005,
+TRANSFERRED_4096_BYTES = 0x00000006,
+TRANSFERRED_8192_BYTES = 0x00000007,
+} DbMemArbWatermarks;
+
+/*
+ * DFSMFlushEvents enum
+ */
+
+typedef enum DFSMFlushEvents {
+DB_FLUSH_AND_INV_DB_DATA_TS = 0x00000000,
+DB_FLUSH_AND_INV_DB_META = 0x00000001,
+DB_CACHE_FLUSH = 0x00000002,
+DB_CACHE_FLUSH_TS = 0x00000003,
+DB_CACHE_FLUSH_AND_INV_EVENT = 0x00000004,
+DB_CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000005,
+} DFSMFlushEvents;
+
+/*
+ * PixelPipeCounterId enum
+ */
+
+typedef enum PixelPipeCounterId {
+PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x00000000,
+PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x00000001,
+PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x00000002,
+PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x00000003,
+PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x00000004,
+PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x00000005,
+PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x00000006,
+PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x00000007,
+} PixelPipeCounterId;
+
+/*
+ * PixelPipeStride enum
+ */
+
+typedef enum PixelPipeStride {
+PIXEL_PIPE_STRIDE_32_BITS = 0x00000000,
+PIXEL_PIPE_STRIDE_64_BITS = 0x00000001,
+PIXEL_PIPE_STRIDE_128_BITS = 0x00000002,
+PIXEL_PIPE_STRIDE_256_BITS = 0x00000003,
+} PixelPipeStride;
+
+/*******************************************************
+ * TA Enums
+ *******************************************************/
+
+/*
+ * TEX_BORDER_COLOR_TYPE enum
+ */
+
+typedef enum TEX_BORDER_COLOR_TYPE {
+TEX_BorderColor_TransparentBlack = 0x00000000,
+TEX_BorderColor_OpaqueBlack = 0x00000001,
+TEX_BorderColor_OpaqueWhite = 0x00000002,
+TEX_BorderColor_Register = 0x00000003,
+} TEX_BORDER_COLOR_TYPE;
+
+/*
+ * TEX_CHROMA_KEY enum
+ */
+
+typedef enum TEX_CHROMA_KEY {
+TEX_ChromaKey_Disabled = 0x00000000,
+TEX_ChromaKey_Kill = 0x00000001,
+TEX_ChromaKey_Blend = 0x00000002,
+TEX_ChromaKey_RESERVED_3 = 0x00000003,
+} TEX_CHROMA_KEY;
+
+/*
+ * TEX_CLAMP enum
+ */
+
+typedef enum TEX_CLAMP {
+TEX_Clamp_Repeat = 0x00000000,
+TEX_Clamp_Mirror = 0x00000001,
+TEX_Clamp_ClampToLast = 0x00000002,
+TEX_Clamp_MirrorOnceToLast = 0x00000003,
+TEX_Clamp_ClampHalfToBorder = 0x00000004,
+TEX_Clamp_MirrorOnceHalfToBorder = 0x00000005,
+TEX_Clamp_ClampToBorder = 0x00000006,
+TEX_Clamp_MirrorOnceToBorder = 0x00000007,
+} TEX_CLAMP;
+
+/*
+ * TEX_COORD_TYPE enum
+ */
+
+typedef enum TEX_COORD_TYPE {
+TEX_CoordType_Unnormalized = 0x00000000,
+TEX_CoordType_Normalized = 0x00000001,
+} TEX_COORD_TYPE;
+
+/*
+ * TEX_DEPTH_COMPARE_FUNCTION enum
+ */
+
+typedef enum TEX_DEPTH_COMPARE_FUNCTION {
+TEX_DepthCompareFunction_Never = 0x00000000,
+TEX_DepthCompareFunction_Less = 0x00000001,
+TEX_DepthCompareFunction_Equal = 0x00000002,
+TEX_DepthCompareFunction_LessEqual = 0x00000003,
+TEX_DepthCompareFunction_Greater = 0x00000004,
+TEX_DepthCompareFunction_NotEqual = 0x00000005,
+TEX_DepthCompareFunction_GreaterEqual = 0x00000006,
+TEX_DepthCompareFunction_Always = 0x00000007,
+} TEX_DEPTH_COMPARE_FUNCTION;
+
+/*
+ * TEX_DIM enum
+ */
+
+typedef enum TEX_DIM {
+TEX_Dim_1D = 0x00000000,
+TEX_Dim_2D = 0x00000001,
+TEX_Dim_3D = 0x00000002,
+TEX_Dim_CubeMap = 0x00000003,
+TEX_Dim_1DArray = 0x00000004,
+TEX_Dim_2DArray = 0x00000005,
+TEX_Dim_2D_MSAA = 0x00000006,
+TEX_Dim_2DArray_MSAA = 0x00000007,
+} TEX_DIM;
+
+/*
+ * TEX_FORMAT_COMP enum
+ */
+
+typedef enum TEX_FORMAT_COMP {
+TEX_FormatComp_Unsigned = 0x00000000,
+TEX_FormatComp_Signed = 0x00000001,
+TEX_FormatComp_UnsignedBiased = 0x00000002,
+TEX_FormatComp_RESERVED_3 = 0x00000003,
+} TEX_FORMAT_COMP;
+
+/*
+ * TEX_MAX_ANISO_RATIO enum
+ */
+
+typedef enum TEX_MAX_ANISO_RATIO {
+TEX_MaxAnisoRatio_1to1 = 0x00000000,
+TEX_MaxAnisoRatio_2to1 = 0x00000001,
+TEX_MaxAnisoRatio_4to1 = 0x00000002,
+TEX_MaxAnisoRatio_8to1 = 0x00000003,
+TEX_MaxAnisoRatio_16to1 = 0x00000004,
+TEX_MaxAnisoRatio_RESERVED_5 = 0x00000005,
+TEX_MaxAnisoRatio_RESERVED_6 = 0x00000006,
+TEX_MaxAnisoRatio_RESERVED_7 = 0x00000007,
+} TEX_MAX_ANISO_RATIO;
+
+/*
+ * TEX_MIP_FILTER enum
+ */
+
+typedef enum TEX_MIP_FILTER {
+TEX_MipFilter_None = 0x00000000,
+TEX_MipFilter_Point = 0x00000001,
+TEX_MipFilter_Linear = 0x00000002,
+TEX_MipFilter_Point_Aniso_Adj = 0x00000003,
+} TEX_MIP_FILTER;
+
+/*
+ * TEX_REQUEST_SIZE enum
+ */
+
+typedef enum TEX_REQUEST_SIZE {
+TEX_RequestSize_32B = 0x00000000,
+TEX_RequestSize_64B = 0x00000001,
+TEX_RequestSize_128B = 0x00000002,
+TEX_RequestSize_2X64B = 0x00000003,
+} TEX_REQUEST_SIZE;
+
+/*
+ * TEX_SAMPLER_TYPE enum
+ */
+
+typedef enum TEX_SAMPLER_TYPE {
+TEX_SamplerType_Invalid = 0x00000000,
+TEX_SamplerType_Valid = 0x00000001,
+} TEX_SAMPLER_TYPE;
+
+/*
+ * TEX_XY_FILTER enum
+ */
+
+typedef enum TEX_XY_FILTER {
+TEX_XYFilter_Point = 0x00000000,
+TEX_XYFilter_Linear = 0x00000001,
+TEX_XYFilter_AnisoPoint = 0x00000002,
+TEX_XYFilter_AnisoLinear = 0x00000003,
+} TEX_XY_FILTER;
+
+/*
+ * TEX_Z_FILTER enum
+ */
+
+typedef enum TEX_Z_FILTER {
+TEX_ZFilter_None = 0x00000000,
+TEX_ZFilter_Point = 0x00000001,
+TEX_ZFilter_Linear = 0x00000002,
+TEX_ZFilter_RESERVED_3 = 0x00000003,
+} TEX_Z_FILTER;
+
+/*
+ * VTX_CLAMP enum
+ */
+
+typedef enum VTX_CLAMP {
+VTX_Clamp_ClampToZero = 0x00000000,
+VTX_Clamp_ClampToNAN = 0x00000001,
+} VTX_CLAMP;
+
+/*
+ * VTX_FETCH_TYPE enum
+ */
+
+typedef enum VTX_FETCH_TYPE {
+VTX_FetchType_VertexData = 0x00000000,
+VTX_FetchType_InstanceData = 0x00000001,
+VTX_FetchType_NoIndexOffset = 0x00000002,
+VTX_FetchType_RESERVED_3 = 0x00000003,
+} VTX_FETCH_TYPE;
+
+/*
+ * VTX_FORMAT_COMP_ALL enum
+ */
+
+typedef enum VTX_FORMAT_COMP_ALL {
+VTX_FormatCompAll_Unsigned = 0x00000000,
+VTX_FormatCompAll_Signed = 0x00000001,
+} VTX_FORMAT_COMP_ALL;
+
+/*
+ * VTX_MEM_REQUEST_SIZE enum
+ */
+
+typedef enum VTX_MEM_REQUEST_SIZE {
+VTX_MemRequestSize_32B = 0x00000000,
+VTX_MemRequestSize_64B = 0x00000001,
+} VTX_MEM_REQUEST_SIZE;
+
+/*
+ * TVX_DATA_FORMAT enum
+ */
+
+typedef enum TVX_DATA_FORMAT {
+TVX_FMT_INVALID = 0x00000000,
+TVX_FMT_8 = 0x00000001,
+TVX_FMT_4_4 = 0x00000002,
+TVX_FMT_3_3_2 = 0x00000003,
+TVX_FMT_RESERVED_4 = 0x00000004,
+TVX_FMT_16 = 0x00000005,
+TVX_FMT_16_FLOAT = 0x00000006,
+TVX_FMT_8_8 = 0x00000007,
+TVX_FMT_5_6_5 = 0x00000008,
+TVX_FMT_6_5_5 = 0x00000009,
+TVX_FMT_1_5_5_5 = 0x0000000a,
+TVX_FMT_4_4_4_4 = 0x0000000b,
+TVX_FMT_5_5_5_1 = 0x0000000c,
+TVX_FMT_32 = 0x0000000d,
+TVX_FMT_32_FLOAT = 0x0000000e,
+TVX_FMT_16_16 = 0x0000000f,
+TVX_FMT_16_16_FLOAT = 0x00000010,
+TVX_FMT_8_24 = 0x00000011,
+TVX_FMT_8_24_FLOAT = 0x00000012,
+TVX_FMT_24_8 = 0x00000013,
+TVX_FMT_24_8_FLOAT = 0x00000014,
+TVX_FMT_10_11_11 = 0x00000015,
+TVX_FMT_10_11_11_FLOAT = 0x00000016,
+TVX_FMT_11_11_10 = 0x00000017,
+TVX_FMT_11_11_10_FLOAT = 0x00000018,
+TVX_FMT_2_10_10_10 = 0x00000019,
+TVX_FMT_8_8_8_8 = 0x0000001a,
+TVX_FMT_10_10_10_2 = 0x0000001b,
+TVX_FMT_X24_8_32_FLOAT = 0x0000001c,
+TVX_FMT_32_32 = 0x0000001d,
+TVX_FMT_32_32_FLOAT = 0x0000001e,
+TVX_FMT_16_16_16_16 = 0x0000001f,
+TVX_FMT_16_16_16_16_FLOAT = 0x00000020,
+TVX_FMT_RESERVED_33 = 0x00000021,
+TVX_FMT_32_32_32_32 = 0x00000022,
+TVX_FMT_32_32_32_32_FLOAT = 0x00000023,
+TVX_FMT_RESERVED_36 = 0x00000024,
+TVX_FMT_1 = 0x00000025,
+TVX_FMT_1_REVERSED = 0x00000026,
+TVX_FMT_GB_GR = 0x00000027,
+TVX_FMT_BG_RG = 0x00000028,
+TVX_FMT_32_AS_8 = 0x00000029,
+TVX_FMT_32_AS_8_8 = 0x0000002a,
+TVX_FMT_5_9_9_9_SHAREDEXP = 0x0000002b,
+TVX_FMT_8_8_8 = 0x0000002c,
+TVX_FMT_16_16_16 = 0x0000002d,
+TVX_FMT_16_16_16_FLOAT = 0x0000002e,
+TVX_FMT_32_32_32 = 0x0000002f,
+TVX_FMT_32_32_32_FLOAT = 0x00000030,
+TVX_FMT_BC1 = 0x00000031,
+TVX_FMT_BC2 = 0x00000032,
+TVX_FMT_BC3 = 0x00000033,
+TVX_FMT_BC4 = 0x00000034,
+TVX_FMT_BC5 = 0x00000035,
+TVX_FMT_APC0 = 0x00000036,
+TVX_FMT_APC1 = 0x00000037,
+TVX_FMT_APC2 = 0x00000038,
+TVX_FMT_APC3 = 0x00000039,
+TVX_FMT_APC4 = 0x0000003a,
+TVX_FMT_APC5 = 0x0000003b,
+TVX_FMT_APC6 = 0x0000003c,
+TVX_FMT_APC7 = 0x0000003d,
+TVX_FMT_CTX1 = 0x0000003e,
+TVX_FMT_RESERVED_63 = 0x0000003f,
+} TVX_DATA_FORMAT;
+
+/*
+ * TVX_DST_SEL enum
+ */
+
+typedef enum TVX_DST_SEL {
+TVX_DstSel_X = 0x00000000,
+TVX_DstSel_Y = 0x00000001,
+TVX_DstSel_Z = 0x00000002,
+TVX_DstSel_W = 0x00000003,
+TVX_DstSel_0f = 0x00000004,
+TVX_DstSel_1f = 0x00000005,
+TVX_DstSel_RESERVED_6 = 0x00000006,
+TVX_DstSel_Mask = 0x00000007,
+} TVX_DST_SEL;
+
+/*
+ * TVX_ENDIAN_SWAP enum
+ */
+
+typedef enum TVX_ENDIAN_SWAP {
+TVX_EndianSwap_None = 0x00000000,
+TVX_EndianSwap_8in16 = 0x00000001,
+TVX_EndianSwap_8in32 = 0x00000002,
+TVX_EndianSwap_8in64 = 0x00000003,
+} TVX_ENDIAN_SWAP;
+
+/*
+ * TVX_INST enum
+ */
+
+typedef enum TVX_INST {
+TVX_Inst_NormalVertexFetch = 0x00000000,
+TVX_Inst_SemanticVertexFetch = 0x00000001,
+TVX_Inst_RESERVED_2 = 0x00000002,
+TVX_Inst_LD = 0x00000003,
+TVX_Inst_GetTextureResInfo = 0x00000004,
+TVX_Inst_GetNumberOfSamples = 0x00000005,
+TVX_Inst_GetLOD = 0x00000006,
+TVX_Inst_GetGradientsH = 0x00000007,
+TVX_Inst_GetGradientsV = 0x00000008,
+TVX_Inst_SetTextureOffsets = 0x00000009,
+TVX_Inst_KeepGradients = 0x0000000a,
+TVX_Inst_SetGradientsH = 0x0000000b,
+TVX_Inst_SetGradientsV = 0x0000000c,
+TVX_Inst_Pass = 0x0000000d,
+TVX_Inst_GetBufferResInfo = 0x0000000e,
+TVX_Inst_RESERVED_15 = 0x0000000f,
+TVX_Inst_Sample = 0x00000010,
+TVX_Inst_Sample_L = 0x00000011,
+TVX_Inst_Sample_LB = 0x00000012,
+TVX_Inst_Sample_LZ = 0x00000013,
+TVX_Inst_Sample_G = 0x00000014,
+TVX_Inst_Gather4 = 0x00000015,
+TVX_Inst_Sample_G_LB = 0x00000016,
+TVX_Inst_Gather4_O = 0x00000017,
+TVX_Inst_Sample_C = 0x00000018,
+TVX_Inst_Sample_C_L = 0x00000019,
+TVX_Inst_Sample_C_LB = 0x0000001a,
+TVX_Inst_Sample_C_LZ = 0x0000001b,
+TVX_Inst_Sample_C_G = 0x0000001c,
+TVX_Inst_Gather4_C = 0x0000001d,
+TVX_Inst_Sample_C_G_LB = 0x0000001e,
+TVX_Inst_Gather4_C_O = 0x0000001f,
+} TVX_INST;
+
+/*
+ * TVX_NUM_FORMAT_ALL enum
+ */
+
+typedef enum TVX_NUM_FORMAT_ALL {
+TVX_NumFormatAll_Norm = 0x00000000,
+TVX_NumFormatAll_Int = 0x00000001,
+TVX_NumFormatAll_Scaled = 0x00000002,
+TVX_NumFormatAll_RESERVED_3 = 0x00000003,
+} TVX_NUM_FORMAT_ALL;
+
+/*
+ * TVX_SRC_SEL enum
+ */
+
+typedef enum TVX_SRC_SEL {
+TVX_SrcSel_X = 0x00000000,
+TVX_SrcSel_Y = 0x00000001,
+TVX_SrcSel_Z = 0x00000002,
+TVX_SrcSel_W = 0x00000003,
+TVX_SrcSel_0f = 0x00000004,
+TVX_SrcSel_1f = 0x00000005,
+} TVX_SRC_SEL;
+
+/*
+ * TVX_SRF_MODE_ALL enum
+ */
+
+typedef enum TVX_SRF_MODE_ALL {
+TVX_SRFModeAll_ZCMO = 0x00000000,
+TVX_SRFModeAll_NZ = 0x00000001,
+} TVX_SRF_MODE_ALL;
+
+/*
+ * TVX_TYPE enum
+ */
+
+typedef enum TVX_TYPE {
+TVX_Type_InvalidTextureResource = 0x00000000,
+TVX_Type_InvalidVertexBuffer = 0x00000001,
+TVX_Type_ValidTextureResource = 0x00000002,
+TVX_Type_ValidVertexBuffer = 0x00000003,
+} TVX_TYPE;
+
+/*******************************************************
+ * PA Enums
+ *******************************************************/
+
+/*
+ * SU_PERFCNT_SEL enum
+ */
+
+typedef enum SU_PERFCNT_SEL {
+PERF_PAPC_PASX_REQ = 0x00000000,
+PERF_PAPC_PASX_DISABLE_PIPE = 0x00000001,
+PERF_PAPC_PASX_FIRST_VECTOR = 0x00000002,
+PERF_PAPC_PASX_SECOND_VECTOR = 0x00000003,
+PERF_PAPC_PASX_FIRST_DEAD = 0x00000004,
+PERF_PAPC_PASX_SECOND_DEAD = 0x00000005,
+PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x00000006,
+PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x00000007,
+PERF_PAPC_PA_INPUT_PRIM = 0x00000008,
+PERF_PAPC_PA_INPUT_NULL_PRIM = 0x00000009,
+PERF_PAPC_PA_INPUT_EVENT_FLAG = 0x0000000a,
+PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0x0000000b,
+PERF_PAPC_PA_INPUT_END_OF_PACKET = 0x0000000c,
+PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0x0000000d,
+PERF_PAPC_CLPR_CULL_PRIM = 0x0000000e,
+PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0x0000000f,
+PERF_PAPC_CLPR_VV_CULL_PRIM = 0x00000010,
+PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x00000011,
+PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x00000012,
+PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x00000013,
+PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x00000014,
+PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x00000015,
+PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x00000016,
+PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x00000017,
+PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x00000018,
+PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x00000019,
+PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x0000001a,
+PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x0000001b,
+PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x0000001c,
+PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x0000001d,
+PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x0000001e,
+PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x0000001f,
+PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x00000020,
+PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x00000021,
+PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x00000022,
+PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x00000023,
+PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x00000024,
+PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x00000025,
+PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x00000026,
+PERF_PAPC_CLSM_NULL_PRIM = 0x00000027,
+PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x00000028,
+PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x00000029,
+PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x0000002a,
+PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x0000002b,
+PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x0000002c,
+PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x0000002d,
+PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x0000002e,
+PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x0000002f,
+PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x00000030,
+PERF_PAPC_SU_INPUT_PRIM = 0x00000031,
+PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x00000032,
+PERF_PAPC_SU_INPUT_NULL_PRIM = 0x00000033,
+PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x00000034,
+PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x00000035,
+PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x00000036,
+PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x00000037,
+PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x00000038,
+PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x00000039,
+PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x0000003a,
+PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x0000003b,
+PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x0000003c,
+PERF_PAPC_SU_OUTPUT_PRIM = 0x0000003d,
+PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x0000003e,
+PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x0000003f,
+PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x00000040,
+PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x00000041,
+PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x00000042,
+PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x00000043,
+PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x00000044,
+PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x00000045,
+PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x00000046,
+PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x00000047,
+PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x00000048,
+PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x00000049,
+PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x0000004a,
+PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x0000004b,
+PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x0000004c,
+PERF_PAPC_PASX_REQ_IDLE = 0x0000004d,
+PERF_PAPC_PASX_REQ_BUSY = 0x0000004e,
+PERF_PAPC_PASX_REQ_STALLED = 0x0000004f,
+PERF_PAPC_PASX_REC_IDLE = 0x00000050,
+PERF_PAPC_PASX_REC_BUSY = 0x00000051,
+PERF_PAPC_PASX_REC_STARVED_SX = 0x00000052,
+PERF_PAPC_PASX_REC_STALLED = 0x00000053,
+PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x00000054,
+PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x00000055,
+PERF_PAPC_CCGSM_IDLE = 0x00000056,
+PERF_PAPC_CCGSM_BUSY = 0x00000057,
+PERF_PAPC_CCGSM_STALLED = 0x00000058,
+PERF_PAPC_CLPRIM_IDLE = 0x00000059,
+PERF_PAPC_CLPRIM_BUSY = 0x0000005a,
+PERF_PAPC_CLPRIM_STALLED = 0x0000005b,
+PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x0000005c,
+PERF_PAPC_CLIPSM_IDLE = 0x0000005d,
+PERF_PAPC_CLIPSM_BUSY = 0x0000005e,
+PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x0000005f,
+PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x00000060,
+PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x00000061,
+PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x00000062,
+PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x00000063,
+PERF_PAPC_CLIPGA_IDLE = 0x00000064,
+PERF_PAPC_CLIPGA_BUSY = 0x00000065,
+PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x00000066,
+PERF_PAPC_CLIPGA_STALLED = 0x00000067,
+PERF_PAPC_CLIP_IDLE = 0x00000068,
+PERF_PAPC_CLIP_BUSY = 0x00000069,
+PERF_PAPC_SU_IDLE = 0x0000006a,
+PERF_PAPC_SU_BUSY = 0x0000006b,
+PERF_PAPC_SU_STARVED_CLIP = 0x0000006c,
+PERF_PAPC_SU_STALLED_SC = 0x0000006d,
+PERF_PAPC_CL_DYN_SCLK_VLD = 0x0000006e,
+PERF_PAPC_SU_DYN_SCLK_VLD = 0x0000006f,
+PERF_PAPC_PA_REG_SCLK_VLD = 0x00000070,
+PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x00000071,
+PERF_PAPC_PASX_SE0_REQ = 0x00000072,
+PERF_PAPC_PASX_SE1_REQ = 0x00000073,
+PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x00000074,
+PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x00000075,
+PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x00000076,
+PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x00000077,
+PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x00000078,
+PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x00000079,
+PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x0000007a,
+PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x0000007b,
+PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x0000007c,
+PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x0000007d,
+PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x0000007e,
+PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x0000007f,
+PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x00000080,
+PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x00000081,
+PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x00000082,
+PERF_PAPC_SU_SE0_STALLED_SC = 0x00000083,
+PERF_PAPC_SU_SE1_STALLED_SC = 0x00000084,
+PERF_PAPC_SU_SE01_STALLED_SC = 0x00000085,
+PERF_PAPC_CLSM_CLIPPING_PRIM = 0x00000086,
+PERF_PAPC_SU_CULLED_PRIM = 0x00000087,
+PERF_PAPC_SU_OUTPUT_EOPG = 0x00000088,
+PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x00000089,
+PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x0000008a,
+PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x0000008b,
+PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x0000008c,
+PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x0000008d,
+PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x0000008e,
+PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 0x0000008f,
+PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 0x00000090,
+PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 0x00000091,
+PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 0x00000092,
+PERF_PAPC_SU_SE0_OUTPUT_EOPG = 0x00000093,
+PERF_PAPC_SU_SE1_OUTPUT_EOPG = 0x00000094,
+PERF_PAPC_SU_SE2_OUTPUT_EOPG = 0x00000095,
+PERF_PAPC_SU_SE3_OUTPUT_EOPG = 0x00000096,
+PERF_PAPC_SU_SE2_STALLED_SC = 0x00000097,
+PERF_PAPC_SU_SE3_STALLED_SC = 0x00000098,
+} SU_PERFCNT_SEL;
+
+/*
+ * SC_PERFCNT_SEL enum
+ */
+
+typedef enum SC_PERFCNT_SEL {
+SC_SRPS_WINDOW_VALID = 0x00000000,
+SC_PSSW_WINDOW_VALID = 0x00000001,
+SC_TPQZ_WINDOW_VALID = 0x00000002,
+SC_QZQP_WINDOW_VALID = 0x00000003,
+SC_TRPK_WINDOW_VALID = 0x00000004,
+SC_SRPS_WINDOW_VALID_BUSY = 0x00000005,
+SC_PSSW_WINDOW_VALID_BUSY = 0x00000006,
+SC_TPQZ_WINDOW_VALID_BUSY = 0x00000007,
+SC_QZQP_WINDOW_VALID_BUSY = 0x00000008,
+SC_TRPK_WINDOW_VALID_BUSY = 0x00000009,
+SC_STARVED_BY_PA = 0x0000000a,
+SC_STALLED_BY_PRIMFIFO = 0x0000000b,
+SC_STALLED_BY_DB_TILE = 0x0000000c,
+SC_STARVED_BY_DB_TILE = 0x0000000d,
+SC_STALLED_BY_TILEORDERFIFO = 0x0000000e,
+SC_STALLED_BY_TILEFIFO = 0x0000000f,
+SC_STALLED_BY_DB_QUAD = 0x00000010,
+SC_STARVED_BY_DB_QUAD = 0x00000011,
+SC_STALLED_BY_QUADFIFO = 0x00000012,
+SC_STALLED_BY_BCI = 0x00000013,
+SC_STALLED_BY_SPI = 0x00000014,
+SC_SCISSOR_DISCARD = 0x00000015,
+SC_BB_DISCARD = 0x00000016,
+SC_SUPERTILE_COUNT = 0x00000017,
+SC_SUPERTILE_PER_PRIM_H0 = 0x00000018,
+SC_SUPERTILE_PER_PRIM_H1 = 0x00000019,
+SC_SUPERTILE_PER_PRIM_H2 = 0x0000001a,
+SC_SUPERTILE_PER_PRIM_H3 = 0x0000001b,
+SC_SUPERTILE_PER_PRIM_H4 = 0x0000001c,
+SC_SUPERTILE_PER_PRIM_H5 = 0x0000001d,
+SC_SUPERTILE_PER_PRIM_H6 = 0x0000001e,
+SC_SUPERTILE_PER_PRIM_H7 = 0x0000001f,
+SC_SUPERTILE_PER_PRIM_H8 = 0x00000020,
+SC_SUPERTILE_PER_PRIM_H9 = 0x00000021,
+SC_SUPERTILE_PER_PRIM_H10 = 0x00000022,
+SC_SUPERTILE_PER_PRIM_H11 = 0x00000023,
+SC_SUPERTILE_PER_PRIM_H12 = 0x00000024,
+SC_SUPERTILE_PER_PRIM_H13 = 0x00000025,
+SC_SUPERTILE_PER_PRIM_H14 = 0x00000026,
+SC_SUPERTILE_PER_PRIM_H15 = 0x00000027,
+SC_SUPERTILE_PER_PRIM_H16 = 0x00000028,
+SC_TILE_PER_PRIM_H0 = 0x00000029,
+SC_TILE_PER_PRIM_H1 = 0x0000002a,
+SC_TILE_PER_PRIM_H2 = 0x0000002b,
+SC_TILE_PER_PRIM_H3 = 0x0000002c,
+SC_TILE_PER_PRIM_H4 = 0x0000002d,
+SC_TILE_PER_PRIM_H5 = 0x0000002e,
+SC_TILE_PER_PRIM_H6 = 0x0000002f,
+SC_TILE_PER_PRIM_H7 = 0x00000030,
+SC_TILE_PER_PRIM_H8 = 0x00000031,
+SC_TILE_PER_PRIM_H9 = 0x00000032,
+SC_TILE_PER_PRIM_H10 = 0x00000033,
+SC_TILE_PER_PRIM_H11 = 0x00000034,
+SC_TILE_PER_PRIM_H12 = 0x00000035,
+SC_TILE_PER_PRIM_H13 = 0x00000036,
+SC_TILE_PER_PRIM_H14 = 0x00000037,
+SC_TILE_PER_PRIM_H15 = 0x00000038,
+SC_TILE_PER_PRIM_H16 = 0x00000039,
+SC_TILE_PER_SUPERTILE_H0 = 0x0000003a,
+SC_TILE_PER_SUPERTILE_H1 = 0x0000003b,
+SC_TILE_PER_SUPERTILE_H2 = 0x0000003c,
+SC_TILE_PER_SUPERTILE_H3 = 0x0000003d,
+SC_TILE_PER_SUPERTILE_H4 = 0x0000003e,
+SC_TILE_PER_SUPERTILE_H5 = 0x0000003f,
+SC_TILE_PER_SUPERTILE_H6 = 0x00000040,
+SC_TILE_PER_SUPERTILE_H7 = 0x00000041,
+SC_TILE_PER_SUPERTILE_H8 = 0x00000042,
+SC_TILE_PER_SUPERTILE_H9 = 0x00000043,
+SC_TILE_PER_SUPERTILE_H10 = 0x00000044,
+SC_TILE_PER_SUPERTILE_H11 = 0x00000045,
+SC_TILE_PER_SUPERTILE_H12 = 0x00000046,
+SC_TILE_PER_SUPERTILE_H13 = 0x00000047,
+SC_TILE_PER_SUPERTILE_H14 = 0x00000048,
+SC_TILE_PER_SUPERTILE_H15 = 0x00000049,
+SC_TILE_PER_SUPERTILE_H16 = 0x0000004a,
+SC_TILE_PICKED_H1 = 0x0000004b,
+SC_TILE_PICKED_H2 = 0x0000004c,
+SC_TILE_PICKED_H3 = 0x0000004d,
+SC_TILE_PICKED_H4 = 0x0000004e,
+SC_QZ0_MULTI_GPU_TILE_DISCARD = 0x0000004f,
+SC_QZ1_MULTI_GPU_TILE_DISCARD = 0x00000050,
+SC_QZ2_MULTI_GPU_TILE_DISCARD = 0x00000051,
+SC_QZ3_MULTI_GPU_TILE_DISCARD = 0x00000052,
+SC_QZ0_TILE_COUNT = 0x00000053,
+SC_QZ1_TILE_COUNT = 0x00000054,
+SC_QZ2_TILE_COUNT = 0x00000055,
+SC_QZ3_TILE_COUNT = 0x00000056,
+SC_QZ0_TILE_COVERED_COUNT = 0x00000057,
+SC_QZ1_TILE_COVERED_COUNT = 0x00000058,
+SC_QZ2_TILE_COVERED_COUNT = 0x00000059,
+SC_QZ3_TILE_COVERED_COUNT = 0x0000005a,
+SC_QZ0_TILE_NOT_COVERED_COUNT = 0x0000005b,
+SC_QZ1_TILE_NOT_COVERED_COUNT = 0x0000005c,
+SC_QZ2_TILE_NOT_COVERED_COUNT = 0x0000005d,
+SC_QZ3_TILE_NOT_COVERED_COUNT = 0x0000005e,
+SC_QZ0_QUAD_PER_TILE_H0 = 0x0000005f,
+SC_QZ0_QUAD_PER_TILE_H1 = 0x00000060,
+SC_QZ0_QUAD_PER_TILE_H2 = 0x00000061,
+SC_QZ0_QUAD_PER_TILE_H3 = 0x00000062,
+SC_QZ0_QUAD_PER_TILE_H4 = 0x00000063,
+SC_QZ0_QUAD_PER_TILE_H5 = 0x00000064,
+SC_QZ0_QUAD_PER_TILE_H6 = 0x00000065,
+SC_QZ0_QUAD_PER_TILE_H7 = 0x00000066,
+SC_QZ0_QUAD_PER_TILE_H8 = 0x00000067,
+SC_QZ0_QUAD_PER_TILE_H9 = 0x00000068,
+SC_QZ0_QUAD_PER_TILE_H10 = 0x00000069,
+SC_QZ0_QUAD_PER_TILE_H11 = 0x0000006a,
+SC_QZ0_QUAD_PER_TILE_H12 = 0x0000006b,
+SC_QZ0_QUAD_PER_TILE_H13 = 0x0000006c,
+SC_QZ0_QUAD_PER_TILE_H14 = 0x0000006d,
+SC_QZ0_QUAD_PER_TILE_H15 = 0x0000006e,
+SC_QZ0_QUAD_PER_TILE_H16 = 0x0000006f,
+SC_QZ1_QUAD_PER_TILE_H0 = 0x00000070,
+SC_QZ1_QUAD_PER_TILE_H1 = 0x00000071,
+SC_QZ1_QUAD_PER_TILE_H2 = 0x00000072,
+SC_QZ1_QUAD_PER_TILE_H3 = 0x00000073,
+SC_QZ1_QUAD_PER_TILE_H4 = 0x00000074,
+SC_QZ1_QUAD_PER_TILE_H5 = 0x00000075,
+SC_QZ1_QUAD_PER_TILE_H6 = 0x00000076,
+SC_QZ1_QUAD_PER_TILE_H7 = 0x00000077,
+SC_QZ1_QUAD_PER_TILE_H8 = 0x00000078,
+SC_QZ1_QUAD_PER_TILE_H9 = 0x00000079,
+SC_QZ1_QUAD_PER_TILE_H10 = 0x0000007a,
+SC_QZ1_QUAD_PER_TILE_H11 = 0x0000007b,
+SC_QZ1_QUAD_PER_TILE_H12 = 0x0000007c,
+SC_QZ1_QUAD_PER_TILE_H13 = 0x0000007d,
+SC_QZ1_QUAD_PER_TILE_H14 = 0x0000007e,
+SC_QZ1_QUAD_PER_TILE_H15 = 0x0000007f,
+SC_QZ1_QUAD_PER_TILE_H16 = 0x00000080,
+SC_QZ2_QUAD_PER_TILE_H0 = 0x00000081,
+SC_QZ2_QUAD_PER_TILE_H1 = 0x00000082,
+SC_QZ2_QUAD_PER_TILE_H2 = 0x00000083,
+SC_QZ2_QUAD_PER_TILE_H3 = 0x00000084,
+SC_QZ2_QUAD_PER_TILE_H4 = 0x00000085,
+SC_QZ2_QUAD_PER_TILE_H5 = 0x00000086,
+SC_QZ2_QUAD_PER_TILE_H6 = 0x00000087,
+SC_QZ2_QUAD_PER_TILE_H7 = 0x00000088,
+SC_QZ2_QUAD_PER_TILE_H8 = 0x00000089,
+SC_QZ2_QUAD_PER_TILE_H9 = 0x0000008a,
+SC_QZ2_QUAD_PER_TILE_H10 = 0x0000008b,
+SC_QZ2_QUAD_PER_TILE_H11 = 0x0000008c,
+SC_QZ2_QUAD_PER_TILE_H12 = 0x0000008d,
+SC_QZ2_QUAD_PER_TILE_H13 = 0x0000008e,
+SC_QZ2_QUAD_PER_TILE_H14 = 0x0000008f,
+SC_QZ2_QUAD_PER_TILE_H15 = 0x00000090,
+SC_QZ2_QUAD_PER_TILE_H16 = 0x00000091,
+SC_QZ3_QUAD_PER_TILE_H0 = 0x00000092,
+SC_QZ3_QUAD_PER_TILE_H1 = 0x00000093,
+SC_QZ3_QUAD_PER_TILE_H2 = 0x00000094,
+SC_QZ3_QUAD_PER_TILE_H3 = 0x00000095,
+SC_QZ3_QUAD_PER_TILE_H4 = 0x00000096,
+SC_QZ3_QUAD_PER_TILE_H5 = 0x00000097,
+SC_QZ3_QUAD_PER_TILE_H6 = 0x00000098,
+SC_QZ3_QUAD_PER_TILE_H7 = 0x00000099,
+SC_QZ3_QUAD_PER_TILE_H8 = 0x0000009a,
+SC_QZ3_QUAD_PER_TILE_H9 = 0x0000009b,
+SC_QZ3_QUAD_PER_TILE_H10 = 0x0000009c,
+SC_QZ3_QUAD_PER_TILE_H11 = 0x0000009d,
+SC_QZ3_QUAD_PER_TILE_H12 = 0x0000009e,
+SC_QZ3_QUAD_PER_TILE_H13 = 0x0000009f,
+SC_QZ3_QUAD_PER_TILE_H14 = 0x000000a0,
+SC_QZ3_QUAD_PER_TILE_H15 = 0x000000a1,
+SC_QZ3_QUAD_PER_TILE_H16 = 0x000000a2,
+SC_QZ0_QUAD_COUNT = 0x000000a3,
+SC_QZ1_QUAD_COUNT = 0x000000a4,
+SC_QZ2_QUAD_COUNT = 0x000000a5,
+SC_QZ3_QUAD_COUNT = 0x000000a6,
+SC_P0_HIZ_TILE_COUNT = 0x000000a7,
+SC_P1_HIZ_TILE_COUNT = 0x000000a8,
+SC_P2_HIZ_TILE_COUNT = 0x000000a9,
+SC_P3_HIZ_TILE_COUNT = 0x000000aa,
+SC_P0_HIZ_QUAD_PER_TILE_H0 = 0x000000ab,
+SC_P0_HIZ_QUAD_PER_TILE_H1 = 0x000000ac,
+SC_P0_HIZ_QUAD_PER_TILE_H2 = 0x000000ad,
+SC_P0_HIZ_QUAD_PER_TILE_H3 = 0x000000ae,
+SC_P0_HIZ_QUAD_PER_TILE_H4 = 0x000000af,
+SC_P0_HIZ_QUAD_PER_TILE_H5 = 0x000000b0,
+SC_P0_HIZ_QUAD_PER_TILE_H6 = 0x000000b1,
+SC_P0_HIZ_QUAD_PER_TILE_H7 = 0x000000b2,
+SC_P0_HIZ_QUAD_PER_TILE_H8 = 0x000000b3,
+SC_P0_HIZ_QUAD_PER_TILE_H9 = 0x000000b4,
+SC_P0_HIZ_QUAD_PER_TILE_H10 = 0x000000b5,
+SC_P0_HIZ_QUAD_PER_TILE_H11 = 0x000000b6,
+SC_P0_HIZ_QUAD_PER_TILE_H12 = 0x000000b7,
+SC_P0_HIZ_QUAD_PER_TILE_H13 = 0x000000b8,
+SC_P0_HIZ_QUAD_PER_TILE_H14 = 0x000000b9,
+SC_P0_HIZ_QUAD_PER_TILE_H15 = 0x000000ba,
+SC_P0_HIZ_QUAD_PER_TILE_H16 = 0x000000bb,
+SC_P1_HIZ_QUAD_PER_TILE_H0 = 0x000000bc,
+SC_P1_HIZ_QUAD_PER_TILE_H1 = 0x000000bd,
+SC_P1_HIZ_QUAD_PER_TILE_H2 = 0x000000be,
+SC_P1_HIZ_QUAD_PER_TILE_H3 = 0x000000bf,
+SC_P1_HIZ_QUAD_PER_TILE_H4 = 0x000000c0,
+SC_P1_HIZ_QUAD_PER_TILE_H5 = 0x000000c1,
+SC_P1_HIZ_QUAD_PER_TILE_H6 = 0x000000c2,
+SC_P1_HIZ_QUAD_PER_TILE_H7 = 0x000000c3,
+SC_P1_HIZ_QUAD_PER_TILE_H8 = 0x000000c4,
+SC_P1_HIZ_QUAD_PER_TILE_H9 = 0x000000c5,
+SC_P1_HIZ_QUAD_PER_TILE_H10 = 0x000000c6,
+SC_P1_HIZ_QUAD_PER_TILE_H11 = 0x000000c7,
+SC_P1_HIZ_QUAD_PER_TILE_H12 = 0x000000c8,
+SC_P1_HIZ_QUAD_PER_TILE_H13 = 0x000000c9,
+SC_P1_HIZ_QUAD_PER_TILE_H14 = 0x000000ca,
+SC_P1_HIZ_QUAD_PER_TILE_H15 = 0x000000cb,
+SC_P1_HIZ_QUAD_PER_TILE_H16 = 0x000000cc,
+SC_P2_HIZ_QUAD_PER_TILE_H0 = 0x000000cd,
+SC_P2_HIZ_QUAD_PER_TILE_H1 = 0x000000ce,
+SC_P2_HIZ_QUAD_PER_TILE_H2 = 0x000000cf,
+SC_P2_HIZ_QUAD_PER_TILE_H3 = 0x000000d0,
+SC_P2_HIZ_QUAD_PER_TILE_H4 = 0x000000d1,
+SC_P2_HIZ_QUAD_PER_TILE_H5 = 0x000000d2,
+SC_P2_HIZ_QUAD_PER_TILE_H6 = 0x000000d3,
+SC_P2_HIZ_QUAD_PER_TILE_H7 = 0x000000d4,
+SC_P2_HIZ_QUAD_PER_TILE_H8 = 0x000000d5,
+SC_P2_HIZ_QUAD_PER_TILE_H9 = 0x000000d6,
+SC_P2_HIZ_QUAD_PER_TILE_H10 = 0x000000d7,
+SC_P2_HIZ_QUAD_PER_TILE_H11 = 0x000000d8,
+SC_P2_HIZ_QUAD_PER_TILE_H12 = 0x000000d9,
+SC_P2_HIZ_QUAD_PER_TILE_H13 = 0x000000da,
+SC_P2_HIZ_QUAD_PER_TILE_H14 = 0x000000db,
+SC_P2_HIZ_QUAD_PER_TILE_H15 = 0x000000dc,
+SC_P2_HIZ_QUAD_PER_TILE_H16 = 0x000000dd,
+SC_P3_HIZ_QUAD_PER_TILE_H0 = 0x000000de,
+SC_P3_HIZ_QUAD_PER_TILE_H1 = 0x000000df,
+SC_P3_HIZ_QUAD_PER_TILE_H2 = 0x000000e0,
+SC_P3_HIZ_QUAD_PER_TILE_H3 = 0x000000e1,
+SC_P3_HIZ_QUAD_PER_TILE_H4 = 0x000000e2,
+SC_P3_HIZ_QUAD_PER_TILE_H5 = 0x000000e3,
+SC_P3_HIZ_QUAD_PER_TILE_H6 = 0x000000e4,
+SC_P3_HIZ_QUAD_PER_TILE_H7 = 0x000000e5,
+SC_P3_HIZ_QUAD_PER_TILE_H8 = 0x000000e6,
+SC_P3_HIZ_QUAD_PER_TILE_H9 = 0x000000e7,
+SC_P3_HIZ_QUAD_PER_TILE_H10 = 0x000000e8,
+SC_P3_HIZ_QUAD_PER_TILE_H11 = 0x000000e9,
+SC_P3_HIZ_QUAD_PER_TILE_H12 = 0x000000ea,
+SC_P3_HIZ_QUAD_PER_TILE_H13 = 0x000000eb,
+SC_P3_HIZ_QUAD_PER_TILE_H14 = 0x000000ec,
+SC_P3_HIZ_QUAD_PER_TILE_H15 = 0x000000ed,
+SC_P3_HIZ_QUAD_PER_TILE_H16 = 0x000000ee,
+SC_P0_HIZ_QUAD_COUNT = 0x000000ef,
+SC_P1_HIZ_QUAD_COUNT = 0x000000f0,
+SC_P2_HIZ_QUAD_COUNT = 0x000000f1,
+SC_P3_HIZ_QUAD_COUNT = 0x000000f2,
+SC_P0_DETAIL_QUAD_COUNT = 0x000000f3,
+SC_P1_DETAIL_QUAD_COUNT = 0x000000f4,
+SC_P2_DETAIL_QUAD_COUNT = 0x000000f5,
+SC_P3_DETAIL_QUAD_COUNT = 0x000000f6,
+SC_P0_DETAIL_QUAD_WITH_1_PIX = 0x000000f7,
+SC_P0_DETAIL_QUAD_WITH_2_PIX = 0x000000f8,
+SC_P0_DETAIL_QUAD_WITH_3_PIX = 0x000000f9,
+SC_P0_DETAIL_QUAD_WITH_4_PIX = 0x000000fa,
+SC_P1_DETAIL_QUAD_WITH_1_PIX = 0x000000fb,
+SC_P1_DETAIL_QUAD_WITH_2_PIX = 0x000000fc,
+SC_P1_DETAIL_QUAD_WITH_3_PIX = 0x000000fd,
+SC_P1_DETAIL_QUAD_WITH_4_PIX = 0x000000fe,
+SC_P2_DETAIL_QUAD_WITH_1_PIX = 0x000000ff,
+SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x00000100,
+SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x00000101,
+SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x00000102,
+SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x00000103,
+SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x00000104,
+SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x00000105,
+SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x00000106,
+SC_EARLYZ_QUAD_COUNT = 0x00000107,
+SC_EARLYZ_QUAD_WITH_1_PIX = 0x00000108,
+SC_EARLYZ_QUAD_WITH_2_PIX = 0x00000109,
+SC_EARLYZ_QUAD_WITH_3_PIX = 0x0000010a,
+SC_EARLYZ_QUAD_WITH_4_PIX = 0x0000010b,
+SC_PKR_QUAD_PER_ROW_H1 = 0x0000010c,
+SC_PKR_QUAD_PER_ROW_H2 = 0x0000010d,
+SC_PKR_4X2_QUAD_SPLIT = 0x0000010e,
+SC_PKR_4X2_FILL_QUAD = 0x0000010f,
+SC_PKR_END_OF_VECTOR = 0x00000110,
+SC_PKR_CONTROL_XFER = 0x00000111,
+SC_PKR_DBHANG_FORCE_EOV = 0x00000112,
+SC_REG_SCLK_BUSY = 0x00000113,
+SC_GRP0_DYN_SCLK_BUSY = 0x00000114,
+SC_GRP1_DYN_SCLK_BUSY = 0x00000115,
+SC_GRP2_DYN_SCLK_BUSY = 0x00000116,
+SC_GRP3_DYN_SCLK_BUSY = 0x00000117,
+SC_GRP4_DYN_SCLK_BUSY = 0x00000118,
+SC_PA0_SC_DATA_FIFO_RD = 0x00000119,
+SC_PA0_SC_DATA_FIFO_WE = 0x0000011a,
+SC_PA1_SC_DATA_FIFO_RD = 0x0000011b,
+SC_PA1_SC_DATA_FIFO_WE = 0x0000011c,
+SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x0000011d,
+SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000011e,
+SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000011f,
+SC_PS_ARB_STALLED_FROM_BELOW = 0x00000120,
+SC_PS_ARB_STARVED_FROM_ABOVE = 0x00000121,
+SC_PS_ARB_SC_BUSY = 0x00000122,
+SC_PS_ARB_PA_SC_BUSY = 0x00000123,
+SC_PA2_SC_DATA_FIFO_RD = 0x00000124,
+SC_PA2_SC_DATA_FIFO_WE = 0x00000125,
+SC_PA3_SC_DATA_FIFO_RD = 0x00000126,
+SC_PA3_SC_DATA_FIFO_WE = 0x00000127,
+SC_PA_SC_DEALLOC_0_0_WE = 0x00000128,
+SC_PA_SC_DEALLOC_0_1_WE = 0x00000129,
+SC_PA_SC_DEALLOC_1_0_WE = 0x0000012a,
+SC_PA_SC_DEALLOC_1_1_WE = 0x0000012b,
+SC_PA_SC_DEALLOC_2_0_WE = 0x0000012c,
+SC_PA_SC_DEALLOC_2_1_WE = 0x0000012d,
+SC_PA_SC_DEALLOC_3_0_WE = 0x0000012e,
+SC_PA_SC_DEALLOC_3_1_WE = 0x0000012f,
+SC_PA0_SC_EOP_WE = 0x00000130,
+SC_PA0_SC_EOPG_WE = 0x00000131,
+SC_PA0_SC_EVENT_WE = 0x00000132,
+SC_PA1_SC_EOP_WE = 0x00000133,
+SC_PA1_SC_EOPG_WE = 0x00000134,
+SC_PA1_SC_EVENT_WE = 0x00000135,
+SC_PA2_SC_EOP_WE = 0x00000136,
+SC_PA2_SC_EOPG_WE = 0x00000137,
+SC_PA2_SC_EVENT_WE = 0x00000138,
+SC_PA3_SC_EOP_WE = 0x00000139,
+SC_PA3_SC_EOPG_WE = 0x0000013a,
+SC_PA3_SC_EVENT_WE = 0x0000013b,
+SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x0000013c,
+SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 0x0000013d,
+SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 0x0000013e,
+SC_PS_ARB_EOP_POP_SYNC_POP = 0x0000013f,
+SC_PS_ARB_EVENT_SYNC_POP = 0x00000140,
+SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 0x00000141,
+SC_PA0_SC_FPOV_WE = 0x00000142,
+SC_PA1_SC_FPOV_WE = 0x00000143,
+SC_PA2_SC_FPOV_WE = 0x00000144,
+SC_PA3_SC_FPOV_WE = 0x00000145,
+SC_PA0_SC_LPOV_WE = 0x00000146,
+SC_PA1_SC_LPOV_WE = 0x00000147,
+SC_PA2_SC_LPOV_WE = 0x00000148,
+SC_PA3_SC_LPOV_WE = 0x00000149,
+SC_SC_SPI_DEALLOC_0_0 = 0x0000014a,
+SC_SC_SPI_DEALLOC_0_1 = 0x0000014b,
+SC_SC_SPI_DEALLOC_0_2 = 0x0000014c,
+SC_SC_SPI_DEALLOC_1_0 = 0x0000014d,
+SC_SC_SPI_DEALLOC_1_1 = 0x0000014e,
+SC_SC_SPI_DEALLOC_1_2 = 0x0000014f,
+SC_SC_SPI_DEALLOC_2_0 = 0x00000150,
+SC_SC_SPI_DEALLOC_2_1 = 0x00000151,
+SC_SC_SPI_DEALLOC_2_2 = 0x00000152,
+SC_SC_SPI_DEALLOC_3_0 = 0x00000153,
+SC_SC_SPI_DEALLOC_3_1 = 0x00000154,
+SC_SC_SPI_DEALLOC_3_2 = 0x00000155,
+SC_SC_SPI_FPOV_0 = 0x00000156,
+SC_SC_SPI_FPOV_1 = 0x00000157,
+SC_SC_SPI_FPOV_2 = 0x00000158,
+SC_SC_SPI_FPOV_3 = 0x00000159,
+SC_SC_SPI_EVENT = 0x0000015a,
+SC_PS_TS_EVENT_FIFO_PUSH = 0x0000015b,
+SC_PS_TS_EVENT_FIFO_POP = 0x0000015c,
+SC_PS_CTX_DONE_FIFO_PUSH = 0x0000015d,
+SC_PS_CTX_DONE_FIFO_POP = 0x0000015e,
+SC_MULTICYCLE_BUBBLE_FREEZE = 0x0000015f,
+SC_EOP_SYNC_WINDOW = 0x00000160,
+SC_PA0_SC_NULL_WE = 0x00000161,
+SC_PA0_SC_NULL_DEALLOC_WE = 0x00000162,
+SC_PA0_SC_DATA_FIFO_EOPG_RD = 0x00000163,
+SC_PA0_SC_DATA_FIFO_EOP_RD = 0x00000164,
+SC_PA0_SC_DEALLOC_0_RD = 0x00000165,
+SC_PA0_SC_DEALLOC_1_RD = 0x00000166,
+SC_PA1_SC_DATA_FIFO_EOPG_RD = 0x00000167,
+SC_PA1_SC_DATA_FIFO_EOP_RD = 0x00000168,
+SC_PA1_SC_DEALLOC_0_RD = 0x00000169,
+SC_PA1_SC_DEALLOC_1_RD = 0x0000016a,
+SC_PA1_SC_NULL_WE = 0x0000016b,
+SC_PA1_SC_NULL_DEALLOC_WE = 0x0000016c,
+SC_PA2_SC_DATA_FIFO_EOPG_RD = 0x0000016d,
+SC_PA2_SC_DATA_FIFO_EOP_RD = 0x0000016e,
+SC_PA2_SC_DEALLOC_0_RD = 0x0000016f,
+SC_PA2_SC_DEALLOC_1_RD = 0x00000170,
+SC_PA2_SC_NULL_WE = 0x00000171,
+SC_PA2_SC_NULL_DEALLOC_WE = 0x00000172,
+SC_PA3_SC_DATA_FIFO_EOPG_RD = 0x00000173,
+SC_PA3_SC_DATA_FIFO_EOP_RD = 0x00000174,
+SC_PA3_SC_DEALLOC_0_RD = 0x00000175,
+SC_PA3_SC_DEALLOC_1_RD = 0x00000176,
+SC_PA3_SC_NULL_WE = 0x00000177,
+SC_PA3_SC_NULL_DEALLOC_WE = 0x00000178,
+SC_PS_PA0_SC_FIFO_EMPTY = 0x00000179,
+SC_PS_PA0_SC_FIFO_FULL = 0x0000017a,
+SC_PA0_PS_DATA_SEND = 0x0000017b,
+SC_PS_PA1_SC_FIFO_EMPTY = 0x0000017c,
+SC_PS_PA1_SC_FIFO_FULL = 0x0000017d,
+SC_PA1_PS_DATA_SEND = 0x0000017e,
+SC_PS_PA2_SC_FIFO_EMPTY = 0x0000017f,
+SC_PS_PA2_SC_FIFO_FULL = 0x00000180,
+SC_PA2_PS_DATA_SEND = 0x00000181,
+SC_PS_PA3_SC_FIFO_EMPTY = 0x00000182,
+SC_PS_PA3_SC_FIFO_FULL = 0x00000183,
+SC_PA3_PS_DATA_SEND = 0x00000184,
+SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000185,
+SC_BUSY_CNT_NOT_ZERO = 0x00000186,
+SC_BM_BUSY = 0x00000187,
+SC_BACKEND_BUSY = 0x00000188,
+SC_SCF_SCB_INTERFACE_BUSY = 0x00000189,
+SC_SCB_BUSY = 0x0000018a,
+SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 0x0000018b,
+SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 0x0000018c,
+SC_PBB_BIN_HIST_NUM_PRIMS = 0x0000018d,
+SC_PBB_BATCH_HIST_NUM_PRIMS = 0x0000018e,
+SC_PBB_BIN_HIST_NUM_CONTEXTS = 0x0000018f,
+SC_PBB_BATCH_HIST_NUM_CONTEXTS = 0x00000190,
+SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 0x00000191,
+SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 0x00000192,
+SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 0x00000193,
+SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 0x00000194,
+SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 0x00000195,
+SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 0x00000196,
+SC_PBB_BUSY = 0x00000197,
+SC_PBB_BUSY_AND_RTR = 0x00000198,
+SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 0x00000199,
+SC_PBB_NUM_BINS = 0x0000019a,
+SC_PBB_END_OF_BIN = 0x0000019b,
+SC_PBB_END_OF_BATCH = 0x0000019c,
+SC_PBB_PRIMBIN_PROCESSED = 0x0000019d,
+SC_PBB_PRIM_ADDED_TO_BATCH = 0x0000019e,
+SC_PBB_NONBINNED_PRIM = 0x0000019f,
+SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 0x000001a0,
+SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 0x000001a1,
+SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 0x000001a2,
+SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 0x000001a3,
+SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 0x000001a4,
+SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 0x000001a5,
+SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 0x000001a6,
+SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 0x000001a7,
+SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 0x000001a8,
+SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 0x000001a9,
+SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 0x000001aa,
+SC_POPS_INTRA_WAVE_OVERLAPS = 0x000001ab,
+SC_POPS_FORCE_EOV = 0x000001ac,
+SC_PKR_QUAD_OVERLAP_NOT_FOUND_IN_WAVE_TABLE = 0x000001ad,
+SC_PKR_QUAD_OVERLAP_FOUND_IN_WAVE_TABLE = 0x000001ae,
+} SC_PERFCNT_SEL;
+
+/*
+ * SePairXsel enum
+ */
+
+typedef enum SePairXsel {
+RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x00000000,
+RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x00000001,
+RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x00000002,
+RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x00000003,
+RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE = 0x00000004,
+} SePairXsel;
+
+/*
+ * SePairYsel enum
+ */
+
+typedef enum SePairYsel {
+RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x00000000,
+RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x00000001,
+RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x00000002,
+RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x00000003,
+RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE = 0x00000004,
+} SePairYsel;
+
+/*
+ * SePairMap enum
+ */
+
+typedef enum SePairMap {
+RASTER_CONFIG_SE_PAIR_MAP_0 = 0x00000000,
+RASTER_CONFIG_SE_PAIR_MAP_1 = 0x00000001,
+RASTER_CONFIG_SE_PAIR_MAP_2 = 0x00000002,
+RASTER_CONFIG_SE_PAIR_MAP_3 = 0x00000003,
+} SePairMap;
+
+/*
+ * SeXsel enum
+ */
+
+typedef enum SeXsel {
+RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x00000000,
+RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x00000001,
+RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x00000002,
+RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x00000003,
+RASTER_CONFIG_SE_XSEL_128_WIDE_TILE = 0x00000004,
+} SeXsel;
+
+/*
+ * SeYsel enum
+ */
+
+typedef enum SeYsel {
+RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x00000000,
+RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x00000001,
+RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x00000002,
+RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x00000003,
+RASTER_CONFIG_SE_YSEL_128_WIDE_TILE = 0x00000004,
+} SeYsel;
+
+/*
+ * SeMap enum
+ */
+
+typedef enum SeMap {
+RASTER_CONFIG_SE_MAP_0 = 0x00000000,
+RASTER_CONFIG_SE_MAP_1 = 0x00000001,
+RASTER_CONFIG_SE_MAP_2 = 0x00000002,
+RASTER_CONFIG_SE_MAP_3 = 0x00000003,
+} SeMap;
+
+/*
+ * ScXsel enum
+ */
+
+typedef enum ScXsel {
+RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x00000000,
+RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x00000001,
+RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x00000002,
+RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x00000003,
+} ScXsel;
+
+/*
+ * ScYsel enum
+ */
+
+typedef enum ScYsel {
+RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x00000000,
+RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x00000001,
+RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x00000002,
+RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x00000003,
+} ScYsel;
+
+/*
+ * ScMap enum
+ */
+
+typedef enum ScMap {
+RASTER_CONFIG_SC_MAP_0 = 0x00000000,
+RASTER_CONFIG_SC_MAP_1 = 0x00000001,
+RASTER_CONFIG_SC_MAP_2 = 0x00000002,
+RASTER_CONFIG_SC_MAP_3 = 0x00000003,
+} ScMap;
+
+/*
+ * PkrXsel2 enum
+ */
+
+typedef enum PkrXsel2 {
+RASTER_CONFIG_PKR_XSEL2_0 = 0x00000000,
+RASTER_CONFIG_PKR_XSEL2_1 = 0x00000001,
+RASTER_CONFIG_PKR_XSEL2_2 = 0x00000002,
+RASTER_CONFIG_PKR_XSEL2_3 = 0x00000003,
+} PkrXsel2;
+
+/*
+ * PkrXsel enum
+ */
+
+typedef enum PkrXsel {
+RASTER_CONFIG_PKR_XSEL_0 = 0x00000000,
+RASTER_CONFIG_PKR_XSEL_1 = 0x00000001,
+RASTER_CONFIG_PKR_XSEL_2 = 0x00000002,
+RASTER_CONFIG_PKR_XSEL_3 = 0x00000003,
+} PkrXsel;
+
+/*
+ * PkrYsel enum
+ */
+
+typedef enum PkrYsel {
+RASTER_CONFIG_PKR_YSEL_0 = 0x00000000,
+RASTER_CONFIG_PKR_YSEL_1 = 0x00000001,
+RASTER_CONFIG_PKR_YSEL_2 = 0x00000002,
+RASTER_CONFIG_PKR_YSEL_3 = 0x00000003,
+} PkrYsel;
+
+/*
+ * PkrMap enum
+ */
+
+typedef enum PkrMap {
+RASTER_CONFIG_PKR_MAP_0 = 0x00000000,
+RASTER_CONFIG_PKR_MAP_1 = 0x00000001,
+RASTER_CONFIG_PKR_MAP_2 = 0x00000002,
+RASTER_CONFIG_PKR_MAP_3 = 0x00000003,
+} PkrMap;
+
+/*
+ * RbXsel enum
+ */
+
+typedef enum RbXsel {
+RASTER_CONFIG_RB_XSEL_0 = 0x00000000,
+RASTER_CONFIG_RB_XSEL_1 = 0x00000001,
+} RbXsel;
+
+/*
+ * RbYsel enum
+ */
+
+typedef enum RbYsel {
+RASTER_CONFIG_RB_YSEL_0 = 0x00000000,
+RASTER_CONFIG_RB_YSEL_1 = 0x00000001,
+} RbYsel;
+
+/*
+ * RbXsel2 enum
+ */
+
+typedef enum RbXsel2 {
+RASTER_CONFIG_RB_XSEL2_0 = 0x00000000,
+RASTER_CONFIG_RB_XSEL2_1 = 0x00000001,
+RASTER_CONFIG_RB_XSEL2_2 = 0x00000002,
+RASTER_CONFIG_RB_XSEL2_3 = 0x00000003,
+} RbXsel2;
+
+/*
+ * RbMap enum
+ */
+
+typedef enum RbMap {
+RASTER_CONFIG_RB_MAP_0 = 0x00000000,
+RASTER_CONFIG_RB_MAP_1 = 0x00000001,
+RASTER_CONFIG_RB_MAP_2 = 0x00000002,
+RASTER_CONFIG_RB_MAP_3 = 0x00000003,
+} RbMap;
+
+/*
+ * BinningMode enum
+ */
+
+typedef enum BinningMode {
+BINNING_ALLOWED = 0x00000000,
+FORCE_BINNING_ON = 0x00000001,
+DISABLE_BINNING_USE_NEW_SC = 0x00000002,
+DISABLE_BINNING_USE_LEGACY_SC = 0x00000003,
+} BinningMode;
+
+/*
+ * BinEventCntl enum
+ */
+
+typedef enum BinEventCntl {
+BINNER_BREAK_BATCH = 0x00000000,
+BINNER_PIPELINE = 0x00000001,
+BINNER_DROP_ASSERT = 0x00000002,
+} BinEventCntl;
+
+/*
+ * CovToShaderSel enum
+ */
+
+typedef enum CovToShaderSel {
+INPUT_COVERAGE = 0x00000000,
+INPUT_INNER_COVERAGE = 0x00000001,
+INPUT_DEPTH_COVERAGE = 0x00000002,
+RAW = 0x00000003,
+} CovToShaderSel;
+
+/*******************************************************
+ * RMI Enums
+ *******************************************************/
+
+/*
+ * RMIPerfSel enum
+ */
+
+typedef enum RMIPerfSel {
+RMI_PERF_SEL_NONE = 0x00000000,
+RMI_PERF_SEL_BUSY = 0x00000001,
+RMI_PERF_SEL_REG_CLK_VLD = 0x00000002,
+RMI_PERF_SEL_DYN_CLK_CMN_VLD = 0x00000003,
+RMI_PERF_SEL_DYN_CLK_RB_VLD = 0x00000004,
+RMI_PERF_SEL_DYN_CLK_PERF_VLD = 0x00000005,
+RMI_PERF_SEL_PERF_WINDOW = 0x00000006,
+RMI_PERF_SEL_EVENT_SEND = 0x00000007,
+RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0 = 0x00000008,
+RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1 = 0x00000009,
+RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2 = 0x0000000a,
+RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3 = 0x0000000b,
+RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4 = 0x0000000c,
+RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5 = 0x0000000d,
+RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6 = 0x0000000e,
+RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7 = 0x0000000f,
+RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8 = 0x00000010,
+RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9 = 0x00000011,
+RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10 = 0x00000012,
+RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11 = 0x00000013,
+RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12 = 0x00000014,
+RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13 = 0x00000015,
+RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14 = 0x00000016,
+RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15 = 0x00000017,
+RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL = 0x00000018,
+RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0 = 0x00000019,
+RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1 = 0x0000001a,
+RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2 = 0x0000001b,
+RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3 = 0x0000001c,
+RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4 = 0x0000001d,
+RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5 = 0x0000001e,
+RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6 = 0x0000001f,
+RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7 = 0x00000020,
+RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8 = 0x00000021,
+RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9 = 0x00000022,
+RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10 = 0x00000023,
+RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11 = 0x00000024,
+RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12 = 0x00000025,
+RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13 = 0x00000026,
+RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14 = 0x00000027,
+RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15 = 0x00000028,
+RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL = 0x00000029,
+RMI_PERF_SEL_UTCL1_TRANSLATION_MISS = 0x0000002a,
+RMI_PERF_SEL_UTCL1_PERMISSION_MISS = 0x0000002b,
+RMI_PERF_SEL_UTCL1_REQUEST = 0x0000002c,
+RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 0x0000002d,
+RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 0x0000002e,
+RMI_PERF_SEL_UTCL1_LFIFO_FULL = 0x0000002f,
+RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 0x00000030,
+RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x00000031,
+RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 0x00000032,
+RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL = 0x00000033,
+RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS = 0x00000034,
+RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 0x00000035,
+RMI_PERF_SEL_RB_RMI_WRREQ_BUSY = 0x00000036,
+RMI_PERF_SEL_RB_RMI_WRREQ_CID0 = 0x00000037,
+RMI_PERF_SEL_RB_RMI_WRREQ_CID1 = 0x00000038,
+RMI_PERF_SEL_RB_RMI_WRREQ_CID2 = 0x00000039,
+RMI_PERF_SEL_RB_RMI_WRREQ_CID3 = 0x0000003a,
+RMI_PERF_SEL_RB_RMI_WRREQ_CID4 = 0x0000003b,
+RMI_PERF_SEL_RB_RMI_WRREQ_CID5 = 0x0000003c,
+RMI_PERF_SEL_RB_RMI_WRREQ_CID6 = 0x0000003d,
+RMI_PERF_SEL_RB_RMI_WRREQ_CID7 = 0x0000003e,
+RMI_PERF_SEL_RB_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID = 0x0000003f,
+RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000040,
+RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 0x00000041,
+RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY = 0x00000042,
+RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID = 0x00000043,
+RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0 = 0x00000044,
+RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1 = 0x00000045,
+RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2 = 0x00000046,
+RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3 = 0x00000047,
+RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4 = 0x00000048,
+RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5 = 0x00000049,
+RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6 = 0x0000004a,
+RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7 = 0x0000004b,
+RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0 = 0x0000004c,
+RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1 = 0x0000004d,
+RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2 = 0x0000004e,
+RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3 = 0x0000004f,
+RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID = 0x00000050,
+RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 0x00000051,
+RMI_PERF_SEL_RB_RMI_RDREQ_BUSY = 0x00000052,
+RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0 = 0x00000053,
+RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1 = 0x00000054,
+RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2 = 0x00000055,
+RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3 = 0x00000056,
+RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4 = 0x00000057,
+RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5 = 0x00000058,
+RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6 = 0x00000059,
+RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7 = 0x0000005a,
+RMI_PERF_SEL_RB_RMI_RDREQ_CID0 = 0x0000005b,
+RMI_PERF_SEL_RB_RMI_RDREQ_CID1 = 0x0000005c,
+RMI_PERF_SEL_RB_RMI_RDREQ_CID2 = 0x0000005d,
+RMI_PERF_SEL_RB_RMI_RDREQ_CID3 = 0x0000005e,
+RMI_PERF_SEL_RB_RMI_RDREQ_CID4 = 0x0000005f,
+RMI_PERF_SEL_RB_RMI_RDREQ_CID5 = 0x00000060,
+RMI_PERF_SEL_RB_RMI_RDREQ_CID6 = 0x00000061,
+RMI_PERF_SEL_RB_RMI_RDREQ_CID7 = 0x00000062,
+RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 0x00000063,
+RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000064,
+RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 0x00000065,
+RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY = 0x00000066,
+RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 0x00000067,
+RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0 = 0x00000068,
+RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1 = 0x00000069,
+RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2 = 0x0000006a,
+RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3 = 0x0000006b,
+RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4 = 0x0000006c,
+RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5 = 0x0000006d,
+RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6 = 0x0000006e,
+RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7 = 0x0000006f,
+RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 0x00000070,
+RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 0x00000071,
+RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 0x00000072,
+RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 0x00000073,
+RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID = 0x00000074,
+RMI_PERF_SEL_RMI_TC_REQ_BUSY = 0x00000075,
+RMI_PERF_SEL_RMI_TC_WRREQ_CID0 = 0x00000076,
+RMI_PERF_SEL_RMI_TC_WRREQ_CID1 = 0x00000077,
+RMI_PERF_SEL_RMI_TC_WRREQ_CID2 = 0x00000078,
+RMI_PERF_SEL_RMI_TC_WRREQ_CID3 = 0x00000079,
+RMI_PERF_SEL_RMI_TC_WRREQ_CID4 = 0x0000007a,
+RMI_PERF_SEL_RMI_TC_WRREQ_CID5 = 0x0000007b,
+RMI_PERF_SEL_RMI_TC_WRREQ_CID6 = 0x0000007c,
+RMI_PERF_SEL_RMI_TC_WRREQ_CID7 = 0x0000007d,
+RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 0x0000007e,
+RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID = 0x0000007f,
+RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID = 0x00000080,
+RMI_PERF_SEL_RMI_TC_RDREQ_CID0 = 0x00000081,
+RMI_PERF_SEL_RMI_TC_RDREQ_CID1 = 0x00000082,
+RMI_PERF_SEL_RMI_TC_RDREQ_CID2 = 0x00000083,
+RMI_PERF_SEL_RMI_TC_RDREQ_CID3 = 0x00000084,
+RMI_PERF_SEL_RMI_TC_RDREQ_CID4 = 0x00000085,
+RMI_PERF_SEL_RMI_TC_RDREQ_CID5 = 0x00000086,
+RMI_PERF_SEL_RMI_TC_RDREQ_CID6 = 0x00000087,
+RMI_PERF_SEL_RMI_TC_RDREQ_CID7 = 0x00000088,
+RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 0x00000089,
+RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID = 0x0000008a,
+RMI_PERF_SEL_UTCL1_BUSY = 0x0000008b,
+RMI_PERF_SEL_RMI_UTC_REQ = 0x0000008c,
+RMI_PERF_SEL_RMI_UTC_BUSY = 0x0000008d,
+RMI_PERF_SEL_UTCL1_UTCL2_REQ = 0x0000008e,
+RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY = 0x0000008f,
+RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT = 0x00000090,
+RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT = 0x00000091,
+RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT = 0x00000092,
+RMI_PERF_SEL_XNACK_FIFO_NUM_USED = 0x00000093,
+RMI_PERF_SEL_LAT_FIFO_NUM_USED = 0x00000094,
+RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ = 0x00000095,
+RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ = 0x00000096,
+RMI_PERF_SEL_XNACK_FIFO_FULL = 0x00000097,
+RMI_PERF_SEL_XNACK_FIFO_BUSY = 0x00000098,
+RMI_PERF_SEL_LAT_FIFO_FULL = 0x00000099,
+RMI_PERF_SEL_SKID_FIFO_DEPTH = 0x0000009a,
+RMI_PERF_SEL_TCIW_INFLIGHT_COUNT = 0x0000009b,
+RMI_PERF_SEL_PRT_FIFO_NUM_USED = 0x0000009c,
+RMI_PERF_SEL_PRT_FIFO_REQ = 0x0000009d,
+RMI_PERF_SEL_PRT_FIFO_BUSY = 0x0000009e,
+RMI_PERF_SEL_TCIW_REQ = 0x0000009f,
+RMI_PERF_SEL_TCIW_BUSY = 0x000000a0,
+RMI_PERF_SEL_SKID_FIFO_REQ = 0x000000a1,
+RMI_PERF_SEL_SKID_FIFO_BUSY = 0x000000a2,
+RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0 = 0x000000a3,
+RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1 = 0x000000a4,
+RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2 = 0x000000a5,
+RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3 = 0x000000a6,
+RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR = 0x000000a7,
+RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR = 0x000000a8,
+RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB = 0x000000a9,
+RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB = 0x000000aa,
+RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 0x000000ab,
+RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 0x000000ac,
+RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 0x000000ad,
+RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 0x000000ae,
+RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR = 0x000000af,
+RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR = 0x000000b0,
+RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB = 0x000000b1,
+RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB = 0x000000b2,
+RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR = 0x000000b3,
+RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR = 0x000000b4,
+RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB = 0x000000b5,
+RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB = 0x000000b6,
+RMI_PERF_SEL_POP_DEMUX_RTS_RTR = 0x000000b7,
+RMI_PERF_SEL_POP_DEMUX_RTSB_RTR = 0x000000b8,
+RMI_PERF_SEL_POP_DEMUX_RTS_RTRB = 0x000000b9,
+RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB = 0x000000ba,
+RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR = 0x000000bb,
+RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR = 0x000000bc,
+RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB = 0x000000bd,
+RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB = 0x000000be,
+RMI_PERF_SEL_UTC_POP_RTS_RTR = 0x000000bf,
+RMI_PERF_SEL_UTC_POP_RTSB_RTR = 0x000000c0,
+RMI_PERF_SEL_UTC_POP_RTS_RTRB = 0x000000c1,
+RMI_PERF_SEL_UTC_POP_RTSB_RTRB = 0x000000c2,
+RMI_PERF_SEL_POP_XNACK_RTS_RTR = 0x000000c3,
+RMI_PERF_SEL_POP_XNACK_RTSB_RTR = 0x000000c4,
+RMI_PERF_SEL_POP_XNACK_RTS_RTRB = 0x000000c5,
+RMI_PERF_SEL_POP_XNACK_RTSB_RTRB = 0x000000c6,
+RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR = 0x000000c7,
+RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR = 0x000000c8,
+RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB = 0x000000c9,
+RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB = 0x000000ca,
+RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR = 0x000000cb,
+RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR = 0x000000cc,
+RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB = 0x000000cd,
+RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB = 0x000000ce,
+RMI_PERF_SEL_SKID_FIFO_IN_RTS = 0x000000cf,
+RMI_PERF_SEL_SKID_FIFO_IN_RTSB = 0x000000d0,
+RMI_PERF_SEL_SKID_FIFO_OUT_RTS = 0x000000d1,
+RMI_PERF_SEL_SKID_FIFO_OUT_RTSB = 0x000000d2,
+RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR = 0x000000d3,
+RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR = 0x000000d4,
+RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR = 0x000000d5,
+RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR = 0x000000d6,
+RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR = 0x000000d7,
+RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR = 0x000000d8,
+RMI_PERF_SEL_REORDER_FIFO_REQ = 0x000000d9,
+RMI_PERF_SEL_REORDER_FIFO_BUSY = 0x000000da,
+RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID = 0x000000db,
+RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0 = 0x000000dc,
+RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1 = 0x000000dd,
+RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2 = 0x000000de,
+RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3 = 0x000000df,
+RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4 = 0x000000e0,
+RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5 = 0x000000e1,
+RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6 = 0x000000e2,
+RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7 = 0x000000e3,
+RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0 = 0x000000e4,
+RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1 = 0x000000e5,
+RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2 = 0x000000e6,
+RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3 = 0x000000e7,
+} RMIPerfSel;
+
+/*******************************************************
+ * IH Enums
+ *******************************************************/
+
+/*
+ * IH_PERF_SEL enum
+ */
+
+typedef enum IH_PERF_SEL {
+IH_PERF_SEL_CYCLE = 0x00000000,
+IH_PERF_SEL_IDLE = 0x00000001,
+IH_PERF_SEL_INPUT_IDLE = 0x00000002,
+IH_PERF_SEL_BUFFER_IDLE = 0x00000003,
+IH_PERF_SEL_RB0_FULL = 0x00000004,
+IH_PERF_SEL_RB0_OVERFLOW = 0x00000005,
+IH_PERF_SEL_RB0_WPTR_WRITEBACK = 0x00000006,
+IH_PERF_SEL_RB0_WPTR_WRAP = 0x00000007,
+IH_PERF_SEL_RB0_RPTR_WRAP = 0x00000008,
+IH_PERF_SEL_MC_WR_IDLE = 0x00000009,
+IH_PERF_SEL_MC_WR_COUNT = 0x0000000a,
+IH_PERF_SEL_MC_WR_STALL = 0x0000000b,
+IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x0000000c,
+IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x0000000d,
+IH_PERF_SEL_BIF_LINE0_RISING = 0x0000000e,
+IH_PERF_SEL_BIF_LINE0_FALLING = 0x0000000f,
+IH_PERF_SEL_RB1_FULL = 0x00000010,
+IH_PERF_SEL_RB1_OVERFLOW = 0x00000011,
+Reserved18 = 0x00000012,
+IH_PERF_SEL_RB1_WPTR_WRAP = 0x00000013,
+IH_PERF_SEL_RB1_RPTR_WRAP = 0x00000014,
+IH_PERF_SEL_RB2_FULL = 0x00000015,
+IH_PERF_SEL_RB2_OVERFLOW = 0x00000016,
+Reserved23 = 0x00000017,
+IH_PERF_SEL_RB2_WPTR_WRAP = 0x00000018,
+IH_PERF_SEL_RB2_RPTR_WRAP = 0x00000019,
+Reserved26 = 0x0000001a,
+Reserved27 = 0x0000001b,
+Reserved28 = 0x0000001c,
+Reserved29 = 0x0000001d,
+IH_PERF_SEL_RB0_FULL_VF0 = 0x0000001e,
+IH_PERF_SEL_RB0_FULL_VF1 = 0x0000001f,
+IH_PERF_SEL_RB0_FULL_VF2 = 0x00000020,
+IH_PERF_SEL_RB0_FULL_VF3 = 0x00000021,
+IH_PERF_SEL_RB0_FULL_VF4 = 0x00000022,
+IH_PERF_SEL_RB0_FULL_VF5 = 0x00000023,
+IH_PERF_SEL_RB0_FULL_VF6 = 0x00000024,
+IH_PERF_SEL_RB0_FULL_VF7 = 0x00000025,
+IH_PERF_SEL_RB0_FULL_VF8 = 0x00000026,
+IH_PERF_SEL_RB0_FULL_VF9 = 0x00000027,
+IH_PERF_SEL_RB0_FULL_VF10 = 0x00000028,
+IH_PERF_SEL_RB0_FULL_VF11 = 0x00000029,
+IH_PERF_SEL_RB0_FULL_VF12 = 0x0000002a,
+IH_PERF_SEL_RB0_FULL_VF13 = 0x0000002b,
+IH_PERF_SEL_RB0_FULL_VF14 = 0x0000002c,
+IH_PERF_SEL_RB0_FULL_VF15 = 0x0000002d,
+IH_PERF_SEL_RB0_OVERFLOW_VF0 = 0x0000002e,
+IH_PERF_SEL_RB0_OVERFLOW_VF1 = 0x0000002f,
+IH_PERF_SEL_RB0_OVERFLOW_VF2 = 0x00000030,
+IH_PERF_SEL_RB0_OVERFLOW_VF3 = 0x00000031,
+IH_PERF_SEL_RB0_OVERFLOW_VF4 = 0x00000032,
+IH_PERF_SEL_RB0_OVERFLOW_VF5 = 0x00000033,
+IH_PERF_SEL_RB0_OVERFLOW_VF6 = 0x00000034,
+IH_PERF_SEL_RB0_OVERFLOW_VF7 = 0x00000035,
+IH_PERF_SEL_RB0_OVERFLOW_VF8 = 0x00000036,
+IH_PERF_SEL_RB0_OVERFLOW_VF9 = 0x00000037,
+IH_PERF_SEL_RB0_OVERFLOW_VF10 = 0x00000038,
+IH_PERF_SEL_RB0_OVERFLOW_VF11 = 0x00000039,
+IH_PERF_SEL_RB0_OVERFLOW_VF12 = 0x0000003a,
+IH_PERF_SEL_RB0_OVERFLOW_VF13 = 0x0000003b,
+IH_PERF_SEL_RB0_OVERFLOW_VF14 = 0x0000003c,
+IH_PERF_SEL_RB0_OVERFLOW_VF15 = 0x0000003d,
+IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 0x0000003e,
+IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 0x0000003f,
+IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 0x00000040,
+IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 0x00000041,
+IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 0x00000042,
+IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 0x00000043,
+IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 0x00000044,
+IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 0x00000045,
+IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 0x00000046,
+IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 0x00000047,
+IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 0x00000048,
+IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 0x00000049,
+IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 0x0000004a,
+IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 0x0000004b,
+IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 0x0000004c,
+IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 0x0000004d,
+IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 0x0000004e,
+IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 0x0000004f,
+IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 0x00000050,
+IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 0x00000051,
+IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 0x00000052,
+IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 0x00000053,
+IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 0x00000054,
+IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 0x00000055,
+IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 0x00000056,
+IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 0x00000057,
+IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 0x00000058,
+IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 0x00000059,
+IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 0x0000005a,
+IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 0x0000005b,
+IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 0x0000005c,
+IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 0x0000005d,
+IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 0x0000005e,
+IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 0x0000005f,
+IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 0x00000060,
+IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 0x00000061,
+IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 0x00000062,
+IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 0x00000063,
+IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 0x00000064,
+IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 0x00000065,
+IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 0x00000066,
+IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 0x00000067,
+IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 0x00000068,
+IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 0x00000069,
+IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 0x0000006a,
+IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 0x0000006b,
+IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 0x0000006c,
+IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 0x0000006d,
+IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 0x0000006e,
+IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 0x0000006f,
+IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 0x00000070,
+IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 0x00000071,
+IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 0x00000072,
+IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 0x00000073,
+IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 0x00000074,
+IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 0x00000075,
+IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 0x00000076,
+IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 0x00000077,
+IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 0x00000078,
+IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 0x00000079,
+IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 0x0000007a,
+IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 0x0000007b,
+IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 0x0000007c,
+IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 0x0000007d,
+IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 0x0000007e,
+IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 0x0000007f,
+IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 0x00000080,
+IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 0x00000081,
+IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 0x00000082,
+IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 0x00000083,
+IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 0x00000084,
+IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 0x00000085,
+IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 0x00000086,
+IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 0x00000087,
+IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 0x00000088,
+IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 0x00000089,
+IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 0x0000008a,
+IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 0x0000008b,
+IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 0x0000008c,
+IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 0x0000008d,
+Reserved142 = 0x0000008e,
+Reserved143 = 0x0000008f,
+Reserved144 = 0x00000090,
+Reserved145 = 0x00000091,
+Reserved146 = 0x00000092,
+Reserved147 = 0x00000093,
+Reserved148 = 0x00000094,
+Reserved149 = 0x00000095,
+IH_PERF_SEL_CLIENT0_INT = 0x00000096,
+IH_PERF_SEL_CLIENT1_INT = 0x00000097,
+IH_PERF_SEL_CLIENT2_INT = 0x00000098,
+IH_PERF_SEL_CLIENT3_INT = 0x00000099,
+IH_PERF_SEL_CLIENT4_INT = 0x0000009a,
+IH_PERF_SEL_CLIENT5_INT = 0x0000009b,
+IH_PERF_SEL_CLIENT6_INT = 0x0000009c,
+IH_PERF_SEL_CLIENT7_INT = 0x0000009d,
+IH_PERF_SEL_CLIENT8_INT = 0x0000009e,
+IH_PERF_SEL_CLIENT9_INT = 0x0000009f,
+IH_PERF_SEL_CLIENT10_INT = 0x000000a0,
+IH_PERF_SEL_CLIENT11_INT = 0x000000a1,
+IH_PERF_SEL_CLIENT12_INT = 0x000000a2,
+IH_PERF_SEL_CLIENT13_INT = 0x000000a3,
+IH_PERF_SEL_CLIENT14_INT = 0x000000a4,
+IH_PERF_SEL_CLIENT15_INT = 0x000000a5,
+IH_PERF_SEL_CLIENT16_INT = 0x000000a6,
+IH_PERF_SEL_CLIENT17_INT = 0x000000a7,
+IH_PERF_SEL_CLIENT18_INT = 0x000000a8,
+IH_PERF_SEL_CLIENT19_INT = 0x000000a9,
+IH_PERF_SEL_CLIENT20_INT = 0x000000aa,
+IH_PERF_SEL_CLIENT21_INT = 0x000000ab,
+IH_PERF_SEL_CLIENT22_INT = 0x000000ac,
+IH_PERF_SEL_CLIENT23_INT = 0x000000ad,
+IH_PERF_SEL_CLIENT24_INT = 0x000000ae,
+IH_PERF_SEL_CLIENT25_INT = 0x000000af,
+IH_PERF_SEL_CLIENT26_INT = 0x000000b0,
+IH_PERF_SEL_CLIENT27_INT = 0x000000b1,
+IH_PERF_SEL_CLIENT28_INT = 0x000000b2,
+IH_PERF_SEL_CLIENT29_INT = 0x000000b3,
+IH_PERF_SEL_CLIENT30_INT = 0x000000b4,
+IH_PERF_SEL_CLIENT31_INT = 0x000000b5,
+Reserved182 = 0x000000b6,
+Reserved183 = 0x000000b7,
+Reserved184 = 0x000000b8,
+Reserved185 = 0x000000b9,
+Reserved186 = 0x000000ba,
+Reserved187 = 0x000000bb,
+Reserved188 = 0x000000bc,
+Reserved189 = 0x000000bd,
+Reserved190 = 0x000000be,
+Reserved191 = 0x000000bf,
+Reserved192 = 0x000000c0,
+Reserved193 = 0x000000c1,
+Reserved194 = 0x000000c2,
+Reserved195 = 0x000000c3,
+Reserved196 = 0x000000c4,
+Reserved197 = 0x000000c5,
+Reserved198 = 0x000000c6,
+Reserved199 = 0x000000c7,
+Reserved200 = 0x000000c8,
+Reserved201 = 0x000000c9,
+Reserved202 = 0x000000ca,
+Reserved203 = 0x000000cb,
+Reserved204 = 0x000000cc,
+Reserved205 = 0x000000cd,
+Reserved206 = 0x000000ce,
+Reserved207 = 0x000000cf,
+Reserved208 = 0x000000d0,
+Reserved209 = 0x000000d1,
+Reserved210 = 0x000000d2,
+Reserved211 = 0x000000d3,
+Reserved212 = 0x000000d4,
+Reserved213 = 0x000000d5,
+Reserved214 = 0x000000d6,
+Reserved215 = 0x000000d7,
+Reserved216 = 0x000000d8,
+Reserved217 = 0x000000d9,
+Reserved218 = 0x000000da,
+Reserved219 = 0x000000db,
+IH_PERF_SEL_RB1_FULL_VF0 = 0x000000dc,
+IH_PERF_SEL_RB1_FULL_VF1 = 0x000000dd,
+IH_PERF_SEL_RB1_FULL_VF2 = 0x000000de,
+IH_PERF_SEL_RB1_FULL_VF3 = 0x000000df,
+IH_PERF_SEL_RB1_FULL_VF4 = 0x000000e0,
+IH_PERF_SEL_RB1_FULL_VF5 = 0x000000e1,
+IH_PERF_SEL_RB1_FULL_VF6 = 0x000000e2,
+IH_PERF_SEL_RB1_FULL_VF7 = 0x000000e3,
+IH_PERF_SEL_RB1_FULL_VF8 = 0x000000e4,
+IH_PERF_SEL_RB1_FULL_VF9 = 0x000000e5,
+IH_PERF_SEL_RB1_FULL_VF10 = 0x000000e6,
+IH_PERF_SEL_RB1_FULL_VF11 = 0x000000e7,
+IH_PERF_SEL_RB1_FULL_VF12 = 0x000000e8,
+IH_PERF_SEL_RB1_FULL_VF13 = 0x000000e9,
+IH_PERF_SEL_RB1_FULL_VF14 = 0x000000ea,
+IH_PERF_SEL_RB1_FULL_VF15 = 0x000000eb,
+IH_PERF_SEL_RB1_OVERFLOW_VF0 = 0x000000ec,
+IH_PERF_SEL_RB1_OVERFLOW_VF1 = 0x000000ed,
+IH_PERF_SEL_RB1_OVERFLOW_VF2 = 0x000000ee,
+IH_PERF_SEL_RB1_OVERFLOW_VF3 = 0x000000ef,
+IH_PERF_SEL_RB1_OVERFLOW_VF4 = 0x000000f0,
+IH_PERF_SEL_RB1_OVERFLOW_VF5 = 0x000000f1,
+IH_PERF_SEL_RB1_OVERFLOW_VF6 = 0x000000f2,
+IH_PERF_SEL_RB1_OVERFLOW_VF7 = 0x000000f3,
+IH_PERF_SEL_RB1_OVERFLOW_VF8 = 0x000000f4,
+IH_PERF_SEL_RB1_OVERFLOW_VF9 = 0x000000f5,
+IH_PERF_SEL_RB1_OVERFLOW_VF10 = 0x000000f6,
+IH_PERF_SEL_RB1_OVERFLOW_VF11 = 0x000000f7,
+IH_PERF_SEL_RB1_OVERFLOW_VF12 = 0x000000f8,
+IH_PERF_SEL_RB1_OVERFLOW_VF13 = 0x000000f9,
+IH_PERF_SEL_RB1_OVERFLOW_VF14 = 0x000000fa,
+IH_PERF_SEL_RB1_OVERFLOW_VF15 = 0x000000fb,
+Reserved252 = 0x000000fc,
+Reserved253 = 0x000000fd,
+Reserved254 = 0x000000fe,
+Reserved255 = 0x000000ff,
+Reserved256 = 0x00000100,
+Reserved257 = 0x00000101,
+Reserved258 = 0x00000102,
+Reserved259 = 0x00000103,
+Reserved260 = 0x00000104,
+Reserved261 = 0x00000105,
+Reserved262 = 0x00000106,
+Reserved263 = 0x00000107,
+Reserved264 = 0x00000108,
+Reserved265 = 0x00000109,
+Reserved266 = 0x0000010a,
+Reserved267 = 0x0000010b,
+IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 0x0000010c,
+IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 0x0000010d,
+IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 0x0000010e,
+IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 0x0000010f,
+IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 0x00000110,
+IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 0x00000111,
+IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 0x00000112,
+IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 0x00000113,
+IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 0x00000114,
+IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 0x00000115,
+IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 0x00000116,
+IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 0x00000117,
+IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 0x00000118,
+IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 0x00000119,
+IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 0x0000011a,
+IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 0x0000011b,
+IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 0x0000011c,
+IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 0x0000011d,
+IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 0x0000011e,
+IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 0x0000011f,
+IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 0x00000120,
+IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 0x00000121,
+IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 0x00000122,
+IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 0x00000123,
+IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 0x00000124,
+IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 0x00000125,
+IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 0x00000126,
+IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 0x00000127,
+IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 0x00000128,
+IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 0x00000129,
+IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 0x0000012a,
+IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 0x0000012b,
+Reserved300 = 0x0000012c,
+Reserved301 = 0x0000012d,
+Reserved302 = 0x0000012e,
+Reserved303 = 0x0000012f,
+Reserved304 = 0x00000130,
+Reserved305 = 0x00000131,
+Reserved306 = 0x00000132,
+Reserved307 = 0x00000133,
+Reserved308 = 0x00000134,
+Reserved309 = 0x00000135,
+Reserved310 = 0x00000136,
+Reserved311 = 0x00000137,
+Reserved312 = 0x00000138,
+Reserved313 = 0x00000139,
+Reserved314 = 0x0000013a,
+Reserved315 = 0x0000013b,
+Reserved316 = 0x0000013c,
+Reserved317 = 0x0000013d,
+Reserved318 = 0x0000013e,
+Reserved319 = 0x0000013f,
+Reserved320 = 0x00000140,
+Reserved321 = 0x00000141,
+Reserved322 = 0x00000142,
+Reserved323 = 0x00000143,
+Reserved324 = 0x00000144,
+Reserved325 = 0x00000145,
+Reserved326 = 0x00000146,
+Reserved327 = 0x00000147,
+Reserved328 = 0x00000148,
+Reserved329 = 0x00000149,
+Reserved330 = 0x0000014a,
+Reserved331 = 0x0000014b,
+IH_PERF_SEL_RB2_FULL_VF0 = 0x0000014c,
+IH_PERF_SEL_RB2_FULL_VF1 = 0x0000014d,
+IH_PERF_SEL_RB2_FULL_VF2 = 0x0000014e,
+IH_PERF_SEL_RB2_FULL_VF3 = 0x0000014f,
+IH_PERF_SEL_RB2_FULL_VF4 = 0x00000150,
+IH_PERF_SEL_RB2_FULL_VF5 = 0x00000151,
+IH_PERF_SEL_RB2_FULL_VF6 = 0x00000152,
+IH_PERF_SEL_RB2_FULL_VF7 = 0x00000153,
+IH_PERF_SEL_RB2_FULL_VF8 = 0x00000154,
+IH_PERF_SEL_RB2_FULL_VF9 = 0x00000155,
+IH_PERF_SEL_RB2_FULL_VF10 = 0x00000156,
+IH_PERF_SEL_RB2_FULL_VF11 = 0x00000157,
+IH_PERF_SEL_RB2_FULL_VF12 = 0x00000158,
+IH_PERF_SEL_RB2_FULL_VF13 = 0x00000159,
+IH_PERF_SEL_RB2_FULL_VF14 = 0x0000015a,
+IH_PERF_SEL_RB2_FULL_VF15 = 0x0000015b,
+IH_PERF_SEL_RB2_OVERFLOW_VF0 = 0x0000015c,
+IH_PERF_SEL_RB2_OVERFLOW_VF1 = 0x0000015d,
+IH_PERF_SEL_RB2_OVERFLOW_VF2 = 0x0000015e,
+IH_PERF_SEL_RB2_OVERFLOW_VF3 = 0x0000015f,
+IH_PERF_SEL_RB2_OVERFLOW_VF4 = 0x00000160,
+IH_PERF_SEL_RB2_OVERFLOW_VF5 = 0x00000161,
+IH_PERF_SEL_RB2_OVERFLOW_VF6 = 0x00000162,
+IH_PERF_SEL_RB2_OVERFLOW_VF7 = 0x00000163,
+IH_PERF_SEL_RB2_OVERFLOW_VF8 = 0x00000164,
+IH_PERF_SEL_RB2_OVERFLOW_VF9 = 0x00000165,
+IH_PERF_SEL_RB2_OVERFLOW_VF10 = 0x00000166,
+IH_PERF_SEL_RB2_OVERFLOW_VF11 = 0x00000167,
+IH_PERF_SEL_RB2_OVERFLOW_VF12 = 0x00000168,
+IH_PERF_SEL_RB2_OVERFLOW_VF13 = 0x00000169,
+IH_PERF_SEL_RB2_OVERFLOW_VF14 = 0x0000016a,
+IH_PERF_SEL_RB2_OVERFLOW_VF15 = 0x0000016b,
+Reserved364 = 0x0000016c,
+Reserved365 = 0x0000016d,
+Reserved366 = 0x0000016e,
+Reserved367 = 0x0000016f,
+Reserved368 = 0x00000170,
+Reserved369 = 0x00000171,
+Reserved370 = 0x00000172,
+Reserved371 = 0x00000173,
+Reserved372 = 0x00000174,
+Reserved373 = 0x00000175,
+Reserved374 = 0x00000176,
+Reserved375 = 0x00000177,
+Reserved376 = 0x00000178,
+Reserved377 = 0x00000179,
+Reserved378 = 0x0000017a,
+Reserved379 = 0x0000017b,
+IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 0x0000017c,
+IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 0x0000017d,
+IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 0x0000017e,
+IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 0x0000017f,
+IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 0x00000180,
+IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 0x00000181,
+IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 0x00000182,
+IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 0x00000183,
+IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 0x00000184,
+IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 0x00000185,
+IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 0x00000186,
+IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 0x00000187,
+IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 0x00000188,
+IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 0x00000189,
+IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 0x0000018a,
+IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 0x0000018b,
+IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 0x0000018c,
+IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 0x0000018d,
+IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 0x0000018e,
+IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 0x0000018f,
+IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 0x00000190,
+IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 0x00000191,
+IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 0x00000192,
+IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 0x00000193,
+IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 0x00000194,
+IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 0x00000195,
+IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 0x00000196,
+IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 0x00000197,
+IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 0x00000198,
+IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 0x00000199,
+IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 0x0000019a,
+IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 0x0000019b,
+Reserved412 = 0x0000019c,
+Reserved413 = 0x0000019d,
+Reserved414 = 0x0000019e,
+Reserved415 = 0x0000019f,
+Reserved416 = 0x000001a0,
+Reserved417 = 0x000001a1,
+Reserved418 = 0x000001a2,
+Reserved419 = 0x000001a3,
+Reserved420 = 0x000001a4,
+Reserved421 = 0x000001a5,
+Reserved422 = 0x000001a6,
+Reserved423 = 0x000001a7,
+Reserved424 = 0x000001a8,
+Reserved425 = 0x000001a9,
+Reserved426 = 0x000001aa,
+Reserved427 = 0x000001ab,
+Reserved428 = 0x000001ac,
+Reserved429 = 0x000001ad,
+Reserved430 = 0x000001ae,
+Reserved431 = 0x000001af,
+Reserved432 = 0x000001b0,
+Reserved433 = 0x000001b1,
+Reserved434 = 0x000001b2,
+Reserved435 = 0x000001b3,
+Reserved436 = 0x000001b4,
+Reserved437 = 0x000001b5,
+Reserved438 = 0x000001b6,
+Reserved439 = 0x000001b7,
+Reserved440 = 0x000001b8,
+Reserved441 = 0x000001b9,
+Reserved442 = 0x000001ba,
+Reserved443 = 0x000001bb,
+Reserved444 = 0x000001bc,
+Reserved445 = 0x000001bd,
+Reserved446 = 0x000001be,
+Reserved447 = 0x000001bf,
+Reserved448 = 0x000001c0,
+Reserved449 = 0x000001c1,
+Reserved450 = 0x000001c2,
+Reserved451 = 0x000001c3,
+Reserved452 = 0x000001c4,
+Reserved453 = 0x000001c5,
+Reserved454 = 0x000001c6,
+Reserved455 = 0x000001c7,
+Reserved456 = 0x000001c8,
+Reserved457 = 0x000001c9,
+Reserved458 = 0x000001ca,
+Reserved459 = 0x000001cb,
+Reserved460 = 0x000001cc,
+Reserved461 = 0x000001cd,
+Reserved462 = 0x000001ce,
+Reserved463 = 0x000001cf,
+Reserved464 = 0x000001d0,
+Reserved465 = 0x000001d1,
+Reserved466 = 0x000001d2,
+Reserved467 = 0x000001d3,
+Reserved468 = 0x000001d4,
+Reserved469 = 0x000001d5,
+Reserved470 = 0x000001d6,
+Reserved471 = 0x000001d7,
+Reserved472 = 0x000001d8,
+Reserved473 = 0x000001d9,
+Reserved474 = 0x000001da,
+Reserved475 = 0x000001db,
+Reserved476 = 0x000001dc,
+Reserved477 = 0x000001dd,
+Reserved478 = 0x000001de,
+Reserved479 = 0x000001df,
+Reserved480 = 0x000001e0,
+Reserved481 = 0x000001e1,
+Reserved482 = 0x000001e2,
+Reserved483 = 0x000001e3,
+Reserved484 = 0x000001e4,
+Reserved485 = 0x000001e5,
+Reserved486 = 0x000001e6,
+Reserved487 = 0x000001e7,
+Reserved488 = 0x000001e8,
+Reserved489 = 0x000001e9,
+Reserved490 = 0x000001ea,
+Reserved491 = 0x000001eb,
+Reserved492 = 0x000001ec,
+Reserved493 = 0x000001ed,
+Reserved494 = 0x000001ee,
+Reserved495 = 0x000001ef,
+Reserved496 = 0x000001f0,
+Reserved497 = 0x000001f1,
+Reserved498 = 0x000001f2,
+Reserved499 = 0x000001f3,
+Reserved500 = 0x000001f4,
+Reserved501 = 0x000001f5,
+Reserved502 = 0x000001f6,
+Reserved503 = 0x000001f7,
+Reserved504 = 0x000001f8,
+Reserved505 = 0x000001f9,
+Reserved506 = 0x000001fa,
+Reserved507 = 0x000001fb,
+Reserved508 = 0x000001fc,
+Reserved509 = 0x000001fd,
+Reserved510 = 0x000001fe,
+Reserved511 = 0x000001ff,
+} IH_PERF_SEL;
+
+/*******************************************************
+ * SEM Enums
+ *******************************************************/
+
+/*
+ * SEM_PERF_SEL enum
+ */
+
+typedef enum SEM_PERF_SEL {
+SEM_PERF_SEL_CYCLE = 0x00000000,
+SEM_PERF_SEL_IDLE = 0x00000001,
+SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 0x00000002,
+SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 0x00000003,
+SEM_PERF_SEL_UVD_REQ_SIGNAL = 0x00000004,
+SEM_PERF_SEL_VCE0_REQ_SIGNAL = 0x00000005,
+SEM_PERF_SEL_ACP_REQ_SIGNAL = 0x00000006,
+SEM_PERF_SEL_ISP_REQ_SIGNAL = 0x00000007,
+SEM_PERF_SEL_VCE1_REQ_SIGNAL = 0x00000008,
+SEM_PERF_SEL_VP8_REQ_SIGNAL = 0x00000009,
+SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 0x0000000a,
+SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 0x0000000b,
+SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 0x0000000c,
+SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 0x0000000d,
+SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 0x0000000e,
+SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 0x0000000f,
+SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 0x00000010,
+SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 0x00000011,
+SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 0x00000012,
+SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 0x00000013,
+SEM_PERF_SEL_SDMA0_REQ_WAIT = 0x00000014,
+SEM_PERF_SEL_SDMA1_REQ_WAIT = 0x00000015,
+SEM_PERF_SEL_UVD_REQ_WAIT = 0x00000016,
+SEM_PERF_SEL_VCE0_REQ_WAIT = 0x00000017,
+SEM_PERF_SEL_ACP_REQ_WAIT = 0x00000018,
+SEM_PERF_SEL_ISP_REQ_WAIT = 0x00000019,
+SEM_PERF_SEL_VCE1_REQ_WAIT = 0x0000001a,
+SEM_PERF_SEL_VP8_REQ_WAIT = 0x0000001b,
+SEM_PERF_SEL_CPG_E0_REQ_WAIT = 0x0000001c,
+SEM_PERF_SEL_CPG_E1_REQ_WAIT = 0x0000001d,
+SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 0x0000001e,
+SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 0x0000001f,
+SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 0x00000020,
+SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 0x00000021,
+SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 0x00000022,
+SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 0x00000023,
+SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 0x00000024,
+SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 0x00000025,
+SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 0x00000026,
+SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 0x00000027,
+SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 0x00000028,
+SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 0x00000029,
+SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 0x0000002a,
+SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 0x0000002b,
+SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 0x0000002c,
+SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 0x0000002d,
+SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 0x0000002e,
+SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 0x0000002f,
+SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 0x00000030,
+SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 0x00000031,
+SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 0x00000032,
+SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 0x00000033,
+SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 0x00000034,
+SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 0x00000035,
+SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 0x00000036,
+SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 0x00000037,
+SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 0x00000038,
+SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 0x00000039,
+SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 0x0000003a,
+SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 0x0000003b,
+SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 0x0000003c,
+SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 0x0000003d,
+SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 0x0000003e,
+SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 0x0000003f,
+SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 0x00000040,
+SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 0x00000041,
+SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 0x00000042,
+SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 0x00000043,
+SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 0x00000044,
+SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 0x00000045,
+SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 0x00000046,
+SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 0x00000047,
+SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 0x00000048,
+SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 0x00000049,
+SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 0x0000004a,
+SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 0x0000004b,
+SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 0x0000004c,
+SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 0x0000004d,
+SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 0x0000004e,
+SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 0x0000004f,
+SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 0x00000050,
+SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 0x00000051,
+SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 0x00000052,
+SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 0x00000053,
+SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 0x00000054,
+SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 0x00000055,
+SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 0x00000056,
+SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 0x00000057,
+SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 0x00000058,
+SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 0x00000059,
+SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 0x0000005a,
+SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 0x0000005b,
+SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 0x0000005c,
+SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 0x0000005d,
+SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 0x0000005e,
+SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 0x0000005f,
+SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 0x00000060,
+SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 0x00000061,
+SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 0x00000062,
+SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 0x00000063,
+SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 0x00000064,
+SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 0x00000065,
+SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 0x00000066,
+SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 0x00000067,
+SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 0x00000068,
+SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 0x00000069,
+SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 0x0000006a,
+SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 0x0000006b,
+SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 0x0000006c,
+SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 0x0000006d,
+SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 0x0000006e,
+SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 0x0000006f,
+SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 0x00000070,
+SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 0x00000071,
+SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 0x00000072,
+SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 0x00000073,
+SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 0x00000074,
+SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 0x00000075,
+SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 0x00000076,
+SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 0x00000077,
+SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 0x00000078,
+SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 0x00000079,
+SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 0x0000007a,
+SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 0x0000007b,
+SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 0x0000007c,
+SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 0x0000007d,
+SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 0x0000007e,
+SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 0x0000007f,
+SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 0x00000080,
+SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 0x00000081,
+SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 0x00000082,
+SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 0x00000083,
+SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 0x00000084,
+SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 0x00000085,
+SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 0x00000086,
+SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 0x00000087,
+SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 0x00000088,
+SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 0x00000089,
+SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 0x0000008a,
+SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 0x0000008b,
+SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 0x0000008c,
+SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 0x0000008d,
+SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 0x0000008e,
+SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 0x0000008f,
+SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 0x00000090,
+SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 0x00000091,
+SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 0x00000092,
+SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 0x00000093,
+SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 0x00000094,
+SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 0x00000095,
+SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 0x00000096,
+SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 0x00000097,
+SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 0x00000098,
+SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 0x00000099,
+SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 0x0000009a,
+SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 0x0000009b,
+SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 0x0000009c,
+SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 0x0000009d,
+SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 0x0000009e,
+SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 0x0000009f,
+SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 0x000000a0,
+SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 0x000000a1,
+SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 0x000000a2,
+SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 0x000000a3,
+SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 0x000000a4,
+SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 0x000000a5,
+SEM_PERF_SEL_MC_RD_REQ = 0x000000a6,
+SEM_PERF_SEL_MC_RD_RET = 0x000000a7,
+SEM_PERF_SEL_MC_WR_REQ = 0x000000a8,
+SEM_PERF_SEL_MC_WR_RET = 0x000000a9,
+SEM_PERF_SEL_ATC_REQ = 0x000000aa,
+SEM_PERF_SEL_ATC_RET = 0x000000ab,
+SEM_PERF_SEL_ATC_XNACK = 0x000000ac,
+SEM_PERF_SEL_ATC_INVALIDATION = 0x000000ad,
+} SEM_PERF_SEL;
+
+/*******************************************************
+ * SDMA Enums
+ *******************************************************/
+
+/*
+ * SDMA_PERF_SEL enum
+ */
+
+typedef enum SDMA_PERF_SEL {
+SDMA_PERF_SEL_CYCLE = 0x00000000,
+SDMA_PERF_SEL_IDLE = 0x00000001,
+SDMA_PERF_SEL_REG_IDLE = 0x00000002,
+SDMA_PERF_SEL_RB_EMPTY = 0x00000003,
+SDMA_PERF_SEL_RB_FULL = 0x00000004,
+SDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005,
+SDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006,
+SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007,
+SDMA_PERF_SEL_RB_RPTR_WB = 0x00000008,
+SDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009,
+SDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a,
+SDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b,
+SDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c,
+SDMA_PERF_SEL_EX_IDLE = 0x0000000d,
+SDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e,
+SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f,
+SDMA_PERF_SEL_MC_WR_IDLE = 0x00000010,
+SDMA_PERF_SEL_MC_WR_COUNT = 0x00000011,
+SDMA_PERF_SEL_MC_RD_IDLE = 0x00000012,
+SDMA_PERF_SEL_MC_RD_COUNT = 0x00000013,
+SDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014,
+SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015,
+SDMA_PERF_SEL_SEM_IDLE = 0x00000018,
+SDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019,
+SDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a,
+SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b,
+SDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c,
+SDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d,
+SDMA_PERF_SEL_INT_IDLE = 0x0000001e,
+SDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f,
+SDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020,
+SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021,
+SDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022,
+SDMA_PERF_SEL_NUM_PACKET = 0x00000023,
+SDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025,
+SDMA_PERF_SEL_CE_WR_IDLE = 0x00000026,
+SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027,
+SDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028,
+SDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029,
+SDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a,
+SDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b,
+SDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e,
+SDMA_PERF_SEL_CE_INFO_FULL = 0x00000031,
+SDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032,
+SDMA_PERF_SEL_CE_RD_STALL = 0x00000033,
+SDMA_PERF_SEL_CE_WR_STALL = 0x00000034,
+SDMA_PERF_SEL_GFX_SELECT = 0x00000035,
+SDMA_PERF_SEL_RLC0_SELECT = 0x00000036,
+SDMA_PERF_SEL_RLC1_SELECT = 0x00000037,
+SDMA_PERF_SEL_PAGE_SELECT = 0x00000038,
+SDMA_PERF_SEL_CTX_CHANGE = 0x00000039,
+SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x0000003a,
+SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x0000003b,
+SDMA_PERF_SEL_DOORBELL = 0x0000003c,
+SDMA_PERF_SEL_RD_BA_RTR = 0x0000003d,
+SDMA_PERF_SEL_WR_BA_RTR = 0x0000003e,
+SDMA_PERF_SEL_F32_L1_WR_VLD = 0x0000003f,
+SDMA_PERF_SEL_CE_L1_WR_VLD = 0x00000040,
+SDMA_PERF_SEL_CE_L1_STALL = 0x00000041,
+SDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 0x00000042,
+SDMA_PERF_SEL_SDMA_INVACK_FLUSH = 0x00000043,
+SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 0x00000044,
+SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 0x00000045,
+SDMA_PERF_SEL_ATCL2_RET_XNACK = 0x00000046,
+SDMA_PERF_SEL_ATCL2_RET_ACK = 0x00000047,
+SDMA_PERF_SEL_ATCL2_FREE = 0x00000048,
+SDMA_PERF_SEL_SDMA_ATCL2_SEND = 0x00000049,
+SDMA_PERF_SEL_DMA_L1_WR_SEND = 0x0000004a,
+SDMA_PERF_SEL_DMA_L1_RD_SEND = 0x0000004b,
+SDMA_PERF_SEL_DMA_MC_WR_SEND = 0x0000004c,
+SDMA_PERF_SEL_DMA_MC_RD_SEND = 0x0000004d,
+SDMA_PERF_SEL_L1_WR_FIFO_IDLE = 0x0000004e,
+SDMA_PERF_SEL_L1_RD_FIFO_IDLE = 0x0000004f,
+SDMA_PERF_SEL_L1_WRL2_IDLE = 0x00000050,
+SDMA_PERF_SEL_L1_RDL2_IDLE = 0x00000051,
+SDMA_PERF_SEL_L1_WRMC_IDLE = 0x00000052,
+SDMA_PERF_SEL_L1_RDMC_IDLE = 0x00000053,
+SDMA_PERF_SEL_L1_WR_INV_IDLE = 0x00000054,
+SDMA_PERF_SEL_L1_RD_INV_IDLE = 0x00000055,
+SDMA_PERF_SEL_L1_WR_INV_EN = 0x00000056,
+SDMA_PERF_SEL_L1_RD_INV_EN = 0x00000057,
+SDMA_PERF_SEL_L1_WR_WAIT_INVADR = 0x00000058,
+SDMA_PERF_SEL_L1_RD_WAIT_INVADR = 0x00000059,
+SDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 0x0000005a,
+SDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 0x0000005b,
+SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 0x0000005c,
+SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 0x0000005d,
+SDMA_PERF_SEL_L1_INV_MIDDLE = 0x0000005e,
+SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER = 0x000000fe,
+SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER = 0x000000ff,
+} SDMA_PERF_SEL;
+
+/*******************************************************
+ * SMUIO Enums
+ *******************************************************/
+
+/*
+ * ROM_SIGNATURE value
+ */
+
+#define ROM_SIGNATURE 0x0000aa55
+
+/*******************************************************
+ * XDMA_CMN Enums
+ *******************************************************/
+
+/*
+ * ENUM_XDMA_LOCAL_SW_MODE enum
+ */
+
+typedef enum ENUM_XDMA_LOCAL_SW_MODE {
+XDMA_LOCAL_SW_MODE_SW_256B_D = 0x00000002,
+XDMA_LOCAL_SW_MODE_SW_64KB_D = 0x0000000a,
+XDMA_LOCAL_SW_MODE_SW_64KB_D_X = 0x0000001a,
+} ENUM_XDMA_LOCAL_SW_MODE;
+
+/*******************************************************
+ * XDMA_SLV Enums
+ *******************************************************/
+
+/*
+ * ENUM_XDMA_SLV_ALPHA_POSITION enum
+ */
+
+typedef enum ENUM_XDMA_SLV_ALPHA_POSITION {
+XDMA_SLV_ALPHA_POSITION_7_0 = 0x00000000,
+XDMA_SLV_ALPHA_POSITION_15_8 = 0x00000001,
+XDMA_SLV_ALPHA_POSITION_23_16 = 0x00000002,
+XDMA_SLV_ALPHA_POSITION_31_24 = 0x00000003,
+} ENUM_XDMA_SLV_ALPHA_POSITION;
+
+/*******************************************************
+ * XDMA_MSTR Enums
+ *******************************************************/
+
+/*
+ * ENUM_XDMA_MSTR_ALPHA_POSITION enum
+ */
+
+typedef enum ENUM_XDMA_MSTR_ALPHA_POSITION {
+XDMA_MSTR_ALPHA_POSITION_7_0 = 0x00000000,
+XDMA_MSTR_ALPHA_POSITION_15_8 = 0x00000001,
+XDMA_MSTR_ALPHA_POSITION_23_16 = 0x00000002,
+XDMA_MSTR_ALPHA_POSITION_31_24 = 0x00000003,
+} ENUM_XDMA_MSTR_ALPHA_POSITION;
+
+/*
+ * ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL enum
+ */
+
+typedef enum ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL {
+XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE0 = 0x00000000,
+XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE1 = 0x00000001,
+XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE2 = 0x00000002,
+XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE3 = 0x00000003,
+XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE4 = 0x00000004,
+XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE5 = 0x00000005,
+} ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL;
+
+
+#endif /*_vega10_ENUM_HEADER*/
+
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.